diff --git a/.gitignore b/.gitignore index 2f02054dcb59420ab6943105d40932901aac0436..59b9974e8a4d89600d985fb918c773137f352885 100644 --- a/.gitignore +++ b/.gitignore @@ -34,3 +34,4 @@ ncscope.* #ctag files tags +.vscode/ \ No newline at end of file diff --git a/.travis.yml b/.travis.yml index f7ecc85ca749d67c94ff14503c4a35a325914747..c8e8951f071f766c2158a4dade15ebdda201b868 100644 --- a/.travis.yml +++ b/.travis.yml @@ -69,7 +69,7 @@ env: # - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm' # - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm' # - RTT_BSP='pic32ethernet' # no scons - - RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm' +# - RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm' # - RTT_BSP='simulator' # x86 diff --git a/bsp/allwinner_tina/.config b/bsp/allwinner_tina/.config index 2c39e4435ecf06d9520f2f4868c03297a89e1d28..06570d57dd64716d573d03f0c7004c41a3d00d78 100644 --- a/bsp/allwinner_tina/.config +++ b/bsp/allwinner_tina/.config @@ -7,20 +7,33 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=0 -CONFIG_RT_DEBUG_THREAD=0 CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set # # Inter-Thread communication @@ -47,11 +60,15 @@ CONFIG_RT_USING_HEAP=y # Kernel Device Object # CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_ARM9=y @@ -60,6 +77,8 @@ CONFIG_ARCH_ARM_ARM9=y # CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -75,6 +94,7 @@ CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_CMD_SIZE=80 @@ -82,6 +102,7 @@ CONFIG_FINSH_CMD_SIZE=80 CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_USING_MSH_DEFAULT=y # CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system @@ -91,6 +112,7 @@ CONFIG_DFS_USING_WORKDIR=y CONFIG_DFS_FILESYSTEMS_MAX=2 CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 CONFIG_DFS_FD_MAX=4 +# CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_RT_USING_DFS_ELMFAT=y # @@ -109,30 +131,59 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 # CONFIG_RT_DFS_ELM_USE_ERASE is not set CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_NET is not set # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set -# CONFIG_RT_USING_DFS_NFS is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -149,26 +200,33 @@ CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set # -# Network stack +# Network # # -# light weight TCP/IP stack +# Socket abstraction layer # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_SAL is not set # -# Modbus master and slave stack +# Network interface device # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_NETDEV is not set # -# RT-Thread UI Engine +# light weight TCP/IP stack # -# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set # # VBUS(Virtual Software BUS) @@ -178,34 +236,35 @@ CONFIG_RT_USING_POSIX=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages # -# -# system packages -# -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERSIMMON is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set - # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set # # Wi-Fi @@ -220,8 +279,49 @@ CONFIG_RT_USING_POSIX=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -229,10 +329,13 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages # +# CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set @@ -240,28 +343,197 @@ CONFIG_RT_USING_POSIX=y # multimedia packages # # CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_IPERF is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages # +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # -# example package: hello +# samples: kernel and components samples # +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +CONFIG_SOC_TINA=y CONFIG_TINA_USING_UART0=y # CONFIG_TINA_USING_UART1 is not set CONFIG_TINA_USING_UART2=y -CONFIG_RT_USING_CPU_FFS=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_TINA_USING_SDIO0=y +CONFIG_TINA_USING_SPI0=y +CONFIG_TINA_USING_SPI1=y +CONFIG_TINA_USING_SPI_FLASH=y diff --git a/bsp/allwinner_tina/Kconfig b/bsp/allwinner_tina/Kconfig index 8f9a367dc2f183e30674cbd498abbc19ad2e8413..1f976aa50e287fbd8ac0361716ef9d9e5acc11f6 100644 --- a/bsp/allwinner_tina/Kconfig +++ b/bsp/allwinner_tina/Kconfig @@ -24,6 +24,7 @@ source "$PKGS_DIR/Kconfig" config SOC_TINA bool select ARCH_ARM_ARM9 + select RT_USING_CACHE select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y diff --git a/bsp/allwinner_tina/rtconfig.h b/bsp/allwinner_tina/rtconfig.h index b9221509b4ef9e6f6690fdd602f27abef6197220..8aff170e0731ef79d1b8893f378172371c7aa279 100644 --- a/bsp/allwinner_tina/rtconfig.h +++ b/bsp/allwinner_tina/rtconfig.h @@ -8,19 +8,16 @@ #define RT_NAME_MAX 8 #define RT_ALIGN_SIZE 4 -/* RT_THREAD_PRIORITY_8 is not set */ #define RT_THREAD_PRIORITY_32 -/* RT_THREAD_PRIORITY_256 is not set */ #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 -#define RT_DEBUG -#define RT_DEBUG_COLOR #define RT_USING_OVERFLOW_CHECK -#define RT_DEBUG_INIT 0 -#define RT_DEBUG_THREAD 0 #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 -/* RT_USING_TIMER_SOFT is not set */ +#define RT_DEBUG +#define RT_DEBUG_COLOR /* Inter-Thread communication */ @@ -29,26 +26,21 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ #define RT_USING_MEMPOOL -/* RT_USING_MEMHEAP is not set */ -/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ -/* RT_USING_MEMTRACE is not set */ #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE -/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -/* RT_USING_MODULE is not set */ +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define ARCH_ARM #define ARCH_ARM_ARM9 @@ -56,10 +48,11 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ @@ -72,10 +65,9 @@ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT -/* FINSH_USING_MSH_ONLY is not set */ +#define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -91,147 +83,112 @@ #define RT_DFS_ELM_CODE_PAGE 437 #define RT_DFS_ELM_WORD_ACCESS #define RT_DFS_ELM_USE_LFN_0 -/* RT_DFS_ELM_USE_LFN_1 is not set */ -/* RT_DFS_ELM_USE_LFN_2 is not set */ -/* RT_DFS_ELM_USE_LFN_3 is not set */ #define RT_DFS_ELM_USE_LFN 0 #define RT_DFS_ELM_MAX_LFN 255 #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 -/* RT_DFS_ELM_USE_ERASE is not set */ #define RT_DFS_ELM_REENTRANT #define RT_USING_DFS_DEVFS -/* RT_USING_DFS_NET is not set */ -/* RT_USING_DFS_ROMFS is not set */ -/* RT_USING_DFS_RAMFS is not set */ -/* RT_USING_DFS_UFFS is not set */ -/* RT_USING_DFS_JFFS2 is not set */ -/* RT_USING_DFS_NFS is not set */ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_CPUTIME is not set */ -/* RT_USING_I2C is not set */ +#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_RTC is not set */ -/* RT_USING_SDIO is not set */ -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_WIFI is not set */ +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_SPI +#define RT_USING_SFUD +#define RT_SFUD_USING_SFDP +#define RT_SFUD_USING_FLASH_INFO_TABLE +#define RT_SFUD_SPI_MAX_HZ 50000000 /* Using USB */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ #define RT_USING_LIBC -/* RT_USING_PTHREADS is not set */ #define RT_USING_POSIX -/* RT_USING_POSIX_MMAP is not set */ -/* RT_USING_POSIX_TERMIOS is not set */ -/* RT_USING_POSIX_AIO is not set */ -/* Network stack */ +/* Network */ -/* light weight TCP/IP stack */ +/* Socket abstraction layer */ -/* RT_USING_LWIP is not set */ -/* Modbus master and slave stack */ +/* Network interface device */ -/* RT_USING_MODBUS is not set */ -/* RT-Thread UI Engine */ +/* light weight TCP/IP stack */ + + +/* AT commands */ -/* PKG_USING_GUIENGINE is not set */ /* VBUS(Virtual Software BUS) */ -/* RT_USING_VBUS is not set */ /* Utilities */ -/* RT_USING_LOGTRACE is not set */ -/* RT_USING_RYM is not set */ /* RT-Thread online packages */ -/* system packages */ - -/* PKG_USING_LWEXT4 is not set */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_PERSIMMON is not set */ -/* PKG_USING_SQLITE is not set */ -/* PKG_USING_RTI is not set */ - /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_LJSON is not set */ -/* PKG_USING_EZXML is not set */ -/* PKG_USING_NANOPB is not set */ -/* PKG_USING_GAGENT_CLOUD is not set */ /* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ -/* PKG_USING_WLAN_WICED is not set */ -/* PKG_USING_COAP is not set */ -/* PKG_USING_NOPOLL is not set */ + +/* IoT Cloud */ + /* security packages */ -/* PKG_USING_MBEDTLS is not set */ -/* PKG_USING_libsodium is not set */ -/* PKG_USING_TINYCRYPT is not set */ /* language packages */ -/* PKG_USING_JERRYSCRIPT is not set */ -/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ -/* PKG_USING_OPENMV is not set */ /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYLOGGER is not set */ -/* PKG_USING_SYSTEMVIEW is not set */ -/* PKG_USING_IPERF is not set */ + +/* system packages */ + + +/* peripheral libraries and drivers */ + /* miscellaneous packages */ -/* PKG_USING_FASTLZ is not set */ -/* PKG_USING_MINILZO is not set */ -/* example package: hello */ +/* samples: kernel and components samples */ + + +/* Privated Packages of RealThread */ -/* PKG_USING_HELLO is not set */ -/* PKG_USING_MULTIBUTTON is not set */ + +/* Network Utilities */ + +#define SOC_TINA #define TINA_USING_UART0 -/* TINA_USING_UART1 is not set */ #define TINA_USING_UART2 -#define RT_USING_CPU_FFS -#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define TINA_USING_SDIO0 +#define TINA_USING_SPI0 +#define TINA_USING_SPI1 +#define TINA_USING_SPI_FLASH #endif diff --git a/bsp/asm9260t/.config b/bsp/asm9260t/.config index 04964a837555a10e7d0731ab78cff8400f31e19a..28d2fb9d30f1aa9e1051dd946be9e4e5ab95f31f 100644 --- a/bsp/asm9260t/.config +++ b/bsp/asm9260t/.config @@ -7,20 +7,35 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=0 -# CONFIG_RT_DEBUG_THREAD is not set -CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set # # Inter-Thread communication @@ -37,24 +52,35 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_USING_HEAP=y +# CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_SMALL_MEM is not set CONFIG_RT_USING_SLAB=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_HEAP=y # # Kernel Device Object # CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart3" -# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_ARM9=y # # RT-Thread Components # CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -65,9 +91,12 @@ CONFIG_RT_USING_USER_MAIN=y # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_CMD_SIZE=80 @@ -83,18 +112,38 @@ CONFIG_FINSH_CMD_SIZE=80 # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# # CONFIG_RT_USING_USB_HOST is not set # CONFIG_RT_USING_USB_DEVICE is not set @@ -103,11 +152,21 @@ CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_POSIX is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# # -# Network stack +# Socket abstraction layer # +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set # # light weight TCP/IP stack @@ -115,68 +174,312 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_LWIP is not set # -# Modbus master and slave stack +# AT commands # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_AT is not set # -# RT-Thread UI Engine +# VBUS(Virtual Software BUS) # -# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_RT_USING_VBUS is not set # -# RT-Thread online packages +# Utilities # +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # -# system packages +# RT-Thread online packages # -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_SQLITE is not set # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# # # Marvell WiFi # -# CONFIG_PKG_USING_MARVELLWIFI is not set +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages # # CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages # +# CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set # # multimedia packages # +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages # +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set # -# BSP_SPECIAL CONFIG +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + # +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +CONFIG_SOC_AT91SAM926=y # CONFIG_RT_USING_UART0 is not set CONFIG_RT_USING_UART3=y # CONFIG_RT_USING_UART4 is not set diff --git a/bsp/asm9260t/Kconfig b/bsp/asm9260t/Kconfig index a51e8064973db6a51aa3dc8d298bf68b0a9ba6b1..49c0baa80ea9646412b6ede511ccadc6d84e2a4d 100644 --- a/bsp/asm9260t/Kconfig +++ b/bsp/asm9260t/Kconfig @@ -19,8 +19,11 @@ source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" config SOC_AT91SAM926 + bool + select ARCH_ARM_ARM9 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y config RT_USING_UART0 @@ -40,3 +43,4 @@ config RT_USING_LED default y help led blink demo + diff --git a/bsp/asm9260t/rtconfig.h b/bsp/asm9260t/rtconfig.h index 8ca5daa56551c4b2fe9b22dc6d97fce031eec790..48cd0c032d61ab26e0fc1f21cb22f89ff86f3c63 100644 --- a/bsp/asm9260t/rtconfig.h +++ b/bsp/asm9260t/rtconfig.h @@ -8,19 +8,19 @@ #define RT_NAME_MAX 8 #define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 -#define RT_DEBUG -#define RT_DEBUG_COLOR #define RT_USING_OVERFLOW_CHECK -#define RT_DEBUG_INIT 0 -/* RT_DEBUG_THREAD is not set */ -#define RT_USING_INTERRUPT_INFO #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG +#define RT_DEBUG_COLOR /* Inter-Thread communication */ @@ -29,131 +29,133 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ #define RT_USING_MEMPOOL #define RT_USING_MEMHEAP -#define RT_USING_HEAP -/* RT_USING_SMALL_MEM is not set */ #define RT_USING_SLAB +#define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE +#define RT_USING_INTERRUPT_INFO #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart3" -/* RT_USING_MODULE is not set */ +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define ARCH_ARM +#define ARCH_ARM_ARM9 /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ #define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" #define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ -/* FINSH_USING_MSH is not set */ /* Device virtual file system */ -/* RT_USING_DFS is not set */ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_I2C is not set */ -/* RT_USING_PIN is not set */ -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_RTC is not set */ -/* RT_USING_SDIO is not set */ -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ +#define RT_SERIAL_RB_BUFSZ 64 + +/* Using USB */ + /* POSIX layer and C standard library */ #define RT_USING_LIBC -/* RT_USING_PTHREADS is not set */ -/* RT_USING_POSIX is not set */ -/* Network stack */ +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + /* light weight TCP/IP stack */ -/* RT_USING_LWIP is not set */ -/* Modbus master and slave stack */ +/* AT commands */ -/* RT_USING_MODBUS is not set */ -/* RT-Thread UI Engine */ +/* VBUS(Virtual Software BUS) */ -/* PKG_USING_GUIENGINE is not set */ -/* RT-Thread online packages */ +/* Utilities */ -/* system packages */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_SQLITE is not set */ +/* RT-Thread online packages */ /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_EZXML is not set */ + +/* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_MARVELLWIFI is not set */ + +/* Wiced WiFi */ + + +/* IoT Cloud */ + /* security packages */ -/* PKG_USING_MBEDTLS is not set */ /* language packages */ -/* PKG_USING_JERRYSCRIPT is not set */ /* multimedia packages */ + /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYLOGGER is not set */ + +/* system packages */ + + +/* peripheral libraries and drivers */ + /* miscellaneous packages */ -/* PKG_USING_HELLO is not set */ -/* BSP_SPECIAL CONFIG */ +/* samples: kernel and components samples */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ -/* RT_USING_UART0 is not set */ +#define SOC_AT91SAM926 #define RT_USING_UART3 -/* RT_USING_UART4 is not set */ #define RT_USING_LED #endif diff --git a/bsp/at91sam9260/.config b/bsp/at91sam9260/.config index d0998436fecaf7a799ed3f188dbccae38c225967..a4dceff449219eba6b814359c74c2bb534aec088 100644 --- a/bsp/at91sam9260/.config +++ b/bsp/at91sam9260/.config @@ -7,6 +7,9 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y @@ -15,6 +18,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set @@ -61,6 +65,12 @@ CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="dbgu" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_ARM9=y # # RT-Thread Components @@ -106,31 +116,43 @@ CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_ELMFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set -# CONFIG_RT_USING_DFS_NFS is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set # # Using USB @@ -143,6 +165,11 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set # @@ -155,14 +182,14 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -177,8 +204,10 @@ CONFIG_RT_USING_LIBC=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -187,12 +216,20 @@ CONFIG_RT_USING_LIBC=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -210,10 +247,15 @@ CONFIG_RT_USING_LIBC=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set # # IoT Cloud @@ -222,6 +264,32 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -229,6 +297,8 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -242,6 +312,10 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -250,30 +324,102 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages # # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -284,13 +430,15 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -299,11 +447,57 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +CONFIG_SOC_AT91SAM926=y CONFIG_RT_USING_DBGU=y # CONFIG_RT_USING_UART0 is not set # CONFIG_RT_USING_UART1 is not set diff --git a/bsp/at91sam9260/Kconfig b/bsp/at91sam9260/Kconfig index 23b4eea1d415d6b6d173171b61974822bfb5e21e..6f021e4c0f59d59a3c2fa4e62a5c0bc407a26557 100644 --- a/bsp/at91sam9260/Kconfig +++ b/bsp/at91sam9260/Kconfig @@ -20,8 +20,10 @@ source "$PKGS_DIR/Kconfig" config SOC_AT91SAM926 bool + select ARCH_ARM_ARM9 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y config RT_USING_DBGU diff --git a/bsp/at91sam9260/rtconfig.h b/bsp/at91sam9260/rtconfig.h index 46ccc8f1675ae851ca6767c653e2705c478ecfbd..1c33c6a1c1911801b4d5b65b11f1ce865ef8547e 100755 --- a/bsp/at91sam9260/rtconfig.h +++ b/bsp/at91sam9260/rtconfig.h @@ -13,6 +13,7 @@ #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_DEBUG @@ -39,6 +40,10 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "dbgu" +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define ARCH_ARM +#define ARCH_ARM_ARM9 /* RT-Thread Components */ @@ -49,9 +54,6 @@ /* C++ features */ -#define RT_USING_DEVICE_IPC -#define RT_USING_SERIAL -#define RT_SERIAL_USING_DMA /* Command shell */ @@ -82,6 +84,8 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN /* Using USB */ @@ -90,16 +94,17 @@ /* POSIX layer and C standard library */ #define RT_USING_LIBC +#define RT_USING_POSIX /* Network */ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -148,13 +153,15 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ -/* example package: hello */ +/* Privated Packages of RealThread */ + + +/* Network Utilities */ +#define SOC_AT91SAM926 #define RT_USING_DBGU #define RT_USING_LED diff --git a/bsp/beaglebone/.config b/bsp/beaglebone/.config index e3fcf0f7ad5c83d5e556733048fc89e8fe02f181..f0886969c5bfe6de6fa7962ba0accf9f5edf34e9 100644 --- a/bsp/beaglebone/.config +++ b/bsp/beaglebone/.config @@ -7,6 +7,9 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y @@ -15,6 +18,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set @@ -61,6 +65,14 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +# CONFIG_RT_IOREMAP_LATE is not set +CONFIG_ARCH_ARM_CORTEX_A=y +# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set # # RT-Thread Components @@ -106,6 +118,7 @@ CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_ELMFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set @@ -115,22 +128,33 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set # # Using USB @@ -143,6 +167,11 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set # @@ -155,14 +184,14 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -177,8 +206,10 @@ CONFIG_RT_USING_LIBC=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -187,12 +218,20 @@ CONFIG_RT_USING_LIBC=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -210,10 +249,15 @@ CONFIG_RT_USING_LIBC=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set # # IoT Cloud @@ -221,6 +265,33 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_ONENET is not set # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -228,6 +299,8 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -241,6 +314,10 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -249,26 +326,102 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages # # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -279,17 +432,72 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # -# sample package -# -# CONFIG_PKG_USING_SAMPLES is not set - -# -# example package: hello +# samples: kernel and components samples # +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +CONFIG_SOC_AM335X=y CONFIG_RT_USING_UART1=y diff --git a/bsp/beaglebone/Kconfig b/bsp/beaglebone/Kconfig index 2784e360686115e9edfb9e9280f520a811f9fbf0..883b838b268025b87b3b7607aa54350fd50463f6 100644 --- a/bsp/beaglebone/Kconfig +++ b/bsp/beaglebone/Kconfig @@ -27,9 +27,11 @@ source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" config SOC_AM335X - bool + bool + select ARCH_ARM_CORTEX_A select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y config RT_USING_UART1 diff --git a/bsp/beaglebone/rtconfig.h b/bsp/beaglebone/rtconfig.h index 4a9030fc4835cafbd30e5e2cb77d83821b0d532d..6e0fc5efc0d7d3a398b9f1114c6869b010cd0b89 100644 --- a/bsp/beaglebone/rtconfig.h +++ b/bsp/beaglebone/rtconfig.h @@ -13,6 +13,7 @@ #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_DEBUG @@ -38,6 +39,10 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define ARCH_ARM +#define ARCH_ARM_CORTEX_A /* RT-Thread Components */ @@ -79,6 +84,7 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN /* Using USB */ @@ -87,16 +93,17 @@ /* POSIX layer and C standard library */ #define RT_USING_LIBC +#define RT_USING_POSIX /* Network */ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -145,11 +152,15 @@ /* miscellaneous packages */ -/* sample package */ +/* samples: kernel and components samples */ + + +/* Privated Packages of RealThread */ -/* example package: hello */ +/* Network Utilities */ +#define SOC_AM335X #define RT_USING_UART1 #endif diff --git a/bsp/d1-allwinner-nezha/.config b/bsp/d1-allwinner-nezha/.config new file mode 100644 index 0000000000000000000000000000000000000000..7b3b8988fa5a33e44b46548534fa5f681faedbd0 --- /dev/null +++ b/bsp/d1-allwinner-nezha/.config @@ -0,0 +1,647 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=20 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +# CONFIG_RT_USING_OVERFLOW_CHECK is not set +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=16384 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=16384 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMTRACE=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x50000 +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0x150000000 +CONFIG_PV_OFFSET=0 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV64=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=16384 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y +# CONFIG_RT_USING_MLIB is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_USING_POSIX_CLOCKTIME=y +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_RT_USING_ARDUINO is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_USB_STACK is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set +CONFIG_BOARD_allwinnerd1=y +CONFIG_ENABLE_FPU=y +# CONFIG_RT_USING_USERSPACE_32BIT_LIMIT is not set + +# +# General Purpose UARTs +# +# CONFIG_BSP_USING_UART1 is not set +CONFIG_RT_USING_SUNXI_HAL=y +CONFIG___STACKSIZE__=16384 diff --git a/bsp/d1-allwinner-nezha/.gitignore b/bsp/d1-allwinner-nezha/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..530a897fce0a62aca0ce0c16c88798754320f27f --- /dev/null +++ b/bsp/d1-allwinner-nezha/.gitignore @@ -0,0 +1,9 @@ +__pycache__/ +rtthread.bin +rtthread.elf +*.map +build/ +.sconsign.dblite +cconfig.h +.vscode/ +rtconfig.pyc diff --git a/bsp/d1-allwinner-nezha/BUGS.md b/bsp/d1-allwinner-nezha/BUGS.md new file mode 100644 index 0000000000000000000000000000000000000000..6a5cdd46e9f31d204077cdade9cfaa2b06f20cb4 --- /dev/null +++ b/bsp/d1-allwinner-nezha/BUGS.md @@ -0,0 +1,3 @@ +# BUGS: +* [] 2021/10/28 + 执行cpp程序不能加载/不能在romfs里面执行cpp程序 diff --git a/bsp/d1-allwinner-nezha/Kconfig b/bsp/d1-allwinner-nezha/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..3ceb953fa1b6e7783214712b8b21bf1e256f5b68 --- /dev/null +++ b/bsp/d1-allwinner-nezha/Kconfig @@ -0,0 +1,47 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config BOARD_allwinnerd1 + bool + select ARCH_RISCV64 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_CACHE + select ARCH_MM_MMU + default y + +config RT_USING_USERSPACE + bool + default y + +config ENABLE_FPU + bool "Enable FPU" + default y + +config RT_USING_USERSPACE_32BIT_LIMIT + bool "Enable userspace 32bit limit" + default n + +source "drivers/Kconfig" +source "libraries/Kconfig" + +config __STACKSIZE__ + int "stack size for interrupt" + default 4096 diff --git a/bsp/d1-allwinner-nezha/README.md b/bsp/d1-allwinner-nezha/README.md new file mode 100644 index 0000000000000000000000000000000000000000..660e3d7bb6bab9e0426ab3b7e27169b36c51a52f --- /dev/null +++ b/bsp/d1-allwinner-nezha/README.md @@ -0,0 +1 @@ +# RT-Thread全志D1移植 diff --git a/bsp/d1-allwinner-nezha/SConscript b/bsp/d1-allwinner-nezha/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/d1-allwinner-nezha/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/d1-allwinner-nezha/SConstruct b/bsp/d1-allwinner-nezha/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..d42964ee59f8f7b93ff68904672365c96b84235a --- /dev/null +++ b/bsp/d1-allwinner-nezha/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +rtconfig.CPU='c906' +rtconfig.VENDOR="t-head" +rtconfig.ARCH='risc-v' + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +stack_size = 4096 + +stack_lds = open('link_stacksize.lds', 'w') +if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__') +stack_lds.write('__STACKSIZE__ = %d;' % stack_size) +stack_lds.close() + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/d1-allwinner-nezha/applications/SConscript b/bsp/d1-allwinner-nezha/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..9ffdfd6d3ac13244a32fb825524e12e0ca88c585 --- /dev/null +++ b/bsp/d1-allwinner-nezha/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/d1-allwinner-nezha/applications/main.c b/bsp/d1-allwinner-nezha/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..17c70e747c1c505f8c4edc4c152ea9cd52b1775c --- /dev/null +++ b/bsp/d1-allwinner-nezha/applications/main.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include +#include +#include + +int main(void) +{ + void rt_hw_uart_start_rx_thread(); + rt_hw_uart_start_rx_thread(); + printf("Hello RISC-V\n"); + + return 0; +} diff --git a/bsp/d1-allwinner-nezha/applications/mnt.c b/bsp/d1-allwinner-nezha/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..8c4199f62d3b52b44433cbf68ed6b99aee3c13bb --- /dev/null +++ b/bsp/d1-allwinner-nezha/applications/mnt.c @@ -0,0 +1,20 @@ +#include + +#ifdef RT_USING_DFS +#include +#include + +int mnt_init(void) +{ + if (dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) != 0) + { + rt_kprintf("Dir / mount failed!\n"); + return -1; + } + + rt_kprintf("file system initialization done!\n"); + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif + diff --git a/bsp/d1-allwinner-nezha/drivers/Kconfig b/bsp/d1-allwinner-nezha/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5744c89702d7f4444a41c20860f929c9372a4a74 --- /dev/null +++ b/bsp/d1-allwinner-nezha/drivers/Kconfig @@ -0,0 +1,18 @@ + + +menu "General Purpose UARTs" + +menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_TXD_PIN + int "uart1 TXD pin number" + default 20 + config BSP_UART1_RXD_PIN + int "uart1 RXD pin number" + default 21 + endif + +endmenu + diff --git a/bsp/d1-allwinner-nezha/drivers/SConscript b/bsp/d1-allwinner-nezha/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..faea9c1bd9bd1920667d46d5b0b9c1b7b68a0726 --- /dev/null +++ b/bsp/d1-allwinner-nezha/drivers/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +objs = [group] + +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/d1-allwinner-nezha/drivers/board.c b/bsp/d1-allwinner-nezha/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..1af9a1c372b3486416459beea5bb38174a5ae3f1 --- /dev/null +++ b/bsp/d1-allwinner-nezha/drivers/board.c @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#include +#include +#include + +#include "board.h" +#include "tick.h" + +#include "drv_uart.h" +#include "encoding.h" +#include "stack.h" +#include "sbi.h" +#include "riscv.h" +#include "stack.h" + +#ifdef RT_USING_USERSPACE + #include "riscv_mmu.h" + #include "mmu.h" + #include "page.h" + #include "lwp_arch.h" + + //这个结构体描述了buddy system的页分配范围 + rt_region_t init_page_region = + { + (rt_size_t)RT_HW_PAGE_START, + (rt_size_t)RT_HW_PAGE_END + }; + + //内核页表 + volatile rt_size_t MMUTable[__SIZE(VPN2_BIT)] __attribute__((aligned(4 * 1024))); + rt_mmu_info mmu_info; + +#endif + +//初始化BSS节区 +void init_bss(void) +{ + unsigned int *dst; + + dst = &__bss_start; + while (dst < &__bss_end) + { + *dst++ = 0; + } +} + +static void __rt_assert_handler(const char *ex_string, const char *func, rt_size_t line) +{ + rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line); + asm volatile("ebreak":::"memory"); +} + +//BSP的C入口 +void primary_cpu_entry(void) +{ + extern void entry(void); + + //初始化BSS + init_bss(); + //关中断 + rt_hw_interrupt_disable(); + rt_assert_set_hook(__rt_assert_handler); + //启动RT-Thread Smart内核 + entry(); +} + + +//这个初始化程序由内核主动调用，此时调度器还未启动，因此在此不能使用依赖线程上下文的函数 +void rt_hw_board_init(void) +{ + /* initalize interrupt */ + rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_uart_init(); + rt_hw_tick_init(); +#ifdef RT_USING_HEAP + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device("uart"); +#endif /* RT_USING_CONSOLE */ + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_HEAP + rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END); +#endif + +#ifdef RT_USING_USERSPACE + rt_page_init(init_page_region); + rt_hw_mmu_map_init(&mmu_info,(void *)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, (rt_size_t *)MMUTable, 0); + rt_hw_mmu_kernel_map_init(&mmu_info, 0x00000000UL, USER_VADDR_START - 1); + + //将低1GB MMIO区域设置为无Cache与Strong Order访存模式 + MMUTable[0] &= ~PTE_CACHE; + MMUTable[0] &= ~PTE_SHARE; + MMUTable[0] |= PTE_SO; + switch_mmu((void *)MMUTable); +#endif +} + +void rt_hw_cpu_reset(void) +{ + sbi_shutdown(); + while(1); +} +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); diff --git a/bsp/d1-allwinner-nezha/drivers/board.h b/bsp/d1-allwinner-nezha/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..835ea87fc292044ae2a04f0f8e870633af148e3b --- /dev/null +++ b/bsp/d1-allwinner-nezha/drivers/board.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ + +#include + +extern unsigned int __bss_start; +extern unsigned int __bss_end; + +#define RT_HW_HEAP_BEGIN ((void *)&__bss_end) +#define RT_HW_HEAP_END ((void *)(((rt_size_t)RT_HW_HEAP_BEGIN) + 50 * 1024 * 1024)) +#define RT_HW_PAGE_START RT_HW_HEAP_END +#define RT_HW_PAGE_END ((void *)(((rt_size_t)RT_HW_PAGE_START) + 50 * 1024 * 1024)) + +void rt_hw_board_init(void); +void rt_init_user_mem(struct rt_thread *thread, const char *name, unsigned long *entry); + +#endif diff --git a/bsp/d1-allwinner-nezha/drivers/drv_uart.c b/bsp/d1-allwinner-nezha/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..ffab3ed132394e8c9f8139931434df577a30cf96 --- /dev/null +++ b/bsp/d1-allwinner-nezha/drivers/drv_uart.c @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#include +#include "sbi.h" + +#define UART_DEFAULT_BAUDRATE 115200 +#define SUNXI_UART_ADDR 0x02500000 + +#define SUNXI_UART_RBR (0x00) /* receive buffer register */ +#define SUNXI_UART_THR (0x00) /* transmit holding register */ +#define SUNXI_UART_DLL (0x00) /* divisor latch low register */ +#define SUNXI_UART_DLH (0x04) /* diviso latch high register */ +#define SUNXI_UART_IER (0x04) /* interrupt enable register */ +#define SUNXI_UART_IIR (0x08) /* interrupt identity register */ +#define SUNXI_UART_FCR (0x08) /* FIFO control register */ +#define SUNXI_UART_LCR (0x0c) /* line control register */ +#define SUNXI_UART_MCR (0x10) /* modem control register */ +#define SUNXI_UART_LSR (0x14) /* line status register */ +#define SUNXI_UART_MSR (0x18) /* modem status register */ +#define SUNXI_UART_SCH (0x1c) /* scratch register */ +#define SUNXI_UART_USR (0x7c) /* status register */ +#define SUNXI_UART_TFL (0x80) /* transmit FIFO level */ +#define SUNXI_UART_RFL (0x84) /* RFL */ +#define SUNXI_UART_HALT (0xa4) /* halt tx register */ +#define SUNXI_UART_RS485 (0xc0) /* RS485 control and status register */ + +#define BIT(x) (1 << x) + +/* Line Status Rigster */ +#define SUNXI_UART_LSR_RXFIFOE (BIT(7)) +#define SUNXI_UART_LSR_TEMT (BIT(6)) +#define SUNXI_UART_LSR_THRE (BIT(5)) +#define SUNXI_UART_LSR_BI (BIT(4)) +#define SUNXI_UART_LSR_FE (BIT(3)) +#define SUNXI_UART_LSR_PE (BIT(2)) +#define SUNXI_UART_LSR_OE (BIT(1)) +#define SUNXI_UART_LSR_DR (BIT(0)) +#define SUNXI_UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ + +struct device_uart +{ + rt_ubase_t hw_base; + rt_uint32_t irqno; +}; + +static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int drv_uart_putc(struct rt_serial_device *serial, char c); +static int drv_uart_getc(struct rt_serial_device *serial); + +const struct rt_uart_ops _uart_ops = +{ + rt_uart_configure, + uart_control, + drv_uart_putc, + drv_uart_getc, + //TODO: add DMA support + RT_NULL +}; + +void uart_init(void) +{ + return ; +} + +struct rt_serial_device serial1; +struct device_uart uart1; + +/* + * UART interface + */ +static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct device_uart *uart; + + RT_ASSERT(serial != RT_NULL); + serial->config = *cfg; + + return (RT_EOK); +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct device_uart *uart; + + uart = serial->parent.user_data; + rt_uint32_t channel = 1; + + RT_ASSERT(uart != RT_NULL); + RT_ASSERT(channel != 3); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + break; + + case RT_DEVICE_CTRL_SET_INT: + break; + } + + return (RT_EOK); +} + +static int drv_uart_putc(struct rt_serial_device *serial, char c) +{ + sbi_console_putchar(c); + return (1); +} + +static int drv_uart_getc(struct rt_serial_device *serial) +{ + uint32_t *lsr = (uint32_t *)(SUNXI_UART_ADDR + SUNXI_UART_LSR); + uint32_t *rbr = (uint32_t *)(SUNXI_UART_ADDR + SUNXI_UART_RBR); + + if(!(*lsr & SUNXI_UART_LSR_DR)) + { + return -1; + } + + return (int)*rbr; +} + +//串口接收监视线程 +static void uart_rx(void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + while(1) + { + rt_hw_serial_isr((struct rt_serial_device *)serial,RT_SERIAL_EVENT_RX_IND); + rt_thread_mdelay(10); + } +} + +//用于启动串口接收监视线程 +void rt_hw_uart_start_rx_thread() +{ + rt_thread_t th; + RT_ASSERT((th = rt_thread_create("uartrx",uart_rx,(void *)&serial1,8192,8,20)) != RT_NULL); + RT_ASSERT(rt_thread_startup(th) == RT_EOK); +} + +/* + * UART Initiation + */ +int rt_hw_uart_init(void) +{ + struct rt_serial_device *serial; + struct device_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + { + serial = &serial1; + uart = &uart1; + + serial->ops = &_uart_ops; + serial->config = config; + serial->config.baud_rate = UART_DEFAULT_BAUDRATE; + + uart->hw_base = 0x10000000; + uart->irqno = 0xa; + + rt_hw_serial_register(serial, + "uart", + RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + } + + return 0; +} + +/* WEAK for SDK 0.5.6 */ +RT_WEAK void uart_debug_init(int uart_channel) +{ +} diff --git a/bsp/d1-allwinner-nezha/drivers/drv_uart.h b/bsp/d1-allwinner-nezha/drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..a7a18d0ddeabc8045f058a7bccc252cf4bcbe5c0 --- /dev/null +++ b/bsp/d1-allwinner-nezha/drivers/drv_uart.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +void rt_hw_uart_start_rx_thread(); +int rt_hw_uart_init(void); +void drv_uart_puts(char *str); // for syscall + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/d1-allwinner-nezha/generateimg.sh b/bsp/d1-allwinner-nezha/generateimg.sh new file mode 100755 index 0000000000000000000000000000000000000000..fd3d660b5d24efc7781d1992428876f3884c56fa --- /dev/null +++ b/bsp/d1-allwinner-nezha/generateimg.sh @@ -0,0 +1,2 @@ +#!/bin/sh +mkimage -A riscv -O linux -T kernel -C none -a 0x45000000 -e 0x45000000 -d rtthread.bin rtthread.img \ No newline at end of file diff --git a/bsp/d1-allwinner-nezha/libraries/Kconfig b/bsp/d1-allwinner-nezha/libraries/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..0d3bf9f9157386b5558bf281d2bb0b3a2b7b2ea5 --- /dev/null +++ b/bsp/d1-allwinner-nezha/libraries/Kconfig @@ -0,0 +1,3 @@ +menuconfig RT_USING_SUNXI_HAL + bool "HAL library from sunxi" + default n diff --git a/bsp/d1-allwinner-nezha/libraries/README.md b/bsp/d1-allwinner-nezha/libraries/README.md new file mode 100644 index 0000000000000000000000000000000000000000..272bf01b8af32f3ebe553aa04030836656ff0913 --- /dev/null +++ b/bsp/d1-allwinner-nezha/libraries/README.md @@ -0,0 +1,3 @@ +# allwinner-libraries + +针对全志芯片的外设驱动库 \ No newline at end of file diff --git a/bsp/d1-allwinner-nezha/libraries/SConscript b/bsp/d1-allwinner-nezha/libraries/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..ec8fa4bf27dd863194ee90c193f292d973bc7842 --- /dev/null +++ b/bsp/d1-allwinner-nezha/libraries/SConscript @@ -0,0 +1,18 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +if not GetDepend('RT_USING_SUNXI_HAL'): + Return('objs') + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/d1-allwinner-nezha/link.lds b/bsp/d1-allwinner-nezha/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..ae787777034d5d9b150f97b059a7737b7b629cd5 --- /dev/null +++ b/bsp/d1-allwinner-nezha/link.lds @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/12/12 bernard The first version + */ + +INCLUDE "link_stacksize.lds" + +OUTPUT_ARCH( "riscv" ) + +/* + * Memory layout: + * 0x10200000 - 0x10201000: Bootloader + * 0x10201000 - 0x10A00000: Kernel + * 0x10A00000 - 0x11200000: Heap + */ + +MEMORY +{ + SRAM : ORIGIN = 0x45000000, LENGTH = 0x7FF000 +} + +ENTRY(_start) +SECTIONS +{ + . = 0x45000000 ; + + /* __STACKSIZE__ = 4096; */ + + .start : + { + *(.start); + } > SRAM + + . = ALIGN(8); + + .text : + { + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for initial. */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(8); + + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + . = ALIGN(8); + _etext = .; + } > SRAM + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } > SRAM + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM + + . = ALIGN(8); + + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.sdata) + *(.sdata.*) + } > SRAM + + /* stack for dual core */ + .stack : + { + . = ALIGN(64); + __stack_start__ = .; + + . += __STACKSIZE__; + __stack_cpu0 = .; + + . += __STACKSIZE__; + __stack_cpu1 = .; + } > SRAM + + . = ALIGN(8); + + .osdebug : + { + _osdebug_start = .; + . += 87K; + _osdebug_end = .; + } > SRAM + + . = ALIGN(8); + + .sbss : + { + __bss_start = .; + *(.sbss) + *(.sbss.*) + *(.dynsbss) + *(.scommon) + } > SRAM + + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + __bss_end = .; + } > SRAM + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/d1-allwinner-nezha/link_stacksize.lds b/bsp/d1-allwinner-nezha/link_stacksize.lds new file mode 100644 index 0000000000000000000000000000000000000000..8685bc0f1c2d15f0a4bf11d75e743e5a61b16d95 --- /dev/null +++ b/bsp/d1-allwinner-nezha/link_stacksize.lds @@ -0,0 +1 @@ +__STACKSIZE__ = 16384; \ No newline at end of file diff --git a/bsp/d1-allwinner-nezha/rtconfig.h b/bsp/d1-allwinner-nezha/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..fc8b52ace337c3bfea6d754d99e25814dfe062ce --- /dev/null +++ b/bsp/d1-allwinner-nezha/rtconfig.h @@ -0,0 +1,213 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 20 +#define RT_USING_SMART +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 16384 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 16384 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMTRACE +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x50000 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_MM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0x150000000 +#define PV_OFFSET 0 +#define ARCH_RISCV +#define ARCH_RISCV64 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 16384 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 32 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_TTY +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_MUSL +#define RT_USING_POSIX +#define RT_USING_POSIX_CLOCKTIME + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define BOARD_allwinnerd1 +#define ENABLE_FPU + +/* General Purpose UARTs */ + +#define RT_USING_SUNXI_HAL +#define __STACKSIZE__ 16384 + +#endif diff --git a/bsp/d1-allwinner-nezha/rtconfig.py b/bsp/d1-allwinner-nezha/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..b72df4dc03684874e40004e61666c7cfe9cced2c --- /dev/null +++ b/bsp/d1-allwinner-nezha/rtconfig.py @@ -0,0 +1,56 @@ +import os + +# toolchains options +ARCH ='risc-v' +VENDOR ='t-head' +CPU ='c906' +CROSS_TOOL ='gcc' + +RTT_ROOT = os.getenv('RTT_ROOT') or os.path.join(os.getcwd(),'..','..') + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/riscv64_musl/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + #PREFIX = 'riscv64-unknown-elf-' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64' + CFLAGS = DEVICE + ' -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields ' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -ggdb' + AFLAGS += ' -ggdb' + else: + CFLAGS += ' -O2 -Os' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n./generateimg.sh\n' diff --git a/bsp/d1-allwinner-nezha/sdcard.bat b/bsp/d1-allwinner-nezha/sdcard.bat new file mode 100644 index 0000000000000000000000000000000000000000..33a56d3020d0a8be7a217007c224c4fd9883b441 --- /dev/null +++ b/bsp/d1-allwinner-nezha/sdcard.bat @@ -0,0 +1,10 @@ +@echo off + +if "%1" EQU "" ( + echo Please input you sdcard volumn! sucn as "sdcard.bat G" +) else ( + echo copy rtthread.bin to volumn:%1 + copy rtthread.bin %1: +) + +@echo on diff --git a/bsp/efm32/copy_this_file_dfs_elm.c b/bsp/efm32/copy_this_file_dfs_elm.c deleted file mode 100644 index c726d0c355e6539507a4cce44024103520413b2f..0000000000000000000000000000000000000000 --- a/bsp/efm32/copy_this_file_dfs_elm.c +++ /dev/null @@ -1,964 +0,0 @@ -/* - * File : dfs_elm.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2008-2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE. - * - * Change Logs: - * Date Author Notes - * 2008-02-22 QiuYi The first version. - * 2011-10-08 Bernard fixed the block size in statfs. - * 2011-11-23 Bernard fixed the rename issue. - */ - -#include -#include "ffconf.h" -#include "ff.h" - -/* ELM FatFs provide a DIR struct */ -#define HAVE_DIR_STRUCTURE - -#include -#include - -#ifdef DFS_ELMFAT_INTERFACE_EFM -#include "diskio.h" - -/* Disk status */ -static volatile DSTATUS diskStat[_VOLUMES]; -#endif -static rt_device_t disk[_VOLUMES] = {0}; - -static int elm_result_to_dfs(FRESULT result) -{ - int status = DFS_STATUS_OK; - - switch (result) - { - case FR_OK: - break; - - case FR_NO_FILE: - case FR_NO_PATH: - case FR_NO_FILESYSTEM: - status = -DFS_STATUS_ENOENT; - break; - - case FR_INVALID_NAME: - status = -DFS_STATUS_EINVAL; - break; - - case FR_EXIST: - case FR_INVALID_OBJECT: - status = -DFS_STATUS_EEXIST; - break; - - case FR_DISK_ERR: - case FR_NOT_READY: - case FR_INT_ERR: - status = -DFS_STATUS_EIO; - break; - - case FR_WRITE_PROTECTED: - case FR_DENIED: - status = -DFS_STATUS_EROFS; - break; - - case FR_MKFS_ABORTED: - status = -DFS_STATUS_EINVAL; - break; - - default: - status = -1; - break; - } - - return status; -} - -int dfs_elm_mount(struct dfs_filesystem *fs, unsigned long rwflag, const void *data) -{ - FATFS *fat; - FRESULT result; - rt_uint32_t index; - - /* handle RT-Thread device routine */ - for (index = 0; index < _VOLUMES; index ++) - { - if (disk[index] == RT_NULL) - { - break; - } - } - if (index == _VOLUMES) - return -DFS_STATUS_ENOSPC; - - /* get device */ - disk[index] = fs->dev_id; - - fat = (FATFS *)rt_malloc(sizeof(FATFS)); - if (fat == RT_NULL) - { - return -1; - } - - /* mount fatfs, always 0 logic driver */ - result = f_mount(index, fat); - if (result == FR_OK) - fs->data = fat; - else - { - rt_free(fat); - return elm_result_to_dfs(result); - } - - return 0; -} - -int dfs_elm_unmount(struct dfs_filesystem *fs) -{ - FATFS *fat; - FRESULT result; - rt_uint32_t index; - - fat = (FATFS *)fs->data; - - RT_ASSERT(fat != RT_NULL); - - /* find the device index and then umount it */ - for (index = 0; index < _VOLUMES; index ++) - { - if (disk[index] == fs->dev_id) - { - result = f_mount(index, RT_NULL); - - if (result == FR_OK) - { - fs->data = RT_NULL; - disk[index] = RT_NULL; - rt_free(fat); - return DFS_STATUS_OK; - } - } - } - - return -DFS_STATUS_ENOENT; -} - -int dfs_elm_mkfs(const char *device_name) -{ - BYTE drv; - rt_device_t dev; - FRESULT result; - - /* find device name */ - for (drv = 0; drv < _VOLUMES; drv ++) - { - dev = disk[drv]; - if (rt_strncmp(dev->parent.name, device_name, RT_NAME_MAX) == 0) - { - /* 1: no partition table */ - /* 0: auto selection of cluster size */ - result = f_mkfs(drv, 1, 0); - if (result != FR_OK) - { - rt_kprintf("format error\n"); - return elm_result_to_dfs(result); - } - - return DFS_STATUS_OK; - } - } - - /* can't find device driver */ - rt_kprintf("can not find device driver: %s\n", device_name); - return -DFS_STATUS_EIO; -} - -int dfs_elm_statfs(struct dfs_filesystem *fs, struct statfs *buf) -{ - FATFS *f; - FRESULT res; - char driver[4]; - DWORD fre_clust, fre_sect, tot_sect; - - RT_ASSERT(fs != RT_NULL); - RT_ASSERT(buf != RT_NULL); - - f = (FATFS *)fs->data; - - rt_snprintf(driver, sizeof(driver), "%d:", f->drv); - res = f_getfree(driver, &fre_clust, &f); - if (res) - return elm_result_to_dfs(res); - - /* Get total sectors and free sectors */ - tot_sect = (f->n_fatent - 2) * f->csize; - fre_sect = fre_clust * f->csize; - - buf->f_bfree = fre_sect; - buf->f_blocks = tot_sect; -#if _MAX_SS != 512 - buf->f_bsize = f->ssize; -#else - buf->f_bsize = 512; -#endif - - return 0; -} - -int dfs_elm_open(struct dfs_fd *file) -{ - FIL *fd; - BYTE mode; - FRESULT result; - char *drivers_fn; - -#if (_VOLUMES > 1) - int vol; - extern int elm_get_vol(FATFS *fat); - - /* add path for ELM FatFS driver support */ - vol = elm_get_vol((FATFS *)file->fs->data); - if (vol < 0) - return -DFS_STATUS_ENOENT; - drivers_fn = rt_malloc(256); - if (drivers_fn == RT_NULL) - return -DFS_STATUS_ENOMEM; - - rt_snprintf(drivers_fn, 256, "%d:%s", vol, file->path); -#else - drivers_fn = file->path; -#endif - - if (file->flags & DFS_O_DIRECTORY) - { - DIR *dir; - - if (file->flags & DFS_O_CREAT) - { - result = f_mkdir(drivers_fn); - if (result != FR_OK) - { -#if _VOLUMES > 1 - rt_free(drivers_fn); -#endif - return elm_result_to_dfs(result); - } - } - - /* open directory */ - dir = (DIR *)rt_malloc(sizeof(DIR)); - if (dir == RT_NULL) - { -#if _VOLUMES > 1 - rt_free(drivers_fn); -#endif - return -DFS_STATUS_ENOMEM; - } - - result = f_opendir(dir, drivers_fn); -#if _VOLUMES > 1 - rt_free(drivers_fn); -#endif - if (result != FR_OK) - { - rt_free(dir); - return elm_result_to_dfs(result); - } - - file->data = dir; - return DFS_STATUS_OK; - } - else - { - mode = FA_READ; - - if (file->flags & DFS_O_WRONLY) - mode |= FA_WRITE; - if ((file->flags & DFS_O_ACCMODE) & DFS_O_RDWR) - mode |= FA_WRITE; - /* Opens the file, if it is existing. If not, a new file is created. */ - if (file->flags & DFS_O_CREAT) - mode |= FA_OPEN_ALWAYS; - /* Creates a new file. If the file is existing, it is truncated and overwritten. */ - if (file->flags & DFS_O_TRUNC) - mode |= FA_CREATE_ALWAYS; - /* Creates a new file. The function fails if the file is already existing. */ - if (file->flags & DFS_O_EXCL) - mode |= FA_CREATE_NEW; - - /* allocate a fd */ - fd = (FIL *)rt_malloc(sizeof(FIL)); - if (fd == RT_NULL) - { - return -DFS_STATUS_ENOMEM; - } - - result = f_open(fd, drivers_fn, mode); -#if _VOLUMES > 1 - rt_free(drivers_fn); -#endif - if (result == FR_OK) - { - file->pos = fd->fptr; - file->size = fd->fsize; - file->data = fd; - - if (file->flags & DFS_O_APPEND) - { - file->pos = f_lseek(fd, fd->fsize); - } - } - else - { - /* open failed, return */ - rt_free(fd); - return elm_result_to_dfs(result); - } - } - - return DFS_STATUS_OK; -} - -int dfs_elm_close(struct dfs_fd *file) -{ - FRESULT result; - - result = FR_OK; - if (file->type == FT_DIRECTORY) - { - DIR *dir; - - dir = (DIR *)(file->data); - RT_ASSERT(dir != RT_NULL); - - /* release memory */ - rt_free(dir); - } - else if (file->type == FT_REGULAR) - { - FIL *fd; - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); - - result = f_close(fd); - if (result == FR_OK) - { - /* release memory */ - rt_free(fd); - } - } - - return elm_result_to_dfs(result); -} - -int dfs_elm_ioctl(struct dfs_fd *file, int cmd, void *args) -{ - return -DFS_STATUS_ENOSYS; -} - -int dfs_elm_read(struct dfs_fd *file, void *buf, rt_size_t len) -{ - FIL *fd; - FRESULT result; - UINT byte_read; - - if (file->type == FT_DIRECTORY) - { - return -DFS_STATUS_EISDIR; - } - - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); - - result = f_read(fd, buf, len, &byte_read); - /* update position */ - file->pos = fd->fptr; - if (result == FR_OK) - return byte_read; - - return elm_result_to_dfs(result); -} - -int dfs_elm_write(struct dfs_fd *file, const void *buf, rt_size_t len) -{ - FIL *fd; - FRESULT result; - UINT byte_write; - - if (file->type == FT_DIRECTORY) - { - return -DFS_STATUS_EISDIR; - } - - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); - - result = f_write(fd, buf, len, &byte_write); - /* update position and file size */ - file->pos = fd->fptr; - file->size = fd->fsize; - if (result == FR_OK) - return byte_write; - - return elm_result_to_dfs(result); -} - -int dfs_elm_flush(struct dfs_fd *file) -{ - FIL *fd; - FRESULT result; - - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); - - result = f_sync(fd); - return elm_result_to_dfs(result); -} - -int dfs_elm_lseek(struct dfs_fd *file, rt_off_t offset) -{ - FRESULT result = FR_OK; - if (file->type == FT_REGULAR) - { - FIL *fd; - - /* regular file type */ - fd = (FIL *)(file->data); - RT_ASSERT(fd != RT_NULL); - - result = f_lseek(fd, offset); - if (result == FR_OK) - { - /* return current position */ - return fd->fptr; - } - } - else if (file->type == FT_DIRECTORY) - { - /* which is a directory */ - DIR *dir; - - dir = (DIR *)(file->data); - RT_ASSERT(dir != RT_NULL); - - result = f_seekdir(dir, offset / sizeof(struct dirent)); - if (result == FR_OK) - { - /* update file position */ - file->pos = offset; - return file->pos; - } - } - - return elm_result_to_dfs(result); -} - -int dfs_elm_getdents(struct dfs_fd *file, struct dirent *dirp, rt_uint32_t count) -{ - DIR *dir; - FILINFO fno; - FRESULT result; - rt_uint32_t index; - struct dirent *d; - - dir = (DIR *)(file->data); - RT_ASSERT(dir != RT_NULL); - - /* make integer count */ - count = (count / sizeof(struct dirent)) * sizeof(struct dirent); - if (count == 0) - return -DFS_STATUS_EINVAL; - -#if _USE_LFN - /* allocate long file name */ - fno.lfname = rt_malloc(256); - fno.lfsize = 256; -#endif - - index = 0; - while (1) - { - char *fn; - - d = dirp + index; - - result = f_readdir(dir, &fno); - if (result != FR_OK || fno.fname[0] == 0) - break; - -#if _USE_LFN - fn = *fno.lfname? fno.lfname : fno.fname; -#else - fn = fno.fname; -#endif - - d->d_type = DFS_DT_UNKNOWN; - if (fno.fattrib & AM_DIR) - d->d_type = DFS_DT_DIR; - else - d->d_type = DFS_DT_REG; - - d->d_namlen = rt_strlen(fn); - d->d_reclen = (rt_uint16_t)sizeof(struct dirent); - rt_strncpy(d->d_name, fn, rt_strlen(fn) + 1); - - index ++; - if (index * sizeof(struct dirent) >= count) - break; - } - -#if _USE_LFN - rt_free(fno.lfname); -#endif - - if (index == 0) - return elm_result_to_dfs(result); - - file->pos += index * sizeof(struct dirent); - - return index * sizeof(struct dirent); -} - -int dfs_elm_unlink(struct dfs_filesystem *fs, const char *path) -{ - FRESULT result; - -#if _VOLUMES > 1 - int vol; - char *drivers_fn; - extern int elm_get_vol(FATFS *fat); - - /* add path for ELM FatFS driver support */ - vol = elm_get_vol((FATFS *)fs->data); - if (vol < 0) - return -DFS_STATUS_ENOENT; - drivers_fn = rt_malloc(256); - if (drivers_fn == RT_NULL) - return -DFS_STATUS_ENOMEM; - - rt_snprintf(drivers_fn, 256, "%d:%s", vol, path); -#else - const char *drivers_fn; - drivers_fn = path; -#endif - - result = f_unlink(drivers_fn); -#if _VOLUMES > 1 - rt_free(drivers_fn); -#endif - return elm_result_to_dfs(result); -} - -int dfs_elm_rename(struct dfs_filesystem *fs, const char *oldpath, const char *newpath) -{ - FRESULT result; - -#if _VOLUMES > 1 - char *drivers_oldfn; - const char *drivers_newfn; - int vol; - extern int elm_get_vol(FATFS *fat); - - /* add path for ELM FatFS driver support */ - vol = elm_get_vol((FATFS *)fs->data); - if (vol < 0) - return -DFS_STATUS_ENOENT; - - drivers_oldfn = rt_malloc(256); - if (drivers_oldfn == RT_NULL) - return -DFS_STATUS_ENOMEM; - drivers_newfn = newpath; - - rt_snprintf(drivers_oldfn, 256, "%d:%s", vol, oldpath); -#else - const char *drivers_oldfn, *drivers_newfn; - - drivers_oldfn = oldpath; - drivers_newfn = newpath; -#endif - - result = f_rename(drivers_oldfn, drivers_newfn); -#if _VOLUMES > 1 - rt_free(drivers_oldfn); -#endif - return elm_result_to_dfs(result); -} - -int dfs_elm_stat(struct dfs_filesystem *fs, const char *path, struct stat *st) -{ - FILINFO file_info; - FRESULT result; - - -#if _VOLUMES > 1 - int vol; - char *drivers_fn; - extern int elm_get_vol(FATFS *fat); - - /* add path for ELM FatFS driver support */ - vol = elm_get_vol((FATFS *)fs->data); - if (vol < 0) - return -DFS_STATUS_ENOENT; - drivers_fn = rt_malloc(256); - if (drivers_fn == RT_NULL) - return -DFS_STATUS_ENOMEM; - - rt_snprintf(drivers_fn, 256, "%d:%s", vol, path); -#else - const char *drivers_fn; - drivers_fn = path; -#endif - -#if _USE_LFN - /* allocate long file name */ - file_info.lfname = rt_malloc(256); - file_info.lfsize = 256; -#endif - - result = f_stat(drivers_fn, &file_info); -#if _VOLUMES > 1 - rt_free(drivers_fn); -#endif - if (result == FR_OK) - { - /* convert to dfs stat structure */ - st->st_dev = 0; - - st->st_mode = DFS_S_IFREG | DFS_S_IRUSR | DFS_S_IRGRP | DFS_S_IROTH | - DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH; - if (file_info.fattrib & AM_DIR) - { - st->st_mode &= ~DFS_S_IFREG; - st->st_mode |= DFS_S_IFDIR | DFS_S_IXUSR | DFS_S_IXGRP | DFS_S_IXOTH; - } - if (file_info.fattrib & AM_RDO) - st->st_mode &= ~(DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH); - - st->st_size = file_info.fsize; - st->st_mtime = file_info.ftime; - } - -#if _USE_LFN - rt_free(file_info.lfname); -#endif - - return elm_result_to_dfs(result); -} - -static const struct dfs_filesystem_operation dfs_elm = -{ - "elm", - dfs_elm_mount, - dfs_elm_unmount, - dfs_elm_mkfs, - dfs_elm_statfs, - - dfs_elm_open, - dfs_elm_close, - dfs_elm_ioctl, - dfs_elm_read, - dfs_elm_write, - dfs_elm_flush, - dfs_elm_lseek, - dfs_elm_getdents, - dfs_elm_unlink, - dfs_elm_stat, - dfs_elm_rename, -}; - -int elm_init(void) -{ -#ifdef DFS_ELMFAT_INTERFACE_EFM - int i; - - for (i = 0; i < _VOLUMES; i++) - { - diskStat[i] = STA_NOINIT; - } -#endif - - /* register fatfs file system */ - dfs_register(&dfs_elm); - - return 0; -} - -/* - * RT-Thread Device Interface for ELM FatFs - */ -#ifdef DFS_ELMFAT_INTERFACE_EFM -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ -DSTATUS disk_initialize ( - BYTE drv /* Physical drive nmuber */ - ) -{ - rt_device_t device = disk[drv]; - - if (!device) - { - return RES_ERROR; - } - if (diskStat[drv] & STA_NODISK) - { - /* No card in the socket */ - return diskStat[drv]; - } - - /* Initialize hardware: the actual operation is performed in dfs_mount() */ - diskStat[drv] &= ~STA_NOINIT; - - return diskStat[drv]; -} - -/*-----------------------------------------------------------------------*/ -/* Get Disk Status */ -/*-----------------------------------------------------------------------*/ -DSTATUS disk_status ( - BYTE drv /* Physical drive nmuber */ - ) -{ - return diskStat[drv]; -} - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ -DRESULT disk_read ( - BYTE drv, /* Physical drive nmuber */ - BYTE *buff, /* Pointer to the data buffer to store read data */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ - ) -{ - rt_device_t device = disk[drv]; - - if (!device) - { - return RES_ERROR; - } - if (!count) - { - return RES_PARERR; - } - if (diskStat[drv] & STA_NOINIT) - { - return RES_NOTRDY; - } - - if (rt_device_read(device, sector, buff, count) != count) - { - return RES_ERROR; - } - else - { - return RES_OK; - } -} - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ -#if _READONLY == 0 -DRESULT disk_write ( - BYTE drv, /* Physical drive nmuber */ - const BYTE *buff, /* Pointer to the data to be written */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ - ) -{ - rt_device_t device = disk[drv]; - - if (!device) - { - return RES_ERROR; - } - if (!count) - { - return RES_PARERR; - } - if (diskStat[drv] & STA_NOINIT) - { - return RES_NOTRDY; - } - if (diskStat[drv] & STA_PROTECT) - { - return RES_WRPRT; - } - - if (rt_device_write(device, sector, buff, count) != count) - { - return RES_ERROR; - } - else - { - return RES_OK; - } -} -#endif /* _READONLY */ - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive nmuber */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive data block */ -) -{ - rt_device_t device = disk[drv]; - - if (!device) - { - return RES_ERROR; - } - if (diskStat[drv] & STA_NOINIT) - { - return RES_NOTRDY; - } - - if (rt_device_control(device, ctrl, buff) != RT_EOK) - { - return RES_ERROR; - } - else - { - return RES_OK; - } -} -#else -#include "diskio.h" - -/* Inidialize a Drive */ -DSTATUS disk_initialize(BYTE drv) -{ - return 0; -} - -/* Return Disk Status */ -DSTATUS disk_status(BYTE drv) -{ - return 0; -} - -/* Read Sector(s) */ -DRESULT disk_read(BYTE drv, BYTE *buff, DWORD sector, BYTE count) -{ - rt_size_t result; - rt_device_t device = disk[drv]; - - result = rt_device_read(device, sector, buff, count); - if (result == count) - { - return RES_OK; - } - - return RES_ERROR; -} - -/* Write Sector(s) */ -DRESULT disk_write(BYTE drv, const BYTE *buff, DWORD sector, BYTE count) -{ - rt_size_t result; - rt_device_t device = disk[drv]; - - result = rt_device_write(device, sector, buff, count); - if (result == count) - { - return RES_OK; - } - - return RES_ERROR; -} - -/* Miscellaneous Functions */ -DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff) -{ - rt_device_t device = disk[drv]; - - if (device == RT_NULL) - return RES_ERROR; - - if (ctrl == GET_SECTOR_COUNT) - { - struct rt_device_blk_geometry geometry; - - rt_memset(&geometry, 0, sizeof(geometry)); - rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); - - *(DWORD *)buff = geometry.sector_count; - if (geometry.sector_count == 0) - return RES_ERROR; - } - else if (ctrl == GET_SECTOR_SIZE) - { - struct rt_device_blk_geometry geometry; - - rt_memset(&geometry, 0, sizeof(geometry)); - rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); - - *(WORD *)buff = geometry.bytes_per_sector; - } - else if (ctrl == GET_BLOCK_SIZE) /* Get erase block size in unit of sectors (DWORD) */ - { - struct rt_device_blk_geometry geometry; - - rt_memset(&geometry, 0, sizeof(geometry)); - rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); - - *(DWORD *)buff = geometry.block_size/geometry.bytes_per_sector; - } - - return RES_OK; -} -#endif - -rt_time_t get_fattime(void) -{ - return 0; -} - -#if _FS_REENTRANT -int ff_cre_syncobj(BYTE drv, _SYNC_t *m) -{ - char name[8]; - rt_mutex_t mutex; - - rt_snprintf(name, sizeof(name), "fat%d", drv); - mutex = rt_mutex_create(name, RT_IPC_FLAG_FIFO); - if (mutex != RT_NULL) - { - *m = mutex; - return RT_TRUE; - } - - return RT_FALSE; -} - -int ff_del_syncobj(_SYNC_t m) -{ - rt_mutex_delete(m); - - return RT_TRUE; -} - -int ff_req_grant(_SYNC_t m) -{ - if (rt_mutex_take(m, _FS_TIMEOUT) == RT_EOK) - return RT_TRUE; - - return RT_FALSE; -} - -void ff_rel_grant(_SYNC_t m) -{ - rt_mutex_release(m); -} - -#endif diff --git a/bsp/efm32/copy_this_file_shell.c b/bsp/efm32/copy_this_file_shell.c deleted file mode 100644 index 45ce3cb45a37b798976f9810411c55249ec998fc..0000000000000000000000000000000000000000 --- a/bsp/efm32/copy_this_file_shell.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * File : shell.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-04-30 Bernard the first verion for FinSH - * 2006-05-08 Bernard change finsh thread stack to 2048 - * 2006-06-03 Bernard add support for skyeye - * 2006-09-24 Bernard remove the code related with hardware - * 2010-01-18 Bernard fix down then up key bug. - * 2010-03-19 Bernard fix backspace issue and fix device read in shell. - * 2010-04-01 Bernard add prompt output when start and remove the empty history - * 2011-02-23 Bernard fix variable section end issue of finsh shell - * initialization when use GNU GCC compiler. - */ - -#include -#include - -#include "finsh.h" -#include "shell.h" - -/* finsh thread */ -static struct rt_thread finsh_thread; -ALIGN(RT_ALIGN_SIZE) -static char finsh_thread_stack[FINSH_THREAD_STACK_SIZE]; -struct finsh_shell* shell; - -#if !defined (RT_USING_NEWLIB) && !defined (RT_USING_MINILIBC) -int strcmp (const char *s1, const char *s2) -{ - while (*s1 && *s1 == *s2) s1++, s2++; - - return (*s1 - *s2); -} - -#ifdef RT_USING_HEAP -char *strdup(const char *s) -{ - size_t len = strlen(s) + 1; - char *tmp = (char *)rt_malloc(len); - - if(!tmp) return NULL; - - rt_memcpy(tmp, s, len); - return tmp; -} -#endif - -#if !defined(__CC_ARM) && !defined(__IAR_SYSTEMS_ICC__) -int isalpha( int ch ) -{ - return (unsigned int)((ch | 0x20) - 'a') < 26u; -} - -int atoi(const char* s) -{ - long int v=0; - int sign=1; - while ( *s == ' ' || (unsigned int)(*s - 9) < 5u) s++; - - switch (*s) - { - case '-': sign=-1; - case '+': ++s; - } - - while ((unsigned int) (*s - '0') < 10u) - { - v=v*10+*s-'0'; ++s; - } - - return sign==-1?-v:v; -} - -int isprint(unsigned char ch) -{ - return (unsigned int)(ch - ' ') < 127u - ' '; -} -#endif -#endif - -#if defined(RT_USING_DFS) && defined(DFS_USING_WORKDIR) -#include -const char* finsh_get_prompt(void) -{ - #define _PROMPT "finsh " - static char finsh_prompt[RT_CONSOLEBUF_SIZE + 1] = {_PROMPT}; - - /* get current working directory */ - getcwd(&finsh_prompt[6], RT_CONSOLEBUF_SIZE - 8); - strcat(finsh_prompt, ">"); - - return finsh_prompt; -} -#endif - -static rt_err_t finsh_rx_ind(rt_device_t dev, rt_size_t size) -{ - RT_ASSERT(shell != RT_NULL); - - /* release semaphore to let finsh thread rx data */ - rt_sem_release(&shell->rx_sem); - - return RT_EOK; -} - -/** - * @ingroup finsh - * - * This function sets the input device of finsh shell. - * - * @param device_name the name of new input device. - */ -void finsh_set_device(const char* device_name) -{ - rt_device_t dev = RT_NULL; - - RT_ASSERT(shell != RT_NULL); - dev = rt_device_find(device_name); - if (dev != RT_NULL && rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) == RT_EOK) - { - if (shell->device != RT_NULL) - { - /* close old finsh device */ - rt_device_close(shell->device); - } - - shell->device = dev; - rt_device_set_rx_indicate(dev, finsh_rx_ind); - } - else - { - rt_kprintf("finsh: can not find device:%s\n", device_name); - } -} - -/** - * @ingroup finsh - * - * This function returns current finsh shell input device. - * - * @return the finsh shell input device name is returned. - */ -const char* finsh_get_device() -{ - RT_ASSERT(shell != RT_NULL); - return shell->device->parent.name; -} - -/** - * @ingroup finsh - * - * This function set the echo mode of finsh shell. - * - * FINSH_OPTION_ECHO=0x01 is echo mode, other values are none-echo mode. - * - * @param echo the echo mode - */ -void finsh_set_echo(rt_uint32_t echo) -{ - RT_ASSERT(shell != RT_NULL); - shell->echo_mode = echo; -} - -/** - * @ingroup finsh - * - * This function gets the echo mode of finsh shell. - * - * @return the echo mode - */ -rt_uint32_t finsh_get_echo() -{ - RT_ASSERT(shell != RT_NULL); - - return shell->echo_mode; -} - -void finsh_auto_complete(char* prefix) -{ - extern void list_prefix(char* prefix); - - rt_kprintf("\n"); - list_prefix(prefix); - rt_kprintf("%s%s", FINSH_PROMPT, prefix); -} - -void finsh_run_line(struct finsh_parser* parser, const char *line) -{ - const char* err_str; - - rt_kprintf("\n"); - finsh_parser_run(parser, (unsigned char*)line); - - /* compile node root */ - if (finsh_errno() == 0) - { - finsh_compiler_run(parser->root); - } - else - { - err_str = finsh_error_string(finsh_errno()); - rt_kprintf("%s\n", err_str); - } - - /* run virtual machine */ - if (finsh_errno() == 0) - { - char ch; - finsh_vm_run(); - - ch = (unsigned char)finsh_stack_bottom(); - if (ch > 0x20 && ch < 0x7e) - { - rt_kprintf("\t'%c', %d, 0x%08x\n", - (unsigned char)finsh_stack_bottom(), - (unsigned int)finsh_stack_bottom(), - (unsigned int)finsh_stack_bottom()); - } - else - { - rt_kprintf("\t%d, 0x%08x\n", - (unsigned int)finsh_stack_bottom(), - (unsigned int)finsh_stack_bottom()); - } - } - - finsh_flush(parser); -} - -#ifdef FINSH_USING_HISTORY -rt_bool_t finsh_handle_history(struct finsh_shell* shell, char ch) -{ - /* - * handle up and down key - * up key : 0x1b 0x5b 0x41 - * down key: 0x1b 0x5b 0x42 - */ - if (ch == 0x1b) - { - shell->stat = WAIT_SPEC_KEY; - return RT_TRUE; - } - - if ((shell->stat == WAIT_SPEC_KEY)) - { - if (ch == 0x5b) - { - shell->stat = WAIT_FUNC_KEY; - return RT_TRUE; - } - - shell->stat = WAIT_NORMAL; - return RT_FALSE; - } - - if (shell->stat == WAIT_FUNC_KEY) - { - shell->stat = WAIT_NORMAL; - - if (ch == 0x41) /* up key */ - { - /* prev history */ - if (shell->current_history > 0)shell->current_history --; - else - { - shell->current_history = 0; - return RT_TRUE; - } - - /* copy the history command */ - memcpy(shell->line, &shell->cmd_history[shell->current_history][0], - FINSH_CMD_SIZE); - shell->line_position = strlen(shell->line); - shell->use_history = 1; - } - else if (ch == 0x42) /* down key */ - { - /* next history */ - if (shell->current_history < shell->history_count - 1) - shell->current_history ++; - else - { - /* set to the end of history */ - if (shell->history_count != 0) - { - shell->current_history = shell->history_count - 1; - } - else return RT_TRUE; - } - - memcpy(shell->line, &shell->cmd_history[shell->current_history][0], - FINSH_CMD_SIZE); - shell->line_position = strlen(shell->line); - shell->use_history = 1; - } - - if (shell->use_history) - { - rt_kprintf("\033[2K\r"); - rt_kprintf("%s%s", FINSH_PROMPT, shell->line); - return RT_TRUE;; - } - } - - return RT_FALSE; -} - -void finsh_push_history(struct finsh_shell* shell) -{ - if ((shell->use_history == 0) && (shell->line_position != 0)) - { - /* push history */ - if (shell->history_count >= FINSH_HISTORY_LINES) - { - /* move history */ - int index; - for (index = 0; index < FINSH_HISTORY_LINES - 1; index ++) - { - memcpy(&shell->cmd_history[index][0], - &shell->cmd_history[index + 1][0], FINSH_CMD_SIZE); - } - memset(&shell->cmd_history[index][0], 0, FINSH_CMD_SIZE); - memcpy(&shell->cmd_history[index][0], shell->line, shell->line_position); - - /* it's the maximum history */ - shell->history_count = FINSH_HISTORY_LINES; - } - else - { - memset(&shell->cmd_history[shell->history_count][0], 0, FINSH_CMD_SIZE); - memcpy(&shell->cmd_history[shell->history_count][0], shell->line, shell->line_position); - - /* increase count and set current history position */ - shell->history_count ++; - } - } - shell->current_history = shell->history_count; -} -#endif - -#ifndef RT_USING_HEAP -struct finsh_shell _shell; -#endif -void finsh_thread_entry(void* parameter) -{ - char ch; - - /* test: for efm32 low power mode */ - emu_all_disable(); - - /* normal is echo mode */ - shell->echo_mode = 1; - - finsh_init(&shell->parser); - rt_kprintf(FINSH_PROMPT); - - while (1) - { - /* test: for efm32 low power mode */ - emu_em2_enable(); - - /* wait receive */ - if (rt_sem_take(&shell->rx_sem, RT_WAITING_FOREVER) != RT_EOK) continue; - - /* test: for efm32 low power mode */ - emu_em2_disable(); - - /* read one character from device */ - while (rt_device_read(shell->device, 0, &ch, 1) == 1) - { - /* handle history key */ - #ifdef FINSH_USING_HISTORY - if (finsh_handle_history(shell, ch) == RT_TRUE) continue; - #endif - - /* handle CR key */ - if (ch == '\r') - { - char next; - - if (rt_device_read(shell->device, 0, &next, 1) == 1) - ch = next; - else ch = '\r'; - } - /* handle tab key */ - else if (ch == '\t') - { - /* auto complete */ - finsh_auto_complete(&shell->line[0]); - /* re-calculate position */ - shell->line_position = strlen(shell->line); - continue; - } - /* handle backspace key */ - else if (ch == 0x7f || ch == 0x08) - { - if (shell->line_position != 0) - { - rt_kprintf("%c %c", ch, ch); - } - if (shell->line_position <= 0) shell->line_position = 0; - else shell->line_position --; - shell->line[shell->line_position] = 0; - continue; - } - - /* handle end of line, break */ - if (ch == '\r' || ch == '\n') - { - /* change to ';' and break */ - shell->line[shell->line_position] = ';'; - - #ifdef FINSH_USING_HISTORY - finsh_push_history(shell); - #endif - - if (shell->line_position != 0) finsh_run_line(&shell->parser, shell->line); - else rt_kprintf("\n"); - - rt_kprintf(FINSH_PROMPT); - memset(shell->line, 0, sizeof(shell->line)); - shell->line_position = 0; - - break; - } - - /* it's a large line, discard it */ - if (shell->line_position >= FINSH_CMD_SIZE) shell->line_position = 0; - - /* normal character */ - shell->line[shell->line_position] = ch; ch = 0; - if (shell->echo_mode) rt_kprintf("%c", shell->line[shell->line_position]); - shell->line_position ++; - shell->use_history = 0; /* it's a new command */ - } /* end of device read */ - } -} - -void finsh_system_function_init(const void* begin, const void* end) -{ - _syscall_table_begin = (struct finsh_syscall*) begin; - _syscall_table_end = (struct finsh_syscall*) end; -} - -void finsh_system_var_init(const void* begin, const void* end) -{ - _sysvar_table_begin = (struct finsh_sysvar*) begin; - _sysvar_table_end = (struct finsh_sysvar*) end; -} - -#if defined(__ICCARM__) /* for IAR compiler */ - #ifdef FINSH_USING_SYMTAB - #pragma section="FSymTab" - #pragma section="VSymTab" - #endif -#endif - -/* - * @ingroup finsh - * - * This function will initialize finsh shell - */ -int finsh_system_init(void) -{ - rt_err_t result; - -#ifdef FINSH_USING_SYMTAB -#ifdef __CC_ARM /* ARM C Compiler */ - extern const int FSymTab$$Base; - extern const int FSymTab$$Limit; - extern const int VSymTab$$Base; - extern const int VSymTab$$Limit; - finsh_system_function_init(&FSymTab$$Base, &FSymTab$$Limit); - finsh_system_var_init(&VSymTab$$Base, &VSymTab$$Limit); -#elif defined (__ICCARM__) /* for IAR Compiler */ - finsh_system_function_init(__section_begin("FSymTab"), - __section_end("FSymTab")); - finsh_system_var_init(__section_begin("VSymTab"), - __section_end("VSymTab")); -#elif defined (__GNUC__) /* GNU GCC Compiler */ - extern const int __fsymtab_start; - extern const int __fsymtab_end; - extern const int __vsymtab_start; - extern const int __vsymtab_end; - finsh_system_function_init(&__fsymtab_start, &__fsymtab_end); - finsh_system_var_init(&__vsymtab_start, &__vsymtab_end); -#endif -#endif - - /* create or set shell structure */ -#ifdef RT_USING_HEAP - shell = (struct finsh_shell*)rt_malloc(sizeof(struct finsh_shell)); -#else - shell = &_shell; -#endif - if (shell == RT_NULL) - { - rt_kprintf("no memory for shell\n"); - return; - } - - memset(shell, 0, sizeof(struct finsh_shell)); - - rt_sem_init(&(shell->rx_sem), "shrx", 0, 0); - result = rt_thread_init(&finsh_thread, - "tshell", - finsh_thread_entry, RT_NULL, - &finsh_thread_stack[0], sizeof(finsh_thread_stack), - FINSH_THREAD_PRIORITY, 10); - - if (result == RT_EOK) - rt_thread_startup(&finsh_thread); -} diff --git a/bsp/efm32/rtconfig.h b/bsp/efm32/rtconfig.h index 040f07fa02d48e66e03e197fa6c5b3fe8d2ccb51..fe3569cb68ba19389175d59e39d3b1f2b0f5df40 100644 --- a/bsp/efm32/rtconfig.h +++ b/bsp/efm32/rtconfig.h @@ -213,6 +213,7 @@ /* SECTION: Runtime library */ // #define RT_USING_NOLIBC // #define RT_USING_NEWLIB +#define RT_USING_LIBC #define RT_LIBC_USING_TIME /* SECTION: Console options */ @@ -281,7 +282,7 @@ #define RT_USING_DFS_ELMFAT #define DFS_ELMFAT_INTERFACE_EFM #endif /* defined(EFM32_USING_SPISD) */ -#if defined(RT_USING_NEWLIB) +#if defined(RT_USING_LIBC) #define RT_USING_DFS_DEVFS #endif /* defined(RT_USING_NEWLIB) */ diff --git a/bsp/fh8620/rtconfig.h b/bsp/fh8620/rtconfig.h index ea210a4703b0e0a3688d32e2597fae40d270a256..7fe505e88248ffea899570fc1a6d5356f9fb4943 100644 --- a/bsp/fh8620/rtconfig.h +++ b/bsp/fh8620/rtconfig.h @@ -69,6 +69,8 @@ // #define RT_USING_SLAB // +#define RT_USING_CACHE + //
#define RT_USING_DEVICE // diff --git a/bsp/gkipc/.config b/bsp/gkipc/.config index 9ef3dadbdef9d9fb540dddceb2d00f0fbfe50998..094dd3482d2d9cf3b0157570f7442680e89db779 100644 --- a/bsp/gkipc/.config +++ b/bsp/gkipc/.config @@ -7,22 +7,35 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=32 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set # CONFIG_RT_THREAD_PRIORITY_32 is not set CONFIG_RT_THREAD_PRIORITY_256=y CONFIG_RT_THREAD_PRIORITY_MAX=256 CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=0 -CONFIG_RT_DEBUG_THREAD=0 CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=1024 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=10240 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set # # Inter-Thread communication @@ -50,11 +63,17 @@ CONFIG_RT_USING_HEAP=y # Kernel Device Object # CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_ARM9=y # # RT-Thread Components @@ -62,6 +81,7 @@ CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y CONFIG_RT_MAIN_THREAD_STACK_SIZE=16384 +CONFIG_RT_MAIN_THREAD_PRIORITY=85 # # C++ features @@ -77,6 +97,7 @@ CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_CMD_SIZE=80 @@ -84,6 +105,7 @@ CONFIG_FINSH_CMD_SIZE=80 CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_USING_MSH_DEFAULT=y # CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system @@ -93,6 +115,7 @@ CONFIG_DFS_USING_WORKDIR=y CONFIG_DFS_FILESYSTEMS_MAX=9 CONFIG_DFS_FILESYSTEM_TYPES_MAX=9 CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_RT_USING_DFS_ELMFAT=y # @@ -111,8 +134,8 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 # CONFIG_RT_DFS_ELM_USE_ERASE is not set CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_NET is not set # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set CONFIG_RT_USING_DFS_JFFS2=y @@ -123,26 +146,47 @@ CONFIG_RT_NFS_HOST_EXPORT="192.168.10.82:/" # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_PWM=y CONFIG_RT_USING_MTD_NOR=y # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set # CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_W25QXX is not set -# CONFIG_RT_USING_GD is not set # CONFIG_RT_USING_ENC28J60 is not set # CONFIG_RT_USING_SPI_WIFI is not set CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -156,11 +200,24 @@ CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_PTHREADS=y +CONFIG_PTHREAD_NUM_MAX=8 # CONFIG_RT_USING_POSIX is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set # -# Network stack +# Network interface device # +# CONFIG_RT_USING_NETDEV is not set +CONFIG_NETDEV_USING_PING=y # # light weight TCP/IP stack @@ -168,7 +225,9 @@ CONFIG_RT_USING_PTHREADS=y CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP212 is not set # CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 CONFIG_RT_LWIP_IGMP=y CONFIG_RT_LWIP_ICMP=y # CONFIG_RT_LWIP_SNMP is not set @@ -185,7 +244,7 @@ CONFIG_RT_LWIP_GWADDR="192.168.1.1" CONFIG_RT_LWIP_MSKADDR="255.255.255.0" CONFIG_RT_LWIP_UDP=y CONFIG_RT_LWIP_TCP=y -# CONFIG_RT_LWIP_RAW is not set +CONFIG_RT_LWIP_RAW=y # CONFIG_RT_LWIP_PPP is not set CONFIG_RT_MEMP_NUM_NETCONN=64 CONFIG_RT_LWIP_PBUF_NUM=16 @@ -198,28 +257,34 @@ CONFIG_RT_LWIP_TCP_WND=11680 CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=100 CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=32 CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=32768 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=126 CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=32 CONFIG_RT_LWIP_REASSEMBLY_FRAG=y CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 CONFIG_SO_REUSE=1 CONFIG_LWIP_SO_RCVTIMEO=1 CONFIG_LWIP_SO_SNDTIMEO=1 CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 # CONFIG_RT_LWIP_NETIF_LOOPBACK is not set CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set # -# Modbus master and slave stack +# AT commands # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_AT is not set CONFIG_LWIP_USING_DHCPD=y - -# -# RT-Thread UI Engine -# -# CONFIG_RT_USING_GUIENGINE is not set +CONFIG_DHCPD_SERVER_IP="192.168.169.1" +CONFIG_DHCPD_USING_ROUTER=y +# CONFIG_LWIP_USING_CUSTOMER_DNS_SERVER is not set # # VBUS(Virtual Software BUS) @@ -229,32 +294,35 @@ CONFIG_LWIP_USING_DHCPD=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages # -# -# system packages -# -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set - # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set # # Wi-Fi @@ -269,8 +337,49 @@ CONFIG_LWIP_USING_DHCPD=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -278,10 +387,13 @@ CONFIG_LWIP_USING_DHCPD=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages # +# CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set @@ -289,26 +401,195 @@ CONFIG_LWIP_USING_DHCPD=y # multimedia packages # # CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_IPERF is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # -# miscellaneous packages +# system packages # -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # -# example package: hello +# miscellaneous packages # +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set - +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_MDNS is not set +# CONFIG_PKG_USING_UPNP is not set +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +CONFIG_SOC_GK710=y # CONFIG_SOC_GK7101 is not set # CONFIG_SOC_GK7102 is not set # CONFIG_SOC_GK7101S is not set @@ -325,14 +606,11 @@ CONFIG_TUNNING_TOOL_SUPPORT=y CONFIG_RT_USING_DMA_MEM=y CONFIG_ARM1176_USE_VFP=y CONFIG_RT_USING_VFP=y -CONFIG_RT_USING_CPU_FFS=y # # Goke Peripheral Device Config # -CONFIG_RT_USING_ADC=y CONFIG_RT_USING_GMAC=y -CONFIG_RT_USING_PWM=y CONFIG_RT_USING_GK_DMA=y CONFIG_RT_USING_LIBZ=y CONFIG_RT_USING_LOGCAPTURE=y diff --git a/bsp/gkipc/Kconfig b/bsp/gkipc/Kconfig index e49a4af73e41e6c3bea2caf3a54f604b3b3fbaf1..5e38d05fbc8c4358671d97be4a99ed314e7ea03c 100644 --- a/bsp/gkipc/Kconfig +++ b/bsp/gkipc/Kconfig @@ -20,8 +20,10 @@ source "$PKGS_DIR/Kconfig" config SOC_GK710 bool + select ARCH_ARM_ARM9 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y choice diff --git a/bsp/gkipc/armv6/rtos_lib.c b/bsp/gkipc/armv6/rtos_lib.c index 7d7aec5c51d24a2e05dec33a95357ed8bdbed858..4d0a75a10d8e15f69a5048cbf5d2ba610b3d5934 100644 --- a/bsp/gkipc/armv6/rtos_lib.c +++ b/bsp/gkipc/armv6/rtos_lib.c @@ -524,7 +524,7 @@ void RTOS_SetErrno(const int err) } int RTOS_GetErrno() { - int err; + int err = 0; #if 0 rt_base_t level; level = rt_hw_interrupt_disable(); @@ -663,7 +663,7 @@ U32 msleep( U32 msecs ) U32 RTOS_SuspendThread( RTOS_ThreadT threadHandle ) { - return rt_thread_suspend((rt_thread_t)threadHandle); + return rt_thread_suspend_witch_flag((rt_thread_t)threadHandle, RT_UNINTERRUPTIBLE); } U32 RTOS_WakeupThread( RTOS_ThreadT threadHandle ) @@ -720,7 +720,7 @@ void thread_statistics() rt_kprintf("%-32.*s %3d", RT_NAME_MAX, thread->name, priority); #endif if (thread->stat == RT_THREAD_READY) rt_kprintf(" ready"); - else if (thread->stat == RT_THREAD_SUSPEND) rt_kprintf(" suspend"); + else if ((thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) rt_kprintf(" suspend"); else if (thread->stat == RT_THREAD_INIT) rt_kprintf(" init"); else if (thread->stat == RT_THREAD_CLOSE) rt_kprintf(" close"); diff --git a/bsp/gkipc/armv6/trap.c b/bsp/gkipc/armv6/trap.c index 602badff39211dea78e9e235a9c2e20486875f64..f3ed43ab13bd1b790fe10b2bbd9799ab57cd8e16 100644 --- a/bsp/gkipc/armv6/trap.c +++ b/bsp/gkipc/armv6/trap.c @@ -88,7 +88,7 @@ static void _rtt_statistics() rt_kprintf("%-32.*s %03d", RT_NAME_MAX, thread->name, priority); #endif if (thread->stat == RT_THREAD_READY) rt_kprintf(" ready "); - else if (thread->stat == RT_THREAD_SUSPEND) rt_kprintf(" suspend"); + else if ((thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) rt_kprintf(" suspend"); else if (thread->stat == RT_THREAD_INIT) rt_kprintf(" init "); else if (thread->stat == RT_THREAD_CLOSE) rt_kprintf(" close "); diff --git a/bsp/gkipc/rtconfig.h b/bsp/gkipc/rtconfig.h index 82262adfd540740a7306e9f3e49ac4568d7704e5..4ce66e9820d6945073b89a4ac757f61b6076e1fb 100644 --- a/bsp/gkipc/rtconfig.h +++ b/bsp/gkipc/rtconfig.h @@ -8,21 +8,19 @@ #define RT_NAME_MAX 32 #define RT_ALIGN_SIZE 4 -/* RT_THREAD_PRIORITY_8 is not set */ -/* RT_THREAD_PRIORITY_32 is not set */ #define RT_THREAD_PRIORITY_256 #define RT_THREAD_PRIORITY_MAX 256 #define RT_TICK_PER_SECOND 100 -#define RT_DEBUG -#define RT_DEBUG_COLOR #define RT_USING_OVERFLOW_CHECK -#define RT_DEBUG_INIT 0 -#define RT_DEBUG_THREAD 0 #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 1024 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 10240 +#define RT_DEBUG +#define RT_DEBUG_COLOR /* Inter-Thread communication */ @@ -31,17 +29,11 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ -/* RT_USING_MEMPOOL is not set */ #define RT_USING_MEMHEAP -/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ -/* RT_USING_MEMHEAP_AS_HEAP is not set */ -/* RT_USING_MEMTRACE is not set */ #define RT_USING_HEAP /* Kernel Device Object */ @@ -51,13 +43,18 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -/* RT_USING_MODULE is not set */ +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_ARM9 /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 16384 +#define RT_MAIN_THREAD_PRIORITY 85 /* C++ features */ @@ -74,10 +71,9 @@ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT -/* FINSH_USING_MSH_ONLY is not set */ +#define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -93,20 +89,12 @@ #define RT_DFS_ELM_CODE_PAGE 437 #define RT_DFS_ELM_WORD_ACCESS #define RT_DFS_ELM_USE_LFN_0 -/* RT_DFS_ELM_USE_LFN_1 is not set */ -/* RT_DFS_ELM_USE_LFN_2 is not set */ -/* RT_DFS_ELM_USE_LFN_3 is not set */ #define RT_DFS_ELM_USE_LFN 0 #define RT_DFS_ELM_MAX_LFN 255 #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 -/* RT_DFS_ELM_USE_ERASE is not set */ #define RT_DFS_ELM_REENTRANT #define RT_USING_DFS_DEVFS -/* RT_USING_DFS_NET is not set */ -/* RT_USING_DFS_ROMFS is not set */ -/* RT_USING_DFS_RAMFS is not set */ -/* RT_USING_DFS_UFFS is not set */ #define RT_USING_DFS_JFFS2 #define RT_USING_DFS_NFS #define RT_NFS_HOST_EXPORT "192.168.10.82:/" @@ -114,50 +102,50 @@ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_CPUTIME is not set */ +#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN +#define RT_USING_ADC +#define RT_USING_PWM #define RT_USING_MTD_NOR -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_RTC is not set */ #define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI -/* RT_USING_SPI_MSD is not set */ -/* RT_USING_SFUD is not set */ -/* RT_USING_W25QXX is not set */ -/* RT_USING_GD is not set */ -/* RT_USING_ENC28J60 is not set */ -/* RT_USING_SPI_WIFI is not set */ #define RT_USING_WDT -/* RT_USING_WIFI is not set */ /* Using USB */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ #define RT_USING_LIBC #define RT_USING_PTHREADS -/* RT_USING_POSIX is not set */ +#define PTHREAD_NUM_MAX 8 -/* Network stack */ +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + +#define NETDEV_USING_PING /* light weight TCP/IP stack */ #define RT_USING_LWIP -/* RT_USING_LWIP141 is not set */ #define RT_USING_LWIP202 -/* RT_USING_LWIP_IPV6 is not set */ +#define RT_LWIP_MEM_ALIGNMENT 4 #define RT_LWIP_IGMP #define RT_LWIP_ICMP -/* RT_LWIP_SNMP is not set */ #define RT_LWIP_DNS #define RT_LWIP_DHCP #define IP_SOF_BROADCAST 1 @@ -170,8 +158,7 @@ #define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP #define RT_LWIP_TCP -/* RT_LWIP_RAW is not set */ -/* RT_LWIP_PPP is not set */ +#define RT_LWIP_RAW #define RT_MEMP_NUM_NETCONN 64 #define RT_LWIP_PBUF_NUM 16 #define RT_LWIP_RAW_PCB_NUM 10 @@ -188,139 +175,84 @@ #define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 #define RT_LWIP_REASSEMBLY_FRAG #define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 #define SO_REUSE 1 #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 -/* RT_LWIP_NETIF_LOOPBACK is not set */ +#define LWIP_SO_LINGER 0 #define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING -/* Modbus master and slave stack */ +/* AT commands */ -/* RT_USING_MODBUS is not set */ #define LWIP_USING_DHCPD -/* RT_USING_NETUTILS is not set */ - -/* RT-Thread UI Engine */ - -/* RT_USING_GUIENGINE is not set */ +#define DHCPD_SERVER_IP "192.168.169.1" +#define DHCPD_USING_ROUTER /* VBUS(Virtual Software BUS) */ -/* RT_USING_VBUS is not set */ /* Utilities */ -/* RT_USING_LOGTRACE is not set */ -/* RT_USING_RYM is not set */ /* RT-Thread online packages */ -/* system packages */ - -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_SQLITE is not set */ -/* PKG_USING_RTI is not set */ - /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_LJSON is not set */ -/* PKG_USING_EZXML is not set */ -/* PKG_USING_NANOPB is not set */ -/* PKG_USING_GAGENT_CLOUD is not set */ /* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ -/* PKG_USING_WLAN_WICED is not set */ -/* PKG_USING_COAP is not set */ -/* PKG_USING_NOPOLL is not set */ + +/* IoT Cloud */ + /* security packages */ -/* PKG_USING_MBEDTLS is not set */ -/* PKG_USING_libsodium is not set */ -/* PKG_USING_TINYCRYPT is not set */ /* language packages */ -/* PKG_USING_JERRYSCRIPT is not set */ -/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ -/* PKG_USING_OPENMV is not set */ /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYLOGGER is not set */ -/* PKG_USING_SYSTEMVIEW is not set */ -/* PKG_USING_IPERF is not set */ -/* miscellaneous packages */ +/* system packages */ -/* PKG_USING_FASTLZ is not set */ -/* PKG_USING_MINILZO is not set */ -/* example package: hello */ +/* peripheral libraries and drivers */ -/* PKG_USING_HELLO is not set */ -/* Privated Packages of RealThread */ +/* miscellaneous packages */ -/* PKG_USING_CODEC is not set */ -/* PKG_USING_PLAYER is not set */ -/* PKG_USING_PERSIMMON_SRC is not set */ -/* Network Utilities */ +/* samples: kernel and components samples */ -/* PKG_USING_MDNS is not set */ -/* PKG_USING_UPNP is not set */ -/* PKG_USING_WLAN_WICED_SRC is not set */ -/* Cloudsdk: RT_thread IOT Cloudsdk */ +/* Privated Packages of RealThread */ -/* PKG_USING_CLOUDSDK is not set */ -/* Webnet: A web server package for rt-thread */ +/* Network Utilities */ -/* PKG_USING_WEBNET is not set */ -/* PKG_USING_COREMARK is not set */ -/* PKG_USING_POWER_MANAGER is not set */ -/* SOC_GK7101 is not set */ -/* SOC_GK7102 is not set */ -/* SOC_GK7101S is not set */ -/* SOC_GK7102S is not set */ +#define SOC_GK710 #define SOC_GK7102C #define BOARD_GK7102C_EVB #define SENSOR_TYPE_SC1135 -/* SENSOR_TYPE_SC1145 is not set */ -/* SENSOR_TYPE_JXH65 is not set */ -/* SENSOR_TYPE_OV9750 is not set */ -/* SENSOR_TYPE_AR0130 is not set */ -/* SENSOR_TYPE_JXH42 is not set */ #define TUNNING_TOOL_SUPPORT #define RT_USING_DMA_MEM #define ARM1176_USE_VFP #define RT_USING_VFP -#define RT_USING_CPU_FFS /* Goke Peripheral Device Config */ -#define RT_USING_ADC #define RT_USING_GMAC -#define RT_USING_PWM #define RT_USING_GK_DMA #define RT_USING_LIBZ #define RT_USING_LOGCAPTURE diff --git a/bsp/imx6sx/cortex-a9/.config b/bsp/imx6sx/cortex-a9/.config index 937db81a3cbf3ca075f46d2c191f5a6de2a83c19..0384fea7986888c09d24205f8f06212255f8d0c9 100644 --- a/bsp/imx6sx/cortex-a9/.config +++ b/bsp/imx6sx/cortex-a9/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -64,9 +65,15 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +# CONFIG_RT_IOREMAP_LATE is not set +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_ARCH_ARM_CORTEX_A9=y +# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set # # RT-Thread Components @@ -112,6 +119,7 @@ CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_ELMFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set @@ -132,12 +140,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -146,15 +155,9 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set - -# -# Using Hardware Crypto drivers -# # CONFIG_RT_USING_HWCRYPTO is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -171,6 +174,7 @@ CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set @@ -209,8 +213,9 @@ CONFIG_NETDEV_IPV6=0 CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y -# CONFIG_RT_USING_LWIP210 is not set +# CONFIG_RT_USING_LWIP212 is not set # CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 CONFIG_RT_LWIP_IGMP=y CONFIG_RT_LWIP_ICMP=y # CONFIG_RT_LWIP_SNMP is not set @@ -252,6 +257,7 @@ CONFIG_SO_REUSE=1 CONFIG_LWIP_SO_RCVTIMEO=1 CONFIG_LWIP_SO_SNDTIMEO=1 CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 # CONFIG_RT_LWIP_NETIF_LOOPBACK is not set CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_RT_LWIP_STATS is not set @@ -259,11 +265,6 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 CONFIG_RT_LWIP_USING_PING=y # CONFIG_RT_LWIP_DEBUG is not set -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set - # # AT commands # @@ -281,6 +282,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -289,14 +291,20 @@ CONFIG_RT_LWIP_USING_PING=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -318,6 +326,8 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -329,13 +339,32 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set # CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -343,6 +372,8 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -357,6 +388,9 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -369,16 +403,27 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages # # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -386,6 +431,16 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -393,6 +448,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -401,10 +457,16 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -412,6 +474,27 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -422,12 +505,15 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -439,4 +525,54 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_MDNS is not set +# CONFIG_PKG_USING_UPNP is not set +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +CONFIG_SOC_MCIMX6X4=y CONFIG_RT_USING_UART1=y diff --git a/bsp/imx6sx/cortex-a9/Kconfig b/bsp/imx6sx/cortex-a9/Kconfig index 0898ab8dd65d7ef6cb1acf2470e077e3b304db95..16ad23cf48cef3a2143902ec0d8d7ecb647b20c7 100644 --- a/bsp/imx6sx/cortex-a9/Kconfig +++ b/bsp/imx6sx/cortex-a9/Kconfig @@ -28,8 +28,10 @@ source "$PKGS_DIR/Kconfig" config SOC_MCIMX6X4 bool + select ARCH_ARM_CORTEX_A9 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y config RT_USING_UART1 diff --git a/bsp/imx6sx/cortex-a9/rtconfig.h b/bsp/imx6sx/cortex-a9/rtconfig.h index ce8ed7880c4a1c552ad0e1050d372ac02efd6a64..b122d915cf3eaa6009b72ec39576c841e4c2d7f1 100644 --- a/bsp/imx6sx/cortex-a9/rtconfig.h +++ b/bsp/imx6sx/cortex-a9/rtconfig.h @@ -39,7 +39,11 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define ARCH_ARM +#define ARCH_ARM_CORTEX_A +#define ARCH_ARM_CORTEX_A9 /* RT-Thread Components */ @@ -87,12 +91,6 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* Using Hardware Crypto drivers */ - - -/* Using WiFi */ - - /* Using USB */ @@ -126,6 +124,7 @@ #define RT_USING_LWIP #define RT_USING_LWIP202 +#define RT_LWIP_MEM_ALIGNMENT 4 #define RT_LWIP_IGMP #define RT_LWIP_ICMP #define RT_LWIP_DNS @@ -161,12 +160,10 @@ #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 #define LWIP_NETIF_LOOPBACK 0 #define RT_LWIP_USING_PING -/* Modbus master and slave stack */ - - /* AT commands */ @@ -215,6 +212,13 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + +#define SOC_MCIMX6X4 #define RT_USING_UART1 #endif diff --git a/bsp/imx6ul/.config b/bsp/imx6ul/.config index 0068adc43f4cbe6540bcc462d279f1b2326e88ff..15489551c1c0058fc44a5e109c8503532956e4c8 100644 --- a/bsp/imx6ul/.config +++ b/bsp/imx6ul/.config @@ -9,6 +9,7 @@ CONFIG_BOARD_IMX6UL=y # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -64,13 +65,16 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" -CONFIG_RT_VER_NUM=0x40002 -CONFIG_ARCH_ARM=y +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_USING_CACHE=y # CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_A=y CONFIG_ARCH_ARM_CORTEX_A7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_ARCH_ARM_SECURE_MODE is not set +# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set # # RT-Thread Components @@ -87,6 +91,8 @@ CONFIG_RT_USING_COMPONENTS_INIT=y # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 @@ -97,9 +103,6 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # @@ -114,6 +117,7 @@ CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_ELMFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set @@ -122,17 +126,25 @@ CONFIG_RT_USING_DFS_DEVFS=y # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -162,8 +174,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_CLOCKTIME is not set # CONFIG_RT_USING_MODULE is not set # @@ -201,6 +214,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_LWP is not set # @@ -210,10 +224,15 @@ CONFIG_RT_USING_POSIX=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -240,9 +259,12 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set # # IoT Cloud @@ -251,8 +273,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -261,15 +285,41 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set # # security packages # # CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_LIBSODIUM is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -277,15 +327,46 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set # # multimedia packages # + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set # # tools packages @@ -294,29 +375,109 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set # # system packages # + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_RT_USING_ARDUINO is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_USB_STACK is not set # # peripheral libraries and drivers @@ -324,18 +485,24 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -343,40 +510,122 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set # CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages # + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set + +# +# Platform Driver Configuration +# + +# +# Select UART Driver +# +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set CONFIG_SOC_MCIMX6X4=y diff --git a/bsp/imx6ul/Kconfig b/bsp/imx6ul/Kconfig index 9fbc95e841fd513578cc4a85d8c3d0e6d38834f4..06b830af268feadb0522840595bf076da55c1583 100644 --- a/bsp/imx6ul/Kconfig +++ b/bsp/imx6ul/Kconfig @@ -18,6 +18,7 @@ config PKGS_DIR config BOARD_IMX6UL bool select ARCH_ARM_CORTEX_A7 + select RT_USING_CACHE default y source "$RTT_DIR/Kconfig" diff --git a/bsp/imx6ul/drivers/Kconfig b/bsp/imx6ul/drivers/Kconfig index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..8c764984cbfeb2eb39fb622e47734aa99d546009 100644 --- a/bsp/imx6ul/drivers/Kconfig +++ b/bsp/imx6ul/drivers/Kconfig @@ -0,0 +1,14 @@ +menu "Platform Driver Configuration" + +menu "Select UART Driver" + if RT_USING_SERIAL + config BSP_USING_UART1 + bool "Enable UART1" + default y + config BSP_USING_UART2 + bool "Enable UART2" + default n + endif +endmenu + +endmenu diff --git a/bsp/imx6ul/drivers/serial.c b/bsp/imx6ul/drivers/serial.c index 0f6943cfbd6e58423b194c6ad61f81644d1f4250..cd237bed427bfb50360002b7f58f9757a21218bd 100644 --- a/bsp/imx6ul/drivers/serial.c +++ b/bsp/imx6ul/drivers/serial.c @@ -12,7 +12,6 @@ #include #include - #include "serial.h" struct hw_uart_device @@ -120,19 +119,10 @@ static const struct rt_uart_ops _uart_ops = uart_control, uart_putc, uart_getc, + RT_NULL /* no DMA */ }; -#ifdef RT_USING_UART0 -/* UART device driver structure */ -static struct hw_uart_device _uart0_device = -{ - HW_UART0, - IMX_INT_UART0 -}; -static struct rt_serial_device _serial0; -#endif - -#ifdef RT_USING_UART1 +#ifdef BSP_USING_UART1 /* UART1 device driver structure */ static struct hw_uart_device _uart1_device = { @@ -142,6 +132,16 @@ static struct hw_uart_device _uart1_device = static struct rt_serial_device _serial1; #endif +#ifdef BSP_USING_UART2 +/* UART2 device driver structure */ +static struct hw_uart_device _uart2_device = +{ + HW_UART2, + IMX_INT_UART2 +}; +static struct rt_serial_device _serial2; +#endif + int rt_hw_uart_init(void) { struct hw_uart_device *uart; @@ -155,25 +155,25 @@ int rt_hw_uart_init(void) config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; -#ifdef RT_USING_UART0 - uart = &_uart0_device; +#ifdef BSP_USING_UART1 + uart = &_uart1_device; - _serial0.ops = &_uart_ops; - _serial0.config = config; + _serial1.ops = &_uart_ops; + _serial1.config = config; /* register UART1 device */ - rt_hw_serial_register(&_serial0, "uart0", + rt_hw_serial_register(&_serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif -#ifdef RT_USING_UART1 - uart = &_uart1_device; - _serial1.ops = &_uart_ops; - _serial1.config = config; +#ifdef BSP_USING_UART2 + uart = &_uart2_device; + _serial2.ops = &_uart_ops; + _serial2.config = config; /* register UART1 device */ - rt_hw_serial_register(&_serial1, "uart1", + rt_hw_serial_register(&_serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif diff --git a/bsp/imx6ul/imx6.lds b/bsp/imx6ul/imx6.lds index a889774f852ef0d15923d9f3e605ec85c2925857..4beeb3770e82da47d168aebc335c936b62cd6838 100644 --- a/bsp/imx6ul/imx6.lds +++ b/bsp/imx6ul/imx6.lds @@ -37,6 +37,13 @@ SECTIONS } =0 __text_end = .; + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + __rodata_start = .; .rodata : { *(.rodata) *(.rodata.*) } __rodata_end = .; diff --git a/bsp/imx6ul/rtconfig.h b/bsp/imx6ul/rtconfig.h index 19826089e27988e8645cefa70540b24bae14f7e1..20900ec5fd473dc7ffb72f5e81ec07cd23db9419 100644 --- a/bsp/imx6ul/rtconfig.h +++ b/bsp/imx6ul/rtconfig.h @@ -9,12 +9,8 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 -/* RT_USING_ARCH_DATA_TYPE is not set */ -/* RT_USING_SMP is not set */ #define RT_ALIGN_SIZE 4 -/* RT_THREAD_PRIORITY_8 is not set */ #define RT_THREAD_PRIORITY_32 -/* RT_THREAD_PRIORITY_256 is not set */ #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK @@ -22,19 +18,7 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 -/* RT_USING_TIMER_SOFT is not set */ #define RT_DEBUG -/* RT_DEBUG_COLOR is not set */ -/* RT_DEBUG_INIT_CONFIG is not set */ -/* RT_DEBUG_THREAD_CONFIG is not set */ -/* RT_DEBUG_SCHEDULER_CONFIG is not set */ -/* RT_DEBUG_IPC_CONFIG is not set */ -/* RT_DEBUG_TIMER_CONFIG is not set */ -/* RT_DEBUG_IRQ_CONFIG is not set */ -/* RT_DEBUG_MEM_CONFIG is not set */ -/* RT_DEBUG_SLAB_CONFIG is not set */ -/* RT_DEBUG_MEMHEAP_CONFIG is not set */ -/* RT_DEBUG_MODULE_CONFIG is not set */ /* Inter-Thread communication */ @@ -43,58 +27,45 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ #define RT_USING_MEMPOOL -/* RT_USING_MEMHEAP is not set */ -/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ -/* RT_USING_MEMTRACE is not set */ #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE -/* RT_USING_DEVICE_OPS is not set */ -/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart" -#define RT_VER_NUM 0x40002 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50000 +#define RT_USING_CACHE #define ARCH_ARM -/* RT_USING_CPU_FFS is not set */ #define ARCH_ARM_CORTEX_A #define ARCH_ARM_CORTEX_A7 -/* ARCH_CPU_STACK_GROWS_UPWARD is not set */ /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT -/* RT_USING_USER_MAIN is not set */ /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION -/* FINSH_ECHO_DISABLE_DEFAULT is not set */ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -/* FINSH_USING_MSH_ONLY is not set */ #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -104,248 +75,116 @@ #define DFS_FILESYSTEMS_MAX 2 #define DFS_FILESYSTEM_TYPES_MAX 2 #define DFS_FD_MAX 16 -/* RT_USING_DFS_MNTTABLE is not set */ -/* RT_USING_DFS_ELMFAT is not set */ #define RT_USING_DFS_DEVFS -/* RT_USING_DFS_ROMFS is not set */ -/* RT_USING_DFS_RAMFS is not set */ -/* RT_USING_DFS_UFFS is not set */ -/* RT_USING_DFS_JFFS2 is not set */ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 #define RT_PIPE_BUFSZ 512 -/* RT_USING_SYSTEM_WORKQUEUE is not set */ #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_CPUTIME is not set */ -/* RT_USING_I2C is not set */ +#define RT_USING_TTY #define RT_USING_PIN -/* RT_USING_ADC is not set */ -/* RT_USING_PWM is not set */ -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_PM is not set */ -/* RT_USING_RTC is not set */ -/* RT_USING_SDIO is not set */ -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_AUDIO is not set */ -/* RT_USING_SENSOR is not set */ -/* RT_USING_TOUCH is not set */ -/* RT_USING_HWCRYPTO is not set */ -/* RT_USING_PULSE_ENCODER is not set */ -/* RT_USING_INPUT_CAPTURE is not set */ -/* RT_USING_WIFI is not set */ /* Using USB */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ #define RT_USING_LIBC -/* RT_USING_PTHREADS is not set */ #define RT_USING_POSIX -/* RT_USING_POSIX_MMAP is not set */ -/* RT_USING_POSIX_TERMIOS is not set */ -/* RT_USING_POSIX_AIO is not set */ -/* RT_USING_MODULE is not set */ /* Network */ /* Socket abstraction layer */ -/* RT_USING_SAL is not set */ /* Network interface device */ -/* RT_USING_NETDEV is not set */ /* light weight TCP/IP stack */ -/* RT_USING_LWIP is not set */ /* AT commands */ -/* RT_USING_AT is not set */ /* VBUS(Virtual Software BUS) */ -/* RT_USING_VBUS is not set */ /* Utilities */ -/* RT_USING_RYM is not set */ -/* RT_USING_ULOG is not set */ -/* RT_USING_UTEST is not set */ -/* RT_USING_LWP is not set */ /* RT-Thread online packages */ /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_WEBNET is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_JSMN is not set */ -/* PKG_USING_LIBMODBUS is not set */ -/* PKG_USING_FREEMODBUS is not set */ -/* PKG_USING_LJSON is not set */ -/* PKG_USING_EZXML is not set */ -/* PKG_USING_NANOPB is not set */ /* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ -/* PKG_USING_WLAN_WICED is not set */ -/* PKG_USING_RW007 is not set */ -/* PKG_USING_COAP is not set */ -/* PKG_USING_NOPOLL is not set */ -/* PKG_USING_NETUTILS is not set */ -/* PKG_USING_AT_DEVICE is not set */ -/* PKG_USING_ATSRV_SOCKET is not set */ -/* PKG_USING_WIZNET is not set */ /* IoT Cloud */ -/* PKG_USING_ONENET is not set */ -/* PKG_USING_GAGENT_CLOUD is not set */ -/* PKG_USING_ALI_IOTKIT is not set */ -/* PKG_USING_AZURE is not set */ -/* PKG_USING_TENCENT_IOTHUB is not set */ -/* PKG_USING_JIOT-C-SDK is not set */ -/* PKG_USING_NIMBLE is not set */ -/* PKG_USING_OTA_DOWNLOADER is not set */ -/* PKG_USING_IPMSG is not set */ -/* PKG_USING_LSSDP is not set */ -/* PKG_USING_AIRKISS_OPEN is not set */ -/* PKG_USING_LIBRWS is not set */ -/* PKG_USING_TCPSERVER is not set */ -/* PKG_USING_PROTOBUF_C is not set */ -/* PKG_USING_ONNX_PARSER is not set */ -/* PKG_USING_ONNX_BACKEND is not set */ /* security packages */ -/* PKG_USING_MBEDTLS is not set */ -/* PKG_USING_libsodium is not set */ -/* PKG_USING_TINYCRYPT is not set */ /* language packages */ -/* PKG_USING_LUA is not set */ -/* PKG_USING_JERRYSCRIPT is not set */ -/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ -/* PKG_USING_OPENMV is not set */ -/* PKG_USING_MUPDF is not set */ -/* PKG_USING_STEMWIN is not set */ -/* PKG_USING_WAVPLAYER is not set */ -/* PKG_USING_TJPGD is not set */ +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYFLASH is not set */ -/* PKG_USING_EASYLOGGER is not set */ -/* PKG_USING_SYSTEMVIEW is not set */ -/* PKG_USING_RDB is not set */ -/* PKG_USING_QRCODE is not set */ -/* PKG_USING_ULOG_EASYFLASH is not set */ -/* PKG_USING_ADBD is not set */ /* system packages */ -/* PKG_USING_GUIENGINE is not set */ -/* PKG_USING_PERSIMMON is not set */ -/* PKG_USING_CAIRO is not set */ -/* PKG_USING_PIXMAN is not set */ -/* PKG_USING_LWEXT4 is not set */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_FAL is not set */ -/* PKG_USING_SQLITE is not set */ -/* PKG_USING_RTI is not set */ -/* PKG_USING_LITTLEVGL2RTT is not set */ -/* PKG_USING_CMSIS is not set */ -/* PKG_USING_DFS_YAFFS is not set */ -/* PKG_USING_LITTLEFS is not set */ -/* PKG_USING_THREAD_POOL is not set */ -/* PKG_USING_ROBOTS is not set */ +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + /* peripheral libraries and drivers */ -/* PKG_USING_SENSORS_DRIVERS is not set */ -/* PKG_USING_REALTEK_AMEBA is not set */ -/* PKG_USING_SHT2X is not set */ -/* PKG_USING_STM32_SDIO is not set */ -/* PKG_USING_ICM20608 is not set */ -/* PKG_USING_U8G2 is not set */ -/* PKG_USING_BUTTON is not set */ -/* PKG_USING_PCF8574 is not set */ -/* PKG_USING_SX12XX is not set */ -/* PKG_USING_SIGNAL_LED is not set */ -/* PKG_USING_LEDBLINK is not set */ -/* PKG_USING_WM_LIBRARIES is not set */ -/* PKG_USING_KENDRYTE_SDK is not set */ -/* PKG_USING_INFRARED is not set */ -/* PKG_USING_ROSSERIAL is not set */ -/* PKG_USING_AT24CXX is not set */ -/* PKG_USING_MOTIONDRIVER2RTT is not set */ -/* PKG_USING_AD7746 is not set */ -/* PKG_USING_PCA9685 is not set */ -/* PKG_USING_I2C_TOOLS is not set */ -/* PKG_USING_NRF24L01 is not set */ -/* PKG_USING_TOUCH_DRIVERS is not set */ -/* PKG_USING_LCD_DRIVERS is not set */ -/* PKG_USING_MAX17048 is not set */ -/* miscellaneous packages */ +/* AI packages */ + -/* PKG_USING_LIBCSV is not set */ -/* PKG_USING_OPTPARSE is not set */ -/* PKG_USING_FASTLZ is not set */ -/* PKG_USING_MINILZO is not set */ -/* PKG_USING_QUICKLZ is not set */ -/* PKG_USING_MULTIBUTTON is not set */ -/* PKG_USING_FLEXIBLE_BUTTON is not set */ -/* PKG_USING_CANFESTIVAL is not set */ -/* PKG_USING_ZLIB is not set */ -/* PKG_USING_DSTR is not set */ -/* PKG_USING_TINYFRAME is not set */ -/* PKG_USING_KENDRYTE_DEMO is not set */ -/* PKG_USING_DIGITALCTRL is not set */ -/* PKG_USING_UPACKER is not set */ -/* PKG_USING_UPARAM is not set */ +/* miscellaneous packages */ /* samples: kernel and components samples */ -/* PKG_USING_KERNEL_SAMPLES is not set */ -/* PKG_USING_FILESYSTEM_SAMPLES is not set */ -/* PKG_USING_NETWORK_SAMPLES is not set */ -/* PKG_USING_PERIPHERAL_SAMPLES is not set */ -/* PKG_USING_HELLO is not set */ -/* PKG_USING_VI is not set */ -/* PKG_USING_NNOM is not set */ -/* PKG_USING_LIBANN is not set */ -/* PKG_USING_ELAPACK is not set */ -/* PKG_USING_ARMv7M_DWT is not set */ -/* PKG_USING_VT100 is not set */ + +/* entertainment: terminal games and other interesting software packages */ + + +/* Platform Driver Configuration */ + +/* Select UART Driver */ + +#define BSP_USING_UART1 #define SOC_MCIMX6X4 #endif diff --git a/bsp/imx6ull-100ask-smart/.config b/bsp/imx6ull-100ask-smart/.config new file mode 100644 index 0000000000000000000000000000000000000000..b2eea34b15f1d1748183415b4255674e10670d6f --- /dev/null +++ b/bsp/imx6ull-100ask-smart/.config @@ -0,0 +1,640 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_MEMTRACE=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +CONFIG_RT_USING_INTERRUPT_INFO=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0xc0000000 +CONFIG_PV_OFFSET=0xc0000000 +# CONFIG_RT_IOREMAP_LATE is not set +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_ARCH_ARM_CORTEX_A7=y +CONFIG_RT_BACKTRACE_FUNCTION_NAME=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=8 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +CONFIG_RT_USING_SOFT_RTC=y +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +CONFIG_RT_USING_SPI_MSD=y +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +CONFIG_RT_USING_POSIX_MMAP=y +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_GETLINE is not set +CONFIG_RT_USING_POSIX_AIO=y +CONFIG_RT_USING_POSIX_CLOCKTIME=y +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +CONFIG_SAL_USING_POSIX=y + +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +CONFIG_NETDEV_USING_IPV6=y +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=1 +# CONFIG_NETDEV_IPV6_SCOPES is not set + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP212 is not set +CONFIG_RT_USING_LWIP_IPV6=y +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +# CONFIG_RT_USING_GDBSERVER is not set +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_RT_LWP_SHM_MAX_NR=64 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +CONFIG_SOC_IMX6ULL=y +CONFIG_RT_USING_UART0=y +# CONFIG_RT_USING_UART1 is not set +CONFIG_BSP_DRV_EMAC=y diff --git a/bsp/imx6ull-100ask-smart/.cproject b/bsp/imx6ull-100ask-smart/.cproject new file mode 100644 index 0000000000000000000000000000000000000000..31c328ad90463d22ec9e1812ebf1f0cf7d6eac34 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/.cproject @@ -0,0 +1,175 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/imx6ull-100ask-smart/.gitignore b/bsp/imx6ull-100ask-smart/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..0ce2d51447d4e9a98b2429f171655766260f06be --- /dev/null +++ b/bsp/imx6ull-100ask-smart/.gitignore @@ -0,0 +1,45 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h +.settings +drivers/automac.h +romfs.c diff --git a/bsp/imx6ull-100ask-smart/.project b/bsp/imx6ull-100ask-smart/.project new file mode 100644 index 0000000000000000000000000000000000000000..e5f00228c02c65463748aa48f618aea3e02462a9 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/.project @@ -0,0 +1,54 @@ + + + qemu-vexpress-a9 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-2-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-2-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-2-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/bsp/imx6ull-100ask-smart/Kconfig b/bsp/imx6ull-100ask-smart/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..10c1d6bcabc95234b93048c7691d06fafd962fdf --- /dev/null +++ b/bsp/imx6ull-100ask-smart/Kconfig @@ -0,0 +1,30 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_IMX6ULL + bool + select ARCH_ARM_CORTEX_A7 + select RT_USING_CACHE + select ARCH_ARM_MMU + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/imx6ull-100ask-smart/README.md b/bsp/imx6ull-100ask-smart/README.md new file mode 100644 index 0000000000000000000000000000000000000000..9c025ec44368ef714914a12b423c120a64cc98a1 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/README.md @@ -0,0 +1,111 @@ +# IMX6ULL板级支持包说明 + +## 1. 简介 + +​ IMX6ULL rt-smart 系统由百问网韦东山老师移植提供，作为CortexA7单核800M主频处理器的开发环境，开发板由myir公司提供核心板，百问网公司设计底板外设等资源 是一套专门用于学习的开发板套件，其中开发板介绍可以参考页面 http://download.100ask.org/boards/Nxp/100ask_imx6ull_pro 。 + +* 当前IMX6ULL开发板对应的硬件特性： + +| 硬件 | 描述 | +| -- | -- | +| CPU主频 | CortexA7 800Mhz x1 | +| DDR | 512MB | +| Flash| 4GB Emmc| +| Ethernet | lan8720a，10M/100M | +| Usb | UsbHost x2 UsbOtg x1 | +| wifi&bluetooth | rtl8723bu | +| Audio | wm8960 | +| Display | RGB888 LCD x1 HDMI x1 | +| Can | x1 | +| RS485 | x1 | +| AP6216 module | x1 | +| ICM8235 module | x1 | +|GPIO prot | Several | + + +* 同时开发板有配套的编译移植教程，可以使用浏览器访问此连接进行观看学习 https://www.bilibili.com/video/BV1ti4y1w7VQ + + + +## 2. 编译说明 + +​ 使用浏览器参考此页面 https://www.rt-thread.org/document/site/rt-smart/rt-smart-quickstart/rt-smart-quickstart/ 参考官方编译说明文档下载并配置相应的环境。 + +### 2.1 下载ENV工具 + +​ 在Windows下请下载[env工具](https://www.rt-thread.org/page/download.html)。 + +### 2.2 下载工具链 + +请先下载对应的工具链并展开到`rtthread-smart/tools/gnu_gcc`目录： + +* [Windows环境](http://117.143.63.254:9012/www/rt-smart/install_arm-linux-musleabi_for_i686-w64-mingw32.zip) +* [Linux环境](http://117.143.63.254:9012/www/rt-smart/install_arm-linux-musleabi_for_x86_64-pc-linux-gnu.tar.bz2) + +目录参考如下： + +``` bash +rtthread-smart\tools\gnu_gcc\install_arm-linux-musleabi_for_i686-w64-mingw32 +``` + +下载env工具，运行`env.bat`进入命令行。 +然后切换到这个代码包根目录rtthread-smart，**运行smart-env.bat**，它会设置一定的环境变量，然后整体的smart开发环境就可以使用了。 + +```bash +> cd \workspace\rt-smart +> smart-env.bat +``` + +**注** + +此处运行smart-env.bat以设置环境，这步非常重要，它包括编译器设置。同时它也会设置工具链的前缀，可以在env终端下输入`set RTT_CC_PREFIX`命令看看返回结果是否生效： + +```bash +> set RTT_CC_PREFIX +RTT_CC_PREFIX=arm-linux-musleabi- +``` + + + +## 2.3 获取最新kernel源码并编译 + +​ 参考上述说明配置好编译环境后，我们需要获取最新支持 imx6ull开发板的kernel源码，进入rt-smart目录下,首先移除掉默认的kernel 再使用git命令获取最新的rt-smart kernel源码. + +``` +> mv kerenl kernel_bak +> git clone https://gitee.com/rtthread/rt-thread.git -b rt-smart kernel +``` + +​ 使用[env工具][2]，可以在console下进入到rt-smart源码 kernel/bsp/imx6ull目录中，运行以下编译命令： + + scons + +​ 来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin rtthread.imx文件。需要使用 百问网imx6ull烧写工具 http://wiki.100ask.org/100ask_imx6ull_tool 烧写更新 rtthread.imx 至imx6ull开发板。 + + + +## 3. 执行 + +​ 烧写方式请参考 https://www.bilibili.com/video/BV19A411s7f9?p=2 视频进行操作， + +​ 烧写成功后打开串口输出就可以看到如下启动打印信息了。 + +```text + \ | / +- RT - Thread Smart Operating System + / | \ 5.0.0 build Dec 22 2020 + 2006 - 2020 Copyright by rt-thread team +lwIP-2.0.2 initialized! +[I/sal.skt] Socket Abstraction Layer initialize success. +Dir /mnt mount failed! +hello rt-thread +msh /> + +``` + +## 4. 联系人信息 + +维护人：[weidongshan][2] + +[1]: http://infocenter.arm.com/help/index.jsp? +[2]: https://gitee.com/weidongshan diff --git a/bsp/imx6ull-100ask-smart/SConscript b/bsp/imx6ull-100ask-smart/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-100ask-smart/SConstruct b/bsp/imx6ull-100ask-smart/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..e1bc58f2c0b68d97bda381cde3e5456dcddcc7aa --- /dev/null +++ b/bsp/imx6ull-100ask-smart/SConstruct @@ -0,0 +1,33 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/imx6ull-100ask-smart/applications/SConscript b/bsp/imx6ull-100ask-smart/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..89083a964a159e254033baaa552061b3f03addb0 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/imx6ull-100ask-smart/applications/main.c b/bsp/imx6ull-100ask-smart/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..d939e28fef5bc12768f66ad59f2910429dfe96dc --- /dev/null +++ b/bsp/imx6ull-100ask-smart/applications/main.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/10/7 bernard the first version + */ +#include +#include +#include + +int main(void) +{ + printf("hello rt-smart\n"); + return 0; +} + diff --git a/bsp/imx6ull-100ask-smart/applications/mnt.c b/bsp/imx6ull-100ask-smart/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..88107618916d17aad6d80b6c9bad9329c7d92c36 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/applications/mnt.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #include + +#ifdef RT_USING_DFS +#include +#include + +int mnt_init(void) +{ + if (dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) != 0) + { + rt_kprintf("Dir / mount failed!\n"); + return -1; + } + + rt_thread_mdelay(200); + if (dfs_mount("sd0", "/mnt", "elm", 0, NULL) != 0) + { + rt_kprintf("Dir /mnt mount failed!\n"); + return -1; + } + + rt_kprintf("file system initialization done!\n"); + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif + diff --git a/bsp/imx6ull-100ask-smart/drivers/Kconfig b/bsp/imx6ull-100ask-smart/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..0eea26be5875e940d61186a0f699c4fede5255ab --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/Kconfig @@ -0,0 +1,11 @@ +config RT_USING_UART0 + bool "Enable UART0" + default n + +config RT_USING_UART1 + bool "Enable UART1" + default y + +config BSP_DRV_EMAC + bool "EMAC driver" + default y diff --git a/bsp/imx6ull-100ask-smart/drivers/SConscript b/bsp/imx6ull-100ask-smart/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..4f10c262171804689c151339a081c037df768460 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/SConscript @@ -0,0 +1,23 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +list = os.listdir(cwd) +CPPPATH = [cwd] +objs = [] + +if not GetDepend('BSP_DRV_EMAC'): + SrcRemove(src, ['drv_smc911x.c']) + +if not GetDepend('BSP_DRV_CLCD'): + SrcRemove(src, ['drv_clcd.c']) + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group + +Return('objs') diff --git a/bsp/imx6ull-100ask-smart/drivers/board.c b/bsp/imx6ull-100ask-smart/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..bdb41b7a958a540998c81a4f581bf9ec3145e742 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/board.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-11-20 Bernard the first version + * 2018-11-22 Jesven add rt_hw_spin_lock + * add rt_hw_spin_unlock + * add smp ipi init + */ + +#include +#include + +#include "board.h" +#include "drv_timer.h" + +#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +#ifdef RT_USING_USERSPACE +struct mem_desc platform_mem_desc[] = { /* 100ask_imx6ull ddr 512M */ + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x1FFFFFFF, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM} +}; +#else +struct mem_desc platform_mem_desc[] = { + {0x10000000, 0x50000000, 0x10000000, DEVICE_MEM}, + {0x60000000, 0x70000000, 0x60000000, NORMAL_MEM} +}; +#endif + +const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); + +#define SYS_CTRL __REG32(REALVIEW_SCTL_BASE) + +extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); + +void idle_wfi(void) +{ + asm volatile ("wfi"); +} + +/** + * This function will initialize board + */ + +rt_mmu_info mmu_info; + +extern size_t MMUTable[]; + +#ifdef RT_USING_USERSPACE +rt_region_t init_page_region = { + (uint32_t)PAGE_START, + (uint32_t)PAGE_END, +}; +#endif + +void rt_hw_board_init(void) +{ +#ifdef RT_USING_USERSPACE + rt_hw_mmu_map_init(&mmu_info, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); + + rt_page_init(init_page_region); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0xf0000000, 0x10000000); + + arch_kuser_init(&mmu_info, (void*)0xffff0000); +#else + rt_hw_mmu_map_init(&mmu_info, (void*)0x80000000, 0x10000000, MMUTable, 0); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0x80000000, 0x10000000); +#endif + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize system heap */ + rt_system_heap_init(HEAP_BEGIN, HEAP_END); + + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + rt_thread_idle_sethook(idle_wfi); + +#ifdef RT_USING_SMP + /* install IPI handle */ + rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler); +#endif +} diff --git a/bsp/imx6ull-100ask-smart/drivers/board.h b/bsp/imx6ull-100ask-smart/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..80636e41efe317c7303a3463aa4da957c0402655 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/board.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#include "imx6ul.h" +#include "mmu.h" + +#if defined(__CC_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) +#elif defined(__GNUC__) +extern int __bss_end; +#define HEAP_BEGIN ((void*)&__bss_end) +#endif + +#ifdef RT_USING_USERSPACE +#define HEAP_END (void*)(KERNEL_VADDR_START + 16 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END (void*)(KERNEL_VADDR_START + 128 * 1024 * 1024) +#else +#define HEAP_END (void*)(0x60000000 + 64 * 1024 * 1024) +#endif + +void rt_hw_board_init(void); + +extern rt_mmu_info mmu_info; + +#endif diff --git a/bsp/imx6ull-100ask-smart/drivers/drv_timer.c b/bsp/imx6ull-100ask-smart/drivers/drv_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..36330ac26d0e0bae672d5e5bb95e3b1cf6438b43 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/drv_timer.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#include +#include +#include + +#include "mmu.h" + +#define TICK_PERIOD (g_sys_freq / RT_TICK_PER_SECOND) +static int g_sys_freq; + +#define IRQ_SECURE_PHY_TIMER 29 /* Secure physical timer event */ +#define IRQ_NOSECURE_PHY_TIMER 30 /* No-Secure physical timer event */ + +#define IRQ_SYS_TICK IRQ_SECURE_PHY_TIMER + + +/* System Counter */ +struct sctr_regs { + rt_uint32_t cntcr; + rt_uint32_t cntsr; + rt_uint32_t cntcv1; + rt_uint32_t cntcv2; + rt_uint32_t resv1[4]; + rt_uint32_t cntfid0; + rt_uint32_t cntfid1; + rt_uint32_t cntfid2; + rt_uint32_t resv2[1001]; + rt_uint32_t counterid[1]; +}; + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + + +#define isb() __asm__ __volatile__ ("" : : : "memory") +#define dsb() __asm__ __volatile__ ("" : : : "memory") +#define dmb() __asm__ __volatile__ ("" : : : "memory") + + +static inline void enable_cntp(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c2, 1" :: "r"(cntv_ctl)); // write CNTP_CTL + isb(); +} + +static inline void disable_cntp(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 0; + asm volatile ("mcr p15, 0, %0, c14, c2, 1" :: "r"(cntv_ctl)); // write CNTP_CTL + isb(); +} + +static inline rt_uint32_t read_cntfrq(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val)); + return val; +} + +static inline void write_cntp_tval(rt_uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c14, c2, 0" :: "r"(val)); + isb(); + return; +} + +static inline void write_cntp_cval(rt_uint64_t val) +{ + asm volatile ("mcrr p15, 2, %Q0, %R0, c14" :: "r" (val)); + isb(); + return; +} + +static inline rt_uint64_t read_cntp_cval(void) +{ + rt_uint64_t val; + asm volatile ("mrrc p15, 2, %Q0, %R0, c14" : "=r" (val)); + return (val); +} + +volatile unsigned int *CCM_CLPCR; + +static void imx6ull_enable_clk_in_waitmode(void) +{ + CCM_CLPCR = rt_ioremap((void*)0x20C4054, 4); + *CCM_CLPCR &= ~((1 << 5) | 0x3); +} + +static void system_counter_clk_source_init(void) +{ + /* to do */ +} + +static void system_counter_init(void) +{ + /* enable system_counter */ +#define SCTR_BASE_ADDR 0x021DC000 +#define CONFIG_SC_TIMER_CLK 8000000 + + /* imx6ull, enable system counter */ + struct sctr_regs *sctr = (struct sctr_regs *)rt_ioremap((void*)SCTR_BASE_ADDR, sizeof(struct sctr_regs)); + unsigned long val, freq; + + freq = CONFIG_SC_TIMER_CLK; + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + sctr->cntfid0 = freq; + + /* Enable system counter */ + val = sctr->cntcr; + val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); + val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; + sctr->cntcr = val; + + imx6ull_enable_clk_in_waitmode(); +} + +static void arch_timer_init(void) +{ + g_sys_freq = read_cntfrq(); + + /* set timeout val */ + disable_cntp(); + write_cntp_tval(TICK_PERIOD); + + /* start timer */ + enable_cntp(); + + /* enable irq */ +} + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + + /* setup for next irq */ + /* clear interrupt */ + disable_cntp(); + write_cntp_cval(read_cntp_cval() + TICK_PERIOD); + enable_cntp(); +} + +int rt_hw_timer_init(void) +{ + /* Setup Timer for generating irq */ + /* enable timer */ + system_counter_clk_source_init(); + system_counter_init(); + arch_timer_init(); + + /* insall irq, enable irq */ + rt_hw_interrupt_install(IRQ_SYS_TICK, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_SYS_TICK); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); diff --git a/bsp/imx6ull-100ask-smart/drivers/drv_timer.h b/bsp/imx6ull-100ask-smart/drivers/drv_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..c50b073d36c9a0ed9ca72e164b459a5841d1b4b9 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/drv_timer.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#ifndef DRV_TIMER_H__ +#define DRV_TIMER_H__ + +void timer_init(int timer, unsigned int preload); +void timer_clear_pending(int timer); + +#endif diff --git a/bsp/imx6ull-100ask-smart/drivers/imx6ul.h b/bsp/imx6ull-100ask-smart/drivers/imx6ul.h new file mode 100644 index 0000000000000000000000000000000000000000..799298f56545be6304600f6c4922155a176dd08c --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/imx6ul.h @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-22 quanzhao first version + */ +#ifndef __IMX6UL_H__ +#define __IMX6UL_H__ + +#include +#include + +enum _gic_base_offsets +{ + kGICDBaseOffset = 0x1000, //!< GIC distributor offset. + kGICCBaseOffset = 0x2000 //!< GIC CPU interface offset. +}; + +/* SOC-relative definitions */ +enum _imx_interrupts +{ + SW_INTERRUPT_0 = 0, //!< Software interrupt 0. + SW_INTERRUPT_1 = 1, //!< Software interrupt 1. + SW_INTERRUPT_2 = 2, //!< Software interrupt 2. + SW_INTERRUPT_3 = 3, //!< Software interrupt 3. + SW_INTERRUPT_4 = 4, //!< Software interrupt 4. + SW_INTERRUPT_5 = 5, //!< Software interrupt 5. + SW_INTERRUPT_6 = 6, //!< Software interrupt 6. + SW_INTERRUPT_7 = 7, //!< Software interrupt 7. + SW_INTERRUPT_8 = 8, //!< Software interrupt 8. + SW_INTERRUPT_9 = 9, //!< Software interrupt 9. + SW_INTERRUPT_10 = 10, //!< Software interrupt 10. + SW_INTERRUPT_11 = 11, //!< Software interrupt 11. + SW_INTERRUPT_12 = 12, //!< Software interrupt 12. + SW_INTERRUPT_13 = 13, //!< Software interrupt 13. + SW_INTERRUPT_14 = 14, //!< Software interrupt 14. + SW_INTERRUPT_15 = 15, //!< Software interrupt 15. + RSVD_INTERRUPT_16 = 16, //!< Reserved. + RSVD_INTERRUPT_17 = 17, //!< Reserved. + RSVD_INTERRUPT_18 = 18, //!< Reserved. + RSVD_INTERRUPT_19 = 19, //!< Reserved. + RSVD_INTERRUPT_20 = 20, //!< Reserved. + RSVD_INTERRUPT_21 = 21, //!< Reserved. + RSVD_INTERRUPT_22 = 22, //!< Reserved. + RSVD_INTERRUPT_23 = 23, //!< Reserved. + RSVD_INTERRUPT_24 = 24, //!< Reserved. + RSVD_INTERRUPT_25 = 25, //!< Reserved. + RSVD_INTERRUPT_26 = 26, //!< Reserved. + RSVD_INTERRUPT_27 = 27, //!< Reserved. + RSVD_INTERRUPT_28 = 28, //!< Reserved. + RSVD_INTERRUPT_29 = 29, //!< Reserved. + RSVD_INTERRUPT_30 = 30, //!< Reserved. + RSVD_INTERRUPT_31 = 31, //!< Reserved. + IMX_INT_IOMUXC_GPR = 32, //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot. + IMX_INT_CHEETAH_CSYSPWRUPREQ = 33, //!< @todo Listed as DAP in RM + IMX_INT_SDMA = 34, //!< Logical OR of all 48 SDMA interrupt requests/events from all channels. + IMX_INT_TSC = 35, //!< TSC + IMX_INT_SNVS_LP_SET_PWR_OFF = 36, //!< PMIC power off request. + IMX_INT_LCDIF = 37, //!< LCDIF interrupt request. + IMX_INT_BEE = 38, //!< BEE interrupt request. + IMX_INT_CSI = 39, //!< CMOS Sensor Interface interrupt request. + IMX_INT_PXP = 40, //!< PXP interrupt request. + IMX_INT_SCTR1 = 41, //!< SCTR1 + IMX_INT_SCTR2 = 42, //!< SCTR2 + IMX_INT_WDOG3 = 43, //!< WDOG3 timer reset interrupt request. + IMX_INT_INTERRUPT_44 = 44, //!< Reserved. + IMX_INT_APBH_DMA = 45, //!< APBH DMA + IMX_INT_EIM = 46, //!< EIM interrupt request. + IMX_INT_NAND_BCH = 47, //!< Reserved. + IMX_INT_NAND_GPMI = 48, //!< Reserved. + IMX_INT_UART6 = 49, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_50 = 50, //!< Reserved. + IMX_INT_SNVS = 51, //!< SNVS consolidated interrupt. + IMX_INT_SNVS_SEC = 52, //!< SNVS security interrupt. + IMX_INT_CSU = 53, //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. + IMX_INT_USDHC1 = 54, //!< uSDHC1 (Enhanced SDHC) interrupt request. + IMX_INT_USDHC2 = 55, //!< uSDHC2 (Enhanced SDHC) interrupt request. + IMX_INT_SAI3 = 56, //!< uSDHC3 (Enhanced SDHC) interrupt request. + IMX_INT_SAI4 = 57, //!< uSDHC4 (Enhanced SDHC) interrupt request. + IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests. + IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests. + IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests. + IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests. + IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests. + IMX_INT_ECSPI1 = 63, //!< eCSPI1 interrupt request. + IMX_INT_ECSPI2 = 64, //!< eCSPI2 interrupt request. + IMX_INT_ECSPI3 = 65, //!< eCSPI3 interrupt request. + IMX_INT_ECSPI4 = 66, //!< eCSPI4 interrupt request. + IMX_INT_I2C4 = 67, //!< Reserved. + IMX_INT_I2C1 = 68, //!< I2C1 interrupt request. + IMX_INT_I2C2 = 69, //!< I2C2 interrupt request. + IMX_INT_I2C3 = 70, //!< I2C3 interrupt request. + IMX_INT_UART7 = 71, //!< Logical OR of UART5 interrupt requests. + IMX_INT_UART8 = 72, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_73 = 73, //!< Reserved. + IMX_INT_USB_OTG2 = 74, //!< USB Host 1 interrupt request. + IMX_INT_USB_OTG1 = 75, //!< USB OTG1 interrupt request. + IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request. + IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request. + IMX_INT_CAAM_JQ2 = 78, //!< SSI1 interrupt request. + IMX_INT_CAAM_ERR = 79, //!< SSI2 interrupt request. + IMX_INT_CAAM_RTIC = 80, //!< SSI3 interrupt request. + IMX_INT_TEMPERATURE = 81, //!< Temperature Sensor (temp. greater than threshold) interrupt request. + IMX_INT_ASRC = 82, //!< Reserved. + IMX_INT_INTERRUPT_83 = 83, //!< Reserved. + IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts. + IMX_INT_INTERRUPT_85 = 85, //!< Reserved. + IMX_INT_PMU_ANA_BO = 86, //!< PMU analog regulator brown-out interrupt request. + IMX_INT_GPT1 = 87, // + IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt. + IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt. + IMX_INT_GPIO1_INT7 = 90, //!< INT7 interrupt request. + IMX_INT_GPIO1_INT6 = 91, //!< INT6 interrupt request. + IMX_INT_GPIO1_INT5 = 92, //!< INT5 interrupt request. + IMX_INT_GPIO1_INT4 = 93, //!< INT4 interrupt request. + IMX_INT_GPIO1_INT3 = 94, //!< INT3 interrupt request. + IMX_INT_GPIO1_INT2 = 95, //!< INT2 interrupt request. + IMX_INT_GPIO1_INT1 = 96, //!< INT1 interrupt request. + IMX_INT_GPIO1_INT0 = 97, //!< INT0 interrupt request. + IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15. + IMX_INT_GPIO1_INT31_16 = 99, //!< Combined interrupt indication for GPIO1 signals 16 - 31. + IMX_INT_GPIO2_INT15_0 = 100, //!< Combined interrupt indication for GPIO2 signals 0 - 15. + IMX_INT_GPIO2_INT31_16 = 101, //!< Combined interrupt indication for GPIO2 signals 16 - 31. + IMX_INT_GPIO3_INT15_0 = 102, //!< Combined interrupt indication for GPIO3 signals 0 - 15. + IMX_INT_GPIO3_INT31_16 = 103, //!< Combined interrupt indication for GPIO3 signals 16 - 31. + IMX_INT_GPIO4_INT15_0 = 104, //!< Combined interrupt indication for GPIO4 signals 0 - 15. + IMX_INT_GPIO4_INT31_16 = 105, //!< Combined interrupt indication for GPIO4 signals 16 - 31. + IMX_INT_GPIO5_INT15_0 = 106, //!< Combined interrupt indication for GPIO5 signals 0 - 15. + IMX_INT_GPIO5_INT31_16 = 107, //!< Combined interrupt indication for GPIO5 signals 16 - 31. + IMX_INT_INTERRUPT_108 = 108, //!< Reserved. + IMX_INT_INTERRUPT_109 = 109, //!< Reserved. + IMX_INT_INTERRUPT_110 = 110, //!< Reserved. + IMX_INT_INTERRUPT_111 = 111, //!< Reserved. + IMX_INT_WDOG1 = 112, //!< WDOG1 timer reset interrupt request. + IMX_INT_WDOG2 = 113, //!< WDOG2 timer reset interrupt request. + IMX_INT_KPP = 114, //!< Key Pad interrupt request. + IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1. + IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2. + IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1. + IMX_INT_INTERRUPT_122 = 122, //!< Reserved. + IMX_INT_SRC = 123, //!< SRC interrupt request. + IMX_INT_INTERRUPT_124 = 124, //!< Logical OR of all L2 interrupt requests. + IMX_INT_INTERRUPT_125 = 125, //!< Parity Check error interrupt request. + IMX_INT_CHEETAH_PERFORM = 126, //!< Logical OR of Performance Unit interrupts. + IMX_INT_CHEETAH_TRIGGER = 127, //!< Logical OR of CTI trigger outputs. + IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC. + IMX_INT_SAI1 = 129, //!< EPDC interrupt request. + IMX_INT_SAI2 = 130, //!< EPDC interrupt request. + IMX_INT_INTERRUPT_131 = 131, //!< DCP general interrupt request. + IMX_INT_ADC1 = 132, //!< DCP channel 0 interrupt request. + IMX_INT_ADC2 = 133, //!< DCP secure interrupt request. + IMX_INT_INTERRUPT_134 = 134, //!< Reserved. + IMX_INT_INTERRUPT_135 = 135, //!< Reserved. + IMX_INT_SJC = 136, //!< SJC interrupt from General Purpose register. + IMX_INT_CAAM_0 = 137, //!< Reserved. + IMX_INT_CAAM_1 = 138, //!< Reserved. + IMX_INT_QSPI = 139, //!< Reserved. + IMX_INT_TZASC1 = 140, //!< ASC1 interrupt request. + IMX_INT_GPT2 = 141, //!< Reserved. + IMX_INT_CAN1 = 142, //!< Reserved. + IMX_INT_CAN2 = 143, //!< Reserved. + IMX_INT_SIM1 = 144, //!< Reserved. + IMX_INT_SIM2 = 145, //!< Reserved. + IMX_INT_PWM5 = 146, //!< Fast Ethernet Controller interrupt request. + IMX_INT_PWM6 = 147, //!< Reserved. + IMX_INT_PWM7 = 148, //!< Reserved. + IMX_INT_PWM8 = 149, //!< Reserved. + IMX_INT_ENET1 = 150, //!< Reserved. + IMX_INT_ENET1_TIMER = 151, //!< Reserved. + IMX_INT_ENET2 = 152, //!< Reserved. + IMX_INT_ENET2_TIMER = 153, //!< Reserved. + IMX_INT_INTERRUPT_154 = 154, //!< Reserved. + IMX_INT_INTERRUPT_155 = 155, //!< Reserved. + IMX_INT_INTERRUPT_156 = 156, //!< Reserved. + IMX_INT_INTERRUPT_157 = 157, //!< Reserved. + IMX_INT_INTERRUPT_158 = 158, //!< Reserved. + IMX_INT_PMU_DIG_BO = 159, //!< //!< PMU digital regulator brown-out interrupt request. + IMX_INTERRUPT_COUNT = 160 //!< Total number of interrupts. +}; + +/* the maximum number of gic */ +# define ARM_GIC_MAX_NR 1 + +/* the maximum number of interrupts */ +#define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT + +/* the maximum entries of the interrupt table */ +#define MAX_HANDLERS IMX_INTERRUPT_COUNT + +/* the basic constants needed by gic */ +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + rt_uint32_t gic_base; + asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base)); + return gic_base + kGICDBaseOffset; +} + +rt_inline rt_uint32_t platform_get_gic_cpu_base(void) +{ + rt_uint32_t gic_base; + asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base)); + return gic_base + kGICCBaseOffset; +} + +#define GIC_IRQ_START 0 + +#define GIC_ACK_INTID_MASK 0x000003ff + +/* the definition needed by gic.c */ +#define __REG32(x) (*((volatile unsigned int *)(x))) + +/* keep compatible with platform SDK */ +typedef enum { + CPU_0, + CPU_1, + CPU_2, + CPU_3, +} cpuid_e; + +enum _gicd_sgi_filter +{ + //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter. + kGicSgiFilter_UseTargetList = 0, + + //! Forward the interrupt to all CPU interfaces except that of the processor that requested + //! the interrupt. + kGicSgiFilter_AllOtherCPUs = 1, + + //! Forward the interrupt only to the CPU interface of the processor that requested the + //! interrupt. + kGicSgiFilter_OnlyThisCPU = 2 +}; + +typedef void (*irq_hdlr_t) (void); + +extern void rt_hw_interrupt_mask(int vector); +extern void rt_hw_interrupt_umask(int vector); +extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr) +{ + rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, RT_NULL, "unknown"); +} + +rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority) +{ + rt_hw_interrupt_umask(irq_id); +} + +rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id) +{ + rt_hw_interrupt_mask(irq_id); +} + +#endif /* __IMX6UL_H__ */ diff --git a/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h b/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..c79400888410a2901c45f01d0cd5fd39de3ba408 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/rt_lcd.h @@ -0,0 +1,59 @@ +#ifndef RT_LCD_H__ +#define RT_LCD_H__ + + +/* ioctls + 0x46 is 'F' */ +#define FBIOGET_VSCREENINFO 0x4600 +#define FBIOPUT_VSCREENINFO 0x4601 +#define FBIOGET_FSCREENINFO 0x4602 +#define FBIOGETCMAP 0x4604 +#define FBIOPUTCMAP 0x4605 +#define FBIOPAN_DISPLAY 0x4606 +#define FBIO_CURSOR 0x4608 +/* #define FBIOGET_MONITORSPEC 0x460C */ +/* #define FBIOPUT_MONITORSPEC 0x460D */ +/* #define FBIOSWITCH_MONIBIT 0x460E */ +#define FBIOGET_CON2FBMAP 0x460F +#define FBIOPUT_CON2FBMAP 0x4610 +#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ +#define FBIOGET_VBLANK 0x4612 +#define FBIO_ALLOC 0x4613 +#define FBIO_FREE 0x4614 +#define FBIOGET_GLYPH 0x4615 +#define FBIOGET_HWCINFO 0x4616 +#define FBIOPUT_MODEINFO 0x4617 +#define FBIOGET_DISPINFO 0x4618 +#define FBIO_WAITFORVSYNC 0x4620 + +struct fb_bitfield +{ + uint32_t offset; /* beginning of bitfield */ + uint32_t length; /* length of bitfield */ + uint32_t msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +struct fb_var_screeninfo +{ + uint32_t xres; + uint32_t yres; + + uint32_t bits_per_pixel; + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ +}; + +struct fb_fix_screeninfo +{ + char id[16]; + unsigned long smem_start; + uint32_t smem_len; + + uint32_t line_length; +}; + +#endif diff --git a/bsp/imx6ull-100ask-smart/drivers/serial.c b/bsp/imx6ull-100ask-smart/drivers/serial.c new file mode 100644 index 0000000000000000000000000000000000000000..1d1d5e5d77fa4c381bb5cccd995e2522be2dcd8b --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/serial.c @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#include +#include + +#include "serial.h" +#include "board.h" +#include "mmu.h" + +/*根据IMX6ULL芯片手册<<55.15 UART Memory Map/Register Definition>>的3608页，定义UART的结构体,*/ +typedef struct { + volatile unsigned int URXD; /**< UART Receiver Register, offset: 0x0 串口接收寄存器，偏移地址0x0 */ + unsigned char RESERVED_0[60]; + volatile unsigned int UTXD; /**< UART Transmitter Register, offset: 0x40 串口发送寄存器，偏移地址0x40*/ + unsigned char RESERVED_1[60]; + volatile unsigned int UCR1; /**< UART Control Register 1, offset: 0x80 串口控制寄存器1，偏移地址0x80*/ + volatile unsigned int UCR2; /**< UART Control Register 2, offset: 0x84 串口控制寄存器2，偏移地址0x84*/ + volatile unsigned int UCR3; /**< UART Control Register 3, offset: 0x88 串口控制寄存器3，偏移地址0x88*/ + volatile unsigned int UCR4; /**< UART Control Register 4, offset: 0x8C 串口控制寄存器4，偏移地址0x8C*/ + volatile unsigned int UFCR; /**< UART FIFO Control Register, offset: 0x90 串口FIFO控制寄存器，偏移地址0x90*/ + volatile unsigned int USR1; /**< UART Status Register 1, offset: 0x94 串口状态寄存器1，偏移地址0x94*/ +volatile unsigned int USR2; /**< UART Status Register 2, offset: 0x98 串口状态寄存器2，偏移地址0x98*/ + volatile unsigned int UESC; /**< UART Escape Character Register, offset: 0x9C 串口转义字符寄存器，偏移地址0x9C*/ + volatile unsigned int UTIM; /**< UART Escape Timer Register, offset: 0xA0 串口转义定时器寄存器 偏移地址0xA0*/ + volatile unsigned int UBIR; /**< UART BRM Incremental Register, offset: 0xA4 串口二进制倍率增加寄存器 偏移地址0xA4*/ + volatile unsigned int UBMR; /**< UART BRM Modulator Register, offset: 0xA8 串口二进制倍率调节寄存器 偏移地址0xA8*/ + volatile unsigned int UBRC; /**< UART Baud Rate Count Register, offset: 0xAC 串口波特率计数寄存器 偏移地址0xAC*/ + volatile unsigned int ONEMS; /**< UART One Millisecond Register, offset: 0xB0 串口一毫秒寄存器 偏移地址0xB0*/ + volatile unsigned int UTS; /**< UART Test Register, offset: 0xB4 串口测试寄存器 偏移地址0xB4*/ + volatile unsigned int UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 串口485模式控制寄存器 偏移地址0xB8*/ +} UART_Type; + + + +struct hw_uart_device +{ + rt_uint32_t hw_base; + rt_uint32_t irqno; +}; + +#define UART_DR(base) __REG32(base + 0x00) +#define UART_FR(base) __REG32(base + 0x18) +#define UART_CR(base) __REG32(base + 0x30) +#define UART_IMSC(base) __REG32(base + 0x38) +#define UART_ICR(base) __REG32(base + 0x44) + +#define UARTFR_RXFE 0x10 +#define UARTFR_TXFF 0x20 +#define UARTIMSC_RXIM 0x10 +#define UARTIMSC_TXIM 0x20 +#define UARTICR_RXIC 0x10 +#define UARTICR_TXIC 0x20 + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + /* 115200,8n1 */ + volatile unsigned int *IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA ; + volatile unsigned int *IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA ; + volatile unsigned int *IOMUXC_UART1_RX_DATA_SELECT_INPUT ; + volatile unsigned int *CCM_CSCDR1; + volatile unsigned int *CCM_CCGR5; + + IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA = (volatile unsigned int *)rt_ioremap((void *)0x20E0084, 4); + IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA = (volatile unsigned int *)rt_ioremap((void *)0x20E0088, 4); + IOMUXC_UART1_RX_DATA_SELECT_INPUT = (volatile unsigned int *)rt_ioremap((void *)0x20E0624, 4); + CCM_CSCDR1 = (volatile unsigned int *)rt_ioremap((void *)0x020C4024, 4); + CCM_CCGR5 = (volatile unsigned int *)rt_ioremap((void *)0x020C407C, 4); + + struct hw_uart_device * uart = (struct hw_uart_device *)serial->parent.user_data; + + UART_Type *uart_reg = (UART_Type *)uart->hw_base; + + /* 设置UART的总时钟 + * UART_CLK_ROOT = 80Mhz + */ + *CCM_CSCDR1 &= ~((1<<6) | (0x3f)); + + /* 给UART1模块提供时钟 + * uart1_clk_enable + */ + *CCM_CCGR5 |= (3<<24); + + /* 配置引脚功能 */ + *IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA &= ~0xf; + *IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA &= ~0xf; + + /* IMX6ULL特殊的地方 */ + *IOMUXC_UART1_RX_DATA_SELECT_INPUT |= 3; + + + /* 设置波特率 + * 115200 = 80M/(16*(UBMR+1)/(UBIR+1)) + * UBIR = 15 + * 115200 = 80M/(UBMR+1) + * UBMR = 80,000,000/115200 = 694 - 1 = 693 + * 真正的baudrate = 80,000,000/694 = 115274 + * 先设置UBIR, 后设置UBMR + */ + uart_reg->UFCR |= (5<<7); + uart_reg->UBIR = 15; + uart_reg->UBMR = 693; + + /* 设置数据格式 */ + uart_reg->UCR2 |= (1<<14) | (0<<8) | (0<<6) | (1<<5) | (1<<2) | (1<<1); + + /* IMX6ULL芯片要求必须设置 */ + uart_reg->UCR3 |= (1<<2); + + /* 使能UART */ + uart_reg->UCR1 |= (1<<0); + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + UART_Type *uart_reg; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + uart_reg = (UART_Type *)uart->hw_base; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + uart_reg->UCR4 &= ~(1<<0); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + uart_reg->UCR4 |= (1<<0); + rt_hw_interrupt_umask(uart->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + UART_Type *uart_reg; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + uart_reg = (UART_Type *)uart->hw_base; + + while ((uart_reg->USR2 & (1<<3)) == 0); + uart_reg->UTXD = c; + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct hw_uart_device *uart; + UART_Type *uart_reg; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + uart_reg = (UART_Type *)uart->hw_base; + + if ((uart_reg->USR2 & (1<<0)) == 0) + ch = -1; + else + ch = uart_reg->URXD; + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +#ifdef RT_USING_UART0 +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + 0x02020000, /* imx6ull uart1 phy addr */ + 58, /* rx irq */ +}; +static struct rt_serial_device _serial0; +#endif + +#ifdef RT_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = +{ + REALVIEW_UART1_BASE, + IRQ_PBA8_UART1, +}; +static struct rt_serial_device _serial1; +#endif + +int rt_hw_uart_init(void) +{ + struct hw_uart_device *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef RT_USING_UART0 + _uart0_device.hw_base = (uint32_t)rt_ioremap((void*)_uart0_device.hw_base, 0x1000); + uart = &_uart0_device; + + _serial0.ops = &_uart_ops; + _serial0.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0"); +#endif + +#ifdef RT_USING_UART1 + _uart1_device.hw_base = (uint32_t)rt_ioremap((void*)_uart1_device.hw_base, 0x1000); + uart = &_uart1_device; + _serial1.ops = &_uart_ops; + _serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); + /* enable Rx and Tx of UART */ + UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1"); +#endif + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/imx6ull-100ask-smart/drivers/serial.h b/bsp/imx6ull-100ask-smart/drivers/serial.h new file mode 100644 index 0000000000000000000000000000000000000000..3d870466c19eb95a4990aff7e9aef8e6a0e3f730 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/drivers/serial.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#ifndef __UART_H__ +#define __UART_H__ + +#include + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/imx6ull-100ask-smart/link.lds b/bsp/imx6ull-100ask-smart/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..ab4674d485a4788d467a6b246d2b3e65c2d5559e --- /dev/null +++ b/bsp/imx6ull-100ask-smart/link.lds @@ -0,0 +1,105 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SECTIONS +{ + /*. = 0x60010000; */ + . = 0xc0010000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } =0 + __text_end = .; + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(8); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(8); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/imx6ull-100ask-smart/makefile.targets b/bsp/imx6ull-100ask-smart/makefile.targets new file mode 100644 index 0000000000000000000000000000000000000000..a00129bd90590dcf655a0e6c5ac8f530e7b5c383 --- /dev/null +++ b/bsp/imx6ull-100ask-smart/makefile.targets @@ -0,0 +1,4 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' \ No newline at end of file diff --git a/bsp/imx6ull-100ask-smart/mkimage.py b/bsp/imx6ull-100ask-smart/mkimage.py new file mode 100644 index 0000000000000000000000000000000000000000..592f7bb8c0444a9ab77910de2db27e347fc0ce0f --- /dev/null +++ b/bsp/imx6ull-100ask-smart/mkimage.py @@ -0,0 +1,235 @@ +# @Time : 2020/12/31 +# @Author : David Dai +# @File : mkimage.py +#!/usr/bin/python2 + +import os +import argparse +import struct + +parser = argparse.ArgumentParser() + +parser.add_argument('-t', '--type') +parser.add_argument('-b', '--bin') +parser.add_argument('-o', '--out', default = "load.bin") +parser.add_argument('-g', '--img', default = "load.img") +parser.add_argument('-a', '--addr', default = "0x00000000") +parser.add_argument('-e', '--ep', default = "0x00000000") + +args = parser.parse_args() + +args.addr = int(args.addr, 16) +args.ep = int(args.ep, 16) + +def stm32image(): + checksum = 0 + + with open(args.out, 'wb') as f: + #write head 'STM32' + f.write(struct.pack('H', 32)) + f.write(struct.pack('H', (len(dcdConfig) << 3) + 8)) + f.write(struct.pack('H', (len(dcdConfig) << 3) + 4)) + f.write(struct.pack('I', int(d[0], 16))) + f.write(struct.pack('>I', int(d[1], 16))) + + #padding data + for i in range(0x27B): + f.write(struct.pack(' rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +\ + 'python mkimage.py ' + MKIMAGE + '\n' diff --git a/bsp/imx6ull-artpi-smart/.config b/bsp/imx6ull-artpi-smart/.config new file mode 100644 index 0000000000000000000000000000000000000000..292c39ddf6d5015df09e318fb4558c2fca8312aa --- /dev/null +++ b/bsp/imx6ull-artpi-smart/.config @@ -0,0 +1,952 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_MEMTRACE=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +CONFIG_RT_USING_INTERRUPT_INFO=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0xc0000000 +CONFIG_PV_OFFSET=0xc0000000 +# CONFIG_RT_IOREMAP_LATE is not set +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_ARCH_ARM_CORTEX_A7=y +CONFIG_ARCH_ARM_SECURE_MODE=y +CONFIG_RT_BACKTRACE_FUNCTION_NAME=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=8 +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +# CONFIG_RT_USING_I2C_BITOPS is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +CONFIG_RT_USING_TOUCH=y +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +CONFIG_RT_USING_USB_DEVICE=y +CONFIG_RT_USBD_THREAD_STACK_SZ=4096 +CONFIG_USB_VENDOR_ID=0x0FFE +CONFIG_USB_PRODUCT_ID=0x0001 +# CONFIG_RT_USB_DEVICE_COMPOSITE is not set +# CONFIG__RT_USB_DEVICE_NONE is not set +# CONFIG__RT_USB_DEVICE_CDC is not set +# CONFIG__RT_USB_DEVICE_MSTORAGE is not set +# CONFIG__RT_USB_DEVICE_HID is not set +# CONFIG__RT_USB_DEVICE_RNDIS is not set +# CONFIG__RT_USB_DEVICE_ECM is not set +CONFIG__RT_USB_DEVICE_WINUSB=y +# CONFIG__RT_USB_DEVICE_AUDIO is not set +CONFIG_RT_USB_DEVICE_WINUSB=y +CONFIG_RT_WINUSB_GUID="{6860DC3C-C05F-4807-8807-1CA861CC1D66}" + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y +# CONFIG_RT_USING_MLIB is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_USING_POSIX_CLOCKTIME=y +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +CONFIG_SAL_USING_POSIX=y + +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +CONFIG_NETDEV_USING_IPV6=y +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=1 +CONFIG_NETDEV_IPV6_SCOPES=y + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP202 is not set +CONFIG_RT_USING_LWIP212=y +CONFIG_RT_USING_LWIP_IPV6=y +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=8192 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +CONFIG_RT_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_NETIF_LOOPBACK=1 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +CONFIG_ULOG_OUTPUT_LVL=7 +# CONFIG_ULOG_USING_ISR_LOG is not set +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=128 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +# CONFIG_ULOG_OUTPUT_FLOAT is not set +CONFIG_ULOG_USING_COLOR=y +CONFIG_ULOG_OUTPUT_TIME=y +# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# POSIX extension functions +# +# CONFIG_PKG_USING_POSIX_GETLINE is not set +# CONFIG_PKG_USING_POSIX_WCWIDTH is not set +# CONFIG_PKG_USING_POSIX_ITOA is not set +# CONFIG_PKG_USING_POSIX_STRINGS is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_RT_USING_ARDUINO is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_USB_STACK is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_MDNS is not set +# CONFIG_PKG_USING_UPNP is not set +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set +# CONFIG_PKG_USING_RIL is not set +# CONFIG_PKG_USING_WATCH_DCM_SVC is not set +# CONFIG_PKG_USING_WATCH_APP_FWK is not set +# CONFIG_PKG_USING_GUI_TEST is not set +# CONFIG_PKG_USING_PMEM is not set +# CONFIG_PKG_USING_LWRDP is not set +# CONFIG_PKG_USING_MASAN is not set +# CONFIG_PKG_USING_BSDIFF_LIB is not set +# CONFIG_PKG_USING_PRC_DIFF is not set + +# +# RT-Thread Smart +# +# CONFIG_PKG_USING_UKERNEL is not set +# CONFIG_PKG_USING_UKERNEL_V100 is not set +# CONFIG_PKG_USING_UKERNEL_LATEST_VERSION is not set +CONFIG_SOC_IMX6ULL=y +CONFIG_CPU_MCIMX6Y2CVM05=y +CONFIG_FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 +CONFIG_FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL=1 + +# +# Platform Driver Configuration +# + +# +# Select UART Driver +# +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set + +# +# Select SPI Driver +# +CONFIG_BSP_USING_SPI=y +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set +# CONFIG_BSP_USING_SPI3 is not set +# CONFIG_BSP_USING_SPI4 is not set + +# +# Select I2C Driver +# +CONFIG_BSP_USING_I2C=y +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_I2C2 is not set +CONFIG_BSP_USING_I2C3=y +CONFIG_I2C3_BAUD_RATE=400000 +CONFIG_BSP_USING_I2C4=y +CONFIG_I2C4_BAUD_RATE=100000 + +# +# Select LCD Driver +# +CONFIG_BSP_USING_LCD=y +CONFIG_BSP_LCD_WIDTH=480 +CONFIG_BSP_LCD_HEIGHT=272 +CONFIG_BSP_LCD_VSW=2 +CONFIG_BSP_LCD_VBP=23 +CONFIG_BSP_LCD_VFP=22 +CONFIG_BSP_LCD_HSW=2 +CONFIG_BSP_LCD_HBP=46 +CONFIG_BSP_LCD_HFP=210 +CONFIG_BSP_LCD_PLL_DIV=8 + +# +# Select SDHC Driver +# +CONFIG_RT_USING_SDIO1=y +CONFIG_RT_USING_SDIO2=y + +# +# Select RTC Driver +# +CONFIG_BSP_USING_ONCHIP_RTC=y + +# +# Select PWM Driver +# +CONFIG_BSP_USING_PWM1=y +# CONFIG_BSP_USING_PWM2 is not set +# CONFIG_BSP_USING_PWM3 is not set +# CONFIG_BSP_USING_PWM4 is not set + +# +# Select WDT Driver +# +CONFIG_RT_USING_WDT1=y +CONFIG_RT_USING_WDT2=y +# CONFIG_RT_USING_WDT3 is not set + +# +# Select ENET Driver +# +CONFIG_RT_USING_ENET1=y +# CONFIG_RT_USING_ENET2 is not set + +# +# Select Wifi Driver +# +# CONFIG_RT_USING_WIFI_RW007 is not set + +# +# Select USB Driver +# +CONFIG_BSP_USING_USB_DEVICE=y diff --git a/bsp/imx6ull-artpi-smart/Kconfig b/bsp/imx6ull-artpi-smart/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..4d44db29958324f645d37c5d0917f7ad412bf3d1 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/Kconfig @@ -0,0 +1,44 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_IMX6ULL + bool + select ARCH_ARM_CORTEX_A7 + select RT_USING_CACHE + select ARCH_ARM_MMU + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_FPU + default y + + if SOC_IMX6ULL + config CPU_MCIMX6Y2CVM05 + bool + default y + config FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + depends on RT_USING_CACHE + int + default 1 + config FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL + int "Disable Clock control in fsl files" + default 1 + endif + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/imx6ull-artpi-smart/README.md b/bsp/imx6ull-artpi-smart/README.md new file mode 100644 index 0000000000000000000000000000000000000000..30825157f3725f7d53eb507c8ba40cd27b27c887 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/README.md @@ -0,0 +1,25 @@ +# RT-Thread Smart for i.MX6ULL + +这是一份ART-pi smart开发板的BSP，支持smart模式也支持传统的RTOS模式； + +ART-pi smart采用了米尔科技的imx6ull核心板，硬件由韦东山团队完成，由社区来完成整体的BSP。硬件规格情况如下： + +![硬件资源](figures/hw_resources.png) + +## 如何编译 + +如果使用smart的模式，请使用smart sdk环境，然后进入到这个bsp目录，执行 + +```bash +scons +``` + +进行编译； + +如果使用RTOS模式，请确保在menuconfig中不选择smart模式，然后执行 + +```bash +scons +``` + +进行编译。 diff --git a/bsp/imx6ull-artpi-smart/SConscript b/bsp/imx6ull-artpi-smart/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/SConstruct b/bsp/imx6ull-artpi-smart/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..8730b80611ec89f94b0901eeab2ded6555c2b9b9 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/SConstruct @@ -0,0 +1,43 @@ +import os +import sys +import rtconfig +import re +RTT_ROOT = os.getenv('RTT_ROOT') or os.path.join('..', '..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +content = "" +TRACE_CONFIG = '' +with open("rtconfig.h") as f: + for line in f.readlines(): + if line.find("RT_BACKTRACE_FUNCTION_NAME") != -1: + for token in line.split(" "): + if re.match(r'RT_BACKTRACE_FUNCTION_NAME$', token, flags=0): + TRACE_CONFIG = " -mpoke-function-name" + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS + TRACE_CONFIG, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS + TRACE_CONFIG, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS + TRACE_CONFIG, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +if GetDepend('RT_USING_SMART'): + # use smart link.lds + env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds') + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/imx6ull-artpi-smart/applications/SConscript b/bsp/imx6ull-artpi-smart/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..89083a964a159e254033baaa552061b3f03addb0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/imx6ull-artpi-smart/applications/init_sdtask.c b/bsp/imx6ull-artpi-smart/applications/init_sdtask.c new file mode 100644 index 0000000000000000000000000000000000000000..16377434aa2248a967e2832df10ceb867c51c6db --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/init_sdtask.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#include + +#if defined(RT_USING_DFS) + +#include +#include +#include + +#define DBG_TAG "app.filesystem" +#define DBG_LVL DBG_INFO +#include + +static void _sdcard_mount(void) +{ + rt_device_t device; + + device = rt_device_find("sd0"); + if (device == NULL) + { + mmcsd_wait_cd_changed(0); + host_change(); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + rt_thread_mdelay(10); + device = rt_device_find("sd0"); + } + + if (device != RT_NULL) + { + if (dfs_mount("sd0", "/mnt", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/mnt'"); + } + else + { + LOG_W("sd card mount to '/mnt' failed!"); + } + } +} + +static void _sdcard_unmount(void) +{ + rt_thread_mdelay(200); + dfs_unmount("/mnt"); + LOG_I("Unmount \"/mnt\""); + + mmcsd_wait_cd_changed(0); + host_change(); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); +} + +static void sd_task_entry(void *parameter) +{ + volatile unsigned int *IN_STATUS; + + IN_STATUS = (volatile unsigned int *)rt_ioremap((void *)0x2190030, 4); + + rt_thread_mdelay(200); + if (dfs_mount("sd0", "/mnt", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/mnt'"); + } + else + { + LOG_W("sd card mount to '/mnt' failed!"); + } + + while (1) + { + rt_thread_mdelay(200); + if (((*IN_STATUS >>6) & 0x1) == 1) + { + *IN_STATUS = 0x40; + _sdcard_mount(); + } + + if (((*IN_STATUS >>7) & 0x1) == 1) + { + *IN_STATUS = (0x80); + _sdcard_unmount(); + } + } +} + +int sd_task_init(void) +{ + rt_thread_t tid; + tid = rt_thread_create("tsdcard", sd_task_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd mount task error!"); + } + + return RT_EOK; +} +INIT_APP_EXPORT(sd_task_init); + +#endif diff --git a/bsp/imx6ull-artpi-smart/applications/init_udb.c b/bsp/imx6ull-artpi-smart/applications/init_udb.c new file mode 100644 index 0000000000000000000000000000000000000000..9b51fbee4572c971457ca9b28c8ed94ca84d9b9b --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/init_udb.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022/01/20 bernard the first version + */ + +#include +#include +#include + +#include + +#ifdef PKG_USING_UDBD +#include + +int udbd_system_init(void) +{ + udbd_init(UDBD_LINK_SOCKET, "e1"); + return 0; +} +INIT_APP_EXPORT(udbd_system_init); +#endif diff --git a/bsp/imx6ull-artpi-smart/applications/init_wifi.c b/bsp/imx6ull-artpi-smart/applications/init_wifi.c new file mode 100644 index 0000000000000000000000000000000000000000..20cb860671152705961c22d77835379b1d28531c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/init_wifi.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022/01/20 bernard the first version + */ + +#include +#include +#include + +#include + +#ifdef PKG_USING_RW007 +#define WIFI_SH_PATH "/sd/wifi.sh" + +int rw007_wifi_init(void) +{ + if (access(WIFI_SH_PATH, 0) != -1) + { + msh_exec(WIFI_SH_PATH, rt_strlen(WIFI_SH_PATH)); + } + else + { + rt_kprintf("%s wi-fi configuration file not exist in sd card!\n", WIFI_SH_PATH); + } + + return 0 +} +INIT_APP_EXPORT(rw007_wifi_init); +#endif diff --git a/bsp/imx6ull-artpi-smart/applications/main.c b/bsp/imx6ull-artpi-smart/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..d83eb620224d27c812be3b8ad7ab31e25a9e5099 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/10/7 bernard the first version + */ +#include +#include +#include + +int main(void) +{ + printf("hello rt-smart\n"); + return 0; +} diff --git a/bsp/imx6ull-artpi-smart/applications/mnt.c b/bsp/imx6ull-artpi-smart/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..bfd8c7d4e83a09f8d7705c5bc2065ff0bcef25d3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/mnt.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include + +#ifdef RT_USING_DFS + +#include +#include + +int mnt_init(void) +{ +#ifdef RT_USING_SDIO2 + rt_thread_mdelay(500); + + int part_id = 3; + if (dfs_mount("emmc","/","elm",0,(void *)part_id) != 0) + { + rt_kprintf("Dir / emmc mount failed!\n"); + return -1; + } + else + { + rt_kprintf("emmc file system initialization done!\n"); + } + + part_id = 1; + if (dfs_mount("sd0","/sd","elm",0,(void *)part_id) != 0) + { + rt_kprintf("Dir / sd0 mount failed!\n"); + return -1; + } + else + { + rt_kprintf("sd0 file system initialization done!\n"); + } +#else + rt_thread_mdelay(500); + if (dfs_mount(NULL, "/", "rom", 0, &romfs_root) != 0) + { + rt_kprintf("Dir / mount failed!\n"); + return -1; + } + + rt_kprintf("file system initialization done!\n"); +#endif + return 0; +} +INIT_APP_EXPORT(mnt_init); + +#endif diff --git a/bsp/imx6ull-artpi-smart/applications/romfs.c b/bsp/imx6ull-artpi-smart/applications/romfs.c new file mode 100644 index 0000000000000000000000000000000000000000..f098a76572cad3c0d6bdb688b5d54515f83c98ec --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/romfs.c @@ -0,0 +1,11 @@ +#include + +static const struct romfs_dirent _romfs_root[] = { + {ROMFS_DIRENT_DIR, "etc", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "mnt", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "bin", RT_NULL, 0} +}; + +const struct romfs_dirent romfs_root = { + ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0])}; + diff --git a/bsp/imx6ull-artpi-smart/drivers/Kconfig b/bsp/imx6ull-artpi-smart/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..54a8bfa955ea0616ee387ffd07e1ae9580892c32 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/Kconfig @@ -0,0 +1,240 @@ +menu "Platform Driver Configuration" + +menu "Select UART Driver" + if RT_USING_SERIAL + config BSP_USING_UART1 + bool "Enable UART1" + default y + config BSP_USING_UART2 + bool "Enable UART2" + default n + config BSP_USING_UART3 + bool "Enable UART3" + default n + config BSP_USING_UART4 + bool "Enable UART4" + default n + config BSP_USING_UART5 + bool "Enable UART5" + default n + config BSP_USING_UART6 + bool "Enable UART6" + default n + config BSP_USING_UART7 + bool "Enable UART7" + default n + config BSP_USING_UART8 + bool "Enable UART8" + default n + endif +endmenu + +menu "Select SPI Driver" + config BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default n + + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI3 + bool "Enable SPI3" + default y + config BSP_USING_SPI4 + bool "Enable SPI4" + default n + endif +endmenu + +menu "Select I2C Driver" + config BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config I2C1_BAUD_RATE + int "Set i2c1 baud rate (HZ)" + default 100000 + endif + + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config I2C2_BAUD_RATE + int "Set i2c2 baud rate (HZ)" + default 100000 + endif + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config I2C3_BAUD_RATE + int "Set i2c3 baud rate (HZ)" + default 100000 + endif + + config BSP_USING_I2C4 + bool "Enable I2C4" + default n + if BSP_USING_I2C4 + config I2C4_BAUD_RATE + int "Set i2c4 baud rate (HZ)" + default 100000 + endif + endif +endmenu + +menu "Select LCD Driver" +config BSP_USING_LCD + bool "Enable LCD" + default y + + if BSP_USING_LCD + config BSP_LCD_WIDTH + int "Width of LCD panel" + default 1000 + config BSP_LCD_HEIGHT + int "Height of LCD panel" + default 600 + config BSP_LCD_VSW + int "value of LCD_VSW" + default 2 + config BSP_LCD_VBP + int "value of LCD_VBP" + default 23 + config BSP_LCD_VFP + int "value of LCD_VFP" + default 22 + config BSP_LCD_HSW + int "value of LCD_HSW" + default 2 + config BSP_LCD_HBP + int "value of LCD_HBP" + default 46 + config BSP_LCD_HFP + int "value of LCD_HFP" + default 210 + config BSP_LCD_PLL_DIV + int "value of PLL DIV" + default 8 + endif +endmenu + +menu "Select SDHC Driver" + if RT_USING_SDIO + config RT_USING_SDIO1 + bool "Enable SDHC1" + default n + config RT_USING_SDIO2 + bool "Enable SDHC2" + default n + endif +endmenu + +menu "Select RTC Driver" + if RT_USING_RTC + config BSP_USING_ONCHIP_RTC + bool "Enable On-Chip RTC" + default y + endif +endmenu + +menu "Select PWM Driver" + config RT_USING_PWM + bool "Enable PWM" + default n + if RT_USING_PWM + config BSP_USING_PWM1 + bool "Enable PWM1" + default n + config BSP_USING_PWM2 + bool "Enable PWM2" + default n + config BSP_USING_PWM3 + bool "Enable PWM3" + default n + config BSP_USING_PWM4 + bool "Enable PWM4" + default n + endif +endmenu + +menu "Select ADC Driver" + config RT_USING_ADC + bool "Enable ADC" + default n + if RT_USING_ADC + config BSP_USING_ADC1_1 + bool "Enable ADC1 CH1" + default n + config BSP_USING_ADC1_2 + bool "Enable ADC1 CH2" + default n + config BSP_USING_ADC1_3 + bool "Enable ADC1 CH3" + default n + config BSP_USING_ADC1_4 + bool "Enable ADC1 CH4" + default n + endif +endmenu + +menu "Select WDT Driver" + if RT_USING_WDT + config RT_USING_WDT1 + bool "Enable WDT1" + default n + config RT_USING_WDT2 + bool "Enable WDT2" + default n + config RT_USING_WDT3 + bool "Enable WDT3" + default n + endif +endmenu + +menu "Select ENET Driver" + config RT_USING_ENET1 + bool "Enable ENET1" + default y + config RT_USING_ENET2 + bool "Enable ENET2" + default n +endmenu + +menu "Select Wifi Driver" + config RT_USING_WIFI_RW007 + bool "Enable wifi RW007" + select BSP_USING_SPI2 + select PKG_USING_RW007 + select RT_USING_WIFI + default n + if RT_USING_WIFI_RW007 + config RW007_DAFAULT_SSID + string "default ssid" + default "rt-thread" + config RW007_DAFAULT_PASSWARD + string "default passward" + default "12345678" + endif +endmenu + +menu "Select USB Driver" + config BSP_USING_USB_DEVICE + bool "Enable USB device" + default y +endmenu + +endmenu diff --git a/bsp/imx6ull-artpi-smart/drivers/SConscript b/bsp/imx6ull-artpi-smart/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..b4b63c8cd1fa7be434625fc18c9b8a27aa4c4dcf --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/SConscript @@ -0,0 +1,22 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('iomux/*.c') + +if GetDepend(['BSP_USING_USB_DEVICE']): + src += Glob('usb/device/*.c') + src += Glob('usb/phy/*.c') + +list = os.listdir(cwd) +CPPPATH = [cwd, cwd + '/iomux'] +objs = [] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/drivers/board.c b/bsp/imx6ull-artpi-smart/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..d7590bc35c901de1645214f061ce832866ea2198 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/board.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-11-20 Bernard the first version + * 2018-11-22 Jesven add rt_hw_spin_lock + * add rt_hw_spin_unlock + * add smp ipi init + */ + +#include +#include +#include + +#include "board.h" + +#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +extern size_t MMUTable[]; +rt_mmu_info mmu_info; + +#ifdef RT_USING_USERSPACE +struct mem_desc platform_mem_desc[] = { /* 100ask_imx6ull ddr 512M */ + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x1FFFFFFF, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM} +}; +#else +struct mem_desc platform_mem_desc[] = { + {0x00000000, 0x80000000, 0x00000000, DEVICE_MEM}, + {0x80000000, 0xFFF00000, 0x80000000, NORMAL_MEM} +}; +#endif +const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); + +void idle_wfi(void) +{ + asm volatile ("wfi"); +} + +/** + * This function will initialize board + */ + +#ifdef RT_USING_USERSPACE +rt_region_t init_page_region = { + (uint32_t)PAGE_START, + (uint32_t)PAGE_END, +}; +#endif + +int board_reboot(int argc, char **argv) +{ + wdog_config_t config; + SRC_Type *src = (SRC_Type*)g_src_vbase; + WDOG_Type *wdog = (WDOG_Type*)g_wdog1_vbase; + + LOG_E("resetting ...\n"); + + rt_hw_ms_delay(50); + + src->SCR &= ~SRC_SCR_WARM_RESET_ENABLE_MASK; + + CLOCK_EnableClock(kCLOCK_Wdog1); + + WDOG_GetDefaultConfig(&config); + config.timeoutValue = 0x00u; + + WDOG_Init(wdog, &config); + + while (1) + { + //waiting... + } + + return 0; +} +MSH_CMD_EXPORT_ALIAS(board_reboot, reboot, reboot system); + +void rt_hw_board_init(void) +{ +#ifdef RT_USING_USERSPACE + rt_hw_mmu_map_init(&mmu_info, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); + + rt_page_init(init_page_region); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0xf0000000, 0x10000000); + + arch_kuser_init(&mmu_info, (void*)0xffff0000); +#else + rt_hw_mmu_map_init(&mmu_info, (void*)0x80000000, 0x10000000, MMUTable, 0); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0x80000000, 0x10000000); +#endif + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize system heap */ + rt_system_heap_init(HEAP_BEGIN, HEAP_END); + + SystemAddressMapping(); + SystemClockInit(); + + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + rt_thread_idle_sethook(idle_wfi); +} diff --git a/bsp/imx6ull-artpi-smart/drivers/board.h b/bsp/imx6ull-artpi-smart/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..03861915b4f2cb261e7457c30784e6961dfb0c84 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/board.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "imx6ull.h" + +#include "mmu.h" + +#if defined(__CC_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) +#elif defined(__GNUC__) +extern int __bss_end; +#define HEAP_BEGIN ((void*)&__bss_end) +#endif + +#ifdef RT_USING_USERSPACE +#define HEAP_END (void*)(KERNEL_VADDR_START + 16 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END (void*)(KERNEL_VADDR_START + 128 * 1024 * 1024) +#else +#define HEAP_END (void*)(0x80000000 + 64 * 1024 * 1024) +#endif + +/* + * memory map for peripherals + */ +/* + start addr - end addr , size + 0x0090_0000 - 0x0091_FFFF, 128KB, OCRAM + 0x0200_0000 - 0x020F_FFFF, 1MB, AIPS-1 + 0x0210_0000 - 0x021F_FFFF, 1MB, AIPS-2 + 0x0220_0000 - 0x022F_FFFF, 1MB, AIPS-3 + */ +void rt_hw_board_init(void); + +extern rt_mmu_info mmu_info; + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/bsp_clock.c b/bsp/imx6ull-artpi-smart/drivers/bsp_clock.c new file mode 100644 index 0000000000000000000000000000000000000000..b6b88fe4e3c00093d45c4ca9f09c36dc8e384a61 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/bsp_clock.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-20 Lyons first version + * 2021-06-24 RiceChen add spi and lcd clock config + */ + +#include "board.h" +#include "fsl_clock.h" + +#define _K_GPT_LOAD_VALUE RT_UINT32_MAX + +/* only used by MCIMX6Y2.h */ +uint32_t *g_ccm_vbase = (uint32_t*)IMX6ULL_CCM_BASE; +uint32_t *g_ccm_analog_vbase = (uint32_t*)IMX6ULL_CCM_ANALOGY_BASE; +uint32_t *g_pmu_vbase = (uint32_t*)IMX6ULL_PMU_BASE; + +uint32_t g_usbphy1_base = IMX6ULL_USBPHY1_BASE; +uint32_t g_usbphy2_base = IMX6ULL_USBPHY2_BASE; + +uint32_t g_usb1_base = IMX6ULL_USB1_BASE; +uint32_t g_usb2_base = IMX6ULL_USB2_BASE; +uint32_t g_usb_analog_base = IMX6ULL_USB_ANALOG_BASE; +/* used by all files */ +uint32_t *g_iomuxc_vbase = (uint32_t*)IMX6ULL_IOMUXC_BASE; +uint32_t *g_iomuxc_snvs_vbase = (uint32_t*)IMX6ULL_IOMUXC_SNVS_BASE; +uint32_t *g_src_vbase = (uint32_t*)IMX6ULL_SRC_BASE; +uint32_t *g_wdog1_vbase = (uint32_t*)IMX6ULL_WATCHDOG1_BASE; +uint32_t *g_snvs_vbase = (uint32_t*)IMX6ULL_SNVS_BASE; + +_internal_rw uint32_t *_s_gpt1_vbase = (uint32_t*)IMX6ULL_GPT1_BASE; + +static void _clk_enable( CCM_Type *base ) +{ + base->CCGR0 = 0XFFFFFFFF; + base->CCGR1 = 0XFFFFFFFF; + base->CCGR2 = 0XFFFFFFFF; + base->CCGR3 = 0XFFFFFFFF; + base->CCGR4 = 0XFFFFFFFF; + base->CCGR5 = 0XFFFFFFFF; + base->CCGR6 = 0XFFFFFFFF; +} + +void BOARD_BootClockRUN(void) +{ + rt_uint32_t reg_value; + + /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */ + CLOCK_SetXtalFreq(24000000U); + CLOCK_SetRtcXtalFreq(32768U); + + /* + * ARM_CLK from 'pll1_sw_clk', whitch from 'pll1_main_clk' or 'step_clk' + * if edit 'pll1_main_clk', switch to 'step_clk' first + */ + reg_value = CCM->CCSR; + if (0 == (reg_value & CCM_CCSR_PLL1_SW_CLK_SEL_MASK)) //if sel 'pll1_main_clk' + { + reg_value &= ~CCM_CCSR_STEP_SEL_MASK; + reg_value |= CCM_CCSR_STEP_SEL(0); //sel 'osc_clk(24M)' + reg_value |= CCM_CCSR_PLL1_SW_CLK_SEL(1); //sel 'step_clk' + CCM->CCSR = reg_value; + } + + /* + * set PLL1(ARM PLL) at 1056MHz + * set ARM_CLK at 528MHz + * PLL output frequency = Fref * DIV_SEL / 2 + * = 24M * DIV_SEL / 2 = 1056M + */ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE(1) + | CCM_ANALOG_PLL_ARM_DIV_SELECT(88); + + reg_value = CCM->CCSR; + reg_value &= ~CCM_CCSR_PLL1_SW_CLK_SEL_MASK; + reg_value |= CCM_CCSR_PLL1_SW_CLK_SEL(0); //resel 'pll1_main_clk' + CCM->CCSR = reg_value; + + CCM->CACRR = CCM_CACRR_ARM_PODF(1); //'CACRR[ARM_PODF]=0b001' divide by 2 + + /* + * set PLL2(System PLL) at fixed 528MHz + * PLL2_PFD0: 528M * 18 / FRAC + * PLL2_PFD1: 528M * 18 / FRAC + * PLL2_PFD2: 528M * 18 / FRAC + * PLL2_PFD3: 528M * 18 / FRAC + */ + reg_value = CCM_ANALOG->PFD_528; + reg_value &= ~0x3F3F3F3F; + reg_value |= CCM_ANALOG_PFD_528_SET_PFD0_FRAC(27); //27: 352MHz + reg_value |= CCM_ANALOG_PFD_528_SET_PFD1_FRAC(16); //16: 594MHz + reg_value |= CCM_ANALOG_PFD_528_SET_PFD2_FRAC(24); //24: 396MHz + reg_value |= CCM_ANALOG_PFD_528_SET_PFD3_FRAC(32); //32: 297MHz + CCM_ANALOG->PFD_528 = reg_value; + + /* + * set PLL3(USB PLL) at fixed 480MHz + * PLL3_PFD0: 480M * 18 / FRAC + * PLL3_PFD1: 480M * 18 / FRAC + * PLL3_PFD2: 480M * 18 / FRAC + * PLL3_PFD3: 480M * 18 / FRAC + */ + reg_value = CCM_ANALOG->PFD_480; + reg_value &= ~0x3F3F3F3F; + reg_value |= CCM_ANALOG_PFD_480_SET_PFD0_FRAC(12); //12: 720MHz + reg_value |= CCM_ANALOG_PFD_480_SET_PFD1_FRAC(16); //16: 540MHz + reg_value |= CCM_ANALOG_PFD_480_SET_PFD2_FRAC(17); //17: 508.24MHz + reg_value |= CCM_ANALOG_PFD_480_SET_PFD3_FRAC(19); //19: 457.74MHz + CCM_ANALOG->PFD_480 = reg_value; + + /* + * set PERCLK_CLK at 66MHz from IPG_CLK + */ + reg_value = CCM->CSCMR1; + reg_value &= ~CCM_CSCMR1_PERCLK_CLK_SEL_MASK; + reg_value |= CCM_CSCMR1_PERCLK_CLK_SEL(0); //sel IPG_CLK + reg_value &= ~CCM_CSCMR1_PERCLK_PODF_MASK; + reg_value |= CCM_CSCMR1_PERCLK_PODF(0); //'CSCMR1[PERCLK_PODF]=0b000000' divide by 1 + CCM->CSCMR1 = reg_value; + + CLOCK_DeinitAudioPll(); + CLOCK_DeinitVideoPll(); + CLOCK_DeinitEnetPll(); + + /* Configure UART divider to default */ + CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ + + /* Configure ECSPI divider to default */ + CLOCK_SetMux(kCLOCK_EcspiMux, 0); /* Set ECSPI source to PLL3 60M */ + CLOCK_SetDiv(kCLOCK_EcspiDiv, 0); /* Set ECSPI divider to 1 */ + + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_Lcdif1PreDiv, 2); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lcdif1Div, 4); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_Lcdif1PreMux, 2); + CLOCK_SetMux(kCLOCK_Lcdif1Mux, 0); +} + +void BOARD_DelayInit(void) +{ + GPT_Type *_GPT = (GPT_Type*)_s_gpt1_vbase; + + _GPT->CR = 0; + + _GPT->CR = GPT_CR_SWR(1); + while (_GPT->CR & GPT_CR_SWR_MASK); + + /* + * 000 No clock + * 001 derive clock from ipg_clk + * 010 derive clock from ipg_clk_highfreq + * 011 derive clock from External Clock + * 100 derive clock from ipg_clk_32k + * 101 derive clock from ipg_clk_24M + */ + _GPT->CR = GPT_CR_CLKSRC(0x1); + + _GPT->PR = GPT_PR_PRESCALER(65); //Set GPT1 Clock to 66MHz/66 = 1MHz + + _GPT->OCR[0] = GPT_OCR_COMP(_K_GPT_LOAD_VALUE); + + _GPT->CR |= GPT_CR_EN(1); +} + +//execution before SystemClockInit called +void SystemAddressMapping(void) +{ + g_ccm_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_ccm_vbase); + g_ccm_analog_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_ccm_analog_vbase); + g_pmu_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_pmu_vbase); + + g_iomuxc_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_iomuxc_vbase); + g_iomuxc_snvs_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_iomuxc_snvs_vbase); + g_src_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_src_vbase); + g_wdog1_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_wdog1_vbase); + g_snvs_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_snvs_vbase); + + _s_gpt1_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)_s_gpt1_vbase); + g_usbphy1_base = (uint32_t)platform_get_periph_vaddr((rt_uint32_t)g_usbphy1_base); + g_usbphy2_base = (uint32_t)platform_get_periph_vaddr((rt_uint32_t)g_usbphy2_base); + + g_usb1_base = (uint32_t)platform_get_periph_vaddr((rt_uint32_t)g_usb1_base); + g_usb2_base = (uint32_t)platform_get_periph_vaddr((rt_uint32_t)g_usb2_base); + g_usb_analog_base = (uint32_t)platform_get_periph_vaddr((rt_uint32_t)g_usb_analog_base); +} + +void SystemClockInit(void) +{ + BOARD_BootClockRUN(); + BOARD_DelayInit(); + + _clk_enable(CCM); +} + +void rt_hw_us_delay(uint32_t us) +{ + GPT_Type *_GPT = (GPT_Type*)_s_gpt1_vbase; + + rt_uint64_t old_cnt, new_cnt; + rt_uint64_t total = 0; + + old_cnt = _GPT->CNT; + while (1) + { + new_cnt = _GPT->CNT; + if (old_cnt != new_cnt) + { + if (new_cnt > old_cnt) + { + total += (new_cnt - old_cnt); + } else { + total += (new_cnt + _K_GPT_LOAD_VALUE - old_cnt); + } + old_cnt = new_cnt; + + if (total >= us) + break; + } + } +} + +void rt_hw_ms_delay(uint32_t ms) +{ + while (ms--) + { + rt_hw_us_delay(1000); + } +} diff --git a/bsp/imx6ull-artpi-smart/drivers/bsp_clock.h b/bsp/imx6ull-artpi-smart/drivers/bsp_clock.h new file mode 100644 index 0000000000000000000000000000000000000000..e84208fb4d0f4a4c02a98f3909b9b1e9b2ad6e6c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/bsp_clock.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-20 Lyons first version + */ + +#ifndef __BSP_CLOCK_H__ +#define __BSP_CLOCK_H__ + +extern uint32_t *g_iomuxc_vbase; +extern uint32_t *g_iomuxc_snvs_vbase; +extern uint32_t *g_src_vbase; +extern uint32_t *g_wdog1_vbase; +extern uint32_t *g_snvs_vbase; + +void SystemAddressMapping(void); +void SystemClockInit(void); + +void rt_hw_us_delay(uint32_t us); +void rt_hw_ms_delay(uint32_t ms); + +#endif //#ifndef __BSP_CLOCK_H__ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_adc.c b/bsp/imx6ull-artpi-smart/drivers/drv_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..0ee1b777f14b8c1c1665ca8b7169be834a63d362 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_adc.c @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-28 tyustli first version + * + */ + +#include +#define RT_USING_ADC +#ifdef RT_USING_ADC + +#define LOG_TAG "drv.adc" +#include + +#include +#include + +#include "fsl_adc.h" +#include "drv_adc.h" +#include +#include + +static rt_err_t imx6ull_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + return RT_EOK; +} + +static rt_err_t imx6ull_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + adc_channel_config_t adc_channel; + ADC_Type *base; + base = (ADC_Type *)(device->parent.user_data); + + adc_channel.channelNumber = channel; + adc_channel.enableInterruptOnConversionCompleted = 0; + + ADC_SetChannelConfig(base, 0, &adc_channel); + + while (0U == ADC_GetChannelStatusFlags(base, 0)) + { + continue; + } + + *value = ADC_GetChannelConversionValue(base, 0); + + return RT_EOK; +} + +static struct rt_adc_ops imx6ull_adc_ops = +{ + .enabled = imx6ull_adc_enabled, + .convert = imx6ull_adc_convert, +}; + + +int imx6ull_adc_gpio_init(void) +{ +#ifdef BSP_USING_ADC1_1 + do { + struct imx6ull_iomuxc gpio; + uint32_t pin_fun_id[5]={IOMUXC_GPIO1_IO01_GPIO1_IO01}; + + gpio.muxRegister = pin_fun_id[0]; + gpio.muxMode = pin_fun_id[1]; + gpio.inputRegister = pin_fun_id[2]; + gpio.inputDaisy = pin_fun_id[3]; + gpio.configRegister = pin_fun_id[4]; + gpio.inputOnfield = 0; + gpio.configValue = IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2U); + + imx6ull_gpio_init(&gpio); + }while(0); +#endif + +#ifdef BSP_USING_ADC1_2 + do { + struct imx6ull_iomuxc gpio; + uint32_t pin_fun_id[5]={IOMUXC_GPIO1_IO02_GPIO1_IO02}; + + gpio.muxRegister = pin_fun_id[0]; + gpio.muxMode = pin_fun_id[1]; + gpio.inputRegister = pin_fun_id[2]; + gpio.inputDaisy = pin_fun_id[3]; + gpio.configRegister = pin_fun_id[4]; + gpio.inputOnfield = 0; + gpio.configValue = IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2U); + + imx6ull_gpio_init(&gpio); + }while(0); +#endif + +#ifdef BSP_USING_ADC1_3 + do { + struct imx6ull_iomuxc gpio; + uint32_t pin_fun_id[5]={IOMUXC_GPIO1_IO03_GPIO1_IO03}; + + gpio.muxRegister = pin_fun_id[0]; + gpio.muxMode = pin_fun_id[1]; + gpio.inputRegister = pin_fun_id[2]; + gpio.inputDaisy = pin_fun_id[3]; + gpio.configRegister = pin_fun_id[4]; + gpio.inputOnfield = 0; + gpio.configValue = IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2U); + + imx6ull_gpio_init(&gpio); + }while(0); +#endif + +#ifdef BSP_USING_ADC1_4 + do { + struct imx6ull_iomuxc gpio; + uint32_t pin_fun_id[5]={IOMUXC_GPIO1_IO04_GPIO1_IO04}; + + gpio.muxRegister = pin_fun_id[0]; + gpio.muxMode = pin_fun_id[1]; + gpio.inputRegister = pin_fun_id[2]; + gpio.inputDaisy = pin_fun_id[3]; + gpio.configRegister = pin_fun_id[4]; + gpio.inputOnfield = 0; + gpio.configValue = IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2U); + + imx6ull_gpio_init(&gpio); + }while(0); +#endif + + return 0; +} + +int rt_hw_adc_init(void) +{ + rt_err_t ret = RT_EOK; + imx6ull_adc_gpio_init(); + +#if defined(BSP_USING_ADC1_1) || defined(BSP_USING_ADC1_2) || defined(BSP_USING_ADC1_3) || defined(BSP_USING_ADC1_4) + static adc_config_t ADC1_config_value; + static struct rt_adc_device adc1_device; + ADC_Type *adc1_base; + + adc1_base = (ADC_Type *)rt_ioremap((void*)ADC1, 0x1000); + + ADC_GetDefaultConfig(&ADC1_config_value); + ADC_Init(adc1_base, &ADC1_config_value); + + ADC_DoAutoCalibration(adc1_base); + + ret = rt_hw_adc_register(&adc1_device, "adc1", &imx6ull_adc_ops, adc1_base); + + if (ret != RT_EOK) + { + LOG_E("register adc1 device failed error code = %d\n", ret); + } + +#endif + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_adc_init); + +void set_adc_default(void *parameter) +{ + int result = 0; + +#ifdef BSP_USING_ADC1_1 + do { + struct rt_adc_device *device = RT_NULL; + device = (struct rt_adc_device *)rt_device_find("adc1"); + if (!device) + { + result = -RT_EIO; + return; + } + + result = rt_adc_enable(device, 1); + result = rt_adc_read(device, 1); + rt_kprintf("adc ch1 read result is %d\n",result); + } while(0); + +#endif + +#ifdef BSP_USING_ADC1_2 + do { + struct rt_adc_device *device = RT_NULL; + device = (struct rt_adc_device *)rt_device_find("adc1"); + if (!device) + { + result = -RT_EIO; + return; + } + + result = rt_adc_enable(device, 2); + result = rt_adc_read(device, 2); + rt_kprintf("adc ch2 read result is %d\n",result); + } while(0); +#endif + +#ifdef BSP_USING_ADC1_3 + do { + struct rt_adc_device *device = RT_NULL; + device = (struct rt_adc_device *)rt_device_find("adc1"); + if (!device) + { + result = -RT_EIO; + return; + } + + result = rt_adc_enable(device, 3); + result = rt_adc_read(device, 3); + rt_kprintf("adc ch3 read result is %d\n",result); + } while(0); +#endif + +#ifdef BSP_USING_ADC1_4 + do { + struct rt_adc_device *device = RT_NULL; + device = (struct rt_adc_device *)rt_device_find("adc1"); + if (!device) + { + result = -RT_EIO; + return; + } + + result = rt_adc_enable(device, 4); + result = rt_adc_read(device, 4); + rt_kprintf("adc ch4 read result is %d\n",result); + } while(0); +#endif + +} + +static int set_adc_init(void) +{ + rt_thread_t tid = rt_thread_create("adc_loop", set_adc_default, RT_NULL, 1024, 16, 20); + RT_ASSERT(tid != RT_NULL); + rt_thread_startup(tid); + return(RT_EOK); +} +INIT_APP_EXPORT(set_adc_init); +#endif /* BSP_USING_ADC */ diff --git a/components/finsh/finsh_heap.h b/bsp/imx6ull-artpi-smart/drivers/drv_adc.h similarity index 42% rename from components/finsh/finsh_heap.h rename to bsp/imx6ull-artpi-smart/drivers/drv_adc.h index 9c04e5c22f903f23fabe0f6080d755f6f99f6ab8..0113b54f3efdeeea5ef6dfb14a5575b0c05b445f 100644 --- a/components/finsh/finsh_heap.h +++ b/bsp/imx6ull-artpi-smart/drivers/drv_adc.h @@ -5,15 +5,14 @@ * * Change Logs: * Date Author Notes - * 2010-03-22 Bernard first version + * 2019-04-20 Lee the first version. */ -#include -#ifndef __FINSH_HEAP_H__ -#define __FINSH_HEAP_H__ +#ifndef DRV_ADC_H__ +#define DRV_ADC_H__ +#include -int finsh_heap_init(void); -void* finsh_heap_allocate(size_t size); -void finsh_heap_free(void*ptr); +int rt_hw_adc_init(void); + +#endif /* DRV_ADC_H__ */ -#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_common.c b/bsp/imx6ull-artpi-smart/drivers/drv_common.c new file mode 100644 index 0000000000000000000000000000000000000000..ad4685a709b82d0abf132457ba6c5b37aaf1203a --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_common.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-04-11 RiceChen the first version + * + */ + +#include +#include +#include "board.h" + +#include "mmu.h" +#include "ioremap.h" +#include "fsl_iomuxc.h" +#include "drv_common.h" + +void *imx6ull_get_periph_vaddr(rt_uint32_t paddr) +{ + return rt_ioremap((void *)paddr, sizeof(sizeof(rt_uint32_t))); +} + +void *imx6ull_get_periph_paddr(rt_uint32_t vaddr) +{ + return rt_hw_mmu_v2p(&mmu_info, (void *)vaddr); +} + +void imx6ull_gpio_init(const struct imx6ull_iomuxc *gpio) +{ + rt_uint32_t mux_reg_vaddr = 0; + rt_uint32_t input_reg_vaddr = 0; + rt_uint32_t config_reg_vaddr = 0; + + mux_reg_vaddr = (rt_uint32_t)(gpio->muxRegister ? (rt_uint32_t)imx6ull_get_periph_vaddr(gpio->muxRegister) : gpio->muxRegister); + input_reg_vaddr = (rt_uint32_t)(gpio->inputRegister ? (rt_uint32_t)imx6ull_get_periph_vaddr(gpio->inputRegister) : gpio->inputRegister); + config_reg_vaddr = (rt_uint32_t)(gpio->configRegister ? (rt_uint32_t)imx6ull_get_periph_vaddr(gpio->configRegister) : gpio->configRegister); + + IOMUXC_SetPinMux(mux_reg_vaddr, gpio->muxMode, input_reg_vaddr, gpio->inputDaisy, config_reg_vaddr, gpio->inputOnfield); + IOMUXC_SetPinConfig(mux_reg_vaddr, gpio->muxMode, input_reg_vaddr, gpio->inputDaisy, config_reg_vaddr, gpio->configValue); +} diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_common.h b/bsp/imx6ull-artpi-smart/drivers/drv_common.h new file mode 100644 index 0000000000000000000000000000000000000000..976beb22f303494479971d6ce245d34ee8709184 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_common.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-04-11 RiceChen the first version + * + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include + +struct imx6ull_iomuxc +{ + rt_uint32_t muxRegister; + rt_uint32_t muxMode; + rt_uint32_t inputRegister; + rt_uint32_t inputDaisy; + rt_uint32_t configRegister; + + rt_uint32_t inputOnfield; + + rt_uint32_t configValue; +}; + +void *imx6ull_get_periph_vaddr(rt_uint32_t paddr); +void *imx6ull_get_periph_paddr(rt_uint32_t vaddr); + +void imx6ull_gpio_init(const struct imx6ull_iomuxc *gpio); + +#endif \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_eth.c b/bsp/imx6ull-artpi-smart/drivers/drv_eth.c new file mode 100644 index 0000000000000000000000000000000000000000..74b3b5b1c2a3301cc38b87120cf0258888c1f825 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_eth.c @@ -0,0 +1,563 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-16 songchao support emac driver + * 2021-06-29 songchao add phy link detect + * 2021-08-13 songchao support dual mac and reduse copy + */ + +#include "drv_eth.h" +#define DBG_TAG "drv.enet" +#define DBG_LVL DBG_LOG +#include + +#define BSP_USING_IMX6ULL_ART_PI + +#if (defined(RT_USING_ENET1)) || (defined(RT_USING_ENET2)) + +#ifdef BSP_USING_IMX6ULL_ART_PI + +static struct imx6ull_iomuxc mdio_gpio[2] = +{ + {IOMUXC_GPIO1_IO06_ENET1_MDIO,0U,0xB029}, + {IOMUXC_GPIO1_IO07_ENET1_MDC,0U,0xB0E9} +}; +#else +static struct imx6ull_iomuxc mdio_gpio[2] = +{ + {IOMUXC_GPIO1_IO06_ENET2_MDIO,0U,0xB029}, + {IOMUXC_GPIO1_IO07_ENET2_MDC,0U,0xB0E9}, +}; +#endif +enum +{ +#ifdef RT_USING_ENET1 + DEV_ENET1, +#endif + +#ifdef RT_USING_ENET2 + DEV_ENET2, +#endif + + DEV_ENET_MAX, +}; + +static struct rt_imx6ul_ethps _imx6ul_eth_device[DEV_ENET_MAX] = +{ +#ifdef RT_USING_ENET1 + { + .dev_addr = {0xa8,0x5e,0x45,0x91,0x92,0x93}, + .mac_name = "e1", + .irq_name = "emac1_intr", + .enet_phy_base_addr = ENET1, + .irq_num = IMX_INT_ENET1, + .phy_num = ENET_PHY1, + .mac_num = 1, + .phy_base_addr = GPIO5, + .phy_gpio_pin = 9, + .phy_id = 7, + .buffConfig = + { + ENET_RXBD_NUM, + ENET_TXBD_NUM, + ENET_RXBUFF_ALIGN_SIZE, + ENET_TXBUFF_ALIGN_SIZE, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + ENET_RXBUFF_TOTAL_SIZE, + ENET_TXBUFF_TOTAL_SIZE + }, + .gpio = + { + {IOMUXC_SNVS_SNVS_TAMPER9_GPIO5_IO09,0U,0x110B0}, + {IOMUXC_ENET1_RX_DATA0_ENET1_RDATA00,0U,0xB0E9}, + {IOMUXC_ENET1_RX_DATA1_ENET1_RDATA01,0U,0xB0E9}, + {IOMUXC_ENET1_RX_EN_ENET1_RX_EN,0U,0xB0E9}, + {IOMUXC_ENET1_RX_ER_ENET1_RX_ER,0U,0xB0E9}, + {IOMUXC_ENET1_TX_CLK_ENET1_REF_CLK1,1U,0x00F0}, + {IOMUXC_ENET1_TX_DATA0_ENET1_TDATA00,0U,0xB0E9}, + {IOMUXC_ENET1_TX_DATA1_ENET1_TDATA01,0U,0xB0E9}, + {IOMUXC_ENET1_TX_EN_ENET1_TX_EN,0U,0xB0E9} + } + }, +#endif + +#ifdef RT_USING_ENET2 + { + .dev_addr = {0xa8,0x5e,0x45,0x01,0x02,0x03}, + .mac_name = "e2", + .irq_name = "emac2_intr", + .enet_phy_base_addr = ENET2, + .irq_num = IMX_INT_ENET2, + .phy_num = ENET_PHY2, + .mac_num = 2, + .phy_base_addr = GPIO5, + .phy_gpio_pin = 6, + .phy_id = 7, + .buffConfig = + { + ENET_RXBD_NUM, + ENET_TXBD_NUM, + ENET_RXBUFF_ALIGN_SIZE, + ENET_TXBUFF_ALIGN_SIZE, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + ENET_RXBUFF_TOTAL_SIZE, + ENET_TXBUFF_TOTAL_SIZE + }, + .gpio = + { + {IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06,0U,0x110B0}, + {IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00,0U,0xB0E9}, + {IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01,0U,0xB0E9}, + {IOMUXC_ENET2_RX_EN_ENET2_RX_EN,0U,0xB0E9}, + {IOMUXC_ENET2_RX_ER_ENET2_RX_ER,0U,0xB0E9}, + {IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2,1U,0x00F0}, + {IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00,0U,0xB0E9}, + {IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01,0U,0xB0E9}, + {IOMUXC_ENET2_TX_EN_ENET2_TX_EN,0U,0xB0E9} + } + + }, +#endif +}; + +void imx6ul_eth_link_change(struct rt_imx6ul_ethps *imx6ul_device,rt_bool_t up) +{ + if(up) + { + LOG_D("enet%d link up\n",imx6ul_device->mac_num); + eth_device_linkchange(&imx6ul_device->parent, RT_TRUE); + imx6ul_device->phy_link_status = RT_TRUE; + } + else + { + LOG_D("enet%d link down\n",imx6ul_device->mac_num); + eth_device_linkchange(&imx6ul_device->parent, RT_FALSE); + imx6ul_device->phy_link_status = RT_FALSE; + } +} + +void ENET_InitModuleClock(void) +{ + const clock_enet_pll_config_t config = {true, true, false, 1, 1}; + CLOCK_InitEnetPll(&config); +} + +rt_err_t enet_buffer_init(enet_buffer_config_t *buffConfig) +{ + void *tx_buff_addr = RT_NULL; + void *rx_buff_addr = RT_NULL; + void *tx_bd_addr = RT_NULL; + void *rx_bd_addr = RT_NULL; + + if(((SYS_PAGE_SIZE<rxBufferTotalSize)|| + ((SYS_PAGE_SIZE<txBufferTotalSize)) + { + LOG_E("ERROR: alloc mem not enough for enet driver\n"); + return RT_ERROR; + } + rx_buff_addr = rt_pages_alloc(RX_BUFFER_INDEX_NUM); + if(!rx_buff_addr) + { + LOG_E("ERROR: rx buff page alloc failed\n"); + return RT_ERROR; + } + buffConfig->rxBufferAlign = (void *)rt_ioremap_nocache(virtual_to_physical(rx_buff_addr), (SYS_PAGE_SIZE<rxPhyBufferAlign = (void *)virtual_to_physical(rx_buff_addr); + + tx_buff_addr = rt_pages_alloc(TX_BUFFER_INDEX_NUM); + if(!tx_buff_addr) + { + LOG_E("ERROR: tx buff page alloc failed\n"); + return RT_ERROR; + } + buffConfig->txBufferAlign = (void *)rt_ioremap_nocache(virtual_to_physical(tx_buff_addr), (SYS_PAGE_SIZE<txPhyBufferAlign = (void *)virtual_to_physical(tx_buff_addr); + + rx_bd_addr = rt_pages_alloc(RX_BD_INDEX_NUM); + if(!rx_bd_addr) + { + LOG_E("ERROR: rx bd page alloc failed\n"); + return RT_ERROR; + } + buffConfig->rxBdStartAddrAlign = (void *)rt_ioremap_nocache(virtual_to_physical(rx_bd_addr), (SYS_PAGE_SIZE<rxPhyBdStartAddrAlign = virtual_to_physical(rx_bd_addr); + + tx_bd_addr = rt_pages_alloc(TX_BD_INDEX_NUM); + if(!tx_bd_addr) + { + LOG_E("ERROR: tx bd page alloc failed\n"); + return RT_ERROR; + } + buffConfig->txBdStartAddrAlign = (void *)rt_ioremap_nocache(virtual_to_physical(tx_bd_addr), (SYS_PAGE_SIZE<txPhyBdStartAddrAlign = virtual_to_physical(tx_bd_addr); + + return RT_EOK; +} + +/* EMAC initialization function */ +static rt_err_t rt_imx6ul_eth_init(rt_device_t dev) +{ + rt_err_t state; + struct rt_imx6ul_ethps *imx6ul_device = (struct rt_imx6ul_ethps *)dev; + ENET_Type *base_addr = RT_NULL; + enet_config_t *config; + enet_handle_t *handle; + enet_buffer_config_t *buffConfig; + rt_uint32_t reg_value; + + imx6ul_device->enet_virtual_base_addr = (ENET_Type *)rt_ioremap((void *)imx6ul_device->enet_phy_base_addr,SYS_PAGE_SIZE); + base_addr = imx6ul_device->enet_virtual_base_addr; + config = &imx6ul_device->config; + handle = &imx6ul_device->handle; + buffConfig = &imx6ul_device->buffConfig; + + for (int i=0; igpio); i++) + { + imx6ull_gpio_init(&imx6ul_device->gpio[i]); + } + + IOMUXC_GPR_Type *GPR1 = (IOMUXC_GPR_Type *)rt_ioremap((void *)IOMUXC_GPR,0x1000); + if(imx6ul_device->mac_num == 1) + { + reg_value = GPR1->GPR1; + reg_value &= ~(IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK + | IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK); + reg_value |= IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(1); + reg_value |= IOMUXC_GPR_GPR1_ENET1_CLK_SEL(0); + GPR1->GPR1 = reg_value; + } + else if(imx6ul_device->mac_num == 2) + { + reg_value = GPR1->GPR1; + reg_value &= ~(IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK + | IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK); + reg_value |= IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(1); + reg_value |= IOMUXC_GPR_GPR1_ENET2_CLK_SEL(0); + GPR1->GPR1 = reg_value; + } + + ENET_InitModuleClock(); + ENET_GetDefaultConfig(config); + config->interrupt |= (ENET_RX_INTERRUPT); + state = enet_buffer_init(buffConfig); + if(state != RT_EOK) + { + return state; + } + ENET_Init(base_addr, handle, config, buffConfig, &imx6ul_device->dev_addr[0], SYS_CLOCK_HZ); + ENET_ActiveRead(base_addr); + rt_hw_interrupt_install(imx6ul_device->irq_num, (rt_isr_handler_t)ENET_DriverIRQHandler, (void *)base_addr,imx6ul_device->irq_name); + rt_hw_interrupt_umask(imx6ul_device->irq_num); + + return RT_EOK; +} + +static rt_err_t rt_imx6ul_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_imx6ul_eth_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_imx6ul_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + return 0; +} + +static rt_size_t rt_imx6ul_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + return 0; +} + +static rt_err_t rt_imx6ul_eth_control(rt_device_t dev, int cmd, void *args) +{ + struct rt_imx6ul_ethps *imx6ul_device = (struct rt_imx6ul_ethps *)dev; + switch (cmd) + { + case NIOCTL_GADDR: + /* get MAC address */ + if (args) + { + rt_memcpy(args, imx6ul_device->dev_addr, MAX_ADDR_LEN); + } + else + { + return -RT_ERROR; + } + break; + + default : + break; + } + return RT_EOK; +} + +static status_t read_data_from_eth(rt_device_t dev,void *read_data,uint16_t *read_length) +{ + status_t status = 0; + uint16_t length = 0; + ENET_Type *base_addr = RT_NULL; + enet_config_t *config; + enet_handle_t *handle; + enet_buffer_config_t *buffConfig; + struct rt_imx6ul_ethps *imx6ul_device = (struct rt_imx6ul_ethps *)dev; + base_addr = imx6ul_device->enet_virtual_base_addr; + config = &imx6ul_device->config; + handle = &imx6ul_device->handle; + buffConfig = &imx6ul_device->buffConfig; + /* Get the Frame size */ + status = ENET_ReadFrame(base_addr,handle,config,read_data,&length); + if((status == kStatus_ENET_RxFrameEmpty)||(status == kStatus_ENET_RxFrameError)) + { + ENET_EnableInterrupts(base_addr,ENET_RX_INTERRUPT); + if(status == kStatus_ENET_RxFrameError) + { + /*recv error happend reinitialize mac*/ + ENET_Init(base_addr, handle, config, buffConfig, &imx6ul_device->dev_addr[0], SYS_CLOCK_HZ); + ENET_ActiveRead(base_addr); + return kStatus_ENET_RxFrameError; + } + else if(status == kStatus_ENET_RxFrameEmpty) + { + return kStatus_ENET_RxFrameEmpty; + } + } + *read_length = length; + return status; +} + +/* transmit data*/ +rt_err_t rt_imx6ul_eth_tx(rt_device_t dev, struct pbuf *p) +{ + rt_err_t ret = RT_ERROR; + struct pbuf *q = RT_NULL; + uint16_t offset = 0; + uint32_t last_flag = 0; + status_t status; + ENET_Type *base_addr = RT_NULL; + enet_handle_t *handle; + struct rt_imx6ul_ethps *imx6ul_device = (struct rt_imx6ul_ethps *)dev; + base_addr = imx6ul_device->enet_virtual_base_addr; + handle = &imx6ul_device->handle; + RT_ASSERT(p); + + for(q = p;q != RT_NULL;q=q->next) + { + if(q->next == RT_NULL) + { + last_flag = 1; + } + else + { + last_flag = 0; + } + status = ENET_SendFrame(base_addr, handle, q->payload, q->len,last_flag); + offset = offset + q->len; + if(status == kStatus_Success) + { + } + else + { + return RT_ERROR; + } + } + if(offset > ENET_FRAME_MAX_FRAMELEN) + { + LOG_E("net error send length %d exceed max length\n",offset); + } + return ret; +} + +struct pbuf *rt_imx6ul_eth_rx(rt_device_t dev) +{ + static struct pbuf *p_s = RT_NULL; + struct pbuf *p = RT_NULL; + status_t status; + uint16_t length = 0; + + if(p_s == RT_NULL) + { + p_s = pbuf_alloc(PBUF_RAW, ENET_FRAME_MAX_FRAMELEN, PBUF_POOL); + if(p_s == RT_NULL) + { + return RT_NULL; + } + } + p = p_s; + status = read_data_from_eth(dev,p->payload,&length); + if(status == kStatus_ENET_RxFrameEmpty) + { + return RT_NULL; + } + else if(status == kStatus_ENET_RxFrameError) + { + return RT_NULL; + } + if(length > ENET_FRAME_MAX_FRAMELEN) + { + LOG_E("net error recv length %d exceed max length\n",length); + return RT_NULL; + } + pbuf_realloc(p, length); + p_s = RT_NULL; + return p; +} + +int32_t get_instance_by_base(void *base) +{ + int32_t i = 0; + int32_t instance = 0; + for(i = 0; i < DEV_ENET_MAX; i ++) + { + if((void *)_imx6ul_eth_device[i].enet_virtual_base_addr == base) + { + break; + } + } + if(i == DEV_ENET_MAX) + { + return -1; + } + return instance; + +} +void rx_enet_callback(void *base) +{ + int32_t instance = 0; + instance = get_instance_by_base(base); + if(instance == -1) + { + LOG_E("interrput match base addr error \n"); + return; + } + eth_device_ready(&(_imx6ul_eth_device[instance].parent)); + ENET_DisableInterrupts(base,ENET_RX_INTERRUPT); +} + +void tx_enet_callback(void *base) +{ + ENET_DisableInterrupts(base,ENET_TX_INTERRUPT); +} + +/*phy link detect thread*/ +static void phy_detect_thread_entry(void *param) +{ + bool link = false; + phy_speed_t speed; + phy_duplex_t duplex; + ENET_Type *base_addr = RT_NULL; + struct rt_imx6ul_ethps *imx6ul_device = (struct rt_imx6ul_ethps *)param; + base_addr = imx6ul_device->enet_virtual_base_addr; + + phy_reset(imx6ul_device->phy_base_addr,imx6ul_device->phy_gpio_pin); + PHY_Init(base_addr, imx6ul_device->phy_num, SYS_CLOCK_HZ,imx6ul_device->phy_id); + PHY_GetLinkStatus(base_addr, imx6ul_device->phy_num, &link); + if (link) + { + /* Get the actual PHY link speed. */ + PHY_GetLinkSpeedDuplex(base_addr, imx6ul_device->phy_num, &speed, &duplex); + /* Change the MII speed and duplex for actual link status. */ + imx6ul_device->config.miiSpeed = (enet_mii_speed_t)speed; + imx6ul_device->config.miiDuplex = (enet_mii_duplex_t)duplex; + } + else + { + LOG_E("\r\nPHY Link down, please check the cable connection and link partner setting.\r\n"); + } + + while(1) + { + PHY_GetLinkStatus(base_addr, imx6ul_device->phy_num, &link); + if(link != imx6ul_device->phy_link_status) + { + if(link == true) + { + PHY_StartNegotiation(base_addr,imx6ul_device->phy_num); + + } + imx6ul_eth_link_change(imx6ul_device,link); + } + rt_thread_delay(DETECT_DELAY_ONE_SECOND); + } +} + +_internal_ro struct rt_device_ops _k_enet_ops = +{ + rt_imx6ul_eth_init, + rt_imx6ul_eth_open, + rt_imx6ul_eth_close, + rt_imx6ul_eth_read, + rt_imx6ul_eth_write, + rt_imx6ul_eth_control, +}; + +static int imx6ul_eth_init(void) +{ + rt_err_t state = RT_EOK; + char link_detect[10]; + + #if 1 + imx6ull_gpio_init(&mdio_gpio[0]); + imx6ull_gpio_init(&mdio_gpio[1]); + #endif + + for (int idx=0; idx +#include +#include "fsl_phy.h" +#include "imx6ull.h" +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_ADDR_LEN 6 +struct rt_imx6ul_ethps +{ + /* inherit from ethernet device */ + struct eth_device parent; + /* interface address info, hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + /* ETH_Speed */ + uint32_t ETH_Speed; + /* ETH_Duplex_Mode */ + uint32_t ETH_Mode; + rt_bool_t phy_link_status; + const char *mac_name; + const char *irq_name; + enum _imx_interrupts irq_num; + uint8_t phy_num; + const ENET_Type *enet_phy_base_addr; + ENET_Type *enet_virtual_base_addr; + uint32_t mac_num; + enet_buffer_config_t buffConfig; + enet_config_t config; + enet_handle_t handle; + struct imx6ull_iomuxc gpio[9]; + GPIO_Type *phy_base_addr; + uint32_t phy_gpio_pin; + uint32_t phy_id; +}; + +int32_t get_instance_by_base(void *base); +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_ETH_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_i2c.c b/bsp/imx6ull-artpi-smart/drivers/drv_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..b937e74297078f96b68ffd58d8380d35a388a193 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_i2c.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 Lyons first version + * 2021-06-23 RiceChen refactor + */ + +#include +#include + +#ifdef BSP_USING_I2C + +#define LOG_TAG "drv.i2c" +#include + +#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) +#error "Please define at least one BSP_USING_I2Cx" +#endif + +#include "fsl_iomuxc.h" +#include "drv_i2c.h" + +static struct imx6ull_i2c_config i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C2 + I2C2_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C3 + I2C3_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C4 + I2C4_BUS_CONFIG, +#endif +}; + +static struct imx6ull_i2c_bus i2c_obj[sizeof(i2c_config) / sizeof(i2c_config[0])]; +static char i2c_buff_temp[4][1024]; +extern uint32_t I2C_GetInstance(I2C_Type *base); + +#ifdef IMX_I2C_IRQ_MODE +static uint32_t g_MasterCompletionFlag[4] = {0,0,0,0}; +static void i2c_master_callback(I2C_Type *base, i2c_master_handle_t *handle, status_t status, void *userData) +{ + /* Signal transfer success when received success status. */ + + uint32_t instance = I2C_GetInstance(imx6ull_get_periph_paddr((uint32_t)base)); + if (status == kStatus_Success) + { + g_MasterCompletionFlag[instance-1] = 1; + } +} +#endif + +static rt_size_t imx6ull_i2c_mst_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + struct imx6ull_i2c_bus *i2c_bus = RT_NULL; + static i2c_master_transfer_t xfer = {0}; + rt_size_t i = 0; + RT_ASSERT(bus != RT_NULL); +#ifdef IMX_I2C_IRQ_MODE + uint32_t timeout_cnt = 100; +#endif + uint32_t instance = 0; + i2c_bus = (struct imx6ull_i2c_bus *)bus; + + instance = I2C_GetInstance(imx6ull_get_periph_paddr((uint32_t)i2c_bus->config->I2C)); + for(i = 0 ;i < num; i++) + { + if(msgs[i].flags & RT_I2C_RD) + { + xfer.flags = kI2C_TransferNoStartFlag; + xfer.slaveAddress = msgs[i].addr; + xfer.direction = kI2C_Read; + xfer.subaddress = 0; + xfer.subaddressSize = 0; + xfer.data = (uint8_t *volatile)i2c_buff_temp[instance - 1]; + xfer.dataSize = msgs[i].len ; + +#ifdef IMX_I2C_IRQ_MODE + I2C_MasterTransferNonBlocking(i2c_bus->config->I2C, &i2c_bus->config->master_handle,&xfer); + while(!g_MasterCompletionFlag[instance - 1]) + { + rt_thread_delay(1); + timeout_cnt--; + if(timeout_cnt == 0) + { + break; + } + } + timeout_cnt = 100; + g_MasterCompletionFlag[instance - 1] = 0; +#else + I2C_MasterTransferBlocking(i2c_bus->config->I2C, &xfer); +#endif + rt_memcpy(msgs[i].buf,i2c_buff_temp[instance - 1],msgs[i].len); + } + else + { + xfer.flags = kI2C_TransferNoStartFlag; + xfer.slaveAddress = msgs[i].addr; + xfer.direction = kI2C_Write; + xfer.subaddress = 0; + xfer.subaddressSize = 0; + xfer.data = (uint8_t *volatile)i2c_buff_temp[instance - 1]; + xfer.dataSize = msgs[i].len; + rt_memcpy(i2c_buff_temp[instance - 1],msgs[i].buf,msgs[i].len); + +#ifdef IMX_I2C_IRQ_MODE + I2C_MasterTransferNonBlocking(i2c_bus->config->I2C, &i2c_bus->config->master_handle,&xfer); + while(!g_MasterCompletionFlag[instance - 1]) + { + timeout_cnt--; + rt_thread_delay(1); + if(timeout_cnt == 0) + { + break; + } + } + timeout_cnt = 100; + g_MasterCompletionFlag[instance - 1] = 0; +#else + I2C_MasterTransferBlocking(i2c_bus->config->I2C, &xfer); +#endif + } + } + + return i; +} + +static rt_err_t imx6ull_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t cmd, rt_uint32_t arg) +{ + return RT_EOK; +} + +static rt_err_t imx6ull_i2c_gpio_init(struct imx6ull_i2c_bus *bus) +{ + struct imx6ull_i2c_bus *i2c_bus = RT_NULL; + + i2c_bus = (struct imx6ull_i2c_bus *)bus; + + imx6ull_gpio_init(&i2c_bus->config->scl_gpio); + imx6ull_gpio_init(&i2c_bus->config->sda_gpio); + return RT_EOK; + +} + +#ifdef RT_USING_DEVICE_OPS +static const struct rt_i2c_bus_device_ops imx6ull_i2c_ops = +{ + .master_xfer = imx6ull_i2c_mst_xfer, + .slave_xfer = RT_NULL, + .i2c_bus_control = imx6ull_i2c_bus_control, +}; +#endif + +extern void I2C_DriverIRQHandler(int irq, void *base); +int rt_hw_i2c_init(void) +{ + rt_uint16_t obj_num = 0; + rt_uint32_t src_clock; + i2c_master_config_t masterConfig = {0}; + + obj_num = sizeof(i2c_config) / sizeof(i2c_config[0]); + + src_clock = (CLOCK_GetFreq(kCLOCK_IpgClk) / (CLOCK_GetDiv(kCLOCK_PerclkDiv) + 1U)); + + for(int i = 0; i < obj_num; i++) + { + i2c_obj[i].config = &i2c_config[i]; + i2c_obj[i].config->I2C = (I2C_Type *)imx6ull_get_periph_vaddr((rt_uint32_t)(i2c_obj[i].config->I2C)); + i2c_obj[i].parent.ops = &imx6ull_i2c_ops; + imx6ull_i2c_gpio_init(&i2c_obj[i]); + + I2C_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = i2c_config[i].baud_rate; + + CLOCK_EnableClock(i2c_obj[i].config->clk_ip_name); + + I2C_MasterInit(i2c_obj[i].config->I2C, &masterConfig, src_clock); + + rt_i2c_bus_device_register(&i2c_obj[i].parent, i2c_obj[i].config->name); + +#ifdef IMX_I2C_IRQ_MODE + I2C_MasterTransferCreateHandle(imx6ull_get_periph_paddr((uint32_t)(i2c_obj[i].config->I2C)), &i2c_obj[i].config->master_handle, i2c_master_callback, NULL); + rt_hw_interrupt_install(i2c_obj[i].config->irq_num, (rt_isr_handler_t)I2C_DriverIRQHandler, (void *)i2c_obj[i].config->I2C,i2c_obj[i].config->name); +#endif + + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_i2c.h b/bsp/imx6ull-artpi-smart/drivers/drv_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..4471683b598004b3de9ea9cb1c24faa1690b0fdb --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_i2c.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 Lyons first version + * 2021-06-23 RiceChen refactor + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include "drv_common.h" + +#include "fsl_iomuxc.h" +#include "fsl_clock.h" +#include "fsl_i2c.h" + +#define IMX_I2C_IRQ_MODE + +struct imx6ull_i2c_config +{ + I2C_Type *I2C; + char *name; + rt_uint32_t baud_rate; + rt_uint32_t clk_ip_name; + rt_uint32_t irq_num; + + struct imx6ull_iomuxc scl_gpio; + struct imx6ull_iomuxc sda_gpio; + + i2c_master_handle_t master_handle; +}; + +struct imx6ull_i2c_bus +{ + struct rt_i2c_bus_device parent; + struct imx6ull_i2c_config *config; +}; + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .I2C = I2C1, \ + .name = "i2c1", \ + .clk_ip_name = kCLOCK_I2c1S, \ + .baud_rate = I2C1_BAUD_RATE, \ + .irq_num = IMX_INT_I2C1, \ + .scl_gpio = {IOMUXC_UART4_TX_DATA_I2C1_SCL, 1, 0x70B0}, \ + .sda_gpio = {IOMUXC_UART4_RX_DATA_I2C1_SDA, 1, 0x70B0}, \ + } +#endif /* BSP_USING_I2C1 */ + +#ifdef BSP_USING_I2C2 +#define I2C2_BUS_CONFIG \ + { \ + .I2C = I2C2, \ + .name = "i2c2", \ + .clk_ip_name = kCLOCK_I2c2S, \ + .baud_rate = I2C2_BAUD_RATE, \ + .irq_num = IMX_INT_I2C2, \ + .scl_gpio = {IOMUXC_UART5_TX_DATA_I2C2_SCL, 1, 0x70B0}, \ + .sda_gpio = {IOMUXC_UART5_RX_DATA_I2C2_SDA, 1, 0x70B0}, \ + } +#endif /* BSP_USING_I2C2 */ + +#ifdef BSP_USING_I2C3 +#define I2C3_BUS_CONFIG \ + { \ + .I2C = I2C3, \ + .name = "i2c3", \ + .clk_ip_name = kCLOCK_I2c3S, \ + .baud_rate = I2C3_BAUD_RATE, \ + .irq_num = IMX_INT_I2C3, \ + .scl_gpio = {IOMUXC_ENET2_RX_DATA0_I2C3_SCL, 1, 0x70B0}, \ + .sda_gpio = {IOMUXC_ENET2_RX_DATA1_I2C3_SDA, 1, 0x70B0}, \ + } +#endif /* BSP_USING_I2C3 */ + +#ifdef BSP_USING_I2C4 +#define I2C4_BUS_CONFIG \ + { \ + .I2C = I2C4, \ + .name = "i2c4", \ + .clk_ip_name = kCLOCK_I2c4S, \ + .baud_rate = I2C4_BAUD_RATE, \ + .irq_num = IMX_INT_I2C4, \ + .scl_gpio = {IOMUXC_UART2_TX_DATA_I2C4_SCL, 1, 0x70B0}, \ + .sda_gpio = {IOMUXC_UART2_RX_DATA_I2C4_SDA, 1, 0x70B0}, \ + } +#endif /* BSP_USING_I2C4 */ + +#endif \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_lcd.c b/bsp/imx6ull-artpi-smart/drivers/drv_lcd.c new file mode 100644 index 0000000000000000000000000000000000000000..6513bb1d8857412066bd2a78f2b38d4886e8a6fe --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_lcd.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-11 Lyons first version + * 2021-06-24 RiceChen refactor + * 2021-07-28 songchao add cmd + */ + +#include +#include +#include + +#ifdef BSP_USING_LCD + +#define LOG_TAG "drv.lcd" +#include + +#include "fsl_iomuxc.h" +#include "drv_lcd.h" +#include +#include "rt_lcd.h" + +static struct imx6ull_lcd_config _lcd_config = LCD_BUS_CONFIG; +static struct imx6ull_lcd_bus _lcd_obj; + +static rt_err_t imx6ull_elcd_init(rt_device_t device) +{ + struct imx6ull_lcd_bus *elcd_dev = RT_NULL; + clock_video_pll_config_t pll_config; + elcdif_rgb_mode_config_t lcd_config; + + RT_ASSERT(device != RT_NULL); + + elcd_dev = (struct imx6ull_lcd_bus *)device; + ELCDIF_Reset(elcd_dev->config->ELCDIF); + pll_config.loopDivider = 32; + pll_config.postDivider = LCD_PLL_DIV; + + pll_config.numerator = 0; + pll_config.denominator = 0; + + CLOCK_InitVideoPll(&pll_config); + + lcd_config.hfp = LCD_HFP; + lcd_config.vfp = LCD_VFP; + lcd_config.hbp = LCD_HBP; + lcd_config.vbp = LCD_VBP; + lcd_config.hsw = LCD_HSW; + lcd_config.vsw = LCD_VSW; + + lcd_config.polarityFlags = kELCDIF_DataEnableActiveHigh | + kELCDIF_VsyncActiveLow | + kELCDIF_HsyncActiveLow | + kELCDIF_DriveDataOnRisingClkEdge; + + switch(elcd_dev->info.pixel_format) + { + case RTGRAPHIC_PIXEL_FORMAT_RGB888: + lcd_config.pixelFormat = kELCDIF_PixelFormatRGB888; + break; + case RTGRAPHIC_PIXEL_FORMAT_RGB565: + lcd_config.pixelFormat = kELCDIF_PixelFormatRGB565; + break; + default: + LOG_E("not support this pixel_format %d\n",elcd_dev->info.pixel_format); + return RT_ERROR; + } + + lcd_config.panelWidth = elcd_dev->info.width; + lcd_config.panelHeight = elcd_dev->info.height; + lcd_config.bufferAddr = (uint32_t)elcd_dev->fb_phy; + lcd_config.dataBus = kELCDIF_DataBus24Bit; + + ELCDIF_RgbModeInit(elcd_dev->config->ELCDIF, &lcd_config); + ELCDIF_RgbModeStart(elcd_dev->config->ELCDIF); + + return RT_EOK; +} +static rt_err_t imx6ull_elcd_control(rt_device_t device, int cmd, void *args) +{ + struct imx6ull_lcd_bus *elcd_dev = RT_NULL; + int mem_size = 0; + + RT_ASSERT(device != RT_NULL); + + elcd_dev = (struct imx6ull_lcd_bus *)device; + switch(cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + { + mem_size = elcd_dev->info.width * elcd_dev->info.height * elcd_dev->info.bits_per_pixel / 8; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)(_lcd_obj.info.framebuffer), mem_size); + break; + } + case RTGRAPHIC_CTRL_POWERON: + { + rt_pin_write(IMX6ULL_LCD_BL_PIN, PIN_HIGH); + break; + } + case RTGRAPHIC_CTRL_POWEROFF: + { + rt_pin_write(IMX6ULL_LCD_BL_PIN, PIN_LOW); + break; + } + case RTGRAPHIC_CTRL_GET_INFO: + { + struct lcd_info *info = (struct lcd_info *)args; + RT_ASSERT(info != RT_NULL); + rt_memcpy(&info->graphic, &elcd_dev->info, sizeof(struct rt_device_graphic_info)); + info->screen.shamem_len = elcd_dev->info.width * elcd_dev->info.height * elcd_dev->info.bits_per_pixel / 8; + info->screen.shamem_start = (rt_uint32_t)lwp_map_user_phy(lwp_self(), RT_NULL, + elcd_dev->fb_phy, + info->screen.shamem_len, 1); + break; + } + case RTGRAPHIC_CTRL_SET_MODE: + { + break; + } + case FBIOGET_FSCREENINFO: + { + struct fb_fix_screeninfo *info = (struct fb_fix_screeninfo *)args; + rt_memcpy(info->id, elcd_dev->config->name, (strlen(elcd_dev->config->name)+1)); + info->smem_len = elcd_dev->info.width * elcd_dev->info.height * elcd_dev->info.bits_per_pixel / 8; + info->smem_start = (rt_uint32_t)lwp_map_user_phy(lwp_self(), RT_NULL, + elcd_dev->fb_phy, + info->smem_len, 1); + info->line_length = elcd_dev->info.width * 2; + break; + } + case FBIOGET_VSCREENINFO: + { + struct fb_var_screeninfo *info = (struct fb_var_screeninfo *)args; + info->bits_per_pixel = elcd_dev->info.bits_per_pixel; + info->xres = elcd_dev->info.width; + info->yres = elcd_dev->info.height; + break; + } + + } + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops elcd_ops = +{ + imx6ull_elcd_init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + imx6ull_elcd_control, +}; +#endif + +int rt_hw_elcd_init(void) +{ + rt_err_t ret = 0; + + _lcd_config.ELCDIF = (LCDIF_Type *)imx6ull_get_periph_vaddr((rt_uint32_t)(_lcd_config.ELCDIF)); + _lcd_config.lcd_mux_base = (rt_uint32_t)imx6ull_get_periph_vaddr((rt_uint32_t)(_lcd_config.lcd_mux_base)); + _lcd_config.lcd_cfg_base = (rt_uint32_t)imx6ull_get_periph_vaddr((rt_uint32_t)(_lcd_config.lcd_cfg_base)); + + for(int i = 0; i < LCD_GPIO_MAX; i++) + { + IOMUXC_SetPinMux((_lcd_config.lcd_mux_base + i * 4), + 0x0U, 0x0U, 0x0U, (_lcd_config.lcd_cfg_base + i * 4), 0); + IOMUXC_SetPinConfig((_lcd_config.lcd_mux_base + i * 4), + 0x0U, 0x0U, 0x0U, (_lcd_config.lcd_cfg_base + i * 4), 0xB9); + } + + CLOCK_EnableClock(_lcd_config.apd_clk_name); + CLOCK_EnableClock(_lcd_config.pix_clk_name); + + _lcd_obj.config = &_lcd_config; + + _lcd_obj.fb_virt = rt_pages_alloc(rt_page_bits(LCD_BUF_SIZE)); + _lcd_obj.fb_phy = _lcd_obj.fb_virt + PV_OFFSET; + + LOG_D("fb address => 0x%08x\n", _lcd_obj.fb_phy); + if(_lcd_obj.fb_phy == RT_NULL) + { + LOG_E("initialize frame buffer failed!\n"); + return -RT_ERROR; + } + + _lcd_obj.info.width = LCD_WIDTH; + _lcd_obj.info.height = LCD_HEIGHT; + _lcd_obj.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; + _lcd_obj.info.bits_per_pixel = LCD_BITS_PER_PIXEL; + _lcd_obj.info.framebuffer = (void *)_lcd_obj.fb_virt; + + _lcd_obj.parent.type = RT_Device_Class_Graphic; + +#ifdef RT_USING_DEVICE_OPS + _lcd_obj.parent.ops = &elcd_ops; +#else + _lcd_obj.parent.init = imx6ull_elcd_init; + _lcd_obj.parent.open = RT_NULL; + _lcd_obj.parent.close = RT_NULL; + _lcd_obj.parent.read = RT_NULL; + _lcd_obj.parent.write = RT_NULL; + _lcd_obj.parent.control = imx6ull_elcd_control; +#endif + + _lcd_obj.parent.user_data = (void *)&_lcd_obj.info; + + ret = rt_device_register(&_lcd_obj.parent, _lcd_obj.config->name, RT_DEVICE_FLAG_RDWR); + + /* LCD_BL */ + rt_pin_mode(IMX6ULL_LCD_BL_PIN, PIN_MODE_OUTPUT); + rt_pin_write(IMX6ULL_LCD_BL_PIN, PIN_HIGH); + + rt_memset((rt_uint8_t *)_lcd_obj.fb_virt, 0xff, LCD_BUF_SIZE); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_elcd_init); + +#endif + diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_lcd.h b/bsp/imx6ull-artpi-smart/drivers/drv_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..19bd1800c64405b125fe18decf28e564b1fe5eda --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_lcd.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-11 Lyons first version + * 2021-06-24 RiceChen refactor + */ + +#ifndef __DRV_LCD_H__ +#define __DRV_LCD_H__ + +#include +#include "drv_pin.h" +#include "drv_common.h" + +#include "fsl_iomuxc.h" +#include "fsl_clock.h" +#include "fsl_elcdif.h" + +#define LCD_GPIO_MAX 29 +#define LCD_MUX_BASE 0x020E0104U +#define LCD_CONFIG_BASE 0x020E0390U + +#define LCD_WIDTH BSP_LCD_WIDTH +#define LCD_HEIGHT BSP_LCD_HEIGHT +#define LCD_VSW BSP_LCD_VSW +#define LCD_VBP BSP_LCD_VBP +#define LCD_VFP BSP_LCD_VFP +#define LCD_HSW BSP_LCD_HSW +#define LCD_HBP BSP_LCD_HBP +#define LCD_HFP BSP_LCD_HFP +#define LCD_PLL_DIV BSP_LCD_PLL_DIV + +#define LCD_BITS_PER_PIXEL 32 +#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8) + +#define IMX6ULL_LCD_BL_PIN GET_PIN(1, 8) + +struct fb_fix_screen_info +{ + rt_uint32_t shamem_start; + rt_uint32_t shamem_len; +}; + +struct lcd_info +{ + struct rt_device_graphic_info graphic; + struct fb_fix_screen_info screen; +}; + +struct imx6ull_lcd_config +{ + LCDIF_Type *ELCDIF; + char *name; + + rt_uint32_t apd_clk_name; + rt_uint32_t pix_clk_name; + + rt_uint32_t lcd_mux_base; + rt_uint32_t lcd_cfg_base; +}; + +struct imx6ull_lcd_bus +{ + struct rt_device parent; + struct rt_device_graphic_info info; + + struct imx6ull_lcd_config *config; + + rt_uint8_t *fb_phy; + rt_uint8_t *fb_virt; +}; + +#ifdef BSP_USING_LCD +#define LCD_BUS_CONFIG \ + { \ + .ELCDIF = LCDIF, \ + .name = "lcd", \ + .apd_clk_name = kCLOCK_Lcd, \ + .pix_clk_name = kCLOCK_Lcdif1, \ + .lcd_mux_base = LCD_MUX_BASE, \ + .lcd_cfg_base = LCD_CONFIG_BASE, \ + } +#endif /* BSP_USING_LCD */ + + +#endif diff --git a/components/lwp/lwp_mem.h b/bsp/imx6ull-artpi-smart/drivers/drv_log.h similarity index 31% rename from components/lwp/lwp_mem.h rename to bsp/imx6ull-artpi-smart/drivers/drv_log.h index 8d333cfe4f71244a5ce17483891d157645d71d0a..f126da0de324c2fe0682d4272f79588812b9dbd8 100644 --- a/components/lwp/lwp_mem.h +++ b/bsp/imx6ull-artpi-smart/drivers/drv_log.h @@ -5,17 +5,23 @@ * * Change Logs: * Date Author Notes - * 2018-06-10 Bernard first version + * 2021-01-03 RiceChen first version */ -#ifndef __LWP_MEM_H__ -#define __LWP_MEM_H__ +/* + * NOTE: DO NOT include this file on the header file. + */ -extern void rt_lwp_mem_init(struct rt_lwp *lwp); -extern void rt_lwp_mem_deinit(struct rt_lwp *lwp); +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ -extern void *rt_lwp_mem_malloc(rt_uint32_t size); -extern void rt_lwp_mem_free(void *addr); -extern void *rt_lwp_mem_realloc(void *rmem, rt_size_t newsize); +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ -#endif +#include \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_pin.c b/bsp/imx6ull-artpi-smart/drivers/drv_pin.c new file mode 100644 index 0000000000000000000000000000000000000000..a804d6b9967654dba016b39ec6ddfcad22eeb8ca --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_pin.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-13 Lyons edit and remove irq setting + * 2021-06-23 RiceChen refactor gpio driver and support gpio IRQ + */ + +#include +#include + +#include "drv_pin.h" +#include "drv_common.h" +#include "fsl_gpio.h" +#include "fsl_iomuxc.h" + +rt_uint32_t iomuxc_base = IOMUXC_BASE; +rt_uint32_t iomuxc_snvs_base = IOMUXC_SNVS_BASE; + +struct pin_mask +{ + GPIO_Type *gpio; + rt_int32_t valid_mask; + clock_ip_name_t gpio_clock; +}; + +struct pin_mask mask_tab[5] = +{ + {GPIO1, 0xffffffff, kCLOCK_Gpio1}, /* GPIO1 */ + {GPIO2, 0x003fffff, kCLOCK_Gpio2}, /* GPIO2 */ + {GPIO3, 0x1fffffff, kCLOCK_Gpio3}, /* GPIO3,29~31 not supported */ + {GPIO4, 0x1fffffff, kCLOCK_Gpio4}, /* GPIO4,29~31 not supported */ + {GPIO5, 0x00000fff, kCLOCK_Gpio5} /* GPIO5,12~31 not supported */ +}; + +const rt_int8_t gpio_reg_offset[5][32] = +{ + { 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,}, + {32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 94, 95, 96, 97, 98, 99, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,}, + {48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, -1, -1, -1,}, + {77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,100,101,102,103,104,105,106,107,108,109,110,111, -1, -1, -1,}, + { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + // GPIO1 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + // GPIO2 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + // GPIO3 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + // GPIO4 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + // GPIO5 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +static void imx6ull_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode) +{ + GPIO_Type *gpio_base = RT_NULL; + gpio_pin_config_t config; + rt_uint32_t config_value = 0; + rt_int8_t port, pin_num, reg_offset; + rt_uint32_t mux_base_addr, config_base_addr; + + port = pin >> 5; + pin_num = pin & 31; + + config.outputLogic = PIN_LOW; + config.interruptMode = kGPIO_NoIntmode; + + switch (mode) + { + case PIN_MODE_OUTPUT: + { + config.direction = kGPIO_DigitalOutput; + config_value = 0x0030U; + } + break; + + case PIN_MODE_INPUT: + { + config.direction = kGPIO_DigitalInput; + config_value = 0x0830U; + } + break; + + case PIN_MODE_INPUT_PULLDOWN: + { + config.direction = kGPIO_DigitalInput; + config_value = 0x3030U; + } + break; + + case PIN_MODE_INPUT_PULLUP: + { + config.direction = kGPIO_DigitalInput; + config_value = 0xB030U; + } + break; + + case PIN_MODE_OUTPUT_OD: + { + config.direction = kGPIO_DigitalOutput; + config_value = 0x0830U; + } + break; + } + + reg_offset = gpio_reg_offset[port][pin_num]; + gpio_base = (GPIO_Type *)imx6ull_get_periph_paddr((rt_uint32_t)mask_tab[port].gpio); + + if(gpio_base != GPIO5) + { + IOMUXC_Type *periph = (IOMUXC_Type*)iomuxc_base; + + mux_base_addr = (rt_uint32_t)&periph->SW_MUX_CTL_PAD[reg_offset]; + config_base_addr = (rt_uint32_t)&periph->SW_PAD_CTL_PAD[reg_offset]; + } + else + { + IOMUXC_SNVS_Type *periph = (IOMUXC_SNVS_Type*)iomuxc_snvs_base; + + mux_base_addr = (rt_uint32_t)&periph->SW_MUX_CTL_PAD[reg_offset]; + config_base_addr = (rt_uint32_t)&periph->SW_PAD_CTL_PAD[reg_offset]; + } + IOMUXC_SetPinMux(mux_base_addr, 0x5U, 0x00000000U, 0x0U, config_base_addr, 1); + IOMUXC_SetPinConfig(mux_base_addr, 0x5U, 0x00000000U, 0x0U, config_base_addr, config_value); + + GPIO_PinInit(mask_tab[port].gpio, pin_num, &config); +} + +static void imx6ull_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value) +{ + rt_int8_t port = 0, pin_num = 0; + + port = pin >> 5; + pin_num = pin & 31; + + GPIO_WritePinOutput(mask_tab[port].gpio, pin_num, value); +} + +static int imx6ull_pin_read(struct rt_device *device, rt_base_t pin) +{ + int value = 0; + rt_int8_t port = 0, pin_num = 0; + + value = PIN_LOW; + port = pin >> 5; + pin_num = pin & 31; + + value = GPIO_ReadPadStatus(mask_tab[port].gpio, pin_num); + + return value; +} + +static rt_err_t imx6ull_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), + void *args) +{ + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[pin].pin == pin && + pin_irq_hdr_tab[pin].hdr == hdr && + pin_irq_hdr_tab[pin].mode == mode && + pin_irq_hdr_tab[pin].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + + pin_irq_hdr_tab[pin].pin = pin; + pin_irq_hdr_tab[pin].hdr = hdr; + pin_irq_hdr_tab[pin].mode = mode; + pin_irq_hdr_tab[pin].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t imx6ull_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[pin].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[pin].pin = -1; + pin_irq_hdr_tab[pin].hdr = RT_NULL; + pin_irq_hdr_tab[pin].mode = 0; + pin_irq_hdr_tab[pin].args = RT_NULL; + + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t imx6ull_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + gpio_interrupt_mode_t int_mode; + rt_int8_t port = 0, pin_num = 0; + + port = pin >> 5; + pin_num = pin & 31; + + if (pin_irq_hdr_tab[pin].pin == -1) + { + rt_kprintf("rtt pin: %d callback function not initialized!\n", pin); + return RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + switch (pin_irq_hdr_tab[pin].mode) + { + case PIN_IRQ_MODE_RISING: + int_mode = kGPIO_IntRisingEdge; + break; + case PIN_IRQ_MODE_FALLING: + int_mode = kGPIO_IntFallingEdge; + break; + case PIN_IRQ_MODE_RISING_FALLING: + int_mode = kGPIO_IntRisingOrFallingEdge; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + int_mode = kGPIO_IntHighLevel; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + int_mode = kGPIO_IntLowLevel; + break; + default: + int_mode = kGPIO_IntRisingEdge; + break; + } + + GPIO_SetPinInterruptConfig(mask_tab[port].gpio, pin_num, int_mode); + GPIO_EnableInterrupts(mask_tab[port].gpio, 1U << pin_num); + } + else if (enabled == PIN_IRQ_DISABLE) + { + GPIO_DisableInterrupts(mask_tab[port].gpio, pin_num); + } + else + { + return RT_EINVAL; + } + + return RT_EOK; +} + +static void imx6ull_isr(rt_int16_t index_offset, rt_int8_t pin_start, GPIO_Type *base) +{ + rt_int32_t isr_status = 0, index = 0; + rt_int8_t i = 0, pin_end = 0; + + + pin_end = pin_start + 15; + isr_status = GPIO_GetPinsInterruptFlags(base) & base->IMR; + + for (i = pin_start; i <= pin_end ; i++) + { + if (isr_status & (1 << i)) + { + GPIO_ClearPinsInterruptFlags(base, (1 << i)); + index = index_offset + i; + if (pin_irq_hdr_tab[index].hdr != RT_NULL) + { + pin_irq_hdr_tab[index].hdr(pin_irq_hdr_tab[index].args); + } + } + } +} + +/* GPIO1 index offset is 0 */ +void GPIO1_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(0, 0, mask_tab[0].gpio); + + rt_interrupt_leave(); +} + +void GPIO1_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(0, 15, mask_tab[0].gpio); + + rt_interrupt_leave(); +} + +/* GPIO2 index offset is 32 */ +void GPIO2_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(32, 0, mask_tab[1].gpio); + + rt_interrupt_leave(); +} + +void GPIO2_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(32, 15, mask_tab[1].gpio); + + rt_interrupt_leave(); +} + +/* GPIO3 index offset is 64 */ +void GPIO3_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(64, 0, mask_tab[2].gpio); + + rt_interrupt_leave(); +} + +void GPIO3_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(64, 15, mask_tab[2].gpio); + + rt_interrupt_leave(); +} + +/* GPIO4 index offset is 96 */ +void GPIO4_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(96, 0, mask_tab[3].gpio); + + rt_interrupt_leave(); +} +void GPIO4_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(96, 15, mask_tab[3].gpio); + + rt_interrupt_leave(); +} + +/* GPIO5 index offset is 128 */ +void GPIO5_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(128, 0, mask_tab[4].gpio); + + rt_interrupt_leave(); +} + +/* GPIO5 index offset is 128 */ +void GPIO5_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(128, 0, mask_tab[4].gpio); + + rt_interrupt_leave(); +} + +static const struct rt_pin_ops gpio_ops = +{ + imx6ull_pin_mode, + imx6ull_pin_write, + imx6ull_pin_read, + imx6ull_pin_attach_irq, + imx6ull_pin_detach_irq, + imx6ull_pin_irq_enable, + RT_NULL, +}; + +static void imx6ull_pin_interrupt_install(void) +{ + rt_hw_interrupt_install(IMX_INT_GPIO1_INT15_0, GPIO1_Combined_0_15_IRQHandler, RT_NULL, "GPIO1_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO1_INT31_16, GPIO1_Combined_16_31_IRQHandler, RT_NULL, "GPIO1_16_31"); + rt_hw_interrupt_install(IMX_INT_GPIO2_INT15_0, GPIO2_Combined_0_15_IRQHandler, RT_NULL, "GPIO2_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO2_INT31_16, GPIO2_Combined_16_31_IRQHandler, RT_NULL, "GPIO2_16_31"); + rt_hw_interrupt_install(IMX_INT_GPIO3_INT15_0, GPIO3_Combined_0_15_IRQHandler, RT_NULL, "GPIO3_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO3_INT31_16, GPIO3_Combined_16_31_IRQHandler, RT_NULL, "GPIO3_16_31"); + rt_hw_interrupt_install(IMX_INT_GPIO4_INT15_0, GPIO4_Combined_0_15_IRQHandler, RT_NULL, "GPIO4_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO4_INT31_16, GPIO4_Combined_16_31_IRQHandler, RT_NULL, "GPIO4_16_31"); + rt_hw_interrupt_install(IMX_INT_GPIO5_INT15_0, GPIO5_Combined_0_15_IRQHandler, RT_NULL, "GPIO5_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO5_INT31_16, GPIO5_Combined_16_31_IRQHandler, RT_NULL, "GPIO5_16_31"); + + rt_hw_interrupt_umask(IMX_INT_GPIO1_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO1_INT31_16); + rt_hw_interrupt_umask(IMX_INT_GPIO2_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO2_INT31_16); + rt_hw_interrupt_umask(IMX_INT_GPIO3_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO3_INT31_16); + rt_hw_interrupt_umask(IMX_INT_GPIO4_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO4_INT31_16); + rt_hw_interrupt_umask(IMX_INT_GPIO5_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO5_INT31_16); +} + +int imx6ull_hw_pin_init(void) +{ + iomuxc_base = (size_t)imx6ull_get_periph_vaddr(iomuxc_base); + iomuxc_snvs_base = (size_t)imx6ull_get_periph_vaddr(iomuxc_snvs_base); + + for(int port = 0; port < sizeof(mask_tab) / sizeof(mask_tab[0]); port++) + { + mask_tab[port].gpio = (GPIO_Type *)imx6ull_get_periph_vaddr((rt_uint32_t)mask_tab[port].gpio); + CLOCK_EnableClock(mask_tab[port].gpio_clock); + } + + imx6ull_pin_interrupt_install(); + + rt_device_pin_register("pin", &gpio_ops, RT_NULL); + + rt_kprintf("pin driver init success\n"); + return RT_EOK; +} +INIT_BOARD_EXPORT(imx6ull_hw_pin_init); diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_pin.h b/bsp/imx6ull-artpi-smart/drivers/drv_pin.h new file mode 100644 index 0000000000000000000000000000000000000000..98c388fe40f3015072b08fa95ea5c370646bc9eb --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_pin.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-13 Lyons first version + * 2021-06-23 RiceChen add get pin API + */ + +#ifndef __DRV_PIN_H__ +#define __DRV_PIN_H__ + +#include "board.h" + +#define GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) + +#endif //#ifndef __DRV_PIN_H__ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_pwm.c b/bsp/imx6ull-artpi-smart/drivers/drv_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..8d094bd562e4a2e1b373529db0eee95931be9b2d --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_pwm.c @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-28 tyustli first version + * + */ + +#include + +#ifdef RT_USING_PWM + +#define LOG_TAG "drv.pwm" +#include + +#include +#include + +#include "fsl_pwm.h" +#include "drv_pwm.h" +#include +#include + +#define PWM_SRC_CLK_FREQ CLOCK_GetFreq(kCLOCK_IpgClk) +/* PWMPR register value of 0xffff has the same effect as 0xfffe */ +#define IMX_PWMPR_MAX 0xfffe +#define NSEC_PER_MSEC 1000000 +#define NSEC_PER_SEC 1000 + +#define MX3_PWMCR_SWR BIT(3) +#define MX3_PWM_SWR_LOOP 5 + +#define MX3_PWMSR_FIFOAV_EMPTY 0 +#define MX3_PWMSR_FIFOAV_1WORD 1 +#define MX3_PWMSR_FIFOAV_2WORDS 2 +#define MX3_PWMSR_FIFOAV_3WORDS 3 +#define MX3_PWMSR_FIFOAV_4WORDS 4 + +#define MX3_PWMCR_STOPEN BIT(25) +#define MX3_PWMCR_DOZEN BIT(24) +#define MX3_PWMCR_WAITEN BIT(23) +#define MX3_PWMCR_DBGEN BIT(22) +#define MX3_PWMCR_BCTR BIT(21) +#define MX3_PWMCR_HCTR BIT(20) +#define MX3_PWMCR_CLKSRC BIT(17) + +#define MX3_PWMCR_EN BIT(0) + +static rt_err_t imx6ull_drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); + +static struct rt_pwm_ops imxrt_drv_ops = +{ + .control = imx6ull_drv_pwm_control +}; + +static void imx6ull_pwm_reset(PWM_Type *base) +{ + int wait_count = 0; + uint32_t cr = 0; + + base->PWMCR = MX3_PWMCR_SWR; + do { + rt_thread_mdelay(1); + cr = base->PWMCR; + } while ((cr & MX3_PWMCR_SWR) && + (wait_count++ < MX3_PWM_SWR_LOOP)); + + if (cr & MX3_PWMCR_SWR) + { + LOG_E("software reset timeout\n"); + } +} +static void imx6ull_pwm_wait_fifo_slot(PWM_Type *base, struct rt_pwm_configuration *configuration) +{ + unsigned int period_ms = 0; + int fifoav = 0; + uint32_t sr = 0; + + sr = base->PWMSR; + fifoav = sr & 0x7; + if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) { + period_ms = configuration->period / NSEC_PER_MSEC; + rt_thread_mdelay(period_ms); + + sr = base->PWMSR; + if (fifoav == (sr & 0x7)) + { + LOG_E("there is no free FIFO slot\n"); + } + } +} + +static rt_err_t imx6ull_pwm_enable(struct rt_device_pwm *device, rt_bool_t enable) +{ + PWM_Type *base = (PWM_Type *)device->parent.user_data; + + if (!enable) + { + pwm_stop_timer(base); + } + else + { + pwm_start_timer(base); + } + + return RT_EOK; +} + +static rt_err_t imx6ull_pwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + uint32_t period = 0, prescaler = 0, val = 0; + uint64_t tmp = 0; + PWM_Type *base = (PWM_Type *)device->parent.user_data; + uint32_t pwm_src_clk; + + pwm_src_clk = PWM_SRC_CLK_FREQ / 1000000; + + val = base->PWMCR; + prescaler = ((val >> 4) & 0xfff)+1; + val = base->PWMPR; + period = val >= IMX_PWMPR_MAX ? IMX_PWMPR_MAX : val; + + tmp = NSEC_PER_SEC * (uint64_t)(period + 2) * prescaler; + + configuration->period = (tmp) / pwm_src_clk; + + val = base->PWMSAR; + + tmp = NSEC_PER_SEC * (uint64_t)(val) * prescaler; + + configuration->pulse = (tmp) / pwm_src_clk; + + return RT_EOK; +} + +static rt_err_t imx6ull_pwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + RT_ASSERT(configuration->period > 0); + RT_ASSERT(configuration->pulse <= configuration->period); + + PWM_Type *base = (PWM_Type *)device->parent.user_data; + uint32_t period_cycles = 0, duty_cycles = 0, prescale = 0; + uint32_t cr = 0; + uint32_t pwm_src_clk = 0; + + pwm_src_clk = PWM_SRC_CLK_FREQ / 1000000; + period_cycles = pwm_src_clk * configuration->period / NSEC_PER_SEC; + prescale = period_cycles / 0x10000 + 1; + period_cycles /= prescale; + + duty_cycles = configuration->pulse * pwm_src_clk / NSEC_PER_SEC ; + duty_cycles /= prescale; + + /* + * according to imx pwm RM, the real period value should be PERIOD + * value in PWMPR plus 2. + */ + if (period_cycles > 2) + { + period_cycles -= 2; + } + else + { + period_cycles = 0; + } + + if (((base->PWMCR) & 0x1) == 1) + { + imx6ull_pwm_wait_fifo_slot(base, configuration); + } + else + { + pwm_start_timer(base); + imx6ull_pwm_reset(base); + } + + base->PWMSAR = duty_cycles; + base->PWMPR = period_cycles; + + cr = ((prescale -1 ) << 4) | + MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | MX3_PWMCR_CLKSRC | MX3_PWMCR_DBGEN; + + cr |= MX3_PWMCR_EN; + + base->PWMCR = cr; + return RT_EOK; +} + +static rt_err_t imx6ull_drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return imx6ull_pwm_enable(device, RT_TRUE); + case PWM_CMD_DISABLE: + return imx6ull_pwm_enable(device, RT_FALSE); + case PWM_CMD_SET: + return imx6ull_pwm_set(device, configuration); + case PWM_CMD_GET: + return imx6ull_pwm_get(device, configuration); + default: + return RT_EINVAL; + } +} + +static rt_err_t imx6ull_drv_pwm_init(PWM_Type *base) +{ + pwm_config_t PwmConfig; + + pwm_get_default_config(&PwmConfig); + + if (pwm_init(base, &PwmConfig) == kStatus_Fail) + { + LOG_E("init pwm failed \n"); + return RT_ERROR; + } + + return RT_EOK; +} + +int imx6ull_pwm_gpio_init(void) +{ +#ifdef BSP_USING_PWM1 + struct imx6ull_iomuxc gpio; + + gpio.muxRegister = 0x020E007C; + gpio.muxMode = 0x0; + gpio.inputRegister = 0x00000000; + gpio.inputDaisy = 0x0; + gpio.configRegister = 0x020E0308; + gpio.inputOnfield = 0; + gpio.configValue = IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2U); + + imx6ull_gpio_init(&gpio); +#endif + return 0; +} + +int rt_hw_pwm_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_PWM1 + + static struct rt_device_pwm pwm1_device; + PWM_Type *pwm1_base; + + imx6ull_pwm_gpio_init(); + pwm1_base = (PWM_Type *)rt_ioremap((void*)PWM1, 0x1000); + if (imx6ull_drv_pwm_init(pwm1_base) != RT_EOK) + { + LOG_E("init pwm1 failed\n"); + } + + ret = rt_device_pwm_register(&pwm1_device, "pwm1", &imxrt_drv_ops, pwm1_base); + + if (ret != RT_EOK) + { + LOG_E("%s register failed", "pwm1"); + } + +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 + + static struct rt_device_pwm pwm2_device; + + imx6ull_pwm_gpio_init(); + if (imx6ull_drv_pwm_init(PWM2) != RT_EOK) + { + LOG_E("init pwm2 failed\n"); + } + + ret = rt_device_pwm_register(&pwm2_device, "pwm2", &imxrt_drv_ops, PWM2); + + if (ret != RT_EOK) + { + LOG_E("%s register failed", "pwm2"); + } +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 + + static struct rt_device_pwm pwm3_device; + + imx6ull_pwm_gpio_init(); + if (imx6ull_drv_pwm_init(PWM3) != RT_EOK) + { + LOG_E("init pwm3 failed\n"); + } + + ret = rt_device_pwm_register(&pwm3_device, "pwm3", &imxrt_drv_ops, PWM3); + + if (ret != RT_EOK) + { + LOG_E("%s register failed", "pwm3"); + } + +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 + + static struct rt_device_pwm pwm4_device; + + imx6ull_pwm_gpio_init(); + if (imx6ull_drv_pwm_init(PWM4) != RT_EOK) + { + LOG_E("init pwm4 failed\n"); + } + + ret = rt_device_pwm_register(&pwm4_device, "pwm4", &imxrt_drv_ops, PWM4); + + if (ret != RT_EOK) + { + LOG_E("%s register failed", "pwm4"); + } +#endif /* BSP_USING_PWM4 */ + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_pwm_init); +int set_pwm_default(void) +{ + int result = 0; + struct rt_device_pwm *device = RT_NULL; + + device = (struct rt_device_pwm *)rt_device_find("pwm1"); + if (!device) + { + result = -RT_EIO; + goto _exit; + } + + result = rt_pwm_set(device, 1, 1000000, 500000); + result = rt_pwm_enable(device, 1); +_exit: + return result; + +} +INIT_APP_EXPORT(set_pwm_default); +#endif /* BSP_USING_PWM */ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_pwm.h b/bsp/imx6ull-artpi-smart/drivers/drv_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..ec794039cc592f7203775ef54fd23b16f58a07dc --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_pwm.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-28 tyustli the first version. + * + */ + +#ifndef DRV_PWM_H__ +#define DRV_PWM_H__ + +#include + +#define BIT(nr) ((1) << (nr)) + +int rt_hw_pwm_init(void); + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_rtc.c b/bsp/imx6ull-artpi-smart/drivers/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..576b952d759c2069519d47bb98d5a9b67d3c70f3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_rtc.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-04-25 Lyons first version + */ + +#include + +#ifdef BSP_USING_ONCHIP_RTC + +#include "board.h" + +#define DBG_TAG "drv.rtc" +#define DBG_LVL DBG_WARNING +#include + +#define _DEVICE_NAME "rtc" + +_internal_rw struct rt_device _s_rtc_device; + +static time_t _get_rtc_timestamp(void) +{ + snvs_hp_rtc_datetime_t rtcDate; + SNVS_Type *snvs = (SNVS_Type*)g_snvs_vbase; + struct tm tm_new; + + SNVS_HP_RTC_GetDatetime(snvs, &rtcDate); + + tm_new.tm_sec = rtcDate.second; + tm_new.tm_min = rtcDate.minute; + tm_new.tm_hour = rtcDate.hour; + tm_new.tm_mday = rtcDate.day; + tm_new.tm_mon = rtcDate.month - 1; + tm_new.tm_year = rtcDate.year - 1900; + + return mktime(&tm_new); +} + +static rt_err_t _set_rtc_time_stamp(time_t time_stamp) +{ + snvs_hp_rtc_datetime_t rtcDate; + SNVS_Type *snvs = (SNVS_Type*)g_snvs_vbase; + struct tm *p_tm; + + p_tm = localtime(&time_stamp); + + rtcDate.second = p_tm->tm_sec; + rtcDate.minute = p_tm->tm_min; + rtcDate.hour = p_tm->tm_hour; + rtcDate.day = p_tm->tm_mday; + rtcDate.month = p_tm->tm_mon + 1; + rtcDate.year = p_tm->tm_year + 1900; + + if (kStatus_Success != SNVS_HP_RTC_SetDatetime(snvs, &rtcDate)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static void _rtc_init(void) +{ + snvs_hp_rtc_config_t snvsRtcConfig; + SNVS_Type *snvs = (SNVS_Type*)g_snvs_vbase; + + SNVS_HP_RTC_GetDefaultConfig(&snvsRtcConfig); + SNVS_HP_RTC_Init(snvs, &snvsRtcConfig); + + SNVS_HP_RTC_StartTimer(snvs); +} + +static rt_err_t _rtc_config(struct rt_device *dev) +{ + return RT_EOK; +} + +static rt_err_t _rtc_ops_control( rt_device_t dev, int cmd, void *args ) +{ + rt_err_t result; + + RT_ASSERT(RT_NULL != dev); + + result = RT_EOK; + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *(rt_uint32_t *)args = _get_rtc_timestamp(); + LOG_D("RTC: get rtc_time %x", *(rt_uint32_t *)args); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + if (_set_rtc_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; + } + LOG_D("RTC: set rtc_time %x", *(rt_uint32_t *)args); + break; + } + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +_internal_ro struct rt_device_ops _k_rtc_ops = +{ + RT_NULL, /* init */ + RT_NULL, /* open */ + RT_NULL, /* close */ + RT_NULL, /* read */ + RT_NULL, /* write */ + _rtc_ops_control, /* control */ +}; +#endif + +static rt_err_t _rt_rtc_register( rt_device_t device, const char *name, rt_uint32_t flag ) +{ + RT_ASSERT(RT_NULL != device); + + _rtc_init(); + if (RT_EOK != _rtc_config(device)) + { + return -RT_ERROR; + } + + device->type = RT_Device_Class_RTC; +#ifdef RT_USING_DEVICE_OPS + device->ops = &_k_rtc_ops; +#else + device->init = RT_NULL; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = _rtc_ops_control; +#endif + device->user_data = RT_NULL; + + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + + /* register a character device */ + return rt_device_register(device, name, flag); +} + +int rt_hw_rtc_init(void) +{ + rt_err_t result; + + result = _rt_rtc_register(&_s_rtc_device, _DEVICE_NAME, RT_DEVICE_FLAG_RDWR); + if (RT_EOK != result) + { + LOG_E("rtc register err code: %d", result); + return result; + } + + LOG_D("rtc init success."); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_ONCHIP_RTC */ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_rw007_port.c b/bsp/imx6ull-artpi-smart/drivers/drv_rw007_port.c new file mode 100644 index 0000000000000000000000000000000000000000..68bef7a01507e06fa4b9eee66d68ab5bdb3efc53 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_rw007_port.c @@ -0,0 +1,94 @@ +#include + +#ifdef PKG_USING_RW007 +#include +#include +#include +#include +#include + +#ifndef PKG_USING_RW007_LATEST_VERSION +#error "please select rw007 latest version." +#endif + +#define RW007_SPI_BUS_NAME "spi2" +#define RW007_CS_PIN GET_PIN(1, 29) /* IOMUXC_UART4_RX_DATA_ECSPI2_SS0 IOMUXC_UART4_RX_DATA_GPIO1_IO29 */ +#define RW007_INT_BUSY_PIN GET_PIN(5, 0) /* IOMUXC_SNVS_SNVS_TAMPER0_GPIO5_IO00 */ +#define RW007_RST_PIN GET_PIN(5, 1) /* IOMUXC_SNVS_SNVS_TAMPER1_GPIO5_IO01 */ + +extern void spi_wifi_isr(int vector); + +static int rw007_gpio_init(void) +{ + int ret = 0; + uint8_t errorCnt = 10; + /* Configure IO */ + rt_pin_mode(RW007_RST_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN); + + /* Reset rw007 and config mode */ + rt_pin_write(RW007_RST_PIN, PIN_LOW); + rt_thread_delay(rt_tick_from_millisecond(100)); + rt_pin_write(RW007_RST_PIN, PIN_HIGH); + + /* Wait rw007 ready(exit busy stat) */ + while(!rt_pin_read(RW007_INT_BUSY_PIN)) + { + rt_thread_delay(rt_tick_from_millisecond(100)); + if (errorCnt) + { + errorCnt--; + } + else + { + ret = -1; + break; + } + } + + rt_thread_delay(rt_tick_from_millisecond(200)); + rt_pin_mode(RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP); + return ret; +} + +int wifi_spi_device_init(void) +{ + char sn_version[32]; + + if (rw007_gpio_init() == -1) + { + rt_hw_wifi_init("rw007 gpio init fault!\n"); + return -1; + } + rt_hw_spi_device_attach(RW007_SPI_BUS_NAME, "rw007", RW007_CS_PIN); + rt_hw_wifi_init("rw007"); + + rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION); + rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP); + + rw007_sn_get(sn_version); + rt_kprintf("\nrw007 sn: [%s]\n", sn_version); + rw007_version_get(sn_version); + rt_kprintf("rw007 ver: [%s]\n\n", sn_version); + +#ifdef RW007_DAFAULT_SSID + rt_wlan_connect(RW007_DAFAULT_SSID, RW007_DAFAULT_PASSWARD); +#endif + + return 0; +} +INIT_APP_EXPORT(wifi_spi_device_init); + +static void int_wifi_irq(void * p) +{ + ((void)p); + spi_wifi_isr(0); +} + +void spi_wifi_hw_init(void) +{ + rt_pin_attach_irq(RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0); + rt_pin_irq_enable(RW007_INT_BUSY_PIN, RT_TRUE); +} + +#endif /* RW007_USING_STM32_DRIVERS */ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_sdio.c b/bsp/imx6ull-artpi-smart/drivers/drv_sdio.c new file mode 100644 index 0000000000000000000000000000000000000000..d5c483759d486573290b97af2f5c54368f5a9cf0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_sdio.c @@ -0,0 +1,706 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-10 Tanek first version + * 2021-07-07 linzhenxing add sd card drivers in mmu + * 2021-07-14 linzhenxing add emmc + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#define DBG_TAG "drv_sdio" +#ifdef RT_SDIO_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* RT_SDIO_DEBUG */ +#include + +#define CACHE_LINESIZE (32) + +#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ +#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ +#define IMXRT_MAX_FREQ (52UL * 1000UL * 1000UL) + +#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ +#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ +#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ +#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ +#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ + +/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ +#define USDHC_READ_WATERMARK_LEVEL (0x80U) +#define USDHC_WRITE_WATERMARK_LEVEL (0x80U) + +/* DMA mode */ +#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2 + +/* Endian mode. */ +#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle + +uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS]; +struct rt_mmcsd_host *host1; +struct rt_mmcsd_host *host2; +static rt_mutex_t mmcsd_mutex = RT_NULL; + +void host_change(void); + +struct imxrt_mmcsd +{ + struct rt_mmcsd_host *host; + struct rt_mmcsd_req *req; + struct rt_mmcsd_cmd *cmd; + + struct rt_timer timer; + + rt_uint32_t *buf; + + usdhc_host_t usdhc_host; + clock_div_t usdhc_div; + clock_ip_name_t ip_clock; + + uint32_t *usdhc_adma2_table; +}; + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the ENET1_RX_DATA0 Pad as FLEXCAN1_TX: + * @code + * IOMUXC_SetPinMux(IOMUXC_ENET1_RX_DATA0_FLEXCAN1_TX, 0); + * @endcode + * + * This is an example to set the GPIO1_IO02 Pad as I2C1_SCL: + * @code + * IOMUXC_SetPinMux(IOMUXC_GPIO1_IO02_I2C1_SCL, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void _IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)rt_ioremap((void*)muxRegister, 0x4)) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)rt_ioremap((void*)inputRegister, 0x4)) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_GPIO1_IO02_I2C1_SCL: + * @code + * IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO02_I2C1_SCL, IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void _IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)rt_ioremap((void*)configRegister, 0x4)) = configValue; + } +} + +static void _mmcsd_gpio_init(struct imxrt_mmcsd *mmcsd) +{ + + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ +#ifdef RT_USING_SDIO1 + /* uSDHC1 pins start*/ + _IOMUXC_SetPinMux(IOMUXC_UART1_RTS_B_USDHC1_CD_B, 0U); + _IOMUXC_SetPinConfig(IOMUXC_UART1_RTS_B_USDHC1_CD_B, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + _IOMUXC_SetPinMux(IOMUXC_SD1_CLK_USDHC1_CLK, 0U); + _IOMUXC_SetPinConfig(IOMUXC_SD1_CLK_USDHC1_CLK, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(1U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(1U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + _IOMUXC_SetPinMux(IOMUXC_SD1_CMD_USDHC1_CMD, 0U); + _IOMUXC_SetPinConfig(IOMUXC_SD1_CMD_USDHC1_CMD, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(1U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + _IOMUXC_SetPinMux(IOMUXC_SD1_DATA0_USDHC1_DATA0, 0U); + _IOMUXC_SetPinConfig(IOMUXC_SD1_DATA0_USDHC1_DATA0, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(1U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + _IOMUXC_SetPinMux(IOMUXC_SD1_DATA1_USDHC1_DATA1, 0U); + _IOMUXC_SetPinConfig(IOMUXC_SD1_DATA1_USDHC1_DATA1, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(1U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + _IOMUXC_SetPinMux(IOMUXC_SD1_DATA2_USDHC1_DATA2, 0U); + _IOMUXC_SetPinConfig(IOMUXC_SD1_DATA2_USDHC1_DATA2, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(1U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + _IOMUXC_SetPinMux(IOMUXC_SD1_DATA3_USDHC1_DATA3, 0U); + _IOMUXC_SetPinConfig(IOMUXC_SD1_DATA3_USDHC1_DATA3, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(1U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + /* uSDHC1 pins end*/ +#endif + +#ifdef RT_USING_SDIO2 + /* uSDHC2 pins start*/ + _IOMUXC_SetPinMux(IOMUXC_NAND_WE_B_USDHC2_CMD, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_WE_B_USDHC2_CMD, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(7U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_RE_B_USDHC2_CLK, 0U); + + _IOMUXC_SetPinConfig(IOMUXC_NAND_RE_B_USDHC2_CLK, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(1U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_ALE_USDHC2_RESET_B, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_ALE_USDHC2_RESET_B, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(1U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_DATA00_USDHC2_DATA0, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA00_USDHC2_DATA0, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(7U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_DATA01_USDHC2_DATA1, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA01_USDHC2_DATA1, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(7U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_DATA02_USDHC2_DATA2, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA02_USDHC2_DATA2, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(7U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_DATA03_USDHC2_DATA3, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA03_USDHC2_DATA3, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(7U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_DATA04_USDHC2_DATA4, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA04_USDHC2_DATA4, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(7U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_DATA05_USDHC2_DATA5, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA05_USDHC2_DATA5, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(7U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_DATA06_USDHC2_DATA6, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA06_USDHC2_DATA6, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(7U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(7U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + _IOMUXC_SetPinMux(IOMUXC_NAND_DATA07_USDHC2_DATA7, 0U); + _IOMUXC_SetPinConfig(IOMUXC_NAND_DATA07_USDHC2_DATA7, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(7U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1U) | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + /* uSDHC2 pins end*/ +#endif +} +static void SDMMCHOST_ErrorRecovery(USDHC_Type *base) +{ + uint32_t status = 0U; + /* get host present status */ + status = USDHC_GetPresentStatusFlags(base); + /* check command inhibit status flag */ + if ((status & kUSDHC_CommandInhibitFlag) != 0U) + { + /* reset command line */ + USDHC_Reset(base, kUSDHC_ResetCommand, 1000U); + } + /* check data inhibit status flag */ + if ((status & kUSDHC_DataInhibitFlag) != 0U) + { + /* reset data line */ + USDHC_Reset(base, kUSDHC_ResetData, 1000U); + } +} + +static void _mmcsd_host_init(struct imxrt_mmcsd *mmcsd) +{ + usdhc_host_t *usdhc_host = &mmcsd->usdhc_host; + + /* Initializes SDHC. */ + usdhc_host->config.dataTimeout = USDHC_DATA_TIMEOUT; + usdhc_host->config.endianMode = USDHC_ENDIAN_MODE; + usdhc_host->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL; + usdhc_host->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL; + usdhc_host->config.readBurstLen = USDHC_READ_BURST_LEN; + usdhc_host->config.writeBurstLen = USDHC_WRITE_BURST_LEN; + + USDHC_Init(usdhc_host->base, &(usdhc_host->config)); +} + +static void _mmcsd_clk_init(struct imxrt_mmcsd *mmcsd) +{ + CLOCK_EnableClock(mmcsd->ip_clock); + CLOCK_SetDiv(mmcsd->usdhc_div, 5U); +} + +static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct imxrt_mmcsd *mmcsd; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + status_t error; + usdhc_adma_config_t dmaConfig; + usdhc_transfer_t fsl_content = {0}; + usdhc_command_t fsl_command = {0}; + usdhc_data_t fsl_data = {0}; + rt_uint32_t *buf = NULL; + + rt_mutex_take(mmcsd_mutex, RT_WAITING_FOREVER); + + RT_ASSERT(host != RT_NULL); + RT_ASSERT(req != RT_NULL); + + mmcsd = (struct imxrt_mmcsd *)host->private_data; + RT_ASSERT(mmcsd != RT_NULL); + + cmd = req->cmd; + RT_ASSERT(cmd != RT_NULL); + + LOG_D("\tcmd->cmd_code: %02d, cmd->arg: %08x, cmd->flags: %08x --> ", cmd->cmd_code, cmd->arg, cmd->flags); + + data = cmd->data; + + memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t)); + /* config adma */ + dmaConfig.dmaMode = USDHC_DMA_MODE; + dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR; + dmaConfig.admaTable = mmcsd->usdhc_adma2_table; + dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS; + + fsl_command.index = cmd->cmd_code; + fsl_command.argument = cmd->arg; + + if (cmd->cmd_code == STOP_TRANSMISSION) + fsl_command.type = kCARD_CommandTypeAbort; + else + fsl_command.type = kCARD_CommandTypeNormal; + + switch (cmd->flags & RESP_MASK) + { + case RESP_NONE: + fsl_command.responseType = kCARD_ResponseTypeNone; + break; + case RESP_R1: + fsl_command.responseType = kCARD_ResponseTypeR1; + break; + case RESP_R1B: + fsl_command.responseType = kCARD_ResponseTypeR1b; + break; + case RESP_R2: + fsl_command.responseType = kCARD_ResponseTypeR2; + break; + case RESP_R3: + fsl_command.responseType = kCARD_ResponseTypeR3; + break; + case RESP_R4: + fsl_command.responseType = kCARD_ResponseTypeR4; + break; + case RESP_R6: + fsl_command.responseType = kCARD_ResponseTypeR6; + break; + case RESP_R7: + fsl_command.responseType = kCARD_ResponseTypeR7; + break; + case RESP_R5: + fsl_command.responseType = kCARD_ResponseTypeR5; + break; + default: + RT_ASSERT(NULL); + } + + fsl_command.flags = 0; + fsl_content.command = &fsl_command; + + if (data) + { + if (req->stop != NULL) + fsl_data.enableAutoCommand12 = true; + else + fsl_data.enableAutoCommand12 = false; + + fsl_data.enableAutoCommand23 = false; + + fsl_data.enableIgnoreError = false; + fsl_data.blockSize = data->blksize; + fsl_data.blockCount = data->blks; + + LOG_D(" blksize:%d, blks:%d ", fsl_data.blockSize, fsl_data.blockCount); + + if (((rt_uint32_t)data->buf & (CACHE_LINESIZE - 1)) || // align cache(32byte) + ((rt_uint32_t)data->buf > 0x00000000 && (rt_uint32_t)data->buf < 0x00080000) /*|| // ITCM + ((rt_uint32_t)data->buf >= 0x20000000 && (rt_uint32_t)data->buf < 0x20080000)*/) // DTCM + { + + buf = rt_malloc_align(fsl_data.blockSize * fsl_data.blockCount, CACHE_LINESIZE); + RT_ASSERT(buf != RT_NULL); + + LOG_D(" malloc buf: %p, data->buf:%p, %d ", buf, data->buf, fsl_data.blockSize * fsl_data.blockCount); + } + + + if ((cmd->cmd_code == WRITE_BLOCK) || (cmd->cmd_code == WRITE_MULTIPLE_BLOCK)) + { + if (buf) + { + LOG_D(" write(data->buf to buf) "); + rt_memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount); + fsl_data.txData = (uint32_t const *)buf; + } + else + { + fsl_data.txData = (uint32_t const *)data->buf; + } + + fsl_data.rxData = NULL; + } + else + { + if (buf) + { + fsl_data.rxData = (uint32_t *)buf; + } + else + { + fsl_data.rxData = (uint32_t *)data->buf; + } + + fsl_data.txData = NULL; + } + + fsl_content.data = &fsl_data; + } + else + { + fsl_content.data = NULL; + } + + error = USDHC_TransferBlocking(mmcsd->usdhc_host.base, &dmaConfig, &fsl_content); + if (error == kStatus_Fail) + { + SDMMCHOST_ErrorRecovery(mmcsd->usdhc_host.base); + LOG_D(" ***USDHC_TransferBlocking error: %d*** --> \n", error); + cmd->err = -RT_ERROR; + } + + if (buf) + { + if (fsl_data.rxData) + { + LOG_D("read copy buf to data->buf "); + rt_memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount); + } + + rt_free_align(buf); + } + + if ((cmd->flags & RESP_MASK) == RESP_R2) + { + cmd->resp[3] = fsl_command.response[0]; + cmd->resp[2] = fsl_command.response[1]; + cmd->resp[1] = fsl_command.response[2]; + cmd->resp[0] = fsl_command.response[3]; + LOG_D(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + cmd->resp[0] = fsl_command.response[0]; + LOG_D(" resp 0x%08X\n", cmd->resp[0]); + } + + mmcsd_req_complete(host); + + rt_mutex_release(mmcsd_mutex); + return; +} + +static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + + struct imxrt_mmcsd *mmcsd; + unsigned int usdhc_clk; + unsigned int bus_width; + uint32_t src_clk; + + RT_ASSERT(host != RT_NULL); + RT_ASSERT(host->private_data != RT_NULL); + RT_ASSERT(io_cfg != RT_NULL); + + + mmcsd = (struct imxrt_mmcsd *)host->private_data; + usdhc_clk = io_cfg->clock; + bus_width = io_cfg->bus_width; + + if (usdhc_clk > IMXRT_MAX_FREQ) + usdhc_clk = IMXRT_MAX_FREQ; + src_clk = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(mmcsd->usdhc_div) + 1U)); + + LOG_D("\tsrc_clk: %d, usdhc_clk: %d, bus_width: %d\n", src_clk, usdhc_clk, bus_width); + if (usdhc_clk) + { + USDHC_SetSdClock(mmcsd->usdhc_host.base, src_clk, usdhc_clk); + /* Change bus width */ + if (bus_width == MMCSD_BUS_WIDTH_8) + USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth8Bit); + else if (bus_width == MMCSD_BUS_WIDTH_4) + USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth4Bit); + else if (bus_width == MMCSD_BUS_WIDTH_1) + USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth1Bit); + else + RT_ASSERT(RT_NULL); + + } +} + +static const struct rt_mmcsd_host_ops ops = +{ + _mmc_request, + _mmc_set_iocfg, + RT_NULL,//_mmc_get_card_status, + RT_NULL,//_mmc_enable_sdio_irq, +}; + +rt_int32_t imxrt_mci_init(void) +{ +#ifdef RT_USING_SDIO1 + struct imxrt_mmcsd *mmcsd1; + + host1 = mmcsd_alloc_host(); + if (!host1) + { + return -RT_ERROR; + } + + mmcsd1 = rt_malloc(sizeof(struct imxrt_mmcsd)); + if (!mmcsd1) + { + LOG_E("alloc mci failed\n"); + goto err; + } + + rt_memset(mmcsd1, 0, sizeof(struct imxrt_mmcsd)); + mmcsd1->usdhc_host.base = (USDHC_Type *)rt_ioremap((void*)USDHC1_BASE, 0x1000); + mmcsd1->usdhc_div = kCLOCK_Usdhc1Div; + mmcsd1->usdhc_adma2_table = g_usdhcAdma2Table; + + strncpy(host1->name, "sd", sizeof(host1->name)-1); + host1->ops = &ops; + host1->freq_min = 375000; + host1->freq_max = 25000000; + host1->valid_ocr = VDD_32_33 | VDD_33_34; + host1->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host1->max_seg_size = 65535; + host1->max_dma_segs = 2; + host1->max_blk_size = 512; + host1->max_blk_count = 4096; + + mmcsd1->host = host1; + _mmcsd_clk_init(mmcsd1); + _mmcsd_gpio_init(mmcsd1); + _mmcsd_host_init(mmcsd1); + + host1->private_data = mmcsd1; + + mmcsd_change(host1); +#endif + +#ifdef RT_USING_SDIO2 + struct imxrt_mmcsd *mmcsd2; + host2 = mmcsd_alloc_host(); + if (!host2) + { + return -RT_ERROR; + } + + mmcsd2 = rt_malloc(sizeof(struct imxrt_mmcsd)); + if (!mmcsd2) + { + LOG_E("alloc mci failed\n"); + goto err; + } + + rt_memset(mmcsd2, 0, sizeof(struct imxrt_mmcsd)); + mmcsd2->usdhc_host.base = (USDHC_Type *)rt_ioremap((void*)USDHC2_BASE, 0x1000); + mmcsd2->usdhc_div = kCLOCK_Usdhc1Div; + mmcsd2->usdhc_adma2_table = g_usdhcAdma2Table; + + strncpy(host2->name, "emmc", sizeof(host2->name)-1); + host2->ops = &ops; + host2->freq_min = 375000; + host2->freq_max = 52000000; + host2->valid_ocr = VDD_35_36; + host2->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host2->max_seg_size = 65535; + host2->max_dma_segs = 2; + host2->max_blk_size = 512; + host2->max_blk_count = 4096; + + mmcsd2->host = host2; + _mmcsd_clk_init(mmcsd2); + _mmcsd_gpio_init(mmcsd2); + _mmcsd_host_init(mmcsd2); + + host2->private_data = mmcsd2; + mmcsd_change(host2); +#endif + mmcsd_mutex = rt_mutex_create("mmutex", RT_IPC_FLAG_FIFO); + if (mmcsd_mutex == RT_NULL) + { + LOG_E("create mmcsd mutex failed.\n"); + return -1; + } + + return 0; + +err: +#ifdef RT_USING_SDIO1 + mmcsd_free_host(host1); +#endif +#ifdef RT_USING_SDIO2 + mmcsd_free_host(host2); +#endif + return -RT_ENOMEM; +} + +INIT_DEVICE_EXPORT(imxrt_mci_init); +void host_change(void) +{ + mmcsd_change(host1); +} + + diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_sdio.h b/bsp/imx6ull-artpi-smart/drivers/drv_sdio.h new file mode 100644 index 0000000000000000000000000000000000000000..df6136c652e10d03e48bb25817f60e56d6aba426 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_sdio.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-14 linzhenxing first version + */ +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +void host_change(void); + +#endif \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_spi.c b/bsp/imx6ull-artpi-smart/drivers/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..a00d86d41a62be98ad51c6bf1502f612b31f77be --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_spi.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 Lyons first version + * 2021-06-23 RiceChen refactor + */ + +#include +#include + +#ifdef BSP_USING_SPI + +#define LOG_TAG "drv.spi" +#include + +#include "fsl_iomuxc.h" +#include "drv_spi.h" + +static struct imx6ull_spi_config spi_config[] = +{ +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif +#ifdef BSP_USING_SPI2 + SPI2_BUS_CONFIG, +#endif +#ifdef BSP_USING_SPI3 + SPI3_BUS_CONFIG, +#endif +#ifdef BSP_USING_SPI4 + SPI4_BUS_CONFIG, +#endif +}; + +static struct imx6ull_spi_bus spi_obj[sizeof(spi_config) / sizeof(spi_config[0])]; + +static rt_err_t imx6ull_ecspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + struct imx6ull_spi_bus *spi_dev = RT_NULL; + ecspi_master_config_t config; + rt_uint32_t scr_clock = 0; + + spi_dev = (struct imx6ull_spi_bus *)(device->bus->parent.user_data); + + ECSPI_MasterGetDefaultConfig(&config); + + config.samplePeriod = 10; + config.txFifoThreshold = 0; + config.channelConfig.dataLineInactiveState = kECSPI_DataLineInactiveStateHigh; + + if (cfg->data_width == 8) + { + config.burstLength = 8; + } + else + { + return -RT_EINVAL; + } + + if (cfg->mode & RT_SPI_SLAVE) + { + config.channelConfig.channelMode = kECSPI_Slave; + } + else + { + config.channelConfig.channelMode = kECSPI_Master; + } + + if(cfg->mode & RT_SPI_CPHA) + { + config.channelConfig.phase = kECSPI_ClockPhaseSecondEdge; + } + else + { + config.channelConfig.phase = kECSPI_ClockPhaseFirstEdge; + } + + if(cfg->mode & RT_SPI_CPOL) + { + config.channelConfig.polarity = kECSPI_PolarityActiveLow; + } + else + { + config.channelConfig.polarity = kECSPI_PolarityActiveHigh; + } + + config.baudRate_Bps = cfg->max_hz; + + scr_clock = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8U); + ECSPI_MasterInit(spi_dev->config->ECSPI, &config, scr_clock); + return RT_EOK; +} + +static rt_uint32_t imx6ull_ecspi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct imx6ull_spi_bus *spi_dev = RT_NULL; + struct imx6ull_spi_cs *cs = RT_NULL; + + const rt_uint8_t *send_ptr = RT_NULL; + rt_uint8_t *recv_ptr = RT_NULL; + rt_uint16_t size = 0; + rt_uint8_t temp_data; + + spi_dev = (struct imx6ull_spi_bus *)(device->bus->parent.user_data); + cs = (struct imx6ull_spi_cs *)device->parent.user_data; + + recv_ptr = (rt_uint8_t *)message->recv_buf; + send_ptr = (rt_uint8_t *)message->send_buf; + size = message->length; + + if(message->cs_take && cs) + { + rt_pin_write(cs->pin, PIN_LOW); + } + + ECSPI_SetChannelSelect(spi_dev->config->ECSPI, kECSPI_Channel0); + while (size--) + { + temp_data = (send_ptr != RT_NULL) ? (*send_ptr++) : 0xff; + + while (!(spi_dev->config->ECSPI->STATREG & ECSPI_STATREG_TE_MASK)); + ECSPI_WriteData(spi_dev->config->ECSPI, temp_data); + + while (!(spi_dev->config->ECSPI->STATREG & ECSPI_STATREG_RR_MASK)); + temp_data = ECSPI_ReadData(spi_dev->config->ECSPI); + + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = temp_data; + } + } + + if(message->cs_release && cs) + { + rt_pin_write(cs->pin, PIN_HIGH); + } + + return message->length; +} + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin) +{ + rt_err_t ret = RT_EOK; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct imx6ull_spi_cs *cs_pin = (struct imx6ull_spi_cs *)rt_malloc(sizeof(struct imx6ull_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; +} + +static rt_err_t imx6ull_spi_gpio_init(struct imx6ull_spi_bus *bus) +{ + struct imx6ull_spi_bus *spi_bus = RT_NULL; + + spi_bus = (struct imx6ull_spi_bus *)bus; + + imx6ull_gpio_init(&spi_bus->config->clk_gpio); + imx6ull_gpio_init(&spi_bus->config->miso_gpio); + imx6ull_gpio_init(&spi_bus->config->mosi_gpio); + + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +static const struct rt_spi_ops imxrt_spi_ops = +{ + .configure = imx6ull_ecspi_configure, + .xfer = imx6ull_ecspi_xfer, +}; +#endif + +int rt_hw_spi_init(void) +{ + rt_uint16_t obj_num = 0; + + obj_num = sizeof(spi_config) / sizeof(spi_config[0]); + + for(int i = 0; i < obj_num; i++) + { + spi_obj[i].config = &spi_config[i]; + spi_obj[i].config->ECSPI = (ECSPI_Type *)imx6ull_get_periph_vaddr((rt_uint32_t)(spi_obj[i].config->ECSPI)); + imx6ull_spi_gpio_init(&spi_obj[i]); + + CLOCK_EnableClock(spi_obj[i].config->clk_ip_name); + + spi_obj[i].parent.parent.user_data = &spi_obj[i]; + rt_spi_bus_register(&spi_obj[i].parent, spi_obj[i].config->name, &imxrt_spi_ops); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spi_init); + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_spi.h b/bsp/imx6ull-artpi-smart/drivers/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..590e589974e1d7b05873550a820fba79eea2a6b0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_spi.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 Lyons first version + * 2021-06-23 RiceChen refactor + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include "drv_common.h" + +#include "fsl_iomuxc.h" +#include "fsl_clock.h" +#include "fsl_ecspi.h" + +struct imx6ull_spi_cs +{ + rt_uint32_t pin; +}; + +struct imx6ull_spi_config +{ + ECSPI_Type *ECSPI; + char *name; + + rt_uint32_t clk_ip_name; + + struct imx6ull_iomuxc clk_gpio; + struct imx6ull_iomuxc miso_gpio; + struct imx6ull_iomuxc mosi_gpio; +}; + +struct imx6ull_spi_bus +{ + struct rt_spi_bus parent; + struct imx6ull_spi_config *config; +}; + +#ifdef BSP_USING_SPI1 +#define SPI1_BUS_CONFIG \ + { \ + .ECSPI = ECSPI1, \ + .name = "spi1", \ + .clk_ip_name = kCLOCK_Ecspi1, \ + .clk_gpio = {IOMUXC_CSI_DATA04_ECSPI1_SCLK, 0, 0X10B1}, \ + .miso_gpio = {IOMUXC_CSI_DATA07_ECSPI1_MISO, 0, 0X10B1}, \ + .mosi_gpio = {IOMUXC_CSI_DATA06_ECSPI1_MOSI, 0, 0X10B1}, \ + } +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_USING_SPI2 +#define SPI2_BUS_CONFIG \ + { \ + .ECSPI = ECSPI2, \ + .name = "spi2", \ + .clk_ip_name = kCLOCK_Ecspi2, \ + .clk_gpio = {IOMUXC_UART4_TX_DATA_ECSPI2_SCLK, 0, 0X10B1}, \ + .miso_gpio = {IOMUXC_UART5_RX_DATA_ECSPI2_MISO, 0, 0X10B1}, \ + .mosi_gpio = {IOMUXC_UART5_TX_DATA_ECSPI2_MOSI, 0, 0X10B1}, \ + } + +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_USING_SPI3 +#define SPI3_BUS_CONFIG \ + { \ + .ECSPI = ECSPI3, \ + .name = "spi3", \ + .clk_ip_name = kCLOCK_Ecspi3, \ + .clk_gpio = {IOMUXC_UART2_RX_DATA_ECSPI3_SCLK, 0, 0X10B1}, \ + .miso_gpio = {IOMUXC_UART2_RTS_B_ECSPI3_MISO, 0, 0X10B1}, \ + .mosi_gpio = {IOMUXC_UART2_CTS_B_ECSPI3_MOSI, 0, 0X10B1}, \ + } + +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_USING_SPI4 +#define SPI4_BUS_CONFIG \ + { \ + .ECSPI = ECSPI4, \ + .name = "spi4", \ + .clk_ip_name = kCLOCK_Ecspi4, \ + .clk_gpio = {IOMUXC_ENET2_TX_DATA1_ECSPI4_SCLK, 0, 0X10B1}, \ + .miso_gpio = {IOMUXC_ENET2_TX_CLK_ECSPI4_MISO, 0, 0X10B1}, \ + .mosi_gpio = {IOMUXC_ENET2_TX_EN_ECSPI4_MOSI, 0, 0X10B1}, \ + } + +#endif /* BSP_USING_SPI4 */ + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin); + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_timer.c b/bsp/imx6ull-artpi-smart/drivers/drv_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..9001ba65de18a98dd782e304d268fc34b2d1db93 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_timer.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#include +#include +#include + +#include +#include "mmu.h" + +#define TICK_PERIOD (g_sys_freq / RT_TICK_PER_SECOND) +static int g_sys_freq; + +#define IRQ_SECURE_PHY_TIMER 29 /* Secure physical timer event */ +#define IRQ_NOSECURE_PHY_TIMER 30 /* No-Secure physical timer event */ + +#define IRQ_SYS_TICK IRQ_SECURE_PHY_TIMER + + +/* System Counter */ +struct sctr_regs { + rt_uint32_t cntcr; + rt_uint32_t cntsr; + rt_uint32_t cntcv1; + rt_uint32_t cntcv2; + rt_uint32_t resv1[4]; + rt_uint32_t cntfid0; + rt_uint32_t cntfid1; + rt_uint32_t cntfid2; + rt_uint32_t resv2[1001]; + rt_uint32_t counterid[1]; +}; + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + + +#define isb() __asm__ __volatile__ ("" : : : "memory") +#define dsb() __asm__ __volatile__ ("" : : : "memory") +#define dmb() __asm__ __volatile__ ("" : : : "memory") + + +static inline void enable_cntp(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c2, 1" :: "r"(cntv_ctl)); // write CNTP_CTL + isb(); +} + +static inline void disable_cntp(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 0; + asm volatile ("mcr p15, 0, %0, c14, c2, 1" :: "r"(cntv_ctl)); // write CNTP_CTL + isb(); +} + +static inline rt_uint32_t read_cntfrq(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val)); + return val; +} + +static inline void write_cntp_tval(rt_uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c14, c2, 0" :: "r"(val)); + isb(); + return; +} + +static inline void write_cntp_cval(rt_uint64_t val) +{ + asm volatile ("mcrr p15, 2, %Q0, %R0, c14" :: "r" (val)); + isb(); + return; +} + +static inline rt_uint64_t read_cntp_cval(void) +{ + rt_uint64_t val; + asm volatile ("mrrc p15, 2, %Q0, %R0, c14" : "=r" (val)); + return (val); +} + +volatile unsigned int *CCM_CLPCR; + +static void imx6ull_enable_clk_in_waitmode(void) +{ + CCM_CLPCR = rt_ioremap((void*)0x20C4054, 4); + *CCM_CLPCR &= ~((1 << 5) | 0x3); +} + +static void system_counter_clk_source_init(void) +{ + /* to do */ +} + +static void system_counter_init(void) +{ + /* enable system_counter */ +#define SCTR_BASE_ADDR 0x021DC000 +#define CONFIG_SC_TIMER_CLK 8000000 + + /* imx6ull, enable system counter */ + struct sctr_regs *sctr = (struct sctr_regs *)rt_ioremap((void*)SCTR_BASE_ADDR, sizeof(struct sctr_regs)); + unsigned long val, freq; + + freq = CONFIG_SC_TIMER_CLK; + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + sctr->cntfid0 = freq; + + /* Enable system counter */ + val = sctr->cntcr; + val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); + val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; + sctr->cntcr = val; + + imx6ull_enable_clk_in_waitmode(); +} + +static void arch_timer_init(void) +{ + g_sys_freq = read_cntfrq(); + + /* set timeout val */ + disable_cntp(); + write_cntp_tval(TICK_PERIOD); + + /* start timer */ + enable_cntp(); + + /* enable irq */ +} + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + + /* setup for next irq */ + /* clear interrupt */ + disable_cntp(); + write_cntp_cval(read_cntp_cval() + TICK_PERIOD); + enable_cntp(); +} + +int rt_hw_timer_init(void) +{ + /* Setup Timer for generating irq */ + /* enable timer */ + system_counter_clk_source_init(); + system_counter_init(); + arch_timer_init(); + + /* insall irq, enable irq */ + rt_hw_interrupt_install(IRQ_SYS_TICK, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_SYS_TICK); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_timer.h b/bsp/imx6ull-artpi-smart/drivers/drv_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..c50b073d36c9a0ed9ca72e164b459a5841d1b4b9 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_timer.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#ifndef DRV_TIMER_H__ +#define DRV_TIMER_H__ + +void timer_init(int timer, unsigned int preload); +void timer_clear_pending(int timer); + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_touch.c b/bsp/imx6ull-artpi-smart/drivers/drv_touch.c new file mode 100644 index 0000000000000000000000000000000000000000..f8f2624f2c2cb0309ee29e6069911fece34fd107 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_touch.c @@ -0,0 +1,500 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 RiceChen the first version + */ + +#include +#include +#include + +#define DBG_TAG "gt911" +#define DBG_LVL DBG_INFO +#include + +#include "drv_touch.h" + +#define GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) +#define IRQ_PIN GET_PIN(1, 5) +#define RST_PIN GET_PIN(5, 2) +static struct rt_i2c_client gt911_client; + +/* hardware section */ +static rt_uint8_t GT911_CFG_TBL[] = +{ + 0x6b, 0x00, 0x04, 0x58, 0x02, 0x05, 0x0d, 0x00, 0x01, 0x0f, + 0x28, 0x0f, 0x50, 0x32, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0x2a, 0x0c, + 0x45, 0x47, 0x0c, 0x08, 0x00, 0x00, 0x00, 0x40, 0x03, 0x2c, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x64, 0x32, 0x00, 0x00, + 0x00, 0x28, 0x64, 0x94, 0xd5, 0x02, 0x07, 0x00, 0x00, 0x04, + 0x95, 0x2c, 0x00, 0x8b, 0x34, 0x00, 0x82, 0x3f, 0x00, 0x7d, + 0x4c, 0x00, 0x7a, 0x5b, 0x00, 0x7a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e, 0x0c, 0x0a, + 0x08, 0x06, 0x04, 0x02, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x16, 0x18, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, + 0x22, 0x24, 0x13, 0x12, 0x10, 0x0f, 0x0a, 0x08, 0x06, 0x04, + 0x02, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x79, 0x01, +}; + +static rt_err_t gt911_write_reg(struct rt_i2c_client *dev, rt_uint8_t *data, rt_uint8_t len) +{ + struct rt_i2c_msg msgs; + + msgs.addr = dev->client_addr; + msgs.flags = RT_I2C_WR; + msgs.buf = data; + msgs.len = len; + + if (rt_i2c_transfer(dev->bus, &msgs, 1) == 1) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +static rt_err_t gt911_read_regs(struct rt_i2c_client *dev, rt_uint8_t *reg, rt_uint8_t *data, rt_uint8_t len) +{ + struct rt_i2c_msg msgs[2]; + + msgs[0].addr = dev->client_addr; + msgs[0].flags = RT_I2C_WR; + msgs[0].buf = reg; + msgs[0].len = GT911_REGITER_LEN; + + msgs[1].addr = dev->client_addr; + msgs[1].flags = RT_I2C_RD; + msgs[1].buf = data; + msgs[1].len = len; + + if (rt_i2c_transfer(dev->bus, msgs, 2) == 2) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +static rt_err_t gt911_get_product_id(struct rt_i2c_client *dev, rt_uint8_t *data, rt_uint8_t len) +{ + rt_uint8_t reg[2]; + + reg[0] = (rt_uint8_t)(GT911_PRODUCT_ID >> 8); + reg[1] = (rt_uint8_t)(GT911_PRODUCT_ID & 0xff); + + if (gt911_read_regs(dev, reg, data, len) != RT_EOK) + { + LOG_E("read id failed"); + return -RT_ERROR; + } + return RT_EOK; +} + +static rt_err_t gt911_get_info(struct rt_i2c_client *dev, struct rt_touch_info *info) +{ + rt_uint8_t reg[2]; + rt_uint8_t out_info[7]; + rt_uint8_t out_len = 7; + + reg[0] = (rt_uint8_t)(GT911_CONFIG_REG >> 8); + reg[1] = (rt_uint8_t)(GT911_CONFIG_REG & 0xFF); + + if(gt911_read_regs(dev, reg, out_info, out_len) != RT_EOK) + { + LOG_E("read info failed"); + return -RT_ERROR; + } + + info->range_x = (out_info[2] << 8) | out_info[1]; + info->range_y = (out_info[4] << 8) | out_info[3]; + info->point_num = out_info[5] & 0x0f; + + return RT_EOK; +} + +static rt_err_t gt911_soft_reset(struct rt_i2c_client *dev) +{ + rt_uint8_t buf[3]; + + buf[0] = (rt_uint8_t)(GT911_COMMAND_REG >> 8); + buf[1] = (rt_uint8_t)(GT911_COMMAND_REG & 0xFF); + buf[2] = 0x02; + + if(gt911_write_reg(dev, buf, 3) != RT_EOK) + { + LOG_E("soft reset failed"); + return -RT_ERROR; + } + return RT_EOK; +} + +static int16_t pre_x[GT911_MAX_TOUCH] = {-1, -1, -1, -1, -1}; +static int16_t pre_y[GT911_MAX_TOUCH] = {-1, -1, -1, -1, -1}; +static int16_t pre_w[GT911_MAX_TOUCH] = {-1, -1, -1, -1, -1}; +static rt_uint8_t s_tp_dowm[GT911_MAX_TOUCH]; +static struct rt_touch_data *read_data; + +static void gt911_touch_up(void *buf, int8_t id) +{ + read_data = (struct rt_touch_data *)buf; + + if(s_tp_dowm[id] == 1) + { + s_tp_dowm[id] = 0; + read_data[id].event = RT_TOUCH_EVENT_UP; + } + else + { + read_data[id].event = RT_TOUCH_EVENT_NONE; + } + + read_data[id].timestamp = rt_touch_get_ts(); + read_data[id].width = pre_w[id]; + read_data[id].x_coordinate = pre_x[id]; + read_data[id].y_coordinate = pre_y[id]; + read_data[id].track_id = id; + + pre_x[id] = -1; /* last point is none */ + pre_y[id] = -1; + pre_w[id] = -1; +} + +static void gt911_touch_down(void *buf, int8_t id, int16_t x, int16_t y, int16_t w) +{ + read_data = (struct rt_touch_data *)buf; + + if (s_tp_dowm[id] == 1) + { + read_data[id].event = RT_TOUCH_EVENT_MOVE; + } + else + { + read_data[id].event = RT_TOUCH_EVENT_DOWN; + s_tp_dowm[id] = 1; + } + + read_data[id].timestamp = rt_touch_get_ts(); + read_data[id].width = w; + read_data[id].x_coordinate = x; + read_data[id].y_coordinate = y; + read_data[id].track_id = id; + + pre_x[id] = x; /* save last point */ + pre_y[id] = y; + pre_w[id] = w; +} + +static rt_size_t gt911_read_point(struct rt_touch_device *touch, void *buf, rt_size_t read_num) +{ + rt_uint8_t point_status = 0; + rt_uint8_t touch_num = 0; + rt_uint8_t write_buf[3]; + rt_uint8_t cmd[2]; + rt_uint8_t read_buf[8 * GT911_MAX_TOUCH] = {0}; + rt_uint8_t read_index; + int8_t read_id = 0; + int16_t input_x = 0; + int16_t input_y = 0; + int16_t input_w = 0; + + static rt_uint8_t pre_touch = 0; + static int8_t pre_id[GT911_MAX_TOUCH] = {0}; + + /* point status register */ + cmd[0] = (rt_uint8_t)((GT911_READ_STATUS >> 8) & 0xFF); + cmd[1] = (rt_uint8_t)(GT911_READ_STATUS & 0xFF); + + if (gt911_read_regs(>911_client, cmd, &point_status, 1) != RT_EOK) + { + LOG_D("read point failed\n"); + read_num = 0; + goto exit_; + } + + if (point_status == 0) /* no data */ + { + read_num = 0; + goto exit_; + } + + if ((point_status & 0x80) == 0) /* data is not ready */ + { + read_num = 0; + goto exit_; + } + + touch_num = point_status & 0x0f; /* get point num */ + + if (touch_num > GT911_MAX_TOUCH) /* point num is not correct */ + { + read_num = 0; + goto exit_; + } + + cmd[0] = (rt_uint8_t)((GT911_POINT1_REG >> 8) & 0xFF); + cmd[1] = (rt_uint8_t)(GT911_POINT1_REG & 0xFF); + + /* read point num is touch_num */ + if(gt911_read_regs(>911_client, cmd, read_buf, read_num * GT911_POINT_INFO_NUM) !=RT_EOK) + { + LOG_D("read point failed\n"); + read_num = 0; + goto exit_; + } + + if(pre_touch > touch_num) /* point up */ + { + for (read_index = 0; read_index < pre_touch; read_index++) + { + rt_uint8_t j; + + for (j = 0; j < touch_num; j++) /* this time touch num */ + { + read_id = read_buf[j * 8] & 0x0F; + + if (pre_id[read_index] == read_id) /* this id is not free */ + { + break; + } + + if (j >= touch_num - 1) + { + rt_uint8_t up_id; + up_id = pre_id[read_index]; + gt911_touch_up(buf, up_id); + } + } + } + } + + if(touch_num) /* point down */ + { + rt_uint8_t off_set; + + for(read_index = 0; read_index < touch_num; read_index++) + { + off_set = read_index * 8; + read_id = read_buf[off_set] & 0x0f; + pre_id[read_index] = read_id; + input_x = read_buf[off_set + 1] | (read_buf[off_set + 2] << 8); /* x */ + input_y = read_buf[off_set + 3] | (read_buf[off_set + 4] << 8); /* y */ + input_w = read_buf[off_set + 5] | (read_buf[off_set + 6] << 8); /* size */ + + gt911_touch_down(buf, read_id, input_x, input_y, input_w); + } + } + else if (pre_touch) + { + for(read_index = 0; read_index < pre_touch; read_index++) + { + gt911_touch_up(buf, pre_id[read_index]); + } + } + + pre_touch = touch_num; + +exit_: + write_buf[0] = (rt_uint8_t)((GT911_READ_STATUS >> 8) & 0xFF); + write_buf[1] = (rt_uint8_t)(GT911_READ_STATUS & 0xFF); + write_buf[2] = 0x00; + gt911_write_reg(>911_client, write_buf, 3); + + return read_num; +} + +static rt_err_t gt911_control(struct rt_touch_device *touch, int cmd, void *arg) +{ + if (cmd == RT_TOUCH_CTRL_GET_ID) + { + return gt911_get_product_id(>911_client, arg, 6); + } + + if (cmd == RT_TOUCH_CTRL_GET_INFO) + { + return gt911_get_info(>911_client, arg); + } + + rt_uint8_t buf[4]; + rt_uint8_t i = 0; + rt_uint8_t *config = RT_NULL; + + config = (rt_uint8_t *)rt_calloc(1, sizeof(GT911_CFG_TBL) + GT911_REGITER_LEN); + if(config == RT_NULL) + { + LOG_D("malloc config memory failed\n"); + return -RT_ERROR; + } + + config[0] = (rt_uint8_t)((GT911_CONFIG_REG >> 8) & 0xFF); + config[1] = (rt_uint8_t)(GT911_CONFIG_REG & 0xFF); + + memcpy(&config[2], GT911_CFG_TBL, sizeof(GT911_CFG_TBL)); + + switch(cmd) + { + case RT_TOUCH_CTRL_SET_X_RANGE: + { + rt_uint16_t x_range; + + x_range = *(rt_uint16_t *)arg; + config[4] = (rt_uint8_t)(x_range >> 8); + config[3] = (rt_uint8_t)(x_range & 0xff); + + GT911_CFG_TBL[2] = config[4]; + GT911_CFG_TBL[1] = config[3]; + break; + } + case RT_TOUCH_CTRL_SET_Y_RANGE: + { + rt_uint16_t y_range; + + y_range = *(rt_uint16_t *)arg; + config[6] = (rt_uint8_t)(y_range >> 8); + config[5] = (rt_uint8_t)(y_range & 0xff); + + GT911_CFG_TBL[4] = config[6]; + GT911_CFG_TBL[3] = config[5]; + break; + } + case RT_TOUCH_CTRL_SET_X_TO_Y: + { + config[8] ^= (1 << 3); + break; + } + case RT_TOUCH_CTRL_SET_MODE: + { + rt_uint16_t trig_type; + trig_type = *(rt_uint16_t *)arg; + + switch (trig_type) + { + case RT_DEVICE_FLAG_INT_RX: + config[8] &= 0xFC; + break; + case RT_DEVICE_FLAG_RDONLY: + config[8] &= 0xFC; + config[8] |= 0x02; + break; + default: + break; + } + break; + } + default: + { + break; + } + } + + if(gt911_write_reg(>911_client, config, sizeof(GT911_CFG_TBL) + GT911_ADDR_LEN) != RT_EOK) + { + LOG_D("send config failed"); + return -1; + } + + buf[0] = (rt_uint8_t)((GT911_CHECK_SUM >> 8) & 0xFF); + buf[1] = (rt_uint8_t)(GT911_CHECK_SUM & 0xFF); + buf[2] = 0; + + for(i = GT911_ADDR_LEN; i < sizeof(GT911_CFG_TBL) + GT911_ADDR_LEN; i++) + { + buf[GT911_ADDR_LEN] += config[i]; + } + + buf[2] = (~buf[2]) + 1; + buf[3] = 1; + + gt911_write_reg(>911_client, buf, 4); + rt_free(config); + + return RT_EOK; +} + +static struct rt_touch_ops gt911_touch_ops = +{ + .touch_readpoint = gt911_read_point, + .touch_control = gt911_control, +}; + +int rt_hw_gt911_init(const char *name, struct rt_touch_config *cfg) +{ + struct rt_touch_device *touch_device = RT_NULL; + + touch_device = (struct rt_touch_device *)rt_malloc(sizeof(struct rt_touch_device)); + if(touch_device == RT_NULL) + { + LOG_E("touch device malloc fail"); + return -RT_ERROR; + } + rt_memset((void *)touch_device, 0, sizeof(struct rt_touch_device)); + + /* hw init*/ + rt_pin_mode(*(rt_uint8_t *)cfg->user_data, PIN_MODE_OUTPUT); + rt_pin_mode(cfg->irq_pin.pin, PIN_MODE_OUTPUT); + rt_pin_write(*(rt_uint8_t *)cfg->user_data, PIN_LOW); + rt_thread_delay(10); + rt_pin_write(*(rt_uint8_t *)cfg->user_data, PIN_HIGH); + rt_thread_delay(10); + rt_pin_write(cfg->irq_pin.pin, PIN_MODE_INPUT); + rt_thread_delay(100); + + gt911_client.bus = (struct rt_i2c_bus_device *)rt_device_find(cfg->dev_name); + + if(gt911_client.bus == RT_NULL) + { + LOG_E("Can't find %s device", cfg->dev_name); + return -RT_ERROR; + } + + if(rt_device_open((rt_device_t)gt911_client.bus, RT_DEVICE_FLAG_RDWR) != RT_EOK) + { + LOG_E("open %s device failed", cfg->dev_name); + return -RT_ERROR; + } + + gt911_client.client_addr = GT911_ADDRESS_HIGH; + gt911_soft_reset(>911_client); + + /* register touch device */ + touch_device->info.type = RT_TOUCH_TYPE_CAPACITANCE; + touch_device->info.vendor = RT_TOUCH_VENDOR_GT; + rt_memcpy(&touch_device->config, cfg, sizeof(struct rt_touch_config)); + touch_device->ops = >911_touch_ops; + + rt_hw_touch_register(touch_device, name, RT_DEVICE_FLAG_INT_RX, RT_NULL); + + LOG_I("touch device gt911 init success"); + + return RT_EOK; +} + +int gt911_init(void) +{ + struct rt_touch_config cfg; + rt_uint8_t rst_pin; + + rst_pin = RST_PIN; + cfg.dev_name = "i2c3"; + cfg.irq_pin.pin = IRQ_PIN; + cfg.irq_pin.mode = PIN_MODE_INPUT_PULLDOWN; + cfg.user_data = &rst_pin; + + rt_hw_gt911_init("gt911", &cfg); + return RT_EOK; +} +INIT_DEVICE_EXPORT(gt911_init); diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_touch.h b/bsp/imx6ull-artpi-smart/drivers/drv_touch.h new file mode 100644 index 0000000000000000000000000000000000000000..609782755b78377e1b4a62b8910c7a8e1da0fb73 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_touch.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 RiceChen the first version + */ + +#ifndef __GT911_H__ +#define __GT911_H__ + +#include "touch.h" + +#define GT911_ADDR_LEN 2 +#define GT911_REGITER_LEN 2 +#define GT911_MAX_TOUCH 5 +#define GT911_POINT_INFO_NUM 5 + +#define GT911_ADDRESS_HIGH 0x5D +#define GT911_ADDRESS_LOW 0x14 + +#define GT911_COMMAND_REG 0x8040 +#define GT911_CONFIG_REG 0x8047 + +#define GT911_PRODUCT_ID 0x8140 +#define GT911_VENDOR_ID 0x814A +#define GT911_READ_STATUS 0x814E + +#define GT911_POINT1_REG 0x814F +#define GT911_POINT2_REG 0x8157 +#define GT911_POINT3_REG 0x815F +#define GT911_POINT4_REG 0x8167 +#define GT911_POINT5_REG 0x816F + +#define GT911_CHECK_SUM 0x80FF + +int rt_hw_gt911_init(const char *name, struct rt_touch_config *cfg); + +#endif /* gt911.h */ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_uart.c b/bsp/imx6ull-artpi-smart/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..2a23cd6dbc873dca077028d27d8c49ecaf66b15e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_uart.c @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-09 Lyons first version + */ + +#include + +#ifdef RT_USING_SERIAL + +#include "board.h" +#include "drv_uart.h" +#include "drv_common.h" + +enum +{ +#ifdef BSP_USING_UART1 + eDevUart_UART1, +#endif +#ifdef BSP_USING_UART2 + eDevUart_UART2, +#endif +#ifdef BSP_USING_UART3 + eDevUart_UART3, +#endif +#ifdef BSP_USING_UART4 + eDevUart_UART4, +#endif +#ifdef BSP_USING_UART5 + eDevUart_UART5, +#endif +#ifdef BSP_USING_UART6 + eDevUart_UART6, +#endif +#ifdef BSP_USING_UART7 + eDevUart_UART7, +#endif +#ifdef BSP_USING_UART8 + eDevUart_UART8, +#endif + + eDevUart_Max, +}; + +_internal_rw struct imx_uart _s_uart[eDevUart_Max] = { +#ifdef BSP_USING_UART1 +{ + .name = "uart0", + .periph.paddr = IMX6ULL_UART1_BASE, + .irqno = UART1_IRQn, + .gpio = { + {IOMUXC_UART1_TX_DATA_UART1_TX, 0, 0x10B0}, + {IOMUXC_UART1_RX_DATA_UART1_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_115200N81, +}, +#endif + +#ifdef BSP_USING_UART2 +{ + .name = "uart1", + .periph.paddr = IMX6ULL_UART2_BASE, + .irqno = UART2_IRQn, + .gpio = { + {IOMUXC_UART2_TX_DATA_UART2_TX, 0, 0x10B0}, + {IOMUXC_UART2_RX_DATA_UART2_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART3 +{ + .name = "uart2", + .periph.paddr = IMX6ULL_UART3_BASE, + .irqno = UART3_IRQn, + .gpio = { + {IOMUXC_UART3_TX_DATA_UART3_TX, 0, 0x10B0}, + {IOMUXC_UART3_RX_DATA_UART3_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART4 +{ + .name = "uart3", + .periph.paddr = IMX6ULL_UART4_BASE, + .irqno = UART4_IRQn, + .gpio = { + {IOMUXC_UART4_TX_DATA_UART4_TX, 0, 0x10B0}, + {IOMUXC_UART4_RX_DATA_UART4_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART5 +{ + .name = "uart4", + .periph.paddr = IMX6ULL_UART5_BASE, + .irqno = UART5_IRQn, + .gpio = { + {IOMUXC_UART5_TX_DATA_UART5_TX, 0, 0x10B0}, + {IOMUXC_UART5_RX_DATA_UART5_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART6 +{ + .name = "uart5", + .periph.paddr = IMX6ULL_UART6_BASE, + .irqno = UART6_IRQn, + .gpio = { + {IOMUXC_ENET2_RX_DATA1_UART6_TX, 0, 0x10B0}, + {IOMUXC_ENET2_RX_DATA0_UART6_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART7 +{ + .name = "uart6", + .periph.paddr = IMX6ULL_UART7_BASE, + .irqno = UART7_IRQn, + .gpio = { + {IOMUXC_ENET2_TX_DATA0_UART7_TX, 0, 0x10B0}, + {IOMUXC_ENET2_RX_EN_UART7_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART8 +{ + .name = "uart7", + .periph.paddr = IMX6ULL_UART8_BASE, + .irqno = UART8_IRQn, + .gpio = { + {IOMUXC_ENET2_TX_DATA1_UART8_TX, 0, 0x10B0}, + {IOMUXC_ENET2_TX_EN_UART8_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif +}; + +static void _uart_gpio_init( struct imx_uart *device ) +{ + for (int i=0; igpio); i++) + { + imx6ull_gpio_init(&device->gpio[i]); + } +} + +static rt_err_t _uart_ops_configure( struct rt_serial_device *dev, + struct serial_configure *cfg ) +{ + struct imx_uart *uart = RT_NULL; + UART_Type *periph = RT_NULL; + rt_uint32_t reg_value; + + RT_ASSERT(RT_NULL != dev); + RT_ASSERT(RT_NULL != cfg); + + uart = (struct imx_uart*)dev; + periph = (UART_Type*)uart->periph.vaddr; + + _uart_gpio_init(uart); + + periph->UCR1 &= ~UART_UCR1_UARTEN_MASK; + + periph->UFCR &= ~UART_UFCR_RFDIV_MASK; + periph->UFCR |= UART_UFCR_RFDIV(5); + + RT_ASSERT(cfg->baud_rate <= BAUD_RATE_921600); + + periph->UBIR = UART_UBIR_INC(15); + periph->UBMR = UART_UBMR_MOD(HW_UART_BUS_CLOCK / cfg->baud_rate - 1); + + reg_value = 0; + + switch (cfg->data_bits) + { + case DATA_BITS_7: + reg_value |= UART_UCR2_WS(0); + break; + default: + reg_value |= UART_UCR2_WS(1); + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + reg_value |= UART_UCR2_STPB(1); + break; + default: + reg_value |= UART_UCR2_STPB(0); + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + reg_value |= UART_UCR2_PREN(1); + reg_value |= UART_UCR2_PROE(1); + break; + case PARITY_EVEN: + reg_value |= UART_UCR2_PREN(1); + reg_value |= UART_UCR2_PROE(0); + break; + default: + reg_value |= UART_UCR2_PREN(0); + reg_value |= UART_UCR2_PROE(0); + break; + } + + periph->UCR3 |= UART_UCR3_RXDMUXSEL(1); //this bit should always be set! + periph->UCR2 |= reg_value | UART_UCR2_IRTS(1) | UART_UCR2_TXEN(1) | UART_UCR2_RXEN(1); + periph->UCR1 |= UART_UCR1_UARTEN(1); + + return RT_EOK; +} + +static rt_err_t _uart_ops_control( struct rt_serial_device *dev, + int cmd, + void *arg ) +{ + struct imx_uart *uart = RT_NULL; + UART_Type *periph = RT_NULL; + rt_err_t result; + + RT_ASSERT(RT_NULL != dev); + + uart = (struct imx_uart*)dev; + periph = (UART_Type*)uart->periph.vaddr; + + result = RT_EOK; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + periph->UCR4 &= ~UART_UCR4_DREN_MASK; + periph->UCR4 |= UART_UCR4_DREN(0); + break; + + case RT_DEVICE_CTRL_SET_INT: + periph->UCR4 |= UART_UCR4_DREN(1); + rt_hw_interrupt_umask(uart->irqno); + break; + + default: + result = -RT_EINVAL; + break; + } + + return result; +} + +static int _uart_ops_putc( struct rt_serial_device *dev, + char ch ) +{ + struct imx_uart *uart = RT_NULL; + UART_Type *periph = RT_NULL; + + RT_ASSERT(RT_NULL != dev); + + uart = (struct imx_uart*)dev; + periph = (UART_Type*)uart->periph.vaddr; + + while (0 == (periph->USR2 & UART_USR2_TXDC_MASK)); + periph->UTXD = ch; + + return 1; +} + +static int _uart_ops_getc( struct rt_serial_device *dev ) +{ + struct imx_uart *uart = RT_NULL; + UART_Type *periph = RT_NULL; + int ch; + + RT_ASSERT(RT_NULL != dev); + + uart = (struct imx_uart*)dev; + periph = (UART_Type*)uart->periph.vaddr; + + ch = (0 == (periph->USR2 & UART_USR2_RDR_MASK)) ? -1 : periph->URXD; + return ch; +} + +_internal_ro struct rt_uart_ops _k_uart_ops = +{ + _uart_ops_configure, /* configure */ + _uart_ops_control, /* control */ + _uart_ops_putc, /* putc */ + _uart_ops_getc, /* getc */ + RT_NULL, /* dma_transmit */ +}; + +static void _uart_isr( int irqno, void* parameter ) +{ + struct rt_serial_device *serial; + + rt_interrupt_enter(); + + serial = (struct rt_serial_device *)parameter; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + + rt_interrupt_leave(); +} + +int rt_hw_uart_init(void) +{ + for (int idx=0; idx +#include +#include +#include +#include +#include +#include +#include +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) + +#ifdef BSP_USING_USB_DEVICE +static usb_device_handle ehci0_handle; +static struct udcd _fsl_udc_0; + +static usb_status_t usb_device_callback(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); +static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_device_endpoint_callback_message_struct_t *message, void *callbackParam); + +#define virtual_to_physical(v) ((void *)((size_t)v + PV_OFFSET)) +#define physical_to_virtual(p) ((void *)((size_t)p - PV_OFFSET)) + +static void USB_DeviceIsrEnable(uint8_t controllerId) +{ + uint8_t irqNumber; +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + uint8_t usbDeviceEhciIrq[] = USBHS_IRQS; + irqNumber = usbDeviceEhciIrq[controllerId - kUSB_ControllerEhci0]; +#endif + /* Install isr, set priority, and enable IRQ. */ +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority((IRQn_Type)irqNumber, 3); +#else + NVIC_SetPriority((IRQn_Type)irqNumber, 3); +#endif + EnableIRQ((IRQn_Type)irqNumber); +} + +/*! + * @brief Initializes USB specific setting that was not set by the Clocks tool. + */ +static void USB_DeviceClockInit(uint8_t controllerId) +{ +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, + }; +#endif +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + if (controllerId == kUSB_ControllerEhci0) + { + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); + } + else + { + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U); + } + USB_EhciPhyInit(controllerId, 0, &phyConfig); +#endif +} + +static struct ep_id _ehci0_ep_pool[] = +{ + {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, + {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, +}; + +/*! + * @brief USB Interrupt service routine. + * + * This function serves as the USB interrupt service routine. + * + * @return None. + */ +void USB_OTG1_IRQHandler(int irq, void *base) +{ + USB_DeviceEhciIsrFunction(ehci0_handle); +} + +static rt_err_t _ehci0_ep_set_stall(rt_uint8_t address) +{ + USB_DeviceStallEndpoint(ehci0_handle, address); + return RT_EOK; +} + +static rt_err_t _ehci0_ep_clear_stall(rt_uint8_t address) +{ + USB_DeviceUnstallEndpoint(ehci0_handle, address); + return RT_EOK; +} + +static rt_err_t _ehci0_set_address(rt_uint8_t address) +{ + USB_DeviceSetStatus(ehci0_handle, kUSB_DeviceStatusAddress, &address); + return RT_EOK; +} + +static rt_err_t _ehci0_set_config(rt_uint8_t address) +{ + return RT_EOK; +} + +static rt_err_t _ehci0_ep_enable(uep_t ep) +{ + usb_device_endpoint_init_struct_t ep_init; + usb_device_endpoint_callback_struct_t ep_callback; + rt_uint32_t param = ep->ep_desc->bEndpointAddress; + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + ep_init.maxPacketSize = ep->ep_desc->wMaxPacketSize; + ep_init.endpointAddress = ep->ep_desc->bEndpointAddress; + ep_init.transferType = ep->ep_desc->bmAttributes; + ep_init.zlt = 0; + ep_callback.callbackFn = usb_device_endpoint_callback; + ep_callback.callbackParam = (void *)param; + ep_callback.isBusy = 0; + USB_DeviceInitEndpoint(ehci0_handle, &ep_init, &ep_callback); + return RT_EOK; +} +static rt_err_t _ehci0_ep_disable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + USB_DeviceDeinitEndpoint(ehci0_handle, ep->ep_desc->bEndpointAddress); + return RT_EOK; +} + +static rt_size_t _ehci0_ep_read(rt_uint8_t address, void *buffer) +{ + rt_size_t size = 0; + + RT_ASSERT(buffer != RT_NULL); + + return size; +} + +static rt_size_t _ehci0_ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) +{ + USB_DeviceRecvRequest(ehci0_handle, address, buffer, size); + return size; +} + +static rt_size_t _ehci0_ep_write(rt_uint8_t address, void *buffer, rt_size_t size) +{ + USB_DeviceSendRequest(ehci0_handle, address, buffer, size); + return size; +} + + +static rt_err_t _ehci0_ep0_send_status(void) +{ + _ehci0_ep_write(0x00, NULL, 0); + return RT_EOK; +} + +static rt_err_t _ehci0_suspend(void) +{ + return RT_EOK; +} + +static rt_err_t _ehci0_wakeup(void) +{ + return RT_EOK; +} + +const static struct udcd_ops _ehci0_udc_ops = +{ + _ehci0_set_address, + _ehci0_set_config, + _ehci0_ep_set_stall, + _ehci0_ep_clear_stall, + _ehci0_ep_enable, + _ehci0_ep_disable, + _ehci0_ep_read_prepare, + _ehci0_ep_read, + _ehci0_ep_write, + _ehci0_ep0_send_status, + _ehci0_suspend, + _ehci0_wakeup, +}; +extern void rt_hw_interrupt_umask(int vector); +static rt_err_t drv_ehci0_usbd_init(rt_device_t device) +{ + usb_status_t result; + + USB_DeviceClockInit(kUSB_ControllerEhci0); + + result = USB_DeviceInit(kUSB_ControllerEhci0, usb_device_callback, &ehci0_handle); + + RT_ASSERT(ehci0_handle); + if(result == kStatus_USB_Success) + { + rt_hw_interrupt_install(75, USB_OTG1_IRQHandler, (void *)ehci0_handle,"usb1_intr"); + rt_hw_interrupt_umask(75); + USB_DeviceRun(ehci0_handle); + } + else + { + rt_kprintf("USB_DeviceInit ehci0 error\r\n"); + return RT_ERROR; + } + return RT_EOK; +} + +struct rt_device_ops imx6ull_usb_ops = +{ + drv_ehci0_usbd_init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, +}; + +static int rt_usbd_init(void) +{ + rt_memset((void *)&_fsl_udc_0, 0, sizeof(struct udcd)); + _fsl_udc_0.parent.type = RT_Device_Class_USBDevice; + _fsl_udc_0.parent.ops = &imx6ull_usb_ops; + _fsl_udc_0.ops = &_ehci0_udc_ops; + /* Register endpoint infomation */ + _fsl_udc_0.ep_pool = _ehci0_ep_pool; + _fsl_udc_0.ep0.id = &_ehci0_ep_pool[0]; + + _fsl_udc_0.device_is_hs = RT_FALSE; + rt_device_register((rt_device_t)&_fsl_udc_0, "usbd", 0); + rt_usb_device_init(); + + return 0; +} +INIT_DEVICE_EXPORT(rt_usbd_init); + +static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_device_endpoint_callback_message_struct_t *message, void *callbackParam) +{ + rt_uint32_t ep_addr = (rt_uint32_t)callbackParam; + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + udcd_t udcd = RT_NULL; + uint8_t state; + if(deviceHandle->controllerId == kUSB_ControllerEhci0) + udcd = &_fsl_udc_0; + + if(message->isSetup) + { + rt_usbd_ep0_setup_handler(udcd, (struct urequest*)message->buffer); + } + else if(ep_addr == 0x00) + { + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + if(state == kUSB_DeviceStateAddressing) + { + if (kStatus_USB_Success == USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL)) + { + state = kUSB_DeviceStateAddress; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + } + rt_usbd_ep0_out_handler(udcd, message->length); + } + else if(ep_addr == 0x80) + { + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + if(state == kUSB_DeviceStateAddressing) + { + if (kStatus_USB_Success == USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL)) + { + state = kUSB_DeviceStateAddress; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + } + rt_usbd_ep0_in_handler(udcd); + } + else if(ep_addr & 0x80) + { + rt_usbd_ep_in_handler(udcd, ep_addr, message->length); + } + else + { + rt_usbd_ep_out_handler(udcd, ep_addr, message->length); + } + return kStatus_USB_Success; +} + +static usb_status_t usb_device_callback(usb_device_handle handle, uint32_t callbackEvent, void *eventParam) +{ + usb_status_t error = kStatus_USB_Error; + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_device_endpoint_init_struct_t ep0_init = + { + 0x40, + 0x00, + USB_EP_ATTR_CONTROL, + 0 + }; + usb_device_endpoint_callback_struct_t ep0_callback = + { + usb_device_endpoint_callback, + 0, + 0 + }; + udcd_t udcd = RT_NULL; + if(deviceHandle->controllerId == kUSB_ControllerEhci0) + udcd = &_fsl_udc_0; + + switch (callbackEvent) + { + case kUSB_DeviceEventBusReset: + ep0_init.endpointAddress = 0x00; + ep0_callback.callbackParam = (void *)0x00; + USB_DeviceInitEndpoint(deviceHandle, &ep0_init, &ep0_callback); + ep0_init.endpointAddress = 0x80; + ep0_callback.callbackParam = (void *)0x80; + USB_DeviceInitEndpoint(deviceHandle, &ep0_init, &ep0_callback); + rt_usbd_reset_handler(udcd); + break; + case kUSB_DeviceEventAttach: + rt_usbd_connect_handler(udcd); + break; + case kUSB_DeviceEventDetach: + rt_usbd_disconnect_handler(udcd); + break; + } + return error; +} + +#endif + +/********************* end of file ************************/ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_wdt.c b/bsp/imx6ull-artpi-smart/drivers/drv_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..763b6526daff95d1d3b26b7c7affbcc48964d4e4 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_wdt.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-28 songchao first version + */ + +#include + +#ifdef RT_USING_WDT +#include +#include +#include "drv_wdt.h" +#include "fsl_wdog.h" +#include "imx6ull.h" + +enum +{ +#ifdef RT_USING_WDT1 + DEV_WDT1, +#endif + +#ifdef RT_USING_WDT2 + DEV_WDT2, +#endif + +#ifdef RT_USING_WDT3 + DEV_WDT3, +#endif + + DEV_MAX, +}; + +#ifdef RT_USING_WDT1 +static wdog_config_t WDOG_1_config = +{ + .timeoutValue = 0xffu, + .enablePowerDown = false, + .softwareResetExtension = false, + .softwareAssertion = true, + .softwareResetSignal = true, + .enableWdog = true, + .workMode = + { + .enableWait = false, + .enableStop = false, + .enableDebug = false, + }, + .enableInterrupt = false, + .interruptTimeValue = 0x04u, +}; +#endif + +#ifdef RT_USING_WDT2 +static wdog_config_t WDOG_2_config = +{ + .timeoutValue = 0xffu, + .enablePowerDown = false, + .softwareResetExtension = false, + .softwareAssertion = true, + .softwareResetSignal = true, + .enableWdog = true, + .workMode = + { + .enableWait = false, + .enableStop = false, + .enableDebug = false, + }, + .enableInterrupt = false, + .interruptTimeValue = 0x04u, +}; +#endif + +#ifdef RT_USING_WDT3 +static wdog_config_t WDOG_3_config = +{ + .timeoutValue = 0xffu, + .enablePowerDown = false, + .softwareResetExtension = false, + .softwareAssertion = true, + .softwareResetSignal = true, + .enableWdog = true, + .workMode = + { + .enableWait = false, + .enableStop = false, + .enableDebug = false, + }, + .enableInterrupt = false, + .interruptTimeValue = 0x04u, +}; +#endif + +static rt_watchdog_t imx6ull_watchdog[DEV_MAX] = +{ +#ifdef RT_USING_WDT1 + { + .name = "wdt1", + .paddr = IMX6ULL_WATCHDOG1_BASE, + .config = &WDOG_1_config, + }, +#endif + +#ifdef RT_USING_WDT2 + { + .name = "wdt2", + .paddr = IMX6ULL_WATCHDOG2_BASE, + .config = &WDOG_2_config, + }, +#endif + +#ifdef RT_USING_WDT3 + { + .name = "wdt3", + .paddr = IMX6ULL_WATCHDOG3_BASE, + .config = &WDOG_3_config, + }, +#endif + +}; + +static rt_err_t imx6ull_wdog_init(rt_watchdog_t *wdt) +{ + WDOG_Type *base = RT_NULL; + base = (WDOG_Type *)wdt->vaddr; + WDOG_Init(base, wdt->config); + WDOG_Disable(base); + return RT_EOK; +} + +static rt_err_t imx6ull_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) +{ + RT_ASSERT(wdt != NULL); + + WDOG_Type *base = RT_NULL; + base = (WDOG_Type *)wdt->vaddr; + + switch(cmd) + { + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + { + *(uint16_t *)args = (base->WCR >> 8) / 2; + } + break; + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + { + RT_ASSERT(*(uint16_t *)args != 0); + WDOG_SetTimeoutValue(base, (*(uint16_t *)args) * 2); + WDOG_Disable(base); + } + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + { + WDOG_Refresh(base); + } + break; + case RT_DEVICE_CTRL_WDT_START: + { + WDOG_Enable(base); + } + break; + case RT_DEVICE_CTRL_WDT_STOP: + { + WDOG_Disable(base); + } + break; + default: + return RT_EINVAL; + } + + return RT_EOK; +} + +static struct rt_watchdog_ops imx6ull_wdog_ops = +{ + .init = imx6ull_wdog_init, + .control = imx6ull_wdog_control, +}; + +int rt_hw_wdt_init(void) +{ + rt_err_t ret = RT_EOK; + for(int idx = 0; idx < GET_ARRAY_NUM(imx6ull_watchdog); idx++) + { + imx6ull_watchdog[idx].ops = &imx6ull_wdog_ops; + imx6ull_watchdog[idx].vaddr = platform_get_periph_vaddr(imx6ull_watchdog[idx].paddr); + ret = rt_hw_watchdog_register(&imx6ull_watchdog[idx], imx6ull_watchdog[idx].name, + RT_DEVICE_FLAG_DEACTIVATE, RT_NULL); + if (ret != RT_EOK) + { + LOG_E("rt device register failed %d\n", ret); + } + } + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_wdt_init); + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_wdt.h b/bsp/imx6ull-artpi-smart/drivers/drv_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..54b49b7300ab194c2fdb647e5e9de9d93a72b2e4 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_wdt.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-28 songchao first version + */ + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#include +#include "fsl_wdog.h" + +#define RT_DEVICE_CTRL_WDT_GET_TIMEOUT (1) /* get timeout(in seconds) */ +#define RT_DEVICE_CTRL_WDT_SET_TIMEOUT (2) /* set timeout(in seconds) */ +#define RT_DEVICE_CTRL_WDT_GET_TIMELEFT (3) /* get the left time before reboot(in seconds) */ +#define RT_DEVICE_CTRL_WDT_KEEPALIVE (4) /* refresh watchdog */ +#define RT_DEVICE_CTRL_WDT_START (5) /* start watchdog */ +#define RT_DEVICE_CTRL_WDT_STOP (6) /* stop watchdog */ + +struct rt_watchdog_ops; +struct rt_watchdog_device +{ + struct rt_device parent; + const struct rt_watchdog_ops *ops; + const char *name; + rt_uint32_t paddr; + rt_uint32_t vaddr; + rt_uint32_t irqno; + wdog_config_t *config; +}; +typedef struct rt_watchdog_device rt_watchdog_t; + +struct rt_watchdog_ops +{ + rt_err_t (*init)(rt_watchdog_t *wdt); + rt_err_t (*control)(rt_watchdog_t *wdt, int cmd, void *arg); +}; + +rt_err_t rt_hw_watchdog_register(rt_watchdog_t *wdt, + const char *name, + rt_uint32_t flag, + void *data); + +#endif /* __WATCHDOG_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/imx6ull.h b/bsp/imx6ull-artpi-smart/drivers/imx6ull.h new file mode 100644 index 0000000000000000000000000000000000000000..1fd81f59966d67dfa3a496600a717efb9a0ad8ec --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/imx6ull.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-22 quanzhao first version + */ + +#ifndef __IMX6UL_H__ +#define __IMX6UL_H__ + +#include +#include + +#ifdef RT_USING_LWP +#include +#include +#endif + +enum _gic_base_offsets +{ + kGICDBaseOffset = 0x1000, //!< GIC distributor offset. + kGICCBaseOffset = 0x2000 //!< GIC CPU interface offset. +}; + +/* SOC-relative definitions */ +enum _imx_interrupts +{ + SW_INTERRUPT_0 = 0, //!< Software interrupt 0. + SW_INTERRUPT_1 = 1, //!< Software interrupt 1. + SW_INTERRUPT_2 = 2, //!< Software interrupt 2. + SW_INTERRUPT_3 = 3, //!< Software interrupt 3. + SW_INTERRUPT_4 = 4, //!< Software interrupt 4. + SW_INTERRUPT_5 = 5, //!< Software interrupt 5. + SW_INTERRUPT_6 = 6, //!< Software interrupt 6. + SW_INTERRUPT_7 = 7, //!< Software interrupt 7. + SW_INTERRUPT_8 = 8, //!< Software interrupt 8. + SW_INTERRUPT_9 = 9, //!< Software interrupt 9. + SW_INTERRUPT_10 = 10, //!< Software interrupt 10. + SW_INTERRUPT_11 = 11, //!< Software interrupt 11. + SW_INTERRUPT_12 = 12, //!< Software interrupt 12. + SW_INTERRUPT_13 = 13, //!< Software interrupt 13. + SW_INTERRUPT_14 = 14, //!< Software interrupt 14. + SW_INTERRUPT_15 = 15, //!< Software interrupt 15. + RSVD_INTERRUPT_16 = 16, //!< Reserved. + RSVD_INTERRUPT_17 = 17, //!< Reserved. + RSVD_INTERRUPT_18 = 18, //!< Reserved. + RSVD_INTERRUPT_19 = 19, //!< Reserved. + RSVD_INTERRUPT_20 = 20, //!< Reserved. + RSVD_INTERRUPT_21 = 21, //!< Reserved. + RSVD_INTERRUPT_22 = 22, //!< Reserved. + RSVD_INTERRUPT_23 = 23, //!< Reserved. + RSVD_INTERRUPT_24 = 24, //!< Reserved. + RSVD_INTERRUPT_25 = 25, //!< Reserved. + RSVD_INTERRUPT_26 = 26, //!< Reserved. + RSVD_INTERRUPT_27 = 27, //!< Reserved. + RSVD_INTERRUPT_28 = 28, //!< Reserved. + RSVD_INTERRUPT_29 = 29, //!< Reserved. + RSVD_INTERRUPT_30 = 30, //!< Reserved. + RSVD_INTERRUPT_31 = 31, //!< Reserved. + IMX_INT_IOMUXC_GPR = 32, //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot. + IMX_INT_CHEETAH_CSYSPWRUPREQ = 33, //!< @todo Listed as DAP in RM + IMX_INT_SDMA = 34, //!< Logical OR of all 48 SDMA interrupt requests/events from all channels. + IMX_INT_TSC = 35, //!< TSC + IMX_INT_SNVS_LP_SET_PWR_OFF = 36, //!< PMIC power off request. + IMX_INT_LCDIF = 37, //!< LCDIF interrupt request. + IMX_INT_BEE = 38, //!< BEE interrupt request. + IMX_INT_CSI = 39, //!< CMOS Sensor Interface interrupt request. + IMX_INT_PXP = 40, //!< PXP interrupt request. + IMX_INT_SCTR1 = 41, //!< SCTR1 + IMX_INT_SCTR2 = 42, //!< SCTR2 + IMX_INT_WDOG3 = 43, //!< WDOG3 timer reset interrupt request. + IMX_INT_INTERRUPT_44 = 44, //!< Reserved. + IMX_INT_APBH_DMA = 45, //!< APBH DMA + IMX_INT_EIM = 46, //!< EIM interrupt request. + IMX_INT_NAND_BCH = 47, //!< Reserved. + IMX_INT_NAND_GPMI = 48, //!< Reserved. + IMX_INT_UART6 = 49, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_50 = 50, //!< Reserved. + IMX_INT_SNVS = 51, //!< SNVS consolidated interrupt. + IMX_INT_SNVS_SEC = 52, //!< SNVS security interrupt. + IMX_INT_CSU = 53, //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. + IMX_INT_USDHC1 = 54, //!< uSDHC1 (Enhanced SDHC) interrupt request. + IMX_INT_USDHC2 = 55, //!< uSDHC2 (Enhanced SDHC) interrupt request. + IMX_INT_SAI3 = 56, //!< uSDHC3 (Enhanced SDHC) interrupt request. + IMX_INT_SAI4 = 57, //!< uSDHC4 (Enhanced SDHC) interrupt request. + IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests. + IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests. + IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests. + IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests. + IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests. + IMX_INT_ECSPI1 = 63, //!< eCSPI1 interrupt request. + IMX_INT_ECSPI2 = 64, //!< eCSPI2 interrupt request. + IMX_INT_ECSPI3 = 65, //!< eCSPI3 interrupt request. + IMX_INT_ECSPI4 = 66, //!< eCSPI4 interrupt request. + IMX_INT_I2C4 = 67, //!< Reserved. + IMX_INT_I2C1 = 68, //!< I2C1 interrupt request. + IMX_INT_I2C2 = 69, //!< I2C2 interrupt request. + IMX_INT_I2C3 = 70, //!< I2C3 interrupt request. + IMX_INT_UART7 = 71, //!< Logical OR of UART5 interrupt requests. + IMX_INT_UART8 = 72, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_73 = 73, //!< Reserved. + IMX_INT_USB_OTG2 = 74, //!< USB Host 1 interrupt request. + IMX_INT_USB_OTG1 = 75, //!< USB OTG1 interrupt request. + IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request. + IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request. + IMX_INT_CAAM_JQ2 = 78, //!< SSI1 interrupt request. + IMX_INT_CAAM_ERR = 79, //!< SSI2 interrupt request. + IMX_INT_CAAM_RTIC = 80, //!< SSI3 interrupt request. + IMX_INT_TEMPERATURE = 81, //!< Temperature Sensor (temp. greater than threshold) interrupt request. + IMX_INT_ASRC = 82, //!< Reserved. + IMX_INT_INTERRUPT_83 = 83, //!< Reserved. + IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts. + IMX_INT_INTERRUPT_85 = 85, //!< Reserved. + IMX_INT_PMU_ANA_BO = 86, //!< PMU analog regulator brown-out interrupt request. + IMX_INT_GPT1 = 87, // + IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt. + IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt. + IMX_INT_GPIO1_INT7 = 90, //!< INT7 interrupt request. + IMX_INT_GPIO1_INT6 = 91, //!< INT6 interrupt request. + IMX_INT_GPIO1_INT5 = 92, //!< INT5 interrupt request. + IMX_INT_GPIO1_INT4 = 93, //!< INT4 interrupt request. + IMX_INT_GPIO1_INT3 = 94, //!< INT3 interrupt request. + IMX_INT_GPIO1_INT2 = 95, //!< INT2 interrupt request. + IMX_INT_GPIO1_INT1 = 96, //!< INT1 interrupt request. + IMX_INT_GPIO1_INT0 = 97, //!< INT0 interrupt request. + IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15. + IMX_INT_GPIO1_INT31_16 = 99, //!< Combined interrupt indication for GPIO1 signals 16 - 31. + IMX_INT_GPIO2_INT15_0 = 100, //!< Combined interrupt indication for GPIO2 signals 0 - 15. + IMX_INT_GPIO2_INT31_16 = 101, //!< Combined interrupt indication for GPIO2 signals 16 - 31. + IMX_INT_GPIO3_INT15_0 = 102, //!< Combined interrupt indication for GPIO3 signals 0 - 15. + IMX_INT_GPIO3_INT31_16 = 103, //!< Combined interrupt indication for GPIO3 signals 16 - 31. + IMX_INT_GPIO4_INT15_0 = 104, //!< Combined interrupt indication for GPIO4 signals 0 - 15. + IMX_INT_GPIO4_INT31_16 = 105, //!< Combined interrupt indication for GPIO4 signals 16 - 31. + IMX_INT_GPIO5_INT15_0 = 106, //!< Combined interrupt indication for GPIO5 signals 0 - 15. + IMX_INT_GPIO5_INT31_16 = 107, //!< Combined interrupt indication for GPIO5 signals 16 - 31. + IMX_INT_INTERRUPT_108 = 108, //!< Reserved. + IMX_INT_INTERRUPT_109 = 109, //!< Reserved. + IMX_INT_INTERRUPT_110 = 110, //!< Reserved. + IMX_INT_INTERRUPT_111 = 111, //!< Reserved. + IMX_INT_WDOG1 = 112, //!< WDOG1 timer reset interrupt request. + IMX_INT_WDOG2 = 113, //!< WDOG2 timer reset interrupt request. + IMX_INT_KPP = 114, //!< Key Pad interrupt request. + IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1. + IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2. + IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1. + IMX_INT_INTERRUPT_122 = 122, //!< Reserved. + IMX_INT_SRC = 123, //!< SRC interrupt request. + IMX_INT_INTERRUPT_124 = 124, //!< Logical OR of all L2 interrupt requests. + IMX_INT_INTERRUPT_125 = 125, //!< Parity Check error interrupt request. + IMX_INT_CHEETAH_PERFORM = 126, //!< Logical OR of Performance Unit interrupts. + IMX_INT_CHEETAH_TRIGGER = 127, //!< Logical OR of CTI trigger outputs. + IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC. + IMX_INT_SAI1 = 129, //!< EPDC interrupt request. + IMX_INT_SAI2 = 130, //!< EPDC interrupt request. + IMX_INT_INTERRUPT_131 = 131, //!< DCP general interrupt request. + IMX_INT_ADC1 = 132, //!< DCP channel 0 interrupt request. + IMX_INT_ADC2 = 133, //!< DCP secure interrupt request. + IMX_INT_INTERRUPT_134 = 134, //!< Reserved. + IMX_INT_INTERRUPT_135 = 135, //!< Reserved. + IMX_INT_SJC = 136, //!< SJC interrupt from General Purpose register. + IMX_INT_CAAM_0 = 137, //!< Reserved. + IMX_INT_CAAM_1 = 138, //!< Reserved. + IMX_INT_QSPI = 139, //!< Reserved. + IMX_INT_TZASC1 = 140, //!< ASC1 interrupt request. + IMX_INT_GPT2 = 141, //!< Reserved. + IMX_INT_CAN1 = 142, //!< Reserved. + IMX_INT_CAN2 = 143, //!< Reserved. + IMX_INT_SIM1 = 144, //!< Reserved. + IMX_INT_SIM2 = 145, //!< Reserved. + IMX_INT_PWM5 = 146, //!< Fast Ethernet Controller interrupt request. + IMX_INT_PWM6 = 147, //!< Reserved. + IMX_INT_PWM7 = 148, //!< Reserved. + IMX_INT_PWM8 = 149, //!< Reserved. + IMX_INT_ENET1 = 150, //!< Reserved. + IMX_INT_ENET1_TIMER = 151, //!< Reserved. + IMX_INT_ENET2 = 152, //!< Reserved. + IMX_INT_ENET2_TIMER = 153, //!< Reserved. + IMX_INT_INTERRUPT_154 = 154, //!< Reserved. + IMX_INT_INTERRUPT_155 = 155, //!< Reserved. + IMX_INT_INTERRUPT_156 = 156, //!< Reserved. + IMX_INT_INTERRUPT_157 = 157, //!< Reserved. + IMX_INT_INTERRUPT_158 = 158, //!< Reserved. + IMX_INT_PMU_DIG_BO = 159, //!< //!< PMU digital regulator brown-out interrupt request. + IMX_INTERRUPT_COUNT = 160 //!< Total number of interrupts. +}; + +/* SOC-relative definitions */ +#include "MCIMX6Y2.h" + +#include "fsl_cache.h" +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "fsl_elcdif.h" +#include "fsl_usdhc.h" +#include "fsl_card.h" +#include "fsl_wdog.h" +#include "fsl_i2c.h" +#include "fsl_ecspi.h" +#include "fsl_snvs_hp.h" +#include "fsl_adc.h" + +#define IMX6ULL_PERIPH_SIZE (16 * 1024) + +/* Interrupt Control Interface */ +#define ARM_GIC_CPU_BASE 0x00A00000 + +/* + * Peripheral addresses + */ +#define IMX6ULL_UART1_BASE UART1_BASE /* UART 1 */ +#define IMX6ULL_UART2_BASE UART2_BASE /* UART 2 */ +#define IMX6ULL_UART3_BASE UART3_BASE /* UART 3 */ +#define IMX6ULL_UART4_BASE UART4_BASE /* UART 4 */ +#define IMX6ULL_UART5_BASE UART5_BASE /* UART 5 */ +#define IMX6ULL_UART6_BASE UART6_BASE /* UART 6 */ +#define IMX6ULL_UART7_BASE UART7_BASE /* UART 7 */ +#define IMX6ULL_UART8_BASE UART8_BASE /* UART 8 */ + +#define IMX6ULL_WATCHDOG1_BASE WDOG1_BASE /* watchdog 1 */ +#define IMX6ULL_WATCHDOG2_BASE WDOG2_BASE /* watchdog 2 */ +#define IMX6ULL_WATCHDOG3_BASE WDOG3_BASE /* watchdog 3 */ + +#define IMX6ULL_GPIO1_BASE GPIO1_BASE /* GPIO port 0 */ +#define IMX6ULL_GPIO2_BASE GPIO2_BASE /* GPIO port 1 */ +#define IMX6ULL_GPIO3_BASE GPIO3_BASE /* GPIO port 2 */ +#define IMX6ULL_GPIO4_BASE GPIO4_BASE /* GPIO port 3 */ +#define IMX6ULL_GPIO5_BASE GPIO5_BASE /* GPIO port 4 */ + +#define IMX6ULL_SNVS_BASE SNVS_BASE /* Real Time Clock */ + +#define IMX6ULL_SCTL_BASE 0x021DC000u /* System Controller */ + +#define IMX6ULL_CLCD_BASE LCDIF_BASE /* CLCD */ + +#define IMX6ULL_GIC_DIST_BASE (ARM_GIC_CPU_BASE+kGICDBaseOffset) /* Generic interrupt controller distributor */ +#define IMX6ULL_GIC_CPU_BASE (ARM_GIC_CPU_BASE+kGICCBaseOffset) /* Generic interrupt controller CPU interface */ + +#define IMX6ULL_IOMUXC_BASE IOMUXC_BASE +#define IMX6ULL_IOMUXC_SNVS_BASE IOMUXC_SNVS_BASE +#define IMX6ULL_IOMUXC_GPR_BASE IOMUXC_GPR_BASE + +#define IMX6ULL_CCM_BASE 0x20C4000u +#define IMX6ULL_CCM_ANALOGY_BASE 0x20C8000u +#define IMX6ULL_PMU_BASE 0x20C8110u + +#define IMX6ULL_ENET1_BASE ENET1_BASE +#define IMX6ULL_ENET2_BASE ENET2_BASE + +#define IMX6ULL_GPT1_BASE GPT1_BASE +#define IMX6ULL_GPT2_BASE GPT2_BASE + +#define IMX6ULL_ECSPI1_BASE ECSPI1_BASE +#define IMX6ULL_ECSPI2_BASE ECSPI2_BASE +#define IMX6ULL_ECSPI3_BASE ECSPI3_BASE +#define IMX6ULL_ECSPI4_BASE ECSPI4_BASE + +#define IMX6ULL_I2C1_BASE I2C1_BASE +#define IMX6ULL_I2C2_BASE I2C2_BASE +#define IMX6ULL_I2C3_BASE I2C3_BASE +#define IMX6ULL_I2C4_BASE I2C4_BASE + +#define IMX6ULL_SDMA_BASE SDMAARM_BASE + +#define IMX6ULL_USDHC1_BASE USDHC1_BASE +#define IMX6ULL_USDHC2_BASE USDHC2_BASE + +#define IMX6ULL_SRC_BASE SRC_BASE + +#define IMX6ULL_GPMI_BASE GPMI_BASE +#define IMX6ULL_BCH_BASE BCH_BASE +#define IMX6ULL_APBH_BASE APBH_BASE + +#define IMX6ULL_CSI_BASE CSI_BASE + +#define IMX6ULL_CAN1_BASE CAN1_BASE +#define IMX6ULL_CAN2_BASE CAN2_BASE + +#define IMX6ULL_USBPHY1_BASE 0x20C9000u +#define IMX6ULL_USBPHY2_BASE 0x20CA000u + +#define IMX6ULL_USB1_BASE 0x2184000u +#define IMX6ULL_USB2_BASE 0x2184200u + +#define IMX6ULL_USB_ANALOG_BASE 0x20C81A0u +/* the maximum number of gic */ +#define ARM_GIC_MAX_NR 1 + +#define _internal_ro static const +#define _internal_rw static +#define _internal_zi static + +#define GET_ARRAY_NUM(ins) ((uint32_t)(sizeof(ins)/sizeof(ins[0]))) + +#include "bsp_clock.h" + +/* the maximum number of interrupts */ +#define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT + +/* the maximum entries of the interrupt table */ +#define MAX_HANDLERS IMX_INTERRUPT_COUNT + +/* the basic constants needed by gic */ +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + rt_uint32_t gic_base; + asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base)); + return gic_base + kGICDBaseOffset; +} + +rt_inline rt_uint32_t platform_get_gic_cpu_base(void) +{ + rt_uint32_t gic_base; + asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base)); + return gic_base + kGICCBaseOffset; +} + +RT_WEAK void *rt_hw_kernel_virt_to_phys(void *v_addr) +{ + void *p_addr = 0; +#ifdef RT_USING_USERSPACE + rt_base_t level; + + extern rt_mmu_info mmu_info; + extern void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr); + + level = rt_hw_interrupt_disable(); + p_addr = _rt_hw_mmu_v2p(&mmu_info, v_addr); + rt_hw_interrupt_enable(level); +#else + p_addr = v_addr; +#endif + + return p_addr; +} + +rt_inline rt_uint32_t platform_get_periph_vaddr(rt_uint32_t paddr) +{ +#ifdef RT_USING_USERSPACE + rt_uint32_t mask = IMX6ULL_PERIPH_SIZE - 1; + return (rt_uint32_t)rt_ioremap((void*)(paddr&(~mask)), IMX6ULL_PERIPH_SIZE) + (paddr & mask); +#else + return paddr; +#endif +} + +rt_inline uint32_t mem_map_v2p(uint32_t virt) +{ +#ifdef RT_USING_USERSPACE + return virt + PV_OFFSET; +#else + return virt; +#endif +} + +rt_inline uint32_t mem_map_p2v(uint32_t phys) +{ +#ifdef RT_USING_USERSPACE + return phys - PV_OFFSET; +#else + return phys; +#endif +} + +#define GIC_IRQ_START 0 + +#define GIC_ACK_INTID_MASK 0x000003ff + +/* the definition needed by gic.c */ +#define __REG32(x) (*((volatile unsigned int *)(x))) + +/* keep compatible with platform SDK */ +typedef enum { + CPU_0, + CPU_1, + CPU_2, + CPU_3, +} cpuid_e; + +enum _gicd_sgi_filter +{ + //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter. + kGicSgiFilter_UseTargetList = 0, + + //! Forward the interrupt to all CPU interfaces except that of the processor that requested + //! the interrupt. + kGicSgiFilter_AllOtherCPUs = 1, + + //! Forward the interrupt only to the CPU interface of the processor that requested the + //! interrupt. + kGicSgiFilter_OnlyThisCPU = 2 +}; + +typedef void (*irq_hdlr_t) (void); + +extern void rt_hw_interrupt_mask(int vector); +extern void rt_hw_interrupt_umask(int vector); +extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr) +{ + rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, RT_NULL, "unknown"); +} + +rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority) +{ + rt_hw_interrupt_umask(irq_id); +} + +rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id) +{ + rt_hw_interrupt_mask(irq_id); +} + +#endif /* __IMX6UL_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/rt_lcd.h b/bsp/imx6ull-artpi-smart/drivers/rt_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..c79400888410a2901c45f01d0cd5fd39de3ba408 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/rt_lcd.h @@ -0,0 +1,59 @@ +#ifndef RT_LCD_H__ +#define RT_LCD_H__ + + +/* ioctls + 0x46 is 'F' */ +#define FBIOGET_VSCREENINFO 0x4600 +#define FBIOPUT_VSCREENINFO 0x4601 +#define FBIOGET_FSCREENINFO 0x4602 +#define FBIOGETCMAP 0x4604 +#define FBIOPUTCMAP 0x4605 +#define FBIOPAN_DISPLAY 0x4606 +#define FBIO_CURSOR 0x4608 +/* #define FBIOGET_MONITORSPEC 0x460C */ +/* #define FBIOPUT_MONITORSPEC 0x460D */ +/* #define FBIOSWITCH_MONIBIT 0x460E */ +#define FBIOGET_CON2FBMAP 0x460F +#define FBIOPUT_CON2FBMAP 0x4610 +#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ +#define FBIOGET_VBLANK 0x4612 +#define FBIO_ALLOC 0x4613 +#define FBIO_FREE 0x4614 +#define FBIOGET_GLYPH 0x4615 +#define FBIOGET_HWCINFO 0x4616 +#define FBIOPUT_MODEINFO 0x4617 +#define FBIOGET_DISPINFO 0x4618 +#define FBIO_WAITFORVSYNC 0x4620 + +struct fb_bitfield +{ + uint32_t offset; /* beginning of bitfield */ + uint32_t length; /* length of bitfield */ + uint32_t msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +struct fb_var_screeninfo +{ + uint32_t xres; + uint32_t yres; + + uint32_t bits_per_pixel; + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ +}; + +struct fb_fix_screeninfo +{ + char id[16]; + unsigned long smem_start; + uint32_t smem_len; + + uint32_t line_length; +}; + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device.h b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device.h new file mode 100644 index 0000000000000000000000000000000000000000..99e8a879f86bfd358256b516f140b19a7656b9a0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device.h @@ -0,0 +1,644 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_USB_DEVICE_H__ +#define __FSL_USB_DEVICE_H__ + +/*! + * @addtogroup usb_device_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines Get/Set status Types */ +typedef enum _usb_device_status +{ + kUSB_DeviceStatusTestMode = 1U, /*!< Test mode */ + kUSB_DeviceStatusSpeed, /*!< Current speed */ + kUSB_DeviceStatusOtg, /*!< OTG status */ + kUSB_DeviceStatusDevice, /*!< Device status */ + kUSB_DeviceStatusEndpoint, /*!< Endpoint state usb_device_endpoint_status_t */ + kUSB_DeviceStatusDeviceState, /*!< Device state */ + kUSB_DeviceStatusAddress, /*!< Device address */ + kUSB_DeviceStatusSynchFrame, /*!< Current frame */ + kUSB_DeviceStatusBus, /*!< Bus status */ + kUSB_DeviceStatusBusSuspend, /*!< Bus suspend */ + kUSB_DeviceStatusBusSleep, /*!< Bus suspend */ + kUSB_DeviceStatusBusResume, /*!< Bus resume */ + kUSB_DeviceStatusRemoteWakeup, /*!< Remote wakeup state */ + kUSB_DeviceStatusBusSleepResume, /*!< Bus resume */ +} usb_device_status_t; + +/*! @brief Defines USB 2.0 device state */ +typedef enum _usb_device_state +{ + kUSB_DeviceStateConfigured = 0U, /*!< Device state, Configured*/ + kUSB_DeviceStateAddress, /*!< Device state, Address*/ + kUSB_DeviceStateDefault, /*!< Device state, Default*/ + kUSB_DeviceStateAddressing, /*!< Device state, Address setting*/ + kUSB_DeviceStateTestMode, /*!< Device state, Test mode*/ +} usb_device_state_t; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +typedef enum _usb_dcd_detection_sequence_status +{ + kUSB_DcdDetectionNotEnabled = 0x0U, + kUSB_DcdDataPinDetectionCompleted = 0x01U, + kUSB_DcdChargingPortDetectionCompleted = 0x02U, + kUSB_DcdChargerTypeDetectionCompleted = 0x03U, +} usb_dcd_detection_sequence_status_t; + +typedef enum _usb_dcd_detection_sequence_results +{ + kUSB_DcdDetectionNoResults = 0x0U, + kUSB_DcdDetectionStandardHost = 0x01U, + kUSB_DcdDetectionChargingPort = 0x02U, + kUSB_DcdDetectionDedicatedCharger = 0x03U, +} usb_dcd_detection_sequence_results_t; +#endif + +/*! @brief Defines endpoint state */ +typedef enum _usb_endpoint_status +{ + kUSB_DeviceEndpointStateIdle = 0U, /*!< Endpoint state, idle*/ + kUSB_DeviceEndpointStateStalled, /*!< Endpoint state, stalled*/ +} usb_device_endpoint_status_t; + +/*! @brief Control endpoint index */ +#define USB_CONTROL_ENDPOINT (0U) +/*! @brief Control endpoint maxPacketSize */ +#define USB_CONTROL_MAX_PACKET_SIZE (64U) + +#if (USB_DEVICE_CONFIG_EHCI && (USB_CONTROL_MAX_PACKET_SIZE != (64U))) +#error For high speed, USB_CONTROL_MAX_PACKET_SIZE must be 64!!! +#endif + +/*! @brief The setup packet size of USB control transfer. */ +#define USB_SETUP_PACKET_SIZE (8U) +/*! @brief USB endpoint mask */ +#define USB_ENDPOINT_NUMBER_MASK (0x0FU) + +/*! @brief Default invalid value or the endpoint callback length of cancelled transfer */ +#define USB_UNINITIALIZED_VAL_32 (0xFFFFFFFFU) + +/*! @brief Available common EVENT types in device callback */ +typedef enum _usb_device_event +{ + kUSB_DeviceEventBusReset = 1U, /*!< USB bus reset signal detected */ + kUSB_DeviceEventSuspend, /*!< USB bus suspend signal detected */ + kUSB_DeviceEventResume, /*!< USB bus resume signal detected. The resume signal is driven by itself or a host */ + kUSB_DeviceEventSleeped, /*!< USB bus LPM suspend signal detected */ + kUSB_DeviceEventLPMResume, /*!< USB bus LPM resume signal detected. The resume signal is driven by itself or a host + */ + kUSB_DeviceEventError, /*!< An error is happened in the bus. */ + kUSB_DeviceEventDetach, /*!< USB device is disconnected from a host. */ + kUSB_DeviceEventAttach, /*!< USB device is connected to a host. */ + kUSB_DeviceEventSetConfiguration, /*!< Set configuration. */ + kUSB_DeviceEventSetInterface, /*!< Set interface. */ + + kUSB_DeviceEventGetDeviceDescriptor, /*!< Get device descriptor. */ + kUSB_DeviceEventGetConfigurationDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetStringDescriptor, /*!< Get string descriptor. */ + kUSB_DeviceEventGetHidDescriptor, /*!< Get HID descriptor. */ + kUSB_DeviceEventGetHidReportDescriptor, /*!< Get HID report descriptor. */ + kUSB_DeviceEventGetHidPhysicalDescriptor, /*!< Get HID physical descriptor. */ + kUSB_DeviceEventGetBOSDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetDeviceQualifierDescriptor, /*!< Get device qualifier descriptor. */ + kUSB_DeviceEventVendorRequest, /*!< Vendor request. */ + kUSB_DeviceEventSetRemoteWakeup, /*!< Enable or disable remote wakeup function. */ + kUSB_DeviceEventGetConfiguration, /*!< Get current configuration index */ + kUSB_DeviceEventGetInterface, /*!< Get current interface alternate setting value */ + kUSB_DeviceEventSetBHNPEnable, +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) + kUSB_DeviceEventDcdTimeOut, /*!< Dcd detect result is timeout */ + kUSB_DeviceEventDcdUnknownType, /*!< Dcd detect result is unknown type */ + kUSB_DeviceEventSDPDetected, /*!< The SDP facility is detected */ + kUSB_DeviceEventChargingPortDetected, /*!< The charging port is detected */ + kUSB_DeviceEventChargingHostDetected, /*!< The CDP facility is detected */ + kUSB_DeviceEventDedicatedChargerDetected, /*!< The DCP facility is detected */ +#endif +} usb_device_event_t; + +/*! @brief Endpoint callback message structure */ +typedef struct _usb_device_endpoint_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_endpoint_callback_message_struct_t; + +/*! + * @brief Endpoint callback function typedef. + * + * This callback function is used to notify the upper layer what the transfer result is. + * This callback pointer is passed when a specified endpoint is initialized by calling API #USB_DeviceInitEndpoint. + * + * @param handle The device handle. It equals to the value returned from #USB_DeviceInit. + * @param message The result of a transfer, which includes transfer buffer, transfer length, and whether is in a + * setup phase. + * phase for control pipe. + * @param callbackParam The parameter for this callback. It is same with + * usb_device_endpoint_callback_struct_t::callbackParam. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_endpoint_callback_t)(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam); + +/*! + * @brief Device callback function typedef. + * + * This callback function is used to notify the upper layer that the device status has changed. + * This callback pointer is passed by calling API #USB_DeviceInit. + * + * @param handle The device handle. It equals the value returned from #USB_DeviceInit. + * @param callbackEvent The callback event type. See enumeration #usb_device_event_t. + * @param eventParam The event parameter for this callback. The parameter type is determined by the callback event. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_callback_t)(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); + +/*! @brief Endpoint callback structure */ +typedef struct _usb_device_endpoint_callback_struct +{ + usb_device_endpoint_callback_t callbackFn; /*!< Endpoint callback function*/ + void *callbackParam; /*!< Parameter for callback function*/ + uint8_t isBusy; +} usb_device_endpoint_callback_struct_t; + +/*! @brief Endpoint initialization structure */ +typedef struct _usb_device_endpoint_init_struct +{ + uint16_t maxPacketSize; /*!< Endpoint maximum packet size */ + uint8_t endpointAddress; /*!< Endpoint address*/ + uint8_t transferType; /*!< Endpoint transfer type*/ + uint8_t zlt; /*!< ZLT flag*/ +} usb_device_endpoint_init_struct_t; + +/*! @brief Endpoint status structure */ +typedef struct _usb_device_endpoint_status_struct +{ + uint8_t endpointAddress; /*!< Endpoint address */ + uint16_t endpointStatus; /*!< Endpoint status : idle or stalled */ +} usb_device_endpoint_status_struct_t; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! @brief USB DCD charge timing specification structure */ +typedef struct _usb_device_dcd_charging_time +{ + uint16_t dcdSeqInitTime; /*!< The dcd sequence init time */ + uint16_t dcdDbncTime; /*!< The debounce time period on DP signal */ + uint16_t dcdDpSrcOnTime; /*!< The time period comparator enabled */ + uint16_t dcdTimeWaitAfterPrD; /*!< The time period between primary and secondary detection */ + uint8_t dcdTimeDMSrcOn; /*!< The amount of time that the modules enable the Vdm_src */ +} usb_device_dcd_charging_time_t; +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name USB device APIs + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes the USB device stack. + * + * This function initializes the USB device module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t. + * @param[in] deviceCallback Function pointer of the device callback. + * @param[out] handle It is an out parameter used to return the pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success The device is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. + * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invalid. There is an empty + * interface entity. + * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than the IP's endpoint number. + * Or, the device has been initialized. + * Or, the mutex or message queue is created failed. + */ +extern usb_status_t USB_DeviceInit(uint8_t controllerId, + usb_device_callback_t deviceCallback, + usb_device_handle *handle); + +/*! + * @brief Enables the device functionality. + * + * The function enables the device functionality, so that the device can be recognized by the host when the device + * detects that it has been connected to a host. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceRun(usb_device_handle handle); + +/*! + * @brief Disables the device functionality. + * + * The function disables the device functionality. After this function called, even if the device is detached to the + * host, + * it can't work. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceStop(usb_device_handle handle); + +/*! + * @brief De-initializes the device controller. + * + * The function de-initializes the device controller specified by the handle. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceDeinit(usb_device_handle handle); + +/*! + * @brief Sends data through a specified endpoint. + * + * The function is used to send data through a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. The function is not reentrant. + * @param[in] length The data length need to be sent. + * + * @retval kStatus_USB_Success The send request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the sending request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceSendRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receives data through a specified endpoint. + * + * The function is used to receive data through a specified endpoint. The function is not reentrant. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length want to be received. + * + * @retval kStatus_USB_Success The receive request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the receiving request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The transfer is cancelled. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Initializes a specified endpoint. + * + * The function is used to initialize a specified endpoint. The corresponding endpoint callback is also initialized. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] epInit Endpoint initialization structure. See the structure usb_device_endpoint_init_struct_t. + * @param[in] epCallback Endpoint callback structure. See the structure + * usb_device_endpoint_callback_struct_t. + * + * @retval kStatus_USB_Success The endpoint is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is + * more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, + usb_device_endpoint_init_struct_t *epInit, + usb_device_endpoint_callback_struct_t *epCallback); + +/*! + * @brief Deinitializes a specified endpoint. + * + * The function is used to deinitializes a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is de-initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Stalls a specified endpoint. + * + * The function is used to stall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Unstalls a specified endpoint. + * + * The function is used to unstall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is unstalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Gets the status of the selected item. + * + * The function is used to get the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[out] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Get status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The parameter is NULL pointer. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type. + */ +extern usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +/*! + * @brief Sets the status of the selected item. + * + * The function is used to set the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[in] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Set status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type or the parameter is NULL pointer. + */ +extern usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! + * @brief Initializes the device dcd module. + * + * The function initializes the device dcd module. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] time_param The time parameter used to config the dcd timing registers. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param); + +/*! + * @brief De-initializes the device dcd module. + * + * The function de-initializes the device dcd module specified by the handle. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle); +#endif +/*! + * @brief Device task function. + * + * The function is used to handle the controller message. + * This function should not be called in the application directly. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceTaskFunction(void *deviceHandle); + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/*! + * @brief Device KHCI task function. + * + * The function is used to handle the KHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceKhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! + * @brief Device EHCI task function. + * + * The function is used to handle the EHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceEhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! + * @brief Device EHCI DCD ISR function. + * + * The function is the EHCI DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDcdHSIsrFunction(void *deviceHandle); +#endif +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/*! + * @brief Device LPC ip3511 controller task function. + * + * The function is used to handle the LPC ip3511 controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceLpcIp3511TaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/*! + * @brief Device KHCI ISR function. + * + * The function is the KHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceKhciIsrFunction(void *deviceHandle); +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! + * @brief Device KHCI DCD ISR function. + * + * The function is the KHCI DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDcdIsrFunction(void *deviceHandle); +#endif +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! + * @brief Device EHCI ISR function. + * + * The function is the EHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceEhciIsrFunction(void *deviceHandle); +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/*! + * @brief Device LPC USB ISR function. + * + * The function is the LPC USB interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle); +#endif + +/*! + * @brief Gets the device stack version function. + * + * The function is used to get the device stack version. + * + * @param[out] version The version structure pointer to keep the device stack version. + * + */ +extern void USB_DeviceGetVersion(uint32_t *version); + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] tick Current hardware tick(uint is ms). + * + */ +extern usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick); +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* __USB_DEVICE_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_dci.c b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_dci.c new file mode 100644 index 0000000000000000000000000000000000000000..12cc432bec321be1562f47e0dbef8d9cba31ecb0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_dci.c @@ -0,0 +1,1467 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "usb_device.h" +#include "usb_device_dci.h" + +#include "fsl_device_registers.h" + +#if ((defined(USB_DEVICE_CONFIG_NUM)) && (USB_DEVICE_CONFIG_NUM > 0U)) + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +#include "usb_device_khci.h" +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +#include "usb_device_ehci.h" +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#include "usb_device_lpcip3511.h" +#endif + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) +#include "fsl_cache.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle); +static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle); +static usb_status_t USB_DeviceGetControllerInterface( + uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface); +static usb_status_t USB_DeviceTransfer(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); +static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param); +static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) +static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); + +#endif +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) +static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +#endif +static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +USB_GLOBAL static usb_device_struct_t s_UsbDevice[USB_DEVICE_CONFIG_NUM]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Allocate a device handle. + * + * This function allocates a device handle. + * + * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param handle It is out parameter, is used to return pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_Error The device has been initialized. + */ +static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle) +{ + uint32_t count; + int i = 0; + for(i=0;icontrollerHandle = NULL; + handle->controllerId = 0U; + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/* KHCI device driver interface */ +static const usb_device_controller_interface_struct_t s_UsbDeviceKhciInterface = { + USB_DeviceKhciInit, USB_DeviceKhciDeinit, USB_DeviceKhciSend, + USB_DeviceKhciRecv, USB_DeviceKhciCancel, USB_DeviceKhciControl +}; +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/* EHCI device driver interface */ +static const usb_device_controller_interface_struct_t s_UsbDeviceEhciInterface = { + USB_DeviceEhciInit, USB_DeviceEhciDeinit, USB_DeviceEhciSend, + USB_DeviceEhciRecv, USB_DeviceEhciCancel, USB_DeviceEhciControl +}; +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/* EHCI device driver interface */ +static const usb_device_controller_interface_struct_t s_UsbDeviceLpc3511IpInterface = { + USB_DeviceLpc3511IpInit, USB_DeviceLpc3511IpDeinit, USB_DeviceLpc3511IpSend, + USB_DeviceLpc3511IpRecv, USB_DeviceLpc3511IpCancel, USB_DeviceLpc3511IpControl +}; +#endif + +/*! + * @brief Get the controller interface handle. + * + * This function is used to get the controller interface handle. + * + * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param controllerInterface It is out parameter, is used to return pointer of the device controller handle to the + * caller. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_ControllerNotFound The controller id is invalided. + */ +static usb_status_t USB_DeviceGetControllerInterface( + uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface) +{ + usb_status_t error = kStatus_USB_ControllerNotFound; + switch (controllerId) + { +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) + /* Get the KHCI controller driver interface */ + case kUSB_ControllerKhci0: + case kUSB_ControllerKhci1: + *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceKhciInterface; + error = kStatus_USB_Success; + break; +#endif +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) + /* Get the EHCI controller driver interface */ + case kUSB_ControllerEhci0: + case kUSB_ControllerEhci1: + error = kStatus_USB_Success; + *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceEhciInterface; + break; +#endif +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) + /* Get the EHCI controller driver interface */ + case kUSB_ControllerLpcIp3511Fs0: + case kUSB_ControllerLpcIp3511Fs1: + case kUSB_ControllerLpcIp3511Hs0: + case kUSB_ControllerLpcIp3511Hs1: + error = kStatus_USB_Success; + *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceLpc3511IpInterface; + break; +#endif + default: + break; + } + return error; +} + +/*! + * @brief Start a new transfer. + * + * This function is used to start a new transfer. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param endpointAddress Endpoint address. Bit7 is direction, 0U - USB_OUT, 1U - USB_IN. + * @param buffer The memory address to be transferred, or the memory address to hold the data need to be + * sent. + * @param length The length of the data. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_InvalidHandle The device handle is invalided. + * @retval kStatus_USB_ControllerNotFound The controller interface is not found. + * @retval kStatus_USB_Error The device is doing reset. + */ +static usb_status_t USB_DeviceTransfer(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_status_t error = kStatus_USB_Error; + uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + USB_OSA_SR_ALLOC(); + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if (NULL != deviceHandle->controllerInterface) + { + if (deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy) + { + return kStatus_USB_Busy; + } + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 1U; + USB_OSA_EXIT_CRITICAL(); + if (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) + { +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + if (length) + { + DCACHE_CleanByRange((uint32_t)buffer, length); + } +#endif + /* Call the controller send interface. */ + error = deviceHandle->controllerInterface->deviceSend(deviceHandle->controllerHandle, endpointAddress, + buffer, length); + } + else + { +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + if (length) + { + DCACHE_CleanInvalidateByRange((uint32_t)buffer, length); + } +#endif + /* Call the controller receive interface. */ + error = deviceHandle->controllerInterface->deviceRecv(deviceHandle->controllerHandle, endpointAddress, + buffer, length); + } + if (kStatus_USB_Success != error) + { + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + USB_OSA_EXIT_CRITICAL(); + } + } + else + { + error = kStatus_USB_ControllerNotFound; + } + return error; +} + +/*! + * @brief Control the status of the selected item. + * + * This function is used to control the status of the selected item.. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param type The control type, please refer to the enumeration usb_device_control_type_t. + * @param param The param type is determined by the selected item. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_InvalidHandle The device handle is invalided. + * @retval kStatus_USB_ControllerNotFound The controller interface is not found. + * @retval kStatus_USB_Error Unsupport type. + * Or, the param is NULL pointer. + */ +static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_status_t error = kStatus_USB_Error; + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if (NULL != deviceHandle->controllerInterface) + { + /* Call the controller control interface. */ + error = deviceHandle->controllerInterface->deviceControl(deviceHandle->controllerHandle, type, param); + } + else + { + error = kStatus_USB_ControllerNotFound; + } + return error; +} + +/*! + * @brief Handle the reset notification. + * + * This function is used to handle the reset notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @retval kStatus_USB_Success Get a device handle successfully. + */ +static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_SR_ALLOC(); +#endif + + handle->isResetting = 1U; + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + /* Clear remote wakeup feature */ + handle->remotewakeup = 0U; +#endif + +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + handle->epCallbackDirectly = 1; + USB_OSA_EXIT_CRITICAL(); +#endif + /* Set the controller to default status. */ + USB_DeviceControl(handle, kUSB_DeviceControlSetDefaultStatus, NULL); +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + handle->epCallbackDirectly = 0; + USB_OSA_EXIT_CRITICAL(); +#endif + + handle->state = kUSB_DeviceStateDefault; + handle->deviceAddress = 0U; + + for (uint32_t count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++) + { + handle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL; + handle->epCallback[count].callbackParam = NULL; + handle->epCallback[count].isBusy = 0U; + } + + /* Call device callback to notify the application that the USB bus reset signal detected. */ + handle->deviceCallback(handle, kUSB_DeviceEventBusReset, NULL); + + handle->isResetting = 0U; + return kStatus_USB_Success; +} + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief Handle the suspend notification. + * + * This function is used to handle the suspend notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus suspend signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventSuspend, NULL); +} + +/*! + * @brief Handle the resume notification. + * + * This function is used to handle the resume notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus resume signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventResume, NULL); +} +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) +/*! + * @brief Handle the suspend notification. + * + * This function is used to handle the suspend notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus suspend signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventSleeped, NULL); +} +#endif +/*! + * @brief Handle the remotewakeup notification. + * + * This function is used to handle the remotewakeup notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param flag The buffer pointer to store remotewakeup flag. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetRemoteWakeUp(usb_device_struct_t *handle, uint8_t **flag) +{ + /* Call device callback to notify the application that the USB bus suspend signal detected. */ + return USB_DeviceControl(handle, kUSB_DeviceControlGetRemoteWakeUp, flag); +} + +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + +#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)) +usb_status_t USB_DeviceErrorNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus error signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventError, NULL); +} +#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */ + +#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) +/*! + * @brief Handle the detach notification. + * + * This function is used to handle the detach notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device is disconnected from a host. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDetach, NULL); +} + +/*! + * @brief Handle the attach notification. + * + * This function is used to handle the attach notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device is connected to a host. */ + return handle->deviceCallback(handle, kUSB_DeviceEventAttach, NULL); +} +#endif + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) +/*! + * @brief Handle the dcd module timeout notification. + * + * This function is used to handle the dcd module timeout notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdTimeOutNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device charger detect timeout happened. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDcdTimeOut, NULL); +} + +/*! + * @brief Handle the dcd module unknown port type notification. + * + * This function is used to handle the dcd module unknown port type notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdUnknownPortTypeNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device charger detect unknown port type happened. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDcdUnknownType, NULL); +} + +/*! + * @brief Handle the SDP facility is detected notification. + * + * This function is used to handle the SDP facility is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdSDPDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the SDP facility is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventSDPDetected, NULL); +} + +/*! + * @brief Handle the charging port is detected notification. + * + * This function is used to handle the charging port is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdChargingPortDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the charing port is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventChargingPortDetected, NULL); +} + +/*! + * @brief Handle the CDP facility is detected notification. + * + * This function is used to handle the CDP facility is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdChargingHostDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the CDP facility is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventChargingHostDetected, NULL); +} + +/*! + * @brief Handle the DCP facility is detected notification. + * + * This function is used to handle the DCP facility is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ + +static usb_status_t USB_DeviceDcdDedicatedChargerDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the DCP facility is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDedicatedChargerDetected, NULL); +} +#endif + +/*! + * @brief Handle the attach notification. + * + * This function is used to handle the attach notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message) +{ + uint8_t endpoint = message->code & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = (message->code & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + usb_status_t error = kStatus_USB_Error; + + switch (message->code) + { + case kUSB_DeviceNotifyBusReset: + error = USB_DeviceResetNotification(handle, message); + break; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + case kUSB_DeviceNotifySuspend: + error = USB_DeviceSuspendNotification(handle, message); + break; + case kUSB_DeviceNotifyResume: + error = USB_DeviceResumeNotification(handle, message); + break; +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) + case kUSB_DeviceNotifyLPMSleep: + error = USB_DeviceSleepNotification(handle, message); + break; +#endif +#endif + +#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)) + case kUSB_DeviceNotifyError: + error = USB_DeviceErrorNotification(handle, message); + break; +#endif + +#if USB_DEVICE_CONFIG_DETACH_ENABLE + case kUSB_DeviceNotifyDetach: + error = USB_DeviceDetachNotification(handle, message); + break; + case kUSB_DeviceNotifyAttach: + error = USB_DeviceAttachNotification(handle, message); + break; +#endif +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) + case kUSB_DeviceNotifyDcdTimeOut: + error = USB_DeviceDcdTimeOutNotification(handle, message); + break; + case kUSB_DeviceNotifyDcdUnknownPortType: + error = USB_DeviceDcdUnknownPortTypeNotification(handle, message); + break; + case kUSB_DeviceNotifySDPDetected: + error = USB_DeviceDcdSDPDetectNotification(handle, message); + break; + case kUSB_DeviceNotifyChargingPortDetected: + error = USB_DeviceDcdChargingPortDetectNotification(handle, message); + break; + case kUSB_DeviceNotifyChargingHostDetected: + error = USB_DeviceDcdChargingHostDetectNotification(handle, message); + break; + case kUSB_DeviceNotifyDedicatedChargerDetected: + error = USB_DeviceDcdDedicatedChargerDetectNotification(handle, message); + break; +#endif + + default: + if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) + { + if (handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn) + { + usb_device_endpoint_callback_message_struct_t endpointCallbackMessage; + endpointCallbackMessage.buffer = message->buffer; + endpointCallbackMessage.length = message->length; + endpointCallbackMessage.isSetup = message->isSetup; + if (message->isSetup) + { + handle->epCallback[0].isBusy = 0U; + handle->epCallback[1].isBusy = 0U; + } + else + { + handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + } + /* Call endpoint callback */ + error = handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn( + handle, &endpointCallbackMessage, + handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam); + } + } + break; + } + return error; +} + +/*! + * @brief Notify the device that the controller status changed. + * + * This function is used to notify the device that the controller status changed. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_device_callback_message_struct_t *message = (usb_device_callback_message_struct_t *)msg; + + if ((NULL == msg) || (NULL == handle)) + { + return kStatus_USB_InvalidHandle; + } + + /* The device callback is invalid or not. */ + if (!deviceHandle->deviceCallback) + { + return kStatus_USB_Error; + } + +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + if (deviceHandle->epCallbackDirectly) + { + if ((message->code & USB_ENDPOINT_NUMBER_MASK) && (!(message->code & 0x70U))) + { + return USB_DeviceNotification(deviceHandle, message); + } + } + + /* Add the message to message queue when the device task is enabled. */ + if (kStatus_USB_OSA_Success != USB_OsaMsgqSend(deviceHandle->notificationQueue, (void *)message)) + { + return kStatus_USB_Busy; + } + return kStatus_USB_Success; +#else + /* Handle the notification by calling USB_DeviceNotification. */ + return USB_DeviceNotification(deviceHandle, message); +#endif +} + +/*! + * @brief Initialize the USB device stack. + * + * This function initializes the USB device module specified by the controllerId. + * + * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param deviceCallback Function pointer of the device callback. + * @param handle It is out parameter, is used to return pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success The device is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. + * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invaild, There is an empty + * interface entity. + * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than IP's endpoint number. + * Or, the device has been initialized. + * Or, the message queue is created failed. + */ +usb_status_t USB_DeviceInit(uint8_t controllerId, usb_device_callback_t deviceCallback, usb_device_handle *handle) +{ + usb_device_struct_t *deviceHandle = NULL; + usb_status_t error; + uint32_t count; + + if (NULL == handle) + { + return kStatus_USB_InvalidHandle; + } + + /* Allocate a device handle by using the controller id. */ + error = USB_DeviceAllocateHandle(controllerId, &deviceHandle); + + if (kStatus_USB_Success != error) + { + return error; + } + + /* Save the device callback */ + deviceHandle->deviceCallback = deviceCallback; + /* Save the controller id */ + deviceHandle->controllerId = controllerId; + /* Clear the device address */ + deviceHandle->deviceAddress = 0U; + /* Clear the device reset state */ + deviceHandle->isResetting = 0U; + + /* Initialize the enpoints */ + for (count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++) + { + deviceHandle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL; + deviceHandle->epCallback[count].callbackParam = NULL; + deviceHandle->epCallback[count].isBusy = 0U; + } + + /* Get the controller interface according to the controller id */ + error = USB_DeviceGetControllerInterface(controllerId, &deviceHandle->controllerInterface); + if (kStatus_USB_Success != error) + { + USB_DeviceFreeHandle(deviceHandle); + return error; + } + if (NULL == deviceHandle->controllerInterface) + { + USB_DeviceFreeHandle(deviceHandle); + return kStatus_USB_ControllerNotFound; + } + if (((usb_device_controller_init_t)NULL == deviceHandle->controllerInterface->deviceInit) || + ((usb_device_controller_deinit_t)NULL == deviceHandle->controllerInterface->deviceDeinit) || + ((usb_device_controller_send_t)NULL == deviceHandle->controllerInterface->deviceSend) || + ((usb_device_controller_recv_t)NULL == deviceHandle->controllerInterface->deviceRecv) || + ((usb_device_controller_cancel_t)NULL == deviceHandle->controllerInterface->deviceCancel) || + ((usb_device_controller_control_t)NULL == deviceHandle->controllerInterface->deviceControl)) + { + USB_DeviceFreeHandle(deviceHandle); + return kStatus_USB_InvalidControllerInterface; + } + +#if USB_DEVICE_CONFIG_USE_TASK + /* Create a message queue when the device handle is enabled. */ + if (kStatus_USB_OSA_Success != + USB_OsaMsgqCreate(&deviceHandle->notificationQueue, USB_DEVICE_CONFIG_MAX_MESSAGES, + (1U + (sizeof(usb_device_callback_message_struct_t) - 1U) / sizeof(uint32_t)))) + { + USB_DeviceDeinit(deviceHandle); + return kStatus_USB_Error; + } +#endif + + *handle = deviceHandle; + + /* Initialize the controller */ + error = deviceHandle->controllerInterface->deviceInit(controllerId, deviceHandle, &deviceHandle->controllerHandle); + if (kStatus_USB_Success != error) + { + USB_DeviceDeinit(deviceHandle); + *handle = NULL; + return error; + } + /* Set the device to deafult state */ + deviceHandle->state = kUSB_DeviceStateDefault; + + return error; +} + +/*! + * @brief Enable the device functionality. + * + * The function enables the device functionality, so that the device can be recognized by the host when the device + * detects that it has been connected to a host. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +usb_status_t USB_DeviceRun(usb_device_handle handle) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlRun, NULL); +} +/*! + * @brief Disable the device functionality. + * + * The function disables the device functionality, after this function called, even the device is detached to the host, + * and the device can't work. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + */ +usb_status_t USB_DeviceStop(usb_device_handle handle) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlStop, NULL); +} +/*! + * @brief De-initialize the device controller. + * + * The function de-initializes the device controller specified by the handle. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + */ +usb_status_t USB_DeviceDeinit(usb_device_handle handle) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + /* De-initialize the controller */ + if (NULL != deviceHandle->controllerInterface) + { + deviceHandle->controllerInterface->deviceDeinit(deviceHandle->controllerHandle); + deviceHandle->controllerInterface = (usb_device_controller_interface_struct_t *)NULL; + } + +#if USB_DEVICE_CONFIG_USE_TASK + /* Destroy the message queue. */ + if (NULL != deviceHandle->notificationQueue) + { + USB_OsaMsgqDestroy(deviceHandle->notificationQueue); + deviceHandle->notificationQueue = NULL; + } +#endif + + /* Free the device handle. */ + USB_DeviceFreeHandle(deviceHandle); + return kStatus_USB_Success; +} + +/*! + * @brief Send data through a specified endpoint. + * + * The function is used to send data through a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to hold the data need to be sent. + * @param length The data length need to be sent. + * + * @retval kStatus_USB_Success The send request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value just means if the sending request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceSendRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length) +{ + return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | + (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Receive data through a specified endpoint. + * + * The function is used to receive data through a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to save the received data. + * @param length The data length want to be received. + * + * @retval kStatus_USB_Success The receive request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length) +{ + return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | + (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Cancel the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The transfer is cancelled. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_status_t error = kStatus_USB_Error; + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if (NULL != deviceHandle->controllerInterface) + { + error = deviceHandle->controllerInterface->deviceCancel(deviceHandle->controllerHandle, endpointAddress); + } + else + { + error = kStatus_USB_ControllerNotFound; + } + return error; +} + +/*! + * @brief Initialize a specified endpoint. + * + * The function is used to initialize a specified endpoint and the corresponding endpoint callback is also initialized. + * + * @param handle The device handle got from USB_DeviceInit. + * @param epInit Endpoint initizlization structure. Please refer to the structure usb_device_endpoint_init_struct_t. + * @param epCallback Endpoint callback structure. Please refer to the structure + * usb_device_endpoint_callback_struct_t. + * + * @retval kStatus_USB_Success The endpoint is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is + * more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, + usb_device_endpoint_init_struct_t *epInit, + usb_device_endpoint_callback_struct_t *epCallback) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + uint8_t endpoint; + uint8_t direction; + + if (!deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if ((!epInit) || (!epCallback)) + { + return kStatus_USB_InvalidParameter; + } + + endpoint = epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK; + direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) + { + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = epCallback->callbackFn; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = + epCallback->callbackParam; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + } + else + { + return kStatus_USB_InvalidParameter; + } + return USB_DeviceControl(handle, kUSB_DeviceControlEndpointInit, epInit); +} + +/*! + * @brief De-initizlize a specified endpoint. + * + * The function is used to de-initizlize a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is de-initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + usb_status_t error = kStatus_USB_Error; +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_SR_ALLOC(); +#endif + + if (!deviceHandle) + { + return kStatus_USB_InvalidHandle; + } +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallbackDirectly = 1; + USB_OSA_EXIT_CRITICAL(); +#endif + error = USB_DeviceControl(handle, kUSB_DeviceControlEndpointDeinit, &endpointAddress); +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallbackDirectly = 0; + USB_OSA_EXIT_CRITICAL(); +#endif + + if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) + { + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = + (usb_device_endpoint_callback_t)NULL; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = NULL; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + } + else + { + return kStatus_USB_InvalidParameter; + } + return error; +} + +/*! + * @brief Stall a specified endpoint. + * + * The function is used to stall a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress) +{ + if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS) + { + return USB_DeviceControl(handle, kUSB_DeviceControlEndpointStall, &endpointAddress); + } + else + { + return kStatus_USB_InvalidParameter; + } +} + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is un-stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress) +{ + if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS) + { + return USB_DeviceControl(handle, kUSB_DeviceControlEndpointUnstall, &endpointAddress); + } + else + { + return kStatus_USB_InvalidParameter; + } +} + +/*! + * @brief Get the status of the selected item. + * + * The function is used to get the status of the selected item. + * + * @param handle The device handle got from USB_DeviceInit. + * @param type The selected item. Please refer to the structure usb_device_status_t. + * @param param The param type is determined by the selected item. + * + * @retval kStatus_USB_Success Get status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The param is NULL pointer. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type. + */ +usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param) +{ + uint8_t *temp8; + usb_status_t error = kStatus_USB_Error; + + if (NULL == param) + { + return kStatus_USB_InvalidParameter; + } + switch (type) + { + case kUSB_DeviceStatusSpeed: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetSpeed, param); + break; + case kUSB_DeviceStatusOtg: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetOtgStatus, param); + break; + case kUSB_DeviceStatusDeviceState: + temp8 = (uint8_t *)param; + error = kStatus_USB_Success; + *temp8 = ((usb_device_struct_t *)handle)->state; + break; + case kUSB_DeviceStatusAddress: + temp8 = (uint8_t *)param; + error = kStatus_USB_Success; + *temp8 = ((usb_device_struct_t *)handle)->deviceAddress; + break; + case kUSB_DeviceStatusDevice: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetDeviceStatus, param); + break; + case kUSB_DeviceStatusEndpoint: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetEndpointStatus, param); + break; + case kUSB_DeviceStatusSynchFrame: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetSynchFrame, param); + break; +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + case kUSB_DeviceStatusRemoteWakeup: + temp8 = (uint8_t *)param; + error = kStatus_USB_Success; + *temp8 = ((usb_device_struct_t *)handle)->remotewakeup; + break; +#endif + default: + break; + } + return error; +} + +/*! + * @brief Set the status of the selected item. + * + * The function is used to set the status of the selected item. + * + * @param handle The device handle got from USB_DeviceInit. + * @param type The selected item. Please refer to the structure usb_device_status_t. + * @param param The param type is determined by the selected item. + * + * @retval kStatus_USB_Success Set status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type, or the param is NULL pointer. + */ +usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param) +{ + usb_status_t error = kStatus_USB_Error; + switch (type) + { +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) || \ + (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) && \ + (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) + case kUSB_DeviceStatusTestMode: + error = USB_DeviceControl(handle, kUSB_DeviceControlSetTestMode, param); + break; +#endif + case kUSB_DeviceStatusOtg: + error = USB_DeviceControl(handle, kUSB_DeviceControlSetOtgStatus, param); + break; + case kUSB_DeviceStatusDeviceState: + if (NULL != param) + { + error = kStatus_USB_Success; + ((usb_device_struct_t *)handle)->state = (uint8_t)(*(uint8_t *)param); + } + break; + case kUSB_DeviceStatusAddress: + if (kUSB_DeviceStateAddressing != ((usb_device_struct_t *)handle)->state) + { + if (NULL != param) + { + error = kStatus_USB_Success; + ((usb_device_struct_t *)handle)->deviceAddress = (uint8_t)(*(uint8_t *)param); + ((usb_device_struct_t *)handle)->state = kUSB_DeviceStateAddressing; + } + } + else + { + error = USB_DeviceControl(handle, kUSB_DeviceControlSetDeviceAddress, + &((usb_device_struct_t *)handle)->deviceAddress); + } + break; + case kUSB_DeviceStatusBusResume: + error = USB_DeviceControl(handle, kUSB_DeviceControlResume, param); + break; + case kUSB_DeviceStatusBusSleepResume: + error = USB_DeviceControl(handle, kUSB_DeviceControlSleepResume, param); + break; +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + case kUSB_DeviceStatusRemoteWakeup: + if (NULL != param) + { + error = kStatus_USB_Success; + ((usb_device_struct_t *)handle)->remotewakeup = (uint8_t)(*(uint8_t *)param); + } + break; +#endif + case kUSB_DeviceStatusBusSuspend: + error = USB_DeviceControl(handle, kUSB_DeviceControlSuspend, param); + break; + case kUSB_DeviceStatusBusSleep: + error = USB_DeviceControl(handle, kUSB_DeviceControlSleep, param); + break; + default: + break; + } + return error; +} + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) +/*! + * @brief Initializes the device dcd module. + * + * The function initializes the device dcd module. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlDcdInitModule, time_param); +} + +/*! + * @brief De-initializes the device dcd module. + * + * The function de-intializes the device dcd module. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlDcdDeinitModule, NULL); +} +#endif + +#if USB_DEVICE_CONFIG_USE_TASK +/*! + * @brief Device task function. + * + * The function is used to handle controller message. + * This function should not be called in applicartion directly. + * + * @param handle The device handle got from USB_DeviceInit. + */ +void USB_DeviceTaskFunction(void *deviceHandle) +{ + usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; + static usb_device_callback_message_struct_t message; + + if (deviceHandle) + { + /* Get the message from the queue */ + if (kStatus_USB_OSA_Success == USB_OsaMsgqRecv(handle->notificationQueue, (uint32_t *)&message, 0U)) + { + /* Handle the message */ + USB_DeviceNotification(handle, &message); + } + } +} +#endif + +/*! + * @brief Get dvice stack version function. + * + * The function is used to get dvice stack version. + * + * @param[out] version The version structure pointer to keep the device stack version. + * + */ +void USB_DeviceGetVersion(uint32_t *version) +{ + if (version) + { + *version = + (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX); + } +} + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] tick Current hardware tick. + * + */ +usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick) +{ + usb_device_struct_t *deviceHandle; + usb_status_t status = kStatus_USB_Success; + + if (handle == NULL) + { + return kStatus_USB_InvalidHandle; + } + deviceHandle = (usb_device_struct_t *)handle; + + deviceHandle->hwTick = tick; + + return status; +} +#endif +#endif /* USB_DEVICE_CONFIG_NUM */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_dci.h b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_dci.h new file mode 100644 index 0000000000000000000000000000000000000000..fd4fdceb0416aec6815e73a1205ae8d330a3fd85 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_dci.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_DEVICE_DCI_H__ +#define __USB_DEVICE_DCI_H__ + +/*! + * @addtogroup usb_device_controller_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Macro to define controller handle */ +#define usb_device_controller_handle usb_device_handle + +/*! @brief Available notify types for device notification */ +typedef enum _usb_device_notification +{ + kUSB_DeviceNotifyBusReset = 0x10U, /*!< Reset signal detected */ + kUSB_DeviceNotifySuspend, /*!< Suspend signal detected */ + kUSB_DeviceNotifyResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyLPMSleep, /*!< LPM signal detected */ + kUSB_DeviceNotifyLPMResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyError, /*!< Errors happened in bus */ + kUSB_DeviceNotifyDetach, /*!< Device disconnected from a host */ + kUSB_DeviceNotifyAttach, /*!< Device connected to a host */ +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) + kUSB_DeviceNotifyDcdTimeOut, /*!< Device charger detection timeout */ + kUSB_DeviceNotifyDcdUnknownPortType, /*!< Device charger detection unknown port type */ + kUSB_DeviceNotifySDPDetected, /*!< The SDP facility is detected */ + kUSB_DeviceNotifyChargingPortDetected, /*!< The charging port is detected */ + kUSB_DeviceNotifyChargingHostDetected, /*!< The CDP facility is detected */ + kUSB_DeviceNotifyDedicatedChargerDetected, /*!< The DCP facility is detected */ +#endif +} usb_device_notification_t; + +/*! @brief Device notification message structure */ +typedef struct _usb_device_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t code; /*!< Notification code */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_callback_message_struct_t; + +/*! @brief Control type for controller */ +typedef enum _usb_device_control_type +{ + kUSB_DeviceControlRun = 0U, /*!< Enable the device functionality */ + kUSB_DeviceControlStop, /*!< Disable the device functionality */ + kUSB_DeviceControlEndpointInit, /*!< Initialize a specified endpoint */ + kUSB_DeviceControlEndpointDeinit, /*!< De-initialize a specified endpoint */ + kUSB_DeviceControlEndpointStall, /*!< Stall a specified endpoint */ + kUSB_DeviceControlEndpointUnstall, /*!< Unstall a specified endpoint */ + kUSB_DeviceControlGetDeviceStatus, /*!< Get device status */ + kUSB_DeviceControlGetEndpointStatus, /*!< Get endpoint status */ + kUSB_DeviceControlSetDeviceAddress, /*!< Set device address */ + kUSB_DeviceControlGetSynchFrame, /*!< Get current frame */ + kUSB_DeviceControlResume, /*!< Drive controller to generate a resume signal in USB bus */ + kUSB_DeviceControlSleepResume, /*!< Drive controller to generate a LPM resume signal in USB bus */ + kUSB_DeviceControlSuspend, /*!< Drive controller to enetr into suspend mode */ + kUSB_DeviceControlSleep, /*!< Drive controller to enetr into sleep mode */ + kUSB_DeviceControlSetDefaultStatus, /*!< Set controller to default status */ + kUSB_DeviceControlGetSpeed, /*!< Get current speed */ + kUSB_DeviceControlGetOtgStatus, /*!< Get OTG status */ + kUSB_DeviceControlSetOtgStatus, /*!< Set OTG status */ + kUSB_DeviceControlSetTestMode, /*!< Drive xCHI into test mode */ + kUSB_DeviceControlGetRemoteWakeUp, /*!< Get flag of LPM Remote Wake-up Enabled by USB host. */ +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) + kUSB_DeviceControlDcdInitModule, + kUSB_DeviceControlDcdDeinitModule, +#endif +} usb_device_control_type_t; + +/*! @brief USB device controller initialization function typedef */ +typedef usb_status_t (*usb_device_controller_init_t)(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *controllerHandle); + +/*! @brief USB device controller de-initialization function typedef */ +typedef usb_status_t (*usb_device_controller_deinit_t)(usb_device_controller_handle controllerHandle); + +/*! @brief USB device controller send data function typedef */ +typedef usb_status_t (*usb_device_controller_send_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller receive data function typedef */ +typedef usb_status_t (*usb_device_controller_recv_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller cancel transfer function in a specified endpoint typedef */ +typedef usb_status_t (*usb_device_controller_cancel_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress); + +/*! @brief USB device controller control function typedef */ +typedef usb_status_t (*usb_device_controller_control_t)(usb_device_controller_handle controllerHandle, + usb_device_control_type_t command, + void *param); + +/*! @brief USB device controller interface structure */ +typedef struct _usb_device_controller_interface_struct +{ + usb_device_controller_init_t deviceInit; /*!< Controller initialization */ + usb_device_controller_deinit_t deviceDeinit; /*!< Controller de-initialization */ + usb_device_controller_send_t deviceSend; /*!< Controller send data */ + usb_device_controller_recv_t deviceRecv; /*!< Controller receive data */ + usb_device_controller_cancel_t deviceCancel; /*!< Controller cancel transfer */ + usb_device_controller_control_t deviceControl; /*!< Controller control */ +} usb_device_controller_interface_struct_t; + +/*! @brief USB device status structure */ +typedef struct _usb_device_struct +{ +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + volatile uint64_t hwTick; /*!< Current hw tick(ms)*/ +#endif + usb_device_controller_handle controllerHandle; /*!< Controller handle */ + const usb_device_controller_interface_struct_t *controllerInterface; /*!< Controller interface handle */ +#if USB_DEVICE_CONFIG_USE_TASK + usb_osa_msgq_handle notificationQueue; /*!< Message queue */ +#endif + usb_device_callback_t deviceCallback; /*!< Device callback function pointer */ + usb_device_endpoint_callback_struct_t + epCallback[USB_DEVICE_CONFIG_ENDPOINTS << 1U]; /*!< Endpoint callback function structure */ + uint8_t deviceAddress; /*!< Current device address */ + uint8_t controllerId; /*!< Controller ID */ + uint8_t state; /*!< Current device state */ +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + uint8_t remotewakeup; /*!< Remote wakeup is enabled or not */ +#endif + uint8_t isResetting; /*!< Is doing device reset or not */ +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + uint8_t epCallbackDirectly; /*!< Whether call ep callback directly when the task is enabled */ +#endif +} usb_device_struct_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @}*/ + +#endif /* __USB_DEVICE_DCI_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_ehci.c b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_ehci.c new file mode 100644 index 0000000000000000000000000000000000000000..507d00db06b119799c93c699f921fde453aaf56e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_ehci.c @@ -0,0 +1,1846 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_device_registers.h" +#include +#include "usb_device.h" +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) + +#include "usb_device_dci.h" + +#include "usb_device_ehci.h" +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#include "usb_phy.h" +#endif +#include "drv_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U) + +#error The SOC does not suppoort dedicated RAM case. + +#endif + +#define virtual_to_physical(v) ((void *)((size_t)v + PV_OFFSET)) +#define physical_to_virtual(p) ((void *)((size_t)p - PV_OFFSET)) + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState); +static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, + usb_device_endpoint_init_struct_t *epInit); +static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpoint, + uint8_t direction); +static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState); +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState); +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +extern usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Apply for QH buffer, 2048-byte alignment */ +void *qh_buffer_vir = NULL; +void *qh_buffer_phy = NULL; + +/* Apply for DTD buffer, 32-byte alignment */ +void *dtd_buffer_vir = NULL; +void *dtd_buffer_phy = NULL; + +/* Apply for ehci device state structure */ +static usb_device_ehci_state_struct_t g_UsbDeviceEhciSate[USB_DEVICE_CONFIG_EHCI]; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +/* Apply for device dcd state structure */ +static usb_device_dcd_state_struct_t s_UsbDeviceDcdHSState[USB_DEVICE_CONFIG_EHCI]; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief EHCI NC get USB NC bass address. + * + * This function is used to get USB NC bass address. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * + * @retval USB NC bass address. + */ +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +void *USB_EhciNCGetBase(uint8_t controllerId) +{ + void *usbNCBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbnc_base_temp[] = USBNC_BASE_ADDRS; + uint32_t usbnc_base[] = USBNC_BASE_ADDRS; + + if (controllerId < kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - kUSB_ControllerEhci0; + + for (instance = 0; instance < (sizeof(usbnc_base_temp) / sizeof(usbnc_base_temp[0])); instance++) + { + if (usbnc_base_temp[instance]) + { + usbnc_base[newinstance++] = usbnc_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + + usbNCBase = (void *)usbnc_base[controllerId]; +#endif + return usbNCBase; +} +#endif +#endif + +/*! + * @brief Set device controller state to default state. + * + * The function is used to set device controller state to default state. + * The function will be called when USB_DeviceEhciInit called or the control type kUSB_DeviceControlGetEndpointStatus + * received in USB_DeviceEhciControl. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState) +{ + usb_device_ehci_dtd_struct_t *p; + + /* Initialize the dtd free queue */ + ehciState->dtdFree = ehciState->dtd; + p = ehciState->dtdFree; + for (uint32_t i = 1U; i < USB_DEVICE_CONFIG_EHCI_MAX_DTD; i++) + { + p->nextDtdPointer = (uint32_t)&ehciState->dtd[i]; + p = (usb_device_ehci_dtd_struct_t *)p->nextDtdPointer; + } + p->nextDtdPointer = 0U; + + + ehciState->dtdCount = USB_DEVICE_CONFIG_EHCI_MAX_DTD; + + /* Not use interrupt threshold. */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ITC_MASK; + ehciState->registerBase->USBCMD |= USBHS_USBCMD_ITC(0U); + + /* Disable setup lockout, please refer to "Control Endpoint Operation" section in RM. */ + ehciState->registerBase->USBMODE |= USBHS_USBMODE_SLOM_MASK; + + /* Set the endian by using CPU's endian */ +//#if (ENDIANNESS == USB_BIG_ENDIAN) +#if 0 + ehciState->registerBase->USBMODE |= USBHS_USBMODE_ES_MASK; +#else + ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_ES_MASK; +#endif + /* Initialize the QHs of endpoint. */ + for (uint32_t i = 0U; i < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); i++) + { + ehciState->qh[i].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[i].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = + USB_CONTROL_MAX_PACKET_SIZE; + ehciState->dtdHard[i] = NULL; + ehciState->dtdTail[i] = NULL; + ehciState->qh[i].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; + } + + /* Add QH buffer address to USBHS_EPLISTADDR_REG */ + //ehciState->registerBase->EPLISTADDR = (uint32_t)ehciState->qh; + ehciState->registerBase->EPLISTADDR = (uint32_t)qh_buffer_phy; + + /* Clear device address */ + ehciState->registerBase->DEVICEADDR = 0U; + +#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) + ehciState->registerBase->OTGSC = ehciState->registerBase->OTGSC & 0x0000FFFF; + ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIE_MASK; +#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ + + /* Enable reset, sof, token, stall interrupt */ + ehciState->registerBase->USBINTR = + (USBHS_USBINTR_UE_MASK | USBHS_USBINTR_UEE_MASK | USBHS_USBINTR_PCE_MASK | USBHS_USBINTR_URE_MASK +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + | USBHS_USBINTR_SLE_MASK +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + ); + + /* Clear reset flag */ + ehciState->isResetting = 0U; +} + +/*! + * @brief Initialize a specified endpoint. + * + * The function is used to initialize a specified endpoint. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param epInit The endpoint initialization structure pointer. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, + usb_device_endpoint_init_struct_t *epInit) +{ + uint32_t primeBit = 1U << ((epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK) + + ((epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint16_t maxPacketSize = epInit->maxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK; + uint8_t endpoint = (epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK); + uint8_t direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + uint8_t transferType = epInit->transferType & USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK; + + /* Cancel pending transfer of the endpoint */ + USB_DeviceEhciCancel(ehciState, epInit->endpointAddress); + + if ((ehciState->registerBase->EPPRIME & primeBit) || (ehciState->registerBase->EPSR & primeBit)) + { + return kStatus_USB_Busy; + } + + /* Make the endpoint max packet size align with USB Specification 2.0. */ + if (USB_ENDPOINT_ISOCHRONOUS == transferType) + { + if (maxPacketSize > USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE) + { + maxPacketSize = USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE; + } + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = + 1U + ((maxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK) >> + USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT); + } + else + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = 0U; + } + + /* Save the max packet size of the endpoint */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = + maxPacketSize; + /* Set ZLT bit. */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.zlt = !epInit->zlt; + + /* Enable the endpoint. */ + if (USB_ENDPOINT_CONTROL == transferType) + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 1U; + ehciState->registerBase->EPCR0 |= + (direction ? + (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); + } + else + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 0U; + ehciState->registerBase->EPCR[endpoint - 1U] |= + (direction ? + (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); + } + + ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 1U; + return kStatus_USB_Success; +} + +/*! + * @brief De-initialize a specified endpoint. + * + * The function is used to de-initialize a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be disabled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint32_t primeBit = + 1U << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t endpoint = (ep & USB_ENDPOINT_NUMBER_MASK); + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + + ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; + + /* Cancel the transfer of the endpoint */ + USB_DeviceEhciCancel(ehciState, ep); + + if ((ehciState->registerBase->EPPRIME & primeBit) || (ehciState->registerBase->EPSR & primeBit)) + { + return kStatus_USB_Busy; + } + + /* Clear endpoint state */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristics = 0U; + /* Disable the endpoint */ + if (!endpoint) + { + ehciState->registerBase->EPCR0 &= + ~(direction ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK) : (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK)); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] &= + ~(direction ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK) : (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK)); + } + + return kStatus_USB_Success; +} + +/*! + * @brief Stall a specified endpoint. + * + * The function is used to stall a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be stalled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + + /* Cancel the transfer of the endpoint */ + USB_DeviceEhciCancel(ehciState, ep); + + /* Set endpoint stall flag. */ + if (ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios) + { + if (!endpoint) + { + ehciState->registerBase->EPCR0 |= (USBHS_EPCR_TXS_MASK | USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] |= (USBHS_EPCR_TXS_MASK | USBHS_EPCR_RXS_MASK); + } + } + else + { + if (!endpoint) + { + ehciState->registerBase->EPCR0 |= (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] |= (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + } + + return kStatus_USB_Success; +} + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be un-stalled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + /* Clear the endpoint stall state */ + if (!endpoint) + { + ehciState->registerBase->EPCR0 &= ~(direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] &= ~(direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + ehciState->registerBase->EPCR[endpoint - 1U] |= (direction ? USBHS_EPCR_TXR_MASK : USBHS_EPCR_RXR_MASK); + } + + return kStatus_USB_Success; +} + +/*! + * @brief Get setup packet data. + * + * The function is used to get setup packet data and copy to a backup buffer. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint number. + * + */ +static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t waitingSafelyAccess = 1U; + uint8_t index = (ep * 2U) | USB_OUT; + + /* Write 1U to clear corresponding bit in EPSETUPSR. */ + ehciState->registerBase->EPSETUPSR = 1U << ep; + while (waitingSafelyAccess) + { + /* Set the setup tripwire bit. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_SUTW_MASK; + + /* Copy setup packet data to backup buffer */ + ehciState->qh[index].setupBufferBack[0] = ehciState->qh[index].setupBuffer[0]; + ehciState->qh[index].setupBufferBack[1] = ehciState->qh[index].setupBuffer[1]; + + /* Read the USBCMD[SUTW] bit. If set, jump out from the while loop; if cleared continue */ + if (ehciState->registerBase->USBCMD & USBHS_USBCMD_SUTW_MASK) + { + waitingSafelyAccess = 0U; + } + } + /* Clear the setup tripwire bit */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_SUTW_MASK; + + /* Poll until the EPSETUPSR bit clearred */ + while (ehciState->registerBase->EPSETUPSR & (1U << ep)) + { + } +} + +/*! + * @brief Cancel the transfer of the control pipe. + * + * The function is used to cancel the transfer of the control pipe. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param endpoint The endpoint number. + * @param direction The direction of the endpoint. + * + */ +static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpoint, + uint8_t direction) +{ + usb_device_ehci_dtd_struct_t *currentDtd; + uint32_t index = ((uint32_t)endpoint << 1U) + (uint32_t)direction; + usb_device_callback_message_struct_t message; + + message.buffer = NULL; + message.length = 0U; + /* Get the dtd of the control pipe */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + /* Pass the transfer buffer address */ + if (NULL == message.buffer) + { + uint32_t bufferAddress = currentDtd->bufferPointerPage[0]; + message.buffer = (uint8_t *)((bufferAddress & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + /* If the dtd is active, set the message length to USB_UNINITIALIZED_VAL_32. Or set the length by using finished + * length. */ + if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) + { + message.length = USB_UNINITIALIZED_VAL_32; + } + else + { + message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - + currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); + } + + /* Move the dtd head pointer to next. */ + /* If the pointer of the head equals to the tail, set the dtd queue to null. */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + else + { + ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); + message.isSetup = 0U; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + message.length = 0U; + } + + /* Clear the token field of the dtd. */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + /* Add the dtd to the free dtd queue. */ + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + + /* Get the next in-used dtd. */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } +} + +/*! + * @brief Handle the endpoint token done interrupt. + * + * The function is used to handle the endpoint token done interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState) +{ + uint32_t status; + uint32_t primeBit; + usb_device_ehci_dtd_struct_t *currentDtd; + usb_device_callback_message_struct_t message; + uint8_t endpoint; + uint8_t direction; + uint8_t count; + uint8_t index; + + /* Get the EPSETUPSR to check the setup packect received in which one endpoint. */ + status = ehciState->registerBase->EPSETUPSR; + + if (status) + { + for (endpoint = 0U; endpoint < USB_DEVICE_CONFIG_ENDPOINTS; endpoint++) + { + /* Check the endpoint receive the setup packet. */ + if (status & (1U << endpoint)) + { + /* Get last setup packet */ + usb_setup_struct_t *deviceSetup = + (usb_setup_struct_t *)&ehciState->qh[(uint8_t)((uint32_t)endpoint << 1U) + USB_OUT].setupBufferBack; + + /* Check the direction of the data phase. */ + direction = (deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_IN) >> USB_REQUEST_TYPE_DIR_SHIFT; + /* Cancel the data phase transfer */ + USB_DeviceEhciCancelControlPipe(ehciState, endpoint, direction); + /* Cancel the status phase transfer */ + USB_DeviceEhciCancelControlPipe(ehciState, endpoint, 1U ^ direction); + message.code = (endpoint) | (USB_OUT << 0x07U); + message.buffer = (uint8_t *)deviceSetup; + message.length = USB_SETUP_PACKET_SIZE; + message.isSetup = 1U; + + /* Fill the setup packet to the backup buffer */ + USB_DeviceEhciFillSetupBuffer(ehciState, endpoint); + /* Notify the up layer the EHCI status changed. */ + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } + } + /* Read the USBHS_EPCOMPLETE_REG to get the endpoint transfer done status */ + status = ehciState->registerBase->EPCOMPLETE; + /* Clear the endpoint transfer done status */ + ehciState->registerBase->EPCOMPLETE = status; + + if (status) + { + for (count = 0U; count < 32U; count++) + { + /* Check the transfer is done or not in the specified endpoint. */ + if (status & ((uint32_t)(1U << count))) + { + if (count > 15U) + { + endpoint = count - 16U; + direction = USB_IN; + } + else + { + endpoint = count; + direction = USB_OUT; + } + if (endpoint >= USB_DEVICE_CONFIG_ENDPOINTS) + { + continue; + } + index = (endpoint << 1U) + direction; + message.buffer = NULL; + message.length = 0U; + + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + uint8_t isTokenDone = 0; + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + + while (currentDtd) + { + /* Don't handle the active dtd. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) || + (currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) + { + if ((!(currentDtd->dtdTokenUnion.dtdTokenBitmap.status & + USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) && + (currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) + { + isTokenDone = 1U; + } + break; + } + currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + + if ((0 == isTokenDone) && (currentDtd)) + { + break; + } + + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + /* Don't handle the active dtd. */ + if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) + { + break; + } + + /* Save the transfer buffer address */ + if (NULL == message.buffer) + { + message.buffer = + (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + /* Save the transferred data length */ + message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - + currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); + + /* Move the dtd queue head pointer to next */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + else + { + ehciState->dtdHard[index] = + (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); + message.isSetup = 0U; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + message.length = 0U; + } + /* Clear the token field of the dtd */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + /* Get the next in-used dtd */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + + if ((NULL != currentDtd) && + (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) + { + primeBit = 1U << (endpoint + 16U * direction); + + /* Try to prime the next dtd. */ + ehciState->registerBase->EPPRIME = primeBit; + + /* Whether the endpoint transmit/receive buffer is ready or not. If not, wait for prime bit + * cleared and prime the next dtd. */ + if (!(ehciState->registerBase->EPSR & primeBit)) + { + /* Wait for the endpoint prime bit cleared by HW */ + while (ehciState->registerBase->EPPRIME & primeBit) + { + } + + /* If the endpoint transmit/receive buffer is not ready */ + if (!(ehciState->registerBase->EPSR & primeBit)) + { + /* Prime next dtd and prime the transfer */ + ehciState->qh[index].nextDtdPointer = (uint32_t)currentDtd; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + ehciState->registerBase->EPPRIME = primeBit; + } + } + } + } + } + } + } + } +} + +/*! + * @brief Handle the port status change interrupt. + * + * The function is used to handle the port status change interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState) +{ + usb_device_callback_message_struct_t message; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + + /* Whether the port is doing reset. */ + if (!(ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK)) + { + /* If not, update the USB speed. */ + if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_HSP_MASK) + { + ehciState->speed = USB_SPEED_HIGH; + } + else + { + ehciState->speed = USB_SPEED_FULL; + } + + /* If the device reset flag is non-zero, notify the up layer the device reset finished. */ + if (ehciState->isResetting) + { + message.code = kUSB_DeviceNotifyBusReset; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + ehciState->isResetting = 0U; + } + } + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + if ((ehciState->isSuspending) && (!(ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK))) + { + /* Set the resume flag */ + ehciState->isSuspending = 0U; + + message.code = kUSB_DeviceNotifyResume; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +} + +/*! + * @brief Handle the reset interrupt. + * + * The function is used to handle the reset interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState) +{ + uint32_t status = 0U; + + /* Clear the setup flag */ + status = ehciState->registerBase->EPSETUPSR; + ehciState->registerBase->EPSETUPSR = status; + /* Clear the endpoint complete flag */ + status = ehciState->registerBase->EPCOMPLETE; + ehciState->registerBase->EPCOMPLETE = status; + + do + { + /* Flush the pending transfers */ + ehciState->registerBase->EPFLUSH = USBHS_EPFLUSH_FERB_MASK | USBHS_EPFLUSH_FETB_MASK; + } while (ehciState->registerBase->EPPRIME & (USBHS_EPPRIME_PERB_MASK | USBHS_EPPRIME_PETB_MASK)); + + /* Whether is the port reset. If yes, set the isResetting flag. Or, notify the up layer. */ + if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) + { + ehciState->isResetting = 1U; + } + else + { + usb_device_callback_message_struct_t message; + message.buffer = (uint8_t *)NULL; + message.code = kUSB_DeviceNotifyBusReset; + message.length = 0U; + message.isSetup = 0U; + + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +} + +/*! + * @brief Handle the sof interrupt. + * + * The function is used to handle the sof interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState) +{ +} + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief Handle the suspend interrupt. + * + * The function is used to handle the suspend interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState) +{ + /* If the port is in suspend state, notify the up layer */ + if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK) + { +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +#else + if (ehciState->registerPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) +#endif + { + usb_device_callback_message_struct_t message; + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + message.code = kUSB_DeviceNotifySuspend; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } +} +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + +/*! + * @brief Get dtds and link to QH. + * + * The function is used to get dtds and link to QH. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param endpointAddress The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * @param buffer The memory address needed to be transferred. + * @param length Data length. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + usb_device_ehci_dtd_struct_t *dtd; + usb_device_ehci_dtd_struct_t *dtdHard; + uint32_t index = ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) << 1U) | + ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + uint32_t primeBit = 1U << ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) + + ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t epStatus = primeBit; + uint32_t sendLength; + uint32_t currentIndex = 0U; + uint32_t dtdRequestCount = (length + USB_DEVICE_ECHI_DTD_TOTAL_BYTES - 1U) / USB_DEVICE_ECHI_DTD_TOTAL_BYTES; + uint8_t qhIdle = 0U; + uint8_t waitingSafelyAccess = 1U; + + + USB_OSA_SR_ALLOC(); + + if (!ehciState) + { + return kStatus_USB_InvalidHandle; + } + + if (0U == ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened) + { + return kStatus_USB_Error; + } + /* Return error when ehci is doing reset */ + if (ehciState->isResetting) + { + return kStatus_USB_Error; + } + + if (!dtdRequestCount) + { + dtdRequestCount = 1U; + } + + USB_OSA_ENTER_CRITICAL(); + /* The free dtd count need to not less than the transfer requests. */ + if (dtdRequestCount > (uint32_t)ehciState->dtdCount) + { + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Busy; + } + + do + { + /* The transfer length need to not more than USB_DEVICE_ECHI_DTD_TOTAL_BYTES for each dtd. */ + if (length > USB_DEVICE_ECHI_DTD_TOTAL_BYTES) + { + sendLength = USB_DEVICE_ECHI_DTD_TOTAL_BYTES; + } + else + { + sendLength = length; + } + length -= sendLength; + + /* Get a free dtd */ + dtd = ehciState->dtdFree; + + ehciState->dtdFree = (usb_device_ehci_dtd_struct_t *)dtd->nextDtdPointer; + ehciState->dtdCount--; + + /* Save the dtd head when current active buffer offset is zero. */ + if (!currentIndex) + { + dtdHard = dtd; + } + + /* Set the dtd field */ + dtd->nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + dtd->dtdTokenUnion.dtdToken = 0U; + + dtd->bufferPointerPage[0] = (uint32_t)(virtual_to_physical(buffer) + currentIndex); + dtd->bufferPointerPage[1] = + (dtd->bufferPointerPage[0] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK) & USB_DEVICE_ECHI_DTD_PAGE_MASK; + dtd->bufferPointerPage[2] = dtd->bufferPointerPage[1] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + dtd->bufferPointerPage[3] = dtd->bufferPointerPage[2] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + dtd->bufferPointerPage[4] = dtd->bufferPointerPage[3] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + + dtd->dtdTokenUnion.dtdTokenBitmap.totalBytes = sendLength; + + /* Save the data length needed to be transferred. */ + dtd->reservedUnion.originalBufferInfo.originalBufferLength = sendLength; + /* Save the original buffer address */ + dtd->reservedUnion.originalBufferInfo.originalBufferOffest = + dtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK; + dtd->reservedUnion.originalBufferInfo.dtdInvalid = 0U; + + /* Set the IOC field in last dtd. */ + if (!length) + { + dtd->dtdTokenUnion.dtdTokenBitmap.ioc = 1U; + } + + /* Set dtd active */ + dtd->dtdTokenUnion.dtdTokenBitmap.status = USB_DEVICE_ECHI_DTD_STATUS_ACTIVE; + + /* Move the buffer offset index */ + currentIndex += sendLength; + + /* Add dtd to the in-used dtd queue */ + if (ehciState->dtdTail[index]) + { + ehciState->dtdTail[index]->nextDtdPointer = (uint32_t)dtd; + ehciState->dtdTail[index] = dtd; + } + else + { + ehciState->dtdHard[index] = dtd; + ehciState->dtdTail[index] = dtd; + qhIdle = 1U; + } + } while (length); + + /* If the QH is not empty */ + if (!qhIdle) + { + /* If the prime bit is set, nothing need to do. */ + if (ehciState->registerBase->EPPRIME & primeBit) + { + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; + } + /* To safely a dtd */ + while (waitingSafelyAccess) + { + /* set the ATDTW flag to USBHS_USBCMD_REG. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_ATDTW_MASK; + /* Read EPSR */ + epStatus = ehciState->registerBase->EPSR; + /* Wait the ATDTW bit set */ + if (ehciState->registerBase->USBCMD & USBHS_USBCMD_ATDTW_MASK) + { + waitingSafelyAccess = 0U; + } + } + /* Clear the ATDTW bit */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ATDTW_MASK; + } + void *dtdhard_phy = NULL; + /* If QH is empty or the endpoint is not primed, need to link current dtd head to the QH. */ + /* When the endpoint is not primed if qhIdle is zero, it means the QH is empty. */ + if ((qhIdle) || (!(epStatus & primeBit))) + { + //ehciState->qh[index].nextDtdPointer = (uint32_t)dtdHard; + dtdhard_phy = imx6ull_get_periph_paddr((uint32_t)dtdHard); + ehciState->qh[index].nextDtdPointer = (uint32_t)dtdhard_phy; + + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + + ehciState->registerBase->EPPRIME = primeBit; + while (!(ehciState->registerBase->EPSR & primeBit)) + { + if (ehciState->registerBase->EPCOMPLETE & primeBit) + { + break; + } + else + { + ehciState->registerBase->EPPRIME = primeBit; + } + } + } + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +/*! + * @brief Initialize the USB device EHCI instance. + * + * This function initializes the USB device EHCI module specified by the controllerId. + * + * @param controllerId The controller id of the USB IP. Please refer to enumeration type usb_controller_index_t. + * @param handle Pointer of the device handle, used to identify the device object is belonged to. + * @param ehciHandle It is out parameter, is used to return pointer of the device EHCI handle to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *ehciHandle) +{ + usb_device_ehci_state_struct_t *ehciState; + uint32_t ehci_base[] = USBHS_BASE_ADDRS; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + usb_device_dcd_state_struct_t *dcdHSState; + uint32_t dcd_base[] = USBHSDCD_BASE_ADDRS; + usb_device_callback_message_struct_t message; +#endif + + if ((controllerId < kUSB_ControllerEhci0) || + ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= USB_DEVICE_CONFIG_EHCI) || + ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= (sizeof(ehci_base) / sizeof(uint32_t)))) + { + return kStatus_USB_ControllerNotFound; + } + + ehciState = &g_UsbDeviceEhciSate[controllerId - kUSB_ControllerEhci0]; + + int num = 1; + int page_size = 4096; + + qh_buffer_vir = (void *)rt_pages_alloc(num); + if(!qh_buffer_vir) + { + rt_kprintf("ERROR: qh buff page alloc failed\n"); + return kStatus_USB_Error; + } + qh_buffer_phy = virtual_to_physical(qh_buffer_vir); + qh_buffer_vir = rt_ioremap_nocache(virtual_to_physical(qh_buffer_vir), (page_size<dtd = s_UsbDeviceEhciDtd[controllerId - kUSB_ControllerEhci0]; + //ehciState->qh = (usb_device_ehci_qh_struct_t *)&qh_buffer[(controllerId - kUSB_ControllerEhci0) * 2048]; + + ehciState->dtd = (usb_device_ehci_dtd_struct_t *)dtd_buffer_vir; + ehciState->qh = (usb_device_ehci_qh_struct_t *)qh_buffer_vir; + + ehciState->controllerId = controllerId; + + ehciState->registerBase = (USBHS_Type *)ehci_base[controllerId - kUSB_ControllerEhci0]; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + ehciState->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerNcBase = (USBNC_Type *)USB_EhciNCGetBase(controllerId); +#endif + +#endif + + /* Get the HW's endpoint count */ + ehciState->endpointCount = + (uint8_t)((ehciState->registerBase->DCCPARAMS & USBHS_DCCPARAMS_DEN_MASK) >> USBHS_DCCPARAMS_DEN_SHIFT); + + if (ehciState->endpointCount < USB_DEVICE_CONFIG_ENDPOINTS) + { + return kStatus_USB_Error; + } + ehciState->deviceHandle = (usb_device_struct_t *)handle; + + /* Clear the controller mode field and set to device mode. */ + ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_CM_MASK; + ehciState->registerBase->USBMODE |= USBHS_USBMODE_CM(0x02U); + + /* Set the EHCI to default status. */ + USB_DeviceEhciSetDefaultState(ehciState); + *ehciHandle = (usb_device_controller_handle)ehciState; +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + dcdHSState = &s_UsbDeviceDcdHSState[controllerId - kUSB_ControllerEhci0]; + + dcdHSState->controllerId = controllerId; + + dcdHSState->dcdRegisterBase = (USBHSDCD_Type *)dcd_base[controllerId - kUSB_ControllerEhci0]; + + dcdHSState->deviceHandle = (usb_device_struct_t *)handle; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK) + { + /* Device is connected to a host. */ + message.code = kUSB_DeviceNotifyAttach; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief De-initialize the USB device EHCI instance. + * + * This function de-initializes the USB device EHCI module. + * + * @param ehciHandle Pointer of the device EHCI handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + + if (!ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + + /* Disable all interrupt. */ + ehciState->registerBase->USBINTR = 0U; + /* Stop the device functionality. */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + /* Reset the controller. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_RST_MASK; + + return kStatus_USB_Success; +} + +/*! + * @brief Send data through a specified endpoint. + * + * This function sends data through a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to hold the data need to be sent. + * @param length The data length need to be sent. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the sending request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + /* Add dtd to the QH */ + return USB_DeviceEhciTransfer( + (usb_device_ehci_state_struct_t *)ehciHandle, + (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Receive data through a specified endpoint. + * + * This function Receives data through a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to save the received data. + * @param length The data length want to be received. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + /* Add dtd to the QH */ + return USB_DeviceEhciTransfer( + (usb_device_ehci_state_struct_t *)ehciHandle, + (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Cancel the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + usb_device_callback_message_struct_t message; + usb_device_ehci_dtd_struct_t *currentDtd; + uint32_t primeBit = + 1U << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t index = + ((ep & USB_ENDPOINT_NUMBER_MASK) << 1U) | ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x07U); + + USB_OSA_SR_ALLOC(); + + if (!ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + + USB_OSA_ENTER_CRITICAL(); + + message.buffer = NULL; + message.length = USB_UNINITIALIZED_VAL_32; + + /* Get the first dtd */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + + while (currentDtd) + { + currentDtd->reservedUnion.originalBufferInfo.dtdInvalid = 1U; + currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + + /* Get the first dtd */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + if (!currentDtd->reservedUnion.originalBufferInfo.dtdInvalid) + { + break; + } + else + { + if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) + { + /* Flush the endpoint to stop a transfer. */ + do + { + /* Set the corresponding bit(s) in the EPFLUSH register */ + ehciState->registerBase->EPFLUSH |= primeBit; + + /* Wait until all bits in the EPFLUSH register are cleared. */ + while (ehciState->registerBase->EPFLUSH & primeBit) + { + } + /* + * Read the EPSR register to ensure that for all endpoints + * commanded to be flushed, that the corresponding bits + * are now cleared. + */ + } while (ehciState->registerBase->EPSR & primeBit); + } + + /* Save the original buffer address. */ + if (NULL == message.buffer) + { + message.buffer = (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + + /* Remove the dtd from the dtd in-used queue. */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + } + else + { + ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = ep; + message.isSetup = 0U; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + } + /* Clear the token field. */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + /* Save the dtd to the free queue. */ + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + } + /* Get the next dtd. */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + if (!currentDtd) + { + /* Set the QH to empty. */ + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +/*! + * @brief Control the status of the selected item. + * + * The function is used to control the status of the selected item. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param type The selected item. Please refer to enumeration type usb_device_control_type_t. + * @param param The param type is determined by the selected item. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, usb_device_control_type_t type, void *param) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + usb_status_t error = kStatus_USB_Error; + uint16_t *temp16; + uint8_t *temp8; +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + usb_device_dcd_state_struct_t *dcdHSState; + dcdHSState = + &s_UsbDeviceDcdHSState[ehciState->controllerId - kUSB_ControllerEhci0]; /*The hard code should be replaced*/ + usb_device_dcd_charging_time_t *deviceDcdTimingConfig = (usb_device_dcd_charging_time_t *)param; +#endif +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + usb_device_struct_t *deviceHandle; + uint64_t startTick; +#endif + + if (!ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + deviceHandle = (usb_device_struct_t *)ehciState->deviceHandle; +#endif + + switch (type) + { + case kUSB_DeviceControlRun: + ehciState->registerBase->USBCMD |= USBHS_USBCMD_RS_MASK; + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlStop: + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlEndpointInit: + if (param) + { + error = USB_DeviceEhciEndpointInit(ehciState, (usb_device_endpoint_init_struct_t *)param); + } + break; + case kUSB_DeviceControlEndpointDeinit: + if (param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointDeinit(ehciState, *temp8); + } + break; + case kUSB_DeviceControlEndpointStall: + if (param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointStall(ehciState, *temp8); + } + break; + case kUSB_DeviceControlEndpointUnstall: + if (param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointUnstall(ehciState, *temp8); + } + break; + case kUSB_DeviceControlGetDeviceStatus: + if (param) + { + temp16 = (uint16_t *)param; + *temp16 = (USB_DEVICE_CONFIG_SELF_POWER << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT)) +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + | (deviceHandle->remotewakeup << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT)) +#endif + ; + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetEndpointStatus: + if (param) + { + usb_device_endpoint_status_struct_t *endpointStatus = (usb_device_endpoint_status_struct_t *)param; + uint8_t ep = (endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + ((endpointStatus->endpointAddress) & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + if (ep < USB_DEVICE_CONFIG_ENDPOINTS) + { + if (ep) + { + endpointStatus->endpointStatus = (ehciState->registerBase->EPCR[ep - 1U] & + (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK)) ? + kUSB_DeviceEndpointStateStalled : + kUSB_DeviceEndpointStateIdle; + } + else + { + endpointStatus->endpointStatus = + (ehciState->registerBase->EPCR0 & (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK)) ? + kUSB_DeviceEndpointStateStalled : + kUSB_DeviceEndpointStateIdle; + } + error = kStatus_USB_Success; + } + } + break; + case kUSB_DeviceControlSetDeviceAddress: + if (param) + { + temp8 = (uint8_t *)param; + ehciState->registerBase->DEVICEADDR = (((uint32_t)(*temp8)) << USBHS_DEVICEADDR_USBADR_SHIFT); + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetSynchFrame: + break; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U) + case kUSB_DeviceControlResume: +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; + startTick = deviceHandle->hwTick; + while ((deviceHandle->hwTick - startTick) < 10) + { + __ASM("nop"); + } + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_FPR_MASK; + error = kStatus_USB_Success; + break; +#endif /* USB_DEVICE_CONFIG_REMOTE_WAKEUP */ + case kUSB_DeviceControlSuspend: + ehciState->registerBase->OTGSC |= 0x007F0000U; + ehciState->registerPhyBase->PWD = 0xFFFFFFFF; + /* ehciState->registerBase->OTGCTL |= ((1U<<10) | (1U<<17) | (1U<<16)); */ + while (ehciState->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK)) + { + __ASM("nop"); + } + /* ehciState->registerPhyBase->CTRL |= ((1U << 21) | (1U << 22) | (1U << 23)); */ + ehciState->registerBase->USBSTS |= USBHS_USBSTS_SRI_MASK; + ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_ENVBUSCHG_WKUP_MASK | USBPHY_CTRL_ENIDCHG_WKUP_MASK | + USBPHY_CTRL_ENDPDMCHG_WKUP_MASK | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciState->registerBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; + ehciState->isSuspending = 1U; + error = kStatus_USB_Success; + break; +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + case kUSB_DeviceControlSetDefaultStatus: + for (uint8_t count = 0U; count < USB_DEVICE_CONFIG_ENDPOINTS; count++) + { + USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_IN << 0x07U))); + USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_OUT << 0x07U))); + } + USB_DeviceEhciSetDefaultState(ehciState); + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlGetSpeed: + if (param) + { + temp8 = (uint8_t *)param; + *temp8 = ehciState->speed; + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetOtgStatus: + break; + case kUSB_DeviceControlSetOtgStatus: + break; +#if (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) + case kUSB_DeviceControlSetTestMode: + if (param) + { + temp8 = (uint8_t *)param; + ehciState->registerBase->PORTSC1 |= ((uint32_t)(*temp8) << 16U); + error = kStatus_USB_Success; + } + break; +#endif +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + case kUSB_DeviceControlDcdInitModule: + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + dcdHSState->dcdRegisterBase->TIMER0 = USBDCD_TIMER0_TSEQ_INIT(deviceDcdTimingConfig->dcdSeqInitTime); + dcdHSState->dcdRegisterBase->TIMER1 = USBDCD_TIMER1_TDCD_DBNC(deviceDcdTimingConfig->dcdDbncTime); + dcdHSState->dcdRegisterBase->TIMER1 |= USBDCD_TIMER1_TVDPSRC_ON(deviceDcdTimingConfig->dcdDpSrcOnTime); + dcdHSState->dcdRegisterBase->TIMER2_BC12 = + USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(deviceDcdTimingConfig->dcdTimeWaitAfterPrD); + dcdHSState->dcdRegisterBase->TIMER2_BC12 |= + USBDCD_TIMER2_BC12_TVDMSRC_ON(deviceDcdTimingConfig->dcdTimeDMSrcOn); + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IE_MASK; + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_BC12_MASK; + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_START_MASK; + break; + case kUSB_DeviceControlDcdDeinitModule: + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + break; +#endif + + default: + break; + } + + return error; +} + +/*! + * @brief Handle the EHCI device interrupt. + * + * The function is used to handle the EHCI device interrupt. + * + * @param deviceHandle The device handle got from USB_DeviceInit. + * + */ +void USB_DeviceEhciIsrFunction(void *deviceHandle) +{ + usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; + usb_device_ehci_state_struct_t *ehciState; + uint32_t status; + + if (NULL == deviceHandle) + { + return; + } + + ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); + + + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + + if (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK) + { + if (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIR_MASK) + { + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; + } + } + else + { + } + +#else + if (ehciState->registerBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK) + { + if (ehciState->registerBase->USBGENCTRL & (1U << 8)) + { + ehciState->registerBase->USBGENCTRL &= ~(1U << 8); + ehciState->registerBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK; + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; + } + } + else + { + } +#endif + +#endif + +#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) + if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSVIS_MASK) + { + usb_device_callback_message_struct_t message; + + ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIS_MASK; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK) + { + /* Device is connected to a host. */ + message.code = kUSB_DeviceNotifyAttach; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + else + { + /* Device is disconnected from a host. */ + message.code = kUSB_DeviceNotifyDetach; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } +#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ + + status = ehciState->registerBase->USBSTS; + status &= ehciState->registerBase->USBINTR; + + ehciState->registerBase->USBSTS = status; + +#if defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U) + if (status & USBHS_USBSTS_UEI_MASK) + { + /* Error interrupt */ + USB_DeviceEhciInterruptError(ehciState); + } +#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */ + + if (status & USBHS_USBSTS_URI_MASK) + { + /* Reset interrupt */ + USB_DeviceEhciInterruptReset(ehciState); + } + + if (status & USBHS_USBSTS_UI_MASK) + { + /* Token done interrupt */ + USB_DeviceEhciInterruptTokenDone(ehciState); + } + + if (status & USBHS_USBSTS_PCI_MASK) + { + /* Port status change interrupt */ + USB_DeviceEhciInterruptPortChange(ehciState); + } + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + if (status & USBHS_USBSTS_SLI_MASK) + { + /* Suspend interrupt */ + USB_DeviceEhciInterruptSuspend(ehciState); + } +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + + if (status & USBHS_USBSTS_SRI_MASK) + { + /* Sof interrupt */ + USB_DeviceEhciInterruptSof(ehciState); + } +} + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +void USB_DeviceDcdHSIsrFunction(void *deviceHandle) +{ + usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; + usb_device_ehci_state_struct_t *ehciState; + usb_device_dcd_state_struct_t *dcdHSState; + uint32_t status; + uint32_t chargerType; + usb_device_callback_message_struct_t message; + + if (NULL == deviceHandle) + { + return; + } + + ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); + + dcdHSState = &s_UsbDeviceDcdHSState[ehciState->controllerId - kUSB_ControllerEhci0]; + + status = dcdHSState->dcdRegisterBase->STATUS; + + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IACK_MASK; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + + if (status & USBDCD_STATUS_ERR_MASK) + { + if (status & USBDCD_STATUS_TO_MASK) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyDcdTimeOut; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + else + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyDcdUnknownPortType; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + } + else + { + switch (status & USBDCD_STATUS_SEQ_STAT_MASK) + { + case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargingPortDetectionCompleted): + chargerType = status & USBDCD_STATUS_SEQ_RES_MASK; + if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionStandardHost)) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifySDPDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort)) + { + message.code = kUSB_DeviceNotifyChargingPortDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + break; + case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargerTypeDetectionCompleted): + chargerType = status & USBDCD_STATUS_SEQ_RES_MASK; + if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort)) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyChargingHostDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionDedicatedCharger)) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyDedicatedChargerDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + break; + + default: + break; + } + } +} +#endif + +#endif /* USB_DEVICE_CONFIG_EHCI */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_ehci.h b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_ehci.h new file mode 100644 index 0000000000000000000000000000000000000000..869e0632639020680dc4f6e762004cc1a4aab755 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/device/usb_device_ehci.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_DEVICE_EHCI_H__ +#define __USB_DEVICE_EHCI_H__ + +#include + +/*! + * @addtogroup usb_device_controller_ehci_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The maximum value of ISO type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE (1024U) + +/*! @brief The maximum value of interrupt type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_INTERUPT_MAX_PACKET_SIZE (1024U) + +/*! @brief The maximum value of bulk type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_BULK_MAX_PACKET_SIZE (512U) + +/*! @brief The maximum value of control type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_CONTROL_MAX_PACKET_SIZE (64U) + +/*! @brief EHCI state structure */ +typedef struct _usb_device_ehci_state_struct +{ + usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object is belonged to */ + USBHS_Type *registerBase; /*!< The base address of the register */ +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ +#endif +#endif + usb_device_ehci_qh_struct_t *qh; /*!< The QH structure base address */ + usb_device_ehci_dtd_struct_t *dtd; /*!< The DTD structure base address */ + usb_device_ehci_dtd_struct_t *dtdFree; /*!< The idle DTD list head */ + usb_device_ehci_dtd_struct_t + *dtdHard[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list head for each endpoint */ + usb_device_ehci_dtd_struct_t + *dtdTail[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list tail for each endpoint */ + int8_t dtdCount; /*!< The idle DTD node count */ + uint8_t endpointCount; /*!< The endpoint number of EHCI */ + uint8_t isResetting; /*!< Whether a PORT reset is occurring or not */ + uint8_t controllerId; /*!< Controller ID */ + uint8_t speed; /*!< Current speed of EHCI */ + uint8_t isSuspending; /*!< Is suspending of the PORT */ +} usb_device_ehci_state_struct_t; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +typedef struct _usb_device_dcd_state_struct +{ + usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object belongs to */ + USBHSDCD_Type *dcdRegisterBase; /*!< The base address of the dcd module */ + uint8_t controllerId; /*!< Controller ID */ +} usb_device_dcd_state_struct_t; +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name USB device EHCI functions + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes the USB device EHCI instance. + * + * This function initializes the USB device EHCI module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration type usb_controller_index_t. + * @param[in] handle Pointer of the device handle used to identify the device object is belonged to. + * @param[out] ehciHandle An out parameter used to return the pointer of the device EHCI handle to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *ehciHandle); + +/*! + * @brief Deinitializes the USB device EHCI instance. + * + * This function deinitializes the USB device EHCI module. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle); + +/*! + * @brief Sends data through a specified endpoint. + * + * This function sends data through a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. + * @param[in] length The data length to be sent. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value means whether the sending request is successful or not. The transfer completion is indicated + * by the + * corresponding callback function. + * Currently, only one transfer request can be supported for a specific endpoint. + * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer can begin only when the previous transfer is done (a notification is received through the + * endpoint + * callback). + */ +usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receive data through a specified endpoint. + * + * This function Receives data through a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length want to be received. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep); + +/*! + * @brief Controls the status of the selected item. + * + * The function is used to control the status of the selected item. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] type The selected item. See enumeration type usb_device_control_type_t. + * @param[in,out] param The parameter type is determined by the selected item. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, + usb_device_control_type_t type, + void *param); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __USB_DEVICE_EHCI_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host.h b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host.h new file mode 100644 index 0000000000000000000000000000000000000000..53be402cd3640a5f3b9ce4bc181004cb00fc08a8 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host.h @@ -0,0 +1,726 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_H_ +#define _USB_HOST_H_ + +#include +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +struct _usb_host_transfer; /* for cross reference */ + +/*! + * @addtogroup usb_host_drv + * @{ + */ + +/*! @brief USB host class handle type define */ +typedef void *usb_host_class_handle; + +/*! @brief USB host controller handle type define */ +typedef void *usb_host_controller_handle; + +/*! @brief USB host configuration handle type define */ +typedef void *usb_host_configuration_handle; + +/*! @brief USB host interface handle type define */ +typedef void *usb_host_interface_handle; + +/*! @brief USB host pipe handle type define */ +typedef void *usb_host_pipe_handle; + +/*! @brief Event codes for device attach/detach */ +typedef enum _usb_host_event +{ + kUSB_HostEventAttach = 1U, /*!< Device is attached */ + kUSB_HostEventDetach, /*!< Device is detached */ + kUSB_HostEventEnumerationDone, /*!< Device's enumeration is done and the device is supported */ + kUSB_HostEventNotSupported, /*!< Device's enumeration is done and the device is not supported */ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + kUSB_HostEventNotSuspended, /*!< Suspend failed */ + kUSB_HostEventSuspended, /*!< Suspend successful */ + kUSB_HostEventNotResumed, /*!< Resume failed */ + kUSB_HostEventDetectResume, /*!< Detect resume signal */ + kUSB_HostEventResumed, /*!< Resume successful */ + kUSB_HostEventL1Sleeped, /*!< L1 Sleep successful,state transition was successful (ACK) */ + kUSB_HostEventL1SleepNYET, /*!< Device was unable to enter the L1 state at this time (NYET) */ + kUSB_HostEventL1SleepNotSupport, /*!< Device does not support the L1 state (STALL) */ + kUSB_HostEventL1SleepError, /*!< Device failed to respond or an error occurred */ + kUSB_HostEventL1NotResumed, /*!< Resume failed */ + kUSB_HostEventL1DetectResume, /*!< Detect resume signal */ + kUSB_HostEventL1Resumed, /*!< Resume successful */ +#endif +} usb_host_event_t; + +/*! @brief USB host device information code */ +typedef enum _usb_host_dev_info +{ + kUSB_HostGetDeviceAddress = 1U, /*!< Device's address */ + kUSB_HostGetDeviceHubNumber, /*!< Device's first hub address */ + kUSB_HostGetDevicePortNumber, /*!< Device's first hub port number */ + kUSB_HostGetDeviceSpeed, /*!< Device's speed */ + kUSB_HostGetDeviceHSHubNumber, /*!< Device's first high-speed hub address */ + kUSB_HostGetDeviceHSHubPort, /*!< Device's first high-speed hub number */ + kUSB_HostGetDeviceLevel, /*!< Device's hub level */ + kUSB_HostGetHostHandle, /*!< Device's host handle */ + kUSB_HostGetDeviceControlPipe, /*!< Device's control pipe handle */ + kUSB_HostGetDevicePID, /*!< Device's PID */ + kUSB_HostGetDeviceVID, /*!< Device's VID */ + kUSB_HostGetHubThinkTime, /*!< Device's hub total think time */ + kUSB_HostGetDeviceConfigIndex, /*!< Device's running zero-based config index */ + kUSB_HostGetConfigurationDes, /*!< Device's configuration descriptor pointer */ + kUSB_HostGetConfigurationLength, /*!< Device's configuration descriptor pointer */ +} usb_host_dev_info_t; + +/*! + * @brief Host callback function typedef. + * + * This callback function is used to notify application device attach/detach event. + * This callback pointer is passed when initializing the host. + * + * @param deviceHandle The device handle, which indicates the attached device. + * @param configurationHandle The configuration handle contains the attached device's configuration information. + * @param event_code The callback event code; See the enumeration host_event_t. + * + * @return A USB error code or kStatus_USB_Success. + * @retval kStatus_USB_Success Application handles the attached device successfully. + * @retval kStatus_USB_NotSupported Application don't support the attached device. + * @retval kStatus_USB_Error Application handles the attached device falsely. + */ +typedef usb_status_t (*host_callback_t)(usb_device_handle deviceHandle, + usb_host_configuration_handle configurationHandle, + uint32_t eventCode); + +/*! + * @brief Transfer callback function typedef. + * + * This callback function is used to notify the upper layer the result of the transfer. + * This callback pointer is passed when calling the send/receive APIs. + * + * @param param The parameter pointer, which is passed when calling the send/receive APIs. + * @param data The data buffer pointer. + * @param data_len The result data length. + * @param status A USB error code or kStatus_USB_Success. + */ +typedef void (*transfer_callback_t)(void *param, uint8_t *data, uint32_t dataLen, usb_status_t status); + +/*! + * @brief Host stack inner transfer callback function typedef. + * + * This callback function is used to notify the upper layer the result of a transfer. + * This callback pointer is passed when initializing the structure usb_host_transfer_t. + * + * @param param The parameter pointer, which is passed when calling the send/receive APIs. + * @param transfer The transfer information; See the structure usb_host_transfer_t. + * @param status A USB error code or kStatus_USB_Success. + */ +typedef void (*host_inner_transfer_callback_t)(void *param, struct _usb_host_transfer *transfer, usb_status_t status); + +/*! @brief USB host endpoint information structure */ +typedef struct _usb_host_ep +{ + usb_descriptor_endpoint_t *epDesc; /*!< Endpoint descriptor pointer*/ + uint8_t *epExtension; /*!< Endpoint extended descriptor pointer*/ + uint16_t epExtensionLength; /*!< Extended descriptor length*/ +} usb_host_ep_t; + +/*! @brief USB host interface information structure */ +typedef struct _usb_host_interface +{ + usb_host_ep_t epList[USB_HOST_CONFIG_INTERFACE_MAX_EP]; /*!< Endpoint array*/ + usb_descriptor_interface_t *interfaceDesc; /*!< Interface descriptor pointer*/ + uint8_t *interfaceExtension; /*!< Interface extended descriptor pointer*/ + uint16_t interfaceExtensionLength; /*!< Extended descriptor length*/ + uint8_t interfaceIndex; /*!< The interface index*/ + uint8_t alternateSettingNumber; /*!< The interface alternate setting value*/ + uint8_t epCount; /*!< Interface's endpoint number*/ +} usb_host_interface_t; + +/*! @brief USB host configuration information structure */ +typedef struct _usb_host_configuration +{ + usb_host_interface_t interfaceList[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interface array*/ + usb_descriptor_configuration_t *configurationDesc; /*!< Configuration descriptor pointer*/ + uint8_t *configurationExtension; /*!< Configuration extended descriptor pointer*/ + uint16_t configurationExtensionLength; /*!< Extended descriptor length*/ + uint8_t interfaceCount; /*!< The configuration's interface number*/ +} usb_host_configuration_t; + +/*! @brief USB host pipe common structure */ +typedef struct _usb_host_pipe +{ + struct _usb_host_pipe *next; /*!< Link the idle pipes*/ + usb_device_handle deviceHandle; /*!< This pipe's device's handle*/ + uint16_t currentCount; /*!< For KHCI transfer*/ + uint16_t nakCount; /*!< Maximum NAK count*/ + uint16_t maxPacketSize; /*!< Maximum packet size*/ + uint16_t interval; /*!< FS/LS: frame unit; HS: micro-frame unit*/ + uint8_t open; /*!< 0 - closed, 1 - open*/ + uint8_t nextdata01; /*!< Data toggle*/ + uint8_t endpointAddress; /*!< Endpoint address*/ + uint8_t direction; /*!< Pipe direction*/ + uint8_t pipeType; /*!< Pipe type, for example USB_ENDPOINT_BULK*/ + uint8_t numberPerUframe; /*!< Transaction number per micro-frame*/ +} usb_host_pipe_t; + +/*! @brief USB host transfer structure */ +typedef struct _usb_host_transfer +{ + struct _usb_host_transfer *next; /*!< The next transfer structure*/ + uint8_t *transferBuffer; /*!< Transfer data buffer*/ + uint32_t transferLength; /*!< Transfer data length*/ + uint32_t transferSofar; /*!< Length transferred so far*/ + host_inner_transfer_callback_t callbackFn; /*!< Transfer callback function*/ + void *callbackParam; /*!< Transfer callback parameter*/ + usb_host_pipe_t *transferPipe; /*!< Transfer pipe pointer*/ + usb_setup_struct_t *setupPacket; /*!< Set up packet buffer*/ + uint8_t direction; /*!< Transfer direction; it's values are USB_OUT or USB_IN*/ + uint8_t setupStatus; /*!< Set up the transfer status*/ + union + { + uint32_t unitHead; /*!< xTD head for this transfer*/ + int32_t transferResult; /*!< KHCI transfer result */ + } union1; + + union + { + uint32_t unitTail; /*! 0U)) +/*! + * @brief Send a bus or device suspend request. + * + * This function is used to send a bus or device suspend request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! + * @brief Send a bus or device resume request. + * + * This function is used to send a bus or device resume request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle); +#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U)) +/*! + * @brief Send a bus or device suspend request. + * + * This function is used to send a bus or device suspend request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + *@param[in] sleeptype Bus suspend or single device suspend. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleeptype); + +/*! + * @brief Send a bus or device resume request. + * + * This function is used to send a bus or device resume request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + * *@param[in] sleeptype Bus suspend or single device suspend. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleepType); +/*! + * @brief Update the lpm param. + * + * The function is used to configuure the lpm token. + * + * @param[in] hostHandle The host handle. + * @param[in] lpmParam HIRD vaule and whether enable remotewakeup. + * + */ +extern usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam); +#endif +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] hostHandle The host handle. + * @param[in] tick Current hardware tick(uint is ms). + * + */ +extern usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick); + +#endif + +/*! @}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _USB_HOST_H_ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_devices.c b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_devices.c new file mode 100644 index 0000000000000000000000000000000000000000..42b16e071ed3a27144f98a7fa2c01e1101a0b166 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_devices.c @@ -0,0 +1,1414 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "usb_host.h" +#include "usb_host_hci.h" +#include "usb_host_devices.h" + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) +#include "usb_host_hub.h" +#endif /* USB_HOST_CONFIG_HUB */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief enumeration transfer callback function. + * + * @param param callback parameter. + * @param transfer the transfer. + * @param status transfer result status. + */ +static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status); + +/*! + * @brief process the new step state. + * + * @param deviceInstance device instance pointer. + * + * @return kStatus_USB_Success or error codes + */ +static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInstance); + +/*! + * @brief process the previous step transfer result. + * + * @param deviceInstance device instance pointer. + * + * @return kStatus_USB_Success or error codes + */ +static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance); + +/*! + * @brief notify the application event, the callback is registered when initializing host. + * + * @param deviceInstance device instance pointer. + * @param eventCode event code. + * + * @return kStatus_USB_Success or error codes + */ +static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode); + +/*! + * @brief allocate one address. + * + * @param hostInstance host instance pointer. + * + * @return address, 0 is invalid. + */ +static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance); + +/*! + * @brief release one address. + * + * @param hostInstance host instance pointer. + * @param address releasing address. + */ +static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address); + +/*! + * @brief release device resource. + * + * @param hostInstance host instance pointer. + * @param deviceInstance device instance pointer. + */ +static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, + usb_host_device_instance_t *deviceInstance); + +/*! + * @brief parse device configuration descriptor. + * + * @param deviceHandle device handle. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle deviceHandle); + +/*! + * @brief remove device instance from host device list. + * + * @param hostHandle host instance handle. + * @param deviceHandle device handle. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! + * @brief control the bus. + * + * This function control the host bus. + * + * @param[in] hostHandle the host handle. + * @param[in] controlType the control code, please reference to bus_event_t. + * + * @retval kStatus_USB_Success control successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. + */ +static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType); + +extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + void *param); +extern usb_status_t USB_HostStandardSetAddress(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + void *param); +extern usb_status_t USB_HostCh9RequestCommon(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + uint8_t *buffer, + uint32_t bufferLen); + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + +extern usb_status_t USB_HostHubDeviceEvent(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + usb_host_configuration_handle configurationHandle, + uint32_t eventCode); + +extern uint32_t USB_HostHubGetHsHubNumber(usb_host_handle hostHandle, uint8_t parentHubNo); + +extern uint32_t USB_HostHubGetHsHubPort(usb_host_handle hostHandle, uint8_t parentHubNo, uint8_t parentPortNo); + +extern usb_status_t USB_HostHubRemovePort(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber); + +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +extern usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST]; + +/*! @brief enumeration step process array */ +static const usb_host_enum_process_entry_t s_EnumEntries[] = \ +{ + /* kStatus_dev_initial */ + { + 0, 0, NULL, + }, + /* kStatus_DEV_GetDes8 */ + { + kStatus_DEV_SetAddress, kStatus_DEV_GetDes8, USB_HostProcessCallback, + }, + /* kStatus_DEV_SetAddress */ + { + kStatus_DEV_GetDes, kStatus_DEV_SetAddress, USB_HostProcessCallback, + }, + /* kStatus_DEV_GetDes */ + { + kStatus_DEV_GetCfg9, kStatus_DEV_GetDes, NULL, + }, + /* kStatus_DEV_GetCfg9 */ + { + kStatus_DEV_GetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback, + }, + /* kStatus_DEV_GetCfg */ + { + kStatus_DEV_SetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback, + }, + /* kStatus_DEV_SetCfg */ + { + kStatus_DEV_EnumDone, kStatus_DEV_SetCfg, NULL, + }, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) +{ + uint8_t nextStep = 0; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)param; + + USB_HostFreeTransfer(deviceInstance->hostHandle, transfer); /* free transfer */ + + if (status == kStatus_USB_Success) + { + nextStep = 1; + } + else if (status == kStatus_USB_TransferStall) + { +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + usb_echo("no response from device\r\n"); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ + if (deviceInstance->stallRetries > 0) /* retry same transfer when stall */ + { + deviceInstance->stallRetries--; + } + else /* process next state when all retries stall */ + { + nextStep = 1; + } + } + else if (status == kStatus_USB_TransferCancel) + { + return; + } + else + { + if (deviceInstance->enumRetries > 0) /* next whole retry */ + { + deviceInstance->enumRetries--; + deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + deviceInstance->configurationValue = 0; + deviceInstance->state = kStatus_DEV_GetDes8; + } + else + { +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + usb_echo("Device No Response\r\n"); +#endif + return; + } + } + + if (nextStep == 1) + { + deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + if (s_EnumEntries[deviceInstance->state - 1].process == NULL) + { + deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState; /* next state */ + } + else + { + status = s_EnumEntries[deviceInstance->state - 1].process( + deviceInstance); /* process the previous state result */ + if (status == kStatus_USB_Success) /* process success */ + { + deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState; + } + else if (status == kStatus_USB_Retry) /* need retry */ + { + deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].retryState; + } + else if (status == kStatus_USB_NotSupported) /* device don't suport by the application */ + { + return; /* unrecoverable fail */ + } + else /* process error, next retry */ + { + if (deviceInstance->enumRetries > 0) /* next whole retry */ + { + deviceInstance->enumRetries--; + deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + deviceInstance->configurationValue = 0; + deviceInstance->state = kStatus_DEV_GetDes8; + } + else + { +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + usb_echo("Device No Response\r\n"); +#endif + return; /* unrecoverable fail */ + } + } + } + } + + if (USB_HostProcessState(deviceInstance) != kStatus_USB_Success) /* process the new state */ + { +#ifdef HOST_ECHO + usb_echo("enumation setup error\r\n"); +#endif + return; + } +} + +static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInstance) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_process_descriptor_param_t getDescriptorParam; + usb_host_transfer_t *transfer; + + /* malloc transfer */ + if (deviceInstance->state != kStatus_DEV_EnumDone) + { + if (USB_HostMallocTransfer(deviceInstance->hostHandle, &transfer) != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("error to get transfer\r\n"); +#endif + return kStatus_USB_Error; + } + transfer->callbackFn = USB_HostEnumerationTransferCallback; + transfer->callbackParam = deviceInstance; + + /* reset transfer fields */ + transfer->setupPacket->bmRequestType = 0x00; + transfer->setupPacket->wIndex = 0; + transfer->setupPacket->wLength = 0; + transfer->setupPacket->wValue = 0; + } + + switch (deviceInstance->state) + { + case kStatus_DEV_GetDes8: + case kStatus_DEV_GetDes: /* get descriptor state */ + getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t); + if (deviceInstance->state == kStatus_DEV_GetDes8) + { + getDescriptorParam.descriptorLength = 8; + } + getDescriptorParam.descriptorBuffer = (uint8_t *)deviceInstance->deviceDescriptor; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE; + getDescriptorParam.descriptorIndex = 0; + getDescriptorParam.languageId = 0; + + transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); + break; + case kStatus_DEV_SetAddress: /* set address state */ + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_ADDRESS; + status = USB_HostStandardSetAddress(deviceInstance, transfer, &deviceInstance->allocatedAddress); + break; + + case kStatus_DEV_GetCfg9: /* get 9 bytes configuration state */ + getDescriptorParam.descriptorBuffer = deviceInstance->enumBuffer; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; + getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; + getDescriptorParam.descriptorLength = 9; + getDescriptorParam.languageId = 0; + + transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); + break; + + case kStatus_DEV_GetCfg: /* get configuration state */ + getDescriptorParam.descriptorBuffer = deviceInstance->configurationDesc; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; + getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; + getDescriptorParam.descriptorLength = deviceInstance->configurationLen; + getDescriptorParam.languageId = 0; + + transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); + break; + + case kStatus_DEV_SetCfg: /* set configuration state */ + transfer->setupPacket->wValue = + USB_SHORT_TO_LITTLE_ENDIAN(deviceInstance->configuration.configurationDesc->bConfigurationValue); + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_CONFIGURATION; + status = USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0); + break; + + case kStatus_DEV_EnumDone: /* enumeration done state */ + status = USB_HostNotifyDevice(deviceInstance, + kUSB_HostEventEnumerationDone); /* notify device enumeration done */ + if (status == kStatus_USB_Success) + { + deviceInstance->state = kStatus_DEV_AppUsed; + } + break; + + default: + break; + } + + return status; +} + +static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance) +{ + usb_host_pipe_t *pipe = (usb_host_pipe_t *)deviceInstance->controlPipe; + usb_status_t status = kStatus_USB_Success; + usb_descriptor_configuration_t *configureDesc; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + + switch (deviceInstance->state) + { + case kStatus_DEV_GetDes8: /* process get 8 bytes descriptor result */ + pipe->maxPacketSize = deviceInstance->deviceDescriptor->bMaxPacketSize0; + hostInstance->controllerTable->controllerIoctl( + hostInstance->controllerHandle, kUSB_HostUpdateControlPacketSize, deviceInstance->controlPipe); + break; + + case kStatus_DEV_SetAddress: /* process set address result */ + deviceInstance->setAddress = deviceInstance->allocatedAddress; + hostInstance->controllerTable->controllerIoctl( + hostInstance->controllerHandle, kUSB_HostUpdateControlEndpointAddress, deviceInstance->controlPipe); + break; + + case kStatus_DEV_GetDes: /* process set address result */ + /* NULL */ + break; + + case kStatus_DEV_GetCfg9: /* process get 9 bytes configuration result */ + configureDesc = (usb_descriptor_configuration_t *)&deviceInstance->enumBuffer[0]; + + deviceInstance->configurationLen = USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(configureDesc->wTotalLength); + if (deviceInstance->configurationDesc != NULL) + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(deviceInstance->configurationDesc); +#else + USB_OsaMemoryFree(deviceInstance->configurationDesc); +#endif + deviceInstance->configurationDesc = NULL; + } + /* for KHCI, the start address and the length should be 4 byte align */ + if ((deviceInstance->configurationLen & 0x03) != 0) + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + deviceInstance->configurationDesc = + (uint8_t *)SDK_Malloc((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4, USB_CACHE_LINESIZE); +#else + deviceInstance->configurationDesc = + (uint8_t *)USB_OsaMemoryAllocate((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4); +#endif + } + else + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + deviceInstance->configurationDesc = + (uint8_t *)SDK_Malloc(deviceInstance->configurationLen, USB_CACHE_LINESIZE); +#else + deviceInstance->configurationDesc = (uint8_t *)USB_OsaMemoryAllocate(deviceInstance->configurationLen); +#endif + } + if (deviceInstance->configurationDesc == NULL) + { + return kStatus_USB_Error; + } + break; + + case kStatus_DEV_GetCfg: /* process get cofiguration result */ + if (((usb_descriptor_configuration_t *)deviceInstance->configurationDesc)->bMaxPower > + USB_HOST_CONFIG_MAX_POWER) + { + return kStatus_USB_Error; + } + deviceInstance->configurationValue++; + if (USB_HostParseDeviceConfigurationDescriptor(deviceInstance) != + kStatus_USB_Success) /* parse configuration descriptor */ + { + return kStatus_USB_Error; + } + + status = USB_HostNotifyDevice(deviceInstance, kUSB_HostEventAttach); + + if (status != kStatus_USB_Success) + { + /* next configuration */ + if (deviceInstance->configurationValue < deviceInstance->deviceDescriptor->bNumConfigurations) + { + return kStatus_USB_Retry; + } + else + { + USB_HostNotifyDevice(deviceInstance, + kUSB_HostEventNotSupported); /* notify application device is not supported */ + return kStatus_USB_NotSupported; + } + } + break; + + case kStatus_DEV_SetCfg: + /* NULL */ + break; + + default: + break; + } + + return status; +} + +static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode) +{ + usb_host_instance_t *hostInstance; + usb_status_t status1 = kStatus_USB_Error; +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + usb_status_t status2 = kStatus_USB_Error; + uint8_t haveHub; + uint8_t haveNoHub; + uint8_t interfaceIndex; +#endif /* USB_HOST_CONFIG_HUB */ + + if (deviceInstance == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + haveHub = 0; + haveNoHub = 0; + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (((usb_descriptor_interface_t *)deviceInstance->configuration.interfaceList[interfaceIndex].interfaceDesc) + ->bInterfaceClass == USB_HOST_HUB_CLASS_CODE) + { + haveHub = 1; + } + else + { + haveNoHub = 1; + } + } + + if ((haveNoHub == 1) && (hostInstance->deviceCallback != NULL)) + { + status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, + eventCode); /* notify application event */ + } + if (haveHub) + { + status2 = USB_HostHubDeviceEvent(hostInstance, deviceInstance, &deviceInstance->configuration, + eventCode); /* notify hub event */ + } + + if ((status1 == kStatus_USB_Success) || (status2 == kStatus_USB_Success)) /* the device is supported */ + { + return kStatus_USB_Success; + } + else if (eventCode == kUSB_HostEventAttach) /* attach event */ + { + status1 = kStatus_USB_NotSupported; + } + else + { + status1 = kStatus_USB_Error; + } +#else + if (hostInstance->deviceCallback != NULL) + { + status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, + eventCode); /* call host callback function */ + } +#endif + return status1; +} + +static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance) +{ + uint8_t address = 0; + uint8_t addressIndex; + uint8_t addressBitIndex; + for (addressIndex = 0; addressIndex < 8; ++addressIndex) /* find the idle address postion byte */ + { + if (hostInstance->addressBitMap[addressIndex] != 0xFF) + { + break; + } + } + if (addressIndex < 8) + { + for (addressBitIndex = 0; addressBitIndex < 8; ++addressBitIndex) /* find the idle address position bit */ + { + if (!(hostInstance->addressBitMap[addressIndex] & (0x01u << addressBitIndex))) + { + hostInstance->addressBitMap[addressIndex] |= (0x01u << addressBitIndex); /* set the allocated bit */ + address = addressIndex * 8 + addressBitIndex + 1; /* the address minimum is 1 */ + break; + } + } + } + return address; +} + +static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address) +{ + USB_HostLock(); + hostInstance->addressBitMap[(uint32_t)(address - 1) >> 3] &= + (~(0x01u << (((uint32_t)address - 1) & 0x07U))); /* reset the allocated bit */ + USB_HostUnlock(); +} + +static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *currentInstance; + usb_host_device_instance_t *prevInstance; + if ((hostHandle == NULL) || (deviceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* search and remove device instance */ + prevInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + if (prevInstance == deviceHandle) + { + hostInstance->deviceList = prevInstance->next; + return kStatus_USB_Success; + } + else + { + currentInstance = prevInstance->next; + } + + while (currentInstance != NULL) + { + if (currentInstance == deviceHandle) + { + prevInstance->next = currentInstance->next; + return kStatus_USB_Success; + } + prevInstance = currentInstance; + currentInstance = currentInstance->next; + } + + return kStatus_USB_Success; +} + +static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, usb_host_device_instance_t *deviceInstance) +{ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + uint8_t level = 0; +#endif + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + if (deviceInstance == hostInstance->suspendedDevice) + { + hostInstance->suspendedDevice = NULL; + } +#endif + /* release device's address */ + if (deviceInstance->setAddress != 0) + { + USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->setAddress); + } + else + { + if (deviceInstance->allocatedAddress != 0) + { + USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->allocatedAddress); + } + } + + /* close control pipe */ + if (deviceInstance->controlPipe != NULL) + { + USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); + if (USB_HostClosePipe(hostInstance, deviceInstance->controlPipe) != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("error when close pipe\r\n"); +#endif + } + deviceInstance->controlPipe = NULL; + } + + /* free configuration buffer */ + if (deviceInstance->configurationDesc != NULL) + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(deviceInstance->configurationDesc); +#else + USB_OsaMemoryFree(deviceInstance->configurationDesc); +#endif + } + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + level = deviceInstance->level; +#endif +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(deviceInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(deviceInstance->deviceDescriptor); +#endif + /* free device instance buffer */ + USB_OsaMemoryFree(deviceInstance); + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + /* enable controller attach if root hub */ + if (level == 1) + { + USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach); + } +#else + /* enable controller attach */ + USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach); +#endif +} + +static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle deviceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + uint32_t endPos; + usb_descriptor_union_t *unionDes; + usb_host_interface_t *interfaceParse = NULL; + usb_host_ep_t *epParse; + uint8_t *buffer; + + if (deviceHandle == NULL) + { + return kStatus_USB_InvalidParameter; + } + + buffer = (uint8_t *)&deviceInstance->configuration; + /* clear the previous parse result, note: end_pos means buffer index here*/ + for (endPos = 0; endPos < sizeof(usb_host_configuration_t); endPos++) + { + buffer[endPos] = 0; + } + for (endPos = 0; endPos < USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE; ++endPos) + { + deviceInstance->interfaceStatus[endPos] = 0; + } + + /* parse configuration descriptor */ + unionDes = (usb_descriptor_union_t *)deviceInstance->configurationDesc; + endPos = (uint32_t)(deviceInstance->configurationDesc + deviceInstance->configurationLen); + + if ((unionDes->common.bLength == USB_DESCRIPTOR_LENGTH_CONFIGURE) && + (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_CONFIGURE)) + { + /* configuration descriptor */ + deviceInstance->configuration.configurationDesc = (usb_descriptor_configuration_t *)unionDes; + deviceInstance->configuration.configurationExtensionLength = 0; + deviceInstance->configuration.configurationExtension = NULL; + deviceInstance->configuration.interfaceCount = 0; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) + { + if (deviceInstance->configuration.configurationExtension == NULL) + { + deviceInstance->configuration.configurationExtension = (uint8_t *)unionDes; + } + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + deviceInstance->configuration.configurationExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + + /* interface descriptor */ + deviceInstance->configuration.interfaceCount = 0; + while ((uint32_t)unionDes < endPos) + { + if (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE) + { + if (unionDes->interface.bAlternateSetting == 0x00) + { + if (deviceInstance->configuration.interfaceCount >= USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE) + { +#ifdef HOST_ECHO + usb_echo( + "Unsupported Device attached\r\n too many interfaces in one configuration, please increase " + "the USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE value\n"); +#endif + return kStatus_USB_Error; + } + interfaceParse = + &deviceInstance->configuration.interfaceList[deviceInstance->configuration.interfaceCount]; + deviceInstance->configuration.interfaceCount++; + interfaceParse->alternateSettingNumber = 0; + interfaceParse->epCount = 0; + interfaceParse->interfaceDesc = &unionDes->interface; + interfaceParse->interfaceExtensionLength = 0; + interfaceParse->interfaceExtension = NULL; + interfaceParse->interfaceIndex = unionDes->interface.bInterfaceNumber; + if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { + if (interfaceParse->interfaceExtension == NULL) + { + interfaceParse->interfaceExtension = (uint8_t *)unionDes; + } + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + interfaceParse->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + + /* endpoint descriptor */ + if (interfaceParse->interfaceDesc->bNumEndpoints != 0) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) || + (interfaceParse->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP)) + { +#ifdef HOST_ECHO + usb_echo("interface descriptor error\n"); +#endif + return kStatus_USB_Error; + } + for (; interfaceParse->epCount < interfaceParse->interfaceDesc->bNumEndpoints; + (interfaceParse->epCount)++) + { + if (((uint32_t)unionDes >= endPos) || + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { +#ifdef HOST_ECHO + usb_echo("endpoint descriptor error\n"); +#endif + return kStatus_USB_Error; + } + epParse = (usb_host_ep_t *)&interfaceParse->epList[interfaceParse->epCount]; + epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes; + epParse->epExtensionLength = 0; + epParse->epExtension = NULL; + if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)) + { + if (epParse->epExtension == NULL) + { + epParse->epExtension = (uint8_t *)unionDes; + } + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + epParse->epExtensionLength += unionDes->common.bLength; + unionDes = + (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + } + } + } + else + { + if (interfaceParse == NULL) + { + return kStatus_USB_Error; /* in normal situation this cannot reach */ + } + interfaceParse->alternateSettingNumber++; + if (interfaceParse->interfaceExtension == NULL) + { + interfaceParse->interfaceExtension = (uint8_t *)unionDes; + } + if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + interfaceParse->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) + { + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + interfaceParse->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + } + } + else + { + return kStatus_USB_Error; + } + } + } + + for (endPos = 0; endPos < deviceInstance->configuration.interfaceCount; ++endPos) + { + deviceInstance->interfaceStatus[endPos] = kStatus_interface_Attached; + } + + return kStatus_USB_Success; +} + +usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle, + uint8_t speed, + uint8_t hubNumber, + uint8_t portNumber, + uint8_t level, + usb_device_handle *deviceHandle) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *newInstance; +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + usb_host_device_instance_t *currentInstance; +#endif + uint8_t address; + usb_host_pipe_init_t pipeInit; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + +/* check whether is the device attached? */ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + currentInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + while (currentInstance != NULL) + { + if ((currentInstance->hubNumber == hubNumber) && (currentInstance->portNumber == portNumber)) + { + *deviceHandle = NULL; +#ifdef HOST_ECHO + usb_echo("device has attached\r\n"); +#endif + return kStatus_USB_Busy; + } + else + { + currentInstance = currentInstance->next; + } + } +#else + if (hostInstance->deviceList != NULL) + { + *deviceHandle = NULL; + usb_echo("device has attached\r\n"); + return kStatus_USB_Busy; + } +#endif + + /* Allocate new device instance */ + newInstance = (usb_host_device_instance_t *)USB_OsaMemoryAllocate(sizeof(usb_host_device_instance_t)); + if (newInstance == NULL) + { +#ifdef HOST_ECHO + usb_echo("allocate dev instance fail\r\n"); +#endif + return kStatus_USB_AllocFail; + } + + /* new instance fields init */ + newInstance->hostHandle = hostHandle; + newInstance->speed = speed; + newInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + newInstance->enumRetries = USB_HOST_CONFIG_ENUMERATION_MAX_RETRIES; + newInstance->setAddress = 0; + newInstance->deviceAttachState = kStatus_device_Attached; +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + newInstance->deviceDescriptor = + (usb_descriptor_device_t *)SDK_Malloc(sizeof(usb_descriptor_device_t) + 9, USB_CACHE_LINESIZE); +#else + newInstance->deviceDescriptor = + (usb_descriptor_device_t *)USB_OsaMemoryAllocate(sizeof(usb_descriptor_device_t) + 9); +#endif + if (newInstance->deviceDescriptor == NULL) + { +#ifdef HOST_ECHO + usb_echo("allocate newInstance->deviceDescriptor fail\r\n"); +#endif +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(newInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(newInstance->deviceDescriptor); +#endif + USB_OsaMemoryFree(newInstance); + return kStatus_USB_AllocFail; + } + newInstance->enumBuffer = (uint8_t *)((uint8_t *)newInstance->deviceDescriptor + sizeof(usb_descriptor_device_t)); +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + newInstance->hubNumber = hubNumber; + newInstance->portNumber = portNumber; + newInstance->level = level; + + if ((speed != USB_SPEED_HIGH) && (level > 1)) + { + newInstance->hsHubNumber = USB_HostHubGetHsHubNumber(hostHandle, hubNumber); + newInstance->hsHubPort = USB_HostHubGetHsHubPort(hostHandle, hubNumber, portNumber); + } + else + { + newInstance->hsHubNumber = hubNumber; + newInstance->hsHubPort = portNumber; + } +#endif /* USB_HOST_CONFIG_HUB */ + + USB_HostLock(); + /* allocate address && insert to the dev list */ + address = USB_HostAllocateDeviceAddress(hostInstance); + if (address == 0) + { +#ifdef HOST_ECHO + usb_echo("allocate address fail\r\n"); +#endif + USB_HostUnlock(); +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(newInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(newInstance->deviceDescriptor); +#endif + USB_OsaMemoryFree(newInstance); + return kStatus_USB_Error; + } + newInstance->allocatedAddress = address; + + newInstance->next = (usb_host_device_instance_t *)hostInstance->deviceList; + hostInstance->deviceList = newInstance; + newInstance->state = kStatus_DEV_Initial; + USB_HostUnlock(); + + /* open control pipe */ + pipeInit.devInstance = newInstance; + pipeInit.pipeType = USB_ENDPOINT_CONTROL; + pipeInit.direction = 0; + pipeInit.endpointAddress = 0; + pipeInit.interval = 0; + pipeInit.maxPacketSize = 8; + pipeInit.numberPerUframe = 0; + pipeInit.nakCount = USB_HOST_CONFIG_MAX_NAK; + if (USB_HostOpenPipe(hostHandle, &newInstance->controlPipe, &pipeInit) != kStatus_USB_Success) + { + /* don't need release resource, resource is released when detach */ + *deviceHandle = newInstance; +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(newInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(newInstance->deviceDescriptor); +#endif + USB_OsaMemoryFree(newInstance); + return kStatus_USB_Error; + } + + /* start enumeration */ + newInstance->state = kStatus_DEV_GetDes8; + USB_HostProcessState(newInstance); /* process enumeration state machine */ + + *deviceHandle = newInstance; + return kStatus_USB_Success; +} + +usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber) +{ + usb_host_device_instance_t *deviceInstance; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + USB_HostLock(); +/* search for device instance handle */ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + while (deviceInstance != NULL) + { + if ((deviceInstance->hubNumber == hubNumber) && (deviceInstance->portNumber == portNumber)) + { + break; + } + deviceInstance = deviceInstance->next; + } +#else + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; +#endif + USB_HostUnlock(); + if (deviceInstance != NULL) + { + return USB_HostDetachDeviceInternal(hostHandle, deviceInstance); /* device instance detach */ + } + return kStatus_USB_Success; +} + +usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + if ((hostHandle == NULL) || (deviceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + deviceInstance->deviceAttachState = kStatus_device_Detached; /* mark the device is detached from host */ + + if (deviceInstance->state >= kStatus_DEV_Initial) /* device instance is valid */ + { + /* detach internally */ + if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeration is not done */ + { + if (deviceInstance->controlPipe != NULL) + { + USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); + } + + /* remove device instance from host */ + USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); + USB_HostReleaseDeviceResource(hostInstance, deviceInstance); + } + else /* enumeration has be done and notifed application */ + { + USB_HostNotifyDevice(deviceInstance, kUSB_HostEventDetach); /* notify application device detach */ + } + } + + return kStatus_USB_Success; +} + +uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle) +{ + return deviceHandle ? ((usb_host_device_instance_t *)deviceHandle)->deviceAttachState : 0x0; +} + +usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_device_instance_t *searchDev; + + if (deviceHandle == NULL) + { + return kStatus_USB_InvalidParameter; + } + /* search for the device */ + searchDev = (usb_host_device_instance_t *)((usb_host_instance_t *)hostHandle)->deviceList; + while ((searchDev != NULL) && ((usb_device_handle)searchDev != deviceHandle)) + { + searchDev = searchDev->next; + } + + if (searchDev) + { + return kStatus_USB_Success; + } + return kStatus_USB_Error; +} + +static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, + &controlType); + + return status; +} + +usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = NULL; + uint8_t interfaceIndex; + uint8_t index = 0; + + if ((deviceHandle == NULL) || (interfaceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + USB_HostLock(); + /* check host_instance valid? */ + for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) + { + if ((g_UsbHostInstance[index].occupied == 1) && + ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) + { + break; + } + } + if (index >= USB_HOST_CONFIG_MAX_HOST) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + /* check deviceHandle valid? */ + if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + /* search interface and set the interface as opened */ + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) + { + deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Opened; + break; + } + } + USB_HostUnlock(); + + return kStatus_USB_Success; +} + +usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = NULL; + uint8_t interfaceIndex; + uint8_t removeLabel = 1; + uint8_t index = 0; + + if (deviceHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + USB_HostLock(); + /* check host_instance valid? */ + for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) + { + if ((g_UsbHostInstance[index].occupied == 1) && + ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) + { + break; + } + } + if (index >= USB_HOST_CONFIG_MAX_HOST) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + /* check deviceHandle valid? */ + if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + if (interfaceHandle != NULL) + { + /* search interface and set the interface as detached */ + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) + { + deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Detached; + break; + } + } + } + + if (deviceInstance->deviceAttachState == kStatus_device_Detached) /* device is removed from host */ + { + removeLabel = 1; + /* check all the interfaces of the device are not opened */ + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened) + { + removeLabel = 0; + break; + } + } + if (removeLabel == 1) + { + /* remove device instance from host */ + USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); + } + USB_HostUnlock(); + + if (removeLabel == 1) + { + USB_HostReleaseDeviceResource((usb_host_instance_t *)deviceInstance->hostHandle, + deviceInstance); /* release device resource */ + } + } + else + { + USB_HostUnlock(); + } + + return kStatus_USB_Success; +} + +usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + uint8_t interfaceIndex = 0; +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + uint8_t level = 0; + uint8_t devHubNo; + uint8_t devPortNo; +#endif + + if ((hostHandle == NULL) || (deviceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + if (deviceInstance->hostHandle != hostHandle) + { + return kStatus_USB_InvalidParameter; + } + + if (USB_HostValidateDevice(hostInstance, deviceInstance) == kStatus_USB_Success) /* device is valid */ + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + devHubNo = deviceInstance->hubNumber; + devPortNo = deviceInstance->portNumber; + level = deviceInstance->level; +#endif + + deviceInstance->deviceAttachState = kStatus_device_Detached; + if (deviceInstance->state >= kStatus_DEV_Initial) /* device is valid */ + { + if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeraion is not done or application don't use */ + { + /* detach internally */ + USB_HostDetachDeviceInternal(hostHandle, deviceHandle); + } + else /* application use the device */ + { + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; + ++interfaceIndex) + { + if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened) + { +#ifdef HOST_ECHO + usb_echo("error: there is class instance that is not deinited\r\n"); +#endif + break; + } + } + /* remove device instance from host */ + USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); + USB_HostReleaseDeviceResource(hostInstance, deviceInstance); /* release resource */ + } + } + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + if (level == 1) + { + USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */ + USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */ + } + else + { + USB_HostHubRemovePort(hostHandle, devHubNo, devPortNo); /* reset hub port */ + } +#else + USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */ + USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */ +#endif /* USB_HOST_CONFIG_HUB */ + } + + return kStatus_USB_Success; +} diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_devices.h b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_devices.h new file mode 100644 index 0000000000000000000000000000000000000000..422e876a1229f15a87ddb896d15630cd06a0860f --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_devices.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_DEV_MNG_H_ +#define _USB_HOST_DEV_MNG_H_ + +#include "usb_host.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @addtogroup usb_host_drv + * @{ + */ +/*! @brief States of device instances enumeration */ +typedef enum _usb_host_device_enumeration_status +{ + kStatus_DEV_Notinit = 0, /*!< Device is invalid */ + kStatus_DEV_Initial, /*!< Device has been processed by host driver */ + kStatus_DEV_GetDes8, /*!< Enumeration process: get 8 bytes' device descriptor */ + kStatus_DEV_SetAddress, /*!< Enumeration process: set device address */ + kStatus_DEV_GetDes, /*!< Enumeration process: get device descriptor */ + kStatus_DEV_GetCfg9, /*!< Enumeration process: get 9 bytes' configuration descriptor */ + kStatus_DEV_GetCfg, /*!< Enumeration process: get configuration descriptor */ + kStatus_DEV_SetCfg, /*!< Enumeration process: set configuration */ + kStatus_DEV_EnumDone, /*!< Enumeration is done */ + kStatus_DEV_AppUsed, /*!< This device has been used by application */ +} usb_host_device_enumeration_status_t; + +/*! @brief States of device's interface */ +typedef enum _usb_host_interface_state +{ + kStatus_interface_Attached = 1, /*!< Interface's default status */ + kStatus_interface_Opened, /*!< Interface is used by application */ + kStatus_interface_Detached, /*!< Interface is not used by application */ +} usb_host_interface_state_t; + +/*! @brief States of device */ +typedef enum _usb_host_device_state +{ + kStatus_device_Detached = 0, /*!< Device is used by application */ + kStatus_device_Attached, /*!< Device's default status */ +} usb_host_device_state_t; + +/*! @brief Device instance */ +typedef struct _usb_host_device_instance +{ + struct _usb_host_device_instance *next; /*!< Next device, or NULL */ + usb_host_handle hostHandle; /*!< Host handle */ + usb_host_configuration_t configuration; /*!< Parsed configuration information for the device */ + usb_descriptor_device_t *deviceDescriptor; /*!< Standard device descriptor */ + usb_host_pipe_handle controlPipe; /*!< Device's control pipe */ + uint8_t *configurationDesc; /*!< Configuration descriptor pointer */ + uint16_t configurationLen; /*!< Configuration descriptor length */ + uint16_t configurationValue; /*!< Configuration index */ + uint8_t interfaceStatus[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interfaces' status, please reference to + #usb_host_interface_state_t */ + uint8_t *enumBuffer; /*!< Buffer for enumeration */ + uint8_t state; /*!< Device state for enumeration */ + uint8_t enumRetries; /*!< Re-enumeration when error in control transfer */ + uint8_t stallRetries; /*!< Re-transfer when stall */ + uint8_t speed; /*!< Device speed */ + uint8_t allocatedAddress; /*!< Temporary address for the device. When set address request succeeds, setAddress is + a value, 1 - 127 */ + uint8_t setAddress; /*!< The address has been set to the device successfully, 1 - 127 */ + uint8_t deviceAttachState; /*!< See the usb_host_device_state_t */ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + /* hub related */ + uint8_t hubNumber; /*!< Device's first connected hub address (root hub = 0) */ + uint8_t portNumber; /*!< Device's first connected hub's port no (1 - 8) */ + uint8_t hsHubNumber; /*!< Device's first connected high-speed hub's address (1 - 8) */ + uint8_t hsHubPort; /*!< Device's first connected high-speed hub's port no (1 - 8) */ + uint8_t level; /*!< Device's level (root device = 0) */ +#endif +} usb_host_device_instance_t; + +typedef struct _usb_host_enum_process_entry +{ + uint8_t successState; /*!< When the last step is successful, the next state value */ + uint8_t retryState; /*!< When the last step need retry, the next state value */ + usb_status_t (*process)(usb_host_device_instance_t *deviceInstance); /*!< When the last step transfer is done, the + function is used to process the transfer + data */ +} usb_host_enum_process_entry_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Calls this function when device attach. + * + * @param hostHandle Host instance handle. + * @param speed Device speed. + * @param hubNumber Device hub no. root device's hub no. is 0. + * @param portNumber Device port no. root device's port no. is 0. + * @param level Device level. root device's level is 1. + * @param deviceHandle Return device handle. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle, + uint8_t speed, + uint8_t hubNumber, + uint8_t portNumber, + uint8_t level, + usb_device_handle *deviceHandle); + +/*! + * @brief Call this function when device detaches. + * + * @param hostHandle Host instance handle. + * @param hubNumber Device hub no. root device's hub no. is 0. + * @param portNumber Device port no. root device's port no. is 0. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber); + +/*! + * @brief Call this function when device detaches. + * + * @param hostHandle Host instance handle. + * @param deviceHandle Device handle. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! + * @brief Gets the device attach/detach state. + * + * @param deviceHandle Device handle. + * + * @return 0x01 - attached; 0x00 - detached. + */ +extern uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle); + +/*! + * @brief Determine whether the device is attached. + * + * @param hostHandle Host instance pointer. + * @param deviceHandle Device handle. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! @}*/ +#endif /* _USB_HOST_DEV_MNG_H_ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_ehci.c b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_ehci.c new file mode 100644 index 0000000000000000000000000000000000000000..8a31514b3ab7e42f90f93b5f293fb7fbce72e2b0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_ehci.c @@ -0,0 +1,4747 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI > 0U)) +#include "usb_host.h" +#include "usb_host_hci.h" +#include "usb_host_devices.h" +#include "fsl_device_registers.h" +#include "usb_host_ehci.h" +#include "usb_phy.h" +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +#include "usb_host.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U) + +#error The SOC does not suppoort dedicated RAM case. + +#endif + +#define USB_HOST_EHCI_BANDWIDTH_DELAY (3500U) +#define USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP (333U) +#define USB_HOST_EHCI_BANDWIDTH_FRAME_TOTOAL_TIME (900U) + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +#define USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH (18U) +#define USB_HOST_EHCI_PORTSC_PTC_J_STATE (0x01U) +#define USB_HOST_EHCI_PORTSC_PTC_K_STATE (0x02U) +#define USB_HOST_EHCI_PORTSC_PTC_SE0_NAK (0x03U) +#define USB_HOST_EHCI_PORTSC_PTC_PACKET (0x04U) +#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_HS (0x05U) +#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_FS (0x06U) +#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_LS (0x07U) +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief compute data bandwidth time. + * + * @param speed data speed. + * @param pipeType data type. + * @param direction data direction. + * @param dataLength data length. + * + *@return time value. + */ +static uint32_t USB_HostBandwidthComputeTime(uint8_t speed, uint8_t pipeType, uint8_t direction, uint32_t dataLength); + +/*! + * @brief compute current allocated bandwidth when ehci work as full-speed or low-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param frameIndex frame index. + * @param frameBandwidths return frame bandwidth data. + */ +static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint16_t *frameBandwidth); + +/*! + * @brief compute current hub's allocated FS/LS bandwidth when ehci work as hi-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param hubNumber hub address. + * @param frameIndex frame index. + * @param frameBandwidths return frame bandwidth data. + */ +static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance, + uint32_t hubNumber, + uint16_t frameIndex, + uint8_t frameBandwidths[8]); + +/*! + * @brief compute current allocated HS bandwidth when ehci work as hi-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param frameIndex frame index. + * @param frameBandwidths return frame bandwidth data. + */ +static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint8_t frameBandwidths[8]); + +/*! + * @brief allocate HS bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param uframeInterval micro-frame interval. + * @param timeData time for allocating. + * @param uframe_index_out return start uframe index. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instance_t *ehciInstance, + uint16_t uframeInterval, + uint16_t timeData, + uint16_t *uframeIndexOut); + +/*! + * @brief allocate HS interrupt bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief allocate bandwidth when host work as full-speed or low-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief get the 2 power value of uint8_t. + * + * @param value input uint8_t value. + */ +static uint8_t USB_HostEhciGet2PowerValue(uint8_t value); + +/*! + * @brief memory zero. + * + * @param buffer buffer pointer. + * @param length buffer length. + */ +static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length); + +/*! + * @brief host ehci delay. + * + * @param ehciIpBase ehci ip base address. + * @param ms millisecond. + */ +static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms); + +/*! + * @brief host ehci start async schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief host ehci stop async schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief host ehci start periodic schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief host ehci stop periodic schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStopPeriodic(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief initialize the qtd for one transfer. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + * + *@return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief release the qtd list. + * + * @param ehciInstance ehci instance pointer. + * @param ehciQtdStart qtd list start pointer. + * @param ehciQtdEnd qtd list end pointer. + * + *@return the transfer's length. + */ +static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_qtd_t *ehciQtdStart, + usb_host_ehci_qtd_t *ehciQtdEnd); + +/*! + * @brief de-initialize qh's linking qtd list. + * 1. remove qtd from qh; 2. remove transfer from qh; 3. release qtd; 4. transfer callback. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe. + * + *@return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief de-initialize transfer's linking qtd list. + * 1. stop this qh schedule; 2. remove qtd from qh; 3. remove transfer from qh; 4. release qtd; 5. transfer callback; 6. + *start this qh schedule. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + * + *@return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief initialize QH when opening one control, bulk or interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief de-initialize QH when closing one control, bulk or interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhDeinit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief add qh to one frame entry. + * + * @param ehciInstance ehci instance pointer. + * @param entryPointerValue entry pointer value. + * @param framePos frame index. + * @param uframeInterval micro-frame interval. + */ +static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos, + uint16_t uframeInterval); + +/*! + * @brief remove entry from frame list. + * + * @param ehciInstance ehci instance pointer. + * @param entryPointerValue entry pointer value. + * @param framePos frame index. + */ +static void USB_HostEhciRemoveFromFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos); + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) +/*! + * @brief add sitd array to the frame list. + * + * @param ehciInstance ehci instance pointer. + * @param entryPointerValue entry pointer value. + * @param startEntryPointer sitd entry pointer. + */ +static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + void *startEntryPointer); + +/*! + * @brief initialize sitd array for one transfer. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + */ +static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief release sitd list. + * + * @param ehciInstance ehci instance pointer. + * @param startSitdPointer start sitd pointer. + * @param endSitdPointer end sitd pointer. + * + * @return transfer's result length. + */ +static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_sitd_t *startSitdPointer, + usb_host_ehci_sitd_t *endSitdPointer); + +/*! + * @brief de-initialize sitd list. + * 1. remove transfer; 2. remove sitd from frame list and release sitd; 3. transfer callback + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); +#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) +/*! + * @brief compute the frame index when inserting itd. + * + * @param ehciInstance ehci instance pointer. + * @param lastLinkUframe last inserted micro-frame. + * @param startUframe start micro-frame. + * @param uframeInterval micro-frame interval. + * + * @return frame index + */ +static uint32_t USB_HostEhciGetItdLinkFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t lastLinkUframe, + uint16_t startUframe, + uint16_t uframeInterval); + +/*! + * @brief initialize itd list for one transfer. + * 1. initialize itd list; 2. insert itd to frame list. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief release itd list. + * + * @param ehciInstance ehci instance pointer. + * @param startItdPointer start itd pointer. + * @param endItdPointer end itd pointer. + * + * @return transfer's result length. + */ +static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_itd_t *startItdPointer, + usb_host_ehci_itd_t *endItdPointer); + +/*! + * @brief de-initialize itd list. + * 1. remove transfer; 2. remove itd from frame list and release itd; 3. transfer callback + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); +#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ + +/*! + * @brief open control or bulk pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciOpenControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief close control or bulk pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief open interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief close interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCloseInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) +/*! + * @brief open iso pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief close iso pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCloseIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief allocate HS iso bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +#endif + +/*! + * @brief reset ehci ip. + * + * @param ehciInstance ehci instance pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciResetIP(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief start ehci ip. + * + * @param ehciInstance ehci instance pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief cancel pipe's transfers. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer the canceling transfer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief control ehci bus. + * + * @param ehciInstance ehci instance pointer. + * @param bus_control control code. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl); + +/*! + * @brief ehci transaction done process function. + * + * @param ehciInstance ehci instance pointer. + */ +void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief ehci port change interrupt process function. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief ehci timer0 interrupt process function. + * cancel control/bulk transfer that time out. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance); + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief ehci timer1 interrupt process function. + * cancel control/bulk transfer that time out. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance); +#endif + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +/*! + * @brief suspend bus. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciSuspendBus(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief resume bus. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciResumeBus(usb_host_ehci_instance_t *ehciInstance); + +extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + void *param); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* EHCI controller driver instances. */ +#if (USB_HOST_CONFIG_EHCI == 1U) +USB_RAM_ADDRESS_ALIGNMENT(4096) +USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; + +#define USB_HOST_EHCI_FRAME_LIST_ARRAY \ + { \ + &s_UsbHostEhciFrameList1[0] \ + } + +USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1; +#define USB_HOST_EHCI_DATA_ARRAY \ + { \ + &s_UsbHostEhciData1 \ + } +#elif(USB_HOST_CONFIG_EHCI == 2U) +USB_RAM_ADDRESS_ALIGNMENT(4096) +USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; +USB_RAM_ADDRESS_ALIGNMENT(4096) +USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList2[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; +#define USB_HOST_EHCI_FRAME_LIST_ARRAY \ + { \ + &s_UsbHostEhciFrameList1[0], &s_UsbHostEhciFrameList2[0] \ + } + +USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1; +USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData2; +#define USB_HOST_EHCI_DATA_ARRAY \ + { \ + &s_UsbHostEhciData1, &s_UsbHostEhciData2 \ + } +#else +#error "Please increase the instance count." +#endif + +static uint8_t s_SlotMaxBandwidth[8] = {125, 125, 125, 125, 125, 125, 50, 0}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! +* @brief EHCI NC get USB NC bass address. +* +* This function is used to get USB NC bass address. +* +* @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. +* +* @retval USB NC bass address. +*/ +#if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +void *USB_EhciNCGetBase(uint8_t controllerId) +{ + void *usbNCBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbnc_base_temp[] = USBNC_BASE_ADDRS; + uint32_t usbnc_base[] = USBNC_BASE_ADDRS; + + if (controllerId < kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - kUSB_ControllerEhci0; + + for (instance = 0; instance < (sizeof(usbnc_base_temp) / sizeof(usbnc_base_temp[0])); instance++) + { + if (usbnc_base_temp[instance]) + { + usbnc_base[newinstance++] = usbnc_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + + usbNCBase = (void *)usbnc_base[controllerId]; +#endif + return usbNCBase; +} +#endif +#endif + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + +usb_status_t USB_HostEhciTestSetMode(usb_host_ehci_instance_t *ehciInstance, uint32_t testMode) +{ + uint32_t ehciPortSC; + + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + ehciPortSC &= ~((uint32_t)USBHS_PORTSC1_PTC_MASK); /* clear test mode bits */ + ehciPortSC |= (testMode << USBHS_PORTSC1_PTC_SHIFT); /* set test mode bits */ + ehciInstance->ehciIpBase->PORTSC1 = ehciPortSC; + return kStatus_USB_Success; +} + +static void USB_HostEhciTestSuspendResume(usb_host_ehci_instance_t *ehciInstance) +{ + uint8_t timeCount; + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + USB_HostEhciSuspendBus(ehciInstance); + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + USB_HostEhciResumeBus(ehciInstance); +} + +static void USB_HostEhciTestCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) +{ + USB_HostFreeTransfer(param, transfer); +} + +static void USB_HostEhciTestSingleStepGetDeviceDesc(usb_host_ehci_instance_t *ehciInstance, + usb_device_handle deviceHandle) +{ + usb_host_process_descriptor_param_t getDescriptorParam; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_transfer_t *transfer; + uint8_t timeCount; + + /* disable periodic shedule */ + USB_HostEhciStopPeriodic(ehciInstance); + + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + /* malloc one transfer */ + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("allocate transfer error\r\n"); +#endif + return; + } + + getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t); + getDescriptorParam.descriptorLength = 18; + getDescriptorParam.descriptorBuffer = (uint8_t *)&deviceInstance->deviceDescriptor; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE; + getDescriptorParam.descriptorIndex = 0; + getDescriptorParam.languageId = 0; + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + transfer->setupPacket->wIndex = 0; + transfer->setupPacket->wLength = 0; + transfer->setupPacket->wValue = 0; + USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); +} + +static usb_status_t USB_HostEhciSingleStepQtdListInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer, + uint8_t setupPhase) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_ehci_qtd_t *qtdPointer = NULL; + volatile uint32_t *entryPointer; + uint32_t qtdNumber; + uint32_t dataLength; + uint32_t dataAddress; + uint8_t index; + + /* compute the qtd number */ + qtdNumber = 1; + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* get qtd list */ + USB_HostEhciLock(); + if (qtdNumber <= ehciInstance->ehciQtdNumber) + { + ehciInstance->ehciQtdNumber -= qtdNumber; + qtdPointer = NULL; + do + { + if (qtdPointer != NULL) + { + qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead; + } + qtdPointer = ehciInstance->ehciQtdHead; + ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; + qtdPointer->nextQtdPointer = 0; + } while (--qtdNumber); + } + else + { + USB_HostEhciUnlock(); + return kStatus_USB_Error; + } + USB_HostEhciUnlock(); + + /* int qTD */ + if (setupPhase == 1) /* setup transaction qtd init */ + { + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: SETUP; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + qtdPointer->transferResults[0] = + ((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + dataAddress = (uint32_t)(transfer->setupPacket); + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000); + } + } + else if (setupPhase == 2) /* data transaction qtd */ + { + dataLength = transfer->transferLength; + if (dataLength != 0) + { + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + + dataAddress = (uint32_t)(transfer->transferBuffer); + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000); + } + } + } + else if (setupPhase == 3) + { + /* status transaction qtd */ + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: dont care; ioc: 1; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | + (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + } + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + qtdPointer->transferResults[0] |= EHCI_HOST_QTD_IOC_MASK; /* set IOC */ + + /* save qtd to transfer */ + transfer->union1.unitHead = (uint32_t)qtdPointer; + transfer->union2.unitTail = (uint32_t)qtdPointer; + /* link transfer to qh */ + transfer->next = NULL; + if (vltQhPointer->ehciTransferHead == NULL) + { + transfer->next = NULL; + vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer; + } + else + { + transfer->next = NULL; + vltQhPointer->ehciTransferTail->next = transfer; + vltQhPointer->ehciTransferTail = transfer; + } + + USB_HostEhciLock(); + /* link qtd to qh (link to end) */ + entryPointer = &(vltQhPointer->nextQtdPointer); + dataAddress = *entryPointer; /* dataAddress variable means entry value here */ + while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE))) + { + entryPointer = (volatile uint32_t *)dataAddress; + dataAddress = *entryPointer; + } + *entryPointer = (uint32_t)qtdPointer; + USB_HostEhciUnlock(); + USB_HostEhciStartAsync(ehciInstance); + + return kStatus_USB_Success; +} + +static void USB_HostEhciTestSingleStepGetDeviceDescData(usb_host_ehci_instance_t *ehciInstance, + usb_device_handle deviceHandle) +{ + static uint8_t buffer[USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH]; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_transfer_t *transfer; + uint8_t timeCount; + + USB_HostEhciStopPeriodic(ehciInstance); + + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { + return; + } + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + transfer->setupPacket->wLength = USB_SHORT_TO_LITTLE_ENDIAN(USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH); + transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN((uint16_t)((uint16_t)USB_DESCRIPTOR_TYPE_DEVICE << 8)); + transfer->setupPacket->wIndex = 0; + USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 1); + + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { + return; + } + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->transferBuffer = buffer; + transfer->transferLength = USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH; + USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 2); + + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { + return; + } + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->transferBuffer = NULL; + transfer->transferLength = 0; + USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 3); + + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + usb_echo("test_single_step_get_dev_desc_data finished\r\n"); + + return; +} + +void USB_HostEhciTestModeInit(usb_device_handle deviceHandle) +{ + uint32_t productId; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_ehci_instance_t *ehciInstance = + (usb_host_ehci_instance_t *)(((usb_host_instance_t *)(deviceInstance->hostHandle))->controllerHandle); + + USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDevicePID, &productId); + + usb_echo("usb host ehci test mode init product id:0x%x\r\n", productId); + + switch (productId) + { + case 0x0101U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_SE0_NAK); + break; + case 0x0102U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_J_STATE); + break; + case 0x0103U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_K_STATE); + break; + case 0x0104U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_PACKET); + break; + case 0x0105U: + usb_echo("set test mode FORCE_ENALBE_HS\r\n"); + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_HS); + break; + case 0x0106U: + USB_HostEhciTestSuspendResume(ehciInstance); + break; + case 0x0107U: + usb_echo("start test SINGLE_STEP_GET_DEV_DESC\r\n"); + USB_HostEhciTestSingleStepGetDeviceDesc(ehciInstance, deviceHandle); + break; + case 0x0108U: + usb_echo("start test SINGLE_STEP_GET_DEV_DESC_DATA\r\n"); + USB_HostEhciTestSingleStepGetDeviceDescData(ehciInstance, deviceHandle); + break; + default: + break; + } + + return; +} + +static void USB_HostEhciSuspendBus(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t ehciPortSC; + + USB_HostEhciLock(); + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + if (ehciPortSC & USBHS_PORTSC1_PE_MASK) + { + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + ehciPortSC &= (uint32_t)(~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (ehciPortSC | USBHS_PORTSC1_SUSP_MASK); + } + USB_HostEhciUnlock(); +} + +static void USB_HostEhciResumeBus(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t ehciPortSC; + + USB_HostEhciLock(); + /* Resume port */ + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + if (ehciPortSC & USBHS_PORTSC1_PE_MASK) + { + ehciPortSC &= (uint32_t)(~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (ehciPortSC | USBHS_PORTSC1_FPR_MASK); + } + USB_HostEhciUnlock(); +} +#endif + +static uint32_t USB_HostBandwidthComputeTime(uint8_t speed, uint8_t pipeType, uint8_t direction, uint32_t dataLength) +{ + uint32_t result = (3167 + ((1000 * dataLength) * 7U * 8U / 6U)) / 1000; + + if (pipeType == USB_ENDPOINT_ISOCHRONOUS) /* iso */ + { + if (speed == USB_SPEED_HIGH) + { + result = 38 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else if (speed == USB_SPEED_FULL) + { + if (direction == USB_IN) + { + result = 7268000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else + { + result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + } + else + { + } + } + else /* interrupt */ + { + if (speed == USB_SPEED_HIGH) + { + result = 55 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else if (speed == USB_SPEED_FULL) + { + result = 9107000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else if (speed == USB_SPEED_LOW) + { + if (direction == USB_IN) + { + result = 64060000 + 2000 * USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP + 676670 * result + + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else + { + result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + } + else + { + } + } + + result /= 1000000; + if (result == 0) + { + result = 1; + } + + return result; +} + +static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint16_t *frameBandwidth) +{ + usb_host_ehci_pipe_t *ehciPipePointer; + + /* clear the bandwidth */ + *frameBandwidth = 0; + + ehciPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciPipePointer != NULL) + { + /* only compute iso and interrupt pipe */ + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || + (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) + { + /* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */ + if ((frameIndex >= ehciPipePointer->startFrame) && + (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & + (uint32_t)(ehciPipePointer->pipeCommon.interval - 1)))) + { + *frameBandwidth += ehciPipePointer->dataTime; + } + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } +} + +static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance, + uint32_t hubNumber, + uint16_t frameIndex, + uint8_t frameBandwidths[8]) +{ + usb_host_ehci_pipe_t *ehciPipePointer; + uint8_t index; + uint32_t deviceInfo; + + for (index = 0; index < 8; ++index) + { + frameBandwidths[index] = 0; + } + + ehciPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciPipePointer != NULL) + { + /* only compute iso and interrupt pipe */ + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || + (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) + { + /* compute FS/LS bandwidth that blong to same high-speed hub, because FS/LS bandwidth is allocated from + * first parent high-speed hub */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, + kUSB_HostGetDeviceHSHubNumber, &deviceInfo); + if (deviceInfo != hubNumber) + { + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + continue; + } + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + if (deviceInfo == USB_SPEED_HIGH) + { + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + continue; + } + + /* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */ + if ((frameIndex >= ehciPipePointer->startFrame) && + (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & + (uint32_t)(ehciPipePointer->pipeCommon.interval - 1)))) + { + if (ehciPipePointer->pipeCommon.pipeType == + USB_ENDPOINT_ISOCHRONOUS) /* iso bandwidth is allocated once */ + { + frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime; + } + else /* iso bandwidth is allocated three times */ + { + frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime; + frameBandwidths[ehciPipePointer->startUframe + 2] += ehciPipePointer->dataTime; + frameBandwidths[ehciPipePointer->startUframe + 3] += ehciPipePointer->dataTime; + } + } + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } + + for (index = 0; index < 7; ++index) /* */ + { + if (frameBandwidths[index] > s_SlotMaxBandwidth[index]) + { + frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]); + frameBandwidths[index] = s_SlotMaxBandwidth[index]; + } + } +} + +static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint8_t frameBandwidths[8]) +{ + usb_host_ehci_pipe_t *ehciPipePointer; + uint8_t index; + uint32_t deviceInfo; + uint16_t frameInterval; + + for (index = 0; index < 8; ++index) + { + frameBandwidths[index] = 0; + } + + ehciPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciPipePointer != NULL) + { + /* only compute iso and interrupt pipe */ + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || + (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) + { + frameInterval = ehciPipePointer->pipeCommon.interval; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + if (deviceInfo == USB_SPEED_HIGH) /* high-speed data bandwidth */ + { + /* frameInterval means micro-frame here */ + if (frameIndex >= ehciPipePointer->startFrame) + { + if ((frameInterval > 8) && + (frameIndex * 8 - ehciPipePointer->startFrame * 8 >= ehciPipePointer->startUframe)) + { + if (!((uint32_t)(frameIndex * 8 - ehciPipePointer->startFrame * 8 - + ehciPipePointer->startUframe) & + (uint32_t)(frameInterval - 1))) + { + frameBandwidths[ehciPipePointer->startUframe] += ehciPipePointer->dataTime; + } + } + else + { + for (index = ehciPipePointer->startUframe; index < 8; index += frameInterval) + { + frameBandwidths[index] += ehciPipePointer->dataTime; + } + } + } + } + else /* full-speed split bandwidth */ + { + if ((frameIndex >= ehciPipePointer->startFrame) && + (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & (uint32_t)(frameInterval - 1)))) + { + for (index = 0; index < 8; ++index) + { + if ((uint32_t)(ehciPipePointer->uframeSmask) & + (uint32_t)(0x01 << index)) /* start-split micro-frames */ + { + frameBandwidths[index] += ehciPipePointer->startSplitTime; + } + if ((uint32_t)(ehciPipePointer->uframeCmask) & + (uint32_t)(0x01 << index)) /* complete-split micro-frames */ + { + frameBandwidths[index] += ehciPipePointer->completeSplitTime; + } + } + } + } + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } + + for (index = 0; index < 7; ++index) /* */ + { + if (frameBandwidths[index] > s_SlotMaxBandwidth[index]) + { + frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]); + frameBandwidths[index] = s_SlotMaxBandwidth[index]; + } + } +} + +/*! + * @brief allocate HS bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param uframeInterval micro-frame interval. + * @param timeData time for allocating. + * @param uframeIndexOut return start uframe index. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instance_t *ehciInstance, + uint16_t uframeInterval, + uint16_t timeData, + uint16_t *uframeIndexOut) +{ + uint16_t uframeIntervalIndex; + uint16_t uframeIndex; + uint16_t frameIndex; + uint8_t frameTimes[8]; + + frameIndex = 0; + USB_HostBandwidthHsHostComputeCurrentHsAll( + ehciInstance, frameIndex, frameTimes); /* compute the allocated bandwidths in the frameIndex frame */ + for (uframeIntervalIndex = 0; (uframeIntervalIndex < uframeInterval); ++uframeIntervalIndex) /* start micro-frame */ + { + /* for all the micro-frame in interval uframeInterval */ + for (uframeIndex = uframeIntervalIndex; uframeIndex < (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8); + uframeIndex += uframeInterval) + { + if (frameIndex != (uframeIndex >> 3)) + { + frameIndex = (uframeIndex >> 3); + USB_HostBandwidthHsHostComputeCurrentHsAll( + ehciInstance, frameIndex, + frameTimes); /* compute the allocated bandwidths in the new frameIndex frame */ + } + if (frameTimes[uframeIndex & 0x0007] + timeData > + s_SlotMaxBandwidth[(uframeIndex & 0x0007)]) /* micro-frame has enough idle bandwidth? */ + { + break; /* fail */ + } + } + if (uframeIndex >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8)) /* success? */ + { + break; + } + } + + if (uframeIntervalIndex < uframeInterval) + { + *uframeIndexOut = (uframeIntervalIndex); + return kStatus_USB_Success; + } + else + { + return kStatus_USB_Error; + } +} + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + +static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_status_t status; + uint32_t deviceInfo; + uint32_t hubNumber; + uint16_t uframeIntervalIndex = 0; + uint16_t frameIntervalIndex = 0; + uint16_t frameIndex; + uint16_t timeCompleteSplit; + uint16_t timeStartSplit; + uint32_t timeData; + uint8_t SsCsNumber = 0; + uint16_t frameInterval; + uint8_t frameTimes[8]; + uint8_t allocateOk = 1; + uint8_t index; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + + timeData = USB_HostBandwidthComputeTime( + deviceInfo, USB_ENDPOINT_ISOCHRONOUS, ehciPipePointer->pipeCommon.direction, + ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe); + /* pipe is high-speed */ + if (deviceInfo == USB_SPEED_HIGH) + { + uframeIntervalIndex = 0; + status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData, + &uframeIntervalIndex); + if (status == kStatus_USB_Success) + { + ehciPipePointer->startFrame = (uframeIntervalIndex / 8); + ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); + ehciPipePointer->dataTime = timeData; + + return kStatus_USB_Success; + } + } + else /* pipe is full-speed or low-speed */ + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, + &deviceInfo); /* deviceInfo variable means hub think time */ + timeData += (deviceInfo * 7 / (6 * 12)); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, + &hubNumber); + frameInterval = ehciPipePointer->pipeCommon.interval; + + /* compute start-split and complete-split bandwidth */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_OUT, + ehciPipePointer->pipeCommon.maxPacketSize); + timeCompleteSplit = 0; + } + else + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, 1); + timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, + ehciPipePointer->pipeCommon.maxPacketSize); + } + /* note: bandwidth must put in one frame */ + for (uframeIntervalIndex = 0; uframeIntervalIndex <= 5; ++uframeIntervalIndex) /* uframe interval */ + { + for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */ + { + allocateOk = 1; + for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += frameInterval) /* check all the frames */ + { + /* compute start-split and complete-split number */ + SsCsNumber = (ehciPipePointer->pipeCommon.maxPacketSize + 187) / + 188; /* ss number for iso out; cs number for iso in */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) /* ISO OUT */ + { + if (uframeIntervalIndex + SsCsNumber > 8) + { + allocateOk = 0; + } + } + else + { + if (uframeIntervalIndex + 2 + SsCsNumber > + 8) /* ISO IN: there are two micro-frame interval between start-split and complete-split */ + { + allocateOk = 0; + } + } + if (allocateOk) + { + /* allocate start-split and complete-split bandwidth */ + USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes); + if (ehciPipePointer->pipeCommon.direction == USB_OUT) /* ISO OUT */ + { + index = uframeIntervalIndex; + for (; index < (uframeIntervalIndex + SsCsNumber); ++index) + { + if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + } + else /* ISO IN */ + { + index = uframeIntervalIndex; + if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + } + if (allocateOk) + { + index = + uframeIntervalIndex + + 2; /* there are two micro-frames interval between start-split and complete-split */ + for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index) + { + if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + } + } + } + + /* allocate data bandwidth */ + if (allocateOk) + { + USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes); + index = uframeIntervalIndex + 1; /* timeData bandwidth start position */ + /* iso must occupy all the uframe bandwidth */ + { + deviceInfo = timeData; /* note: deviceInfo variable means bandwidth here */ + while ((index < 8) && (deviceInfo > s_SlotMaxBandwidth[index])) + { + if (frameTimes[index] > 0) + { + allocateOk = 0; + break; + } + else + { + deviceInfo -= s_SlotMaxBandwidth[index]; + } + ++index; + } + } + } + if (allocateOk) + { + /* data bandwidth can be put in the frame? */ + index = uframeIntervalIndex + 1; /* timeData bandwidth start position */ + frameTimes[index] += timeData; + for (; index < 7; ++index) + { + if (frameTimes[index] > s_SlotMaxBandwidth[index]) + { + frameTimes[index + 1] += (frameTimes[index] - s_SlotMaxBandwidth[index]); + frameTimes[index] = s_SlotMaxBandwidth[index]; + } + else + { + break; + } + } + if (frameTimes[index] > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + } + } + + if (allocateOk) + { + break; + } + } + if (allocateOk) + { + break; + } + } + if (allocateOk) + { + break; + } + } + + if (allocateOk) + { + ehciPipePointer->startFrame = frameIntervalIndex; + ehciPipePointer->startUframe = uframeIntervalIndex; + ehciPipePointer->dataTime = timeData; + ehciPipePointer->startSplitTime = timeStartSplit; + ehciPipePointer->completeSplitTime = timeCompleteSplit; + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + index = uframeIntervalIndex; + for (; index < (uframeIntervalIndex + SsCsNumber); ++index) + { + ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index); + } + } + else + { + index = uframeIntervalIndex; + ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index); + index = uframeIntervalIndex + 2; + for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index) + { + ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index); + } + } + + return kStatus_USB_Success; + } + } + + return kStatus_USB_Error; +} + +#endif + +static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_status_t status; + uint32_t deviceInfo; + uint32_t hubNumber; + uint16_t uframeIntervalIndex = 0; + uint16_t frameIntervalIndex = 0; + uint16_t frameIndex; + uint16_t timeCompleteSplit; + uint16_t timeStartSplit; + uint32_t timeData; + uint8_t SsCsNumber; + uint16_t frameInterval; + uint8_t frameTimes[8]; + uint8_t allocateOk = 1; + uint8_t index; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + + timeData = USB_HostBandwidthComputeTime( + deviceInfo, USB_ENDPOINT_INTERRUPT, ehciPipePointer->pipeCommon.direction, + ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe); + /* pipe is high-speed */ + if (deviceInfo == USB_SPEED_HIGH) + { + uframeIntervalIndex = 0; + status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData, + &uframeIntervalIndex); + if (status == kStatus_USB_Success) + { + ehciPipePointer->startFrame = (uframeIntervalIndex / 8); + ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); + /* for HS interrupt start transaction position */ + if (ehciPipePointer->uframeInterval >= 8) + { + ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe); + } + else + { + ehciPipePointer->uframeSmask = 0x00u; + for (index = ehciPipePointer->startUframe; index < 8; index += ehciPipePointer->uframeInterval) + { + ehciPipePointer->uframeSmask |= (0x01U << index); + } + } + ehciPipePointer->dataTime = timeData; + + return kStatus_USB_Success; + } + } + else /* pipe is full-speed or low-speed */ + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, + &deviceInfo); + timeData += (deviceInfo * 7 / (6 * 12)); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, + &hubNumber); + frameInterval = ehciPipePointer->pipeCommon.interval; + SsCsNumber = 3; /* complete split number */ + + /* compute start-split and complete-split bandwidth */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, + ehciPipePointer->pipeCommon.maxPacketSize) + + USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 1); + timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 0); + } + else + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 1); + timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, + ehciPipePointer->pipeCommon.maxPacketSize) + + USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 0); + } + /* note: bandwidth must put in one frame */ + for (uframeIntervalIndex = 0; uframeIntervalIndex <= 4; ++uframeIntervalIndex) /* uframe interval */ + { + for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */ + { + allocateOk = 1; + for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += frameInterval) /* check all the frames */ + { + /* allocate data bandwidth */ + USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes); + index = uframeIntervalIndex + 1; + for (; index <= (uframeIntervalIndex + 3); ++index) /* data bandwidth number is 3. + uframeIntervalIndex don't exceed 4, so + index cannot exceed 7 */ + { + if (frameTimes[index] + timeData > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + + if (allocateOk) + { + USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes); + /* allocate start_split bandwidth */ + if (frameTimes[uframeIntervalIndex] + timeStartSplit > s_SlotMaxBandwidth[uframeIntervalIndex]) + { + allocateOk = 0; + } + if (allocateOk) + { + /* allocate complete_split bandwidth */ + index = uframeIntervalIndex + 2; + /* complete-split number is normal 3. When uframeIntervalIndex is 4, complete-split number + * is 2. */ + for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index) + { + if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + } + } + + if (!allocateOk) + { + break; /* allocate fail */ + } + } + if (allocateOk) + { + break; + } + } + if (allocateOk) + { + break; + } + } + + if (allocateOk) + { + ehciPipePointer->startFrame = frameIntervalIndex; + ehciPipePointer->startUframe = uframeIntervalIndex; + ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe); + ehciPipePointer->uframeCmask = 0; + index = uframeIntervalIndex + 2; + for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index) + { + ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index); + } + ehciPipePointer->dataTime = timeData; + ehciPipePointer->startSplitTime = timeStartSplit; + ehciPipePointer->completeSplitTime = timeCompleteSplit; + + return kStatus_USB_Success; + } + } + + return kStatus_USB_BandwidthFail; +} + +static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + uint32_t FslsTime = 0; + uint32_t speed = 0; + uint16_t uframeIntervalIndex; + uint16_t frameIndex; + uint16_t frameInterval; + uint16_t frameTime; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, + &FslsTime); + FslsTime += (FslsTime * 7 / (6 * 12)); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); + FslsTime = FslsTime + USB_HostBandwidthComputeTime(speed, ehciPipePointer->pipeCommon.pipeType, + ehciPipePointer->pipeCommon.direction, + ehciPipePointer->pipeCommon.maxPacketSize); + + frameInterval = ehciPipePointer->pipeCommon.interval; + for (uframeIntervalIndex = 0; uframeIntervalIndex < ehciPipePointer->uframeInterval; + ++uframeIntervalIndex) /* uframeIntervalIndex can exceed 8 */ + { + for (frameIndex = (uframeIntervalIndex >> 3); frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += frameInterval) + { + USB_HostBandwidthFslsHostComputeCurrent(ehciInstance, frameIndex, &frameTime); + if (frameTime + FslsTime > USB_HOST_EHCI_BANDWIDTH_FRAME_TOTOAL_TIME) + { + break; + } + } + if (frameIndex >= USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) + { + break; + } + } + if (uframeIntervalIndex < ehciPipePointer->uframeInterval) + { + ehciPipePointer->startFrame = (uframeIntervalIndex >> 3); + ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); + ehciPipePointer->uframeSmask = 0; /* useless */ + ehciPipePointer->uframeCmask = 0; + ehciPipePointer->dataTime = FslsTime; + + return kStatus_USB_Success; + } + + return kStatus_USB_BandwidthFail; +} + +static uint8_t USB_HostEhciGet2PowerValue(uint8_t value) +{ + if ((value == 0) || (value == 1)) + { + return value; + } + if (value & 0xf0) + { + if (value & 0x80) + { + return 128; + } + else if (value & 0x40) + { + return 64; + } + else if (value & 0x20) + { + return 32; + } + else + { + return 16; + } + } + else + { + if (value & 0x08) + { + return 8; + } + else if (value & 0x04) + { + return 4; + } + else if (value & 0x02) + { + return 2; + } + else + { + return 1; + } + } +} + +static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length) +{ + /* note: the zero unit is uint32_t */ + while (length--) + { + *buffer = 0; + buffer++; + } +} + +static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms) +{ + /* note: the max delay time cannot exceed half of max value (0x4000) */ + int32_t sofStart; + int32_t SofEnd; + uint32_t distance; + + sofStart = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + + do + { + SofEnd = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + distance = (uint32_t)(SofEnd - sofStart + EHCI_MAX_UFRAME_VALUE + 1); + } while ((distance & EHCI_MAX_UFRAME_VALUE) < (ms * 8)); /* compute the distance between sofStart and SofEnd */ +} + +static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)) + { + /* the status must be same when change USBCMD->ASE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_ASE_MASK)); + } while ((stateSync == USBHS_USBSTS_AS_MASK) || (stateSync == USBHS_USBCMD_ASE_MASK)); + + ehciInstance->ehciIpBase->ASYNCLISTADDR = (uint32_t)(ehciInstance->shedFirstQh); + ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_ASE_MASK; + while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)) + { + } + } +} + +static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + /* the status must be same when change USBCMD->ASE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_ASE_MASK)); + } while ((stateSync == USBHS_USBSTS_AS_MASK) || (stateSync == USBHS_USBCMD_ASE_MASK)); + + ehciInstance->ehciIpBase->USBCMD &= (uint32_t)(~(uint32_t)USBHS_USBCMD_ASE_MASK); /* disable async schedule */ + while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) + { + } +} + +static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK)) + { + /* the status must be same when change USBCMD->PSE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)); + } while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK)); + ehciInstance->ehciIpBase->PERIODICLISTBASE = (uint32_t)(ehciInstance->ehciFrameList); + if (!(ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)) + { + ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_PSE_MASK; /* start periodic schedule */ + } + while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK)) + { + } + } + return; +} + +static void USB_HostEhciStopPeriodic(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + /* the status must be same when change USBCMD->PSE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)); + } while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK)); + + ehciInstance->ehciIpBase->USBCMD &= (~USBHS_USBCMD_PSE_MASK); /* stop periodic schedule */ + while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) + { + } +} + +static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_ehci_qtd_t *qtdPointer = NULL; + usb_host_ehci_qtd_t *BaseQtdPointer = NULL; + volatile uint32_t *entryPointer; + uint32_t qtdNumber; + uint32_t dataLength; + uint32_t dataAddress; + uint32_t endAddress; + uint8_t index; + + /* compute the qtd number */ + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) + { + /* assume setup data don't exceed one qtd data size, one qtd can transfer least 16k data */ + if (transfer->transferLength == 0) + { + qtdNumber = 2; + } + else + { + qtdNumber = 3; + } + } + else + { + qtdNumber = + (((transfer->transferLength) & 0xFFFFC000U) >> 14) + (((transfer->transferLength) & 0x00003FFF) ? 1 : 0); + } + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* get qtd list */ + USB_HostEhciLock(); + if (qtdNumber <= ehciInstance->ehciQtdNumber) + { + ehciInstance->ehciQtdNumber -= qtdNumber; + BaseQtdPointer = ehciInstance->ehciQtdHead; + qtdPointer = NULL; + do + { + if (qtdPointer != NULL) + { + qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead; + } + qtdPointer = ehciInstance->ehciQtdHead; + ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; + qtdPointer->nextQtdPointer = 0; + } while (--qtdNumber); + if (ehciInstance->ehciQtdNumber == 0) + { + ehciInstance->ehciQtdTail = NULL; + } + } + else + { + USB_HostEhciUnlock(); + return kStatus_USB_Error; + } + USB_HostEhciUnlock(); + + /* int qTD list */ + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) + { + /* setup transaction qtd */ + qtdPointer = BaseQtdPointer; + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: SETUP; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + qtdPointer->transferResults[0] = + ((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + dataAddress = ((uint32_t)transfer->setupPacket); + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); + } + + /* data transaction qtd */ + dataLength = transfer->transferLength; + if (dataLength != 0) + { + qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); + + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + if (transfer->direction == USB_OUT) + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + else + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + + dataAddress = (uint32_t)transfer->transferBuffer; + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); + } + } + + /* status transaction qtd */ + qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: dont care; ioc: 1; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + if ((dataLength == 0) || (transfer->direction == USB_OUT)) + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | + (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + else + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | + (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + } + else + { + dataLength = transfer->transferLength; + dataAddress = (uint32_t)transfer->transferBuffer; + qtdPointer = BaseQtdPointer; + while (1) + { + endAddress = dataAddress + (16 * 1024); + if (endAddress > (uint32_t)(transfer->transferBuffer + transfer->transferLength)) + { + endAddress = (uint32_t)(transfer->transferBuffer + transfer->transferLength); + } + + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + if (transfer->direction == USB_OUT) + { + qtdPointer->transferResults[0] = + (((endAddress - dataAddress) << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.nextdata01 << EHCI_HOST_QTD_DT_SHIFT) | + (EHCI_HOST_QTD_CERR_MAX_VALUE << EHCI_HOST_QTD_CERR_SHIFT) | + (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + else + { + qtdPointer->transferResults[0] = + (((endAddress - dataAddress) << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.nextdata01 << EHCI_HOST_QTD_DT_SHIFT) | + (EHCI_HOST_QTD_CERR_MAX_VALUE << EHCI_HOST_QTD_CERR_SHIFT) | + (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); + } + dataAddress = endAddress; /* for next qtd */ + + if (qtdPointer->nextQtdPointer == 0) + { + break; + } + qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); + } + + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + qtdPointer->transferResults[0] |= EHCI_HOST_QTD_IOC_MASK; /* last one set IOC */ + } + + /* save qtd to transfer */ + transfer->union1.unitHead = (uint32_t)BaseQtdPointer; + transfer->union2.unitTail = (uint32_t)qtdPointer; + /* link transfer to qh */ + transfer->next = NULL; + if (vltQhPointer->ehciTransferHead == NULL) + { + transfer->next = NULL; + vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer; + } + else + { + transfer->next = NULL; + vltQhPointer->ehciTransferTail->next = transfer; + vltQhPointer->ehciTransferTail = transfer; + } + + USB_HostEhciLock(); + /* link qtd to qh (link to end) */ + entryPointer = &(vltQhPointer->nextQtdPointer); + dataAddress = *entryPointer; /* dataAddress variable means entry value here */ + while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE))) + { + entryPointer = (volatile uint32_t *)dataAddress; + dataAddress = *entryPointer; + } + *entryPointer = (uint32_t)BaseQtdPointer; + USB_HostEhciUnlock(); + USB_HostEhciStartAsync(ehciInstance); + + return kStatus_USB_Success; +} + +static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_qtd_t *ehciQtdStart, + usb_host_ehci_qtd_t *ehciQtdEnd) +{ + uint32_t length = 0; + usb_host_ehci_qtd_t *qtdPointer; + + ehciQtdEnd->nextQtdPointer = 0; + + /* compute remaining length */ + qtdPointer = ehciQtdStart; + while (qtdPointer != ehciQtdEnd) + { + length += + ((qtdPointer->transferResults[0] & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); + qtdPointer = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; + } + qtdPointer = ehciQtdEnd; + length += ((qtdPointer->transferResults[0] & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); + + /* put releasing qtd to idle qtd list */ + USB_HostEhciLock(); + if (ehciInstance->ehciQtdNumber == 0) + { + ehciInstance->ehciQtdHead = ehciQtdStart; + ehciInstance->ehciQtdTail = ehciQtdEnd; + } + else + { + ehciInstance->ehciQtdTail->nextQtdPointer = (uint32_t)ehciQtdStart; + ehciInstance->ehciQtdTail = ehciQtdEnd; + } + + while (ehciQtdStart != ehciQtdEnd) + { + ehciInstance->ehciQtdNumber++; + ehciQtdStart = (usb_host_ehci_qtd_t *)ehciQtdStart->nextQtdPointer; + } + ehciInstance->ehciQtdNumber++; + USB_HostEhciUnlock(); + + return length; +} + +static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + uint8_t needStop = 0; + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + + USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */ + /* remove qtd from qh */ + if ((!((uint32_t)vltQhPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE)) || + (!((uint32_t)vltQhPointer->currentQtdPointer & EHCI_HOST_T_INVALID_VALUE))) + { + /* need stop async schedule */ + if ((!(vltQhPointer->horizontalLinkPointer & EHCI_HOST_T_INVALID_VALUE)) && + (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT)) + { + needStop = 1; + } + if (needStop) + { + USB_HostEhciStopAsync(ehciInstance); + } + vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid current qtd */ + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + if (needStop) + { + USB_HostEhciStartAsync(ehciInstance); + } + } + + /* remove transfer from the QH transfer list */ + transfer = vltQhPointer->ehciTransferHead; + vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = NULL; + USB_HostEhciUnlock(); + + /* release qtd and transfer callback*/ + while (transfer != NULL) + { + nextTransfer = transfer->next; /* the transfer is released when call back */ + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + transfer = nextTransfer; + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_transfer_t *preSearchTransfer; + uint32_t qhNextQtdValue; + uint32_t qtdPointerEntry; + uint32_t *searchQtdEntryPointer; + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + + USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */ + /* remove qtd from qh */ + qhNextQtdValue = (uint32_t)vltQhPointer->currentQtdPointer; + qtdPointerEntry = *((uint32_t *)qhNextQtdValue + 2); /* note: qtdPointerEntry means qtd status */ + if ((qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE) || (!(qtdPointerEntry & EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) + { + qhNextQtdValue = (uint32_t)vltQhPointer->nextQtdPointer; + } + if (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE)) /* there is pending qtd in the qh */ + { + /* this qh don't schedule temporarily */ + if (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT) + { + USB_HostEhciStopAsync(ehciInstance); + } + vltQhPointer->currentQtdPointer |= EHCI_HOST_T_INVALID_VALUE; /* invalid current qtd */ + vltQhPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + if (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT) + { + USB_HostEhciStartAsync(ehciInstance); + } + + /* remove qtd from qh one by one */ + qtdPointerEntry = transfer->union1.unitHead; + while (1) + { + /* search qh's qtd list for qtdPointerEntry */ + searchQtdEntryPointer = &qhNextQtdValue; + while (!((*searchQtdEntryPointer) & EHCI_HOST_T_INVALID_VALUE)) + { + if ((*searchQtdEntryPointer) == qtdPointerEntry) + { + *searchQtdEntryPointer = *((uint32_t *)qtdPointerEntry); /* remove the qtd from qh */ + break; + } + else + { + searchQtdEntryPointer = (uint32_t *)(*searchQtdEntryPointer); + } + } + if (qtdPointerEntry == transfer->union2.unitTail) + { + break; + } + qtdPointerEntry = *((uint32_t *)qtdPointerEntry); + } + } + + /* remove transfer from the QH transfer list */ + preSearchTransfer = vltQhPointer->ehciTransferHead; + if (preSearchTransfer == transfer) + { + vltQhPointer->ehciTransferHead = preSearchTransfer->next; + } + else + { + while (preSearchTransfer != NULL) + { + if (preSearchTransfer->next == transfer) + { + preSearchTransfer->next = transfer->next; + break; + } + else + { + preSearchTransfer = preSearchTransfer->next; + } + } + } + USB_HostEhciUnlock(); + + /* release qtd and callback */ + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = + (transfer->transferLength < transfer->transferSofar) ? 0 : (transfer->transferLength - transfer->transferSofar); + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + + /* start this qh schedule */ + vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + if ((qhNextQtdValue != 0) && (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE))) + { + vltQhPointer->nextQtdPointer = qhNextQtdValue; + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_qh_t *qhPointer = NULL; + uint32_t address, speed, portNumber, hubNumber; + uint32_t controlBits1 = 0; + uint32_t controlBits2 = 0; + /* get qh */ + USB_HostEhciLock(); + if (ehciInstance->ehciQhList != NULL) + { + qhPointer = (usb_host_ehci_qh_t *)ehciInstance->ehciQhList; + ehciInstance->ehciQhList = + (usb_host_ehci_qh_t *)(ehciInstance->ehciQhList->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK); + } + USB_HostEhciUnlock(); + if (qhPointer == NULL) + { +#ifdef HOST_EHCO + usb_echo("get qh error\r\n"); +#endif + return kStatus_USB_Error; + } + ehciPipePointer->ehciQh = (void *)qhPointer; + + /* initialize qh */ + USB_HostEhciZeroMem((uint32_t *)qhPointer, sizeof(usb_host_ehci_qh_t) / 4); + qhPointer->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->ehciPipePointer = ehciPipePointer; + qhPointer->timeOutLabel = 0; + qhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); + /* initialize staticEndpointStates[0] */ + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) + { + /* Software should set the RL field to zero if the queue head is an interrupt endpoint. */ + controlBits1 |= ((0U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); + } + else + { + if (ehciPipePointer->pipeCommon.nakCount >= 16) + { + controlBits1 |= ((15U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); + } + else + { + controlBits1 |= + (((uint32_t)ehciPipePointer->pipeCommon.nakCount << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); + } + } + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) + { + if (speed != USB_SPEED_HIGH) + { + controlBits1 |= (1 << EHCI_HOST_QH_C_SHIFT); + } + controlBits1 |= (1 << EHCI_HOST_QH_DTC_SHIFT); + } + controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT); + controlBits1 |= (speed << EHCI_HOST_QH_EPS_SHIFT); + controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_QH_ENDPT_SHIFT); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &address); + controlBits1 |= (address << EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT); + qhPointer->staticEndpointStates[0] = controlBits1; + if (speed == USB_SPEED_HIGH) + { + controlBits2 |= ((uint32_t)ehciPipePointer->pipeCommon.numberPerUframe << EHCI_HOST_QH_MULT_SHIFT); + } + else + { + controlBits2 |= (0x00000001U << EHCI_HOST_QH_MULT_SHIFT); + } + /*initialize staticEndpointStates[1] */ + if (speed != USB_SPEED_HIGH) + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, + &hubNumber); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubPort, + &portNumber); + } + else + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber, + &hubNumber); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber, + &portNumber); + } + controlBits2 |= (portNumber << EHCI_HOST_QH_PORT_NUMBER_SHIFT); + controlBits2 |= (hubNumber << EHCI_HOST_QH_HUB_ADDR_SHIFT); + controlBits2 |= ((uint32_t)ehciPipePointer->uframeCmask << EHCI_HOST_QH_UFRAME_CMASK_SHIFT); + controlBits2 |= ((uint32_t)ehciPipePointer->uframeSmask << EHCI_HOST_QH_UFRAME_SMASK_SHIFT); + qhPointer->staticEndpointStates[1] = controlBits2; + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciQhDeinit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_qh_t *qhPointer; + + qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* de-initialize qtd from qh */ + USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); + + /* release QH */ + USB_HostEhciLock(); + qhPointer->horizontalLinkPointer = (uint32_t)ehciInstance->ehciQhList; + ehciInstance->ehciQhList = qhPointer; + USB_HostEhciUnlock(); + + return kStatus_USB_Success; +} + +static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos, + uint16_t uframeInterval) +{ + volatile uint32_t *frameEntryPointer; + uint32_t frameEntryValue; + + /* search for the inserting point by interval */ + frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]); + while (frameEntryPointer) + { + frameEntryValue = *frameEntryPointer; + if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE) + { + /* insert into the end */ + *((uint32_t *)entryPointerValue) = EHCI_HOST_T_INVALID_VALUE; + *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH); + break; + } + + if ((frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK) == entryPointerValue) + { + return; /* has inserted */ + } + if (((frameEntryValue & EHCI_HOST_POINTER_TYPE_MASK) == EHCI_HOST_POINTER_TYPE_QH) && + (((usb_host_ehci_qh_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK)) + ->ehciPipePointer->uframeInterval <= uframeInterval)) + { + /* insert into this point */ + *((uint32_t *)entryPointerValue) = frameEntryValue; + *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH); + return; + } + else + { + frameEntryPointer = (volatile uint32_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK); + } + } +} + +static void USB_HostEhciRemoveFromFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos) +{ + volatile uint32_t *frameEntryPointer; + uint32_t frameEntryValue; + + /* search for the qh/itd/sitd entry */ + frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]); + + while (frameEntryPointer) + { + frameEntryValue = *frameEntryPointer; + if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE) + { + return; + } + + if ((frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK) == entryPointerValue) + { + /* remove the entry */ + *frameEntryPointer = *((uint32_t *)entryPointerValue); + break; + } + else + { + frameEntryPointer = (volatile uint32_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK); + } + } +} + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) +static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + void *startEntryPointer) +{ + usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + usb_host_ehci_sitd_t *sitdPointer; + uint32_t distance; + uint32_t frameInterval; + int32_t shouldLinkFrame; + int32_t currentFrame; + + frameInterval = (ehciPipePointer->uframeInterval >> 3); + + if (isoPointer->lastLinkFrame == 0xFFFF) /* first link */ + { + currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); + currentFrame = ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & + (EHCI_MAX_UFRAME_VALUE >> 3)); /* add USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER */ + /* frame should align with interval */ + currentFrame -= ehciPipePointer->startFrame; + currentFrame = + ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1))); /* frameInterval is power of 2 */ + currentFrame += ehciPipePointer->startFrame; + } + else + { + shouldLinkFrame = isoPointer->lastLinkFrame + frameInterval; /* continuous next should link frame */ + if (shouldLinkFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) + { + shouldLinkFrame = shouldLinkFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); + } + currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); + distance = ((shouldLinkFrame - currentFrame + (EHCI_MAX_UFRAME_VALUE >> 3) + 1) & + (EHCI_MAX_UFRAME_VALUE >> 3)); /* get the distance from shouldLinkFrame to currentFrame */ + /* shouldLinkFrame has add frameInterval, think about the align with interval, so here add (frameInterval * + * 2) */ + if ((distance <= (USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER + frameInterval * 2)) && (distance > 0)) + { + currentFrame = shouldLinkFrame; + } + else /* re-link */ + { + currentFrame = + ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & (EHCI_MAX_UFRAME_VALUE >> 3)); + if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) + { + currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); + } + /* frame should align with interval */ + currentFrame -= ehciPipePointer->startFrame; + currentFrame = ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1))); + currentFrame += ehciPipePointer->startFrame; + } + } + if (currentFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) /* frame turn around */ + { + shouldLinkFrame = + (currentFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE); /* shouldLinkFrame means inserted frame position */ + } + else + { + shouldLinkFrame = currentFrame; /* shouldLinkFrame means inserted frame position */ + } + + sitdPointer = (usb_host_ehci_sitd_t *)startEntryPointer; + while (sitdPointer) + { + sitdPointer->frameEntryIndex = shouldLinkFrame; + /* add to frame list head */ + sitdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame]; + ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame] = + ((uint32_t)sitdPointer | EHCI_HOST_POINTER_TYPE_SITD); + if (sitdPointer->nextSitdIndex == 0xFF) /* 0xFF is invalid value */ + { + break; + } + sitdPointer = &(ehciInstance->ehciSitdIndexBase[sitdPointer->nextSitdIndex]); /* next sitd */ + + shouldLinkFrame += frameInterval; + currentFrame += frameInterval; + if (shouldLinkFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) + { + shouldLinkFrame = (shouldLinkFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE); + } + } + + if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) + { + currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); + } + isoPointer->lastLinkFrame = currentFrame; /* save the last link frame value */ +} + +static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_iso_t *isoPointer; + uint32_t sitdNumber = 0; + usb_host_ehci_sitd_t *sitdPointer; + uint32_t dataLength = 0; + uint32_t sitdLength = 0; + uint32_t dataBufferValue; + uint32_t hubNumber; + uint32_t portNumber; + uint32_t address; + uint32_t tmp; + uint8_t index; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &address); + + sitdNumber = ((transfer->transferLength - 1 + (ehciPipePointer->pipeCommon.maxPacketSize)) / + (ehciPipePointer->pipeCommon.maxPacketSize)); + /* get sitd array */ + tmp = ehciPipePointer - ehciInstance->ehciPipeIndexBase; /* pipe index */ + /* USB_HostEhciLock(); */ + if (ehciInstance->ehciSitdNumber >= sitdNumber) + { + sitdPointer = ehciInstance->ehciSitdList; + transfer->union1.unitHead = (uint32_t)sitdPointer; + for (index = 1; index < sitdNumber; ++index) + { + sitdPointer->nextSitdIndex = + (((usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer) - ehciInstance->ehciSitdIndexBase); + sitdPointer = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer; + } + sitdPointer->nextSitdIndex = 0xFF; + ehciInstance->ehciSitdList = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer; + ehciInstance->ehciSitdNumber -= sitdNumber; + } + else + { + /* USB_HostEhciUnlock(); */ + return kStatus_USB_Error; + } + /* USB_HostEhciUnlock(); */ + transfer->union2.unitTail = (uint32_t)sitdPointer; + /* initialize sitd array */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber, + &hubNumber); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber, + &portNumber); + sitdPointer = (usb_host_ehci_sitd_t *)transfer->union1.unitHead; + dataLength = transfer->transferLength; + while (sitdNumber--) + { + USB_HostEhciZeroMem((uint32_t *)sitdPointer, 7); + sitdLength = dataLength; + if (sitdLength > ehciPipePointer->pipeCommon.maxPacketSize) + { + sitdLength = ehciPipePointer->pipeCommon.maxPacketSize; + } + dataBufferValue = (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength)); + dataLength -= sitdLength; /* update left data length */ + sitdPointer->transferResults[1] = dataBufferValue; + sitdPointer->transferResults[2] = ((dataBufferValue + 4 * 1024) & 0xFFFFF000U); + sitdPointer->endpointStates[0] = + (((uint32_t)ehciPipePointer->pipeCommon.direction << EHCI_HOST_SITD_DIRECTION_SHIFT) | + (portNumber << EHCI_HOST_SITD_PORT_NUMBER_SHIFT) | (hubNumber << EHCI_HOST_SITD_HUB_ADDR_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_SITD_ENDPT_SHIFT) | + (address << EHCI_HOST_SITD_DEVICE_ADDRESS_SHIFT)); + sitdPointer->transferResults[0] = + ((sitdLength << EHCI_HOST_SITD_TOTAL_BYTES_SHIFT) | (EHCI_HOST_SITD_STATUS_ACTIVE_MASK)); + + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + sitdPointer->endpointStates[1] = (((uint32_t)ehciPipePointer->uframeCmask << EHCI_HOST_SITD_CMASK_SHIFT) | + ((uint32_t)ehciPipePointer->uframeSmask << EHCI_HOST_SITD_SMASK_SHIFT)); + + tmp = (sitdLength + 187) / 188; + if (tmp > 1) + { + sitdPointer->transferResults[2] |= (0x01 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */ + } + else + { + sitdPointer->transferResults[2] |= (0x00 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */ + } + sitdPointer->transferResults[2] |= (tmp << EHCI_HOST_SITD_TCOUNT_SHIFT); /* for iso split */ + } + + sitdPointer->backPointer = EHCI_HOST_T_INVALID_VALUE; + + sitdPointer = (ehciInstance->ehciSitdIndexBase + sitdPointer->nextSitdIndex); + } + sitdPointer = (usb_host_ehci_sitd_t *)transfer->union2.unitTail; + sitdPointer->transferResults[0] |= (1U << EHCI_HOST_SITD_IOC_SHIFT); /* last set IOC */ + + /* link transfer to usb_host_ehci_iso_t transfer list */ + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + USB_HostEhciLock(); + if (isoPointer->ehciTransferHead == NULL) + { + transfer->next = NULL; + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer; + } + else + { + transfer->next = NULL; + isoPointer->ehciTransferTail->next = transfer; + isoPointer->ehciTransferTail = transfer; + } + USB_HostEhciUnlock(); + + /* link itd to frame list (note: initialize frameEntryIndex)*/ + USB_HostEhciLinkSitd(ehciInstance, ehciPipePointer, (void *)transfer->union1.unitHead); + + return kStatus_USB_Success; +} + +static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_sitd_t *startSitdPointer, + usb_host_ehci_sitd_t *endSitdPointer) +{ + usb_host_ehci_sitd_t *sitdPointer = startSitdPointer; + uint32_t leftLength = 0; + /* remove itd from frame list */ + while (1) + { + /* record the transfer's result length */ + leftLength += + ((sitdPointer->transferResults[0] & EHCI_HOST_SITD_TOTAL_BYTES_MASK) >> EHCI_HOST_SITD_TOTAL_BYTES_SHIFT); + USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)sitdPointer, + sitdPointer->frameEntryIndex); /* remove from the inserted frame list */ + + /* release itd */ + /* USB_HostEhciLock(); */ + sitdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciSitdList; + ehciInstance->ehciSitdList = sitdPointer; + ehciInstance->ehciSitdNumber++; + /* USB_HostEhciUnlock(); */ + + if (sitdPointer == endSitdPointer) + { + break; + } + + sitdPointer = &(ehciInstance->ehciSitdIndexBase[sitdPointer->nextSitdIndex]); + } + + return leftLength; +} + +static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + + /* firstly remove the transfer (because host task may occupy to access the resource) */ + USB_HostEhciLock(); + transfer = isoPointer->ehciTransferHead; + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL; + USB_HostEhciUnlock(); + + while (transfer != NULL) + { + nextTransfer = transfer->next; + /* remove sitd from frame list and release itd */ + transfer->transferSofar = + transfer->transferLength - USB_HostEhciSitdArrayRelease(ehciInstance, + (usb_host_ehci_sitd_t *)transfer->union1.unitHead, + (usb_host_ehci_sitd_t *)transfer->union2.unitTail); + /* transfer callback */ + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + /* next transfer */ + transfer = nextTransfer; + } + + return kStatus_USB_Success; +} +#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) +static uint32_t USB_HostEhciGetItdLinkFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t lastLinkUframe, + uint16_t startUframe, + uint16_t uframeInterval) +{ + int32_t shouldLinkUframe; + int32_t currentUframe; + int32_t distance; + + if (lastLinkUframe != 0xFFFF) + { + shouldLinkUframe = lastLinkUframe + uframeInterval; + if (shouldLinkUframe > (int32_t)EHCI_MAX_UFRAME_VALUE) + { + shouldLinkUframe = shouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + distance = ((shouldLinkUframe - currentUframe + EHCI_MAX_UFRAME_VALUE + 1) & + EHCI_MAX_UFRAME_VALUE); /* get the distance */ + /* shouldLinkUframe has add uframeInterval, think about the align with interval, so here add (uframeInterval + * * 2) */ + if ((distance <= (int32_t)(USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER + (uframeInterval * 2))) && (distance > 2)) + { + currentUframe = shouldLinkUframe; + } + else /* re-link */ + { + currentUframe = + ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE); + if (currentUframe > (int32_t)EHCI_MAX_UFRAME_VALUE) + { + currentUframe = currentUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + /* uframe should align with interval */ + currentUframe -= startUframe; + currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) & + (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */ + currentUframe += startUframe; + } + } + else + { + currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + currentUframe = ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE); + /* uframe should align with interval */ + currentUframe -= startUframe; + currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) & + (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */ + currentUframe += startUframe; + } + + return currentUframe; +} + +static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_iso_t *isoPointer; + usb_host_ehci_itd_t *itdPointer = NULL; + usb_host_ehci_itd_t *tmpItdPointer; + uint32_t dataLength; /* the remaining data for sending */ + uint32_t transactionLength; /* the initializing transaction descriptor data length */ + uint32_t itdBufferValue; + uint32_t itdBufferBaseValue; /* for calculating PG value */ + uint32_t address; + uint32_t lastShouldLinkUframe; + uint32_t linkUframe; + uint32_t minDataPerItd = ehciPipePointer->pipeCommon.numberPerUframe * ehciPipePointer->pipeCommon.maxPacketSize; + uint8_t maxItdNumber; + uint8_t index = 0; + + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &address); + + /* max needed itd number, the actual needed number may be less because micro-frame interval may be less than 8 */ + maxItdNumber = ((transfer->transferLength - 1 + minDataPerItd) / minDataPerItd); + if (ehciPipePointer->uframeInterval < 8) + { + maxItdNumber = ((maxItdNumber * ehciPipePointer->uframeInterval + 7) / 8) + 1; + } + if (maxItdNumber > ehciInstance->ehciItdNumber) + { + return kStatus_USB_Error; + } + + /* link transfer to usb_host_ehci_iso_t transfer list */ + transfer->next = NULL; + /* USB_HostEhciLock(); */ + if (isoPointer->ehciTransferHead == NULL) + { + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer; + } + else + { + isoPointer->ehciTransferTail->next = transfer; + isoPointer->ehciTransferTail = transfer; + } + /* USB_HostEhciUnlock(); */ + + dataLength = transfer->transferLength; + transfer->union1.unitHead = (uint32_t)NULL; + /* get the link micro-frame */ + lastShouldLinkUframe = USB_HostEhciGetItdLinkFrame( + ehciInstance, isoPointer->lastLinkFrame, + (uint16_t)((ehciPipePointer->startFrame << 3) + ehciPipePointer->startUframe), ehciPipePointer->uframeInterval); + if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE) + { + linkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + else + { + linkUframe = lastShouldLinkUframe; + } + while (dataLength) + { + /* get one idle itd */ + tmpItdPointer = ehciInstance->ehciItdList; + ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)tmpItdPointer->nextLinkPointer; + ehciInstance->ehciItdNumber -= 1; + if (tmpItdPointer == NULL) + { + return kStatus_USB_Error; /* this should not reach */ + } + tmpItdPointer->nextItdPointer = NULL; + + /* use the itd */ + if (transfer->union1.unitHead == (uint32_t)NULL) /* first itd */ + { + transfer->union1.unitHead = (uint32_t)tmpItdPointer; + } + else /* link itd list */ + { + itdPointer->nextItdPointer = tmpItdPointer; + } + itdPointer = tmpItdPointer; + + /* itd has been set to all zero when releasing */ + itdBufferBaseValue = itdBufferValue = + (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength)); + for (index = 0; index < 7; ++index) + { + itdPointer->bufferPointers[index] = ((itdBufferBaseValue + (index * 4 * 1024)) & 0xFFFFF000U); + } + /* initialize iTD common fields */ + itdPointer->bufferPointers[0] |= + (((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_ITD_ENDPT_SHIFT) | + (address << EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT)); + itdPointer->bufferPointers[1] |= + (((uint32_t)ehciPipePointer->pipeCommon.direction << EHCI_HOST_ITD_DIRECTION_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT)); + itdPointer->bufferPointers[2] |= (ehciPipePointer->pipeCommon.numberPerUframe); + /* initialize transaction descriptors */ + for (index = (linkUframe & 0x0007); index < 8; index += ehciPipePointer->uframeInterval) + { + transactionLength = ((dataLength > minDataPerItd) ? minDataPerItd : dataLength); + /* initialize the uframeIndex's transaction descriptor in itd */ + itdPointer->transactions[index] = + ((EHCI_HOST_ITD_STATUS_ACTIVE_MASK) | (transactionLength << EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT) | + ((((itdBufferValue & 0xFFFFF000U) - (itdBufferBaseValue & 0xFFFFF000U)) >> + EHCI_HOST_ITD_BUFFER_POINTER_SHIFT) + << EHCI_HOST_ITD_PG_SHIFT) | + (itdBufferValue & EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK)); + dataLength -= transactionLength; + itdBufferValue += transactionLength; + if (dataLength <= 0) + { + break; + } + } + } + + transfer->union2.unitTail = (uint32_t)itdPointer; + itdPointer->transactions[index] |= (1 << EHCI_HOST_ITD_IOC_SHIFT); /* last set IOC */ + + /* link itd to frame list (note: initialize frameEntryIndex)*/ + while (itdPointer) + { + itdPointer->frameEntryIndex = linkUframe; + /* add to frame head */ + itdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3]; + *(uint32_t *)((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3] = + ((uint32_t)itdPointer | EHCI_HOST_POINTER_TYPE_ITD); + itdPointer = itdPointer->nextItdPointer; + if (itdPointer == NULL) + { + break; + } + + linkUframe += ehciPipePointer->uframeInterval; + lastShouldLinkUframe += ehciPipePointer->uframeInterval; + if (linkUframe >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE << 3)) + { + linkUframe = (linkUframe - (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE << 3)); + } + } + + if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE) + { + lastShouldLinkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + isoPointer->lastLinkFrame = lastShouldLinkUframe; + + return kStatus_USB_Success; +} + +static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_itd_t *startItdPointer, + usb_host_ehci_itd_t *endItdPointer) +{ + usb_host_ehci_itd_t *itdPointer = startItdPointer; + uint8_t index; + uint32_t doneLength = 0; + + /* remove itd from frame list */ + while (1) + { + /* record the transfer's result length */ + for (index = 0; index < 8; ++index) + { + doneLength += ((itdPointer->transactions[index] & EHCI_HOST_ITD_TRANSACTION_LEN_MASK) >> + EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT); + } + + USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)itdPointer, + itdPointer->frameEntryIndex); /* remove from the inserted frame list */ + + /* release itd */ + /* USB_HostEhciLock(); */ + USB_HostEhciZeroMem((uint32_t *)itdPointer, sizeof(usb_host_ehci_itd_t) >> 2); + itdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciItdList; + ehciInstance->ehciItdList = itdPointer; + ehciInstance->ehciItdNumber++; + /* USB_HostEhciUnlock(); */ + + if (itdPointer == endItdPointer) + { + break; + } + itdPointer = itdPointer->nextItdPointer; + } + + return doneLength; +} + +static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + uint32_t doneLength = 0; + + /* firstly remove the transfer (because host task may occupy to access the resource) */ + USB_HostEhciLock(); + transfer = isoPointer->ehciTransferHead; + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL; + USB_HostEhciUnlock(); + + while (transfer != NULL) + { + nextTransfer = transfer->next; + doneLength = 0; + /* remove itd from frame list and release itd */ + doneLength = USB_HostEhciItdArrayRelease(ehciInstance, (usb_host_ehci_itd_t *)transfer->union1.unitHead, + (usb_host_ehci_itd_t *)transfer->union2.unitTail); + + /* transfer callback */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + doneLength = transfer->transferLength; + } + transfer->transferSofar = doneLength; + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + + /* next transfer */ + transfer = nextTransfer; + } + + return kStatus_USB_Success; +} +#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ + +static usb_status_t USB_HostEhciOpenControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_qh_t *qhPointer; + + if (USB_HostEhciQhInit(ehciInstance, ehciPipePointer) != kStatus_USB_Success) /* initialize control/bulk qh */ + { + return kStatus_USB_Error; + } + + qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + + /* add qh to async */ + qhPointer->horizontalLinkPointer = ehciInstance->shedFirstQh->horizontalLinkPointer; + ehciInstance->shedFirstQh->horizontalLinkPointer = ((uint32_t)qhPointer | EHCI_HOST_POINTER_TYPE_QH); + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + volatile usb_host_ehci_qh_t *vltPrevQhPointer; + uint32_t horizontalLinkValue; + + /* remove qh from async schedule */ + if ((ehciInstance->shedFirstQh->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK) == + (uint32_t)ehciPipePointer->ehciQh) /* the removing qh is the first qh in the async list */ + { + USB_HostEhciStopAsync(ehciInstance); + ehciInstance->shedFirstQh->horizontalLinkPointer = + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer; + USB_HostEhciStartAsync(ehciInstance); + } + else + { + /* search for the removing qh from the async list */ + vltPrevQhPointer = ehciInstance->shedFirstQh; + while (vltPrevQhPointer != NULL) + { + horizontalLinkValue = vltPrevQhPointer->horizontalLinkPointer; + if ((horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE) || + ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh) || + ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciInstance->shedFirstQh)) + { + break; + } + + vltPrevQhPointer = (volatile usb_host_ehci_qh_t *)(horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK); + } + + /* remove the qh from async list */ + if ((vltPrevQhPointer != NULL) && (!(horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE)) && + ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh)) + { + USB_HostEhciStopAsync(ehciInstance); + vltPrevQhPointer->horizontalLinkPointer = + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer; + USB_HostEhciStartAsync(ehciInstance); + } + } + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer = + EHCI_HOST_T_INVALID_VALUE; /* invalid next qh link */ + return USB_HostEhciQhDeinit(ehciInstance, ehciPipePointer); /* de-initialize qh and release qh */ +} + +static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_status_t status = kStatus_USB_Success; + uint32_t frameIndex; + + /* allocate bandwidth */ + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + status = USB_HostBandwidthHsHostAllocateInterrupt(ehciInstance, ehciPipePointer); /* host works as high-speed */ + } + else + { + status = USB_HostBandwidthFslsHostAllocate(ehciInstance, + ehciPipePointer); /* host works as full-speed or low-speed */ + } + + if (status != kStatus_USB_Success) + { + return status; + } + if (USB_HostEhciQhInit(ehciInstance, ehciPipePointer) != kStatus_USB_Success) + { + return kStatus_USB_Error; + } + + /* insert QH to frame list */ + for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += (ehciPipePointer->uframeInterval / 8)) + { + USB_HostEhciAddQhToFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex, + ehciPipePointer->uframeInterval); + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciCloseInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + uint32_t frameIndex; + + /* remove from frame list */ + for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += (ehciPipePointer->uframeInterval / 8)) + { + USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex); + } + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer |= + EHCI_HOST_T_INVALID_VALUE; /* invalid next qh link */ + + return USB_HostEhciQhDeinit(ehciInstance, ehciPipePointer); /* de-initilaze qh and release qh */ +} + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + +static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer; + usb_status_t status = kStatus_USB_Success; + + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + status = USB_HostBandwidthHsHostAllocateIso( + ehciInstance, ehciPipePointer); /* allocate iso bandwidth when host works as high-speed */ + } + else + { + status = USB_HostBandwidthFslsHostAllocate( + ehciInstance, ehciPipePointer); /* allocate iso bandwidth when host works as full-speed or low-speed */ + } + + if (status != kStatus_USB_Success) + { + return status; + } + + /* get usb_host_ehci_iso_t */ + if (ehciInstance->ehciIsoList == NULL) + { + return kStatus_USB_Error; + } + USB_HostEhciLock(); + isoPointer = ehciInstance->ehciIsoList; + ehciInstance->ehciIsoList = ehciInstance->ehciIsoList->next; + USB_HostEhciUnlock(); + isoPointer->lastLinkFrame = 0xFFFF; + ehciPipePointer->ehciQh = isoPointer; + + return status; +} + +static usb_status_t USB_HostEhciCloseIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer; + uint32_t speed; + + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + + if (isoPointer->ehciTransferHead != NULL) + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd list and free them */ +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd list and free them */ +#endif + } + } + + /* release usb_host_ehci_iso_t */ + USB_HostEhciLock(); + isoPointer->next = ehciInstance->ehciIsoList; + ehciInstance->ehciIsoList = isoPointer; + USB_HostEhciUnlock(); + return kStatus_USB_Success; +} + +#endif + +static usb_status_t USB_HostEhciResetIP(usb_host_ehci_instance_t *ehciInstance) +{ + /* reset controller */ + ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RST_MASK; + while (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_RST_MASK) + { + } +/* set host mode */ +#if (ENDIANNESS == USB_LITTLE_ENDIAN) + ehciInstance->ehciIpBase->USBMODE |= 0x03; +#else + ehciInstance->ehciIpBase->USBMODE |= (0x03 | (0x01 << USBHS_USBMODE_ES_SHIFT)); +#endif + /* check frame list size */ + if (!(ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK)) + { +#if ((USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE < 8) || (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE > 1024)) + return kStatus_USB_Error; +#endif +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE & (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE - 1)) + return kStatus_USB_Error; /* frame size must be 1024/512/256/128/64/32/16/8 */ +#endif + } + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t tmp = 0; + + if (ehciInstance->ehciIpBase->HCSPARAMS & USBHS_HCSPARAMS_PPC_MASK) /* Ports have power port switches */ + { + /* only has one port */ + tmp = ehciInstance->ehciIpBase->PORTSC1; + tmp &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (tmp | USBHS_PORTSC1_PP_MASK); /* turn on port power */ + } + + /* set frame list size */ + if (ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK) + { +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE <= 64) + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_FS2_MASK); +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 64) + ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 32) + ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 16) + ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 8) + ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT); +#endif +#else +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 1024) + ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 512) + ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 256) + ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 128) + ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT); +#endif +#endif + } + + /* start the controller */ + ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RS_MASK; + + /* set timer0 */ + ehciInstance->ehciIpBase->GPTIMER0LD = (300 * 1000 - 1); /* 100ms */ + + /* enable interrupt (USB interrupt enable + USB error interrupt enable + port change detect enable + system error + * enable + interrupt on async advance enable) + general purpos Timer 0 Interrupt enable */ + ehciInstance->ehciIpBase->USBINTR |= (0x1000037); + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_qh_t *qhPointer; +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + usb_host_ehci_iso_t *isoPointer; + uint32_t speed; +#endif + uint8_t cancelPipe = 0; + + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + case USB_ENDPOINT_INTERRUPT: + qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + if (qhPointer->ehciTransferHead == NULL) /* there is no transfer to cancel */ + { + return kStatus_USB_Success; + } + if (transfer != NULL) + { + if ((qhPointer->ehciTransferHead == transfer) && + (qhPointer->ehciTransferHead == qhPointer->ehciTransferTail)) /* only has this one transfer */ + { + cancelPipe = 1; + } + else + { + cancelPipe = 0; + } + } + else + { + cancelPipe = 1; + } + if (cancelPipe == 1) /* cancel all pipe */ + { + USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); /* release all the qtd */ + } + else /* cancel one transfer */ + { + USB_HostEhciTransferQtdListDeinit(ehciInstance, ehciPipePointer, transfer); + } + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + if (isoPointer->ehciTransferHead == NULL) /* there is no transfer to cancel */ + { + return kStatus_USB_Success; + } + /* cancel all pipe, don't implement canceling transfer for iso */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd */ +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd */ +#endif + } + break; +#endif + + default: + break; + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl) +{ + usb_status_t status = kStatus_USB_Success; + uint32_t portScRegister; + + switch (busControl) + { + case kUSB_HostBusReset: + /* reset port */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + portScRegister &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK); + while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) + { + } + break; + + case kUSB_HostBusRestart: + ehciInstance->deviceAttached = kEHCIDeviceDetached; + ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */ + break; + + case kUSB_HostBusEnableAttach: /* enable device attach */ + if (ehciInstance->deviceAttached == kEHCIDeviceDetached) + { + ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */ + } + break; + + case kUSB_HostBusDisableAttach: /* disable device attach */ + ehciInstance->ehciIpBase->USBINTR &= (~USBHS_USBINTR_PCE_MASK); /* disable ehci port change interrupt */ + break; +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + case kUSB_HostBusSuspend: + if (ehciInstance->ehciIpBase->PORTSC1 && USBHS_PORTSC1_CCS_MASK) + { + /* set timer1 */ + ehciInstance->ehciIpBase->GPTIMER1LD = (1 * 1000); /* 1ms */ + ehciInstance->ehciIpBase->GPTIMER1CTL |= + (USBHS_GPTIMER0CTL_RUN_MASK | USBHS_GPTIMER0CTL_MODE_MASK | USBHS_GPTIMER0CTL_RST_MASK); + + USB_HostEhciStopAsync(ehciInstance); + USB_HostEhciStopPeriodic(ehciInstance); + while (ehciInstance->ehciIpBase->USBSTS & (USBHS_USBSTS_PS_MASK | USBHS_USBSTS_AS_MASK)) + { + __ASM("nop"); + } + ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKCN_MASK; + ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_WKDS_MASK; + ehciInstance->ehciIpBase->PORTSC1 |= (USBHS_PORTSC1_SUSP_MASK); /* Suspend the device */ + + ehciInstance->matchTick = 0U; + ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_TIE1_MASK); + ehciInstance->busSuspendStatus = kBus_EhciStartSuspend; + } + else + { + status = kStatus_USB_Error; + } + break; + case kUSB_HostBusResume: + ehciInstance->ehciIpBase->PORTSC1 &= ~(USBHS_PORTSC1_SUSP_MASK); /* Clear Suspend bit */ + ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + if (ehciInstance->deviceAttached != kEHCIDeviceDetached) + { + ehciInstance->busSuspendStatus = kBus_EhciStartResume; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciInstance->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciInstance->ehciIpBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); + ehciInstance->ehciIpBase->PORTSC1 |= (USBHS_PORTSC1_FPR_MASK); /* Resume the device */ + } + else + { + status = kStatus_USB_Error; + } + break; +#endif + default: + status = kStatus_USB_Error; + break; + } + return status; +} + +void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance) +{ + /* process async QH */ + usb_host_ehci_pipe_t *ehciPipePointer; + usb_host_ehci_pipe_t *ehciClearPipePointer = NULL; + volatile usb_host_ehci_qh_t *vltQhPointer; + volatile usb_host_ehci_qtd_t *vltQtdPointer; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + uint32_t qtdStatus = 0; +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + volatile usb_host_ehci_itd_t *vltItdPointer; + uint8_t index = 0; +#endif +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + volatile usb_host_ehci_sitd_t *vltSitdPointer; +#endif +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + usb_host_ehci_iso_t *isoPointer; + uint32_t dataLength; + uint32_t speed; +#endif + + ehciPipePointer = ehciInstance->ehciRunningPipeList; /* check all the running pipes */ + while (ehciPipePointer != NULL) + { + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_INTERRUPT: + case USB_ENDPOINT_CONTROL: + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */ + transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */ + while (transfer != NULL) + { + nextTransfer = transfer->next; + /* normal case */ + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; + if ((vltQtdPointer->transferResults[0] & (EHCI_HOST_QTD_IOC_MASK)) && + (!(vltQtdPointer->transferResults[0] & + EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) /* transfer is done */ + { + qtdStatus = (vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_STATUS_ERROR_MASK); + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + + vltQhPointer->ehciTransferHead = transfer->next; + vltQhPointer->timeOutLabel = 0; + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + if (qtdStatus) /* has errors */ + { + if (!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) + { + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + } + if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK) + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferFailed); /* transfer fail */ + } + else + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferStall); /* transfer stall */ + } + } + else + { + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) && + (transfer->setupPacket->bRequest == USB_REQUEST_STANDARD_CLEAR_FEATURE) && + (transfer->setupPacket->bmRequestType == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) && + ((USB_SHORT_FROM_LITTLE_ENDIAN(transfer->setupPacket->wValue) & 0x00FFu) == + USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT)) + { + ehciClearPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciClearPipePointer != NULL) + { + /* only compute bulk and interrupt pipe */ + if (((ehciClearPipePointer->pipeCommon.endpointAddress | + (ehciClearPipePointer->pipeCommon.direction + << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)) == + (uint8_t)(USB_SHORT_FROM_LITTLE_ENDIAN(transfer->setupPacket->wIndex))) && + (ehciClearPipePointer->pipeCommon.deviceHandle == + ehciPipePointer->pipeCommon.deviceHandle)) + { + break; + } + ehciClearPipePointer = + (usb_host_ehci_pipe_t *)ehciClearPipePointer->pipeCommon.next; + } + + if ((ehciClearPipePointer != NULL) && + ((ehciClearPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) || + (ehciClearPipePointer->pipeCommon.pipeType == USB_ENDPOINT_BULK))) + { + ((volatile usb_host_ehci_qh_t *)(ehciClearPipePointer->ehciQh)) + ->transferOverlayResults[0] &= (~EHCI_HOST_QTD_DT_MASK); + } + } + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_Success); /* transfer success */ + } + } + else if ((!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) && + (vltQhPointer->transferOverlayResults[0] & + EHCI_HOST_QH_STATUS_ERROR_MASK)) /* there is error and transfer is done */ + { + qtdStatus = (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QH_STATUS_ERROR_MASK); + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)(vltQhPointer->currentQtdPointer); + + if (((uint32_t)vltQtdPointer & EHCI_HOST_T_INVALID_VALUE) || + (vltQtdPointer == NULL)) /* the error status is unreasonable */ + { + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + } + else + { + /* remove qtd from qh */ + while ((vltQtdPointer != NULL) && (!(vltQtdPointer->transferResults[0] & + EHCI_HOST_QTD_IOC_MASK))) /* find the IOC qtd */ + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; + } + + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + if (vltQtdPointer != NULL) + { + vltQhPointer->nextQtdPointer = vltQtdPointer->nextQtdPointer; + } + + transfer->transferSofar = USB_HostEhciQtdListRelease( + ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + vltQhPointer->ehciTransferHead = transfer->next; + vltQhPointer->timeOutLabel = 0; + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK) + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferFailed); /* transfer fail */ + } + else + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferStall); /* transfer stall */ + } + } + } + else + { + break; + } + transfer = nextTransfer; + } + break; +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + qtdStatus = 0; /* qtdStatus means break here, because there is only one break in while for misra */ + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; /* pipe's usb_host_ehci_iso_t */ + transfer = isoPointer->ehciTransferHead; /* usb_host_ehci_iso_t's transfer */ + while (transfer != NULL) + { + nextTransfer = transfer->next; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, + kUSB_HostGetDeviceSpeed, &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + vltItdPointer = + (volatile usb_host_ehci_itd_t *)(transfer->union2.unitTail); /* transfer's last itd */ + for (index = 0; index < 8; ++index) + { + if (vltItdPointer->transactions[index] & EHCI_HOST_ITD_STATUS_ACTIVE_MASK) + { + break; + } + } + if (index == 8) /* transfer is done */ + { + /* remove itd from frame list and release itd */ + dataLength = USB_HostEhciItdArrayRelease(ehciInstance, + (usb_host_ehci_itd_t *)transfer->union1.unitHead, + (usb_host_ehci_itd_t *)transfer->union2.unitTail); + transfer->transferSofar = dataLength; + isoPointer->ehciTransferHead = transfer->next; + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_Success); /* transfer callback success */ + /* TODO: iso callback error */ + } + else + { + qtdStatus = 1; /* break */ + } +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + vltSitdPointer = + (volatile usb_host_ehci_sitd_t *)(transfer->union2.unitTail); /* transfer's last sitd */ + if (!(vltSitdPointer->transferResults[0] & + EHCI_HOST_SITD_STATUS_ACTIVE_MASK)) /* transfer is done */ + { + /* remove sitd from frame list and release itd */ + dataLength = USB_HostEhciSitdArrayRelease( + ehciInstance, (usb_host_ehci_sitd_t *)transfer->union1.unitHead, + (usb_host_ehci_sitd_t *)transfer->union2.unitTail); + transfer->transferSofar = dataLength; + isoPointer->ehciTransferHead = transfer->next; + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_Success); /* transfer callback success */ + /* TODO: iso callback error */ + } + else + { + qtdStatus = 1; /* break */ + } +#endif + } + if (qtdStatus == 1) + { + break; + } + transfer = nextTransfer; + } + break; +#endif + + default: + break; + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } +} + +static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance) +{ + /* note: only has one port */ + uint32_t portScRegister = ehciInstance->ehciIpBase->PORTSC1; + int32_t sofStart = 0; + int32_t sofCount = 0; + uint32_t index; + + if (portScRegister & USBHS_PORTSC1_CSC_MASK) /* connection status change */ + { + sofStart = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + + /* process CSC bit */ + while (1) + { + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + if (portScRegister & USBHS_PORTSC1_CSC_MASK) + { + /* clear csc bit */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + portScRegister &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_CSC_MASK); + } + sofCount = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + if (((sofCount - sofStart + EHCI_MAX_UFRAME_VALUE + 1) & EHCI_MAX_UFRAME_VALUE) > + (1 * 8)) /* delay 1ms to clear CSC */ + { + break; + } + } + } + + /* process CCS bit */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + if (portScRegister & USBHS_PORTSC1_CCS_MASK) /* process attach */ + { + if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) || + (ehciInstance->deviceAttached == kEHCIDeviceAttached)) + { + return; + } +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); +#endif + for (index = 0; index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY; ++index) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1); + if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK)) + { + break; + } + } + if (index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY) /* CCS is cleared */ + { + ehciInstance->deviceAttached = kEHCIDeviceDetached; + return; + } + /* reset port */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + portScRegister &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK); + while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) + { + } + ehciInstance->firstDeviceSpeed = + ((ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PSPD_MASK) >> USBHS_PORTSC1_PSPD_SHIFT); + /* enable ehci phy disconnection */ + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 1); + } + + /* wait for reset */ + USB_HostEhciDelay(ehciInstance->ehciIpBase, USB_HOST_EHCI_PORT_RESET_DELAY); + /* process attach */ + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_ATTACH); + /* gpt timer start */ + ehciInstance->ehciIpBase->GPTIMER0CTL |= + (USBHS_GPTIMER0CTL_RUN_MASK | USBHS_GPTIMER0CTL_MODE_MASK | USBHS_GPTIMER0CTL_RST_MASK); + ehciInstance->deviceAttached = kEHCIDevicePhyAttached; + } + else + { + if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) || + (ehciInstance->deviceAttached == kEHCIDeviceAttached)) + { +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); +#endif + /* disable ehci phy disconnection */ + USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 0); + /* disable async and periodic */ + USB_HostEhciStopAsync(ehciInstance); + USB_HostEhciStopPeriodic(ehciInstance); + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_DETACH); + } + } +} + +static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + volatile usb_host_ehci_qtd_t *vltQtdPointer; + usb_host_transfer_t *transfer; + uint32_t backValue; + volatile uint32_t *totalBytesAddress = NULL; + usb_host_ehci_pipe_t *ehciPipePointer = ehciInstance->ehciRunningPipeList; + uint8_t timeoutLabel; + + while (ehciPipePointer != NULL) + { + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */ + transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */ + if ((transfer != NULL)) /* there is transfering data */ + { + timeoutLabel = 0; + if (ehciInstance->deviceAttached != kEHCIDeviceAttached) + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; + + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + timeoutLabel = 1; + } + else + { + if (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK) + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQhPointer->currentQtdPointer; + totalBytesAddress = &(vltQhPointer->transferOverlayResults[0]); + } + else + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; + totalBytesAddress = ((uint32_t *)vltQtdPointer + 2); + } + + backValue = + (((*totalBytesAddress) & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> + EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); /* backValue is used for total bytes to transfer */ + if (vltQhPointer->timeOutLabel != backValue) /* use total bytes to reflect the time out */ + { + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + vltQhPointer->timeOutLabel = backValue; + } + else + { + /* time out when the total bytes don't change for the duration + * USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE + */ + (vltQhPointer->timeOutValue)--; + if (vltQhPointer->timeOutValue == 0) + { + /* stop the qh schedule */ + USB_HostEhciStopAsync(ehciInstance); + if (backValue != (((*totalBytesAddress) & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> + EHCI_HOST_QTD_TOTAL_BYTES_SHIFT)) + { + USB_HostEhciStartAsync(ehciInstance); + } + else + { + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + USB_HostEhciStartAsync(ehciInstance); + timeoutLabel = 1; + } + } + } + } + + if (timeoutLabel == 1) + { + /* remove qtd from qh */ + while ((vltQtdPointer != NULL) && + (!(vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_IOC_MASK)) && + (vltQtdPointer != (usb_host_ehci_qtd_t *)vltQhPointer->ehciTransferTail)) + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; + } + if ((vltQtdPointer != NULL) && (!(vltQtdPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE))) + { + vltQhPointer->nextQtdPointer = + vltQtdPointer->nextQtdPointer; /* start qh if there are other qtd that don't belong to + the transfer */ + } + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + + vltQhPointer->ehciTransferHead = transfer->next; + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferFailed); + } + } + break; + default: + break; + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } +} + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance) +{ + if (ehciInstance->deviceAttached != kEHCIDeviceDetached) + { + if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + + if (0 == ehciInstance->matchTick) + { + ehciInstance->matchTick = hostPointer->hwTick; + } + else + { + if ((hostPointer->hwTick - ehciInstance->matchTick) >= 5) + { + ehciInstance->ehciIpBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + ehciInstance->ehciIpBase->USBSTS |= USBHS_USBSTS_SRI_MASK; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +#if 0 + ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_ENVBUSCHG_WKUP_MASK + | USBPHY_CTRL_ENIDCHG_WKUP_MASK + | USBPHY_CTRL_ENDPDMCHG_WKUP_MASK + | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK + ; +#endif +#endif + ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; + + ehciInstance->registerPhyBase->PWD = 0xFFFFFFFFU; + + while (ehciInstance->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK)) + { + __ASM("nop"); + } + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; + ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciInstance->ehciIpBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventSuspended); /* call host callback function */ + ehciInstance->busSuspendStatus = kBus_EhciSuspended; + } + } + } + else if (kBus_EhciStartResume == ehciInstance->busSuspendStatus) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK)) + { + ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKDS_MASK; + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventResumed); /* call host callback function */ + hostPointer->suspendedDevice = NULL; + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); + } + } + else + { + } + } + else + { + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); + } +} +#endif + +usb_status_t USB_HostEhciCreate(uint8_t controllerId, + usb_host_handle upperLayerHandle, + usb_host_controller_handle *controllerHandle) +{ + uint32_t index = 0; + usb_osa_status_t osaStatus; + usb_host_ehci_instance_t *ehciInstance; + uint32_t usbhsBaseAddrs[] = USBHS_BASE_ADDRS; + usb_host_ehci_data_t *usbHostEhciData[] = USB_HOST_EHCI_DATA_ARRAY; + uint8_t *usbHostEhciFrameList[] = USB_HOST_EHCI_FRAME_LIST_ARRAY; + uint32_t *framePointer; + + if ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= (sizeof(usbhsBaseAddrs) / sizeof(usbhsBaseAddrs[0]))) + { + return kStatus_USB_ControllerNotFound; + } + + *controllerHandle = NULL; + ehciInstance = (usb_host_ehci_instance_t *)USB_OsaMemoryAllocate( + sizeof(usb_host_ehci_instance_t)); /* malloc host ehci instance */ + if (ehciInstance == NULL) + { + return kStatus_USB_AllocFail; + } + ehciInstance->controllerId = controllerId; + ehciInstance->hostHandle = upperLayerHandle; + ehciInstance->deviceAttached = kEHCIDeviceDetached; + ehciInstance->ehciIpBase = (USBHS_Type *) + usbhsBaseAddrs[controllerId - kUSB_ControllerEhci0]; /* operate ehci ip through the base address */ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->busSuspendStatus = kBus_EhciIdle; + +#if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciInstance->registerNcBase = (USBNC_Type *)USB_EhciNCGetBase(controllerId); +#endif + +#endif + +#endif + + if (USB_HostEhciResetIP(ehciInstance) != kStatus_USB_Success) /* reset ehci ip */ + { + USB_OsaMemoryFree(ehciInstance); + return kStatus_USB_Error; + } + + /* initialize ehci frame list */ + ehciInstance->ehciFrameList = usbHostEhciFrameList[ehciInstance->controllerId - kUSB_ControllerEhci0]; + + /* initialize ehci units */ + ehciInstance->ehciUnitBase = (uint32_t *)(usbHostEhciData[ehciInstance->controllerId - kUSB_ControllerEhci0]); + /* initialize qh/qtd/itd/sitd/iso list */ + ehciInstance->ehciQhList = (usb_host_ehci_qh_t *)((uint32_t)(ehciInstance->ehciUnitBase)); + ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)((uint32_t)ehciInstance->ehciQhList + + (sizeof(usb_host_ehci_qh_t) * USB_HOST_CONFIG_EHCI_MAX_QH)); + ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)((uint32_t)ehciInstance->ehciQtdHead + + (sizeof(usb_host_ehci_qtd_t) * USB_HOST_CONFIG_EHCI_MAX_QTD)); + ehciInstance->ehciSitdList = ehciInstance->ehciSitdIndexBase = + (usb_host_ehci_sitd_t *)((uint32_t)ehciInstance->ehciItdList + + (sizeof(usb_host_ehci_itd_t) * USB_HOST_CONFIG_EHCI_MAX_ITD)); + ehciInstance->ehciIsoList = (usb_host_ehci_iso_t *)((uint32_t)ehciInstance->ehciSitdList + + (sizeof(usb_host_ehci_sitd_t) * USB_HOST_CONFIG_EHCI_MAX_SITD)); + ehciInstance->ehciPipeIndexBase = + (usb_host_ehci_pipe_t *)((uint32_t)ehciInstance->ehciIsoList + + (sizeof(usb_host_ehci_iso_t) * USB_HOST_EHCI_ISO_NUMBER)); + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QH; ++index) + { + ehciInstance->ehciQhList[index - 1].horizontalLinkPointer = (uint32_t)(&ehciInstance->ehciQhList[index]); + } + ehciInstance->ehciQhList[USB_HOST_CONFIG_EHCI_MAX_QH - 1].horizontalLinkPointer = (uint32_t)NULL; + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QTD; ++index) + { + ehciInstance->ehciQtdHead[index - 1].nextQtdPointer = (uint32_t)(&ehciInstance->ehciQtdHead[index]); + } + ehciInstance->ehciQtdNumber = USB_HOST_CONFIG_EHCI_MAX_QTD; + ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1].nextQtdPointer = (uint32_t)NULL; + ehciInstance->ehciQtdTail = &ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1]; + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_ITD; ++index) + { + ehciInstance->ehciItdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciItdList[index]); + } + ehciInstance->ehciItdNumber = USB_HOST_CONFIG_EHCI_MAX_ITD; + ehciInstance->ehciItdList[USB_HOST_CONFIG_EHCI_MAX_ITD - 1].nextLinkPointer = (uint32_t)NULL; +#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_SITD; ++index) + { + ehciInstance->ehciSitdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciSitdList[index]); + } + ehciInstance->ehciSitdNumber = USB_HOST_CONFIG_EHCI_MAX_SITD; + ehciInstance->ehciSitdList[USB_HOST_CONFIG_EHCI_MAX_SITD - 1].nextLinkPointer = (uint32_t)NULL; +#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + for (index = 1; index < USB_HOST_EHCI_ISO_NUMBER; ++index) + { + ehciInstance->ehciIsoList[index - 1].next = &ehciInstance->ehciIsoList[index]; + } + ehciInstance->ehciIsoList[USB_HOST_EHCI_ISO_NUMBER - 1].next = NULL; +#endif + + /* initialize pipes */ + ehciInstance->ehciPipeList = ehciInstance->ehciPipeIndexBase; + for (index = 1; index < USB_HOST_CONFIG_MAX_PIPES; ++index) + { + ehciInstance->ehciPipeList[index - 1].pipeCommon.next = (usb_host_pipe_t *)&ehciInstance->ehciPipeList[index]; + } + /* initialize mutext */ + osaStatus = USB_OsaMutexCreate(&ehciInstance->ehciMutex); + if (osaStatus != kStatus_USB_OSA_Success) + { +#ifdef HOST_ECHO + usb_echo("ehci mutex init fail\r\n"); +#endif + USB_OsaMemoryFree(ehciInstance); + return kStatus_USB_Error; + } + /* initialize task event */ + osaStatus = USB_OsaEventCreate(&ehciInstance->taskEventHandle, 1); + if (osaStatus != kStatus_USB_OSA_Success) + { +#ifdef HOST_ECHO + usb_echo("ehci event init fail\r\n"); +#endif + USB_OsaMutexDestroy(ehciInstance->ehciMutex); + USB_OsaMemoryFree(ehciInstance); + return kStatus_USB_Error; + } + + /* initialize first qh */ + ehciInstance->shedFirstQh = ehciInstance->ehciQhList; + ehciInstance->ehciQhList = + (usb_host_ehci_qh_t *)(ehciInstance->ehciQhList->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK); + ehciInstance->shedFirstQh->staticEndpointStates[0] |= (1 << EHCI_HOST_QH_H_SHIFT); /* first qh */ + ehciInstance->shedFirstQh->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->horizontalLinkPointer = + (uint32_t)((uint32_t)(ehciInstance->shedFirstQh) | EHCI_HOST_POINTER_TYPE_QH); + + /* initialize periodic list */ + framePointer = (uint32_t *)ehciInstance->ehciFrameList; + for (index = 0; index < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; ++index) + { + framePointer[index] = EHCI_HOST_T_INVALID_VALUE; + } + + USB_HostEhciStartIP(ehciInstance); /* start ehci ip */ + + *controllerHandle = ehciInstance; + + return kStatus_USB_Success; +} + +usb_status_t USB_HostEhciDestory(usb_host_controller_handle controllerHandle) +{ + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + + /* disable all interrupts */ + ehciInstance->ehciIpBase->USBINTR = 0; + /* stop the controller */ + ehciInstance->ehciIpBase->USBCMD = 0; + /* free memory */ + USB_OsaMutexDestroy(ehciInstance->ehciMutex); + USB_OsaEventDestroy(ehciInstance->taskEventHandle); + USB_OsaMemoryFree(ehciInstance); + + return kStatus_USB_Success; +} + +usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit) +{ + usb_host_ehci_pipe_t *ehciPipePointer = NULL; + usb_status_t status; + uint32_t speed; + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + + /* get one pipe */ + USB_HostEhciLock(); + if (ehciInstance->ehciPipeList != NULL) + { + ehciPipePointer = ehciInstance->ehciPipeList; + ehciInstance->ehciPipeList = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } + USB_HostEhciUnlock(); + if (ehciPipePointer == NULL) + { +#ifdef HOST_ECHO + usb_echo("ehci open pipe failed\r\n"); +#endif + return kStatus_USB_Busy; + } + + /* initialize pipe informations */ + USB_HostEhciZeroMem((uint32_t *)ehciPipePointer, sizeof(usb_host_ehci_pipe_t) / 4); + ehciPipePointer->pipeCommon.deviceHandle = pipeInit->devInstance; + ehciPipePointer->pipeCommon.endpointAddress = pipeInit->endpointAddress; + ehciPipePointer->pipeCommon.direction = pipeInit->direction; + ehciPipePointer->pipeCommon.interval = pipeInit->interval; + ehciPipePointer->pipeCommon.maxPacketSize = pipeInit->maxPacketSize; + ehciPipePointer->pipeCommon.pipeType = pipeInit->pipeType; + ehciPipePointer->pipeCommon.numberPerUframe = pipeInit->numberPerUframe; + if (ehciPipePointer->pipeCommon.numberPerUframe == 0) + { + ehciPipePointer->pipeCommon.numberPerUframe = 1; + } + ehciPipePointer->pipeCommon.nakCount = pipeInit->nakCount; + ehciPipePointer->pipeCommon.nextdata01 = 0; + ehciPipePointer->ehciQh = NULL; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) + { + ehciPipePointer->pipeCommon.interval = + (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* iso interval is the power of 2 */ + } + else if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) + { + if (speed == USB_SPEED_HIGH) + { + ehciPipePointer->pipeCommon.interval = + (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* HS interrupt interval is the power of 2 */ + } + else + { + ehciPipePointer->pipeCommon.interval = USB_HostEhciGet2PowerValue( + ehciPipePointer->pipeCommon + .interval); /* FS/LS interrupt interval should be the power of 2, it is used for ehci bandwidth */ + } + } + else + { + } + + /* save the micro-frame interval, it is convenient for the interval process */ + if (speed == USB_SPEED_HIGH) + { + ehciPipePointer->uframeInterval = ehciPipePointer->pipeCommon.interval; + } + else + { + ehciPipePointer->uframeInterval = 8 * ehciPipePointer->pipeCommon.interval; + } + + /* open pipe */ + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_CONTROL: + case USB_ENDPOINT_BULK: + status = USB_HostEhciOpenControlBulk(ehciInstance, ehciPipePointer); + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + status = USB_HostEhciOpenIso(ehciInstance, ehciPipePointer); + break; +#endif + + case USB_ENDPOINT_INTERRUPT: + status = USB_HostEhciOpenInterrupt(ehciInstance, ehciPipePointer); + break; + + default: + status = kStatus_USB_Error; + break; + } + + if (status != kStatus_USB_Success) + { + /* release pipe */ + USB_HostEhciLock(); + ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList; + ehciInstance->ehciPipeList = ehciPipePointer; + USB_HostEhciUnlock(); + return status; + } + + /* add pipe to run pipe list */ + USB_HostEhciLock(); + ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList; + ehciInstance->ehciRunningPipeList = ehciPipePointer; + USB_HostEhciUnlock(); + + *pipeHandle = ehciPipePointer; + return status; +} + +usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle) +{ + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle; + usb_host_pipe_t *prevPointer = NULL; + + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + USB_HostEhciCloseControlBulk(ehciInstance, ehciPipePointer); + break; + + case USB_ENDPOINT_INTERRUPT: + USB_HostEhciCloseInterrupt(ehciInstance, ehciPipePointer); + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + USB_HostEhciCloseIso(ehciInstance, ehciPipePointer); + break; +#endif + + default: + break; + } + + /* delete pipe from run pipe list */ + USB_HostEhciLock(); + prevPointer = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList; + if (prevPointer == (usb_host_pipe_t *)ehciPipePointer) + { + ehciInstance->ehciRunningPipeList = (usb_host_ehci_pipe_t *)(prevPointer->next); + } + else + { + while (prevPointer != NULL) + { + if (prevPointer->next == (usb_host_pipe_t *)ehciPipePointer) + { + prevPointer->next = ehciPipePointer->pipeCommon.next; + break; + } + else + { + prevPointer = prevPointer->next; + } + } + } + USB_HostEhciUnlock(); + + /* release pipe */ + USB_HostEhciLock(); + ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList; + ehciInstance->ehciPipeList = ehciPipePointer; + USB_HostEhciUnlock(); + + return kStatus_USB_Success; +} + +usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle; + usb_status_t status = kStatus_USB_Success; +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + uint32_t speed; +#endif + + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + case USB_ENDPOINT_INTERRUPT: + status = USB_HostEhciQhQtdListInit(ehciInstance, ehciPipePointer, + transfer); /* initialize qtd for control/bulk transfer */ + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + status = USB_HostEhciItdArrayInit(ehciInstance, ehciPipePointer, + transfer); /* initialize itd for iso transfer */ +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + status = USB_HostEhciSitdArrayInit(ehciInstance, ehciPipePointer, + transfer); /* initialize sitd for iso transfer */ +#endif + } + break; +#endif + + default: + break; + } + return status; +} + +usb_status_t USB_HostEhciReadpipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + return USB_HostEhciWritePipe(controllerHandle, pipeHandle, transfer); /* same as write */ +} + +usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, uint32_t ioctlEvent, void *ioctlParam) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + usb_host_cancel_param_t *param; + usb_host_ehci_pipe_t *ehciPipePointer; + volatile usb_host_ehci_qh_t *vltQhPointer; + uint32_t deviceAddress; + + if (controllerHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + switch (ioctlEvent) + { + case kUSB_HostCancelTransfer: /* cancel pipe or one transfer */ + param = (usb_host_cancel_param_t *)ioctlParam; + status = USB_HostEhciCancelPipe(ehciInstance, (usb_host_ehci_pipe_t *)param->pipeHandle, param->transfer); + break; + + case kUSB_HostBusControl: /* bus control */ + status = USB_HostEhciControlBus(ehciInstance, *((uint8_t *)ioctlParam)); + break; + + case kUSB_HostGetFrameNumber: /* get frame number */ + *((uint32_t *)ioctlParam) = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); + break; + + case kUSB_HostUpdateControlEndpointAddress: + ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam; + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* update address */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &deviceAddress); + vltQhPointer->staticEndpointStates[0] |= deviceAddress; + break; + + case kUSB_HostUpdateControlPacketSize: + ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam; + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + USB_HostEhciLock(); + if (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) + { + USB_HostEhciStopAsync(ehciInstance); + /* update max packet size */ + vltQhPointer->staticEndpointStates[0] = + (((vltQhPointer->staticEndpointStates[0]) & (~EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK)) | + ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT)); + USB_HostEhciStartAsync(ehciInstance); + } + else + { + /* update max packet size */ + vltQhPointer->staticEndpointStates[0] = + (((vltQhPointer->staticEndpointStates[0]) & (~EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK)) | + ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT)); + } + USB_HostEhciUnlock(); + break; + + default: + break; + } + return status; +} + +void USB_HostEhciTaskFunction(void *hostHandle) +{ + usb_host_ehci_instance_t *ehciInstance; + uint32_t bitSet; + usb_device_handle deviceHandle; + + if (hostHandle == NULL) + { + return; + } + ehciInstance = (usb_host_ehci_instance_t *)((usb_host_instance_t *)hostHandle)->controllerHandle; + + if (USB_OsaEventWait(ehciInstance->taskEventHandle, 0xFF, 0, 0, &bitSet) == + kStatus_USB_OSA_Success) /* wait all event */ + { + if (bitSet & EHCI_TASK_EVENT_PORT_CHANGE) /* port change */ + { + USB_HostEhciPortChange(ehciInstance); + } + + if (bitSet & EHCI_TASK_EVENT_TIMER0) /* timer0 */ + { + USB_HostEhciTimer0(ehciInstance); + } + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + if (bitSet & EHCI_TASK_EVENT_TIMER1) /* timer1 */ + { + USB_HostEhciTimer1(ehciInstance); + } +#endif + + if (ehciInstance->deviceAttached == kEHCIDeviceAttached) + { + if (bitSet & EHCI_TASK_EVENT_TRANSACTION_DONE) /* transaction done */ + { + USB_HostEhciTransactionDone(ehciInstance); + } + + if (bitSet & EHCI_TASK_EVENT_DEVICE_DETACH) /* device detach */ + { + ehciInstance->ehciIpBase->USBINTR &= + (~USBHS_USBINTR_PCE_MASK); /* disable attach, enable when the detach process is done */ + ehciInstance->deviceAttached = kEHCIDeviceDetached; + USB_HostDetachDevice(ehciInstance->hostHandle, 0, 0); + } + } + else if (ehciInstance->deviceAttached != kEHCIDeviceAttached) + { + if (bitSet & EHCI_TASK_EVENT_DEVICE_ATTACH) /* device is attached */ + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + + if (USB_HostAttachDevice(ehciInstance->hostHandle, ehciInstance->firstDeviceSpeed, 0, 0, 1, + &deviceHandle) == kStatus_USB_Success) + { + ehciInstance->deviceAttached = kEHCIDeviceAttached; + } + } + } + else + { + } + } +} + +void USB_HostEhciIsrFunction(void *hostHandle) +{ + usb_host_ehci_instance_t *ehciInstance; + static uint32_t interruptStatus = 0; + + if (hostHandle == NULL) + { + return; + } + + ehciInstance = (usb_host_ehci_instance_t *)((usb_host_instance_t *)hostHandle)->controllerHandle; + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + if (ehciInstance->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + ehciInstance->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventDetectResume); /* call host callback function */ + + while (!(ehciInstance->registerNcBase->USB_OTGn_PHY_CTRL_0 & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)) + { + } + + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); + if ((kBus_EhciSuspended == ehciInstance->busSuspendStatus)) + { + /* ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; */ + ehciInstance->busSuspendStatus = kBus_EhciStartResume; + } + else + { + } + } + else + { + } +#else + if (ehciInstance->ehciIpBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventDetectResume); /* call host callback function */ + + while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + { + } + ehciInstance->ehciIpBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK; + ehciInstance->ehciIpBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); + if ((kBus_EhciSuspended == ehciInstance->busSuspendStatus)) + { + ehciInstance->busSuspendStatus = kBus_EhciStartResume; + /*ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; */ + } + else + { + } + } + else + { + } +#endif /* FSL_FEATURE_SOC_USBNC_COUNT */ + +#endif /* USB_HOST_CONFIG_LOW_POWER_MODE */ + + interruptStatus = ehciInstance->ehciIpBase->USBSTS; + interruptStatus &= ehciInstance->ehciIpBase->USBINTR; + while (interruptStatus) /* there are usb interrupts */ + { + ehciInstance->ehciIpBase->USBSTS = interruptStatus; /* clear interrupt */ + + if (interruptStatus & USBHS_USBSTS_SRI_MASK) /* SOF interrupt */ + { + } + + if (interruptStatus & USBHS_USBSTS_SEI_MASK) /* system error interrupt */ + { + } + + if ((interruptStatus & USBHS_USBSTS_UI_MASK) || + (interruptStatus & USBHS_USBSTS_UEI_MASK)) /* USB interrupt or USB error interrupt */ + { + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TRANSACTION_DONE); + } + + if (interruptStatus & USBHS_USBSTS_PCI_MASK) /* port change detect interrupt */ + { +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK) + { + if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus) + { + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventNotSuspended); /* call host callback function */ + hostPointer->suspendedDevice = NULL; + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); + } + else + { + } + } +#endif + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_PORT_CHANGE); + } + + if (interruptStatus & USBHS_USBSTS_TI0_MASK) /* timer 0 interrupt */ + { + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER0); + } + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + if (interruptStatus & USBHS_USBSTS_TI1_MASK) /* timer 1 interrupt */ + { + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER1); + } +#endif + + interruptStatus = ehciInstance->ehciIpBase->USBSTS; + interruptStatus &= ehciInstance->ehciIpBase->USBINTR; + } +} + +#endif /* USB_HOST_CONFIG_EHCI */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_ehci.h b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_ehci.h new file mode 100644 index 0000000000000000000000000000000000000000..162d6576cd9aa864ed75d143a07d5685366a8dd3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_ehci.h @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_CONTROLLER_EHCI_H_ +#define _USB_HOST_CONTROLLER_EHCI_H_ + +/******************************************************************************* + * KHCI private public structures, enumerations, macros, functions + ******************************************************************************/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* EHCI host macros */ +#define EHCI_HOST_T_INVALID_VALUE (1U) +#define EHCI_HOST_POINTER_TYPE_ITD (0x00U) +#define EHCI_HOST_POINTER_TYPE_QH (0x00000002U) +#define EHCI_HOST_POINTER_TYPE_SITD (0x00000004U) +#define EHCI_HOST_POINTER_TYPE_FSTN (0x00000006U) +#define EHCI_HOST_POINTER_TYPE_MASK (0x00000006U) +#define EHCI_HOST_POINTER_ADDRESS_MASK (0xFFFFFFE0U) +#define EHCI_HOST_PID_OUT (0U) +#define EHCI_HOST_PID_IN (1U) +#define EHCI_HOST_PID_SETUP (2U) + +#define EHCI_HOST_QH_RL_SHIFT (28U) +#define EHCI_HOST_QH_RL_MASK (0xF0000000U) +#define EHCI_HOST_QH_C_SHIFT (27U) +#define EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT (16U) +#define EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK (0x07FF0000U) +#define EHCI_HOST_QH_H_SHIFT (15U) +#define EHCI_HOST_QH_DTC_SHIFT (14U) +#define EHCI_HOST_QH_EPS_SHIFT (12U) +#define EHCI_HOST_QH_ENDPT_SHIFT (8U) +#define EHCI_HOST_QH_I_SHIFT (7U) +#define EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT (0U) +#define EHCI_HOST_QH_MULT_SHIFT (30U) +#define EHCI_HOST_QH_PORT_NUMBER_SHIFT (23U) +#define EHCI_HOST_QH_HUB_ADDR_SHIFT (16U) +#define EHCI_HOST_QH_UFRAME_CMASK_SHIFT (8U) +#define EHCI_HOST_QH_UFRAME_SMASK_SHIFT (0U) +#define EHCI_HOST_QH_STATUS_ERROR_MASK (0x0000007EU) +#define EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK (0x0000003EU) + +#define EHCI_HOST_QTD_DT_SHIFT (31U) +#define EHCI_HOST_QTD_DT_MASK (0x80000000U) +#define EHCI_HOST_QTD_TOTAL_BYTES_SHIFT (16U) +#define EHCI_HOST_QTD_TOTAL_BYTES_MASK (0x7FFF0000U) +#define EHCI_HOST_QTD_IOC_MASK (0x00008000U) +#define EHCI_HOST_QTD_C_PAGE_SHIFT (12U) +#define EHCI_HOST_QTD_CERR_SHIFT (10U) +#define EHCI_HOST_QTD_CERR_MAX_VALUE (0x00000003U) +#define EHCI_HOST_QTD_PID_CODE_SHIFT (8U) +#define EHCI_HOST_QTD_STATUS_SHIFT (0U) +#define EHCI_HOST_QTD_CURRENT_OFFSET_MASK (0x00000FFFU) +#define EHCI_HOST_QTD_BUFFER_POINTER_SHIFT (12U) +#define EHCI_HOST_QTD_STATUS_ACTIVE_MASK (0x00000080U) +#define EHCI_HOST_QTD_STATUS_MASK (0x000000ffU) +#define EHCI_HOST_QTD_STATUS_ERROR_MASK (0x0000007EU) +#define EHCI_HOST_QTD_STATUS_STALL_ERROR_MASK (0x00000040U) + +#define EHCI_HOST_ITD_STATUS_ACTIVE_MASK (0x80000000U) +#define EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT (16U) +#define EHCI_HOST_ITD_TRANSACTION_LEN_MASK (0x0FFF0000U) +#define EHCI_HOST_ITD_IOC_SHIFT (15U) +#define EHCI_HOST_ITD_PG_SHIFT (12U) +#define EHCI_HOST_ITD_TRANSACTION_OFFSET_SHIFT (0U) +#define EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK (0x00000FFFU) +#define EHCI_HOST_ITD_BUFFER_POINTER_SHIFT (12U) +#define EHCI_HOST_ITD_ENDPT_SHIFT (8U) +#define EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT (0U) +#define EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT (0U) +#define EHCI_HOST_ITD_MULT_SHIFT (0U) +#define EHCI_HOST_ITD_DIRECTION_SHIFT (11U) + +#define EHCI_HOST_SITD_STATUS_ACTIVE_MASK (0x00000080U) +#define EHCI_HOST_SITD_DIRECTION_SHIFT (31U) +#define EHCI_HOST_SITD_PORT_NUMBER_SHIFT (24U) +#define EHCI_HOST_SITD_HUB_ADDR_SHIFT (16U) +#define EHCI_HOST_SITD_ENDPT_SHIFT (8U) +#define EHCI_HOST_SITD_DEVICE_ADDRESS_SHIFT (0U) +#define EHCI_HOST_SITD_CMASK_SHIFT (8U) +#define EHCI_HOST_SITD_SMASK_SHIFT (0U) +#define EHCI_HOST_SITD_TOTAL_BYTES_SHIFT (16U) +#define EHCI_HOST_SITD_TOTAL_BYTES_MASK (0x03FF0000U) +#define EHCI_HOST_SITD_TP_SHIFT (3U) +#define EHCI_HOST_SITD_TCOUNT_SHIFT (0U) +#define EHCI_HOST_SITD_IOC_SHIFT (31U) + +/* register related MACROs */ +#define EHCI_PORTSC1_W1_BITS (0x0000002AU) +#define EHCI_MAX_UFRAME_VALUE (0x00003FFFU) + +/* task event */ +#define EHCI_TASK_EVENT_DEVICE_ATTACH (0x01U) +#define EHCI_TASK_EVENT_TRANSACTION_DONE (0x02U) +#define EHCI_TASK_EVENT_DEVICE_DETACH (0x04U) +#define EHCI_TASK_EVENT_PORT_CHANGE (0x08U) +#define EHCI_TASK_EVENT_TIMER0 (0x10U) +#define EHCI_TASK_EVENT_TIMER1 (0x20U) + +#define USB_HostEhciLock() USB_OsaMutexLock(ehciInstance->ehciMutex) +#define USB_HostEhciUnlock() USB_OsaMutexUnlock(ehciInstance->ehciMutex) + +/******************************************************************************* + * KHCI driver public structures, enumerations, macros, functions + ******************************************************************************/ + +/*! + * @addtogroup usb_host_controller_ehci + * @{ + */ + +/*! @brief The maximum supported ISO pipe number */ +#define USB_HOST_EHCI_ISO_NUMBER USB_HOST_CONFIG_EHCI_MAX_ITD +/*! @brief Check the port connect state delay if the state is unstable */ +#define USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY (101U) +/*! @brief Delay for port reset */ +#define USB_HOST_EHCI_PORT_RESET_DELAY (11U) +/*! @brief The SITD inserts a frame interval for putting more SITD continuously. + * There is an interval when an application sends two FS/LS ISO transfers. + * When the interval is less than the macro, the two transfers are continuous in the frame list. Otherwise, the two + * transfers + * are not continuous. + * For example: + * - Use case 1: when inserting the SITD first, the inserted frame = the current frame value + this MACRO value. + * - Use case 2: when inserting SITD is not first, choose between the last inserted frame value and the + * current frame value according to the following criteria: + * If the interval is less than the MACRO value, the new SITD is continuous with the last SITD. + * If not, the new SITD inserting frame = the current frame value + this MACRO value. + */ +#define USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER (2U) +/*! @brief The ITD inserts a micro-frame interval for putting more ITD continuously. + * There is an interval when an application sends two HS ISO transfers. + * When the interval is less than the macro, the two transfers are continuous in the frame list. Otherwise, the two + * transfers + * are not continuous. + * For example: + * - Use case 1: when inserting ITD first, the inserted micro-frame = the current micro-frame value + this MACRO value. + * - Use case 2: when inserting ITD is not first, choose between the last inserted micro-frame value and the + * current micro-frame value according to the following criteria: + * If the interval is less than this MACRO value, the new ITD is continuous with the last ITD. + * If not, the new ITD inserting micro-frame = the current micro-frame value + this MACRO value. + */ +#define USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER (16U) +/*! @brief Control or bulk transaction timeout value (unit: 100 ms) */ +#define USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE (20U) + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +typedef enum _bus_ehci_suspend_request_state +{ + kBus_EhciIdle = 0U, + kBus_EhciStartSuspend, + kBus_EhciSuspended, + kBus_EhciStartResume, +} bus_ehci_suspend_request_state_t; +#endif + +/*! @brief EHCI state for device attachment/detachment. */ +typedef enum _host_ehci_device_state_ +{ + kEHCIDevicePhyAttached = 1, /*!< Device is physically attached */ + kEHCIDeviceAttached, /*!< Device is attached and initialized */ + kEHCIDeviceDetached, /*!< Device is detached and de-initialized */ +} host_ehci_device_state_t; + +/*! @brief EHCI pipe structure */ +typedef struct _usb_host_ehci_pipe +{ + usb_host_pipe_t pipeCommon; /*!< Common pipe information */ + void *ehciQh; /*!< Control/bulk/interrupt: QH; ISO: usb_host_ehci_iso_t*/ + + /* bandwidth */ + uint16_t uframeInterval; /*!< Micro-frame interval value */ + uint16_t startFrame; /*!< + Bandwidth start frame: its value is from 0 to frame_list. + */ + uint16_t dataTime; /*!< + Bandwidth time value: + - When the host works as HS: it's the data bandwidth value. + - When the host works as FS/LS: + - For FS/LS device, it's the data bandwidth value when transferring the data by FS/LS. + - For HS device, it's the data bandwidth value when transferring the data by HS. + */ + uint16_t startSplitTime; /*!< + Start splitting the bandwidth time value: + - When the host works as HS, it is the start split bandwidth value. + */ + uint16_t completeSplitTime; /*!< + Complete splitting the bandwidth time value: + - When host works as HS, it is the complete split bandwidth value. + */ + uint8_t startUframe; /*!< + Bandwidth start micro-frame: its value is from 0 to 7. + */ + uint8_t uframeSmask; /*!< + Start micro-frame. + - When host works as an HS: + - For FS/LS device, it's the interrupt or ISO transfer start-split mask. + - For HS device, it's the interrupt transfer start micro-frame mask. + - When host works as FS/LS, it's the interrupt and ISO start micro-frame mask + */ + uint8_t uframeCmask; /*!< + Complete micro-frame + - When host works as HS: + - For FS/LS device, it's the interrupt or ISO transfer complete-split mask. + */ +} usb_host_ehci_pipe_t; + +/*! @brief EHCI QH structure. See the USB EHCI specification */ +typedef struct _usb_host_ehci_qh +{ + uint32_t horizontalLinkPointer; /*!< QH specification filed, queue head a horizontal link pointer */ + uint32_t + staticEndpointStates[2]; /*!< QH specification filed, static endpoint state and configuration information */ + uint32_t currentQtdPointer; /*!< QH specification filed, current qTD pointer */ + uint32_t nextQtdPointer; /*!< QH specification filed, next qTD pointer */ + uint32_t alternateNextQtdPointer; /*!< QH specification filed, alternate next qTD pointer */ + uint32_t + transferOverlayResults[6]; /*!< QH specification filed, transfer overlay configuration and transfer results */ + + /* reserved space */ + usb_host_ehci_pipe_t *ehciPipePointer; /*!< EHCI pipe pointer */ + usb_host_transfer_t *ehciTransferHead; /*!< Transfer list head on this QH */ + usb_host_transfer_t *ehciTransferTail; /*!< Transfer list tail on this QH */ + uint16_t timeOutValue; /*!< Its maximum value is USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE. When the value is + zero, the transfer times out. */ + uint16_t timeOutLabel; /*!< It's used to judge the transfer timeout. The EHCI driver maintain the value */ +} usb_host_ehci_qh_t; + +/*! @brief EHCI QTD structure. See the USB EHCI specification. */ +typedef struct _usb_host_ehci_qtd +{ + uint32_t nextQtdPointer; /*!< QTD specification filed, the next QTD pointer */ + uint32_t alternateNextQtdPointer; /*!< QTD specification filed, alternate next QTD pointer */ + uint32_t transferResults[2]; /*!< QTD specification filed, transfer results fields */ + uint32_t bufferPointers[4]; /*!< QTD specification filed, transfer buffer fields */ +} usb_host_ehci_qtd_t; + +/*! @brief EHCI ITD structure. See the USB EHCI specification. */ +typedef struct _usb_host_ehci_itd +{ + uint32_t nextLinkPointer; /*!< ITD specification filed, the next linker pointer */ + uint32_t transactions[8]; /*!< ITD specification filed, transactions information */ + uint32_t bufferPointers[7]; /*!< ITD specification filed, transfer buffer fields */ + + /* add space */ + struct _usb_host_ehci_itd *nextItdPointer; /*!< Next ITD pointer */ + uint32_t frameEntryIndex; /*!< The ITD inserted frame value */ + uint32_t reserved[6]; /*!< Reserved fields for 32 bytes align */ +} usb_host_ehci_itd_t; + +/*! @brief EHCI SITD structure. See the USB EHCI specification. */ +typedef struct _usb_host_ehci_sitd +{ + uint32_t nextLinkPointer; /*!< SITD specification filed, the next linker pointer */ + uint32_t endpointStates[2]; /*!< SITD specification filed, endpoint configuration information */ + uint32_t transferResults[3]; /*!< SITD specification filed, transfer result fields */ + uint32_t backPointer; /*!< SITD specification filed, back pointer */ + + /* reserved space */ + uint16_t frameEntryIndex; /*!< The SITD inserted frame value */ + uint8_t nextSitdIndex; /*!< The next SITD index; Get the next SITD pointer through adding base address with the + index. 0xFF means invalid. */ + uint8_t reserved; /*!< Reserved fields for 32 bytes align */ +} usb_host_ehci_sitd_t; + +/*! @brief EHCI ISO structure; An ISO pipe has an instance of this structure to keep the ISO pipe-specific information. + */ +typedef struct _usb_host_ehci_iso +{ + struct _usb_host_ehci_iso *next; /*!< Next instance pointer */ + usb_host_pipe_t *ehciPipePointer; /*!< This ISO's EHCI pipe pointer */ + usb_host_transfer_t *ehciTransferHead; /*!< Transfer list head on this ISO pipe */ + usb_host_transfer_t *ehciTransferTail; /*!< Transfer list head on this ISO pipe */ + + uint16_t lastLinkFrame; /*!< It means that the inserted frame for ISO ITD/SITD. 0xFFFF is invalid. For ITD, it is a + micro-frame value. For SITD, it is a frame value */ +} usb_host_ehci_iso_t; + +/*! @brief EHCI instance structure */ +typedef struct _usb_host_ehci_instance +{ + usb_host_handle hostHandle; /*!< Related host handle*/ + uint32_t *ehciUnitBase; /*!< Keep the QH/QTD/ITD/SITD buffer pointer for release*/ + uint8_t *ehciFrameList; /*!< The frame list of the current ehci instance*/ + usb_host_ehci_qh_t *ehciQhList; /*!< Idle QH list pointer */ + usb_host_ehci_qtd_t *ehciQtdHead; /*!< Idle QTD list pointer head */ + usb_host_ehci_qtd_t *ehciQtdTail; /*!< Idle QTD list pointer tail (recently used qTD will be used)*/ + usb_host_ehci_itd_t *ehciItdList; /*!< Idle ITD list pointer*/ + usb_host_ehci_sitd_t *ehciSitdIndexBase; /*!< SITD buffer's start pointer*/ + usb_host_ehci_sitd_t *ehciSitdList; /*!< Idle SITD list pointer*/ + usb_host_ehci_iso_t *ehciIsoList; /*!< Idle ISO list pointer*/ + USBHS_Type *ehciIpBase; /*!< EHCI IP base address*/ + usb_host_ehci_qh_t *shedFirstQh; /*!< First async QH*/ + usb_host_ehci_pipe_t *ehciPipeIndexBase; /*!< Pipe buffer's start pointer*/ + usb_host_ehci_pipe_t *ehciPipeList; /*!< Idle pipe list pointer*/ + usb_host_ehci_pipe_t *ehciRunningPipeList; /*!< Running pipe list pointer*/ + usb_osa_mutex_handle ehciMutex; /*!< EHCI mutex*/ + usb_osa_event_handle taskEventHandle; /*!< EHCI task event*/ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + uint64_t matchTick; + USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ +#endif + +#endif + uint8_t controllerId; /*!< EHCI controller ID*/ + uint8_t deviceAttached; /*!< Device attach/detach state, see #host_ehci_device_state_t */ + uint8_t firstDeviceSpeed; /*!< The first device's speed, the controller's work speed*/ + uint8_t ehciItdNumber; /*!< Idle ITD number*/ + uint8_t ehciSitdNumber; /*!< Idle SITD number*/ + uint8_t ehciQtdNumber; /*!< Idle QTD number*/ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + bus_ehci_suspend_request_state_t busSuspendStatus; /*!< Bus Suspend Status*/ +#endif +} usb_host_ehci_instance_t; + +/*! @brief EHCI data structure */ +typedef struct _usb_host_ehci_data +{ +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_QH)) && (USB_HOST_CONFIG_EHCI_MAX_QH > 0U)) + usb_host_ehci_qh_t ehciQh[USB_HOST_CONFIG_EHCI_MAX_QH]; /*!< Idle QH list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_QTD)) && (USB_HOST_CONFIG_EHCI_MAX_QTD > 0U)) + usb_host_ehci_qtd_t ehciQtd[USB_HOST_CONFIG_EHCI_MAX_QTD]; /*!< Idle QTD list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_ITD)) && (USB_HOST_CONFIG_EHCI_MAX_ITD > 0U)) + usb_host_ehci_itd_t ehciItd[USB_HOST_CONFIG_EHCI_MAX_ITD]; /*!< Idle ITD list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_SITD)) && (USB_HOST_CONFIG_EHCI_MAX_SITD > 0U)) + usb_host_ehci_sitd_t ehciSitd[USB_HOST_CONFIG_EHCI_MAX_SITD]; /*!< Idle SITD list array*/ +#endif +#if ((defined(USB_HOST_EHCI_ISO_NUMBER)) && (USB_HOST_EHCI_ISO_NUMBER > 0U)) + usb_host_ehci_iso_t ehciIso[USB_HOST_EHCI_ISO_NUMBER]; /*!< Idle ISO list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_MAX_PIPES)) && (USB_HOST_CONFIG_MAX_PIPES > 0U)) + usb_host_ehci_pipe_t ehciPipe[USB_HOST_CONFIG_MAX_PIPES]; /*!< Idle pipe list array*/ +#endif +} usb_host_ehci_data_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif +/*! + * @name USB host EHCI APIs + * @{ + */ + +/*! + * @brief Creates the USB host EHCI instance. + * + * This function initializes the USB host EHCI controller driver. + * + * @param[in] controllerId The controller ID of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param[in] upperLayerHandle The host level handle. + * @param[out] controllerHandle return the controller instance handle. + * + * @retval kStatus_USB_Success The host is initialized successfully. + * @retval kStatus_USB_AllocFail Allocating memory failed. + * @retval kStatus_USB_Error Host mutex create fail, KHCI/EHCI mutex or KHCI/EHCI event create fail. + * Or, KHCI/EHCI IP initialize fail. + */ +extern usb_status_t USB_HostEhciCreate(uint8_t controllerId, + usb_host_handle upperLayerHandle, + usb_host_controller_handle *controllerHandle); + +/*! + * @brief Destroys the USB host EHCI instance. + * + * This function de-initializes The USB host EHCI controller driver. + * + * @param[in] controllerHandle The controller handle. + * + * @retval kStatus_USB_Success The host is initialized successfully. + */ +extern usb_status_t USB_HostEhciDestory(usb_host_controller_handle controllerHandle); + +/*! + * @brief Opens the USB host pipe. + * + * This function opens a pipe according to the pipe_init_ptr parameter. + * + * @param[in] controllerHandle The controller handle. + * @param[out] pipeHandle The pipe handle pointer, it is used to return the pipe handle. + * @param[in] pipeInit It is used to initialize the pipe. + * + * @retval kStatus_USB_Success The host is initialized successfully. + * @retval kStatus_USB_Error There is no idle pipe. + * Or, there is no idle QH for EHCI. + * Or, bandwidth allocate fail for EHCI. + */ +extern usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit); + +/*! + * @brief Closes the USB host pipe. + * + * This function closes a pipe and releases related resources. + * + * @param[in] controllerHandle The controller handle. + * @param[in] pipeHandle The closing pipe handle. + * + * @retval kStatus_USB_Success The host is initialized successfully. + */ +extern usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle); + +/*! + * @brief Sends data to the pipe. + * + * This function requests to send the transfer to the specified pipe. + * + * @param[in] controllerHandle The controller handle. + * @param[in] pipeHandle The sending pipe handle. + * @param[in] transfer The transfer information. + * + * @retval kStatus_USB_Success Sent successfully. + * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI. + * @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI. + */ +extern usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); + +/*! + * @brief Receives data from the pipe. + * + * This function requests to receive the transfer from the specified pipe. + * + * @param[in] controllerHandle The controller handle. + * @param[in] pipeHandle The receiving pipe handle. + * @param[in] transfer The transfer information. + + * @retval kStatus_USB_Success Send successfully. + * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI. + * @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI. + */ +extern usb_status_t USB_HostEhciReadpipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); + +/*! + * @brief Controls the EHCI. + * + * This function controls the EHCI. + * + * @param[in] controllerHandle The controller handle. + * @param[in] ioctlEvent See enumeration host_bus_control_t. + * @param[in] ioctlParam The control parameter. + * + * @retval kStatus_USB_Success Cancel successfully. + * @retval kStatus_USB_InvalidHandle The controllerHandle is a NULL pointer. + */ +extern usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, + uint32_t ioctlEvent, + void *ioctlParam); + +/*! @}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _USB_HOST_CONTROLLER_EHCI_H_ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_hci.c b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_hci.c new file mode 100644 index 0000000000000000000000000000000000000000..927bf8bd9c398b7973c779b07709916ad2af8004 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_hci.c @@ -0,0 +1,1052 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_common.h" +#include "usb_host.h" +#include "usb_host_hci.h" +#include "usb_host_devices.h" +#include "fsl_device_registers.h" +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#include "fsl_cache.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + +extern uint32_t USB_HostHubGetTotalThinkTime(usb_host_handle hostHandle, uint8_t parentHubNo); + +extern usb_status_t USB_HostHubSuspendDevice(usb_host_handle hostHandle); + +extern usb_status_t USB_HostHubResumeDevice(usb_host_handle hostHandle); +#endif + +/*! + * @brief get the idle host instance. + * + * @return host instance pointer. + */ +static usb_host_instance_t *USB_HostGetInstance(void); + +/*! + * @brief release host instance. + * + * @param hostInstance host instance pointer. + */ +static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance); + +/*! + * @brief get the khci/ehci interface. + * + * @param controllerId controller id. + * @param controllerTable return controller interface structure. + */ +static void USB_HostGetControllerInterface(uint8_t controllerId, + const usb_host_controller_interface_t **controllerTable); + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) +extern void USB_HostEhciTestModeInit(usb_device_handle devHandle); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ +#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS)) +extern void USB_HostIp3516HsTestModeInit(usb_device_handle devHandle); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ +#endif /* USB_HOST_CONFIG_EHCI */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief USB host instance resource */ +usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST]; + +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) +#include "usb_host_ehci.h" +static const usb_host_controller_interface_t s_EhciInterface = \ +{ + USB_HostEhciCreate, USB_HostEhciDestory, USB_HostEhciOpenPipe, USB_HostEhciClosePipe, + USB_HostEhciWritePipe, USB_HostEhciReadpipe, USB_HostEhciIoctl, +}; +#endif /* USB_HOST_CONFIG_EHCI */ + +#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI)) +#include "usb_host_khci.h" +static const usb_host_controller_interface_t s_KhciInterface = \ +{ + USB_HostKhciCreate, USB_HostKhciDestory, USB_HostKhciOpenPipe, USB_HostKhciClosePipe, + USB_HostKhciWritePipe, USB_HostKhciReadpipe, USB_HostKciIoctl, +}; +#endif /* USB_HOST_CONFIG_KHCI */ + +#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U)) +#include "usb_host_ohci.h" +static const usb_host_controller_interface_t s_OhciInterface = \ +{ + USB_HostOhciCreate, USB_HostOhciDestory, USB_HostOhciOpenPipe, USB_HostOhciClosePipe, + USB_HostOhciWritePipe, USB_HostOhciReadPipe, USB_HostOhciIoctl, +}; +#endif /* USB_HOST_CONFIG_OHCI */ + +#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U)) +#include "usb_host_ip3516hs.h" +static const usb_host_controller_interface_t s_Ip3516HsInterface = \ +{ + USB_HostIp3516HsCreate, USB_HostIp3516HsDestory, USB_HostIp3516HsOpenPipe, USB_HostIp3516HsClosePipe, + USB_HostIp3516HsWritePipe, USB_HostIp3516HsReadPipe, USB_HostIp3516HsIoctl, +}; +#endif /* USB_HOST_CONFIG_IP3516HS */ + +USB_DMA_NONINIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE) static uint8_t s_Setupbuffer[USB_HOST_CONFIG_MAX_HOST][USB_HOST_CONFIG_MAX_TRANSFERS][USB_DATA_ALIGN_SIZE_MULTIPLE(8)]; +/******************************************************************************* +* Code +******************************************************************************/ + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : usb_test_mode_init +* Returned Value : None +* Comments : +* This function is called by common class to initialize the class driver. It +* is called in response to a select interface call by application +* +*END*--------------------------------------------------------------------*/ +usb_status_t USB_HostTestModeInit(usb_device_handle deviceHandle) +{ +#if (((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) || \ + ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS))) + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; +#endif + uint32_t productId; + uint32_t vendorId; + + usb_echo("usb host test init\r\n"); + USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDevicePID, &productId); + USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDeviceVID, &vendorId); + usb_echo(" vendor id :0x%x product id:0x%x \r\n", vendorId, productId); + + if ((productId != 0x0200U) && (productId != 0x0101) && (productId != 0x0102) && (productId != 0x0103) && + (productId != 0x0104) && (productId != 0x0105) && (productId != 0x0106) && (productId != 0x0107) && + (productId != 0x0108)) + { + usb_echo("Unsupported Device\r\n"); + } + + if (productId == 0x0200U) + { + usb_echo("PET test device attached\r\n"); + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) + if (hostInstance->controllerTable == &s_EhciInterface) + { + USB_HostEhciTestModeInit(deviceHandle); + } +#elif((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS)) + if (hostInstance->controllerTable == &s_Ip3516HsInterface) + { + USB_HostIp3516HsTestModeInit(deviceHandle); + } +#endif + } + + return kStatus_USB_Success; +} +#endif + +static usb_host_instance_t *USB_HostGetInstance(void) +{ + uint8_t i = 0; + uint32_t index = 0; + USB_OSA_SR_ALLOC(); + USB_OSA_ENTER_CRITICAL(); + for (; i < USB_HOST_CONFIG_MAX_HOST; i++) + { + if (g_UsbHostInstance[i].occupied != 1) + { + uint8_t *buffer = (uint8_t *)&g_UsbHostInstance[i]; + for (uint32_t j = 0U; j < sizeof(usb_host_instance_t); j++) + { + buffer[j] = 0x00U; + } + g_UsbHostInstance[i].occupied = 1; + USB_OSA_EXIT_CRITICAL(); + for (index = 0; index < USB_HOST_CONFIG_MAX_TRANSFERS; ++index) + { + g_UsbHostInstance[i].transferList[index].setupPacket = + (usb_setup_struct_t *)&(s_Setupbuffer[i][index][0]); + } + return &g_UsbHostInstance[i]; + } + } + USB_OSA_EXIT_CRITICAL(); + return NULL; +} + +static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance) +{ + USB_OSA_SR_ALLOC(); + USB_OSA_ENTER_CRITICAL(); + hostInstance->occupied = 0; + USB_OSA_EXIT_CRITICAL(); +} + +static void USB_HostGetControllerInterface(uint8_t controllerId, + const usb_host_controller_interface_t **controllerTable) +{ +#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI)) + if (controllerId == kUSB_ControllerKhci0) + { + *controllerTable = &s_KhciInterface; + } +#endif /* USB_HOST_CONFIG_KHCI */ + +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) + if ((controllerId == kUSB_ControllerEhci0) || (controllerId == kUSB_ControllerEhci1)) + { + *controllerTable = &s_EhciInterface; + } +#endif /* USB_HOST_CONFIG_EHCI */ + +#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U)) + if (controllerId == kUSB_ControllerOhci0) + { + *controllerTable = &s_OhciInterface; + } +#endif /* USB_HOST_CONFIG_OHCI */ + +#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U)) + if (controllerId == kUSB_ControllerIp3516Hs0) + { + *controllerTable = &s_Ip3516HsInterface; + } +#endif /* USB_HOST_CONFIG_IP3516HS */ +} + +usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, host_callback_t callbackFn) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = NULL; + usb_host_transfer_t *transferPrev = NULL; + uint8_t i = 0; + + hostInstance = USB_HostGetInstance(); /* get one host instance */ + if (hostInstance == NULL) + { + return kStatus_USB_InvalidHandle; + } + + /* get khci/ehci API table */ + USB_HostGetControllerInterface(controllerId, &hostInstance->controllerTable); + if (hostInstance->controllerTable == NULL) + { + USB_HostReleaseInstance(hostInstance); + return kStatus_USB_ControllerNotFound; + } + + /* judge the controller interface one time at here */ + if ((hostInstance->controllerTable->controllerCreate == NULL) || + (hostInstance->controllerTable->controllerDestory == NULL) || + (hostInstance->controllerTable->controllerOpenPipe == NULL) || + (hostInstance->controllerTable->controllerClosePipe == NULL) || + (hostInstance->controllerTable->controllerWritePipe == NULL) || + (hostInstance->controllerTable->controllerReadPipe == NULL) || + (hostInstance->controllerTable->controllerIoctl == NULL)) + { + return kStatus_USB_Error; + } + + /* HOST instance init*/ + hostInstance->controllerId = controllerId; + hostInstance->deviceCallback = callbackFn; + hostInstance->deviceList = NULL; + if (kStatus_USB_OSA_Success != USB_OsaMutexCreate(&hostInstance->hostMutex)) + { + USB_HostReleaseInstance(hostInstance); +#ifdef HOST_ECHO + usb_echo("host init: create host mutex fail\r\n"); +#endif + return kStatus_USB_Error; + } + + /* initialize transfer list */ + + hostInstance->transferHead = &hostInstance->transferList[0]; + transferPrev = hostInstance->transferHead; + for (i = 1; i < USB_HOST_CONFIG_MAX_TRANSFERS; ++i) + { + transferPrev->next = &hostInstance->transferList[i]; + transferPrev = transferPrev->next; + } + + /* controller create */ + status = + hostInstance->controllerTable->controllerCreate(controllerId, hostInstance, &(hostInstance->controllerHandle)); + if ((status != kStatus_USB_Success) || (hostInstance->controllerHandle == NULL)) + { + USB_OsaMutexDestroy(hostInstance->hostMutex); + USB_HostReleaseInstance(hostInstance); +#ifdef HOST_ECHO + usb_echo("host init: controller init fail\r\n"); +#endif + return kStatus_USB_Error; + } + + *hostHandle = hostInstance; + return kStatus_USB_Success; +} + +usb_status_t USB_HostDeinit(usb_host_handle hostHandle) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *deviceInstance = NULL; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + /* device list detach */ + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + while (deviceInstance != NULL) + { + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + USB_HostDetachDeviceInternal(hostHandle, deviceInstance); + } + + /* controller instance destory */ + status = hostInstance->controllerTable->controllerDestory(hostInstance->controllerHandle); + hostInstance->controllerHandle = NULL; + if (status != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("host controller destory fail\r\n"); +#endif + } + + /* resource release */ + if (hostInstance->hostMutex) + { + USB_OsaMutexDestroy(hostInstance->hostMutex); + hostInstance->hostMutex = NULL; + } + USB_HostReleaseInstance(hostInstance); + + return status; +} + +usb_status_t USB_HostOpenPipe(usb_host_handle hostHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeInit == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* call controller open pipe interface */ + status = hostInstance->controllerTable->controllerOpenPipe(hostInstance->controllerHandle, pipeHandle, pipeInit); + + return status; +} + +usb_status_t USB_HostClosePipe(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* call controller close pipe interface */ + status = hostInstance->controllerTable->controllerClosePipe(hostInstance->controllerHandle, pipeHandle); + + return status; +} + +usb_status_t USB_HostSend(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize transfer */ + transfer->transferSofar = 0; + transfer->direction = USB_OUT; + + USB_HostLock(); /* This api can be called by host task and app task */ +/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function + */ +#if 0 + if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) + { + USB_HostUnlock(); + return status; + } +#endif +/* call controller write pipe interface */ +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + if (transfer->transferLength > 0) + { + DCACHE_CleanByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); + } +#endif + status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer); + + USB_HostUnlock(); + return status; +} + +usb_status_t USB_HostSendSetup(usb_host_handle hostHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize transfer */ + transfer->transferSofar = 0; + transfer->next = NULL; + transfer->setupStatus = 0; + if ((transfer->setupPacket->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_IN) + { + transfer->direction = USB_IN; + } + else + { + transfer->direction = USB_OUT; + } + + USB_HostLock(); /* This API can be called by host task and application task */ +/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function + */ +#if 0 + if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) + { + USB_HostUnlock(); + return status; + } +#endif +/* call controller write pipe interface */ +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + DCACHE_CleanByRange((uint32_t)&transfer->setupPacket->bmRequestType, sizeof(usb_setup_struct_t)); + if (transfer->transferLength > 0) + { + DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); + } +#endif + status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer); + + USB_HostUnlock(); + return status; +} + +usb_status_t USB_HostRecv(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize transfer */ + transfer->transferSofar = 0; + transfer->direction = USB_IN; + + USB_HostLock(); /* This API can be called by host task and application task */ +/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function + */ +#if 0 + if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) + { + USB_HostUnlock(); + return status; + } +#endif + +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + if (transfer->transferLength > 0) + { + DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); + } +#endif + status = hostInstance->controllerTable->controllerReadPipe(hostInstance->controllerHandle, pipeHandle, transfer); + + USB_HostUnlock(); + return status; +} + +usb_status_t USB_HostCancelTransfer(usb_host_handle hostHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_cancel_param_t cancelParam; + + if ((hostHandle == NULL) || (pipeHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize cancel parameter */ + cancelParam.pipeHandle = pipeHandle; + cancelParam.transfer = transfer; + + /* USB_HostLock(); This api can be called by host task and app task */ + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostCancelTransfer, + &cancelParam); + /* USB_HostUnlock(); */ + + return status; +} + +usb_status_t USB_HostMallocTransfer(usb_host_handle hostHandle, usb_host_transfer_t **transfer) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* get one from the transfer_head */ + USB_HostLock(); + if (hostInstance->transferHead != NULL) + { + *transfer = hostInstance->transferHead; + hostInstance->transferHead = hostInstance->transferHead->next; + USB_HostUnlock(); + return kStatus_USB_Success; + } + else + { + *transfer = NULL; + USB_HostUnlock(); + return kStatus_USB_Error; + } +} + +usb_status_t USB_HostFreeTransfer(usb_host_handle hostHandle, usb_host_transfer_t *transfer) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + if (transfer == NULL) + { + return kStatus_USB_Success; + } + + /* release one to the transfer_head */ + USB_HostLock(); + transfer->next = hostInstance->transferHead; + hostInstance->transferHead = transfer; + USB_HostUnlock(); + return kStatus_USB_Success; +} + +usb_status_t USB_HostHelperGetPeripheralInformation(usb_device_handle deviceHandle, + uint32_t infoCode, + uint32_t *infoValue) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + if ((deviceHandle == NULL) || (infoValue == NULL)) + { + return kStatus_USB_InvalidParameter; + } + + switch (infoCode) + { + case kUSB_HostGetDeviceAddress: /* device address */ + *infoValue = (uint32_t)deviceInstance->setAddress; + break; + + case kUSB_HostGetDeviceControlPipe: /* device control pipe */ + *infoValue = (uint32_t)deviceInstance->controlPipe; + break; + + case kUSB_HostGetHostHandle: /* device host handle */ + *infoValue = (uint32_t)deviceInstance->hostHandle; + break; + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + case kUSB_HostGetDeviceHubNumber: /* device hub address */ + *infoValue = (uint32_t)deviceInstance->hubNumber; + break; + + case kUSB_HostGetDevicePortNumber: /* device port no */ + *infoValue = (uint32_t)deviceInstance->portNumber; + break; + + case kUSB_HostGetDeviceLevel: /* device level */ + *infoValue = (uint32_t)deviceInstance->level; + break; + + case kUSB_HostGetDeviceHSHubNumber: /* device high-speed hub address */ + *infoValue = (uint32_t)deviceInstance->hsHubNumber; + break; + + case kUSB_HostGetDeviceHSHubPort: /* device high-speed hub port no */ + *infoValue = (uint32_t)deviceInstance->hsHubPort; + break; + + case kUSB_HostGetHubThinkTime: /* device hub think time */ + *infoValue = USB_HostHubGetTotalThinkTime(deviceInstance->hostHandle, deviceInstance->hubNumber); + break; +#else + case kUSB_HostGetDeviceHubNumber: /* device hub address */ + case kUSB_HostGetDevicePortNumber: /* device port no */ + case kUSB_HostGetDeviceHSHubNumber: /* device high-speed hub address */ + case kUSB_HostGetDeviceHSHubPort: /* device high-speed hub port no */ + case kUSB_HostGetHubThinkTime: /* device hub think time */ + *infoValue = 0; + break; + case kUSB_HostGetDeviceLevel: /* device level */ + *infoValue = 1; + break; +#endif /* USB_HOST_CONFIG_HUB */ + + case kUSB_HostGetDeviceSpeed: /* device speed */ + *infoValue = (uint32_t)deviceInstance->speed; + break; + + case kUSB_HostGetDevicePID: /* device pid */ + *infoValue = (uint32_t)USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(deviceInstance->deviceDescriptor->idProduct); + break; + + case kUSB_HostGetDeviceVID: /* device vid */ + *infoValue = (uint32_t)USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(deviceInstance->deviceDescriptor->idVendor); + break; + + case kUSB_HostGetDeviceConfigIndex: /* device config index */ + *infoValue = (uint32_t)deviceInstance->configurationValue - 1U; + break; + + case kUSB_HostGetConfigurationDes: /* configuration descriptor pointer */ + *infoValue = (uint32_t)deviceInstance->configurationDesc; + break; + + case kUSB_HostGetConfigurationLength: /* configuration descriptor length */ + *infoValue = (uint32_t)deviceInstance->configurationLen; + break; + + default: + return kStatus_USB_Error; + } + + return kStatus_USB_Success; +} + +usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle interfaceHandle, + uint8_t alternateSetting, + usb_host_interface_t *interface) +{ + uint32_t endPosition; + usb_descriptor_union_t *unionDes; + usb_host_ep_t *epParse; + + if (interfaceHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + if (alternateSetting == 0) + { + return kStatus_USB_InvalidParameter; + } + + /* parse configuration descriptor */ + unionDes = (usb_descriptor_union_t *)((usb_host_interface_t *)interfaceHandle) + ->interfaceDesc; /* interface extend descriptor start */ + endPosition = + (uint32_t)unionDes + + ((usb_host_interface_t *)interfaceHandle)->interfaceExtensionLength; /* interface extend descriptor end */ + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + + /* search for the alternate setting interface descritpor */ + while ((uint32_t)unionDes < endPosition) + { + if (unionDes->interface.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE) + { + if (unionDes->interface.bAlternateSetting == alternateSetting) + { + break; + } + else + { + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + } + else + { + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + } + if ((uint32_t)unionDes >= endPosition) + { + return kStatus_USB_Error; + } + + /* initialize interface handle structure instance */ + interface->interfaceDesc = &unionDes->interface; + interface->alternateSettingNumber = 0; + interface->epCount = 0; + interface->interfaceExtension = NULL; + interface->interfaceExtensionLength = 0; + interface->interfaceIndex = unionDes->interface.bInterfaceNumber; + + /* search for endpoint descriptor start position */ + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPosition) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { + if (interface->interfaceExtension == NULL) + { + interface->interfaceExtension = (uint8_t *)unionDes; + } + interface->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + + /* parse endpoint descriptor */ + if (interface->interfaceDesc->bNumEndpoints != 0) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) || + (interface->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP)) + { +#ifdef HOST_ECHO + usb_echo("interface descriptor error\n"); +#endif + return kStatus_USB_Error; + } + for (; interface->epCount < interface->interfaceDesc->bNumEndpoints; (interface->epCount)++) + { + if (((uint32_t)unionDes >= endPosition) || + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { +#ifdef HOST_ECHO + usb_echo("endpoint descriptor error\n"); +#endif + return kStatus_USB_Error; + } + epParse = (usb_host_ep_t *)&interface->epList[interface->epCount]; + epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes; + epParse->epExtensionLength = 0; + epParse->epExtension = NULL; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPosition) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)) + { + if (epParse->epExtension == NULL) + { + epParse->epExtension = (uint8_t *)unionDes; + } + epParse->epExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + } + } + + return kStatus_USB_Success; +} + +void USB_HostGetVersion(uint32_t *version) +{ + if (version) + { + *version = + (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX); + } +} + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +/* Send BUS or specific device suepend request */ +usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance; + usb_host_device_instance_t *deviceInstance; + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusSuspend; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + hostInstance->suspendedDevice = (void *)deviceHandle; + + if (NULL == deviceHandle) + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + status = USB_HostHubSuspendDevice(hostInstance); +#else + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + deviceInstance = (usb_host_device_instance_t *)deviceHandle; + if (0 == deviceInstance->hubNumber) + { +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, + kUSB_HostBusControl, &type); + } +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + } + else + { + if (kStatus_USB_Success == USB_HostValidateDevice(hostInstance, deviceHandle)) + { + status = USB_HostHubSuspendDevice(hostInstance); + } + } +#endif + } + if (kStatus_USB_Error == status) + { + hostInstance->suspendedDevice = NULL; + } + return status; +} + +/* Send BUS or specific device resume request */ +usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance; + usb_host_device_instance_t *deviceInstance; + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusResume; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostInstance->suspendedDevice != deviceHandle) + { + return kStatus_USB_InvalidParameter; + } + hostInstance->suspendedDevice = (void *)deviceHandle; + + if (NULL == deviceHandle) + { + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + deviceInstance = (usb_host_device_instance_t *)deviceHandle; + if (0 == deviceInstance->hubNumber) + { +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, + kUSB_HostBusControl, &type); + } +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + } + else + { + if (kStatus_USB_Success == USB_HostValidateDevice(hostInstance, deviceHandle)) + { + status = USB_HostHubResumeDevice(hostInstance); + } + } +#endif + } + + return status; +} +#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U)) +/* Send BUS or specific device suepend request */ +usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleepType) +{ + usb_host_instance_t *hostInstance; + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusL1Sleep; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + hostInstance->suspendedDevice = (void *)deviceHandle; + + if (1U == sleepType) + { + /*#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))*/ + /*To do, implete hub L1 suspend device*/ + /*#else*/ + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); + /*#endif*/ + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) +/*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/ +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, + &type); + } + } + if (kStatus_USB_Error == status) + { + hostInstance->suspendedDevice = NULL; + } + return status; +} +/* Send BUS or specific device suepend request */ +usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam) +{ + usb_host_instance_t *hostInstance; + usb_status_t status = kStatus_USB_Error; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostL1Config, lpmParam); + + return status; +} + +/* Send BUS or specific device resume request */ +usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleepType) +{ + usb_host_instance_t *hostInstance; + + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusL1Resume; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + if (1U == sleepType) + { + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) +/*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/ + +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, + &type); + } + } + + return status; +} +#endif +/* Update HW tick(unit is ms) */ +usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick) +{ + usb_host_instance_t *hostInstance; + usb_status_t status = kStatus_USB_Success; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + hostInstance->hwTick = tick; + + return status; +} +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_hci.h b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_hci.h new file mode 100644 index 0000000000000000000000000000000000000000..26b6d4a9c56f7c650999acc1924bbb3dca01e252 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/host/usb_host_hci.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_HCI_H_ +#define _USB_HOST_HCI_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief USB host lock */ +#define USB_HostLock() USB_OsaMutexLock(hostInstance->hostMutex) +/*! @brief USB host unlock */ +#define USB_HostUnlock() USB_OsaMutexUnlock(hostInstance->hostMutex) + +/*! + * @addtogroup usb_host_controller_driver + * @{ + */ + +/*! @brief USB host controller control code */ +typedef enum _usb_host_controller_control +{ + kUSB_HostCancelTransfer = 1U, /*!< Cancel transfer code */ + kUSB_HostBusControl, /*!< Bus control code */ + kUSB_HostGetFrameNumber, /*!< Get frame number code */ + kUSB_HostUpdateControlEndpointAddress, /*!< Update control endpoint address */ + kUSB_HostUpdateControlPacketSize, /*!< Update control endpoint maximum packet size */ + kUSB_HostPortAttachDisable, /*!< Disable the port attach event */ + kUSB_HostPortAttachEnable, /*!< Enable the port attach event */ + kUSB_HostL1Config, /*!< L1 suspend Bus control code */ +} usb_host_controller_control_t; + +/*! @brief USB host controller bus control code */ +typedef enum _usb_host_bus_control +{ + kUSB_HostBusReset = 1U, /*!< Reset bus */ + kUSB_HostBusRestart, /*!< Restart bus */ + kUSB_HostBusEnableAttach, /*!< Enable attach */ + kUSB_HostBusDisableAttach, /*!< Disable attach */ + kUSB_HostBusSuspend, /*!< Suspend BUS */ + kUSB_HostBusResume, /*!< Resume BUS */ + kUSB_HostBusL1SuspendInit, /*!< L1 Suspend BUS */ + kUSB_HostBusL1Sleep, /*!< L1 Suspend BUS */ + kUSB_HostBusL1Resume, /*!< L1 Resume BUS */ +} usb_host_bus_control_t; + +/*! @brief USB host controller interface structure */ +typedef struct _usb_host_controller_interface +{ + usb_status_t (*controllerCreate)( + uint8_t controllerId, + usb_host_handle upperLayerHandle, + usb_host_controller_handle *controllerHandle); /*!< Create a controller instance function prototype*/ + usb_status_t (*controllerDestory)( + usb_host_controller_handle controllerHandle); /*!< Destroy a controller instance function prototype*/ + usb_status_t (*controllerOpenPipe)(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit); /*!< Open a controller pipe function prototype*/ + usb_status_t (*controllerClosePipe)( + usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle); /*!< Close a controller pipe function prototype*/ + usb_status_t (*controllerWritePipe)(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); /*!< Write data to a pipe function prototype*/ + usb_status_t (*controllerReadPipe)(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); /*!< Read data from a pipe function prototype*/ + usb_status_t (*controllerIoctl)(usb_host_controller_handle controllerHandle, + uint32_t ioctlEvent, + void *ioctlParam); /*!< Control a controller function prototype*/ +} usb_host_controller_interface_t; + +/*! @}*/ + +/*! + * @addtogroup usb_host_drv + * @{ + */ + +/*! @brief USB host instance structure */ +typedef struct _usb_host_instance +{ + void *controllerHandle; /*!< The low level controller handle*/ + host_callback_t deviceCallback; /*!< Device attach/detach callback*/ + usb_osa_mutex_handle hostMutex; /*!< Host layer mutex*/ + usb_host_transfer_t transferList[USB_HOST_CONFIG_MAX_TRANSFERS]; /*!< Transfer resource*/ + usb_host_transfer_t *transferHead; /*!< Idle transfer head*/ + const usb_host_controller_interface_t *controllerTable; /*!< KHCI/EHCI interface*/ + void *deviceList; /*!< Device list*/ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + void *suspendedDevice; /*!< Suspended device handle*/ + volatile uint64_t hwTick; /*!< Current hw tick(ms)*/ + uint8_t sleepType; /*!< L1 LPM device handle*/ +#endif + uint8_t addressBitMap[16]; /*!< Used for address allocation. The first bit is the address 1, second bit is the + address 2*/ + uint8_t occupied; /*!< 0 - the instance is not occupied; 1 - the instance is occupied*/ + uint8_t controllerId; /*!< The controller ID*/ +} usb_host_instance_t; + +/*! @}*/ + +#endif /* _USB_HOST_HCI_H_ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/include/usb.h b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb.h new file mode 100644 index 0000000000000000000000000000000000000000..256896b472c96ed5aa4ffa4d72f75f0bff5ec080 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_H__ +#define __USB_H__ + +#include +#include +#include +#include "usb_misc.h" +#include "usb_spec.h" + +/*! + * @addtogroup usb_drv + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Defines USB stack major version */ +#define USB_STACK_VERSION_MAJOR (1U) +/*! @brief Defines USB stack minor version */ +#define USB_STACK_VERSION_MINOR (6U) +/*! @brief Defines USB stack bugfix version */ +#define USB_STACK_VERSION_BUGFIX (3U) + +/*! @brief USB stack version definition */ +#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @brief USB error code */ +typedef enum _usb_status +{ + kStatus_USB_Success = 0x00U, /*!< Success */ + kStatus_USB_Error, /*!< Failed */ + + kStatus_USB_Busy, /*!< Busy */ + kStatus_USB_InvalidHandle, /*!< Invalid handle */ + kStatus_USB_InvalidParameter, /*!< Invalid parameter */ + kStatus_USB_InvalidRequest, /*!< Invalid request */ + kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */ + kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */ + + kStatus_USB_NotSupported, /*!< Configuration is not supported */ + kStatus_USB_Retry, /*!< Enumeration get configuration retry */ + kStatus_USB_TransferStall, /*!< Transfer stalled */ + kStatus_USB_TransferFailed, /*!< Transfer failed */ + kStatus_USB_AllocFail, /*!< Allocation failed */ + kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */ + kStatus_USB_TransferCancel, /*!< The transfer cancelled */ + kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */ + kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */ + kStatus_USB_EHCIAttached, + kStatus_USB_EHCIDetached, +} usb_status_t; + +/*! @brief USB host handle type define */ +typedef void *usb_host_handle; + +/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the + * attached device instance handle*/ +typedef void *usb_device_handle; + +/*! @brief USB OTG handle type define */ +typedef void *usb_otg_handle; + +/*! @brief USB controller ID */ +typedef enum _usb_controller_index +{ + kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ + kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved + to be used in the future. */ + kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ + kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */ + kUSB_ControllerLpcIp3511Fs1 = + 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ + kUSB_ControllerLpcIp3511Hs1 = + 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */ + kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */ + kUSB_ControllerIp3516Hs1 = + 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, this is reserved + to be used in the future. */ +} usb_controller_index_t; + +/** +* @brief USB stack version fields +*/ +typedef struct _usb_version +{ + uint8_t major; /*!< Major */ + uint8_t minor; /*!< Minor */ + uint8_t bugfix; /*!< Bug fix */ +} usb_version_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @} */ + +#endif /* __USB_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_device_config.h b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_device_config.h new file mode 100644 index 0000000000000000000000000000000000000000..551d92edc7e27c12248839ebe7529170da08f9f0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_device_config.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_DEVICE_CONFIG_H_ +#define _USB_DEVICE_CONFIG_H_ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! + * @addtogroup usb_device_configuration + * @{ + */ + +/*! + * @name Hardware instance define + * @{ + */ + +/*! @brief KHCI instance count */ +#define USB_DEVICE_CONFIG_KHCI (0U) + +/*! @brief EHCI instance count */ +#define USB_DEVICE_CONFIG_EHCI (2U) + +/*! @brief LPC USB IP3511 FS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511FS (0U) + +/*! @brief LPC USB IP3511 HS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511HS (0U) + +/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/ +#define USB_DEVICE_CONFIG_NUM \ + (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI + USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) + +/* @} */ + +/*! + * @name class instance define + * @{ + */ + +/*! @brief HID instance count */ +#define USB_DEVICE_CONFIG_HID (0U) + +/*! @brief CDC ACM instance count */ +#define USB_DEVICE_CONFIG_CDC_ACM (1U) + +/*! @brief MSC instance count */ +#define USB_DEVICE_CONFIG_MSC (0U) + +/*! @brief Audio instance count */ +#define USB_DEVICE_CONFIG_AUDIO (0U) + +/*! @brief PHDC instance count */ +#define USB_DEVICE_CONFIG_PHDC (0U) + +/*! @brief Video instance count */ +#define USB_DEVICE_CONFIG_VIDEO (0U) + +/*! @brief CCID instance count */ +#define USB_DEVICE_CONFIG_CCID (0U) + +/*! @brief Printer instance count */ +#define USB_DEVICE_CONFIG_PRINTER (0U) + +/*! @brief DFU instance count */ +#define USB_DEVICE_CONFIG_DFU (0U) + +/* @} */ + +/*! @brief Whether device is self power. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_SELF_POWER (1U) + +/*! @brief How many endpoints are supported in the stack. */ +#define USB_DEVICE_CONFIG_ENDPOINTS (4U) + +/*! @brief Whether the device task is enabled. */ +#define USB_DEVICE_CONFIG_USE_TASK (0U) + +/*! @brief How many the notification message are supported when the device task is enabled. */ +#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U) + +/*! @brief Whether test mode enabled. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (0U) + +/*! @brief Whether device CV test is enabled. */ +#define USB_DEVICE_CONFIG_CV_TEST (0U) + +/*! @brief Whether device compliance test is enabled. If the macro is enabled, + the test mode and CV test macroes will be set.*/ +#define USB_DEVICE_CONFIG_COMPLIANCE_TEST (0U) + +#if ((defined(USB_DEVICE_CONFIG_COMPLIANCE_TEST)) && (USB_DEVICE_CONFIG_COMPLIANCE_TEST > 0U)) + +/*! @brief Undefine the marco USB_DEVICE_CONFIG_USB20_TEST_MODE. */ +#undef USB_DEVICE_CONFIG_USB20_TEST_MODE +/*! @brief Undefine the marco USB_DEVICE_CONFIG_CV_TEST. */ +#undef USB_DEVICE_CONFIG_CV_TEST + +/*! @brief enable the test mode. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (1U) + +/*! @brief enable the CV test */ +#define USB_DEVICE_CONFIG_CV_TEST (1U) + +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) + +/*! @brief The MAX buffer length for the KHCI DMA workaround.*/ +#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U) +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! @brief How many the DTD are supported. */ +#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U) + +/*! @brief Whether the EHCI ID pin detect feature enabled. */ +#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U) +#endif + +/*! @brief Whether the keep alive feature enabled. */ +#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U) + +/*! @brief Whether the transfer buffer is cache-enabled or not. */ +#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (1U) + +/*! @brief Whether the low power mode is enabled or not. */ +#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U) + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! @brief Whether device remote wakeup supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) + +/*! @brief Whether LPM is supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_LPM_L1 (0U) +#else +/*! @brief The device remote wakeup is unsupported. */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) +#endif + +/*! @brief Whether the device detached feature is enabled or not. */ +#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U) + +/*! @brief Whether handle the USB bus error. */ +#define USB_DEVICE_CONFIG_ERROR_HANDLING (0U) + +/* @} */ +/*! @brief rt-thread port alloc */ +#include +#define USB_OSA_SR_ALLOC(...) +/*! @brief rt-thread port enter critical */ +#define USB_OSA_ENTER_CRITICAL rt_enter_critical +/*! @brief rt-thread port exit critical */ +#define USB_OSA_EXIT_CRITICAL rt_exit_critical + +#endif /* _USB_DEVICE_CONFIG_H_ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_ehci.h b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_ehci.h new file mode 100644 index 0000000000000000000000000000000000000000..edc349664347bb525d3a1dee13102d1b77d1a71f --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_ehci.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_EHCI_H__ +#define __USB_EHCI_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Device QH */ +#define USB_DEVICE_EHCI_QH_POINTER_MASK (0xFFFFFFC0U) +#define USB_DEVICE_EHCI_QH_MULT_MASK (0xC0000000U) +#define USB_DEVICE_EHCI_QH_ZLT_MASK (0x20000000U) +#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE_MASK (0x07FF0000U) +#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE (0x00000800U) +#define USB_DEVICE_EHCI_QH_IOS_MASK (0x00008000U) + +/* Device DTD */ +#define USB_DEVICE_ECHI_DTD_POINTER_MASK (0xFFFFFFE0U) +#define USB_DEVICE_ECHI_DTD_TERMINATE_MASK (0x00000001U) +#define USB_DEVICE_ECHI_DTD_PAGE_MASK (0xFFFFF000U) +#define USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK (0x00000FFFU) +#define USB_DEVICE_ECHI_DTD_PAGE_BLOCK (0x00001000U) +#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES_MASK (0x7FFF0000U) +#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES (0x00004000U) +#define USB_DEVICE_ECHI_DTD_IOC_MASK (0x00008000U) +#define USB_DEVICE_ECHI_DTD_MULTIO_MASK (0x00000C00U) +#define USB_DEVICE_ECHI_DTD_STATUS_MASK (0x000000FFU) +#define USB_DEVICE_EHCI_DTD_STATUS_ERROR_MASK (0x00000068U) +#define USB_DEVICE_ECHI_DTD_STATUS_ACTIVE (0x00000080U) +#define USB_DEVICE_ECHI_DTD_STATUS_HALTED (0x00000040U) +#define USB_DEVICE_ECHI_DTD_STATUS_DATA_BUFFER_ERROR (0x00000020U) +#define USB_DEVICE_ECHI_DTD_STATUS_TRANSACTION_ERROR (0x00000008U) + +typedef struct _usb_device_ehci_qh_struct +{ + union + { + volatile uint32_t capabilttiesCharacteristics; + struct + { + volatile uint32_t reserved1 : 15; + volatile uint32_t ios : 1; + volatile uint32_t maxPacketSize : 11; + volatile uint32_t reserved2 : 2; + volatile uint32_t zlt : 1; + volatile uint32_t mult : 2; + } capabilttiesCharacteristicsBitmap; + } capabilttiesCharacteristicsUnion; + volatile uint32_t currentDtdPointer; + volatile uint32_t nextDtdPointer; + union + { + volatile uint32_t dtdToken; + struct + { + volatile uint32_t status : 8; + volatile uint32_t reserved1 : 2; + volatile uint32_t multiplierOverride : 2; + volatile uint32_t reserved2 : 3; + volatile uint32_t ioc : 1; + volatile uint32_t totalBytes : 15; + volatile uint32_t reserved3 : 1; + } dtdTokenBitmap; + } dtdTokenUnion; + volatile uint32_t bufferPointerPage[5]; + volatile uint32_t reserved1; + uint32_t setupBuffer[2]; + uint32_t setupBufferBack[2]; + union + { + uint32_t endpointStatus; + struct + { + uint32_t isOpened : 1; + uint32_t : 31; + } endpointStatusBitmap; + } endpointStatusUnion; + uint32_t reserved2; +} usb_device_ehci_qh_struct_t; + +typedef struct _usb_device_ehci_dtd_struct +{ + volatile uint32_t nextDtdPointer; + union + { + volatile uint32_t dtdToken; + struct + { + volatile uint32_t status : 8; + volatile uint32_t reserved1 : 2; + volatile uint32_t multiplierOverride : 2; + volatile uint32_t reserved2 : 3; + volatile uint32_t ioc : 1; + volatile uint32_t totalBytes : 15; + volatile uint32_t reserved3 : 1; + } dtdTokenBitmap; + } dtdTokenUnion; + volatile uint32_t bufferPointerPage[5]; + union + { + volatile uint32_t reserved; + struct + { + uint32_t originalBufferOffest : 12; + uint32_t originalBufferLength : 19; + uint32_t dtdInvalid : 1; + } originalBufferInfo; + } reservedUnion; +} usb_device_ehci_dtd_struct_t; + +#endif /* __USB_EHCI_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_misc.h b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_misc.h new file mode 100644 index 0000000000000000000000000000000000000000..4efff5372fe1d2638bdd88520c814ef48e74e3ad --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_misc.h @@ -0,0 +1,454 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_MISC_H__ +#define __USB_MISC_H__ + +#define ENDIANNESS USB_LITTLE_ENDIAN +#ifndef ENDIANNESS + +#error ENDIANNESS should be defined, and then rebulid the project. + +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define USB printf */ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +extern int DbgConsole_Printf(const char *fmt_s, ...); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#if defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE < 1) +#define usb_echo printf +#else +#define usb_echo DbgConsole_Printf +#endif + +#if defined(__ICCARM__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED __packed +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED +#endif + +#elif defined(__GNUC__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED __attribute__((__packed__)) +#endif + +#elif defined(__CC_ARM) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED _Pragma("pack(1U)") +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED _Pragma("pack()") +#endif + +#endif + +#define USB_SHORT_GET_LOW(x) (((uint16_t)x) & 0xFFU) +#define USB_SHORT_GET_HIGH(x) ((uint8_t)(((uint16_t)x) >> 8U) & 0xFFU) + +#define USB_LONG_GET_BYTE0(x) ((uint8_t)(((uint32_t)(x))) & 0xFFU) +#define USB_LONG_GET_BYTE1(x) ((uint8_t)(((uint32_t)(x)) >> 8U) & 0xFFU) +#define USB_LONG_GET_BYTE2(x) ((uint8_t)(((uint32_t)(x)) >> 16U) & 0xFFU) +#define USB_LONG_GET_BYTE3(x) ((uint8_t)(((uint32_t)(x)) >> 24U) & 0xFFU) + +#define USB_MEM4_ALIGN_MASK (0x03U) + +/* accessory macro */ +#define USB_MEM4_ALIGN(n) ((n + 3U) & (0xFFFFFFFCu)) +#define USB_MEM32_ALIGN(n) ((n + 31U) & (0xFFFFFFE0u)) +#define USB_MEM64_ALIGN(n) ((n + 63U) & (0xFFFFFFC0u)) + +/* big/little endian */ +#define SWAP2BYTE_CONST(n) ((((n)&0x00FFU) << 8U) | (((n)&0xFF00U) >> 8U)) +#define SWAP4BYTE_CONST(n) \ + ((((n)&0x000000FFU) << 24U) | (((n)&0x0000FF00U) << 8U) | (((n)&0x00FF0000U) >> 8U) | (((n)&0xFF000000U) >> 24U)) + +#define USB_ASSIGN_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + *((uint8_t *)&(n) + 2) = *((uint8_t *)&(m) + 2); \ + *((uint8_t *)&(n) + 3) = *((uint8_t *)&(m) + 3); \ + } + +#define USB_ASSIGN_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + *((uint8_t *)&(n) + 2) = (uint8_t)(m >> 16); \ + *((uint8_t *)&(n) + 3) = (uint8_t)(m >> 24); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + } + +//#if (ENDIANNESS == USB_BIG_ENDIAN) +#if 0 + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) (n) +#define USB_LONG_TO_BIG_ENDIAN(n) (n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) (n) +#define USB_LONG_FROM_BIG_ENDIAN(n) (n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = ((n >> 24U) & 0xFFU); \ + m[2] = ((n >> 16U) & 0xFFU); \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \ + (((uint8_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 24U) & 0xFFU); \ + m[1] = ((n >> 16U) & 0xFFU); \ + m[2] = ((n >> 8U) & 0xFFU); \ + m[3] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \ + (((uint8_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 8U) & 0xFFU); \ + m[1] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \ + ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((n)&0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n)))))) + +#else + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) (n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) (n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) (n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) (n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = ((n >> 24U) & 0xFFU); \ + m[2] = ((n >> 16U) & 0xFFU); \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \ + (((uint8_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 24U) & 0xFFU); \ + m[1] = ((n >> 16U) & 0xFFU); \ + m[2] = ((n >> 8U) & 0xFFU); \ + m[3] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \ + (((uint8_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 8U) & 0xFFU); \ + m[1] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \ + ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((n)&0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n)))))) + +#endif + +/* + * The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack. + * The USB device global variables are put into the section m_usb_global and m_usb_bdt or the section + * .bss.m_usb_global and .bss.m_usb_bdt by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device + * global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM. + * The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of + * the marco can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and + * USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM + * is not less than 2K Bytes. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT means USB device global variables, only including USB_BDT, are put + * into the USB dedicated RAM, the USB_GLOBAL will be put into .bss section. This feature is used for some SOCs, + * the USB dedicated RAM size is not more than 512 Bytes. + */ +#define USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL 1 +#define USB_STACK_DEDICATED_RAM_TYPE_BDT 2 + +#if defined(__ICCARM__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +/* disable misra 19.13 */ +_Pragma("diag_suppress=Pm120") +#define USB_ALIGN_PRAGMA(x) _Pragma(#x) + _Pragma("diag_default=Pm120") + +#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n) + _Pragma("diag_suppress=Pm120") +#define USB_LINK_SECTION_PART(str) _Pragma(#str) +#define USB_LINK_SECTION_SUB(sec) USB_LINK_SECTION_PART(location = #sec) +#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"") +#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"") +#define USB_LINK_USB_GLOBAL_BSS _Pragma("location = \".bss.m_usb_global\"") +#define USB_LINK_USB_BDT_BSS _Pragma("location = \".bss.m_usb_bdt\"") + _Pragma("diag_default=Pm120") +#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"") +#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"") +#elif defined(__CC_ARM) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __weak +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec))) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init)) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init)) +#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global"))) __attribute__((zero_init)) +#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt"))) __attribute__((zero_init)) +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init)) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init)) + +#elif defined(__GNUC__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec))) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @"))) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @"))) +#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global, \"aw\", %nobits @"))) +#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt, \"aw\", %nobits @"))) +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @"))) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @"))) + +#else +#error The tool-chain is not supported. +#endif + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#if ((defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) && (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#elif(defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, 0) +#elif(defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(0, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#else +#define USB_CACHE_LINESIZE 4 +#endif + +#else +#define USB_CACHE_LINESIZE 4 +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#define USB_DATA_ALIGN 64 +#else +#define USB_DATA_ALIGN 4 +#endif + +#define USB_DATA_ALIGN_SIZE MAX(USB_CACHE_LINESIZE, USB_DATA_ALIGN) + +#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) ((n + USB_DATA_ALIGN_SIZE - 1) & (~(USB_DATA_ALIGN_SIZE - 1))) + +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL) + +#define USB_GLOBAL USB_LINK_USB_GLOBAL +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL +#endif + +#elif defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT) + +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif + +#else + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA + +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_BDT USB_LINK_USB_BDT_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif + +#endif + +#define USB_DMA_NONINIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_INIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_INIT_SUB + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONCACHEABLE USB_LINK_NONCACHE_NONINIT_DATA + +#else +#define USB_DMA_DATA_NONCACHEABLE +#endif + +#define USB_GLOBAL_DEDICATED_RAM USB_LINK_USB_GLOBAL + +/* #define USB_RAM_ADDRESS_NONCACHEREG_ALIGNMENT(n, var) AT_NONCACHEABLE_SECTION_ALIGN(var, n) */ +/* #define USB_RAM_ADDRESS_NONCACHEREG(var) AT_NONCACHEABLE_SECTION(var) */ + +#endif /* __USB_MISC_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_spec.h b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_spec.h new file mode 100644 index 0000000000000000000000000000000000000000..d77b7d3598693a8b6302e101ec2deb689bef3f88 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/include/usb_spec.h @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_SPEC_H__ +#define __USB_SPEC_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* USB speed (the value cannot be changed because EHCI QH use the value directly)*/ +#define USB_SPEED_FULL (0x00U) +#define USB_SPEED_LOW (0x01U) +#define USB_SPEED_HIGH (0x02U) + +/* Set up packet structure */ +typedef struct _usb_setup_struct +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} usb_setup_struct_t; + +/* USB standard descriptor endpoint type */ +#define USB_ENDPOINT_CONTROL (0x00U) +#define USB_ENDPOINT_ISOCHRONOUS (0x01U) +#define USB_ENDPOINT_BULK (0x02U) +#define USB_ENDPOINT_INTERRUPT (0x03U) + +/* USB standard descriptor transfer direction (cannot change the value because iTD use the value directly) */ +#define USB_OUT (0U) +#define USB_IN (1U) + +/* USB standard descriptor length */ +#define USB_DESCRIPTOR_LENGTH_DEVICE (0x12U) +#define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U) +#define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU) +#define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U) + +/* USB Device Capability Type Codes */ +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_USB20_EXTENSION (0x02U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_SUPERSPEED (0x03U) + +/* USB standard descriptor type */ +#define USB_DESCRIPTOR_TYPE_DEVICE (0x01U) +#define USB_DESCRIPTOR_TYPE_CONFIGURE (0x02U) +#define USB_DESCRIPTOR_TYPE_STRING (0x03U) +#define USB_DESCRIPTOR_TYPE_INTERFACE (0x04U) +#define USB_DESCRIPTOR_TYPE_ENDPOINT (0x05U) +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER (0x06U) +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION (0x07U) +#define USB_DESCRIPTOR_TYPE_INTERFAACE_POWER (0x08U) +#define USB_DESCRIPTOR_TYPE_OTG (0x09U) +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION (0x0BU) +#define USB_DESCRIPTOR_TYPE_BOS (0x0F) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY (0x10) + +#define USB_DESCRIPTOR_TYPE_HID (0x21U) +#define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U) +#define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U) + +/* USB standard request type */ +#define USB_REQUEST_TYPE_DIR_MASK (0x80U) +#define USB_REQUEST_TYPE_DIR_SHIFT (7U) +#define USB_REQUEST_TYPE_DIR_OUT (0x00U) +#define USB_REQUEST_TYPE_DIR_IN (0x80U) + +#define USB_REQUEST_TYPE_TYPE_MASK (0x60U) +#define USB_REQUEST_TYPE_TYPE_SHIFT (5U) +#define USB_REQUEST_TYPE_TYPE_STANDARD (0U) +#define USB_REQUEST_TYPE_TYPE_CLASS (0x20U) +#define USB_REQUEST_TYPE_TYPE_VENDOR (0x40U) + +#define USB_REQUEST_TYPE_RECIPIENT_MASK (0x1FU) +#define USB_REQUEST_TYPE_RECIPIENT_SHIFT (0U) +#define USB_REQUEST_TYPE_RECIPIENT_DEVICE (0x00U) +#define USB_REQUEST_TYPE_RECIPIENT_INTERFACE (0x01U) +#define USB_REQUEST_TYPE_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQUEST_TYPE_RECIPIENT_OTHER (0x03U) + +/* USB standard request */ +#define USB_REQUEST_STANDARD_GET_STATUS (0x00U) +#define USB_REQUEST_STANDARD_CLEAR_FEATURE (0x01U) +#define USB_REQUEST_STANDARD_SET_FEATURE (0x03U) +#define USB_REQUEST_STANDARD_SET_ADDRESS (0x05U) +#define USB_REQUEST_STANDARD_GET_DESCRIPTOR (0x06U) +#define USB_REQUEST_STANDARD_SET_DESCRIPTOR (0x07U) +#define USB_REQUEST_STANDARD_GET_CONFIGURATION (0x08U) +#define USB_REQUEST_STANDARD_SET_CONFIGURATION (0x09U) +#define USB_REQUEST_STANDARD_GET_INTERFACE (0x0AU) +#define USB_REQUEST_STANDARD_SET_INTERFACE (0x0BU) +#define USB_REQUEST_STANDARD_SYNCH_FRAME (0x0CU) + +/* USB standard request GET Status */ +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT (0U) +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT (1U) + +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_MASK (0x01U) +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_SHIFT (0U) + +#define USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR (0xF000U) + +/* USB standard request CLEAR/SET feature */ +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT (0U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP (1U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE (2U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE (3U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_HNP_SUPPORT (4U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_ALT_HNP_SUPPORT (5U) + +/* USB standard descriptor configure bmAttributes */ +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK (0x80U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_SHIFT (7U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_MASK (0x40U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT (6U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_MASK (0x20U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT (5U) + +/* USB standard descriptor endpoint bmAttributes */ +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK (0x80U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT (7U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT (0U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN (0x80U) + +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK (0x0FU) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK (0x03U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_MASK (0x0CU) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SHFIT (2U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_NO_SYNC (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ASYNC (0x04U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ADAPTIVE (0x08U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SYNC (0x0CU) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_MASK (0x30U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_SHFIT (4U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_DATA_ENDPOINT (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_FEEDBACK_ENDPOINT (0x10U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_IMPLICIT_FEEDBACK_DATA_ENDPOINT (0x20U) + +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK (0x07FFu) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U) + +/* USB standard descriptor otg bmAttributes */ +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_SRP_MASK (0x01u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_HNP_MASK (0x02u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_ADP_MASK (0x04u) + +/* USB standard descriptor device capability usb20 extension bmAttributes */ +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_MASK (0x02U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_SHIFT (1U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U) + + +/* Language structure */ +typedef struct _usb_language +{ + uint8_t **string; /* The Strings descriptor array */ + uint32_t *length; /* The strings descriptor length array */ + uint16_t languageId; /* The language id of current language */ +} usb_language_t; + +typedef struct _usb_language_list +{ + uint8_t *languageString; /* The String 0U pointer */ + uint32_t stringLength; /* The String 0U Length */ + usb_language_t *languageList; /* The language list */ + uint8_t count; /* The language count */ +} usb_language_list_t; + +typedef struct _usb_descriptor_common +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bData[1]; /* Data */ +} usb_descriptor_common_t; + +typedef struct _usb_descriptor_device +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bcdUSB[2]; /* UUSB Specification Release Number in Binary-Coded Decimal, e.g. 0x0200U */ + uint8_t bDeviceClass; /* Class code */ + uint8_t bDeviceSubClass; /* Sub-Class code */ + uint8_t bDeviceProtocol; /* Protocol code */ + uint8_t bMaxPacketSize0; /* Maximum packet size for endpoint zero */ + uint8_t idVendor[2]; /* Vendor ID (assigned by the USB-IF) */ + uint8_t idProduct[2]; /* Product ID (assigned by the manufacturer) */ + uint8_t bcdDevice[2]; /* Device release number in binary-coded decimal */ + uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */ + uint8_t iProduct; /* Index of string descriptor describing product */ + uint8_t iSerialNumber; /* Index of string descriptor describing the device serial number */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} usb_descriptor_device_t; + +typedef struct _usb_descriptor_configuration +{ + uint8_t bLength; /* Descriptor size in bytes = 9U */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2U or 7U */ + uint8_t wTotalLength[2]; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this configuration. */ + uint8_t bConfigurationValue; /* Value to set this configuration. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Configuration characteristics */ + uint8_t bMaxPower; /* Maximum power from bus, 2 mA units */ +} usb_descriptor_configuration_t; + +typedef struct _usb_descriptor_interface +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_descriptor_interface_t; + +typedef struct _usb_descriptor_endpoint +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSize[2]; + uint8_t bInterval; +} usb_descriptor_endpoint_t; + +typedef struct _usb_descriptor_binary_device_object_store +{ + uint8_t bLength; /* Descriptor size in bytes = 5U */ + uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/ + uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/ +} usb_descriptor_bos_t; + +typedef struct _usb_descriptor_usb20_extension +{ + uint8_t bLength; /* Descriptor size in bytes = 7U */ + uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/ + uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/ +} usb_descriptor_usb20_extension_t; + +typedef union _usb_descriptor_union +{ + usb_descriptor_common_t common; /* Common descriptor */ + usb_descriptor_device_t device; /* Device descriptor */ + usb_descriptor_configuration_t configuration; /* Configuration descriptor */ + usb_descriptor_interface_t interface; /* Interface descriptor */ + usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */ +} usb_descriptor_union_t; + +#endif /* __USB_SPEC_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/phy/usb_phy.c b/bsp/imx6ull-artpi-smart/drivers/usb/phy/usb_phy.c new file mode 100644 index 0000000000000000000000000000000000000000..70537b97dc61235b531d42e547e01a929f3629d0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/phy/usb_phy.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_device_registers.h" + +#include + +void *USB_EhciPhyGetBase(uint8_t controllerId) +{ + void *usbPhyBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbphy_base_temp[] = USBPHY_BASE_ADDRS; + uint32_t usbphy_base[] = USBPHY_BASE_ADDRS; + + if (controllerId < kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - kUSB_ControllerEhci0; + + for (instance = 0; instance < (sizeof(usbphy_base_temp) / sizeof(usbphy_base_temp[0])); instance++) + { + if (usbphy_base_temp[instance]) + { + usbphy_base[newinstance++] = usbphy_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + + usbPhyBase = (void *)usbphy_base[controllerId]; +#endif + return usbPhyBase; +} + +/*! + * @brief ehci phy initialization. + * + * This function initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return kStatus_USB_Error; + } + +#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U)) + ANATOP->HW_ANADIG_REG_3P0.RW = + (ANATOP->HW_ANADIG_REG_3P0.RW & + (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) | + ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK; + ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET = + ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK; +#endif + +#if (defined USB_ANALOG) + USB_ANALOG->INSTANCE[controllerId - kUSB_ControllerEhci0].CHRG_DETECT_SET = USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1); +#endif + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; + + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return kStatus_USB_Error; + } + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + +#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U)) + usbPhyBase->CTRL |= USBPHY_CTRL_AUTORESUME_EN_MASK; +#else + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK; +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK; + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD + * pfd clock = 480MHz*18/N, where N=18~35 + * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode + */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */ + + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK; + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK; + while (!(usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK)) + { + } +#endif + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief ehci phy de-initialization. + * + * This function de-initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + */ +void USB_EhciPhyDeinit(uint8_t controllerId) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */ + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */ +#endif +} + +/*! + * @brief ehci phy disconnect detection enable or disable. + * + * This function enable/disable host ehci disconnect detection. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } + + if (enable) + { + usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } + else + { + usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK); + } +#endif +} diff --git a/bsp/imx6ull-artpi-smart/drivers/usb/phy/usb_phy.h b/bsp/imx6ull-artpi-smart/drivers/usb/phy/usb_phy.h new file mode 100644 index 0000000000000000000000000000000000000000..0409f9c8b90afe8d3585b8c8988055c8545a7912 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/usb/phy/usb_phy.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __USB_PHY_H__ +#define __USB_PHY_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +typedef struct _usb_phy_config_struct +{ + uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */ + uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */ + uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */ +} usb_phy_config_struct_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief EHCI PHY get USB phy bass address. + * + * This function is used to get USB phy bass address. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * + * @retval USB phy bass address. + */ +extern void *USB_EhciPhyGetBase(uint8_t controllerId); + +/*! + * @brief EHCI PHY initialization. + * + * This function initializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * @param[in] freq The external input clock. + * + * @retval kStatus_USB_Success Cancel successfully. + * @retval kStatus_USB_Error The freq value is incorrect. + */ +extern uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +extern uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief EHCI PHY deinitialization. + * + * This function deinitializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + */ +extern void USB_EhciPhyDeinit(uint8_t controllerId); + +/*! + * @brief EHCI PHY disconnect detection enable or disable. + * + * This function enable/disable the host EHCI disconnect detection. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); + +#if defined(__cplusplus) +} +#endif + +#endif /* __USB_PHY_H__ */ diff --git a/bsp/imx6ull-artpi-smart/figures/hw_resources.png b/bsp/imx6ull-artpi-smart/figures/hw_resources.png new file mode 100644 index 0000000000000000000000000000000000000000..d835bb588eda4860dadd011eb604400df4bf8072 Binary files /dev/null and b/bsp/imx6ull-artpi-smart/figures/hw_resources.png differ diff --git a/bsp/imx6ull-artpi-smart/libraries/SConscript b/bsp/imx6ull-artpi-smart/libraries/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..4c815c49b835a3a5ea61f337dc17154dd316d7d1 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/Include/cmsis_gcc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..bb89fbba9e40005859e15a8d584e998cbdb6ae59 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..8ca37048bfa3c0dc48f91ade0ad14d7cba447258 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = [] + +path = [cwd + '/Include'] + +group = DefineGroup('libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca.h new file mode 100644 index 0000000000000000000000000000000000000000..47d1e7fbbecca5a08b9e5ea987fc17f52c2042e3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca.h @@ -0,0 +1,50 @@ +/* Copyright (c) 2009 - 2015 ARM LIMITED + Copyright (c) 2016, Freescale Semiconductor, Inc. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA_H +#define __CORE_CA_H + +/*------------------ GNU Compiler ----------------------*/ +#if defined ( __GNUC__ ) + #include "cortexa_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include "cortexa_iar.h" + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CA_H */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca7.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca7.h new file mode 100644 index 0000000000000000000000000000000000000000..4e3a347b967cac375f59cfd3c7c5726bd427e1bb --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca7.h @@ -0,0 +1,1377 @@ +/* Copyright (c) 2009 - 2015 ARM LIMITED + Copyright (c) 2016, Freescale Semiconductor, Inc. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA7_H_GENERIC +#define __CORE_CA7_H_GENERIC + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(__GNUC__) + #define FORCEDINLINE __attribute__((always_inline)) +#else + #define FORCEDINLINE +#endif + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_ca.h" /* Core Instruction and Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA7_H_DEPENDANT +#define __CORE_CA7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved0:4; /*!< bit: 20..23 Reserved */ + uint32_t J:1; /*!< bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CPSR_Type; + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< CPSR: M Mask */ + + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< bit: 0 MMU enable */ + uint32_t A:1; /*!< bit: 1 Alignment check enable */ + uint32_t C:1; /*!< bit: 2 Cache enable */ + uint32_t _reserved0:2; /*!< bit: 3.. 4 Reserved */ + uint32_t CP15BEN:1; /*!< bit: 5 CP15 barrier enable */ + uint32_t _reserved1:1; /*!< bit: 6 Reserved */ + uint32_t B:1; /*!< bit: 7 Endianness model */ + uint32_t _reserved2:2; /*!< bit: 8.. 9 Reserved */ + uint32_t SW:1; /*!< bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< bit: 13 Vectors bit */ + uint32_t RR:1; /*!< bit: 14 Round Robin select */ + uint32_t _reserved3:2; /*!< bit:15..16 Reserved */ + uint32_t HA:1; /*!< bit: 17 Hardware Access flag enable */ + uint32_t _reserved4:1; /*!< bit: 18 Reserved */ + uint32_t WXN:1; /*!< bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< bit: 22 Alignment model */ + uint32_t _reserved5:1; /*!< bit: 23 Reserved */ + uint32_t VE:1; /*!< bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< bit: 25 Exception Endianness */ + uint32_t _reserved6:1; /*!< bit: 26 Reserved */ + uint32_t NMFI:1; /*!< bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< bit: 29 Access flag enable */ + uint32_t TE:1; /*!< bit: 30 Thumb Exception enable */ + uint32_t _reserved7:1; /*!< bit: 31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ + struct + { + uint32_t _reserved0:6; /*!< bit: 0.. 5 Reserved */ + uint32_t SMP:1; /*!< bit: 6 Enables coherent requests to the processor */ + uint32_t _reserved1:3; /*!< bit: 7.. 9 Reserved */ + uint32_t DODMBS:1; /*!< bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + uint32_t _reserved3:12; /*!< bit:16..27 Reserved */ + uint32_t DDI:1; /*!< bit: 28 Disable dual issue */ + uint32_t _reserved7:3; /*!< bit:29..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< ACTLR: DDI Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< ACTLR: L1PCTL Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< ACTLR: L1RADIS Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< ACTLR: DODMBS Mask */ + +#define ACTLR_SMP_Pos 6U /*!< ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< ACTLR: SMP Mask */ + + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t _reserved0:20; /*!< bit: 0..19 Reserved */ + uint32_t cp10:2; /*!< bit:20..21 Access rights for coprocessor 10 */ + uint32_t cp11:2; /*!< bit:22..23 Access rights for coprocessor 11 */ + uint32_t _reserved1:6; /*!< bit:24..29 Reserved */ + uint32_t D32DIS:1; /*!< bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< CPACR: D32DIS Mask */ + +#define CPACR_cp11_Pos 22U /*!< CPACR: cp11 Position */ +#define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /*!< CPACR: cp11 Mask */ + +#define CPACR_cp10_Pos 20U /*!< CPACR: cp10 Position */ +#define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /*!< CPACR: cp10 Mask */ + + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< bit: 4.. 7 Fault on which domain */ + uint32_t _reserved0:2; /*!< bit: 8.. 9 Reserved */ + uint32_t FS1:1; /*!< bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< bit: 12 External abort type */ + uint32_t CM:1; /*!< bit: 13 Cache maintenance fault */ + uint32_t _reserved1:18; /*!< bit:14..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< DFSR: FS1 Mask */ + +#define DFSR_Domain_Pos 4U /*!< DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< DFSR: FS0 Mask */ + + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t _reserved0:6; /*!< bit: 4.. 9 Reserved */ + uint32_t FS1:1; /*!< bit: 10 Fault Status bits bit 4 */ + uint32_t _reserved1:1; /*!< bit: 11 Reserved */ + uint32_t ExT:1; /*!< bit: 12 External abort type */ + uint32_t _reserved2:19; /*!< bit:13..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< IFSR: FS1 Mask */ + +#define IFSR_FS0_Pos 0U /*!< IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< IFSR: FS0 Mask */ + + +/* CP15 Register ISR */ +typedef union +{ + struct + { + uint32_t _reserved0:6; /*!< bit: 0.. 5 Reserved */ + uint32_t F:1; /*!< bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< bit: 8 External abort pending bit */ + uint32_t _reserved1:23; /*!< bit:14..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< ISR: F Mask */ + + +/* Mask and shift a bit field value for use in a register bit range. */ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/* Mask and shift a register value to extract a bit filed value. */ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + + + +/******************************************************************************* + * CP15 Access Functions + ******************************************************************************/ +FORCEDINLINE __STATIC_INLINE uint32_t __get_SCTLR(void) +{ + return __MRC(15, 0, 1, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) +{ + __MCR(15, 0, sctlr, 1, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_ACTLR(void) +{ + return __MRC(15, 0, 1, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_ACTLR(uint32_t actlr) +{ + __MCR(15, 0, actlr, 1, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CPACR(void) +{ + return __MRC(15, 0, 1, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_CPACR(uint32_t cpacr) +{ + __MCR(15, 0, cpacr, 1, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBR0(void) +{ + return __MRC(15, 0, 2, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) +{ + __MCR(15, 0, ttbr0, 2, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBR1(void) +{ + return __MRC(15, 0, 2, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBR1(uint32_t ttbr1) +{ + __MCR(15, 0, ttbr1, 2, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBCR(void) +{ + return __MRC(15, 0, 2, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBCR(uint32_t ttbcr) +{ + __MCR(15, 0, ttbcr, 2, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DACR(void) +{ + return __MRC(15, 0, 3, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DACR(uint32_t dacr) +{ + __MCR(15, 0, dacr, 3, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DFSR(void) +{ + return __MRC(15, 0, 5, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DFSR(uint32_t dfsr) +{ + __MCR(15, 0, dfsr, 5, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_IFSR(void) +{ + return __MRC(15, 0, 5, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_IFSR(uint32_t ifsr) +{ + __MCR(15, 0, ifsr, 5, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DFAR(void) +{ + return __MRC(15, 0, 6, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DFAR(uint32_t dfar) +{ + __MCR(15, 0, dfar, 6, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_IFAR(void) +{ + return __MRC(15, 0, 6, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_IFAR(uint32_t ifar) +{ + __MCR(15, 0, ifar, 6, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_VBAR(void) +{ + return __MRC(15, 0, 12, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_VBAR(uint32_t vbar) +{ + __MCR(15, 0, vbar, 12, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_ISR(void) +{ + return __MRC(15, 0, 12, 1, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_ISR(uint32_t isr) +{ + __MCR(15, 0, isr, 12, 1, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CONTEXTIDR(void) +{ + return __MRC(15, 0, 13, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_CONTEXTIDR(uint32_t contextidr) +{ + __MCR(15, 0, contextidr, 13, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CBAR(void) +{ + return __MRC(15, 4, 15, 0, 0); +} + + +/******************************************************************************* + * L1 Cache Functions + ******************************************************************************/ +#define L1C_INSTRUCTION_CACHE_LINE_SIZE (32U) +#define L1C_DATA_CACHE_LINE_SIZE (64U) + +#define L1C_DATA_CACHE_OP_CLEAN (1U) +#define L1C_DATA_CACHE_OP_INVALIDATE (2U) +#define L1C_DATA_CACHE_OP_CLEAN_INVALIDATE (3U) + +/* Invalidate both intruction cache and branch predictor */ +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateInstructionCacheAll(void) +{ + /* ICIALLU only affects self core. */ + __MCR(15, 0, 0, 7, 5, 0); + /* BPIALL only affects self core. */ + __MCR(15, 0, 0, 7, 5, 6); + /* Ensure completion of the invalidation */ + __DSB(); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateInstructionCacheLine(const void *VirtAddr) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_INSTRUCTION_CACHE_LINE_SIZE - 1); + /* ICIMVAU */ + __MCR(15, 0, base, 7, 5, 1); + /* BPIMVA */ + __MCR(15, 0, base, 7, 5, 7); + /* Ensure completion of the invalidation */ + __DSB(); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateInstructionCacheRange(const void *VirtAddr, uint32_t length) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_INSTRUCTION_CACHE_LINE_SIZE - 1); + uint32_t end = (uint32_t)VirtAddr + length; + + while (base < end) + { + /* ICIMVAU */ + __MCR(15, 0, base, 7, 5, 1); + /* BPIMVA */ + __MCR(15, 0, base, 7, 5, 7); + base += L1C_INSTRUCTION_CACHE_LINE_SIZE; + } + + /* Ensure completion of the invalidation */ + __DSB(); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_EnableInstructionCache() +{ + uint32_t sctlr = __get_SCTLR(); + + if ((sctlr & (SCTLR_I_Msk | SCTLR_Z_Msk)) != (SCTLR_I_Msk | SCTLR_Z_Msk)) + { /* Enable cache and branch predictor */ + L1C_InvalidateInstructionCacheAll(); + sctlr |= SCTLR_I_Msk | SCTLR_Z_Msk; + __set_SCTLR(sctlr); + /* __ISB() is not needed as there's no instruction changes */ + } +} + +FORCEDINLINE __STATIC_INLINE void L1C_DisableInstructionCache() +{ + uint32_t sctlr = __get_SCTLR(); + + if ((sctlr & (SCTLR_I_Msk | SCTLR_Z_Msk)) != 0) + { /* Disable cache and branch predictor */ + sctlr &= ~(SCTLR_I_Msk | SCTLR_Z_Msk); + __set_SCTLR(sctlr); + /* __ISB() is not needed as there's no instruction changes */ + } +} + +FORCEDINLINE __STATIC_INLINE void L1C_OpDataCacheAll(uint32_t operation) +{ + uint32_t clidr, loc, ctype; + uint32_t level; + uint32_t ccsidr, set, ass, setshift, assshift; + uint32_t i, j, reg; + + clidr = __MRC(15, 1, 0, 0, 1); + loc = (clidr >> 24) & 0x7UL; + + for (level = 0; level < loc; level++) + { /* Clean each level */ + ctype = (clidr >> (level * 3)) & 0x7UL; + if (ctype == 2 || /* Data cache only */ + ctype == 3 || /* Separate instruction and data caches */ + ctype == 4) /* Unified cache */ + { + __MCR(15, 2, level << 1, 0, 0, 0); /* Select data cache */ + + ccsidr = __MRC(15, 1, 0, 0, 0); /* Get cache size ID */ + set = ((ccsidr >> 13) & 0x7FFFUL) + 1; + ass = ((ccsidr >> 3) & 0x3FFUL) + 1; + + setshift = (ccsidr & 0x7UL) + 2 + 2; + for (i = 1; i < 10 && ass > (1UL << i); i++) + { + } + assshift = 32 - i; + + for (i = 0; i < ass; i++) + { + for (j = 0; j < set; j++) + { + reg = (i << assshift) | (j << setshift) | (level << 1); + switch (operation) + { + case L1C_DATA_CACHE_OP_CLEAN: + /* DCCSW */ + __MCR(15, 0, reg, 7, 10, 2); + break; + case L1C_DATA_CACHE_OP_INVALIDATE: + /* DCISW */ + __MCR(15, 0, reg, 7, 6, 2); + break; + case L1C_DATA_CACHE_OP_CLEAN_INVALIDATE: + /* DCCISW */ + __MCR(15, 0, reg, 7, 14, 2); + break; + default: + break; + } + } + } + /* Ensure completion of the L1 cache operation */ + __DSB(); + } + } + + /* Ensure completion of the cache operation */ + __DSB(); +} + +/* Invalidate data cache */ +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateDataCacheAll(void) +{ + L1C_OpDataCacheAll(L1C_DATA_CACHE_OP_INVALIDATE); +} + +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateDataCacheLine(const void *VirtAddr) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + /* DCIMVAC */ + __MCR(15, 0, base, 7, 6, 1); + /* Ensure completion of the invalidation */ + __DSB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateDataCacheRange(const void *VirtAddr, uint32_t length) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + uint32_t end = (uint32_t)VirtAddr + length; + + while (base < end) + { + /* DCIMVAC */ + __MCR(15, 0, base, 7, 6, 1); + base += L1C_DATA_CACHE_LINE_SIZE; + } + + /* Ensure completion of the invalidation */ + __DSB(); +} + +/* Clean data cache */ +FORCEDINLINE __STATIC_INLINE void L1C_CleanDataCacheAll(void) +{ + L1C_OpDataCacheAll(L1C_DATA_CACHE_OP_CLEAN); +} + +FORCEDINLINE __STATIC_INLINE void L1C_CleanDataCacheLine(const void *VirtAddr) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + /* DCCMVAC */ + __MCR(15, 0, base, 7, 10, 1); + /* Ensure completion of the clean */ + __DSB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_CleanDataCacheRange(const void *VirtAddr, uint32_t length) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + uint32_t end = (uint32_t)VirtAddr + length; + + while (base < end) + { + /* DCCMVAC */ + __MCR(15, 0, base, 7, 10, 1); + base += L1C_DATA_CACHE_LINE_SIZE; + } + + /* Ensure completion of the clean */ + __DSB(); +} + +/* Clean and invalidate data cache */ +FORCEDINLINE __STATIC_INLINE void L1C_CleanInvalidateDataCacheAll(void) +{ + L1C_OpDataCacheAll(L1C_DATA_CACHE_OP_CLEAN_INVALIDATE); +} + +FORCEDINLINE __STATIC_INLINE void L1C_CleanInvalidateDataCacheLine(const void *VirtAddr) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + /* DCCIMVAC */ + __MCR(15, 0, base, 7, 14, 1); + /* Ensure completion of the clean */ + __DSB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_CleanInvalidateDataCacheRange(const void *VirtAddr, uint32_t length) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + uint32_t end = (uint32_t)VirtAddr + length; + + while (base < end) + { + /* DCCIMVAC */ + __MCR(15, 0, base, 7, 14, 1); + base += L1C_DATA_CACHE_LINE_SIZE; + } + + /* Ensure completion of the clean */ + __DSB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_EnableDataCache() +{ + uint32_t sctlr = __get_SCTLR(); + + if ((sctlr & SCTLR_C_Msk) != SCTLR_C_Msk) + { /* Enable cache */ + L1C_InvalidateDataCacheAll(); + sctlr |= SCTLR_C_Msk; + __set_SCTLR(sctlr); + /* __ISB() is not needed as there's no instruction changes */ + } +} + +FORCEDINLINE __STATIC_INLINE void L1C_DisableDataCache() +{ + uint32_t sctlr = __get_SCTLR(); + + if ((sctlr & SCTLR_C_Msk) != 0) + { /* Disable cache */ + sctlr &= ~SCTLR_C_Msk; + __set_SCTLR(sctlr); + L1C_CleanInvalidateDataCacheAll(); + /* __ISB() is not needed as there's no instruction changes */ + } +} + +/******************************************************************************* + * MMU Functions + ******************************************************************************/ +enum _mmu_memory_type +{ + MMU_MemoryStronglyOrdered = 0U, /*!< TEX: 0, C: 0, B: 0 */ + MMU_MemoryDevice = 1U, /*!< TEX: 0, C: 0, B: 1 */ + MMU_MemoryWriteBackNoWriteAllocate = 3U, /*!< TEX: 0, C: 1, B: 1 */ + MMU_MemoryNonCacheable = 4U, /*!< TEX: 1, C: 0, B: 0 */ + MMU_MemoryWriteBackWriteAllocate = 7U, /*!< TEX: 1, C: 1, B: 1 */ +}; + +enum _mmu_domain_access +{ + MMU_DomainNA = 0U, /*!< No acces. Any access to the domain generates a Domain fault */ + MMU_DomainClient = 1U, /*!< Accesses are checked against the permission bits in the translation tables */ + MMU_DomainManager = 3U, /*!< Accesses are not checked against the permission bits in the translation tables */ +}; + +enum _mmu_access_permission +{ + MMU_AccessNANA = 0U, /*!< No access in both privileged and unprivileged modes */ + MMU_AccessRWNA = 1U, /*!< Read/Write in privileged mode, no access in unprivileged mode */ + MMU_AccessRWRO = 2U, /*!< Read/Write in privileged mode, Read Only in unprivileged mode */ + MMU_AccessRWRW = 3U, /*!< Read/Write in privileged mode, Read/Write in unprivileged mode */ + MMU_AccessRONA = 5U, /*!< Read Only in privileged mode, no access in unprivileged mode */ + MMU_AccessRORO = 7U, /*!< Read Only in privileged mode, Read Only in unprivileged mode */ +}; + +typedef struct _mmu_attribute_t +{ + uint8_t type; /*!< memory type, see _mmu_memory_type */ + uint8_t domain; /*!< memory domain assignment */ + uint8_t accessPerm; /*!< the memory region access permission, see _mmu_access_permission */ + uint8_t shareable:1; /*!< memory region is shareable among multiple cores or system master */ + uint8_t notSecure:1; /*!< translated physical address is in non-secure memory map */ + uint8_t notGlob:1; /*!< the region translation is process specific */ + uint8_t notExec:1; /*!< the memory region cannot execute code */ +} mmu_attribute_t; + +/* L1Table must be 16KB aligned (bit [13:0] all 0) with size 16KB */ +FORCEDINLINE __STATIC_INLINE void MMU_Init(uint32_t *L1Table) +{ + uint32_t L1Base = (uint32_t)L1Table; + + /* Use TTBR translation, with 16KB L1Table size (N=0) */ + __set_TTBCR(0); + + /* Set TTBR0 with inner/outer write back write allocate and not shareable, [4:3]=01, [1]=0, [6,0]=01 */ + __set_TTBR0((L1Base & 0xFFFFC000UL) | 0x9UL); + + /* Set all domains to client */ + __set_DACR(0x55555555UL); + + /* Set PROCID and ASID to 0 */ + __MCR(15, 0, 0, 13, 0, 1); + + /* Set all virtual space to invalid */ + memset(L1Table, 0, 4096*4); +} + +/* L1Table[4096], L2Table[256] */ +/* L2Table == NULL: use L1Table entry */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigPage(uint32_t *L1Table, uint32_t *L2Table, const void *VirtAddr, + uint32_t PhysAddr, const mmu_attribute_t *Attr) +{ + uint32_t index1 = (uint32_t)VirtAddr >> 20; + uint32_t index2 = ((uint32_t)VirtAddr >> 12) & 0xFFUL; + uint32_t descriptor1 = L1Table[index1]; + uint32_t descriptor2 = (PhysAddr & 0xFFFFF000UL) | /* Physical address */ + (Attr->notGlob ? (1UL << 11) : 0) | /* nG */ + (Attr->shareable ? (1UL << 10) : 0) | /* S */ + (Attr->notExec ? 1UL : 0) | /* XN */ + (((Attr->type >> 2) & 7UL) << 6) | /* TEX */ + ((Attr->type & 3UL) << 2) | /* C,B */ + ((Attr->accessPerm & 4UL) << 9) | /* AP[2] */ + ((Attr->accessPerm & 3UL) << 4) | /* AP[1:0] */ + 2UL; /* Small Page */ + + if ((descriptor1 & 3UL) == 1) /* Page table first level already exists */ + { + /* Ignore the parameter and use the descriptor */ + L2Table = (uint32_t *)(descriptor1 & 0xFFFFFC00UL); + L2Table[index2] = descriptor2; + } + else if ((descriptor1 & 3UL) == 0) /* No L2 table available */ + { + L1Table[index1] = ((uint32_t)L2Table & 0xFFFFFC00UL) | /* L2 Table address */ + ((Attr->domain & 15UL) << 5) | /* Domain */ + (Attr->notSecure ? (1UL << 3) : 0) | /* NS */ + 1UL; /* Page Table */ + /* Use L2Table in parameter */ + L2Table[index2] = descriptor2; + } +} + +/* L1Table[4096], L2Table[256] */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigLargePage(uint32_t *L1Table, uint32_t *L2Table, const void *VirtAddr, + uint32_t PhysAddr, const mmu_attribute_t *Attr) +{ + uint32_t i; + uint32_t index1 = (uint32_t)VirtAddr >> 20; + uint32_t index2 = ((uint32_t)VirtAddr >> 12) & 0xF0UL; + uint32_t descriptor1 = L1Table[index1]; + uint32_t descriptor2 = (PhysAddr & 0xFFFF0000UL) | /* Physical address */ + (Attr->notGlob ? (1UL << 11) : 0) | /* nG */ + (Attr->shareable ? (1UL << 10) : 0) | /* S */ + (Attr->notExec ? (1UL << 15) : 0) | /* XN */ + (((Attr->type >> 2) & 7UL) << 12) | /* TEX */ + ((Attr->type & 3UL) << 2) | /* C,B */ + ((Attr->accessPerm & 4UL) << 9) | /* AP[2] */ + ((Attr->accessPerm & 3UL) << 4) | /* AP[1:0] */ + 1UL; /* Large Page */ + + if ((descriptor1 & 3UL) == 1) /* Page table first level already exists */ + { + /* Ignore the parameter and use the descriptor */ + L2Table = (uint32_t *)(descriptor1 & 0xFFFFFC00UL); + for (i = 0; i < 16; i++) + L2Table[index2 + i] = descriptor2; + } + else if ((descriptor1 & 3UL) == 0) /* No L2 table available */ + { + L1Table[index1] = ((uint32_t)L2Table & 0xFFFFFC00UL) | /* L2 Table address */ + ((Attr->domain & 15UL) << 5) | /* Domain */ + (Attr->notSecure ? (1UL << 3) : 0) | /* NS */ + 1UL; /* Page Table */ + /* Use L2Table in parameter */ + for (i = 0; i < 16; i++) + L2Table[index2 + i] = descriptor2; + } +} + +/* L1Table[4096] */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigSection(uint32_t *L1Table, const void *VirtAddr, + uint32_t PhysAddr, const mmu_attribute_t *Attr) +{ + uint32_t index = (uint32_t)VirtAddr >> 20; + uint32_t descriptor = (PhysAddr & 0xFFF00000UL) | /* Physical address */ + (Attr->notSecure ? (1UL << 19) : 0) | /* NS */ + (Attr->notGlob ? (1UL << 17) : 0) | /* nG */ + (Attr->shareable ? (1UL << 16) : 0) | /* S */ + (Attr->notExec ? (1UL << 4) : 0) | /* XN */ + (((Attr->type >> 2) & 7UL) << 12) | /* TEX */ + ((Attr->type & 3UL) << 2) | /* C,B */ + ((Attr->domain & 15UL) << 5) | /* Domain */ + ((Attr->accessPerm & 4UL) << 15) | /* AP[2] */ + ((Attr->accessPerm & 3UL) << 10) | /* AP[1:0] */ + 2UL; /* Section */ + + L1Table[index] = descriptor; +} + +/* L1Table[4096] */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigSuperSection(uint32_t *L1Table, const void *VirtAddr, + uint32_t PhysAddr, const mmu_attribute_t *Attr) +{ + uint32_t i; + uint32_t index = ((uint32_t)VirtAddr >> 20) & 0xFF0UL; + uint32_t descriptor = (PhysAddr & 0xFF000000UL) | /* Physical address */ + (Attr->notSecure ? (1UL << 19) : 0) | /* NS */ + (Attr->notGlob ? (1UL << 17) : 0) | /* nG */ + (Attr->shareable ? (1UL << 16) : 0) | /* S */ + (Attr->notExec ? (1UL << 4) : 0) | /* XN */ + (((Attr->type >> 2) & 7UL) << 12) | /* TEX */ + ((Attr->type & 3UL) << 2) | /* C,B */ + /* Supersection has fixed domain 0 */ + ((Attr->accessPerm & 4UL) << 15) | /* AP[2] */ + ((Attr->accessPerm & 3UL) << 10) | /* AP[1:0] */ + 2; /* Section */ + + for (i = 0; i < 16; i++) + L1Table[index + i] = descriptor; +} + +FORCEDINLINE __STATIC_INLINE uint32_t * MMU_GetL1Table(void) +{ + return (uint32_t *)(__get_TTBR0() & 0xFFFFC000UL); +} + +FORCEDINLINE __STATIC_INLINE void MMU_SetL1Table(uint32_t *L1Table) +{ + /* update L1Table base address without changing other attributes */ + __set_TTBR0(((uint32_t)L1Table & 0xFFFFC000UL) | (__get_TTBR0() & 0x3FFFUL)); +} + +FORCEDINLINE __STATIC_INLINE uint32_t * MMU_GetL2Table(const void *VirtAddr) +{ + uint32_t index1 = (uint32_t)VirtAddr >> 20; + uint32_t descriptor1; + uint32_t *L1Table = MMU_GetL1Table(); + uint32_t *L2Table = NULL; + + descriptor1 = L1Table[index1]; + if ((descriptor1 & 3UL) == 1) /* Page */ + L2Table = (uint32_t *)(descriptor1 & 0xFFFFFC00UL); + + return L2Table; +} + +FORCEDINLINE __STATIC_INLINE void MMU_SetContext(uint32_t procid, uint32_t asid) +{ + uint32_t reg = (procid << 8) | (asid & 0xFFUL); + + __MCR(15, 0, reg, 13, 0, 1); +} + +/* access: _mmu_domain_access */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigDomain(uint32_t domain, uint32_t access) +{ + uint32_t dacr = __get_DACR(); + uint32_t mask = 3UL << ((domain & 0xFUL) * 2); + uint32_t reg = (dacr & ~mask) | ((access & 3) << ((domain & 0xFUL) * 2)); + + __set_DACR(reg); +} + +FORCEDINLINE __STATIC_INLINE void MMU_InvalidateTLB(void) +{ + /* TLBIALL only affects self core */ + __MCR(15, 0, 0, 8, 7, 0); + __DSB(); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void MMU_Disable(void) +{ + uint32_t sctlr = __get_SCTLR(); + + sctlr &= ~SCTLR_M_Msk; + __set_SCTLR(sctlr); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void MMU_Enable(void) +{ + uint32_t sctlr = __get_SCTLR(); + + MMU_InvalidateTLB(); + sctlr |= SCTLR_M_Msk; + __set_SCTLR(sctlr); + __ISB(); +} + +/******************************************************************************* + * GIC Functions + ******************************************************************************/ +typedef struct +{ + uint32_t RESERVED0[1024]; + __IOM uint32_t D_CTLR; /*!< Offset: 0x1000 (R/W) Distributor Control Register */ + __IM uint32_t D_TYPER; /*!< Offset: 0x1004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t D_IIDR; /*!< Offset: 0x1008 (R/ ) Distributor Implementer Identification Register */ + uint32_t RESERVED1[29]; + __IOM uint32_t D_IGROUPR[16]; /*!< Offset: 0x1080 - 0x0BC (R/W) Interrupt Group Registers */ + uint32_t RESERVED2[16]; + __IOM uint32_t D_ISENABLER[16]; /*!< Offset: 0x1100 - 0x13C (R/W) Interrupt Set-Enable Registers */ + uint32_t RESERVED3[16]; + __IOM uint32_t D_ICENABLER[16]; /*!< Offset: 0x1180 - 0x1BC (R/W) Interrupt Clear-Enable Registers */ + uint32_t RESERVED4[16]; + __IOM uint32_t D_ISPENDR[16]; /*!< Offset: 0x1200 - 0x23C (R/W) Interrupt Set-Pending Registers */ + uint32_t RESERVED5[16]; + __IOM uint32_t D_ICPENDR[16]; /*!< Offset: 0x1280 - 0x2BC (R/W) Interrupt Clear-Pending Registers */ + uint32_t RESERVED6[16]; + __IOM uint32_t D_ISACTIVER[16]; /*!< Offset: 0x1300 - 0x33C (R/W) Interrupt Set-Active Registers */ + uint32_t RESERVED7[16]; + __IOM uint32_t D_ICACTIVER[16]; /*!< Offset: 0x1380 - 0x3BC (R/W) Interrupt Clear-Active Registers */ + uint32_t RESERVED8[16]; + __IOM uint8_t D_IPRIORITYR[512]; /*!< Offset: 0x1400 - 0x5FC (R/W) Interrupt Priority Registers */ + uint32_t RESERVED9[128]; + __IOM uint8_t D_ITARGETSR[512]; /*!< Offset: 0x1800 - 0x9FC (R/W) Interrupt Targets Registers */ + uint32_t RESERVED10[128]; + __IOM uint32_t D_ICFGR[32]; /*!< Offset: 0x1C00 - 0xC7C (R/W) Interrupt configuration registers */ + uint32_t RESERVED11[32]; + __IM uint32_t D_PPISR; /*!< Offset: 0x1D00 (R/ ) Private Peripheral Interrupt Status Register */ + __IM uint32_t D_SPISR[15]; /*!< Offset: 0x1D04 - 0xD3C (R/ ) Shared Peripheral Interrupt Status Registers */ + uint32_t RESERVED12[112]; + __OM uint32_t D_SGIR; /*!< Offset: 0x1F00 ( /W) Software Generated Interrupt Register */ + uint32_t RESERVED13[3]; + __IOM uint8_t D_CPENDSGIR[16]; /*!< Offset: 0x1F10 - 0xF1C (R/W) SGI Clear-Pending Registers */ + __IOM uint8_t D_SPENDSGIR[16]; /*!< Offset: 0x1F20 - 0xF2C (R/W) SGI Set-Pending Registers */ + uint32_t RESERVED14[40]; + __IM uint32_t D_PIDR4; /*!< Offset: 0x1FD0 (R/ ) Peripheral ID4 Register */ + __IM uint32_t D_PIDR5; /*!< Offset: 0x1FD4 (R/ ) Peripheral ID5 Register */ + __IM uint32_t D_PIDR6; /*!< Offset: 0x1FD8 (R/ ) Peripheral ID6 Register */ + __IM uint32_t D_PIDR7; /*!< Offset: 0x1FDC (R/ ) Peripheral ID7 Register */ + __IM uint32_t D_PIDR0; /*!< Offset: 0x1FE0 (R/ ) Peripheral ID0 Register */ + __IM uint32_t D_PIDR1; /*!< Offset: 0x1FE4 (R/ ) Peripheral ID1 Register */ + __IM uint32_t D_PIDR2; /*!< Offset: 0x1FE8 (R/ ) Peripheral ID2 Register */ + __IM uint32_t D_PIDR3; /*!< Offset: 0x1FEC (R/ ) Peripheral ID3 Register */ + __IM uint32_t D_CIDR0; /*!< Offset: 0x1FF0 (R/ ) Component ID0 Register */ + __IM uint32_t D_CIDR1; /*!< Offset: 0x1FF4 (R/ ) Component ID1 Register */ + __IM uint32_t D_CIDR2; /*!< Offset: 0x1FF8 (R/ ) Component ID2 Register */ + __IM uint32_t D_CIDR3; /*!< Offset: 0x1FFC (R/ ) Component ID3 Register */ + + __IOM uint32_t C_CTLR; /*!< Offset: 0x2000 (R/W) CPU Interface Control Register */ + __IOM uint32_t C_PMR; /*!< Offset: 0x2004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t C_BPR; /*!< Offset: 0x2008 (R/W) Binary Point Register */ + __IM uint32_t C_IAR; /*!< Offset: 0x200C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t C_EOIR; /*!< Offset: 0x2010 ( /W) End Of Interrupt Register */ + __IM uint32_t C_RPR; /*!< Offset: 0x2014 (R/ ) Running Priority Register */ + __IM uint32_t C_HPPIR; /*!< Offset: 0x2018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t C_ABPR; /*!< Offset: 0x201C (R/W) Aliased Binary Point Register */ + __IM uint32_t C_AIAR; /*!< Offset: 0x2020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t C_AEOIR; /*!< Offset: 0x2024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t C_AHPPIR; /*!< Offset: 0x2028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + uint32_t RESERVED15[41]; + __IOM uint32_t C_APR0; /*!< Offset: 0x20D0 (R/W) Active Priority Register */ + uint32_t RESERVED16[3]; + __IOM uint32_t C_NSAPR0; /*!< Offset: 0x20E0 (R/W) Non-secure Active Priority Register */ + uint32_t RESERVED17[6]; + __IM uint32_t C_IIDR; /*!< Offset: 0x20FC (R/ ) CPU Interface Identification Register */ + uint32_t RESERVED18[960]; + __OM uint32_t C_DIR; /*!< Offset: 0x3000 ( /W) Deactivate Interrupt Register */ +} GIC_Type; + + +/* For simplicity, we only use group0 of GIC */ +FORCEDINLINE __STATIC_INLINE void GIC_Init(void) +{ + uint32_t i; + uint32_t irqRegs; + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + irqRegs = (gic->D_TYPER & 0x1FUL) + 1; + + /* On POR, all SPI is in group 0, level-sensitive and using 1-N model */ + + /* Disable all PPI, SGI and SPI */ + for (i = 0; i < irqRegs; i++) + gic->D_ICENABLER[i] = 0xFFFFFFFFUL; + + /* Make all interrupts have higher priority */ + gic->C_PMR = (0xFFUL << (8 - __GIC_PRIO_BITS)) & 0xFFUL; + + /* No subpriority, all priority level allows preemption */ + gic->C_BPR = 7 - __GIC_PRIO_BITS; + + /* Enable group0 distribution */ + gic->D_CTLR = 1UL; + + /* Enable group0 signaling */ + gic->C_CTLR = 1UL; +} + +FORCEDINLINE __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->D_ISENABLER[((uint32_t)(int32_t)IRQn) >> 5] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + +FORCEDINLINE __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->D_ICENABLER[((uint32_t)(int32_t)IRQn) >> 5] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + +/* Return IRQ number (and CPU source in SGI case) */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_AcknowledgeIRQ(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return gic->C_IAR & 0x1FFFUL; +} + +/* value should be got from GIC_AcknowledgeIRQ() */ +FORCEDINLINE __STATIC_INLINE void GIC_DeactivateIRQ(uint32_t value) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->C_EOIR = value; +} + +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetRunningPriority(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return gic->C_RPR & 0xFFUL; +} + +FORCEDINLINE __STATIC_INLINE void GIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->C_BPR = PriorityGroup & 0x7UL; +} + +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetPriorityGrouping(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return gic->C_BPR & 0x7UL; +} + +FORCEDINLINE __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8UL - __GIC_PRIO_BITS)) & (uint32_t)0xFFUL); +} + +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return(((uint32_t)gic->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)] >> (8UL - __GIC_PRIO_BITS))); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_gcc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..408afbbf6ebefba261f5f4d9c7b3e12b3cb293b1 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_gcc.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEXA_GCC_H +#define __CORTEXA_GCC_H + +#include "cmsis_gcc.h" + +#define __STRINGIFY(x) #x + +#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \ + __ASM volatile ("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : : "r" (src) ) + +#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \ + ({ \ + uint32_t __dst; \ + __ASM volatile ("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : "=r" (__dst) ); \ + __dst; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_APSR(uint32_t apsr) +{ + __ASM volatile ("MSR apsr, %0" : : "r" (apsr) : "cc"); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc"); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void) +{ + uint32_t result; + + __ASM volatile ("VMRS %0, fpexc" : "=r" (result) ); + return result; +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc)); +} + +#endif /* __CORTEXA_GCC_H */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_iar.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_iar.h new file mode 100644 index 0000000000000000000000000000000000000000..e9a70d8ea0de27c6e94a79b7b1b00858db78fb6b --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_iar.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEXA_IAR_H +#define __CORTEXA_IAR_H + +#ifdef __cplusplus +/* FIXME: work around the IAR CPP compiling issue in Cortex-A support */ +#define __get_PSR() 0 +#endif + +#include + +static inline uint32_t __get_FPEXC(void) +{ + uint32_t result; + + __ASM volatile ("VMRS %0, fpexc" : "=r" (result) ); + return result; +} + +static inline void __set_FPEXC(uint32_t fpexc) +{ + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc)); +} + +#endif /* __CORTEXA_IAR_H */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..8ca37048bfa3c0dc48f91ade0ad14d7cba447258 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = [] + +path = [cwd + '/Include'] + +group = DefineGroup('libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..4c815c49b835a3a5ea61f337dc17154dd316d7d1 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.h new file mode 100644 index 0000000000000000000000000000000000000000..ea6e0c692699838e173270e0f322373d86f250bc --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.h @@ -0,0 +1,42163 @@ +/* +** ################################################################### +** Processors: MCIMX6Y2CVM05 +** MCIMX6Y2CVM08 +** MCIMX6Y2DVM05 +** MCIMX6Y2DVM09 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: IMX6ULLRM, Rev. 1, Feb. 2017 +** Version: rev. 3.0, 2017-02-28 +** Build: b170422 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCIMX6Y2 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-12-18) +** Initial version. +** - rev. 2.0 (2016-08-02) +** Rev.B Header GA +** - rev. 3.0 (2017-02-28) +** Rev.1 Header GA +** +** ################################################################### +*/ + +/*! + * @file MCIMX6Y2.h + * @version 3.0 + * @date 2017-02-28 + * @brief CMSIS Peripheral Access Layer for MCIMX6Y2 + * + * CMSIS Peripheral Access Layer for MCIMX6Y2 + */ + +#ifndef _MCIMX6Y2_H_ +#define _MCIMX6Y2_H_ /**< Symbol preventing repeated inclusion */ + +extern uint32_t *g_ccm_vbase; +extern uint32_t *g_ccm_analog_vbase; +extern uint32_t *g_pmu_vbase; + +extern uint32_t g_usbphy1_base; +extern uint32_t g_usbphy2_base; +extern uint32_t g_usb1_base; +extern uint32_t g_usb2_base; +extern uint32_t g_usb_analog_base; + + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 160 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + Software0_IRQn = 0, /**< Cortex-A7 Software Generated Interrupt 0 */ + Software1_IRQn = 1, /**< Cortex-A7 Software Generated Interrupt 1 */ + Software2_IRQn = 2, /**< Cortex-A7 Software Generated Interrupt 2 */ + Software3_IRQn = 3, /**< Cortex-A7 Software Generated Interrupt 3 */ + Software4_IRQn = 4, /**< Cortex-A7 Software Generated Interrupt 4 */ + Software5_IRQn = 5, /**< Cortex-A7 Software Generated Interrupt 5 */ + Software6_IRQn = 6, /**< Cortex-A7 Software Generated Interrupt 6 */ + Software7_IRQn = 7, /**< Cortex-A7 Software Generated Interrupt 7 */ + Software8_IRQn = 8, /**< Cortex-A7 Software Generated Interrupt 8 */ + Software9_IRQn = 9, /**< Cortex-A7 Software Generated Interrupt 9 */ + Software10_IRQn = 10, /**< Cortex-A7 Software Generated Interrupt 10 */ + Software11_IRQn = 11, /**< Cortex-A7 Software Generated Interrupt 11 */ + Software12_IRQn = 12, /**< Cortex-A7 Software Generated Interrupt 12 */ + Software13_IRQn = 13, /**< Cortex-A7 Software Generated Interrupt 13 */ + Software14_IRQn = 14, /**< Cortex-A7 Software Generated Interrupt 14 */ + Software15_IRQn = 15, /**< Cortex-A7 Software Generated Interrupt 15 */ + VirtualMaintenance_IRQn = 25, /**< Cortex-A7 Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /**< Cortex-A7 Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /**< Cortex-A7 Virtual Timer Interrupt */ + LegacyFastInt_IRQn = 28, /**< Cortex-A7 Legacy nFIQ signal Interrupt */ + SecurePhyTimer_IRQn = 29, /**< Cortex-A7 Secure Physical Timer Interrupt */ + NonSecurePhyTimer_IRQn = 30, /**< Cortex-A7 Non-secure Physical Timer Interrupt */ + LegacyIRQ_IRQn = 31, /**< Cortex-A7 Legacy nIRQ Interrupt */ + + /* Device specific interrupts */ + IOMUXC_IRQn = 32, /**< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot. */ + DAP_IRQn = 33, /**< Debug Access Port interrupt request. */ + SDMA_IRQn = 34, /**< SDMA interrupt request from all channels. */ + TSC_IRQn = 35, /**< TSC interrupt. */ + SNVS_IRQn = 36, /**< Logic OR of SNVS_LP and SNVS_HP interrupts. */ + LCDIF_IRQn = 37, /**< LCDIF sync interrupt. */ + RNGB_IRQn = 38, /**< RNGB interrupt. */ + CSI_IRQn = 39, /**< CMOS Sensor Interface interrupt request. */ + PXP_IRQ0_IRQn = 40, /**< PXP interrupt pxp_irq_0. */ + SCTR_IRQ0_IRQn = 41, /**< SCTR compare interrupt ipi_int[0]. */ + SCTR_IRQ1_IRQn = 42, /**< SCTR compare interrupt ipi_int[1]. */ + WDOG3_IRQn = 43, /**< WDOG3 timer reset interrupt request. */ + Reserved44_IRQn = 44, /**< Reserved */ + APBH_IRQn = 45, /**< DMA Logical OR of APBH DMA channels 0-3 completion and error interrupts. */ + WEIM_IRQn = 46, /**< WEIM interrupt request. */ + RAWNAND_BCH_IRQn = 47, /**< BCH operation complete interrupt. */ + RAWNAND_GPMI_IRQn = 48, /**< GPMI operation timeout error interrupt. */ + UART6_IRQn = 49, /**< UART6 interrupt request. */ + PXP_IRQ1_IRQn = 50, /**< PXP interrupt pxp_irq_1. */ + SNVS_Consolidated_IRQn = 51, /**< SNVS consolidated interrupt. */ + SNVS_Security_IRQn = 52, /**< SNVS security interrupt. */ + CSU_IRQn = 53, /**< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. */ + USDHC1_IRQn = 54, /**< USDHC1 (Enhanced SDHC) interrupt request. */ + USDHC2_IRQn = 55, /**< USDHC2 (Enhanced SDHC) interrupt request. */ + SAI3_RX_IRQn = 56, /**< SAI3 interrupt ipi_int_sai_rx. */ + SAI3_TX_IRQn = 57, /**< SAI3 interrupt ipi_int_sai_tx. */ + UART1_IRQn = 58, /**< UART1 interrupt request. */ + UART2_IRQn = 59, /**< UART2 interrupt request. */ + UART3_IRQn = 60, /**< UART3 interrupt request. */ + UART4_IRQn = 61, /**< UART4 interrupt request. */ + UART5_IRQn = 62, /**< UART5 interrupt request. */ + eCSPI1_IRQn = 63, /**< eCSPI1 interrupt request. */ + eCSPI2_IRQn = 64, /**< eCSPI2 interrupt request. */ + eCSPI3_IRQn = 65, /**< eCSPI3 interrupt request. */ + eCSPI4_IRQn = 66, /**< eCSPI4 interrupt request. */ + I2C4_IRQn = 67, /**< I2C4 interrupt request. */ + I2C1_IRQn = 68, /**< I2C1 interrupt request. */ + I2C2_IRQn = 69, /**< I2C2 interrupt request. */ + I2C3_IRQn = 70, /**< I2C3 interrupt request. */ + UART7_IRQn = 71, /**< UART-7 ORed interrupt. */ + UART8_IRQn = 72, /**< UART-8 ORed interrupt. */ + Reserved73_IRQn = 73, /**< Reserved */ + USB_OTG2_IRQn = 74, /**< USBO2 USB OTG2 */ + USB_OTG1_IRQn = 75, /**< USBO2 USB OTG1 */ + USB_PHY1_IRQn = 76, /**< UTMI0 interrupt request. */ + USB_PHY2_IRQn = 77, /**< UTMI1 interrupt request. */ + DCP_IRQ_IRQn = 78, /**< DCP interrupt request dcp_irq. */ + DCP_VMI_IRQ_IRQn = 79, /**< DCP interrupt request dcp_vmi_irq. */ + DCP_SEC_IRQ_IRQn = 80, /**< DCP interrupt request secure_irq. */ + TEMPMON_IRQn = 81, /**< Temperature Monitor Temperature Sensor (temperature greater than threshold) interrupt request. */ + ASRC_IRQn = 82, /**< ASRC interrupt request. */ + ESAI_IRQn = 83, /**< ESAI interrupt request. */ + SPDIF_IRQn = 84, /**< SPDIF interrupt. */ + Reserved85_IRQn = 85, /**< Reserved */ + PMU_IRQ1_IRQn = 86, /**< Brown-out event on either the 1.1, 2.5 or 3.0 regulators. */ + GPT1_IRQn = 87, /**< Logical OR of GPT1 rollover interrupt line, input capture 1 and 2 lines, output compare 1, 2, and 3 interrupt lines. */ + EPIT1_IRQn = 88, /**< EPIT1 output compare interrupt. */ + EPIT2_IRQn = 89, /**< EPIT2 output compare interrupt. */ + GPIO1_INT7_IRQn = 90, /**< INT7 interrupt request. */ + GPIO1_INT6_IRQn = 91, /**< INT6 interrupt request. */ + GPIO1_INT5_IRQn = 92, /**< INT5 interrupt request. */ + GPIO1_INT4_IRQn = 93, /**< INT4 interrupt request. */ + GPIO1_INT3_IRQn = 94, /**< INT3 interrupt request. */ + GPIO1_INT2_IRQn = 95, /**< INT2 interrupt request. */ + GPIO1_INT1_IRQn = 96, /**< INT1 interrupt request. */ + GPIO1_INT0_IRQn = 97, /**< INT0 interrupt request. */ + GPIO1_Combined_0_15_IRQn = 98, /**< Combined interrupt indication for GPIO1 signals 0 - 15. */ + GPIO1_Combined_16_31_IRQn = 99, /**< Combined interrupt indication for GPIO1 signals 16 - 31. */ + GPIO2_Combined_0_15_IRQn = 100, /**< Combined interrupt indication for GPIO2 signals 0 - 15. */ + GPIO2_Combined_16_31_IRQn = 101, /**< Combined interrupt indication for GPIO2 signals 16 - 31. */ + GPIO3_Combined_0_15_IRQn = 102, /**< Combined interrupt indication for GPIO3 signals 0 - 15. */ + GPIO3_Combined_16_31_IRQn = 103, /**< Combined interrupt indication for GPIO3 signals 16 - 31. */ + GPIO4_Combined_0_15_IRQn = 104, /**< Combined interrupt indication for GPIO4 signals 0 - 15. */ + GPIO4_Combined_16_31_IRQn = 105, /**< Combined interrupt indication for GPIO4 signals 16 - 31. */ + GPIO5_Combined_0_15_IRQn = 106, /**< Combined interrupt indication for GPIO5 signals 0 - 15. */ + GPIO5_Combined_16_31_IRQn = 107, /**< Combined interrupt indication for GPIO5 signals 16 - 31. */ + Reserved108_IRQn = 108, /**< Reserved */ + Reserved109_IRQn = 109, /**< Reserved */ + Reserved110_IRQn = 110, /**< Reserved */ + Reserved111_IRQn = 111, /**< Reserved */ + WDOG1_IRQn = 112, /**< WDOG1 timer reset interrupt request. */ + WDOG2_IRQn = 113, /**< WDOG2 timer reset interrupt request. */ + KPP_IRQn = 114, /**< Key Pad interrupt request. */ + PWM1_IRQn = 115, /**< hasRegInstance(`PWM1`)?`Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM2_IRQn = 116, /**< hasRegInstance(`PWM2`)?`Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM3_IRQn = 117, /**< hasRegInstance(`PWM3`)?`Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM4_IRQn = 118, /**< hasRegInstance(`PWM4`)?`Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + CCM_IRQ1_IRQn = 119, /**< CCM interrupt request ipi_int_1. */ + CCM_IRQ2_IRQn = 120, /**< CCM interrupt request ipi_int_2. */ + GPC_IRQn = 121, /**< GPC interrupt request 1. */ + Reserved122_IRQn = 122, /**< Reserved */ + SRC_IRQn = 123, /**< SRC interrupt request src_ipi_int_1. */ + Reserved124_IRQn = 124, /**< Reserved */ + Reserved125_IRQn = 125, /**< Reserved */ + CPU_PerformanceUnit_IRQn = 126, /**< Performance Unit interrupt ~ipi_pmu_irq_b. */ + CPU_CTI_Trigger_IRQn = 127, /**< CTI trigger outputs interrupt ~ipi_cti_irq_b. */ + SRC_Combined_IRQn = 128, /**< Combined CPU wdog interrupts (4x) out of SRC. */ + SAI1_IRQn = 129, /**< SAI1 interrupt request. */ + SAI2_IRQn = 130, /**< SAI2 interrupt request. */ + Reserved131_IRQn = 131, /**< Reserved */ + ADC1_IRQn = 132, /**< ADC1 interrupt request. */ + ADC_5HC_IRQn = 133, /**< ADC_5HC interrupt request. */ + Reserved134_IRQn = 134, /**< Reserved */ + Reserved135_IRQn = 135, /**< Reserved */ + SJC_IRQn = 136, /**< SJC interrupt from General Purpose register. */ + CAAM_Job_Ring0_IRQn = 137, /**< CAAM job ring 0 interrupt ipi_caam_irq0. */ + CAAM_Job_Ring1_IRQn = 138, /**< CAAM job ring 1 interrupt ipi_caam_irq1. */ + QSPI_IRQn = 139, /**< QSPI1 interrupt request ipi_int_ored. */ + TZASC_IRQn = 140, /**< TZASC (PL380) interrupt request. */ + GPT2_IRQn = 141, /**< Logical OR of GPT2 rollover interrupt line, input capture 1 and 2 lines, output compare 1, 2 and 3 interrupt lines. */ + CAN1_IRQn = 142, /**< Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken */ + CAN2_IRQn = 143, /**< Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken */ + Reserved144_IRQn = 144, /**< Reserved */ + Reserved145_IRQn = 145, /**< Reserved */ + PWM5_IRQn = 146, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM6_IRQn = 147, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM7_IRQn = 148, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM8_IRQn = 149, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + ENET1_IRQn = 150, /**< ENET1 interrupt */ + ENET1_1588_IRQn = 151, /**< ENET1 1588 Timer interrupt [synchronous] request. */ + ENET2_IRQn = 152, /**< ENET2 interrupt */ + ENET2_1588_IRQn = 153, /**< MAC 0 1588 Timer interrupt [synchronous] request. */ + Reserved154_IRQn = 154, /**< Reserved */ + Reserved155_IRQn = 155, /**< Reserved */ + Reserved156_IRQn = 156, /**< Reserved */ + Reserved157_IRQn = 157, /**< Reserved */ + Reserved158_IRQn = 158, /**< Reserved */ + PMU_IRQ2_IRQn = 159 /**< Brown-out event on either core, gpu or soc regulators. */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Configuration of the Cortex-A7 Processor and Core Peripherals + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-A7 Processor and Core Peripherals + * @{ + */ + +#define __CA7_REV 0x0005 /**< Core revision r0p5 */ +#define __GIC_PRIO_BITS 5 /**< Number of Bits used for Priority Levels */ +#define __FPU_PRESENT 1 /**< FPU present or not */ + +#include "core_ca7.h" /* Core Peripheral Access Layer */ +#include "system_MCIMX6Y2.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_MOD = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TMS = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TDO = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TDI = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TCK = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TRST_B = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_CTS_B = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_RTS_B = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART5_TX_DATA = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART5_RX_DATA = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA0 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA1 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_ER = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA0 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA1 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA0 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA1 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_EN = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_ER = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_CLK = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_RESET = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA00 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA01 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA02 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA03 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA04 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA05 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA06 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA07 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA08 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA09 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA10 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA11 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA12 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA13 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA14 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA15 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA16 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA17 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA18 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA19 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA20 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA21 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA22 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA23 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_MCLK = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA00 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA01 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA02 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA03 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA04 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA05 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD_DDR + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD_DDR collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad_ddr +{ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 = 16U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 = 17U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B = 18U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B = 19U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B = 20U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B = 21U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B = 22U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 = 23U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 = 24U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 = 25U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 = 26U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 = 27U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 = 28U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 = 29U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P = 30U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P = 31U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P = 32U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_RESET = 33U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ +} iomuxc_sw_pad_ctl_pad_ddr_t; + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_CTS_B = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_RTS_B = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART5_TX_DATA = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART5_RX_DATA = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA0 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA1 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_EN = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA0 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA1 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_EN = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_ER = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA0 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA1 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_EN = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA0 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA1 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_EN = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_ER = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_CLK = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_RESET = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA00 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA01 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA02 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA03 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA04 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA05 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA06 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA07 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA08 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA09 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA10 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA11 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA12 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA13 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA14 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA15 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA16 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA17 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA18 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA19 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA20 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA21 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA22 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA23 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_MCLK = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA00 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA01 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA02 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA03 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA04 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA05 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA06 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA07 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA05_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA00_SELECT_INPUT = 6U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA01_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA04_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA06_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA07_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA08_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA09_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA10_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA11_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA12_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA13_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA14_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA15_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA16_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA17_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA18_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA19_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA20_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA21_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA22_SELECT_INPUT = 25U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA23_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_CSI_HSYNC_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_CSI_VSYNC_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_CSI_FIELD_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_SCLK_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_MISO_SELECT_INPUT = 32U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_MOSI_SELECT_INPUT = 33U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_SS0_B_SELECT_INPUT = 34U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_SCLK_SELECT_INPUT = 35U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_MISO_SELECT_INPUT = 36U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_MOSI_SELECT_INPUT = 37U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_SS0_B_SELECT_INPUT = 38U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_SCLK_SELECT_INPUT = 39U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_MISO_SELECT_INPUT = 40U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_MOSI_SELECT_INPUT = 41U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_SS0_B_SELECT_INPUT = 42U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_SCLK_SELECT_INPUT = 43U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_MISO_SELECT_INPUT = 44U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_MOSI_SELECT_INPUT = 45U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_SS0_B_SELECT_INPUT = 46U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_REF_CLK1_SELECT_INPUT = 47U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_MAC0_MDIO_SELECT_INPUT = 48U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_REF_CLK2_SELECT_INPUT = 49U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_MAC0_MDIO_SELECT_INPUT = 50U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 51U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 52U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CAPTURE1_SELECT_INPUT = 53U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CAPTURE2_SELECT_INPUT = 54U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CLK_SELECT_INPUT = 55U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CAPTURE1_SELECT_INPUT = 56U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CAPTURE2_SELECT_INPUT = 57U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CLK_SELECT_INPUT = 58U, /**< IOMUXC select input index */ + kIOMUXC_I2C1_SCL_SELECT_INPUT = 59U, /**< IOMUXC select input index */ + kIOMUXC_I2C1_SDA_SELECT_INPUT = 60U, /**< IOMUXC select input index */ + kIOMUXC_I2C2_SCL_SELECT_INPUT = 61U, /**< IOMUXC select input index */ + kIOMUXC_I2C2_SDA_SELECT_INPUT = 62U, /**< IOMUXC select input index */ + kIOMUXC_I2C3_SCL_SELECT_INPUT = 63U, /**< IOMUXC select input index */ + kIOMUXC_I2C3_SDA_SELECT_INPUT = 64U, /**< IOMUXC select input index */ + kIOMUXC_I2C4_SCL_SELECT_INPUT = 65U, /**< IOMUXC select input index */ + kIOMUXC_I2C4_SDA_SELECT_INPUT = 66U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL0_SELECT_INPUT = 67U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL1_SELECT_INPUT = 68U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL2_SELECT_INPUT = 69U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW1_SELECT_INPUT = 71U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW2_SELECT_INPUT = 72U, /**< IOMUXC select input index */ + kIOMUXC_LCD_BUSY_SELECT_INPUT = 73U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_MCLK_SELECT_INPUT = 74U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA_SELECT_INPUT = 75U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 76U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 77U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_MCLK_SELECT_INPUT = 78U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_DATA_SELECT_INPUT = 79U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 80U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 81U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_MCLK_SELECT_INPUT = 82U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_RX_DATA_SELECT_INPUT = 83U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT = 84U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT = 85U, /**< IOMUXC select input index */ + kIOMUXC_SDMA_EVENTS0_SELECT_INPUT = 86U, /**< IOMUXC select input index */ + kIOMUXC_SDMA_EVENTS1_SELECT_INPUT = 87U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_IN_SELECT_INPUT = 88U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_EXT_CLK_SELECT_INPUT = 89U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RTS_B_SELECT_INPUT = 90U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RX_DATA_SELECT_INPUT = 91U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RTS_B_SELECT_INPUT = 92U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RX_DATA_SELECT_INPUT = 93U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RTS_B_SELECT_INPUT = 94U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RX_DATA_SELECT_INPUT = 95U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RTS_B_SELECT_INPUT = 96U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RX_DATA_SELECT_INPUT = 97U, /**< IOMUXC select input index */ + kIOMUXC_UART5_RTS_B_SELECT_INPUT = 98U, /**< IOMUXC select input index */ + kIOMUXC_UART5_RX_DATA_SELECT_INPUT = 99U, /**< IOMUXC select input index */ + kIOMUXC_UART6_RTS_B_SELECT_INPUT = 100U, /**< IOMUXC select input index */ + kIOMUXC_UART6_RX_DATA_SELECT_INPUT = 101U, /**< IOMUXC select input index */ + kIOMUXC_UART7_RTS_B_SELECT_INPUT = 102U, /**< IOMUXC select input index */ + kIOMUXC_UART7_RX_DATA_SELECT_INPUT = 103U, /**< IOMUXC select input index */ + kIOMUXC_UART8_RTS_B_SELECT_INPUT = 104U, /**< IOMUXC select input index */ + kIOMUXC_UART8_RX_DATA_SELECT_INPUT = 105U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 106U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG_OC_SELECT_INPUT = 107U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 108U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_WP_SELECT_INPUT = 109U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CLK_SELECT_INPUT = 110U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 111U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CMD_SELECT_INPUT = 112U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 114U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 115U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 116U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 117U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 118U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 119U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 120U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC group + * + * Defines the enumeration for the IOMUXC group collections. + */ +typedef enum _iomuxc_grp +{ + kIOMUXC_SW_PAD_CTL_GRP_ADDDS = 0U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL = 1U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_B0DS = 2U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRPK = 3U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_CTLDS = 4U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_B1DS = 5U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRHYS = 6U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRPKE = 7U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRMODE = 8U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDR_TYPE = 9U, /**< IOMUXC group index */ +} iomuxc_grp_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_snvs_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC_SNVS SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC_SNVS SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_snvs_sw_mux_ctl_pad +{ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE0 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE1 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER0 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER1 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER2 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER3 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER4 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER5 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER6 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER7 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER8 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER9 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_snvs_sw_mux_ctl_pad_t; + +/*! + * @addtogroup iomuxc_snvs_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC_SNVS SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC_SNVS SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_snvs_sw_pad_ctl_pad +{ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE0 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE1 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER0 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER1 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER2 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER3 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER4 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER5 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER6 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER7 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER8 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER9 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_snvs_sw_pad_ctl_pad_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[1]; /**< Control register, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __I uint32_t HS; /**< Status register, offset: 0x8 */ + __I uint32_t R[1]; /**< Data result register, array offset: 0xC, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CFG; /**< Configuration register, offset: 0x14 */ + __IO uint32_t GC; /**< General control register, offset: 0x18 */ + __IO uint32_t GS; /**< General status register, offset: 0x1C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x20 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x24 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x28 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name HC - Control register */ +#define ADC_HC_ADCH_MASK (0x1FU) +#define ADC_HC_ADCH_SHIFT (0U) +#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) +#define ADC_HC_AIEN_MASK (0x80U) +#define ADC_HC_AIEN_SHIFT (7U) +#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) + +/* The count of ADC_HC */ +#define ADC_HC_COUNT (1U) + +/*! @name HS - Status register */ +#define ADC_HS_COCO0_MASK (0x1U) +#define ADC_HS_COCO0_SHIFT (0U) +#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) + +/*! @name R - Data result register */ +#define ADC_R_CDATA_MASK (0xFFFU) +#define ADC_R_CDATA_SHIFT (0U) +#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) + +/* The count of ADC_R */ +#define ADC_R_COUNT (1U) + +/*! @name CFG - Configuration register */ +#define ADC_CFG_ADICLK_MASK (0x3U) +#define ADC_CFG_ADICLK_SHIFT (0U) +#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) +#define ADC_CFG_MODE_MASK (0xCU) +#define ADC_CFG_MODE_SHIFT (2U) +#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) +#define ADC_CFG_ADLSMP_MASK (0x10U) +#define ADC_CFG_ADLSMP_SHIFT (4U) +#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) +#define ADC_CFG_ADIV_MASK (0x60U) +#define ADC_CFG_ADIV_SHIFT (5U) +#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) +#define ADC_CFG_ADLPC_MASK (0x80U) +#define ADC_CFG_ADLPC_SHIFT (7U) +#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) +#define ADC_CFG_ADSTS_MASK (0x300U) +#define ADC_CFG_ADSTS_SHIFT (8U) +#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) +#define ADC_CFG_ADHSC_MASK (0x400U) +#define ADC_CFG_ADHSC_SHIFT (10U) +#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) +#define ADC_CFG_REFSEL_MASK (0x1800U) +#define ADC_CFG_REFSEL_SHIFT (11U) +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_ADTRG_MASK (0x2000U) +#define ADC_CFG_ADTRG_SHIFT (13U) +#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) +#define ADC_CFG_AVGS_MASK (0xC000U) +#define ADC_CFG_AVGS_SHIFT (14U) +#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) +#define ADC_CFG_OVWREN_MASK (0x10000U) +#define ADC_CFG_OVWREN_SHIFT (16U) +#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) + +/*! @name GC - General control register */ +#define ADC_GC_ADACKEN_MASK (0x1U) +#define ADC_GC_ADACKEN_SHIFT (0U) +#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) +#define ADC_GC_DMAEN_MASK (0x2U) +#define ADC_GC_DMAEN_SHIFT (1U) +#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) +#define ADC_GC_ACREN_MASK (0x4U) +#define ADC_GC_ACREN_SHIFT (2U) +#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) +#define ADC_GC_ACFGT_MASK (0x8U) +#define ADC_GC_ACFGT_SHIFT (3U) +#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) +#define ADC_GC_ACFE_MASK (0x10U) +#define ADC_GC_ACFE_SHIFT (4U) +#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) +#define ADC_GC_AVGE_MASK (0x20U) +#define ADC_GC_AVGE_SHIFT (5U) +#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) +#define ADC_GC_ADCO_MASK (0x40U) +#define ADC_GC_ADCO_SHIFT (6U) +#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) +#define ADC_GC_CAL_MASK (0x80U) +#define ADC_GC_CAL_SHIFT (7U) +#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) + +/*! @name GS - General status register */ +#define ADC_GS_ADACT_MASK (0x1U) +#define ADC_GS_ADACT_SHIFT (0U) +#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) +#define ADC_GS_CALF_MASK (0x2U) +#define ADC_GS_CALF_SHIFT (1U) +#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) +#define ADC_GS_AWKST_MASK (0x4U) +#define ADC_GS_AWKST_SHIFT (2U) +#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) + +/*! @name CV - Compare value register */ +#define ADC_CV_CV1_MASK (0xFFFU) +#define ADC_CV_CV1_SHIFT (0U) +#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) +#define ADC_CV_CV2_MASK (0xFFF0000U) +#define ADC_CV_CV2_SHIFT (16U) +#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) + +/*! @name OFS - Offset correction value register */ +#define ADC_OFS_OFS_MASK (0xFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +#define ADC_OFS_SIGN_MASK (0x1000U) +#define ADC_OFS_SIGN_SHIFT (12U) +#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) + +/*! @name CAL - Calibration value register */ +#define ADC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x2198000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { 0u, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ADC_5HC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_5HC_Peripheral_Access_Layer ADC_5HC Peripheral Access Layer + * @{ + */ + +/** ADC_5HC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[5]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x14 */ + __I uint32_t R[5]; /**< Data result register for HW triggers, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x2C */ + __IO uint32_t GC; /**< General control register, offset: 0x30 */ + __IO uint32_t GS; /**< General status register, offset: 0x34 */ + __IO uint32_t CV; /**< Compare value register, offset: 0x38 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x3C */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x40 */ +} ADC_5HC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC_5HC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_5HC_Register_Masks ADC_5HC Register Masks + * @{ + */ + +/*! @name HC - Control register for hardware triggers */ +#define ADC_5HC_HC_ADCH_MASK (0x1FU) +#define ADC_5HC_HC_ADCH_SHIFT (0U) +#define ADC_5HC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HC_ADCH_SHIFT)) & ADC_5HC_HC_ADCH_MASK) +#define ADC_5HC_HC_AIEN_MASK (0x80U) +#define ADC_5HC_HC_AIEN_SHIFT (7U) +#define ADC_5HC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HC_AIEN_SHIFT)) & ADC_5HC_HC_AIEN_MASK) + +/* The count of ADC_5HC_HC */ +#define ADC_5HC_HC_COUNT (5U) + +/*! @name HS - Status register for HW triggers */ +#define ADC_5HC_HS_COCO0_MASK (0x1U) +#define ADC_5HC_HS_COCO0_SHIFT (0U) +#define ADC_5HC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO0_SHIFT)) & ADC_5HC_HS_COCO0_MASK) +#define ADC_5HC_HS_COCO1_MASK (0x2U) +#define ADC_5HC_HS_COCO1_SHIFT (1U) +#define ADC_5HC_HS_COCO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO1_SHIFT)) & ADC_5HC_HS_COCO1_MASK) +#define ADC_5HC_HS_COCO2_MASK (0x4U) +#define ADC_5HC_HS_COCO2_SHIFT (2U) +#define ADC_5HC_HS_COCO2(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO2_SHIFT)) & ADC_5HC_HS_COCO2_MASK) +#define ADC_5HC_HS_COCO3_MASK (0x8U) +#define ADC_5HC_HS_COCO3_SHIFT (3U) +#define ADC_5HC_HS_COCO3(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO3_SHIFT)) & ADC_5HC_HS_COCO3_MASK) +#define ADC_5HC_HS_COCO4_MASK (0x10U) +#define ADC_5HC_HS_COCO4_SHIFT (4U) +#define ADC_5HC_HS_COCO4(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO4_SHIFT)) & ADC_5HC_HS_COCO4_MASK) + +/*! @name R - Data result register for HW triggers */ +#define ADC_5HC_R_CDATA_MASK (0xFFFU) +#define ADC_5HC_R_CDATA_SHIFT (0U) +#define ADC_5HC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_R_CDATA_SHIFT)) & ADC_5HC_R_CDATA_MASK) + +/* The count of ADC_5HC_R */ +#define ADC_5HC_R_COUNT (5U) + +/*! @name CFG - Configuration register */ +#define ADC_5HC_CFG_ADICLK_MASK (0x3U) +#define ADC_5HC_CFG_ADICLK_SHIFT (0U) +#define ADC_5HC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADICLK_SHIFT)) & ADC_5HC_CFG_ADICLK_MASK) +#define ADC_5HC_CFG_MODE_MASK (0xCU) +#define ADC_5HC_CFG_MODE_SHIFT (2U) +#define ADC_5HC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_MODE_SHIFT)) & ADC_5HC_CFG_MODE_MASK) +#define ADC_5HC_CFG_ADLSMP_MASK (0x10U) +#define ADC_5HC_CFG_ADLSMP_SHIFT (4U) +#define ADC_5HC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADLSMP_SHIFT)) & ADC_5HC_CFG_ADLSMP_MASK) +#define ADC_5HC_CFG_ADIV_MASK (0x60U) +#define ADC_5HC_CFG_ADIV_SHIFT (5U) +#define ADC_5HC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADIV_SHIFT)) & ADC_5HC_CFG_ADIV_MASK) +#define ADC_5HC_CFG_ADLPC_MASK (0x80U) +#define ADC_5HC_CFG_ADLPC_SHIFT (7U) +#define ADC_5HC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADLPC_SHIFT)) & ADC_5HC_CFG_ADLPC_MASK) +#define ADC_5HC_CFG_ADSTS_MASK (0x300U) +#define ADC_5HC_CFG_ADSTS_SHIFT (8U) +#define ADC_5HC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADSTS_SHIFT)) & ADC_5HC_CFG_ADSTS_MASK) +#define ADC_5HC_CFG_ADHSC_MASK (0x400U) +#define ADC_5HC_CFG_ADHSC_SHIFT (10U) +#define ADC_5HC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADHSC_SHIFT)) & ADC_5HC_CFG_ADHSC_MASK) +#define ADC_5HC_CFG_REFSEL_MASK (0x1800U) +#define ADC_5HC_CFG_REFSEL_SHIFT (11U) +#define ADC_5HC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_REFSEL_SHIFT)) & ADC_5HC_CFG_REFSEL_MASK) +#define ADC_5HC_CFG_ADTRG_MASK (0x2000U) +#define ADC_5HC_CFG_ADTRG_SHIFT (13U) +#define ADC_5HC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADTRG_SHIFT)) & ADC_5HC_CFG_ADTRG_MASK) +#define ADC_5HC_CFG_AVGS_MASK (0xC000U) +#define ADC_5HC_CFG_AVGS_SHIFT (14U) +#define ADC_5HC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_AVGS_SHIFT)) & ADC_5HC_CFG_AVGS_MASK) +#define ADC_5HC_CFG_OVWREN_MASK (0x10000U) +#define ADC_5HC_CFG_OVWREN_SHIFT (16U) +#define ADC_5HC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_OVWREN_SHIFT)) & ADC_5HC_CFG_OVWREN_MASK) + +/*! @name GC - General control register */ +#define ADC_5HC_GC_ADACKEN_MASK (0x1U) +#define ADC_5HC_GC_ADACKEN_SHIFT (0U) +#define ADC_5HC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ADACKEN_SHIFT)) & ADC_5HC_GC_ADACKEN_MASK) +#define ADC_5HC_GC_DMAEN_MASK (0x2U) +#define ADC_5HC_GC_DMAEN_SHIFT (1U) +#define ADC_5HC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_DMAEN_SHIFT)) & ADC_5HC_GC_DMAEN_MASK) +#define ADC_5HC_GC_ACREN_MASK (0x4U) +#define ADC_5HC_GC_ACREN_SHIFT (2U) +#define ADC_5HC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACREN_SHIFT)) & ADC_5HC_GC_ACREN_MASK) +#define ADC_5HC_GC_ACFGT_MASK (0x8U) +#define ADC_5HC_GC_ACFGT_SHIFT (3U) +#define ADC_5HC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACFGT_SHIFT)) & ADC_5HC_GC_ACFGT_MASK) +#define ADC_5HC_GC_ACFE_MASK (0x10U) +#define ADC_5HC_GC_ACFE_SHIFT (4U) +#define ADC_5HC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACFE_SHIFT)) & ADC_5HC_GC_ACFE_MASK) +#define ADC_5HC_GC_AVGE_MASK (0x20U) +#define ADC_5HC_GC_AVGE_SHIFT (5U) +#define ADC_5HC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_AVGE_SHIFT)) & ADC_5HC_GC_AVGE_MASK) +#define ADC_5HC_GC_ADCO_MASK (0x40U) +#define ADC_5HC_GC_ADCO_SHIFT (6U) +#define ADC_5HC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ADCO_SHIFT)) & ADC_5HC_GC_ADCO_MASK) +#define ADC_5HC_GC_CAL_MASK (0x80U) +#define ADC_5HC_GC_CAL_SHIFT (7U) +#define ADC_5HC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_CAL_SHIFT)) & ADC_5HC_GC_CAL_MASK) + +/*! @name GS - General status register */ +#define ADC_5HC_GS_ADACT_MASK (0x1U) +#define ADC_5HC_GS_ADACT_SHIFT (0U) +#define ADC_5HC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_ADACT_SHIFT)) & ADC_5HC_GS_ADACT_MASK) +#define ADC_5HC_GS_CALF_MASK (0x2U) +#define ADC_5HC_GS_CALF_SHIFT (1U) +#define ADC_5HC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_CALF_SHIFT)) & ADC_5HC_GS_CALF_MASK) +#define ADC_5HC_GS_AWKST_MASK (0x4U) +#define ADC_5HC_GS_AWKST_SHIFT (2U) +#define ADC_5HC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_AWKST_SHIFT)) & ADC_5HC_GS_AWKST_MASK) + +/*! @name CV - Compare value register */ +#define ADC_5HC_CV_CV1_MASK (0xFFFU) +#define ADC_5HC_CV_CV1_SHIFT (0U) +#define ADC_5HC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CV_CV1_SHIFT)) & ADC_5HC_CV_CV1_MASK) +#define ADC_5HC_CV_CV2_MASK (0xFFF0000U) +#define ADC_5HC_CV_CV2_SHIFT (16U) +#define ADC_5HC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CV_CV2_SHIFT)) & ADC_5HC_CV_CV2_MASK) + +/*! @name OFS - Offset correction value register */ +#define ADC_5HC_OFS_OFS_MASK (0xFFFU) +#define ADC_5HC_OFS_OFS_SHIFT (0U) +#define ADC_5HC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_OFS_OFS_SHIFT)) & ADC_5HC_OFS_OFS_MASK) +#define ADC_5HC_OFS_SIGN_MASK (0x1000U) +#define ADC_5HC_OFS_SIGN_SHIFT (12U) +#define ADC_5HC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_OFS_SIGN_SHIFT)) & ADC_5HC_OFS_SIGN_MASK) + +/*! @name CAL - Calibration value register */ +#define ADC_5HC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_5HC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_5HC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CAL_CAL_CODE_SHIFT)) & ADC_5HC_CAL_CAL_CODE_MASK) + + +/*! + * @} + */ /* end of group ADC_5HC_Register_Masks */ + + +/* ADC_5HC - Peripheral instance base addresses */ +/** Peripheral ADC_5HC base address */ +#define ADC_5HC_BASE (0x219C000u) +/** Peripheral ADC_5HC base pointer */ +#define ADC_5HC ((ADC_5HC_Type *)ADC_5HC_BASE) +/** Array initializer of ADC_5HC peripheral base addresses */ +#define ADC_5HC_BASE_ADDRS { ADC_5HC_BASE } +/** Array initializer of ADC_5HC peripheral base pointers */ +#define ADC_5HC_BASE_PTRS { ADC_5HC } +/** Interrupt vectors for the ADC_5HC peripheral type */ +#define ADC_5HC_IRQS { ADC_5HC_IRQn } + +/*! + * @} + */ /* end of group ADC_5HC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ + __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ + __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ + __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ + __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - Master Priviledge Registers */ +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) + +/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) + +/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) + +/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) + +/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) + +/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x207C000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x217C000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x227C000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- APBH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer + * @{ + */ + +/** APBH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ + __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ + __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ + __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ + __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ + __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ + __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ + __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ + uint8_t RESERVED_2[156]; + __I uint32_t CH0_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CH0_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */ + uint8_t RESERVED_4[12]; + __I uint32_t CH0_CMD; /**< APBH DMA Channel n Command Register, offset: 0x120 */ + uint8_t RESERVED_5[12]; + __I uint32_t CH0_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CH0_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */ + uint8_t RESERVED_7[12]; + __I uint32_t CH0_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */ + uint8_t RESERVED_8[12]; + __I uint32_t CH0_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */ + uint8_t RESERVED_9[12]; + __I uint32_t CH1_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CH1_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */ + uint8_t RESERVED_11[12]; + __I uint32_t CH1_CMD; /**< APBH DMA Channel n Command Register, offset: 0x190 */ + uint8_t RESERVED_12[12]; + __I uint32_t CH1_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CH1_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */ + uint8_t RESERVED_14[12]; + __I uint32_t CH1_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */ + uint8_t RESERVED_15[12]; + __I uint32_t CH1_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */ + uint8_t RESERVED_16[12]; + __I uint32_t CH2_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH2_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */ + uint8_t RESERVED_18[12]; + __I uint32_t CH2_CMD; /**< APBH DMA Channel n Command Register, offset: 0x200 */ + uint8_t RESERVED_19[12]; + __I uint32_t CH2_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH2_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */ + uint8_t RESERVED_21[12]; + __I uint32_t CH2_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */ + uint8_t RESERVED_22[12]; + __I uint32_t CH2_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */ + uint8_t RESERVED_23[12]; + __I uint32_t CH3_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH3_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */ + uint8_t RESERVED_25[12]; + __I uint32_t CH3_CMD; /**< APBH DMA Channel n Command Register, offset: 0x270 */ + uint8_t RESERVED_26[12]; + __I uint32_t CH3_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */ + uint8_t RESERVED_28[12]; + __I uint32_t CH3_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */ + uint8_t RESERVED_29[12]; + __I uint32_t CH3_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */ + uint8_t RESERVED_30[12]; + __I uint32_t CH4_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t CH4_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */ + uint8_t RESERVED_32[12]; + __I uint32_t CH4_CMD; /**< APBH DMA Channel n Command Register, offset: 0x2E0 */ + uint8_t RESERVED_33[12]; + __I uint32_t CH4_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */ + uint8_t RESERVED_34[12]; + __IO uint32_t CH4_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */ + uint8_t RESERVED_35[12]; + __I uint32_t CH4_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */ + uint8_t RESERVED_36[12]; + __I uint32_t CH4_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */ + uint8_t RESERVED_37[12]; + __I uint32_t CH5_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */ + uint8_t RESERVED_38[12]; + __IO uint32_t CH5_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */ + uint8_t RESERVED_39[12]; + __I uint32_t CH5_CMD; /**< APBH DMA Channel n Command Register, offset: 0x350 */ + uint8_t RESERVED_40[12]; + __I uint32_t CH5_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */ + uint8_t RESERVED_41[12]; + __IO uint32_t CH5_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */ + uint8_t RESERVED_42[12]; + __I uint32_t CH5_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */ + uint8_t RESERVED_43[12]; + __I uint32_t CH5_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */ + uint8_t RESERVED_44[12]; + __I uint32_t CH6_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t CH6_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */ + uint8_t RESERVED_46[12]; + __I uint32_t CH6_CMD; /**< APBH DMA Channel n Command Register, offset: 0x3C0 */ + uint8_t RESERVED_47[12]; + __I uint32_t CH6_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */ + uint8_t RESERVED_48[12]; + __IO uint32_t CH6_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */ + uint8_t RESERVED_49[12]; + __I uint32_t CH6_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */ + uint8_t RESERVED_50[12]; + __I uint32_t CH6_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */ + uint8_t RESERVED_51[12]; + __I uint32_t CH7_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */ + uint8_t RESERVED_52[12]; + __IO uint32_t CH7_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */ + uint8_t RESERVED_53[12]; + __I uint32_t CH7_CMD; /**< APBH DMA Channel n Command Register, offset: 0x430 */ + uint8_t RESERVED_54[12]; + __I uint32_t CH7_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */ + uint8_t RESERVED_55[12]; + __IO uint32_t CH7_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */ + uint8_t RESERVED_56[12]; + __I uint32_t CH7_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */ + uint8_t RESERVED_57[12]; + __I uint32_t CH7_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */ + uint8_t RESERVED_58[12]; + __I uint32_t CH8_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */ + uint8_t RESERVED_59[12]; + __IO uint32_t CH8_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */ + uint8_t RESERVED_60[12]; + __I uint32_t CH8_CMD; /**< APBH DMA Channel n Command Register, offset: 0x4A0 */ + uint8_t RESERVED_61[12]; + __I uint32_t CH8_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t CH8_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */ + uint8_t RESERVED_63[12]; + __I uint32_t CH8_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */ + uint8_t RESERVED_64[12]; + __I uint32_t CH8_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */ + uint8_t RESERVED_65[12]; + __I uint32_t CH9_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t CH9_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */ + uint8_t RESERVED_67[12]; + __I uint32_t CH9_CMD; /**< APBH DMA Channel n Command Register, offset: 0x510 */ + uint8_t RESERVED_68[12]; + __I uint32_t CH9_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */ + uint8_t RESERVED_69[12]; + __IO uint32_t CH9_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */ + uint8_t RESERVED_70[12]; + __I uint32_t CH9_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */ + uint8_t RESERVED_71[12]; + __I uint32_t CH9_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */ + uint8_t RESERVED_72[12]; + __I uint32_t CH10_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */ + uint8_t RESERVED_73[12]; + __IO uint32_t CH10_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */ + uint8_t RESERVED_74[12]; + __I uint32_t CH10_CMD; /**< APBH DMA Channel n Command Register, offset: 0x580 */ + uint8_t RESERVED_75[12]; + __I uint32_t CH10_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */ + uint8_t RESERVED_76[12]; + __IO uint32_t CH10_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */ + uint8_t RESERVED_77[12]; + __I uint32_t CH10_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */ + uint8_t RESERVED_78[12]; + __I uint32_t CH10_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */ + uint8_t RESERVED_79[12]; + __I uint32_t CH11_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t CH11_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */ + uint8_t RESERVED_81[12]; + __I uint32_t CH11_CMD; /**< APBH DMA Channel n Command Register, offset: 0x5F0 */ + uint8_t RESERVED_82[12]; + __I uint32_t CH11_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */ + uint8_t RESERVED_83[12]; + __IO uint32_t CH11_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */ + uint8_t RESERVED_84[12]; + __I uint32_t CH11_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */ + uint8_t RESERVED_85[12]; + __I uint32_t CH11_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */ + uint8_t RESERVED_86[12]; + __I uint32_t CH12_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */ + uint8_t RESERVED_87[12]; + __IO uint32_t CH12_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */ + uint8_t RESERVED_88[12]; + __I uint32_t CH12_CMD; /**< APBH DMA Channel n Command Register, offset: 0x660 */ + uint8_t RESERVED_89[12]; + __I uint32_t CH12_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */ + uint8_t RESERVED_90[12]; + __IO uint32_t CH12_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */ + uint8_t RESERVED_91[12]; + __I uint32_t CH12_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */ + uint8_t RESERVED_92[12]; + __I uint32_t CH12_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */ + uint8_t RESERVED_93[12]; + __I uint32_t CH13_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */ + uint8_t RESERVED_94[12]; + __IO uint32_t CH13_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */ + uint8_t RESERVED_95[12]; + __I uint32_t CH13_CMD; /**< APBH DMA Channel n Command Register, offset: 0x6D0 */ + uint8_t RESERVED_96[12]; + __I uint32_t CH13_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */ + uint8_t RESERVED_97[12]; + __IO uint32_t CH13_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */ + uint8_t RESERVED_98[12]; + __I uint32_t CH13_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */ + uint8_t RESERVED_99[12]; + __I uint32_t CH13_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */ + uint8_t RESERVED_100[12]; + __I uint32_t CH14_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */ + uint8_t RESERVED_101[12]; + __IO uint32_t CH14_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */ + uint8_t RESERVED_102[12]; + __I uint32_t CH14_CMD; /**< APBH DMA Channel n Command Register, offset: 0x740 */ + uint8_t RESERVED_103[12]; + __I uint32_t CH14_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */ + uint8_t RESERVED_104[12]; + __IO uint32_t CH14_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */ + uint8_t RESERVED_105[12]; + __I uint32_t CH14_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */ + uint8_t RESERVED_106[12]; + __I uint32_t CH14_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */ + uint8_t RESERVED_107[12]; + __I uint32_t CH15_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */ + uint8_t RESERVED_108[12]; + __IO uint32_t CH15_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */ + uint8_t RESERVED_109[12]; + __I uint32_t CH15_CMD; /**< APBH DMA Channel n Command Register, offset: 0x7B0 */ + uint8_t RESERVED_110[12]; + __I uint32_t CH15_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */ + uint8_t RESERVED_111[12]; + __IO uint32_t CH15_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */ + uint8_t RESERVED_112[12]; + __I uint32_t CH15_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */ + uint8_t RESERVED_113[12]; + __I uint32_t CH15_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */ + uint8_t RESERVED_114[12]; + __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ +} APBH_Type; + +/* ---------------------------------------------------------------------------- + -- APBH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Masks APBH Register Masks + * @{ + */ + +/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_RSVD0_SHIFT (16U) +#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK) +#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK) +#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK) +#define APBH_CTRL0_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK) + +/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_SET_RSVD0_SHIFT (16U) +#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK) +#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK) +#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK) +#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SET_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK) + +/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U) +#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK) +#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK) +#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK) +#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U) +#define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK) + +/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U) +#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK) +#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK) +#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK) +#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U) +#define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK) + +/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK) + +/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK) + +/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */ +#define APBH_DEVSEL_CH0_MASK (0x3U) +#define APBH_DEVSEL_CH0_SHIFT (0U) +#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK) +#define APBH_DEVSEL_CH1_MASK (0xCU) +#define APBH_DEVSEL_CH1_SHIFT (2U) +#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK) +#define APBH_DEVSEL_CH2_MASK (0x30U) +#define APBH_DEVSEL_CH2_SHIFT (4U) +#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK) +#define APBH_DEVSEL_CH3_MASK (0xC0U) +#define APBH_DEVSEL_CH3_SHIFT (6U) +#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK) +#define APBH_DEVSEL_CH4_MASK (0x300U) +#define APBH_DEVSEL_CH4_SHIFT (8U) +#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK) +#define APBH_DEVSEL_CH5_MASK (0xC00U) +#define APBH_DEVSEL_CH5_SHIFT (10U) +#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK) +#define APBH_DEVSEL_CH6_MASK (0x3000U) +#define APBH_DEVSEL_CH6_SHIFT (12U) +#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK) +#define APBH_DEVSEL_CH7_MASK (0xC000U) +#define APBH_DEVSEL_CH7_SHIFT (14U) +#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK) +#define APBH_DEVSEL_CH8_MASK (0x30000U) +#define APBH_DEVSEL_CH8_SHIFT (16U) +#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK) +#define APBH_DEVSEL_CH9_MASK (0xC0000U) +#define APBH_DEVSEL_CH9_SHIFT (18U) +#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK) +#define APBH_DEVSEL_CH10_MASK (0x300000U) +#define APBH_DEVSEL_CH10_SHIFT (20U) +#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK) +#define APBH_DEVSEL_CH11_MASK (0xC00000U) +#define APBH_DEVSEL_CH11_SHIFT (22U) +#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK) +#define APBH_DEVSEL_CH12_MASK (0x3000000U) +#define APBH_DEVSEL_CH12_SHIFT (24U) +#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK) +#define APBH_DEVSEL_CH13_MASK (0xC000000U) +#define APBH_DEVSEL_CH13_SHIFT (26U) +#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK) +#define APBH_DEVSEL_CH14_MASK (0x30000000U) +#define APBH_DEVSEL_CH14_SHIFT (28U) +#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK) +#define APBH_DEVSEL_CH15_MASK (0xC0000000U) +#define APBH_DEVSEL_CH15_SHIFT (30U) +#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK) + +/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */ +#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U) +#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U) +#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK) +#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU) +#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U) +#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK) +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U) +#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U) +#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK) +#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U) +#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U) +#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK) +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U) +#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U) +#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK) +#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U) +#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U) +#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK) +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U) +#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U) +#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK) +#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U) +#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U) +#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK) +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U) +#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U) +#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK) +#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U) +#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U) +#define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK) +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U) +#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U) +#define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK) +#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U) +#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U) +#define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK) +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U) +#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U) +#define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK) +#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U) +#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U) +#define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK) +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U) +#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U) +#define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK) +#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U) +#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U) +#define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK) + +/*! @name DEBUG - AHB to APBH DMA Debug Register */ +#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U) +#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U) +#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK) + +/*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH0_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH0_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH0_CMD_COMMAND_MASK (0x3U) +#define APBH_CH0_CMD_COMMAND_SHIFT (0U) +#define APBH_CH0_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK) +#define APBH_CH0_CMD_CHAIN_MASK (0x4U) +#define APBH_CH0_CMD_CHAIN_SHIFT (2U) +#define APBH_CH0_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK) +#define APBH_CH0_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH0_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH0_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK) +#define APBH_CH0_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH0_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH0_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK) +#define APBH_CH0_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH0_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH0_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK) +#define APBH_CH0_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH0_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH0_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK) +#define APBH_CH0_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH0_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH0_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH0_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH0_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK) +#define APBH_CH0_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH0_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH0_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK) +#define APBH_CH0_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH0_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH0_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK) + +/*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH0_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH0_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH0_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK) + +/*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH0_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH0_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH0_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH0_SEMA_PHORE_SHIFT (16U) +#define APBH_CH0_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK) + +/*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH0_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH0_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH0_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH0_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH0_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RSVD1_SHIFT)) & APBH_CH0_DEBUG1_RSVD1_MASK) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH0_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH0_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH0_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_LOCK_SHIFT)) & APBH_CH0_DEBUG1_LOCK_MASK) +#define APBH_CH0_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH0_DEBUG1_READY_SHIFT (26U) +#define APBH_CH0_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK) +#define APBH_CH0_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH0_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH0_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_SENSE_SHIFT)) & APBH_CH0_DEBUG1_SENSE_MASK) +#define APBH_CH0_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH0_DEBUG1_END_SHIFT (28U) +#define APBH_CH0_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK) +#define APBH_CH0_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH0_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH0_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK) +#define APBH_CH0_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH0_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH0_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK) +#define APBH_CH0_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH0_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH0_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK) + +/*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH0_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH0_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH0_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH0_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH0_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK) + +/*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH1_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH1_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH1_CMD_COMMAND_MASK (0x3U) +#define APBH_CH1_CMD_COMMAND_SHIFT (0U) +#define APBH_CH1_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK) +#define APBH_CH1_CMD_CHAIN_MASK (0x4U) +#define APBH_CH1_CMD_CHAIN_SHIFT (2U) +#define APBH_CH1_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK) +#define APBH_CH1_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH1_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH1_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK) +#define APBH_CH1_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH1_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH1_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK) +#define APBH_CH1_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH1_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH1_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK) +#define APBH_CH1_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH1_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH1_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK) +#define APBH_CH1_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH1_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH1_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH1_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH1_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK) +#define APBH_CH1_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH1_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH1_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK) +#define APBH_CH1_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH1_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH1_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK) + +/*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH1_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH1_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH1_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK) + +/*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH1_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH1_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH1_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH1_SEMA_PHORE_SHIFT (16U) +#define APBH_CH1_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK) + +/*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH1_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH1_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH1_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH1_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH1_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RSVD1_SHIFT)) & APBH_CH1_DEBUG1_RSVD1_MASK) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH1_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH1_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH1_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_LOCK_SHIFT)) & APBH_CH1_DEBUG1_LOCK_MASK) +#define APBH_CH1_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH1_DEBUG1_READY_SHIFT (26U) +#define APBH_CH1_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK) +#define APBH_CH1_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH1_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH1_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_SENSE_SHIFT)) & APBH_CH1_DEBUG1_SENSE_MASK) +#define APBH_CH1_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH1_DEBUG1_END_SHIFT (28U) +#define APBH_CH1_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK) +#define APBH_CH1_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH1_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH1_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK) +#define APBH_CH1_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH1_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH1_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK) +#define APBH_CH1_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH1_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH1_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK) + +/*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH1_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH1_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH1_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH1_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH1_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK) + +/*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH2_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH2_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH2_CMD_COMMAND_MASK (0x3U) +#define APBH_CH2_CMD_COMMAND_SHIFT (0U) +#define APBH_CH2_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK) +#define APBH_CH2_CMD_CHAIN_MASK (0x4U) +#define APBH_CH2_CMD_CHAIN_SHIFT (2U) +#define APBH_CH2_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK) +#define APBH_CH2_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH2_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH2_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK) +#define APBH_CH2_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH2_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH2_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK) +#define APBH_CH2_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH2_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH2_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK) +#define APBH_CH2_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH2_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH2_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK) +#define APBH_CH2_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH2_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH2_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH2_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH2_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK) +#define APBH_CH2_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH2_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH2_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK) +#define APBH_CH2_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH2_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH2_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK) + +/*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH2_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH2_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH2_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK) + +/*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH2_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH2_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH2_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH2_SEMA_PHORE_SHIFT (16U) +#define APBH_CH2_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK) + +/*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH2_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH2_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH2_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH2_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH2_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RSVD1_SHIFT)) & APBH_CH2_DEBUG1_RSVD1_MASK) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH2_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH2_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH2_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_LOCK_SHIFT)) & APBH_CH2_DEBUG1_LOCK_MASK) +#define APBH_CH2_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH2_DEBUG1_READY_SHIFT (26U) +#define APBH_CH2_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK) +#define APBH_CH2_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH2_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH2_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_SENSE_SHIFT)) & APBH_CH2_DEBUG1_SENSE_MASK) +#define APBH_CH2_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH2_DEBUG1_END_SHIFT (28U) +#define APBH_CH2_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK) +#define APBH_CH2_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH2_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH2_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK) +#define APBH_CH2_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH2_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH2_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK) +#define APBH_CH2_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH2_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH2_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK) + +/*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH2_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH2_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH2_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH2_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH2_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK) + +/*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH3_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH3_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH3_CMD_COMMAND_MASK (0x3U) +#define APBH_CH3_CMD_COMMAND_SHIFT (0U) +#define APBH_CH3_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK) +#define APBH_CH3_CMD_CHAIN_MASK (0x4U) +#define APBH_CH3_CMD_CHAIN_SHIFT (2U) +#define APBH_CH3_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK) +#define APBH_CH3_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH3_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH3_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK) +#define APBH_CH3_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH3_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH3_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK) +#define APBH_CH3_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH3_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH3_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK) +#define APBH_CH3_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH3_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH3_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK) +#define APBH_CH3_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH3_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH3_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH3_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH3_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK) +#define APBH_CH3_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH3_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH3_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK) +#define APBH_CH3_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH3_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH3_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK) + +/*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH3_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH3_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH3_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK) + +/*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH3_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH3_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH3_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH3_SEMA_PHORE_SHIFT (16U) +#define APBH_CH3_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK) + +/*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH3_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH3_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH3_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH3_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH3_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RSVD1_SHIFT)) & APBH_CH3_DEBUG1_RSVD1_MASK) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH3_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH3_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH3_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_LOCK_SHIFT)) & APBH_CH3_DEBUG1_LOCK_MASK) +#define APBH_CH3_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH3_DEBUG1_READY_SHIFT (26U) +#define APBH_CH3_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK) +#define APBH_CH3_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH3_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH3_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_SENSE_SHIFT)) & APBH_CH3_DEBUG1_SENSE_MASK) +#define APBH_CH3_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH3_DEBUG1_END_SHIFT (28U) +#define APBH_CH3_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK) +#define APBH_CH3_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH3_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH3_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK) +#define APBH_CH3_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH3_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH3_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK) +#define APBH_CH3_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH3_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH3_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK) + +/*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH3_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH3_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH3_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH3_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH3_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK) + +/*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH4_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH4_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH4_CMD_COMMAND_MASK (0x3U) +#define APBH_CH4_CMD_COMMAND_SHIFT (0U) +#define APBH_CH4_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK) +#define APBH_CH4_CMD_CHAIN_MASK (0x4U) +#define APBH_CH4_CMD_CHAIN_SHIFT (2U) +#define APBH_CH4_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK) +#define APBH_CH4_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH4_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH4_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK) +#define APBH_CH4_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH4_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH4_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK) +#define APBH_CH4_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH4_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH4_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK) +#define APBH_CH4_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH4_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH4_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK) +#define APBH_CH4_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH4_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH4_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH4_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH4_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK) +#define APBH_CH4_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH4_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH4_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK) +#define APBH_CH4_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH4_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH4_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK) + +/*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH4_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH4_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH4_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK) + +/*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH4_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH4_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH4_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH4_SEMA_PHORE_SHIFT (16U) +#define APBH_CH4_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK) + +/*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH4_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH4_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH4_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH4_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH4_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RSVD1_SHIFT)) & APBH_CH4_DEBUG1_RSVD1_MASK) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH4_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH4_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH4_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_LOCK_SHIFT)) & APBH_CH4_DEBUG1_LOCK_MASK) +#define APBH_CH4_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH4_DEBUG1_READY_SHIFT (26U) +#define APBH_CH4_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK) +#define APBH_CH4_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH4_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH4_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_SENSE_SHIFT)) & APBH_CH4_DEBUG1_SENSE_MASK) +#define APBH_CH4_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH4_DEBUG1_END_SHIFT (28U) +#define APBH_CH4_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK) +#define APBH_CH4_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH4_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH4_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK) +#define APBH_CH4_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH4_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH4_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK) +#define APBH_CH4_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH4_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH4_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK) + +/*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH4_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH4_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH4_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH4_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH4_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK) + +/*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH5_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH5_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH5_CMD_COMMAND_MASK (0x3U) +#define APBH_CH5_CMD_COMMAND_SHIFT (0U) +#define APBH_CH5_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK) +#define APBH_CH5_CMD_CHAIN_MASK (0x4U) +#define APBH_CH5_CMD_CHAIN_SHIFT (2U) +#define APBH_CH5_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK) +#define APBH_CH5_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH5_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH5_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK) +#define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH5_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH5_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK) +#define APBH_CH5_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH5_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH5_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK) +#define APBH_CH5_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH5_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH5_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK) +#define APBH_CH5_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH5_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH5_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH5_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH5_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK) +#define APBH_CH5_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH5_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH5_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK) +#define APBH_CH5_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH5_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH5_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK) + +/*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH5_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH5_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH5_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK) + +/*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH5_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH5_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH5_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH5_SEMA_PHORE_SHIFT (16U) +#define APBH_CH5_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK) + +/*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH5_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH5_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH5_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH5_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH5_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RSVD1_SHIFT)) & APBH_CH5_DEBUG1_RSVD1_MASK) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH5_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH5_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH5_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_LOCK_SHIFT)) & APBH_CH5_DEBUG1_LOCK_MASK) +#define APBH_CH5_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH5_DEBUG1_READY_SHIFT (26U) +#define APBH_CH5_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK) +#define APBH_CH5_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH5_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH5_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_SENSE_SHIFT)) & APBH_CH5_DEBUG1_SENSE_MASK) +#define APBH_CH5_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH5_DEBUG1_END_SHIFT (28U) +#define APBH_CH5_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK) +#define APBH_CH5_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH5_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH5_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK) +#define APBH_CH5_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH5_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH5_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK) +#define APBH_CH5_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH5_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH5_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK) + +/*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH5_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH5_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH5_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH5_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH5_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK) + +/*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH6_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH6_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH6_CMD_COMMAND_MASK (0x3U) +#define APBH_CH6_CMD_COMMAND_SHIFT (0U) +#define APBH_CH6_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK) +#define APBH_CH6_CMD_CHAIN_MASK (0x4U) +#define APBH_CH6_CMD_CHAIN_SHIFT (2U) +#define APBH_CH6_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK) +#define APBH_CH6_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH6_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH6_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK) +#define APBH_CH6_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH6_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH6_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK) +#define APBH_CH6_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH6_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH6_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK) +#define APBH_CH6_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH6_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH6_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK) +#define APBH_CH6_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH6_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH6_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH6_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH6_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK) +#define APBH_CH6_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH6_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH6_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK) +#define APBH_CH6_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH6_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH6_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK) + +/*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH6_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH6_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH6_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK) + +/*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH6_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH6_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH6_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH6_SEMA_PHORE_SHIFT (16U) +#define APBH_CH6_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK) + +/*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH6_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH6_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH6_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH6_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH6_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RSVD1_SHIFT)) & APBH_CH6_DEBUG1_RSVD1_MASK) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH6_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH6_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH6_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_LOCK_SHIFT)) & APBH_CH6_DEBUG1_LOCK_MASK) +#define APBH_CH6_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH6_DEBUG1_READY_SHIFT (26U) +#define APBH_CH6_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK) +#define APBH_CH6_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH6_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH6_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_SENSE_SHIFT)) & APBH_CH6_DEBUG1_SENSE_MASK) +#define APBH_CH6_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH6_DEBUG1_END_SHIFT (28U) +#define APBH_CH6_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK) +#define APBH_CH6_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH6_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH6_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK) +#define APBH_CH6_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH6_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH6_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK) +#define APBH_CH6_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH6_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH6_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK) + +/*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH6_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH6_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH6_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH6_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH6_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK) + +/*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH7_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH7_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH7_CMD_COMMAND_MASK (0x3U) +#define APBH_CH7_CMD_COMMAND_SHIFT (0U) +#define APBH_CH7_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK) +#define APBH_CH7_CMD_CHAIN_MASK (0x4U) +#define APBH_CH7_CMD_CHAIN_SHIFT (2U) +#define APBH_CH7_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK) +#define APBH_CH7_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH7_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH7_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK) +#define APBH_CH7_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH7_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH7_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDLOCK_SHIFT)) & APBH_CH7_CMD_NANDLOCK_MASK) +#define APBH_CH7_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH7_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH7_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH7_CMD_NANDWAIT4READY_MASK) +#define APBH_CH7_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH7_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH7_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_SEMAPHORE_SHIFT)) & APBH_CH7_CMD_SEMAPHORE_MASK) +#define APBH_CH7_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH7_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH7_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH7_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH7_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH7_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH7_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH7_CMD_HALTONTERMINATE_MASK) +#define APBH_CH7_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH7_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH7_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CMDWORDS_SHIFT)) & APBH_CH7_CMD_CMDWORDS_MASK) +#define APBH_CH7_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH7_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH7_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_XFER_COUNT_SHIFT)) & APBH_CH7_CMD_XFER_COUNT_MASK) + +/*! @name CH7_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH7_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH7_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH7_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_BAR_ADDRESS_SHIFT)) & APBH_CH7_BAR_ADDRESS_MASK) + +/*! @name CH7_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH7_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH7_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH7_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH7_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH7_SEMA_PHORE_SHIFT (16U) +#define APBH_CH7_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_PHORE_SHIFT)) & APBH_CH7_SEMA_PHORE_MASK) + +/*! @name CH7_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH7_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH7_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH7_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH7_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH7_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH7_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH7_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RSVD1_SHIFT)) & APBH_CH7_DEBUG1_RSVD1_MASK) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH7_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH7_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH7_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_LOCK_SHIFT)) & APBH_CH7_DEBUG1_LOCK_MASK) +#define APBH_CH7_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH7_DEBUG1_READY_SHIFT (26U) +#define APBH_CH7_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_READY_SHIFT)) & APBH_CH7_DEBUG1_READY_MASK) +#define APBH_CH7_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH7_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH7_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_SENSE_SHIFT)) & APBH_CH7_DEBUG1_SENSE_MASK) +#define APBH_CH7_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH7_DEBUG1_END_SHIFT (28U) +#define APBH_CH7_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_END_SHIFT)) & APBH_CH7_DEBUG1_END_MASK) +#define APBH_CH7_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH7_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH7_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_KICK_SHIFT)) & APBH_CH7_DEBUG1_KICK_MASK) +#define APBH_CH7_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH7_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH7_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_BURST_SHIFT)) & APBH_CH7_DEBUG1_BURST_MASK) +#define APBH_CH7_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH7_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH7_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_REQ_SHIFT)) & APBH_CH7_DEBUG1_REQ_MASK) + +/*! @name CH7_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH7_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH7_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH7_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH7_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH7_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH7_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_APB_BYTES_MASK) + +/*! @name CH8_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH8_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH8_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH8_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH8_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH8_CMD_COMMAND_MASK (0x3U) +#define APBH_CH8_CMD_COMMAND_SHIFT (0U) +#define APBH_CH8_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_COMMAND_SHIFT)) & APBH_CH8_CMD_COMMAND_MASK) +#define APBH_CH8_CMD_CHAIN_MASK (0x4U) +#define APBH_CH8_CMD_CHAIN_SHIFT (2U) +#define APBH_CH8_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CHAIN_SHIFT)) & APBH_CH8_CMD_CHAIN_MASK) +#define APBH_CH8_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH8_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH8_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_IRQONCMPLT_SHIFT)) & APBH_CH8_CMD_IRQONCMPLT_MASK) +#define APBH_CH8_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH8_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH8_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDLOCK_SHIFT)) & APBH_CH8_CMD_NANDLOCK_MASK) +#define APBH_CH8_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH8_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH8_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH8_CMD_NANDWAIT4READY_MASK) +#define APBH_CH8_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH8_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH8_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_SEMAPHORE_SHIFT)) & APBH_CH8_CMD_SEMAPHORE_MASK) +#define APBH_CH8_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH8_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH8_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH8_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH8_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH8_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH8_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH8_CMD_HALTONTERMINATE_MASK) +#define APBH_CH8_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH8_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH8_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CMDWORDS_SHIFT)) & APBH_CH8_CMD_CMDWORDS_MASK) +#define APBH_CH8_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH8_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH8_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_XFER_COUNT_SHIFT)) & APBH_CH8_CMD_XFER_COUNT_MASK) + +/*! @name CH8_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH8_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH8_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH8_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_BAR_ADDRESS_SHIFT)) & APBH_CH8_BAR_ADDRESS_MASK) + +/*! @name CH8_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH8_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH8_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH8_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH8_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH8_SEMA_PHORE_SHIFT (16U) +#define APBH_CH8_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_PHORE_SHIFT)) & APBH_CH8_SEMA_PHORE_MASK) + +/*! @name CH8_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH8_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH8_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH8_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH8_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH8_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH8_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH8_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RSVD1_SHIFT)) & APBH_CH8_DEBUG1_RSVD1_MASK) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH8_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH8_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH8_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_LOCK_SHIFT)) & APBH_CH8_DEBUG1_LOCK_MASK) +#define APBH_CH8_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH8_DEBUG1_READY_SHIFT (26U) +#define APBH_CH8_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_READY_SHIFT)) & APBH_CH8_DEBUG1_READY_MASK) +#define APBH_CH8_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH8_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH8_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_SENSE_SHIFT)) & APBH_CH8_DEBUG1_SENSE_MASK) +#define APBH_CH8_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH8_DEBUG1_END_SHIFT (28U) +#define APBH_CH8_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_END_SHIFT)) & APBH_CH8_DEBUG1_END_MASK) +#define APBH_CH8_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH8_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH8_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_KICK_SHIFT)) & APBH_CH8_DEBUG1_KICK_MASK) +#define APBH_CH8_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH8_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH8_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_BURST_SHIFT)) & APBH_CH8_DEBUG1_BURST_MASK) +#define APBH_CH8_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH8_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH8_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_REQ_SHIFT)) & APBH_CH8_DEBUG1_REQ_MASK) + +/*! @name CH8_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH8_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH8_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH8_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH8_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH8_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH8_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_APB_BYTES_MASK) + +/*! @name CH9_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH9_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH9_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH9_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH9_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH9_CMD_COMMAND_MASK (0x3U) +#define APBH_CH9_CMD_COMMAND_SHIFT (0U) +#define APBH_CH9_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_COMMAND_SHIFT)) & APBH_CH9_CMD_COMMAND_MASK) +#define APBH_CH9_CMD_CHAIN_MASK (0x4U) +#define APBH_CH9_CMD_CHAIN_SHIFT (2U) +#define APBH_CH9_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CHAIN_SHIFT)) & APBH_CH9_CMD_CHAIN_MASK) +#define APBH_CH9_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH9_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH9_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_IRQONCMPLT_SHIFT)) & APBH_CH9_CMD_IRQONCMPLT_MASK) +#define APBH_CH9_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH9_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH9_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDLOCK_SHIFT)) & APBH_CH9_CMD_NANDLOCK_MASK) +#define APBH_CH9_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH9_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH9_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH9_CMD_NANDWAIT4READY_MASK) +#define APBH_CH9_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH9_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH9_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_SEMAPHORE_SHIFT)) & APBH_CH9_CMD_SEMAPHORE_MASK) +#define APBH_CH9_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH9_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH9_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH9_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH9_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH9_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH9_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH9_CMD_HALTONTERMINATE_MASK) +#define APBH_CH9_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH9_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH9_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CMDWORDS_SHIFT)) & APBH_CH9_CMD_CMDWORDS_MASK) +#define APBH_CH9_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH9_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH9_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_XFER_COUNT_SHIFT)) & APBH_CH9_CMD_XFER_COUNT_MASK) + +/*! @name CH9_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH9_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH9_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH9_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_BAR_ADDRESS_SHIFT)) & APBH_CH9_BAR_ADDRESS_MASK) + +/*! @name CH9_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH9_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH9_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH9_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH9_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH9_SEMA_PHORE_SHIFT (16U) +#define APBH_CH9_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_PHORE_SHIFT)) & APBH_CH9_SEMA_PHORE_MASK) + +/*! @name CH9_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH9_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH9_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH9_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH9_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH9_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH9_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH9_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RSVD1_SHIFT)) & APBH_CH9_DEBUG1_RSVD1_MASK) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH9_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH9_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH9_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_LOCK_SHIFT)) & APBH_CH9_DEBUG1_LOCK_MASK) +#define APBH_CH9_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH9_DEBUG1_READY_SHIFT (26U) +#define APBH_CH9_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_READY_SHIFT)) & APBH_CH9_DEBUG1_READY_MASK) +#define APBH_CH9_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH9_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH9_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_SENSE_SHIFT)) & APBH_CH9_DEBUG1_SENSE_MASK) +#define APBH_CH9_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH9_DEBUG1_END_SHIFT (28U) +#define APBH_CH9_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_END_SHIFT)) & APBH_CH9_DEBUG1_END_MASK) +#define APBH_CH9_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH9_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH9_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_KICK_SHIFT)) & APBH_CH9_DEBUG1_KICK_MASK) +#define APBH_CH9_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH9_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH9_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_BURST_SHIFT)) & APBH_CH9_DEBUG1_BURST_MASK) +#define APBH_CH9_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH9_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH9_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_REQ_SHIFT)) & APBH_CH9_DEBUG1_REQ_MASK) + +/*! @name CH9_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH9_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH9_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH9_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH9_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH9_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH9_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_APB_BYTES_MASK) + +/*! @name CH10_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH10_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH10_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH10_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH10_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH10_CMD_COMMAND_MASK (0x3U) +#define APBH_CH10_CMD_COMMAND_SHIFT (0U) +#define APBH_CH10_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_COMMAND_SHIFT)) & APBH_CH10_CMD_COMMAND_MASK) +#define APBH_CH10_CMD_CHAIN_MASK (0x4U) +#define APBH_CH10_CMD_CHAIN_SHIFT (2U) +#define APBH_CH10_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CHAIN_SHIFT)) & APBH_CH10_CMD_CHAIN_MASK) +#define APBH_CH10_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH10_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH10_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_IRQONCMPLT_SHIFT)) & APBH_CH10_CMD_IRQONCMPLT_MASK) +#define APBH_CH10_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH10_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH10_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDLOCK_SHIFT)) & APBH_CH10_CMD_NANDLOCK_MASK) +#define APBH_CH10_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH10_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH10_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH10_CMD_NANDWAIT4READY_MASK) +#define APBH_CH10_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH10_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH10_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_SEMAPHORE_SHIFT)) & APBH_CH10_CMD_SEMAPHORE_MASK) +#define APBH_CH10_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH10_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH10_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH10_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH10_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH10_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH10_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH10_CMD_HALTONTERMINATE_MASK) +#define APBH_CH10_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH10_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH10_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CMDWORDS_SHIFT)) & APBH_CH10_CMD_CMDWORDS_MASK) +#define APBH_CH10_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH10_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH10_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_XFER_COUNT_SHIFT)) & APBH_CH10_CMD_XFER_COUNT_MASK) + +/*! @name CH10_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH10_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH10_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH10_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_BAR_ADDRESS_SHIFT)) & APBH_CH10_BAR_ADDRESS_MASK) + +/*! @name CH10_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH10_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH10_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH10_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH10_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH10_SEMA_PHORE_SHIFT (16U) +#define APBH_CH10_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_PHORE_SHIFT)) & APBH_CH10_SEMA_PHORE_MASK) + +/*! @name CH10_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH10_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH10_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH10_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH10_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH10_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH10_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH10_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RSVD1_SHIFT)) & APBH_CH10_DEBUG1_RSVD1_MASK) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH10_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH10_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH10_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_LOCK_SHIFT)) & APBH_CH10_DEBUG1_LOCK_MASK) +#define APBH_CH10_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH10_DEBUG1_READY_SHIFT (26U) +#define APBH_CH10_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_READY_SHIFT)) & APBH_CH10_DEBUG1_READY_MASK) +#define APBH_CH10_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH10_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH10_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_SENSE_SHIFT)) & APBH_CH10_DEBUG1_SENSE_MASK) +#define APBH_CH10_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH10_DEBUG1_END_SHIFT (28U) +#define APBH_CH10_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_END_SHIFT)) & APBH_CH10_DEBUG1_END_MASK) +#define APBH_CH10_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH10_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH10_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_KICK_SHIFT)) & APBH_CH10_DEBUG1_KICK_MASK) +#define APBH_CH10_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH10_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH10_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_BURST_SHIFT)) & APBH_CH10_DEBUG1_BURST_MASK) +#define APBH_CH10_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH10_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH10_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_REQ_SHIFT)) & APBH_CH10_DEBUG1_REQ_MASK) + +/*! @name CH10_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH10_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH10_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH10_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH10_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH10_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH10_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_APB_BYTES_MASK) + +/*! @name CH11_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH11_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH11_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH11_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH11_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH11_CMD_COMMAND_MASK (0x3U) +#define APBH_CH11_CMD_COMMAND_SHIFT (0U) +#define APBH_CH11_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_COMMAND_SHIFT)) & APBH_CH11_CMD_COMMAND_MASK) +#define APBH_CH11_CMD_CHAIN_MASK (0x4U) +#define APBH_CH11_CMD_CHAIN_SHIFT (2U) +#define APBH_CH11_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CHAIN_SHIFT)) & APBH_CH11_CMD_CHAIN_MASK) +#define APBH_CH11_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH11_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH11_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_IRQONCMPLT_SHIFT)) & APBH_CH11_CMD_IRQONCMPLT_MASK) +#define APBH_CH11_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH11_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH11_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDLOCK_SHIFT)) & APBH_CH11_CMD_NANDLOCK_MASK) +#define APBH_CH11_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH11_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH11_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH11_CMD_NANDWAIT4READY_MASK) +#define APBH_CH11_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH11_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH11_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_SEMAPHORE_SHIFT)) & APBH_CH11_CMD_SEMAPHORE_MASK) +#define APBH_CH11_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH11_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH11_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH11_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH11_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH11_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH11_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH11_CMD_HALTONTERMINATE_MASK) +#define APBH_CH11_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH11_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH11_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CMDWORDS_SHIFT)) & APBH_CH11_CMD_CMDWORDS_MASK) +#define APBH_CH11_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH11_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH11_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_XFER_COUNT_SHIFT)) & APBH_CH11_CMD_XFER_COUNT_MASK) + +/*! @name CH11_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH11_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH11_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH11_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_BAR_ADDRESS_SHIFT)) & APBH_CH11_BAR_ADDRESS_MASK) + +/*! @name CH11_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH11_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH11_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH11_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH11_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH11_SEMA_PHORE_SHIFT (16U) +#define APBH_CH11_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_PHORE_SHIFT)) & APBH_CH11_SEMA_PHORE_MASK) + +/*! @name CH11_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH11_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH11_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH11_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH11_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH11_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH11_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH11_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RSVD1_SHIFT)) & APBH_CH11_DEBUG1_RSVD1_MASK) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH11_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH11_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH11_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_LOCK_SHIFT)) & APBH_CH11_DEBUG1_LOCK_MASK) +#define APBH_CH11_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH11_DEBUG1_READY_SHIFT (26U) +#define APBH_CH11_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_READY_SHIFT)) & APBH_CH11_DEBUG1_READY_MASK) +#define APBH_CH11_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH11_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH11_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_SENSE_SHIFT)) & APBH_CH11_DEBUG1_SENSE_MASK) +#define APBH_CH11_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH11_DEBUG1_END_SHIFT (28U) +#define APBH_CH11_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_END_SHIFT)) & APBH_CH11_DEBUG1_END_MASK) +#define APBH_CH11_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH11_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH11_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_KICK_SHIFT)) & APBH_CH11_DEBUG1_KICK_MASK) +#define APBH_CH11_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH11_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH11_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_BURST_SHIFT)) & APBH_CH11_DEBUG1_BURST_MASK) +#define APBH_CH11_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH11_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH11_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_REQ_SHIFT)) & APBH_CH11_DEBUG1_REQ_MASK) + +/*! @name CH11_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH11_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH11_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH11_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH11_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH11_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH11_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_APB_BYTES_MASK) + +/*! @name CH12_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH12_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH12_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH12_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH12_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH12_CMD_COMMAND_MASK (0x3U) +#define APBH_CH12_CMD_COMMAND_SHIFT (0U) +#define APBH_CH12_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_COMMAND_SHIFT)) & APBH_CH12_CMD_COMMAND_MASK) +#define APBH_CH12_CMD_CHAIN_MASK (0x4U) +#define APBH_CH12_CMD_CHAIN_SHIFT (2U) +#define APBH_CH12_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CHAIN_SHIFT)) & APBH_CH12_CMD_CHAIN_MASK) +#define APBH_CH12_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH12_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH12_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_IRQONCMPLT_SHIFT)) & APBH_CH12_CMD_IRQONCMPLT_MASK) +#define APBH_CH12_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH12_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH12_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDLOCK_SHIFT)) & APBH_CH12_CMD_NANDLOCK_MASK) +#define APBH_CH12_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH12_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH12_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH12_CMD_NANDWAIT4READY_MASK) +#define APBH_CH12_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH12_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH12_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_SEMAPHORE_SHIFT)) & APBH_CH12_CMD_SEMAPHORE_MASK) +#define APBH_CH12_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH12_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH12_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH12_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH12_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH12_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH12_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH12_CMD_HALTONTERMINATE_MASK) +#define APBH_CH12_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH12_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH12_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CMDWORDS_SHIFT)) & APBH_CH12_CMD_CMDWORDS_MASK) +#define APBH_CH12_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH12_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH12_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_XFER_COUNT_SHIFT)) & APBH_CH12_CMD_XFER_COUNT_MASK) + +/*! @name CH12_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH12_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH12_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH12_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_BAR_ADDRESS_SHIFT)) & APBH_CH12_BAR_ADDRESS_MASK) + +/*! @name CH12_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH12_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH12_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH12_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH12_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH12_SEMA_PHORE_SHIFT (16U) +#define APBH_CH12_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_PHORE_SHIFT)) & APBH_CH12_SEMA_PHORE_MASK) + +/*! @name CH12_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH12_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH12_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH12_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH12_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH12_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH12_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH12_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RSVD1_SHIFT)) & APBH_CH12_DEBUG1_RSVD1_MASK) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH12_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH12_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH12_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_LOCK_SHIFT)) & APBH_CH12_DEBUG1_LOCK_MASK) +#define APBH_CH12_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH12_DEBUG1_READY_SHIFT (26U) +#define APBH_CH12_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_READY_SHIFT)) & APBH_CH12_DEBUG1_READY_MASK) +#define APBH_CH12_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH12_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH12_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_SENSE_SHIFT)) & APBH_CH12_DEBUG1_SENSE_MASK) +#define APBH_CH12_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH12_DEBUG1_END_SHIFT (28U) +#define APBH_CH12_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_END_SHIFT)) & APBH_CH12_DEBUG1_END_MASK) +#define APBH_CH12_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH12_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH12_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_KICK_SHIFT)) & APBH_CH12_DEBUG1_KICK_MASK) +#define APBH_CH12_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH12_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH12_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_BURST_SHIFT)) & APBH_CH12_DEBUG1_BURST_MASK) +#define APBH_CH12_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH12_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH12_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_REQ_SHIFT)) & APBH_CH12_DEBUG1_REQ_MASK) + +/*! @name CH12_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH12_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH12_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH12_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH12_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH12_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH12_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_APB_BYTES_MASK) + +/*! @name CH13_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH13_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH13_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH13_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH13_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH13_CMD_COMMAND_MASK (0x3U) +#define APBH_CH13_CMD_COMMAND_SHIFT (0U) +#define APBH_CH13_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_COMMAND_SHIFT)) & APBH_CH13_CMD_COMMAND_MASK) +#define APBH_CH13_CMD_CHAIN_MASK (0x4U) +#define APBH_CH13_CMD_CHAIN_SHIFT (2U) +#define APBH_CH13_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CHAIN_SHIFT)) & APBH_CH13_CMD_CHAIN_MASK) +#define APBH_CH13_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH13_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH13_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_IRQONCMPLT_SHIFT)) & APBH_CH13_CMD_IRQONCMPLT_MASK) +#define APBH_CH13_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH13_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH13_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDLOCK_SHIFT)) & APBH_CH13_CMD_NANDLOCK_MASK) +#define APBH_CH13_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH13_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH13_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH13_CMD_NANDWAIT4READY_MASK) +#define APBH_CH13_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH13_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH13_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_SEMAPHORE_SHIFT)) & APBH_CH13_CMD_SEMAPHORE_MASK) +#define APBH_CH13_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH13_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH13_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH13_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH13_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH13_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH13_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH13_CMD_HALTONTERMINATE_MASK) +#define APBH_CH13_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH13_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH13_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CMDWORDS_SHIFT)) & APBH_CH13_CMD_CMDWORDS_MASK) +#define APBH_CH13_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH13_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH13_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_XFER_COUNT_SHIFT)) & APBH_CH13_CMD_XFER_COUNT_MASK) + +/*! @name CH13_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH13_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH13_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH13_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_BAR_ADDRESS_SHIFT)) & APBH_CH13_BAR_ADDRESS_MASK) + +/*! @name CH13_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH13_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH13_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH13_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH13_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH13_SEMA_PHORE_SHIFT (16U) +#define APBH_CH13_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_PHORE_SHIFT)) & APBH_CH13_SEMA_PHORE_MASK) + +/*! @name CH13_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH13_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH13_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH13_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH13_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH13_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH13_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH13_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RSVD1_SHIFT)) & APBH_CH13_DEBUG1_RSVD1_MASK) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH13_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH13_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH13_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_LOCK_SHIFT)) & APBH_CH13_DEBUG1_LOCK_MASK) +#define APBH_CH13_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH13_DEBUG1_READY_SHIFT (26U) +#define APBH_CH13_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_READY_SHIFT)) & APBH_CH13_DEBUG1_READY_MASK) +#define APBH_CH13_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH13_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH13_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_SENSE_SHIFT)) & APBH_CH13_DEBUG1_SENSE_MASK) +#define APBH_CH13_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH13_DEBUG1_END_SHIFT (28U) +#define APBH_CH13_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_END_SHIFT)) & APBH_CH13_DEBUG1_END_MASK) +#define APBH_CH13_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH13_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH13_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_KICK_SHIFT)) & APBH_CH13_DEBUG1_KICK_MASK) +#define APBH_CH13_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH13_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH13_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_BURST_SHIFT)) & APBH_CH13_DEBUG1_BURST_MASK) +#define APBH_CH13_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH13_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH13_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_REQ_SHIFT)) & APBH_CH13_DEBUG1_REQ_MASK) + +/*! @name CH13_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH13_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH13_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH13_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH13_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH13_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH13_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_APB_BYTES_MASK) + +/*! @name CH14_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH14_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH14_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH14_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH14_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH14_CMD_COMMAND_MASK (0x3U) +#define APBH_CH14_CMD_COMMAND_SHIFT (0U) +#define APBH_CH14_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_COMMAND_SHIFT)) & APBH_CH14_CMD_COMMAND_MASK) +#define APBH_CH14_CMD_CHAIN_MASK (0x4U) +#define APBH_CH14_CMD_CHAIN_SHIFT (2U) +#define APBH_CH14_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CHAIN_SHIFT)) & APBH_CH14_CMD_CHAIN_MASK) +#define APBH_CH14_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH14_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH14_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_IRQONCMPLT_SHIFT)) & APBH_CH14_CMD_IRQONCMPLT_MASK) +#define APBH_CH14_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH14_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH14_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDLOCK_SHIFT)) & APBH_CH14_CMD_NANDLOCK_MASK) +#define APBH_CH14_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH14_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH14_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH14_CMD_NANDWAIT4READY_MASK) +#define APBH_CH14_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH14_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH14_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_SEMAPHORE_SHIFT)) & APBH_CH14_CMD_SEMAPHORE_MASK) +#define APBH_CH14_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH14_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH14_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH14_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH14_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH14_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH14_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH14_CMD_HALTONTERMINATE_MASK) +#define APBH_CH14_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH14_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH14_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CMDWORDS_SHIFT)) & APBH_CH14_CMD_CMDWORDS_MASK) +#define APBH_CH14_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH14_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH14_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_XFER_COUNT_SHIFT)) & APBH_CH14_CMD_XFER_COUNT_MASK) + +/*! @name CH14_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH14_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH14_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH14_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_BAR_ADDRESS_SHIFT)) & APBH_CH14_BAR_ADDRESS_MASK) + +/*! @name CH14_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH14_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH14_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH14_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH14_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH14_SEMA_PHORE_SHIFT (16U) +#define APBH_CH14_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_PHORE_SHIFT)) & APBH_CH14_SEMA_PHORE_MASK) + +/*! @name CH14_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH14_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH14_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH14_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH14_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH14_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH14_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH14_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RSVD1_SHIFT)) & APBH_CH14_DEBUG1_RSVD1_MASK) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH14_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH14_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH14_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_LOCK_SHIFT)) & APBH_CH14_DEBUG1_LOCK_MASK) +#define APBH_CH14_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH14_DEBUG1_READY_SHIFT (26U) +#define APBH_CH14_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_READY_SHIFT)) & APBH_CH14_DEBUG1_READY_MASK) +#define APBH_CH14_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH14_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH14_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_SENSE_SHIFT)) & APBH_CH14_DEBUG1_SENSE_MASK) +#define APBH_CH14_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH14_DEBUG1_END_SHIFT (28U) +#define APBH_CH14_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_END_SHIFT)) & APBH_CH14_DEBUG1_END_MASK) +#define APBH_CH14_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH14_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH14_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_KICK_SHIFT)) & APBH_CH14_DEBUG1_KICK_MASK) +#define APBH_CH14_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH14_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH14_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_BURST_SHIFT)) & APBH_CH14_DEBUG1_BURST_MASK) +#define APBH_CH14_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH14_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH14_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_REQ_SHIFT)) & APBH_CH14_DEBUG1_REQ_MASK) + +/*! @name CH14_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH14_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH14_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH14_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH14_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH14_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH14_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_APB_BYTES_MASK) + +/*! @name CH15_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH15_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH15_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH15_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH15_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH15_CMD_COMMAND_MASK (0x3U) +#define APBH_CH15_CMD_COMMAND_SHIFT (0U) +#define APBH_CH15_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_COMMAND_SHIFT)) & APBH_CH15_CMD_COMMAND_MASK) +#define APBH_CH15_CMD_CHAIN_MASK (0x4U) +#define APBH_CH15_CMD_CHAIN_SHIFT (2U) +#define APBH_CH15_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CHAIN_SHIFT)) & APBH_CH15_CMD_CHAIN_MASK) +#define APBH_CH15_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH15_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH15_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_IRQONCMPLT_SHIFT)) & APBH_CH15_CMD_IRQONCMPLT_MASK) +#define APBH_CH15_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH15_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH15_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDLOCK_SHIFT)) & APBH_CH15_CMD_NANDLOCK_MASK) +#define APBH_CH15_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH15_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH15_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH15_CMD_NANDWAIT4READY_MASK) +#define APBH_CH15_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH15_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH15_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_SEMAPHORE_SHIFT)) & APBH_CH15_CMD_SEMAPHORE_MASK) +#define APBH_CH15_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH15_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH15_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH15_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH15_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH15_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH15_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH15_CMD_HALTONTERMINATE_MASK) +#define APBH_CH15_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH15_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH15_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CMDWORDS_SHIFT)) & APBH_CH15_CMD_CMDWORDS_MASK) +#define APBH_CH15_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH15_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH15_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_XFER_COUNT_SHIFT)) & APBH_CH15_CMD_XFER_COUNT_MASK) + +/*! @name CH15_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH15_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH15_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH15_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_BAR_ADDRESS_SHIFT)) & APBH_CH15_BAR_ADDRESS_MASK) + +/*! @name CH15_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH15_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH15_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH15_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH15_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH15_SEMA_PHORE_SHIFT (16U) +#define APBH_CH15_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_PHORE_SHIFT)) & APBH_CH15_SEMA_PHORE_MASK) + +/*! @name CH15_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH15_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH15_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH15_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH15_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH15_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH15_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH15_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RSVD1_SHIFT)) & APBH_CH15_DEBUG1_RSVD1_MASK) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH15_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH15_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH15_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_LOCK_SHIFT)) & APBH_CH15_DEBUG1_LOCK_MASK) +#define APBH_CH15_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH15_DEBUG1_READY_SHIFT (26U) +#define APBH_CH15_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_READY_SHIFT)) & APBH_CH15_DEBUG1_READY_MASK) +#define APBH_CH15_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH15_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH15_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_SENSE_SHIFT)) & APBH_CH15_DEBUG1_SENSE_MASK) +#define APBH_CH15_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH15_DEBUG1_END_SHIFT (28U) +#define APBH_CH15_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_END_SHIFT)) & APBH_CH15_DEBUG1_END_MASK) +#define APBH_CH15_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH15_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH15_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_KICK_SHIFT)) & APBH_CH15_DEBUG1_KICK_MASK) +#define APBH_CH15_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH15_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH15_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_BURST_SHIFT)) & APBH_CH15_DEBUG1_BURST_MASK) +#define APBH_CH15_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH15_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH15_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_REQ_SHIFT)) & APBH_CH15_DEBUG1_REQ_MASK) + +/*! @name CH15_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH15_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH15_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH15_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH15_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH15_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH15_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_APB_BYTES_MASK) + +/*! @name VERSION - APBH Bridge Version Register */ +#define APBH_VERSION_STEP_MASK (0xFFFFU) +#define APBH_VERSION_STEP_SHIFT (0U) +#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK) +#define APBH_VERSION_MINOR_MASK (0xFF0000U) +#define APBH_VERSION_MINOR_SHIFT (16U) +#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK) +#define APBH_VERSION_MAJOR_MASK (0xFF000000U) +#define APBH_VERSION_MAJOR_SHIFT (24U) +#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group APBH_Register_Masks */ + + +/* APBH - Peripheral instance base addresses */ +/** Peripheral APBH base address */ +#define APBH_BASE (0x1804000u) +/** Peripheral APBH base pointer */ +#define APBH ((APBH_Type *)APBH_BASE) +/** Array initializer of APBH peripheral base addresses */ +#define APBH_BASE_ADDRS { APBH_BASE } +/** Array initializer of APBH peripheral base pointers */ +#define APBH_BASE_PTRS { APBH } +/** Interrupt vectors for the APBH peripheral type */ +#define APBH_IRQS { APBH_IRQn } + +/*! + * @} + */ /* end of group APBH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ASRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer + * @{ + */ + +/** ASRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */ + __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */ + __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */ + __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */ + __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */ + __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */ + __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */ + uint8_t RESERVED_1[28]; + __IO uint32_t ASRPMn[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */ + __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */ + uint8_t RESERVED_2[4]; + __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */ + __IO uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */ + __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */ + __IO uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */ + __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */ + __IO uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */ + __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */ + uint8_t RESERVED_3[8]; + __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */ + __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */ + __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */ + __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */ + __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */ + __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */ + __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */ + __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */ + __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */ + __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */ + __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */ + __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */ + __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */ + __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */ + uint8_t RESERVED_4[8]; + __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */ +} ASRC_Type; + +/* ---------------------------------------------------------------------------- + -- ASRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Register_Masks ASRC Register Masks + * @{ + */ + +/*! @name ASRCTR - ASRC Control Register */ +#define ASRC_ASRCTR_ASRCEN_MASK (0x1U) +#define ASRC_ASRCTR_ASRCEN_SHIFT (0U) +#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK) +#define ASRC_ASRCTR_ASREA_MASK (0x2U) +#define ASRC_ASRCTR_ASREA_SHIFT (1U) +#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK) +#define ASRC_ASRCTR_ASREB_MASK (0x4U) +#define ASRC_ASRCTR_ASREB_SHIFT (2U) +#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK) +#define ASRC_ASRCTR_ASREC_MASK (0x8U) +#define ASRC_ASRCTR_ASREC_SHIFT (3U) +#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK) +#define ASRC_ASRCTR_SRST_MASK (0x10U) +#define ASRC_ASRCTR_SRST_SHIFT (4U) +#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK) +#define ASRC_ASRCTR_IDRA_MASK (0x2000U) +#define ASRC_ASRCTR_IDRA_SHIFT (13U) +#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK) +#define ASRC_ASRCTR_USRA_MASK (0x4000U) +#define ASRC_ASRCTR_USRA_SHIFT (14U) +#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK) +#define ASRC_ASRCTR_IDRB_MASK (0x8000U) +#define ASRC_ASRCTR_IDRB_SHIFT (15U) +#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK) +#define ASRC_ASRCTR_USRB_MASK (0x10000U) +#define ASRC_ASRCTR_USRB_SHIFT (16U) +#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK) +#define ASRC_ASRCTR_IDRC_MASK (0x20000U) +#define ASRC_ASRCTR_IDRC_SHIFT (17U) +#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK) +#define ASRC_ASRCTR_USRC_MASK (0x40000U) +#define ASRC_ASRCTR_USRC_SHIFT (18U) +#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK) +#define ASRC_ASRCTR_ATSA_MASK (0x100000U) +#define ASRC_ASRCTR_ATSA_SHIFT (20U) +#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK) +#define ASRC_ASRCTR_ATSB_MASK (0x200000U) +#define ASRC_ASRCTR_ATSB_SHIFT (21U) +#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK) +#define ASRC_ASRCTR_ATSC_MASK (0x400000U) +#define ASRC_ASRCTR_ATSC_SHIFT (22U) +#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK) + +/*! @name ASRIER - ASRC Interrupt Enable Register */ +#define ASRC_ASRIER_ADIEA_MASK (0x1U) +#define ASRC_ASRIER_ADIEA_SHIFT (0U) +#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK) +#define ASRC_ASRIER_ADIEB_MASK (0x2U) +#define ASRC_ASRIER_ADIEB_SHIFT (1U) +#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK) +#define ASRC_ASRIER_ADIEC_MASK (0x4U) +#define ASRC_ASRIER_ADIEC_SHIFT (2U) +#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK) +#define ASRC_ASRIER_ADOEA_MASK (0x8U) +#define ASRC_ASRIER_ADOEA_SHIFT (3U) +#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK) +#define ASRC_ASRIER_ADOEB_MASK (0x10U) +#define ASRC_ASRIER_ADOEB_SHIFT (4U) +#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK) +#define ASRC_ASRIER_ADOEC_MASK (0x20U) +#define ASRC_ASRIER_ADOEC_SHIFT (5U) +#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK) +#define ASRC_ASRIER_AOLIE_MASK (0x40U) +#define ASRC_ASRIER_AOLIE_SHIFT (6U) +#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK) +#define ASRC_ASRIER_AFPWE_MASK (0x80U) +#define ASRC_ASRIER_AFPWE_SHIFT (7U) +#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK) + +/*! @name ASRCNCR - ASRC Channel Number Configuration Register */ +#define ASRC_ASRCNCR_ANCA_MASK (0xFU) +#define ASRC_ASRCNCR_ANCA_SHIFT (0U) +#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK) +#define ASRC_ASRCNCR_ANCB_MASK (0xF0U) +#define ASRC_ASRCNCR_ANCB_SHIFT (4U) +#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK) +#define ASRC_ASRCNCR_ANCC_MASK (0xF00U) +#define ASRC_ASRCNCR_ANCC_SHIFT (8U) +#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK) + +/*! @name ASRCFG - ASRC Filter Configuration Status Register */ +#define ASRC_ASRCFG_PREMODA_MASK (0xC0U) +#define ASRC_ASRCFG_PREMODA_SHIFT (6U) +#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK) +#define ASRC_ASRCFG_POSTMODA_MASK (0x300U) +#define ASRC_ASRCFG_POSTMODA_SHIFT (8U) +#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK) +#define ASRC_ASRCFG_PREMODB_MASK (0xC00U) +#define ASRC_ASRCFG_PREMODB_SHIFT (10U) +#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK) +#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U) +#define ASRC_ASRCFG_POSTMODB_SHIFT (12U) +#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK) +#define ASRC_ASRCFG_PREMODC_MASK (0xC000U) +#define ASRC_ASRCFG_PREMODC_SHIFT (14U) +#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK) +#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U) +#define ASRC_ASRCFG_POSTMODC_SHIFT (16U) +#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK) +#define ASRC_ASRCFG_NDPRA_MASK (0x40000U) +#define ASRC_ASRCFG_NDPRA_SHIFT (18U) +#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK) +#define ASRC_ASRCFG_NDPRB_MASK (0x80000U) +#define ASRC_ASRCFG_NDPRB_SHIFT (19U) +#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK) +#define ASRC_ASRCFG_NDPRC_MASK (0x100000U) +#define ASRC_ASRCFG_NDPRC_SHIFT (20U) +#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK) +#define ASRC_ASRCFG_INIRQA_MASK (0x200000U) +#define ASRC_ASRCFG_INIRQA_SHIFT (21U) +#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK) +#define ASRC_ASRCFG_INIRQB_MASK (0x400000U) +#define ASRC_ASRCFG_INIRQB_SHIFT (22U) +#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK) +#define ASRC_ASRCFG_INIRQC_MASK (0x800000U) +#define ASRC_ASRCFG_INIRQC_SHIFT (23U) +#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK) + +/*! @name ASRCSR - ASRC Clock Source Register */ +#define ASRC_ASRCSR_AICSA_MASK (0xFU) +#define ASRC_ASRCSR_AICSA_SHIFT (0U) +#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK) +#define ASRC_ASRCSR_AICSB_MASK (0xF0U) +#define ASRC_ASRCSR_AICSB_SHIFT (4U) +#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK) +#define ASRC_ASRCSR_AICSC_MASK (0xF00U) +#define ASRC_ASRCSR_AICSC_SHIFT (8U) +#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK) +#define ASRC_ASRCSR_AOCSA_MASK (0xF000U) +#define ASRC_ASRCSR_AOCSA_SHIFT (12U) +#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK) +#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U) +#define ASRC_ASRCSR_AOCSB_SHIFT (16U) +#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK) +#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U) +#define ASRC_ASRCSR_AOCSC_SHIFT (20U) +#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK) + +/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */ +#define ASRC_ASRCDR1_AICPA_MASK (0x7U) +#define ASRC_ASRCDR1_AICPA_SHIFT (0U) +#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK) +#define ASRC_ASRCDR1_AICDA_MASK (0x38U) +#define ASRC_ASRCDR1_AICDA_SHIFT (3U) +#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK) +#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U) +#define ASRC_ASRCDR1_AICPB_SHIFT (6U) +#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK) +#define ASRC_ASRCDR1_AICDB_MASK (0xE00U) +#define ASRC_ASRCDR1_AICDB_SHIFT (9U) +#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK) +#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U) +#define ASRC_ASRCDR1_AOCPA_SHIFT (12U) +#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK) +#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U) +#define ASRC_ASRCDR1_AOCDA_SHIFT (15U) +#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK) +#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U) +#define ASRC_ASRCDR1_AOCPB_SHIFT (18U) +#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK) +#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U) +#define ASRC_ASRCDR1_AOCDB_SHIFT (21U) +#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK) + +/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */ +#define ASRC_ASRCDR2_AICPC_MASK (0x7U) +#define ASRC_ASRCDR2_AICPC_SHIFT (0U) +#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK) +#define ASRC_ASRCDR2_AICDC_MASK (0x38U) +#define ASRC_ASRCDR2_AICDC_SHIFT (3U) +#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK) +#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U) +#define ASRC_ASRCDR2_AOCPC_SHIFT (6U) +#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK) +#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U) +#define ASRC_ASRCDR2_AOCDC_SHIFT (9U) +#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK) + +/*! @name ASRSTR - ASRC Status Register */ +#define ASRC_ASRSTR_AIDEA_MASK (0x1U) +#define ASRC_ASRSTR_AIDEA_SHIFT (0U) +#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK) +#define ASRC_ASRSTR_AIDEB_MASK (0x2U) +#define ASRC_ASRSTR_AIDEB_SHIFT (1U) +#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK) +#define ASRC_ASRSTR_AIDEC_MASK (0x4U) +#define ASRC_ASRSTR_AIDEC_SHIFT (2U) +#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK) +#define ASRC_ASRSTR_AODFA_MASK (0x8U) +#define ASRC_ASRSTR_AODFA_SHIFT (3U) +#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK) +#define ASRC_ASRSTR_AODFB_MASK (0x10U) +#define ASRC_ASRSTR_AODFB_SHIFT (4U) +#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK) +#define ASRC_ASRSTR_AODFC_MASK (0x20U) +#define ASRC_ASRSTR_AODFC_SHIFT (5U) +#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK) +#define ASRC_ASRSTR_AOLE_MASK (0x40U) +#define ASRC_ASRSTR_AOLE_SHIFT (6U) +#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK) +#define ASRC_ASRSTR_FPWT_MASK (0x80U) +#define ASRC_ASRSTR_FPWT_SHIFT (7U) +#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK) +#define ASRC_ASRSTR_AIDUA_MASK (0x100U) +#define ASRC_ASRSTR_AIDUA_SHIFT (8U) +#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK) +#define ASRC_ASRSTR_AIDUB_MASK (0x200U) +#define ASRC_ASRSTR_AIDUB_SHIFT (9U) +#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK) +#define ASRC_ASRSTR_AIDUC_MASK (0x400U) +#define ASRC_ASRSTR_AIDUC_SHIFT (10U) +#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK) +#define ASRC_ASRSTR_AODOA_MASK (0x800U) +#define ASRC_ASRSTR_AODOA_SHIFT (11U) +#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK) +#define ASRC_ASRSTR_AODOB_MASK (0x1000U) +#define ASRC_ASRSTR_AODOB_SHIFT (12U) +#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK) +#define ASRC_ASRSTR_AODOC_MASK (0x2000U) +#define ASRC_ASRSTR_AODOC_SHIFT (13U) +#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK) +#define ASRC_ASRSTR_AIOLA_MASK (0x4000U) +#define ASRC_ASRSTR_AIOLA_SHIFT (14U) +#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK) +#define ASRC_ASRSTR_AIOLB_MASK (0x8000U) +#define ASRC_ASRSTR_AIOLB_SHIFT (15U) +#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK) +#define ASRC_ASRSTR_AIOLC_MASK (0x10000U) +#define ASRC_ASRSTR_AIOLC_SHIFT (16U) +#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK) +#define ASRC_ASRSTR_AOOLA_MASK (0x20000U) +#define ASRC_ASRSTR_AOOLA_SHIFT (17U) +#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK) +#define ASRC_ASRSTR_AOOLB_MASK (0x40000U) +#define ASRC_ASRSTR_AOOLB_SHIFT (18U) +#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK) +#define ASRC_ASRSTR_AOOLC_MASK (0x80000U) +#define ASRC_ASRSTR_AOOLC_SHIFT (19U) +#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK) +#define ASRC_ASRSTR_ATQOL_MASK (0x100000U) +#define ASRC_ASRSTR_ATQOL_SHIFT (20U) +#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK) +#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U) +#define ASRC_ASRSTR_DSLCNT_SHIFT (21U) +#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK) + +/*! @name ASRPMn - ASRC Parameter Register n */ +#define ASRC_ASRPMn_PARAMETER_VALUE_MASK (0xFFFFFFU) +#define ASRC_ASRPMn_PARAMETER_VALUE_SHIFT (0U) +#define ASRC_ASRPMn_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPMn_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPMn_PARAMETER_VALUE_MASK) + +/* The count of ASRC_ASRPMn */ +#define ASRC_ASRPMn_COUNT (5U) + +/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */ +#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U) +#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U) +#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK) +#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U) +#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U) +#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK) + +/*! @name ASRCCR - ASRC Channel Counter Register */ +#define ASRC_ASRCCR_ACIA_MASK (0xFU) +#define ASRC_ASRCCR_ACIA_SHIFT (0U) +#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK) +#define ASRC_ASRCCR_ACIB_MASK (0xF0U) +#define ASRC_ASRCCR_ACIB_SHIFT (4U) +#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK) +#define ASRC_ASRCCR_ACIC_MASK (0xF00U) +#define ASRC_ASRCCR_ACIC_SHIFT (8U) +#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK) +#define ASRC_ASRCCR_ACOA_MASK (0xF000U) +#define ASRC_ASRCCR_ACOA_SHIFT (12U) +#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK) +#define ASRC_ASRCCR_ACOB_MASK (0xF0000U) +#define ASRC_ASRCCR_ACOB_SHIFT (16U) +#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK) +#define ASRC_ASRCCR_ACOC_MASK (0xF00000U) +#define ASRC_ASRCCR_ACOC_SHIFT (20U) +#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK) + +/*! @name ASRDIA - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIA_DATA_SHIFT (0U) +#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK) + +/*! @name ASRDOA - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOA_DATA_SHIFT (0U) +#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK) + +/*! @name ASRDIB - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIB_DATA_SHIFT (0U) +#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK) + +/*! @name ASRDOB - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOB_DATA_SHIFT (0U) +#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK) + +/*! @name ASRDIC - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIC_DATA_SHIFT (0U) +#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK) + +/*! @name ASRDOC - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOC_DATA_SHIFT (0U) +#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK) + +/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */ +#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU) +#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U) +#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK) + +/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */ +#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U) +#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK) + +/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */ +#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU) +#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U) +#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK) + +/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */ +#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U) +#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK) + +/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */ +#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU) +#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U) +#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK) + +/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */ +#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U) +#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK) + +/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */ +#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU) +#define ASRC_ASR76K_ASR76K_SHIFT (0U) +#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK) + +/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */ +#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU) +#define ASRC_ASR56K_ASR56K_SHIFT (0U) +#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK) + +/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */ +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU) +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U) +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK) +#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U) +#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U) +#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK) +#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U) +#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U) +#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK) +#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U) +#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U) +#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK) +#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U) +#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U) +#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK) +#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U) +#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U) +#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK) +#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U) +#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U) +#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK) + +/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */ +#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU) +#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U) +#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK) +#define ASRC_ASRFSTA_IAEA_MASK (0x800U) +#define ASRC_ASRFSTA_IAEA_SHIFT (11U) +#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK) +#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U) +#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U) +#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK) +#define ASRC_ASRFSTA_OAFA_MASK (0x800000U) +#define ASRC_ASRFSTA_OAFA_SHIFT (23U) +#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK) + +/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */ +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU) +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U) +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK) +#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U) +#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U) +#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK) +#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U) +#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U) +#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK) +#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U) +#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U) +#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK) +#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U) +#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U) +#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK) +#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U) +#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U) +#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK) +#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U) +#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U) +#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK) + +/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */ +#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU) +#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U) +#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK) +#define ASRC_ASRFSTB_IAEB_MASK (0x800U) +#define ASRC_ASRFSTB_IAEB_SHIFT (11U) +#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK) +#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U) +#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U) +#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK) +#define ASRC_ASRFSTB_OAFB_MASK (0x800000U) +#define ASRC_ASRFSTB_OAFB_SHIFT (23U) +#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK) + +/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */ +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU) +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U) +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK) +#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U) +#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U) +#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK) +#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U) +#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U) +#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK) +#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U) +#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U) +#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK) +#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U) +#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U) +#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK) +#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U) +#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U) +#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK) +#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U) +#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U) +#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK) + +/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */ +#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU) +#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U) +#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK) +#define ASRC_ASRFSTC_IAEC_MASK (0x800U) +#define ASRC_ASRFSTC_IAEC_SHIFT (11U) +#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK) +#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U) +#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U) +#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK) +#define ASRC_ASRFSTC_OAFC_MASK (0x800000U) +#define ASRC_ASRFSTC_OAFC_SHIFT (23U) +#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK) + +/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */ +#define ASRC_ASRMCR1_OW16_MASK (0x1U) +#define ASRC_ASRMCR1_OW16_SHIFT (0U) +#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK) +#define ASRC_ASRMCR1_OSGN_MASK (0x2U) +#define ASRC_ASRMCR1_OSGN_SHIFT (1U) +#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK) +#define ASRC_ASRMCR1_OMSB_MASK (0x4U) +#define ASRC_ASRMCR1_OMSB_SHIFT (2U) +#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK) +#define ASRC_ASRMCR1_IMSB_MASK (0x100U) +#define ASRC_ASRMCR1_IMSB_SHIFT (8U) +#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK) +#define ASRC_ASRMCR1_IWD_MASK (0xE00U) +#define ASRC_ASRMCR1_IWD_SHIFT (9U) +#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK) + +/* The count of ASRC_ASRMCR1 */ +#define ASRC_ASRMCR1_COUNT (3U) + + +/*! + * @} + */ /* end of group ASRC_Register_Masks */ + + +/* ASRC - Peripheral instance base addresses */ +/** Peripheral ASRC base address */ +#define ASRC_BASE (0x2034000u) +/** Peripheral ASRC base pointer */ +#define ASRC ((ASRC_Type *)ASRC_BASE) +/** Array initializer of ASRC peripheral base addresses */ +#define ASRC_BASE_ADDRS { ASRC_BASE } +/** Array initializer of ASRC peripheral base pointers */ +#define ASRC_BASE_PTRS { ASRC } +/** Interrupt vectors for the ASRC peripheral type */ +#define ASRC_IRQS { ASRC_IRQn } + +/*! + * @} + */ /* end of group ASRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BCH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer + * @{ + */ + +/** BCH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ + __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ + __I uint32_t STATUS0_SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ + __I uint32_t STATUS0_CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ + __I uint32_t STATUS0_TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ + __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ + __IO uint32_t MODE_SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ + __IO uint32_t MODE_CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ + __IO uint32_t MODE_TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ + __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ + __IO uint32_t ENCODEPTR_SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ + __IO uint32_t ENCODEPTR_CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ + __IO uint32_t ENCODEPTR_TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ + __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ + __IO uint32_t DATAPTR_SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ + __IO uint32_t DATAPTR_CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ + __IO uint32_t DATAPTR_TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ + __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ + __IO uint32_t METAPTR_SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ + __IO uint32_t METAPTR_CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ + __IO uint32_t METAPTR_TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ + uint8_t RESERVED_0[16]; + __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ + __IO uint32_t LAYOUTSELECT_SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ + __IO uint32_t LAYOUTSELECT_CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ + __IO uint32_t LAYOUTSELECT_TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ + __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ + __IO uint32_t FLASH0LAYOUT0_SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ + __IO uint32_t FLASH0LAYOUT0_CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ + __IO uint32_t FLASH0LAYOUT0_TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ + __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ + __IO uint32_t FLASH0LAYOUT1_SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ + __IO uint32_t FLASH0LAYOUT1_CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ + __IO uint32_t FLASH0LAYOUT1_TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ + __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ + __IO uint32_t FLASH1LAYOUT0_SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ + __IO uint32_t FLASH1LAYOUT0_CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ + __IO uint32_t FLASH1LAYOUT0_TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ + __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ + __IO uint32_t FLASH1LAYOUT1_SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ + __IO uint32_t FLASH1LAYOUT1_CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ + __IO uint32_t FLASH1LAYOUT1_TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ + __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ + __IO uint32_t FLASH2LAYOUT0_SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ + __IO uint32_t FLASH2LAYOUT0_CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ + __IO uint32_t FLASH2LAYOUT0_TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ + __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ + __IO uint32_t FLASH2LAYOUT1_SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ + __IO uint32_t FLASH2LAYOUT1_CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ + __IO uint32_t FLASH2LAYOUT1_TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ + __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ + __IO uint32_t FLASH3LAYOUT0_SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ + __IO uint32_t FLASH3LAYOUT0_CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ + __IO uint32_t FLASH3LAYOUT0_TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ + __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ + __IO uint32_t FLASH3LAYOUT1_SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ + __IO uint32_t FLASH3LAYOUT1_CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ + __IO uint32_t FLASH3LAYOUT1_TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ + __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ + __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ + __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ + __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ + __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */ + __I uint32_t DBGKESREAD_SET; /**< KES Debug Read Register, offset: 0x114 */ + __I uint32_t DBGKESREAD_CLR; /**< KES Debug Read Register, offset: 0x118 */ + __I uint32_t DBGKESREAD_TOG; /**< KES Debug Read Register, offset: 0x11C */ + __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */ + __I uint32_t DBGCSFEREAD_SET; /**< Chien Search Debug Read Register, offset: 0x124 */ + __I uint32_t DBGCSFEREAD_CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ + __I uint32_t DBGCSFEREAD_TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ + __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ + __I uint32_t DBGSYNDGENREAD_SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ + __I uint32_t DBGSYNDGENREAD_CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ + __I uint32_t DBGSYNDGENREAD_TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ + __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ + __I uint32_t DBGAHBMREAD_SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ + __I uint32_t DBGAHBMREAD_CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ + __I uint32_t DBGAHBMREAD_TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ + __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */ + __I uint32_t BLOCKNAME_SET; /**< Block Name Register, offset: 0x154 */ + __I uint32_t BLOCKNAME_CLR; /**< Block Name Register, offset: 0x158 */ + __I uint32_t BLOCKNAME_TOG; /**< Block Name Register, offset: 0x15C */ + __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */ + __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */ + __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */ + __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */ + __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ + __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ + __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ + __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ +} BCH_Type; + +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK) +#define BCH_CTRL_RSVD0_MASK (0x2U) +#define BCH_CTRL_RSVD0_SHIFT (1U) +#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK) +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_RSVD1_MASK (0xF0U) +#define BCH_CTRL_RSVD1_SHIFT (4U) +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK) +#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_RSVD2_MASK (0x200U) +#define BCH_CTRL_RSVD2_SHIFT (9U) +#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_RSVD3_MASK (0xF800U) +#define BCH_CTRL_RSVD3_SHIFT (11U) +#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK) +#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK) +#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK) +#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK) +#define BCH_CTRL_RSVD4_MASK (0x300000U) +#define BCH_CTRL_RSVD4_SHIFT (20U) +#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK) +#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK) +#define BCH_CTRL_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_RSVD5_SHIFT (23U) +#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK) +#define BCH_CTRL_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLKGATE_SHIFT (30U) +#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK) +#define BCH_CTRL_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SFTRST_SHIFT (31U) +#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_SET_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK) +#define BCH_CTRL_SET_RSVD0_MASK (0x2U) +#define BCH_CTRL_SET_RSVD0_SHIFT (1U) +#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_SET_RSVD1_MASK (0xF0U) +#define BCH_CTRL_SET_RSVD1_SHIFT (4U) +#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_SET_RSVD2_MASK (0x200U) +#define BCH_CTRL_SET_RSVD2_SHIFT (9U) +#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_SET_RSVD3_MASK (0xF800U) +#define BCH_CTRL_SET_RSVD3_SHIFT (11U) +#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK) +#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_SET_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK) +#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_SET_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK) +#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK) +#define BCH_CTRL_SET_RSVD4_MASK (0x300000U) +#define BCH_CTRL_SET_RSVD4_SHIFT (20U) +#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK) +#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_SET_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK) +#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_SET_RSVD5_SHIFT (23U) +#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK) +#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_SET_CLKGATE_SHIFT (30U) +#define BCH_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK) +#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SET_SFTRST_SHIFT (31U) +#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_CLR_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK) +#define BCH_CTRL_CLR_RSVD0_MASK (0x2U) +#define BCH_CTRL_CLR_RSVD0_SHIFT (1U) +#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U) +#define BCH_CTRL_CLR_RSVD1_SHIFT (4U) +#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_CLR_RSVD2_MASK (0x200U) +#define BCH_CTRL_CLR_RSVD2_SHIFT (9U) +#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U) +#define BCH_CTRL_CLR_RSVD3_SHIFT (11U) +#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK) +#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_CLR_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK) +#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_CLR_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK) +#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK) +#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U) +#define BCH_CTRL_CLR_RSVD4_SHIFT (20U) +#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK) +#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_CLR_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK) +#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_CLR_RSVD5_SHIFT (23U) +#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK) +#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U) +#define BCH_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK) +#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_CLR_SFTRST_SHIFT (31U) +#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_TOG_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK) +#define BCH_CTRL_TOG_RSVD0_MASK (0x2U) +#define BCH_CTRL_TOG_RSVD0_SHIFT (1U) +#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U) +#define BCH_CTRL_TOG_RSVD1_SHIFT (4U) +#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_TOG_RSVD2_MASK (0x200U) +#define BCH_CTRL_TOG_RSVD2_SHIFT (9U) +#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U) +#define BCH_CTRL_TOG_RSVD3_SHIFT (11U) +#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK) +#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_TOG_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK) +#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_TOG_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK) +#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK) +#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U) +#define BCH_CTRL_TOG_RSVD4_SHIFT (20U) +#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK) +#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_TOG_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK) +#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_TOG_RSVD5_SHIFT (23U) +#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK) +#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U) +#define BCH_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK) +#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_TOG_SFTRST_SHIFT (31U) +#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK) + +/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_RSVD0_MASK (0x3U) +#define BCH_STATUS0_RSVD0_SHIFT (0U) +#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK) +#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK) +#define BCH_STATUS0_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK) +#define BCH_STATUS0_ALLONES_MASK (0x10U) +#define BCH_STATUS0_ALLONES_SHIFT (4U) +#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK) +#define BCH_STATUS0_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_RSVD1_SHIFT (5U) +#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK) +#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK) +#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK) +#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_HANDLE_SHIFT (20U) +#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK) + +/*! @name STATUS0_SET - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_SET_RSVD0_MASK (0x3U) +#define BCH_STATUS0_SET_RSVD0_SHIFT (0U) +#define BCH_STATUS0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD0_SHIFT)) & BCH_STATUS0_SET_RSVD0_MASK) +#define BCH_STATUS0_SET_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_SET_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_SET_UNCORRECTABLE_MASK) +#define BCH_STATUS0_SET_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_SET_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_SET_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_CORRECTED_SHIFT)) & BCH_STATUS0_SET_CORRECTED_MASK) +#define BCH_STATUS0_SET_ALLONES_MASK (0x10U) +#define BCH_STATUS0_SET_ALLONES_SHIFT (4U) +#define BCH_STATUS0_SET_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_ALLONES_SHIFT)) & BCH_STATUS0_SET_ALLONES_MASK) +#define BCH_STATUS0_SET_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_SET_RSVD1_SHIFT (5U) +#define BCH_STATUS0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD1_SHIFT)) & BCH_STATUS0_SET_RSVD1_MASK) +#define BCH_STATUS0_SET_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_SET_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_SET_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_STATUS_BLK0_SHIFT)) & BCH_STATUS0_SET_STATUS_BLK0_MASK) +#define BCH_STATUS0_SET_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_SET_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_SET_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_COMPLETED_CE_SHIFT)) & BCH_STATUS0_SET_COMPLETED_CE_MASK) +#define BCH_STATUS0_SET_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_SET_HANDLE_SHIFT (20U) +#define BCH_STATUS0_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_HANDLE_SHIFT)) & BCH_STATUS0_SET_HANDLE_MASK) + +/*! @name STATUS0_CLR - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) +#define BCH_STATUS0_CLR_RSVD0_SHIFT (0U) +#define BCH_STATUS0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK) +#define BCH_STATUS0_CLR_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_CLR_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_CLR_UNCORRECTABLE_MASK) +#define BCH_STATUS0_CLR_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CLR_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CLR_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_CORRECTED_SHIFT)) & BCH_STATUS0_CLR_CORRECTED_MASK) +#define BCH_STATUS0_CLR_ALLONES_MASK (0x10U) +#define BCH_STATUS0_CLR_ALLONES_SHIFT (4U) +#define BCH_STATUS0_CLR_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_ALLONES_SHIFT)) & BCH_STATUS0_CLR_ALLONES_MASK) +#define BCH_STATUS0_CLR_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_CLR_RSVD1_SHIFT (5U) +#define BCH_STATUS0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD1_SHIFT)) & BCH_STATUS0_CLR_RSVD1_MASK) +#define BCH_STATUS0_CLR_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_CLR_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_STATUS_BLK0_SHIFT)) & BCH_STATUS0_CLR_STATUS_BLK0_MASK) +#define BCH_STATUS0_CLR_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_CLR_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_COMPLETED_CE_SHIFT)) & BCH_STATUS0_CLR_COMPLETED_CE_MASK) +#define BCH_STATUS0_CLR_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_CLR_HANDLE_SHIFT (20U) +#define BCH_STATUS0_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_HANDLE_SHIFT)) & BCH_STATUS0_CLR_HANDLE_MASK) + +/*! @name STATUS0_TOG - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_TOG_RSVD0_MASK (0x3U) +#define BCH_STATUS0_TOG_RSVD0_SHIFT (0U) +#define BCH_STATUS0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD0_SHIFT)) & BCH_STATUS0_TOG_RSVD0_MASK) +#define BCH_STATUS0_TOG_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_TOG_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_TOG_UNCORRECTABLE_MASK) +#define BCH_STATUS0_TOG_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_TOG_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_TOG_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_CORRECTED_SHIFT)) & BCH_STATUS0_TOG_CORRECTED_MASK) +#define BCH_STATUS0_TOG_ALLONES_MASK (0x10U) +#define BCH_STATUS0_TOG_ALLONES_SHIFT (4U) +#define BCH_STATUS0_TOG_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_ALLONES_SHIFT)) & BCH_STATUS0_TOG_ALLONES_MASK) +#define BCH_STATUS0_TOG_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_TOG_RSVD1_SHIFT (5U) +#define BCH_STATUS0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD1_SHIFT)) & BCH_STATUS0_TOG_RSVD1_MASK) +#define BCH_STATUS0_TOG_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_TOG_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_STATUS_BLK0_SHIFT)) & BCH_STATUS0_TOG_STATUS_BLK0_MASK) +#define BCH_STATUS0_TOG_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_TOG_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_COMPLETED_CE_SHIFT)) & BCH_STATUS0_TOG_COMPLETED_CE_MASK) +#define BCH_STATUS0_TOG_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_TOG_HANDLE_SHIFT (20U) +#define BCH_STATUS0_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_HANDLE_SHIFT)) & BCH_STATUS0_TOG_HANDLE_MASK) + +/*! @name MODE - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK) +#define BCH_MODE_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_RSVD_SHIFT (8U) +#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK) + +/*! @name MODE_SET - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_SET_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_SET_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_SET_ERASE_THRESHOLD_MASK) +#define BCH_MODE_SET_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_SET_RSVD_SHIFT (8U) +#define BCH_MODE_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_RSVD_SHIFT)) & BCH_MODE_SET_RSVD_MASK) + +/*! @name MODE_CLR - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_CLR_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_CLR_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_CLR_ERASE_THRESHOLD_MASK) +#define BCH_MODE_CLR_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_CLR_RSVD_SHIFT (8U) +#define BCH_MODE_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_RSVD_SHIFT)) & BCH_MODE_CLR_RSVD_MASK) + +/*! @name MODE_TOG - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_TOG_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_TOG_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_TOG_ERASE_THRESHOLD_MASK) +#define BCH_MODE_TOG_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_TOG_RSVD_SHIFT (8U) +#define BCH_MODE_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_RSVD_SHIFT)) & BCH_MODE_TOG_RSVD_MASK) + +/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK) + +/*! @name ENCODEPTR_SET - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_SET_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_SET_ADDR_SHIFT)) & BCH_ENCODEPTR_SET_ADDR_MASK) + +/*! @name ENCODEPTR_CLR - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_CLR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_CLR_ADDR_SHIFT)) & BCH_ENCODEPTR_CLR_ADDR_MASK) + +/*! @name ENCODEPTR_TOG - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_TOG_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_TOG_ADDR_SHIFT)) & BCH_ENCODEPTR_TOG_ADDR_MASK) + +/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK) + +/*! @name DATAPTR_SET - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_SET_ADDR_SHIFT (0U) +#define BCH_DATAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_SET_ADDR_SHIFT)) & BCH_DATAPTR_SET_ADDR_MASK) + +/*! @name DATAPTR_CLR - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_CLR_ADDR_SHIFT)) & BCH_DATAPTR_CLR_ADDR_MASK) + +/*! @name DATAPTR_TOG - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_DATAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_TOG_ADDR_SHIFT)) & BCH_DATAPTR_TOG_ADDR_MASK) + +/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_ADDR_SHIFT (0U) +#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK) + +/*! @name METAPTR_SET - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_SET_ADDR_SHIFT (0U) +#define BCH_METAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_SET_ADDR_SHIFT)) & BCH_METAPTR_SET_ADDR_MASK) + +/*! @name METAPTR_CLR - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_METAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_CLR_ADDR_SHIFT)) & BCH_METAPTR_CLR_ADDR_MASK) + +/*! @name METAPTR_TOG - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_METAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_TOG_ADDR_SHIFT)) & BCH_METAPTR_TOG_ADDR_MASK) + +/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_SET - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_CLR - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_TOG - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK) + +/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_SET - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_CLR - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_TOG - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_SET - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_CLR - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_TOG - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_SET - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_CLR - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_TOG - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_SET - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_CLR - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_TOG - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_SET - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_CLR - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_TOG - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_SET - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_CLR - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_TOG - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_SET - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_CLR - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_TOG - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_SET - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_CLR - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_TOG - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK) +#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK) + +/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_SET_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK) + +/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_CLR_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK) + +/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_TOG_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK) + +/*! @name DBGKESREAD - KES Debug Read Register */ +#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK) + +/*! @name DBGKESREAD_SET - KES Debug Read Register */ +#define BCH_DBGKESREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_SET_VALUES_SHIFT)) & BCH_DBGKESREAD_SET_VALUES_MASK) + +/*! @name DBGKESREAD_CLR - KES Debug Read Register */ +#define BCH_DBGKESREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_CLR_VALUES_SHIFT)) & BCH_DBGKESREAD_CLR_VALUES_MASK) + +/*! @name DBGKESREAD_TOG - KES Debug Read Register */ +#define BCH_DBGKESREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_TOG_VALUES_SHIFT)) & BCH_DBGKESREAD_TOG_VALUES_MASK) + +/*! @name DBGCSFEREAD - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK) + +/*! @name DBGCSFEREAD_SET - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_SET_VALUES_SHIFT)) & BCH_DBGCSFEREAD_SET_VALUES_MASK) + +/*! @name DBGCSFEREAD_CLR - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_CLR_VALUES_SHIFT)) & BCH_DBGCSFEREAD_CLR_VALUES_MASK) + +/*! @name DBGCSFEREAD_TOG - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_TOG_VALUES_SHIFT)) & BCH_DBGCSFEREAD_TOG_VALUES_MASK) + +/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_SET - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_SET_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_CLR - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_CLR_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_TOG - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_TOG_VALUES_MASK) + +/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK) + +/*! @name DBGAHBMREAD_SET - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_SET_VALUES_SHIFT)) & BCH_DBGAHBMREAD_SET_VALUES_MASK) + +/*! @name DBGAHBMREAD_CLR - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_CLR_VALUES_SHIFT)) & BCH_DBGAHBMREAD_CLR_VALUES_MASK) + +/*! @name DBGAHBMREAD_TOG - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_TOG_VALUES_SHIFT)) & BCH_DBGAHBMREAD_TOG_VALUES_MASK) + +/*! @name BLOCKNAME - Block Name Register */ +#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK) + +/*! @name BLOCKNAME_SET - Block Name Register */ +#define BCH_BLOCKNAME_SET_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_SET_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_SET_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_SET_NAME_SHIFT)) & BCH_BLOCKNAME_SET_NAME_MASK) + +/*! @name BLOCKNAME_CLR - Block Name Register */ +#define BCH_BLOCKNAME_CLR_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_CLR_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_CLR_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_CLR_NAME_SHIFT)) & BCH_BLOCKNAME_CLR_NAME_MASK) + +/*! @name BLOCKNAME_TOG - Block Name Register */ +#define BCH_BLOCKNAME_TOG_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_TOG_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_TOG_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_TOG_NAME_SHIFT)) & BCH_BLOCKNAME_TOG_NAME_MASK) + +/*! @name VERSION - BCH Version Register */ +#define BCH_VERSION_STEP_MASK (0xFFFFU) +#define BCH_VERSION_STEP_SHIFT (0U) +#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK) +#define BCH_VERSION_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_MINOR_SHIFT (16U) +#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK) +#define BCH_VERSION_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_MAJOR_SHIFT (24U) +#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK) + +/*! @name VERSION_SET - BCH Version Register */ +#define BCH_VERSION_SET_STEP_MASK (0xFFFFU) +#define BCH_VERSION_SET_STEP_SHIFT (0U) +#define BCH_VERSION_SET_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_STEP_SHIFT)) & BCH_VERSION_SET_STEP_MASK) +#define BCH_VERSION_SET_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_SET_MINOR_SHIFT (16U) +#define BCH_VERSION_SET_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MINOR_SHIFT)) & BCH_VERSION_SET_MINOR_MASK) +#define BCH_VERSION_SET_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_SET_MAJOR_SHIFT (24U) +#define BCH_VERSION_SET_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MAJOR_SHIFT)) & BCH_VERSION_SET_MAJOR_MASK) + +/*! @name VERSION_CLR - BCH Version Register */ +#define BCH_VERSION_CLR_STEP_MASK (0xFFFFU) +#define BCH_VERSION_CLR_STEP_SHIFT (0U) +#define BCH_VERSION_CLR_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_STEP_SHIFT)) & BCH_VERSION_CLR_STEP_MASK) +#define BCH_VERSION_CLR_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_CLR_MINOR_SHIFT (16U) +#define BCH_VERSION_CLR_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MINOR_SHIFT)) & BCH_VERSION_CLR_MINOR_MASK) +#define BCH_VERSION_CLR_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_CLR_MAJOR_SHIFT (24U) +#define BCH_VERSION_CLR_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MAJOR_SHIFT)) & BCH_VERSION_CLR_MAJOR_MASK) + +/*! @name VERSION_TOG - BCH Version Register */ +#define BCH_VERSION_TOG_STEP_MASK (0xFFFFU) +#define BCH_VERSION_TOG_STEP_SHIFT (0U) +#define BCH_VERSION_TOG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_STEP_SHIFT)) & BCH_VERSION_TOG_STEP_MASK) +#define BCH_VERSION_TOG_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_TOG_MINOR_SHIFT (16U) +#define BCH_VERSION_TOG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MINOR_SHIFT)) & BCH_VERSION_TOG_MINOR_MASK) +#define BCH_VERSION_TOG_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_TOG_MAJOR_SHIFT (24U) +#define BCH_VERSION_TOG_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MAJOR_SHIFT)) & BCH_VERSION_TOG_MAJOR_MASK) + +/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_RSVD_SHIFT (9U) +#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_SET - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_SET_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_SET_RSVD_SHIFT (9U) +#define BCH_DEBUG1_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_RSVD_SHIFT)) & BCH_DEBUG1_SET_RSVD_MASK) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_CLR - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_CLR_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_CLR_RSVD_SHIFT (9U) +#define BCH_DEBUG1_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_RSVD_SHIFT)) & BCH_DEBUG1_CLR_RSVD_MASK) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_TOG - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_TOG_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_TOG_RSVD_SHIFT (9U) +#define BCH_DEBUG1_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_RSVD_SHIFT)) & BCH_DEBUG1_TOG_RSVD_MASK) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK) + + +/*! + * @} + */ /* end of group BCH_Register_Masks */ + + +/* BCH - Peripheral instance base addresses */ +/** Peripheral BCH base address */ +#define BCH_BASE (0x1808000u) +/** Peripheral BCH base pointer */ +#define BCH ((BCH_Type *)BCH_BASE) +/** Array initializer of BCH peripheral base addresses */ +#define BCH_BASE_ADDRS { BCH_BASE } +/** Array initializer of BCH peripheral base pointers */ +#define BCH_BASE_PTRS { BCH } +/** Interrupt vectors for the BCH peripheral type */ +#define BCH_IRQS { RAWNAND_BCH_IRQn } + +/*! + * @} + */ /* end of group BCH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_2[48]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + uint8_t RESERVED_3[1024]; + __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_4[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) + +/*! @name CTRL1 - Control 1 Register */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) + +/*! @name TIMER - Free Running Timer Register */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) + +/*! @name RX14MASK - Rx Buffer 14 Mask Register */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) + +/*! @name RX15MASK - Rx Buffer 15 Mask Register */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) + +/*! @name ECR - Error Counter Register */ +#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) +#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) +#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) +#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) +#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) +#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) + +/*! @name ESR1 - Error and Status 1 Register */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +/*! @name IMASK2 - Interrupt Masks 2 Register */ +#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUFHM_SHIFT (0U) +#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) + +/*! @name IMASK1 - Interrupt Masks 1 Register */ +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) + +/*! @name IFLAG2 - Interrupt Flags 2 Register */ +#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUFHI_SHIFT (0U) +#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) + +/*! @name IFLAG1 - Interrupt Flags 1 Register */ +#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) +#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) + +/*! @name CTRL2 - Control 2 Register */ +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) + +/*! @name ESR2 - Error and Status 2 Register */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) + +/*! @name CRCR - CRC Register */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) + +/*! @name RXFGMASK - Rx FIFO Global Mask Register */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) + +/*! @name RXFIR - Rx FIFO Information Register */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (64U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (64U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (64U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (64U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (64U) + +/*! @name GFWR - Glitch Filter Width Registers */ +#define CAN_GFWR_GFWR_MASK (0xFFU) +#define CAN_GFWR_GFWR_SHIFT (0U) +#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x2090000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x2094000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +/* Backward compatibility */ +#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK +#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT +#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x) +#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK +#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT +#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x) + + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ + __IO uint32_t CCDR; /**< CCM Control Divider Register, offset: 0x4 */ + __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ + __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ + __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ + __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ + __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ + __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ + __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ + __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ + __IO uint32_t CS1CDR; /**< CCM SAI1 Clock Divider Register, offset: 0x28 */ + __IO uint32_t CS2CDR; /**< CCM SAI2 Clock Divider Register, offset: 0x2C */ + __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ + __IO uint32_t CHSCCDR; /**< CCM HSC Clock Divider Register, offset: 0x34 */ + __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ + __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ + uint8_t RESERVED_0[8]; + __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ + __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ + __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ + __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ + __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ + __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ + uint8_t RESERVED_2[4]; + __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CCR - CCM Control Register */ +#define CCM_CCR_OSCNT_MASK (0x7FU) +#define CCM_CCR_OSCNT_SHIFT (0U) +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) +#define CCM_CCR_COSC_EN_MASK (0x1000U) +#define CCM_CCR_COSC_EN_SHIFT (12U) +#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) +#define CCM_CCR_RBC_EN_MASK (0x8000000U) +#define CCM_CCR_RBC_EN_SHIFT (27U) +#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) + +/*! @name CCDR - CCM Control Divider Register */ +#define CCM_CCDR_MMDC_CH1_MASK_MASK (0x10000U) +#define CCM_CCDR_MMDC_CH1_MASK_SHIFT (16U) +#define CCM_CCDR_MMDC_CH1_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCDR_MMDC_CH1_MASK_SHIFT)) & CCM_CCDR_MMDC_CH1_MASK_MASK) +#define CCM_CCDR_MMDC_CH0_MASK_MASK (0x20000U) +#define CCM_CCDR_MMDC_CH0_MASK_SHIFT (17U) +#define CCM_CCDR_MMDC_CH0_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCDR_MMDC_CH0_MASK_SHIFT)) & CCM_CCDR_MMDC_CH0_MASK_MASK) + +/*! @name CSR - CCM Status Register */ +#define CCM_CSR_REF_EN_B_MASK (0x1U) +#define CCM_CSR_REF_EN_B_SHIFT (0U) +#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) +#define CCM_CSR_COSC_READY_MASK (0x20U) +#define CCM_CSR_COSC_READY_SHIFT (5U) +#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) + +/*! @name CCSR - CCM Clock Switcher Register */ +#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) +#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +#define CCM_CCSR_PLL1_SW_CLK_SEL_MASK (0x4U) +#define CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT (2U) +#define CCM_CCSR_PLL1_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL1_SW_CLK_SEL_MASK) +#define CCM_CCSR_SECONDARY_CLK_SEL_MASK (0x8U) +#define CCM_CCSR_SECONDARY_CLK_SEL_SHIFT (3U) +#define CCM_CCSR_SECONDARY_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_SECONDARY_CLK_SEL_SHIFT)) & CCM_CCSR_SECONDARY_CLK_SEL_MASK) +#define CCM_CCSR_STEP_SEL_MASK (0x100U) +#define CCM_CCSR_STEP_SEL_SHIFT (8U) +#define CCM_CCSR_STEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_STEP_SEL_SHIFT)) & CCM_CCSR_STEP_SEL_MASK) + +/*! @name CACRR - CCM Arm Clock Root Register */ +#define CCM_CACRR_ARM_PODF_MASK (0x7U) +#define CCM_CACRR_ARM_PODF_SHIFT (0U) +#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) + +/*! @name CBCDR - CCM Bus Clock Divider Register */ +#define CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7U) +#define CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT (0U) +#define CCM_CBCDR_PERIPH2_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) +#define CCM_CBCDR_FABRIC_MMDC_PODF_MASK (0x38U) +#define CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT (3U) +#define CCM_CBCDR_FABRIC_MMDC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT)) & CCM_CBCDR_FABRIC_MMDC_PODF_MASK) +#define CCM_CBCDR_AXI_SEL_MASK (0x40U) +#define CCM_CBCDR_AXI_SEL_SHIFT (6U) +#define CCM_CBCDR_AXI_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_SEL_SHIFT)) & CCM_CBCDR_AXI_SEL_MASK) +#define CCM_CBCDR_AXI_ALT_SEL_MASK (0x80U) +#define CCM_CBCDR_AXI_ALT_SEL_SHIFT (7U) +#define CCM_CBCDR_AXI_ALT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_ALT_SEL_SHIFT)) & CCM_CBCDR_AXI_ALT_SEL_MASK) +#define CCM_CBCDR_IPG_PODF_MASK (0x300U) +#define CCM_CBCDR_IPG_PODF_SHIFT (8U) +#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) +#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) +#define CCM_CBCDR_AHB_PODF_SHIFT (10U) +#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) +#define CCM_CBCDR_AXI_PODF_MASK (0x70000U) +#define CCM_CBCDR_AXI_PODF_SHIFT (16U) +#define CCM_CBCDR_AXI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_PODF_SHIFT)) & CCM_CBCDR_AXI_PODF_MASK) +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH2_CLK_SEL_MASK (0x4000000U) +#define CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT (26U) +#define CCM_CBCDR_PERIPH2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH2_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) + +/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) +#define CCM_CBCMR_PERIPH2_CLK2_SEL_MASK (0x100000U) +#define CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT (20U) +#define CCM_CBCMR_PERIPH2_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH2_CLK2_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x600000U) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT (21U) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) +#define CCM_CBCMR_LCDIF1_PODF_MASK (0x3800000U) +#define CCM_CBCMR_LCDIF1_PODF_SHIFT (23U) +#define CCM_CBCMR_LCDIF1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF1_PODF_SHIFT)) & CCM_CBCMR_LCDIF1_PODF_MASK) + +/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) +#define CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x380U) +#define CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT (7U) +#define CCM_CSCMR1_QSPI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_QSPI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) +#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) +#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) +#define CCM_CSCMR1_BCH_CLK_SEL_MASK (0x40000U) +#define CCM_CSCMR1_BCH_CLK_SEL_SHIFT (18U) +#define CCM_CSCMR1_BCH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_BCH_CLK_SEL_SHIFT)) & CCM_CSCMR1_BCH_CLK_SEL_MASK) +#define CCM_CSCMR1_GPMI_CLK_SEL_MASK (0x80000U) +#define CCM_CSCMR1_GPMI_CLK_SEL_SHIFT (19U) +#define CCM_CSCMR1_GPMI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_GPMI_CLK_SEL_SHIFT)) & CCM_CSCMR1_GPMI_CLK_SEL_MASK) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK (0x3800000U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT (23U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT)) & CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK) +#define CCM_CSCMR1_QSPI1_PODF_MASK (0x1C000000U) +#define CCM_CSCMR1_QSPI1_PODF_SHIFT (26U) +#define CCM_CSCMR1_QSPI1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_QSPI1_PODF_SHIFT)) & CCM_CSCMR1_QSPI1_PODF_MASK) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK (0x60000000U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT (29U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT)) & CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK) + +/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) +#define CCM_CSCMR2_LDB_DI0_DIV_MASK (0x400U) +#define CCM_CSCMR2_LDB_DI0_DIV_SHIFT (10U) +#define CCM_CSCMR2_LDB_DI0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_LDB_DI0_DIV_SHIFT)) & CCM_CSCMR2_LDB_DI0_DIV_MASK) +#define CCM_CSCMR2_LDB_DI1_DIV_MASK (0x800U) +#define CCM_CSCMR2_LDB_DI1_DIV_SHIFT (11U) +#define CCM_CSCMR2_LDB_DI1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_LDB_DI1_DIV_SHIFT)) & CCM_CSCMR2_LDB_DI1_DIV_MASK) +#define CCM_CSCMR2_ESAI_CLK_SEL_MASK (0x180000U) +#define CCM_CSCMR2_ESAI_CLK_SEL_SHIFT (19U) +#define CCM_CSCMR2_ESAI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_ESAI_CLK_SEL_SHIFT)) & CCM_CSCMR2_ESAI_CLK_SEL_MASK) +#define CCM_CSCMR2_VID_CLK_SEL_MASK (0xE00000U) +#define CCM_CSCMR2_VID_CLK_SEL_SHIFT (21U) +#define CCM_CSCMR2_VID_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_SEL_SHIFT)) & CCM_CSCMR2_VID_CLK_SEL_MASK) +#define CCM_CSCMR2_VID_CLK_PRE_PODF_MASK (0x3000000U) +#define CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT (24U) +#define CCM_CSCMR2_VID_CLK_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT)) & CCM_CSCMR2_VID_CLK_PRE_PODF_MASK) +#define CCM_CSCMR2_VID_CLK_PODF_MASK (0x1C000000U) +#define CCM_CSCMR2_VID_CLK_PODF_SHIFT (26U) +#define CCM_CSCMR2_VID_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_PODF_SHIFT)) & CCM_CSCMR2_VID_CLK_PODF_MASK) + +/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) +#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) +#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) +#define CCM_CSCDR1_BCH_PODF_MASK (0x380000U) +#define CCM_CSCDR1_BCH_PODF_SHIFT (19U) +#define CCM_CSCDR1_BCH_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_BCH_PODF_SHIFT)) & CCM_CSCDR1_BCH_PODF_MASK) +#define CCM_CSCDR1_GPMI_PODF_MASK (0x1C00000U) +#define CCM_CSCDR1_GPMI_PODF_SHIFT (22U) +#define CCM_CSCDR1_GPMI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_GPMI_PODF_SHIFT)) & CCM_CSCDR1_GPMI_PODF_MASK) + +/*! @name CS1CDR - CCM SAI1 Clock Divider Register */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) +#define CCM_CS1CDR_ESAI_CLK_PRED_MASK (0xE00U) +#define CCM_CS1CDR_ESAI_CLK_PRED_SHIFT (9U) +#define CCM_CS1CDR_ESAI_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_ESAI_CLK_PRED_SHIFT)) & CCM_CS1CDR_ESAI_CLK_PRED_MASK) +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) +#define CCM_CS1CDR_ESAI_CLK_PODF_MASK (0xE000000U) +#define CCM_CS1CDR_ESAI_CLK_PODF_SHIFT (25U) +#define CCM_CS1CDR_ESAI_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_ESAI_CLK_PODF_SHIFT)) & CCM_CS1CDR_ESAI_CLK_PODF_MASK) + +/*! @name CS2CDR - CCM SAI2 Clock Divider Register */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0xE00U) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT (9U) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT)) & CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK) +#define CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x38000U) +#define CCM_CS2CDR_ENFC_CLK_SEL_SHIFT (15U) +#define CCM_CS2CDR_ENFC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT)) & CCM_CS2CDR_ENFC_CLK_SEL_MASK) +#define CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x1C0000U) +#define CCM_CS2CDR_ENFC_CLK_PRED_SHIFT (18U) +#define CCM_CS2CDR_ENFC_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_PRED_SHIFT)) & CCM_CS2CDR_ENFC_CLK_PRED_MASK) +#define CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x7E00000U) +#define CCM_CS2CDR_ENFC_CLK_PODF_SHIFT (21U) +#define CCM_CS2CDR_ENFC_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_PODF_SHIFT)) & CCM_CS2CDR_ENFC_CLK_PODF_MASK) + +/*! @name CDCDR - CCM D1 Clock Divider Register */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) + +/*! @name CHSCCDR - CCM HSC Clock Divider Register */ +#define CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0xE00U) +#define CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT (9U) +#define CCM_CHSCCDR_EPDC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT)) & CCM_CHSCCDR_EPDC_CLK_SEL_MASK) +#define CCM_CHSCCDR_EPDC_PODF_MASK (0x7000U) +#define CCM_CHSCCDR_EPDC_PODF_SHIFT (12U) +#define CCM_CHSCCDR_EPDC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_PODF_SHIFT)) & CCM_CHSCCDR_EPDC_PODF_MASK) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT (15U) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT)) & CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK) + +/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ +#define CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0xE00U) +#define CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT (9U) +#define CCM_CSCDR2_LCDIF1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) +#define CCM_CSCDR2_LCDIF1_PRED_MASK (0x7000U) +#define CCM_CSCDR2_LCDIF1_PRED_SHIFT (12U) +#define CCM_CSCDR2_LCDIF1_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_PRED_SHIFT)) & CCM_CSCDR2_LCDIF1_PRED_MASK) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT (15U) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK) +#define CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x40000U) +#define CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT (18U) +#define CCM_CSCDR2_ECSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT)) & CCM_CSCDR2_ECSPI_CLK_SEL_MASK) +#define CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x1F80000U) +#define CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT (19U) +#define CCM_CSCDR2_ECSPI_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT)) & CCM_CSCDR2_ECSPI_CLK_PODF_MASK) + +/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) +#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) + +/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +#define CCM_CDHIPR_AXI_PODF_BUSY_MASK (0x1U) +#define CCM_CDHIPR_AXI_PODF_BUSY_SHIFT (0U) +#define CCM_CDHIPR_AXI_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AXI_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AXI_PODF_BUSY_MASK) +#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) +#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) +#define CCM_CDHIPR_MMDC_PODF_BUSY_MASK (0x4U) +#define CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT (2U) +#define CCM_CDHIPR_MMDC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_MMDC_PODF_BUSY_MASK) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) +#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) + +/*! @name CLPCR - CCM Low Power Control Register */ +#define CCM_CLPCR_LPM_MASK (0x3U) +#define CCM_CLPCR_LPM_SHIFT (0U) +#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) +#define CCM_CLPCR_SBYOS_MASK (0x40U) +#define CCM_CLPCR_SBYOS_SHIFT (6U) +#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) +#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) +#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) +#define CCM_CLPCR_VSTBY_MASK (0x100U) +#define CCM_CLPCR_VSTBY_SHIFT (8U) +#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) +#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) +#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) +#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) +#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_MASK (0x80000U) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_SHIFT (19U) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_SHIFT)) & CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_MASK) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_MASK (0x200000U) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_SHIFT (21U) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_SHIFT)) & CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_MASK) +#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) +#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) +#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) +#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) +#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) +#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) + +/*! @name CISR - CCM Interrupt Status Register */ +#define CCM_CISR_LRF_PLL_MASK (0x1U) +#define CCM_CISR_LRF_PLL_SHIFT (0U) +#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) +#define CCM_CISR_COSC_READY_MASK (0x40U) +#define CCM_CISR_COSC_READY_SHIFT (6U) +#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) +#define CCM_CISR_AXI_PODF_LOADED_MASK (0x20000U) +#define CCM_CISR_AXI_PODF_LOADED_SHIFT (17U) +#define CCM_CISR_AXI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AXI_PODF_LOADED_SHIFT)) & CCM_CISR_AXI_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) +#define CCM_CISR_MMDC_PODF_LOADED_MASK (0x200000U) +#define CCM_CISR_MMDC_PODF_LOADED_SHIFT (21U) +#define CCM_CISR_MMDC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_MMDC_PODF_LOADED_SHIFT)) & CCM_CISR_MMDC_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) + +/*! @name CIMR - CCM Interrupt Mask Register */ +#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) +#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) +#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) +#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) +#define CCM_CIMR_MASK_AXI_PODF_LOADED_MASK (0x20000U) +#define CCM_CIMR_MASK_AXI_PODF_LOADED_SHIFT (17U) +#define CCM_CIMR_MASK_AXI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AXI_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AXI_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED_MASK (0x200000U) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED_SHIFT (21U) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_MMDC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_MMDC_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) + +/*! @name CCOSR - CCM Clock Output Source Register */ +#define CCM_CCOSR_CLKO_SEL_MASK (0xFU) +#define CCM_CCOSR_CLKO_SEL_SHIFT (0U) +#define CCM_CCOSR_CLKO_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO_SEL_SHIFT)) & CCM_CCOSR_CLKO_SEL_MASK) +#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) +#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) +#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) +#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) +#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) +#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) +#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) +#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) + +/*! @name CGPR - CCM General Purpose Register */ +#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) +#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) +#define CCM_CGPR_MMDC_EXT_CLK_DIS_MASK (0x4U) +#define CCM_CGPR_MMDC_EXT_CLK_DIS_SHIFT (2U) +#define CCM_CGPR_MMDC_EXT_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_MMDC_EXT_CLK_DIS_SHIFT)) & CCM_CGPR_MMDC_EXT_CLK_DIS_MASK) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) +#define CCM_CGPR_FPL_MASK (0x10000U) +#define CCM_CGPR_FPL_SHIFT (16U) +#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) +#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) +#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) + +/*! @name CCGR0 - CCM Clock Gating Register 0 */ +#define CCM_CCGR0_CG0_MASK (0x3U) +#define CCM_CCGR0_CG0_SHIFT (0U) +#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) +#define CCM_CCGR0_CG1_MASK (0xCU) +#define CCM_CCGR0_CG1_SHIFT (2U) +#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) +#define CCM_CCGR0_CG2_MASK (0x30U) +#define CCM_CCGR0_CG2_SHIFT (4U) +#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) +#define CCM_CCGR0_CG3_MASK (0xC0U) +#define CCM_CCGR0_CG3_SHIFT (6U) +#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) +#define CCM_CCGR0_CG4_MASK (0x300U) +#define CCM_CCGR0_CG4_SHIFT (8U) +#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) +#define CCM_CCGR0_CG5_MASK (0xC00U) +#define CCM_CCGR0_CG5_SHIFT (10U) +#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) +#define CCM_CCGR0_CG6_MASK (0x3000U) +#define CCM_CCGR0_CG6_SHIFT (12U) +#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) +#define CCM_CCGR0_CG7_MASK (0xC000U) +#define CCM_CCGR0_CG7_SHIFT (14U) +#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) +#define CCM_CCGR0_CG8_MASK (0x30000U) +#define CCM_CCGR0_CG8_SHIFT (16U) +#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) +#define CCM_CCGR0_CG9_MASK (0xC0000U) +#define CCM_CCGR0_CG9_SHIFT (18U) +#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) +#define CCM_CCGR0_CG10_MASK (0x300000U) +#define CCM_CCGR0_CG10_SHIFT (20U) +#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) +#define CCM_CCGR0_CG11_MASK (0xC00000U) +#define CCM_CCGR0_CG11_SHIFT (22U) +#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) +#define CCM_CCGR0_CG12_MASK (0x3000000U) +#define CCM_CCGR0_CG12_SHIFT (24U) +#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) +#define CCM_CCGR0_CG13_MASK (0xC000000U) +#define CCM_CCGR0_CG13_SHIFT (26U) +#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) +#define CCM_CCGR0_CG14_MASK (0x30000000U) +#define CCM_CCGR0_CG14_SHIFT (28U) +#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) +#define CCM_CCGR0_CG15_MASK (0xC0000000U) +#define CCM_CCGR0_CG15_SHIFT (30U) +#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) + +/*! @name CCGR1 - CCM Clock Gating Register 1 */ +#define CCM_CCGR1_CG0_MASK (0x3U) +#define CCM_CCGR1_CG0_SHIFT (0U) +#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) +#define CCM_CCGR1_CG1_MASK (0xCU) +#define CCM_CCGR1_CG1_SHIFT (2U) +#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) +#define CCM_CCGR1_CG2_MASK (0x30U) +#define CCM_CCGR1_CG2_SHIFT (4U) +#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) +#define CCM_CCGR1_CG3_MASK (0xC0U) +#define CCM_CCGR1_CG3_SHIFT (6U) +#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) +#define CCM_CCGR1_CG4_MASK (0x300U) +#define CCM_CCGR1_CG4_SHIFT (8U) +#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) +#define CCM_CCGR1_CG5_MASK (0xC00U) +#define CCM_CCGR1_CG5_SHIFT (10U) +#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) +#define CCM_CCGR1_CG6_MASK (0x3000U) +#define CCM_CCGR1_CG6_SHIFT (12U) +#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) +#define CCM_CCGR1_CG7_MASK (0xC000U) +#define CCM_CCGR1_CG7_SHIFT (14U) +#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) +#define CCM_CCGR1_CG8_MASK (0x30000U) +#define CCM_CCGR1_CG8_SHIFT (16U) +#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) +#define CCM_CCGR1_CG9_MASK (0xC0000U) +#define CCM_CCGR1_CG9_SHIFT (18U) +#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) +#define CCM_CCGR1_CG10_MASK (0x300000U) +#define CCM_CCGR1_CG10_SHIFT (20U) +#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) +#define CCM_CCGR1_CG11_MASK (0xC00000U) +#define CCM_CCGR1_CG11_SHIFT (22U) +#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) +#define CCM_CCGR1_CG12_MASK (0x3000000U) +#define CCM_CCGR1_CG12_SHIFT (24U) +#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) +#define CCM_CCGR1_CG13_MASK (0xC000000U) +#define CCM_CCGR1_CG13_SHIFT (26U) +#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) +#define CCM_CCGR1_CG14_MASK (0x30000000U) +#define CCM_CCGR1_CG14_SHIFT (28U) +#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) +#define CCM_CCGR1_CG15_MASK (0xC0000000U) +#define CCM_CCGR1_CG15_SHIFT (30U) +#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) + +/*! @name CCGR2 - CCM Clock Gating Register 2 */ +#define CCM_CCGR2_CG0_MASK (0x3U) +#define CCM_CCGR2_CG0_SHIFT (0U) +#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) +#define CCM_CCGR2_CG1_MASK (0xCU) +#define CCM_CCGR2_CG1_SHIFT (2U) +#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) +#define CCM_CCGR2_CG2_MASK (0x30U) +#define CCM_CCGR2_CG2_SHIFT (4U) +#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) +#define CCM_CCGR2_CG3_MASK (0xC0U) +#define CCM_CCGR2_CG3_SHIFT (6U) +#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) +#define CCM_CCGR2_CG4_MASK (0x300U) +#define CCM_CCGR2_CG4_SHIFT (8U) +#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) +#define CCM_CCGR2_CG5_MASK (0xC00U) +#define CCM_CCGR2_CG5_SHIFT (10U) +#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) +#define CCM_CCGR2_CG6_MASK (0x3000U) +#define CCM_CCGR2_CG6_SHIFT (12U) +#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) +#define CCM_CCGR2_CG7_MASK (0xC000U) +#define CCM_CCGR2_CG7_SHIFT (14U) +#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) +#define CCM_CCGR2_CG8_MASK (0x30000U) +#define CCM_CCGR2_CG8_SHIFT (16U) +#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) +#define CCM_CCGR2_CG9_MASK (0xC0000U) +#define CCM_CCGR2_CG9_SHIFT (18U) +#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) +#define CCM_CCGR2_CG10_MASK (0x300000U) +#define CCM_CCGR2_CG10_SHIFT (20U) +#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) +#define CCM_CCGR2_CG11_MASK (0xC00000U) +#define CCM_CCGR2_CG11_SHIFT (22U) +#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) +#define CCM_CCGR2_CG12_MASK (0x3000000U) +#define CCM_CCGR2_CG12_SHIFT (24U) +#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) +#define CCM_CCGR2_CG13_MASK (0xC000000U) +#define CCM_CCGR2_CG13_SHIFT (26U) +#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) +#define CCM_CCGR2_CG14_MASK (0x30000000U) +#define CCM_CCGR2_CG14_SHIFT (28U) +#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) +#define CCM_CCGR2_CG15_MASK (0xC0000000U) +#define CCM_CCGR2_CG15_SHIFT (30U) +#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) + +/*! @name CCGR3 - CCM Clock Gating Register 3 */ +#define CCM_CCGR3_CG0_MASK (0x3U) +#define CCM_CCGR3_CG0_SHIFT (0U) +#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) +#define CCM_CCGR3_CG1_MASK (0xCU) +#define CCM_CCGR3_CG1_SHIFT (2U) +#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) +#define CCM_CCGR3_CG2_MASK (0x30U) +#define CCM_CCGR3_CG2_SHIFT (4U) +#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) +#define CCM_CCGR3_CG3_MASK (0xC0U) +#define CCM_CCGR3_CG3_SHIFT (6U) +#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) +#define CCM_CCGR3_CG4_MASK (0x300U) +#define CCM_CCGR3_CG4_SHIFT (8U) +#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) +#define CCM_CCGR3_CG5_MASK (0xC00U) +#define CCM_CCGR3_CG5_SHIFT (10U) +#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) +#define CCM_CCGR3_CG6_MASK (0x3000U) +#define CCM_CCGR3_CG6_SHIFT (12U) +#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) +#define CCM_CCGR3_CG7_MASK (0xC000U) +#define CCM_CCGR3_CG7_SHIFT (14U) +#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) +#define CCM_CCGR3_CG8_MASK (0x30000U) +#define CCM_CCGR3_CG8_SHIFT (16U) +#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) +#define CCM_CCGR3_CG9_MASK (0xC0000U) +#define CCM_CCGR3_CG9_SHIFT (18U) +#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) +#define CCM_CCGR3_CG10_MASK (0x300000U) +#define CCM_CCGR3_CG10_SHIFT (20U) +#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) +#define CCM_CCGR3_CG11_MASK (0xC00000U) +#define CCM_CCGR3_CG11_SHIFT (22U) +#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) +#define CCM_CCGR3_CG12_MASK (0x3000000U) +#define CCM_CCGR3_CG12_SHIFT (24U) +#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) +#define CCM_CCGR3_CG13_MASK (0xC000000U) +#define CCM_CCGR3_CG13_SHIFT (26U) +#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) +#define CCM_CCGR3_CG14_MASK (0x30000000U) +#define CCM_CCGR3_CG14_SHIFT (28U) +#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) +#define CCM_CCGR3_CG15_MASK (0xC0000000U) +#define CCM_CCGR3_CG15_SHIFT (30U) +#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) + +/*! @name CCGR4 - CCM Clock Gating Register 4 */ +#define CCM_CCGR4_CG0_MASK (0x3U) +#define CCM_CCGR4_CG0_SHIFT (0U) +#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) +#define CCM_CCGR4_CG1_MASK (0xCU) +#define CCM_CCGR4_CG1_SHIFT (2U) +#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) +#define CCM_CCGR4_CG2_MASK (0x30U) +#define CCM_CCGR4_CG2_SHIFT (4U) +#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) +#define CCM_CCGR4_CG3_MASK (0xC0U) +#define CCM_CCGR4_CG3_SHIFT (6U) +#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) +#define CCM_CCGR4_CG4_MASK (0x300U) +#define CCM_CCGR4_CG4_SHIFT (8U) +#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) +#define CCM_CCGR4_CG5_MASK (0xC00U) +#define CCM_CCGR4_CG5_SHIFT (10U) +#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) +#define CCM_CCGR4_CG6_MASK (0x3000U) +#define CCM_CCGR4_CG6_SHIFT (12U) +#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) +#define CCM_CCGR4_CG7_MASK (0xC000U) +#define CCM_CCGR4_CG7_SHIFT (14U) +#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) +#define CCM_CCGR4_CG8_MASK (0x30000U) +#define CCM_CCGR4_CG8_SHIFT (16U) +#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) +#define CCM_CCGR4_CG9_MASK (0xC0000U) +#define CCM_CCGR4_CG9_SHIFT (18U) +#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) +#define CCM_CCGR4_CG10_MASK (0x300000U) +#define CCM_CCGR4_CG10_SHIFT (20U) +#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) +#define CCM_CCGR4_CG11_MASK (0xC00000U) +#define CCM_CCGR4_CG11_SHIFT (22U) +#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) +#define CCM_CCGR4_CG12_MASK (0x3000000U) +#define CCM_CCGR4_CG12_SHIFT (24U) +#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) +#define CCM_CCGR4_CG13_MASK (0xC000000U) +#define CCM_CCGR4_CG13_SHIFT (26U) +#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) +#define CCM_CCGR4_CG14_MASK (0x30000000U) +#define CCM_CCGR4_CG14_SHIFT (28U) +#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) +#define CCM_CCGR4_CG15_MASK (0xC0000000U) +#define CCM_CCGR4_CG15_SHIFT (30U) +#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) + +/*! @name CCGR5 - CCM Clock Gating Register 5 */ +#define CCM_CCGR5_CG0_MASK (0x3U) +#define CCM_CCGR5_CG0_SHIFT (0U) +#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) +#define CCM_CCGR5_CG1_MASK (0xCU) +#define CCM_CCGR5_CG1_SHIFT (2U) +#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) +#define CCM_CCGR5_CG2_MASK (0x30U) +#define CCM_CCGR5_CG2_SHIFT (4U) +#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) +#define CCM_CCGR5_CG3_MASK (0xC0U) +#define CCM_CCGR5_CG3_SHIFT (6U) +#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) +#define CCM_CCGR5_CG4_MASK (0x300U) +#define CCM_CCGR5_CG4_SHIFT (8U) +#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) +#define CCM_CCGR5_CG5_MASK (0xC00U) +#define CCM_CCGR5_CG5_SHIFT (10U) +#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) +#define CCM_CCGR5_CG6_MASK (0x3000U) +#define CCM_CCGR5_CG6_SHIFT (12U) +#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) +#define CCM_CCGR5_CG7_MASK (0xC000U) +#define CCM_CCGR5_CG7_SHIFT (14U) +#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) +#define CCM_CCGR5_CG8_MASK (0x30000U) +#define CCM_CCGR5_CG8_SHIFT (16U) +#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) +#define CCM_CCGR5_CG9_MASK (0xC0000U) +#define CCM_CCGR5_CG9_SHIFT (18U) +#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) +#define CCM_CCGR5_CG10_MASK (0x300000U) +#define CCM_CCGR5_CG10_SHIFT (20U) +#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) +#define CCM_CCGR5_CG11_MASK (0xC00000U) +#define CCM_CCGR5_CG11_SHIFT (22U) +#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) +#define CCM_CCGR5_CG12_MASK (0x3000000U) +#define CCM_CCGR5_CG12_SHIFT (24U) +#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) +#define CCM_CCGR5_CG13_MASK (0xC000000U) +#define CCM_CCGR5_CG13_SHIFT (26U) +#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) +#define CCM_CCGR5_CG14_MASK (0x30000000U) +#define CCM_CCGR5_CG14_SHIFT (28U) +#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) +#define CCM_CCGR5_CG15_MASK (0xC0000000U) +#define CCM_CCGR5_CG15_SHIFT (30U) +#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) + +/*! @name CCGR6 - CCM Clock Gating Register 6 */ +#define CCM_CCGR6_CG0_MASK (0x3U) +#define CCM_CCGR6_CG0_SHIFT (0U) +#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) +#define CCM_CCGR6_CG1_MASK (0xCU) +#define CCM_CCGR6_CG1_SHIFT (2U) +#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) +#define CCM_CCGR6_CG2_MASK (0x30U) +#define CCM_CCGR6_CG2_SHIFT (4U) +#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) +#define CCM_CCGR6_CG3_MASK (0xC0U) +#define CCM_CCGR6_CG3_SHIFT (6U) +#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) +#define CCM_CCGR6_CG4_MASK (0x300U) +#define CCM_CCGR6_CG4_SHIFT (8U) +#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) +#define CCM_CCGR6_CG5_MASK (0xC00U) +#define CCM_CCGR6_CG5_SHIFT (10U) +#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) +#define CCM_CCGR6_CG6_MASK (0x3000U) +#define CCM_CCGR6_CG6_SHIFT (12U) +#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) +#define CCM_CCGR6_CG7_MASK (0xC000U) +#define CCM_CCGR6_CG7_SHIFT (14U) +#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) +#define CCM_CCGR6_CG8_MASK (0x30000U) +#define CCM_CCGR6_CG8_SHIFT (16U) +#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) +#define CCM_CCGR6_CG9_MASK (0xC0000U) +#define CCM_CCGR6_CG9_SHIFT (18U) +#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) +#define CCM_CCGR6_CG10_MASK (0x300000U) +#define CCM_CCGR6_CG10_SHIFT (20U) +#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) +#define CCM_CCGR6_CG11_MASK (0xC00000U) +#define CCM_CCGR6_CG11_SHIFT (22U) +#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) +#define CCM_CCGR6_CG12_MASK (0x3000000U) +#define CCM_CCGR6_CG12_SHIFT (24U) +#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) +#define CCM_CCGR6_CG13_MASK (0xC000000U) +#define CCM_CCGR6_CG13_SHIFT (26U) +#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) +#define CCM_CCGR6_CG14_MASK (0x30000000U) +#define CCM_CCGR6_CG14_SHIFT (28U) +#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) +#define CCM_CCGR6_CG15_MASK (0xC0000000U) +#define CCM_CCGR6_CG15_SHIFT (30U) +#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) + +/*! @name CMEOR - CCM Module Enable Overide Register */ +#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) +#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) +#define CCM_CMEOR_MOD_EN_OV_EPIT_MASK (0x40U) +#define CCM_CMEOR_MOD_EN_OV_EPIT_SHIFT (6U) +#define CCM_CMEOR_MOD_EN_OV_EPIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_EPIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_EPIT_MASK) +#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) +#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (g_ccm_vbase) //(0x20C4000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ + __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ + __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ + __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ + __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ + __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ + __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ + __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ + __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ + __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ + __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ + __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ + __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ + __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ + __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ + __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ + __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ + __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ + __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ + __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ + __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ + __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ + __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ + __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ + __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ + __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ + __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ + __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ + __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ + uint8_t RESERVED_7[64]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name PLL_ARM - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) + +/*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) + +/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) + +/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) + +/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) + +/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) + +/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) + +/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) + +/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) + +/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) + +/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) + +/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) + +/*! @name PLL_SYS - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) + +/*! @name PLL_SYS_SET - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) + +/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) + +/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) + +/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) + +/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) + +/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) + +/*! @name PLL_AUDIO - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) + +/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) + +/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) + +/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) + +/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) + +/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) + +/*! @name PLL_VIDEO - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) + +/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) + +/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) + +/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) + +/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) + +/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) + +/*! @name PLL_ENET - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) + +/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) + +/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) + +/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) + +/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) + +/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) + +/*! @name MISC0 - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK) + +/*! @name MISC1 - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) + +/*! @name MISC2 - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + +/*! @name MISC2_SET - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) + +/*! @name MISC2_CLR - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) + +/*! @name MISC2_TOG - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (g_ccm_analog_vbase) //(0x20C8000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer + * @{ + */ + +/** CSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ + __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ + __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ + __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ + __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ + __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ + __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ + __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ + __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ + __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ + __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ + __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ + uint8_t RESERVED_1[16]; + __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ + __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ +} CSI_Type; + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/*! @name CSICR1 - CSI Control Register 1 */ +#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) +#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) +#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) +#define CSI_CSICR1_REDGE_MASK (0x2U) +#define CSI_CSICR1_REDGE_SHIFT (1U) +#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) +#define CSI_CSICR1_INV_PCLK_MASK (0x4U) +#define CSI_CSICR1_INV_PCLK_SHIFT (2U) +#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) +#define CSI_CSICR1_INV_DATA_MASK (0x8U) +#define CSI_CSICR1_INV_DATA_SHIFT (3U) +#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) +#define CSI_CSICR1_GCLK_MODE_MASK (0x10U) +#define CSI_CSICR1_GCLK_MODE_SHIFT (4U) +#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) +#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) +#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) +#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK) +#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U) +#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U) +#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) +#define CSI_CSICR1_PACK_DIR_MASK (0x80U) +#define CSI_CSICR1_PACK_DIR_SHIFT (7U) +#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) +#define CSI_CSICR1_FCC_MASK (0x100U) +#define CSI_CSICR1_FCC_SHIFT (8U) +#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) +#define CSI_CSICR1_CCIR_EN_MASK (0x400U) +#define CSI_CSICR1_CCIR_EN_SHIFT (10U) +#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) +#define CSI_CSICR1_HSYNC_POL_MASK (0x800U) +#define CSI_CSICR1_HSYNC_POL_SHIFT (11U) +#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) +#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) +#define CSI_CSICR1_SOF_INTEN_SHIFT (16U) +#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) +#define CSI_CSICR1_SOF_POL_MASK (0x20000U) +#define CSI_CSICR1_SOF_POL_SHIFT (17U) +#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) +#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) +#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) +#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) +#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) +#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) +#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) +#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) +#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) +#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) +#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) +#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) +#define CSI_CSICR1_COF_INT_EN_SHIFT (26U) +#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) +#define CSI_CSICR1_VIDEO_MODE_MASK (0x8000000U) +#define CSI_CSICR1_VIDEO_MODE_SHIFT (27U) +#define CSI_CSICR1_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_VIDEO_MODE_SHIFT)) & CSI_CSICR1_VIDEO_MODE_MASK) +#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) +#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) +#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) +#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) +#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) +#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) +#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) +#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) +#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) +#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) +#define CSI_CSICR1_SWAP16_EN_SHIFT (31U) +#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) + +/*! @name CSICR2 - CSI Control Register 2 */ +#define CSI_CSICR2_HSC_MASK (0xFFU) +#define CSI_CSICR2_HSC_SHIFT (0U) +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) +#define CSI_CSICR2_VSC_MASK (0xFF00U) +#define CSI_CSICR2_VSC_SHIFT (8U) +#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) +#define CSI_CSICR2_LVRM_MASK (0x70000U) +#define CSI_CSICR2_LVRM_SHIFT (16U) +#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) +#define CSI_CSICR2_BTS_MASK (0x180000U) +#define CSI_CSICR2_BTS_SHIFT (19U) +#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) +#define CSI_CSICR2_SCE_MASK (0x800000U) +#define CSI_CSICR2_SCE_SHIFT (23U) +#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) +#define CSI_CSICR2_AFS_MASK (0x3000000U) +#define CSI_CSICR2_AFS_SHIFT (24U) +#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) +#define CSI_CSICR2_DRM_MASK (0x4000000U) +#define CSI_CSICR2_DRM_SHIFT (26U) +#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) + +/*! @name CSICR3 - CSI Control Register 3 */ +#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) +#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) +#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) +#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) +#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) +#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) +#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) +#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) +#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) +#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) +#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) +#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) +#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) +#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) +#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) +#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) +#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) +#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) +#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) +#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) +#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) +#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) +#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) +#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) +#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) +#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) +#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) +#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) +#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) +#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) +#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) +#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) +#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) +#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) +#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) +#define CSI_CSICR3_FRMCNT_SHIFT (16U) +#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) + +/*! @name CSISTATFIFO - CSI Statistic FIFO Register */ +#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) +#define CSI_CSISTATFIFO_STAT_SHIFT (0U) +#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) + +/*! @name CSIRFIFO - CSI RX FIFO Register */ +#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) +#define CSI_CSIRFIFO_IMAGE_SHIFT (0U) +#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) + +/*! @name CSIRXCNT - CSI RX Count Register */ +#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) +#define CSI_CSIRXCNT_RXCNT_SHIFT (0U) +#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) + +/*! @name CSISR - CSI Status Register */ +#define CSI_CSISR_DRDY_MASK (0x1U) +#define CSI_CSISR_DRDY_SHIFT (0U) +#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) +#define CSI_CSISR_ECC_INT_MASK (0x2U) +#define CSI_CSISR_ECC_INT_SHIFT (1U) +#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) +#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) +#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) +#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) +#define CSI_CSISR_COF_INT_MASK (0x2000U) +#define CSI_CSISR_COF_INT_SHIFT (13U) +#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) +#define CSI_CSISR_F1_INT_MASK (0x4000U) +#define CSI_CSISR_F1_INT_SHIFT (14U) +#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) +#define CSI_CSISR_F2_INT_MASK (0x8000U) +#define CSI_CSISR_F2_INT_SHIFT (15U) +#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) +#define CSI_CSISR_SOF_INT_MASK (0x10000U) +#define CSI_CSISR_SOF_INT_SHIFT (16U) +#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) +#define CSI_CSISR_EOF_INT_MASK (0x20000U) +#define CSI_CSISR_EOF_INT_SHIFT (17U) +#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) +#define CSI_CSISR_RxFF_INT_MASK (0x40000U) +#define CSI_CSISR_RxFF_INT_SHIFT (18U) +#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) +#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) +#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) +#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) +#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) +#define CSI_CSISR_STATFF_INT_MASK (0x200000U) +#define CSI_CSISR_STATFF_INT_SHIFT (21U) +#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) +#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) +#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) +#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) +#define CSI_CSISR_RF_OR_INT_SHIFT (24U) +#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) +#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) +#define CSI_CSISR_SF_OR_INT_SHIFT (25U) +#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) +#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) +#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) +#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK) +#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U) +#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U) +#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) + +/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) + +/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) + +/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) + +/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) + +/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) + +/*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) + +/*! @name CSICR18 - CSI Control Register 18 */ +#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) +#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) +#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) +#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) +#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) +#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) +#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) +#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) +#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) +#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) +#define CSI_CSICR18_AHB_HPROT_SHIFT (12U) +#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK (0x30000U) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK) +#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) +#define CSI_CSICR18_MASK_OPTION_SHIFT (18U) +#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) +#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) +#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) +#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) + +/*! @name CSICR19 - CSI Control Register 19 */ +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) + + +/*! + * @} + */ /* end of group CSI_Register_Masks */ + + +/* CSI - Peripheral instance base addresses */ +/** Peripheral CSI base address */ +#define CSI_BASE (0x21C4000u) +/** Peripheral CSI base pointer */ +#define CSI ((CSI_Type *)CSI_BASE) +/** Array initializer of CSI peripheral base addresses */ +#define CSI_BASE_ADDRS { CSI_BASE } +/** Array initializer of CSI peripheral base pointers */ +#define CSI_BASE_PTRS { CSI } +/** Interrupt vectors for the CSI peripheral type */ +#define CSI_IRQS { CSI_IRQn } + +/*! + * @} + */ /* end of group CSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer + * @{ + */ + +/** DCP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ + uint8_t RESERVED_14[28]; + __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ + uint8_t RESERVED_19[12]; + __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ + uint8_t RESERVED_30[524]; + __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ + uint8_t RESERVED_31[12]; + __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ + uint8_t RESERVED_32[12]; + __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ + uint8_t RESERVED_33[12]; + __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ +} DCP_Type; + +/* ---------------------------------------------------------------------------- + -- DCP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Register_Masks DCP Register Masks + * @{ + */ + +/*! @name CTRL - DCP control register 0 */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) +#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) +#define DCP_CTRL_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SFTRST_SHIFT (31U) +#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) + +/*! @name STAT - DCP status register */ +#define DCP_STAT_IRQ_MASK (0xFU) +#define DCP_STAT_IRQ_SHIFT (0U) +#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) +#define DCP_STAT_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) +#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_READY_CHANNELS_SHIFT (16U) +#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) +#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) +#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) + +/*! @name CHANNELCTRL - DCP channel control register */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) + +/*! @name CAPABILITY0 - DCP capability 0 register */ +#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) +#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) +#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) +#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) +#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) +#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) +#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) +#define DCP_CAPABILITY0_RSVD_SHIFT (12U) +#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) + +/*! @name CAPABILITY1 - DCP capability 1 register */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) + +/*! @name CONTEXT - DCP context buffer pointer */ +#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CONTEXT_ADDR_SHIFT (0U) +#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) + +/*! @name KEY - DCP key index */ +#define DCP_KEY_SUBWORD_MASK (0x3U) +#define DCP_KEY_SUBWORD_SHIFT (0U) +#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) +#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) +#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) +#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) +#define DCP_KEY_INDEX_MASK (0x30U) +#define DCP_KEY_INDEX_SHIFT (4U) +#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) +#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) +#define DCP_KEY_RSVD_INDEX_SHIFT (6U) +#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) +#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) +#define DCP_KEY_RSVD_SHIFT (8U) +#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) + +/*! @name KEYDATA - DCP key data */ +#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_KEYDATA_DATA_SHIFT (0U) +#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) + +/*! @name PACKET0 - DCP work packet 0 status register */ +#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET0_ADDR_SHIFT (0U) +#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) + +/*! @name PACKET1 - DCP work packet 1 status register */ +#define DCP_PACKET1_INTERRUPT_MASK (0x1U) +#define DCP_PACKET1_INTERRUPT_SHIFT (0U) +#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) +#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) +#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) +#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) +#define DCP_PACKET1_CHAIN_MASK (0x4U) +#define DCP_PACKET1_CHAIN_SHIFT (2U) +#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) +#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) +#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) +#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) +#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) +#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) +#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) +#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) +#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) +#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) +#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) +#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) +#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) +#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) +#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) +#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) +#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) +#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) +#define DCP_PACKET1_OTP_KEY_MASK (0x400U) +#define DCP_PACKET1_OTP_KEY_SHIFT (10U) +#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) +#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) +#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) +#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) +#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) +#define DCP_PACKET1_HASH_INIT_SHIFT (12U) +#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) +#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) +#define DCP_PACKET1_HASH_TERM_SHIFT (13U) +#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) +#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) +#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) +#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) +#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) +#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) +#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) +#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) +#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) +#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) +#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) +#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) +#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) +#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) +#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) +#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) +#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) +#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) +#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) +#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) +#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) +#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) +#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) +#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) +#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) +#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) +#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) +#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) +#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) +#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) +#define DCP_PACKET1_TAG_MASK (0xFF000000U) +#define DCP_PACKET1_TAG_SHIFT (24U) +#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) + +/*! @name PACKET2 - DCP work packet 2 status register */ +#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) +#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) +#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) +#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) +#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) +#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) +#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) +#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) +#define DCP_PACKET2_RSVD_MASK (0xF00000U) +#define DCP_PACKET2_RSVD_SHIFT (20U) +#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) +#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) +#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) +#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) + +/*! @name PACKET3 - DCP work packet 3 status register */ +#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET3_ADDR_SHIFT (0U) +#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) + +/*! @name PACKET4 - DCP work packet 4 status register */ +#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET4_ADDR_SHIFT (0U) +#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) + +/*! @name PACKET5 - DCP work packet 5 status register */ +#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) +#define DCP_PACKET5_COUNT_SHIFT (0U) +#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) + +/*! @name PACKET6 - DCP work packet 6 status register */ +#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET6_ADDR_SHIFT (0U) +#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) + +/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) + +/*! @name CH0SEMA - DCP channel 0 semaphore register */ +#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) +#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH0SEMA_VALUE_SHIFT (16U) +#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) + +/*! @name CH0STAT - DCP channel 0 status register */ +#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) +#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) +#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) +#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) +#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) +#define DCP_CH0STAT_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TAG_SHIFT (24U) +#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) + +/*! @name CH0OPTS - DCP channel 0 options register */ +#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) + +/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) + +/*! @name CH1SEMA - DCP channel 1 semaphore register */ +#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) +#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH1SEMA_VALUE_SHIFT (16U) +#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) + +/*! @name CH1STAT - DCP channel 1 status register */ +#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) +#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) +#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) +#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) +#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) +#define DCP_CH1STAT_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TAG_SHIFT (24U) +#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) + +/*! @name CH1OPTS - DCP channel 1 options register */ +#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) + +/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) + +/*! @name CH2SEMA - DCP channel 2 semaphore register */ +#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) +#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH2SEMA_VALUE_SHIFT (16U) +#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) + +/*! @name CH2STAT - DCP channel 2 status register */ +#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) +#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) +#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) +#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) +#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) +#define DCP_CH2STAT_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TAG_SHIFT (24U) +#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) + +/*! @name CH2OPTS - DCP channel 2 options register */ +#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) + +/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) + +/*! @name CH3SEMA - DCP channel 3 semaphore register */ +#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) +#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH3SEMA_VALUE_SHIFT (16U) +#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) + +/*! @name CH3STAT - DCP channel 3 status register */ +#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) +#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) +#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) +#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) +#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) +#define DCP_CH3STAT_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TAG_SHIFT (24U) +#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) + +/*! @name CH3OPTS - DCP channel 3 options register */ +#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) + +/*! @name DBGSELECT - DCP debug select register */ +#define DCP_DBGSELECT_INDEX_MASK (0xFFU) +#define DCP_DBGSELECT_INDEX_SHIFT (0U) +#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) +#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) +#define DCP_DBGSELECT_RSVD_SHIFT (8U) +#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) + +/*! @name DBGDATA - DCP debug data register */ +#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_DBGDATA_DATA_SHIFT (0U) +#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) + +/*! @name PAGETABLE - DCP page table register */ +#define DCP_PAGETABLE_ENABLE_MASK (0x1U) +#define DCP_PAGETABLE_ENABLE_SHIFT (0U) +#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) +#define DCP_PAGETABLE_FLUSH_MASK (0x2U) +#define DCP_PAGETABLE_FLUSH_SHIFT (1U) +#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) +#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) +#define DCP_PAGETABLE_BASE_SHIFT (2U) +#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) + +/*! @name VERSION - DCP version register */ +#define DCP_VERSION_STEP_MASK (0xFFFFU) +#define DCP_VERSION_STEP_SHIFT (0U) +#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) +#define DCP_VERSION_MINOR_MASK (0xFF0000U) +#define DCP_VERSION_MINOR_SHIFT (16U) +#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) +#define DCP_VERSION_MAJOR_MASK (0xFF000000U) +#define DCP_VERSION_MAJOR_SHIFT (24U) +#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group DCP_Register_Masks */ + + +/* DCP - Peripheral instance base addresses */ +/** Peripheral DCP base address */ +#define DCP_BASE (0x2280000u) +/** Peripheral DCP base pointer */ +#define DCP ((DCP_Type *)DCP_BASE) +/** Array initializer of DCP peripheral base addresses */ +#define DCP_BASE_ADDRS { DCP_BASE } +/** Array initializer of DCP peripheral base pointers */ +#define DCP_BASE_PTRS { DCP } +/** Interrupt vectors for the DCP peripheral type */ +#define DCP_IRQS { DCP_IRQ_IRQn } +#define DCP_VMI_IRQS { DCP_VMI_IRQ_IRQn } +#define DCP_SEC_IRQS { DCP_SEC_IRQ_IRQn } + +/*! + * @} + */ /* end of group DCP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ECSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer + * @{ + */ + +/** ECSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */ + __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */ + __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */ + __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */ + __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */ + __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */ + __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */ + __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */ + uint8_t RESERVED_0[28]; + __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ +} ECSPI_Type; + +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/*! @name RXDATA - Receive Data Register */ +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U) +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK) + +/*! @name TXDATA - Transmit Data Register */ +#define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U) +#define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK) + +/*! @name CONREG - Control Register */ +#define ECSPI_CONREG_EN_MASK (0x1U) +#define ECSPI_CONREG_EN_SHIFT (0U) +#define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK) +#define ECSPI_CONREG_HT_MASK (0x2U) +#define ECSPI_CONREG_HT_SHIFT (1U) +#define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK) +#define ECSPI_CONREG_XCH_MASK (0x4U) +#define ECSPI_CONREG_XCH_SHIFT (2U) +#define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK) +#define ECSPI_CONREG_SMC_MASK (0x8U) +#define ECSPI_CONREG_SMC_SHIFT (3U) +#define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK) +#define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U) +#define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U) +#define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK) +#define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U) +#define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U) +#define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK) +#define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U) +#define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U) +#define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK) +#define ECSPI_CONREG_DRCTL_MASK (0x30000U) +#define ECSPI_CONREG_DRCTL_SHIFT (16U) +#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK) +#define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U) +#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U) +#define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK) +#define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U) +#define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U) +#define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK) + +/*! @name CONFIGREG - Config Register */ +#define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU) +#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U) +#define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK) +#define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U) +#define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U) +#define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK) +#define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U) +#define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U) +#define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK) +#define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U) +#define ECSPI_CONFIGREG_SS_POL_SHIFT (12U) +#define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK) +#define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U) +#define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U) +#define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK) +#define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U) +#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U) +#define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK) +#define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U) +#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U) +#define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK) + +/*! @name INTREG - Interrupt Control Register */ +#define ECSPI_INTREG_TEEN_MASK (0x1U) +#define ECSPI_INTREG_TEEN_SHIFT (0U) +#define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK) +#define ECSPI_INTREG_TDREN_MASK (0x2U) +#define ECSPI_INTREG_TDREN_SHIFT (1U) +#define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK) +#define ECSPI_INTREG_TFEN_MASK (0x4U) +#define ECSPI_INTREG_TFEN_SHIFT (2U) +#define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK) +#define ECSPI_INTREG_RREN_MASK (0x8U) +#define ECSPI_INTREG_RREN_SHIFT (3U) +#define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK) +#define ECSPI_INTREG_RDREN_MASK (0x10U) +#define ECSPI_INTREG_RDREN_SHIFT (4U) +#define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK) +#define ECSPI_INTREG_RFEN_MASK (0x20U) +#define ECSPI_INTREG_RFEN_SHIFT (5U) +#define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK) +#define ECSPI_INTREG_ROEN_MASK (0x40U) +#define ECSPI_INTREG_ROEN_SHIFT (6U) +#define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK) +#define ECSPI_INTREG_TCEN_MASK (0x80U) +#define ECSPI_INTREG_TCEN_SHIFT (7U) +#define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK) + +/*! @name DMAREG - DMA Control Register */ +#define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU) +#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U) +#define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK) +#define ECSPI_DMAREG_TEDEN_MASK (0x80U) +#define ECSPI_DMAREG_TEDEN_SHIFT (7U) +#define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK) +#define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U) +#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U) +#define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK) +#define ECSPI_DMAREG_RXDEN_MASK (0x800000U) +#define ECSPI_DMAREG_RXDEN_SHIFT (23U) +#define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK) +#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U) +#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U) +#define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK) +#define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U) +#define ECSPI_DMAREG_RXTDEN_SHIFT (31U) +#define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK) + +/*! @name STATREG - Status Register */ +#define ECSPI_STATREG_TE_MASK (0x1U) +#define ECSPI_STATREG_TE_SHIFT (0U) +#define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK) +#define ECSPI_STATREG_TDR_MASK (0x2U) +#define ECSPI_STATREG_TDR_SHIFT (1U) +#define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK) +#define ECSPI_STATREG_TF_MASK (0x4U) +#define ECSPI_STATREG_TF_SHIFT (2U) +#define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK) +#define ECSPI_STATREG_RR_MASK (0x8U) +#define ECSPI_STATREG_RR_SHIFT (3U) +#define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK) +#define ECSPI_STATREG_RDR_MASK (0x10U) +#define ECSPI_STATREG_RDR_SHIFT (4U) +#define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK) +#define ECSPI_STATREG_RF_MASK (0x20U) +#define ECSPI_STATREG_RF_SHIFT (5U) +#define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK) +#define ECSPI_STATREG_RO_MASK (0x40U) +#define ECSPI_STATREG_RO_SHIFT (6U) +#define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK) +#define ECSPI_STATREG_TC_MASK (0x80U) +#define ECSPI_STATREG_TC_SHIFT (7U) +#define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK) + +/*! @name PERIODREG - Sample Period Control Register */ +#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU) +#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U) +#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK) +#define ECSPI_PERIODREG_CSRC_MASK (0x8000U) +#define ECSPI_PERIODREG_CSRC_SHIFT (15U) +#define ECSPI_PERIODREG_CSRC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK) +#define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U) +#define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U) +#define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK) + +/*! @name TESTREG - Test Control Register */ +#define ECSPI_TESTREG_TXCNT_MASK (0x7FU) +#define ECSPI_TESTREG_TXCNT_SHIFT (0U) +#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK) +#define ECSPI_TESTREG_RXCNT_MASK (0x7F00U) +#define ECSPI_TESTREG_RXCNT_SHIFT (8U) +#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK) +#define ECSPI_TESTREG_LBC_MASK (0x80000000U) +#define ECSPI_TESTREG_LBC_SHIFT (31U) +#define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK) + +/*! @name MSGDATA - Message Data Register */ +#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU) +#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U) +#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK) + + +/*! + * @} + */ /* end of group ECSPI_Register_Masks */ + + +/* ECSPI - Peripheral instance base addresses */ +/** Peripheral ECSPI1 base address */ +#define ECSPI1_BASE (0x2008000u) +/** Peripheral ECSPI1 base pointer */ +#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE) +/** Peripheral ECSPI2 base address */ +#define ECSPI2_BASE (0x200C000u) +/** Peripheral ECSPI2 base pointer */ +#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE) +/** Peripheral ECSPI3 base address */ +#define ECSPI3_BASE (0x2010000u) +/** Peripheral ECSPI3 base pointer */ +#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE) +/** Peripheral ECSPI4 base address */ +#define ECSPI4_BASE (0x2014000u) +/** Peripheral ECSPI4 base pointer */ +#define ECSPI4 ((ECSPI_Type *)ECSPI4_BASE) +/** Array initializer of ECSPI peripheral base addresses */ +#define ECSPI_BASE_ADDRS { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE, ECSPI4_BASE } +/** Array initializer of ECSPI peripheral base pointers */ +#define ECSPI_BASE_PTRS { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3, ECSPI4 } +/** Interrupt vectors for the ECSPI peripheral type */ +#define ECSPI_IRQS { NotAvail_IRQn, eCSPI1_IRQn, eCSPI2_IRQn, eCSPI3_IRQn, eCSPI4_IRQn } + +/*! + * @} + */ /* end of group ECSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS0GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x0 */ + __IO uint32_t CS0GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x4 */ + __IO uint32_t CS0RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x8 */ + __IO uint32_t CS0RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0xC */ + __IO uint32_t CS0WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x10 */ + __IO uint32_t CS0WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x14 */ + __IO uint32_t CS1GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x18 */ + __IO uint32_t CS1GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x1C */ + __IO uint32_t CS1RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x20 */ + __IO uint32_t CS1RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x24 */ + __IO uint32_t CS1WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x28 */ + __IO uint32_t CS1WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x2C */ + __IO uint32_t CS2GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x30 */ + __IO uint32_t CS2GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x34 */ + __IO uint32_t CS2RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x38 */ + __IO uint32_t CS2RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x3C */ + __IO uint32_t CS2WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x40 */ + __IO uint32_t CS2WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x44 */ + __IO uint32_t CS3GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x48 */ + __IO uint32_t CS3GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x4C */ + __IO uint32_t CS3RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x50 */ + __IO uint32_t CS3RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x54 */ + __IO uint32_t CS3WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x58 */ + __IO uint32_t CS3WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x5C */ + __IO uint32_t CS4GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x60 */ + __IO uint32_t CS4GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x64 */ + __IO uint32_t CS4RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x68 */ + __IO uint32_t CS4RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x6C */ + __IO uint32_t CS4WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x70 */ + __IO uint32_t CS4WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x74 */ + __IO uint32_t CS5GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x78 */ + __IO uint32_t CS5GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x7C */ + __IO uint32_t CS5RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x80 */ + __IO uint32_t CS5RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x84 */ + __IO uint32_t CS5WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x88 */ + __IO uint32_t CS5WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x8C */ + __IO uint32_t WCR; /**< EIM Configuration Register, offset: 0x90 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name CS0GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS0GCR1_CSEN_MASK (0x1U) +#define EIM_CS0GCR1_CSEN_SHIFT (0U) +#define EIM_CS0GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CSEN_SHIFT)) & EIM_CS0GCR1_CSEN_MASK) +#define EIM_CS0GCR1_SWR_MASK (0x2U) +#define EIM_CS0GCR1_SWR_SHIFT (1U) +#define EIM_CS0GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SWR_SHIFT)) & EIM_CS0GCR1_SWR_MASK) +#define EIM_CS0GCR1_SRD_MASK (0x4U) +#define EIM_CS0GCR1_SRD_SHIFT (2U) +#define EIM_CS0GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SRD_SHIFT)) & EIM_CS0GCR1_SRD_MASK) +#define EIM_CS0GCR1_MUM_MASK (0x8U) +#define EIM_CS0GCR1_MUM_SHIFT (3U) +#define EIM_CS0GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_MUM_SHIFT)) & EIM_CS0GCR1_MUM_MASK) +#define EIM_CS0GCR1_WFL_MASK (0x10U) +#define EIM_CS0GCR1_WFL_SHIFT (4U) +#define EIM_CS0GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WFL_SHIFT)) & EIM_CS0GCR1_WFL_MASK) +#define EIM_CS0GCR1_RFL_MASK (0x20U) +#define EIM_CS0GCR1_RFL_SHIFT (5U) +#define EIM_CS0GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_RFL_SHIFT)) & EIM_CS0GCR1_RFL_MASK) +#define EIM_CS0GCR1_CRE_MASK (0x40U) +#define EIM_CS0GCR1_CRE_SHIFT (6U) +#define EIM_CS0GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CRE_SHIFT)) & EIM_CS0GCR1_CRE_MASK) +#define EIM_CS0GCR1_CREP_MASK (0x80U) +#define EIM_CS0GCR1_CREP_SHIFT (7U) +#define EIM_CS0GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CREP_SHIFT)) & EIM_CS0GCR1_CREP_MASK) +#define EIM_CS0GCR1_BL_MASK (0x700U) +#define EIM_CS0GCR1_BL_SHIFT (8U) +#define EIM_CS0GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BL_SHIFT)) & EIM_CS0GCR1_BL_MASK) +#define EIM_CS0GCR1_WC_MASK (0x800U) +#define EIM_CS0GCR1_WC_SHIFT (11U) +#define EIM_CS0GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WC_SHIFT)) & EIM_CS0GCR1_WC_MASK) +#define EIM_CS0GCR1_BCD_MASK (0x3000U) +#define EIM_CS0GCR1_BCD_SHIFT (12U) +#define EIM_CS0GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BCD_SHIFT)) & EIM_CS0GCR1_BCD_MASK) +#define EIM_CS0GCR1_BCS_MASK (0xC000U) +#define EIM_CS0GCR1_BCS_SHIFT (14U) +#define EIM_CS0GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BCS_SHIFT)) & EIM_CS0GCR1_BCS_MASK) +#define EIM_CS0GCR1_DSZ_MASK (0x70000U) +#define EIM_CS0GCR1_DSZ_SHIFT (16U) +#define EIM_CS0GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_DSZ_SHIFT)) & EIM_CS0GCR1_DSZ_MASK) +#define EIM_CS0GCR1_SP_MASK (0x80000U) +#define EIM_CS0GCR1_SP_SHIFT (19U) +#define EIM_CS0GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SP_SHIFT)) & EIM_CS0GCR1_SP_MASK) +#define EIM_CS0GCR1_CSREC_MASK (0x700000U) +#define EIM_CS0GCR1_CSREC_SHIFT (20U) +#define EIM_CS0GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CSREC_SHIFT)) & EIM_CS0GCR1_CSREC_MASK) +#define EIM_CS0GCR1_AUS_MASK (0x800000U) +#define EIM_CS0GCR1_AUS_SHIFT (23U) +#define EIM_CS0GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_AUS_SHIFT)) & EIM_CS0GCR1_AUS_MASK) +#define EIM_CS0GCR1_GBC_MASK (0x7000000U) +#define EIM_CS0GCR1_GBC_SHIFT (24U) +#define EIM_CS0GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_GBC_SHIFT)) & EIM_CS0GCR1_GBC_MASK) +#define EIM_CS0GCR1_WP_MASK (0x8000000U) +#define EIM_CS0GCR1_WP_SHIFT (27U) +#define EIM_CS0GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WP_SHIFT)) & EIM_CS0GCR1_WP_MASK) +#define EIM_CS0GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS0GCR1_PSZ_SHIFT (28U) +#define EIM_CS0GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_PSZ_SHIFT)) & EIM_CS0GCR1_PSZ_MASK) + +/*! @name CS0GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS0GCR2_ADH_MASK (0x3U) +#define EIM_CS0GCR2_ADH_SHIFT (0U) +#define EIM_CS0GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_ADH_SHIFT)) & EIM_CS0GCR2_ADH_MASK) +#define EIM_CS0GCR2_DAPS_MASK (0xF0U) +#define EIM_CS0GCR2_DAPS_SHIFT (4U) +#define EIM_CS0GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAPS_SHIFT)) & EIM_CS0GCR2_DAPS_MASK) +#define EIM_CS0GCR2_DAE_MASK (0x100U) +#define EIM_CS0GCR2_DAE_SHIFT (8U) +#define EIM_CS0GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAE_SHIFT)) & EIM_CS0GCR2_DAE_MASK) +#define EIM_CS0GCR2_DAP_MASK (0x200U) +#define EIM_CS0GCR2_DAP_SHIFT (9U) +#define EIM_CS0GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAP_SHIFT)) & EIM_CS0GCR2_DAP_MASK) +#define EIM_CS0GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS0GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS0GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS0GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS0RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS0RCR1_RCSN_MASK (0x7U) +#define EIM_CS0RCR1_RCSN_SHIFT (0U) +#define EIM_CS0RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RCSN_SHIFT)) & EIM_CS0RCR1_RCSN_MASK) +#define EIM_CS0RCR1_RCSA_MASK (0x70U) +#define EIM_CS0RCR1_RCSA_SHIFT (4U) +#define EIM_CS0RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RCSA_SHIFT)) & EIM_CS0RCR1_RCSA_MASK) +#define EIM_CS0RCR1_OEN_MASK (0x700U) +#define EIM_CS0RCR1_OEN_SHIFT (8U) +#define EIM_CS0RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_OEN_SHIFT)) & EIM_CS0RCR1_OEN_MASK) +#define EIM_CS0RCR1_OEA_MASK (0x7000U) +#define EIM_CS0RCR1_OEA_SHIFT (12U) +#define EIM_CS0RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_OEA_SHIFT)) & EIM_CS0RCR1_OEA_MASK) +#define EIM_CS0RCR1_RADVN_MASK (0x70000U) +#define EIM_CS0RCR1_RADVN_SHIFT (16U) +#define EIM_CS0RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RADVN_SHIFT)) & EIM_CS0RCR1_RADVN_MASK) +#define EIM_CS0RCR1_RAL_MASK (0x80000U) +#define EIM_CS0RCR1_RAL_SHIFT (19U) +#define EIM_CS0RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RAL_SHIFT)) & EIM_CS0RCR1_RAL_MASK) +#define EIM_CS0RCR1_RADVA_MASK (0x700000U) +#define EIM_CS0RCR1_RADVA_SHIFT (20U) +#define EIM_CS0RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RADVA_SHIFT)) & EIM_CS0RCR1_RADVA_MASK) +#define EIM_CS0RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS0RCR1_RWSC_SHIFT (24U) +#define EIM_CS0RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RWSC_SHIFT)) & EIM_CS0RCR1_RWSC_MASK) + +/*! @name CS0RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS0RCR2_RBEN_MASK (0x7U) +#define EIM_CS0RCR2_RBEN_SHIFT (0U) +#define EIM_CS0RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBEN_SHIFT)) & EIM_CS0RCR2_RBEN_MASK) +#define EIM_CS0RCR2_RBE_MASK (0x8U) +#define EIM_CS0RCR2_RBE_SHIFT (3U) +#define EIM_CS0RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBE_SHIFT)) & EIM_CS0RCR2_RBE_MASK) +#define EIM_CS0RCR2_RBEA_MASK (0x70U) +#define EIM_CS0RCR2_RBEA_SHIFT (4U) +#define EIM_CS0RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBEA_SHIFT)) & EIM_CS0RCR2_RBEA_MASK) +#define EIM_CS0RCR2_RL_MASK (0x300U) +#define EIM_CS0RCR2_RL_SHIFT (8U) +#define EIM_CS0RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RL_SHIFT)) & EIM_CS0RCR2_RL_MASK) +#define EIM_CS0RCR2_PAT_MASK (0x7000U) +#define EIM_CS0RCR2_PAT_SHIFT (12U) +#define EIM_CS0RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_PAT_SHIFT)) & EIM_CS0RCR2_PAT_MASK) +#define EIM_CS0RCR2_APR_MASK (0x8000U) +#define EIM_CS0RCR2_APR_SHIFT (15U) +#define EIM_CS0RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_APR_SHIFT)) & EIM_CS0RCR2_APR_MASK) + +/*! @name CS0WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS0WCR1_WCSN_MASK (0x7U) +#define EIM_CS0WCR1_WCSN_SHIFT (0U) +#define EIM_CS0WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WCSN_SHIFT)) & EIM_CS0WCR1_WCSN_MASK) +#define EIM_CS0WCR1_WCSA_MASK (0x38U) +#define EIM_CS0WCR1_WCSA_SHIFT (3U) +#define EIM_CS0WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WCSA_SHIFT)) & EIM_CS0WCR1_WCSA_MASK) +#define EIM_CS0WCR1_WEN_MASK (0x1C0U) +#define EIM_CS0WCR1_WEN_SHIFT (6U) +#define EIM_CS0WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WEN_SHIFT)) & EIM_CS0WCR1_WEN_MASK) +#define EIM_CS0WCR1_WEA_MASK (0xE00U) +#define EIM_CS0WCR1_WEA_SHIFT (9U) +#define EIM_CS0WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WEA_SHIFT)) & EIM_CS0WCR1_WEA_MASK) +#define EIM_CS0WCR1_WBEN_MASK (0x7000U) +#define EIM_CS0WCR1_WBEN_SHIFT (12U) +#define EIM_CS0WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBEN_SHIFT)) & EIM_CS0WCR1_WBEN_MASK) +#define EIM_CS0WCR1_WBEA_MASK (0x38000U) +#define EIM_CS0WCR1_WBEA_SHIFT (15U) +#define EIM_CS0WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBEA_SHIFT)) & EIM_CS0WCR1_WBEA_MASK) +#define EIM_CS0WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS0WCR1_WADVN_SHIFT (18U) +#define EIM_CS0WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WADVN_SHIFT)) & EIM_CS0WCR1_WADVN_MASK) +#define EIM_CS0WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS0WCR1_WADVA_SHIFT (21U) +#define EIM_CS0WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WADVA_SHIFT)) & EIM_CS0WCR1_WADVA_MASK) +#define EIM_CS0WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS0WCR1_WWSC_SHIFT (24U) +#define EIM_CS0WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WWSC_SHIFT)) & EIM_CS0WCR1_WWSC_MASK) +#define EIM_CS0WCR1_WBED_MASK (0x40000000U) +#define EIM_CS0WCR1_WBED_SHIFT (30U) +#define EIM_CS0WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBED_SHIFT)) & EIM_CS0WCR1_WBED_MASK) +#define EIM_CS0WCR1_WAL_MASK (0x80000000U) +#define EIM_CS0WCR1_WAL_SHIFT (31U) +#define EIM_CS0WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WAL_SHIFT)) & EIM_CS0WCR1_WAL_MASK) + +/*! @name CS0WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS0WCR2_WBCDD_MASK (0x1U) +#define EIM_CS0WCR2_WBCDD_SHIFT (0U) +#define EIM_CS0WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR2_WBCDD_SHIFT)) & EIM_CS0WCR2_WBCDD_MASK) + +/*! @name CS1GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS1GCR1_CSEN_MASK (0x1U) +#define EIM_CS1GCR1_CSEN_SHIFT (0U) +#define EIM_CS1GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CSEN_SHIFT)) & EIM_CS1GCR1_CSEN_MASK) +#define EIM_CS1GCR1_SWR_MASK (0x2U) +#define EIM_CS1GCR1_SWR_SHIFT (1U) +#define EIM_CS1GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SWR_SHIFT)) & EIM_CS1GCR1_SWR_MASK) +#define EIM_CS1GCR1_SRD_MASK (0x4U) +#define EIM_CS1GCR1_SRD_SHIFT (2U) +#define EIM_CS1GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SRD_SHIFT)) & EIM_CS1GCR1_SRD_MASK) +#define EIM_CS1GCR1_MUM_MASK (0x8U) +#define EIM_CS1GCR1_MUM_SHIFT (3U) +#define EIM_CS1GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_MUM_SHIFT)) & EIM_CS1GCR1_MUM_MASK) +#define EIM_CS1GCR1_WFL_MASK (0x10U) +#define EIM_CS1GCR1_WFL_SHIFT (4U) +#define EIM_CS1GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WFL_SHIFT)) & EIM_CS1GCR1_WFL_MASK) +#define EIM_CS1GCR1_RFL_MASK (0x20U) +#define EIM_CS1GCR1_RFL_SHIFT (5U) +#define EIM_CS1GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_RFL_SHIFT)) & EIM_CS1GCR1_RFL_MASK) +#define EIM_CS1GCR1_CRE_MASK (0x40U) +#define EIM_CS1GCR1_CRE_SHIFT (6U) +#define EIM_CS1GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CRE_SHIFT)) & EIM_CS1GCR1_CRE_MASK) +#define EIM_CS1GCR1_CREP_MASK (0x80U) +#define EIM_CS1GCR1_CREP_SHIFT (7U) +#define EIM_CS1GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CREP_SHIFT)) & EIM_CS1GCR1_CREP_MASK) +#define EIM_CS1GCR1_BL_MASK (0x700U) +#define EIM_CS1GCR1_BL_SHIFT (8U) +#define EIM_CS1GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BL_SHIFT)) & EIM_CS1GCR1_BL_MASK) +#define EIM_CS1GCR1_WC_MASK (0x800U) +#define EIM_CS1GCR1_WC_SHIFT (11U) +#define EIM_CS1GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WC_SHIFT)) & EIM_CS1GCR1_WC_MASK) +#define EIM_CS1GCR1_BCD_MASK (0x3000U) +#define EIM_CS1GCR1_BCD_SHIFT (12U) +#define EIM_CS1GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BCD_SHIFT)) & EIM_CS1GCR1_BCD_MASK) +#define EIM_CS1GCR1_BCS_MASK (0xC000U) +#define EIM_CS1GCR1_BCS_SHIFT (14U) +#define EIM_CS1GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BCS_SHIFT)) & EIM_CS1GCR1_BCS_MASK) +#define EIM_CS1GCR1_DSZ_MASK (0x70000U) +#define EIM_CS1GCR1_DSZ_SHIFT (16U) +#define EIM_CS1GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_DSZ_SHIFT)) & EIM_CS1GCR1_DSZ_MASK) +#define EIM_CS1GCR1_SP_MASK (0x80000U) +#define EIM_CS1GCR1_SP_SHIFT (19U) +#define EIM_CS1GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SP_SHIFT)) & EIM_CS1GCR1_SP_MASK) +#define EIM_CS1GCR1_CSREC_MASK (0x700000U) +#define EIM_CS1GCR1_CSREC_SHIFT (20U) +#define EIM_CS1GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CSREC_SHIFT)) & EIM_CS1GCR1_CSREC_MASK) +#define EIM_CS1GCR1_AUS_MASK (0x800000U) +#define EIM_CS1GCR1_AUS_SHIFT (23U) +#define EIM_CS1GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_AUS_SHIFT)) & EIM_CS1GCR1_AUS_MASK) +#define EIM_CS1GCR1_GBC_MASK (0x7000000U) +#define EIM_CS1GCR1_GBC_SHIFT (24U) +#define EIM_CS1GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_GBC_SHIFT)) & EIM_CS1GCR1_GBC_MASK) +#define EIM_CS1GCR1_WP_MASK (0x8000000U) +#define EIM_CS1GCR1_WP_SHIFT (27U) +#define EIM_CS1GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WP_SHIFT)) & EIM_CS1GCR1_WP_MASK) +#define EIM_CS1GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS1GCR1_PSZ_SHIFT (28U) +#define EIM_CS1GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_PSZ_SHIFT)) & EIM_CS1GCR1_PSZ_MASK) + +/*! @name CS1GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS1GCR2_ADH_MASK (0x3U) +#define EIM_CS1GCR2_ADH_SHIFT (0U) +#define EIM_CS1GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_ADH_SHIFT)) & EIM_CS1GCR2_ADH_MASK) +#define EIM_CS1GCR2_DAPS_MASK (0xF0U) +#define EIM_CS1GCR2_DAPS_SHIFT (4U) +#define EIM_CS1GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAPS_SHIFT)) & EIM_CS1GCR2_DAPS_MASK) +#define EIM_CS1GCR2_DAE_MASK (0x100U) +#define EIM_CS1GCR2_DAE_SHIFT (8U) +#define EIM_CS1GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAE_SHIFT)) & EIM_CS1GCR2_DAE_MASK) +#define EIM_CS1GCR2_DAP_MASK (0x200U) +#define EIM_CS1GCR2_DAP_SHIFT (9U) +#define EIM_CS1GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAP_SHIFT)) & EIM_CS1GCR2_DAP_MASK) +#define EIM_CS1GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS1GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS1GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS1GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS1RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS1RCR1_RCSN_MASK (0x7U) +#define EIM_CS1RCR1_RCSN_SHIFT (0U) +#define EIM_CS1RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RCSN_SHIFT)) & EIM_CS1RCR1_RCSN_MASK) +#define EIM_CS1RCR1_RCSA_MASK (0x70U) +#define EIM_CS1RCR1_RCSA_SHIFT (4U) +#define EIM_CS1RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RCSA_SHIFT)) & EIM_CS1RCR1_RCSA_MASK) +#define EIM_CS1RCR1_OEN_MASK (0x700U) +#define EIM_CS1RCR1_OEN_SHIFT (8U) +#define EIM_CS1RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_OEN_SHIFT)) & EIM_CS1RCR1_OEN_MASK) +#define EIM_CS1RCR1_OEA_MASK (0x7000U) +#define EIM_CS1RCR1_OEA_SHIFT (12U) +#define EIM_CS1RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_OEA_SHIFT)) & EIM_CS1RCR1_OEA_MASK) +#define EIM_CS1RCR1_RADVN_MASK (0x70000U) +#define EIM_CS1RCR1_RADVN_SHIFT (16U) +#define EIM_CS1RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RADVN_SHIFT)) & EIM_CS1RCR1_RADVN_MASK) +#define EIM_CS1RCR1_RAL_MASK (0x80000U) +#define EIM_CS1RCR1_RAL_SHIFT (19U) +#define EIM_CS1RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RAL_SHIFT)) & EIM_CS1RCR1_RAL_MASK) +#define EIM_CS1RCR1_RADVA_MASK (0x700000U) +#define EIM_CS1RCR1_RADVA_SHIFT (20U) +#define EIM_CS1RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RADVA_SHIFT)) & EIM_CS1RCR1_RADVA_MASK) +#define EIM_CS1RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS1RCR1_RWSC_SHIFT (24U) +#define EIM_CS1RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RWSC_SHIFT)) & EIM_CS1RCR1_RWSC_MASK) + +/*! @name CS1RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS1RCR2_RBEN_MASK (0x7U) +#define EIM_CS1RCR2_RBEN_SHIFT (0U) +#define EIM_CS1RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBEN_SHIFT)) & EIM_CS1RCR2_RBEN_MASK) +#define EIM_CS1RCR2_RBE_MASK (0x8U) +#define EIM_CS1RCR2_RBE_SHIFT (3U) +#define EIM_CS1RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBE_SHIFT)) & EIM_CS1RCR2_RBE_MASK) +#define EIM_CS1RCR2_RBEA_MASK (0x70U) +#define EIM_CS1RCR2_RBEA_SHIFT (4U) +#define EIM_CS1RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBEA_SHIFT)) & EIM_CS1RCR2_RBEA_MASK) +#define EIM_CS1RCR2_RL_MASK (0x300U) +#define EIM_CS1RCR2_RL_SHIFT (8U) +#define EIM_CS1RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RL_SHIFT)) & EIM_CS1RCR2_RL_MASK) +#define EIM_CS1RCR2_PAT_MASK (0x7000U) +#define EIM_CS1RCR2_PAT_SHIFT (12U) +#define EIM_CS1RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_PAT_SHIFT)) & EIM_CS1RCR2_PAT_MASK) +#define EIM_CS1RCR2_APR_MASK (0x8000U) +#define EIM_CS1RCR2_APR_SHIFT (15U) +#define EIM_CS1RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_APR_SHIFT)) & EIM_CS1RCR2_APR_MASK) + +/*! @name CS1WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS1WCR1_WCSN_MASK (0x7U) +#define EIM_CS1WCR1_WCSN_SHIFT (0U) +#define EIM_CS1WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WCSN_SHIFT)) & EIM_CS1WCR1_WCSN_MASK) +#define EIM_CS1WCR1_WCSA_MASK (0x38U) +#define EIM_CS1WCR1_WCSA_SHIFT (3U) +#define EIM_CS1WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WCSA_SHIFT)) & EIM_CS1WCR1_WCSA_MASK) +#define EIM_CS1WCR1_WEN_MASK (0x1C0U) +#define EIM_CS1WCR1_WEN_SHIFT (6U) +#define EIM_CS1WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WEN_SHIFT)) & EIM_CS1WCR1_WEN_MASK) +#define EIM_CS1WCR1_WEA_MASK (0xE00U) +#define EIM_CS1WCR1_WEA_SHIFT (9U) +#define EIM_CS1WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WEA_SHIFT)) & EIM_CS1WCR1_WEA_MASK) +#define EIM_CS1WCR1_WBEN_MASK (0x7000U) +#define EIM_CS1WCR1_WBEN_SHIFT (12U) +#define EIM_CS1WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBEN_SHIFT)) & EIM_CS1WCR1_WBEN_MASK) +#define EIM_CS1WCR1_WBEA_MASK (0x38000U) +#define EIM_CS1WCR1_WBEA_SHIFT (15U) +#define EIM_CS1WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBEA_SHIFT)) & EIM_CS1WCR1_WBEA_MASK) +#define EIM_CS1WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS1WCR1_WADVN_SHIFT (18U) +#define EIM_CS1WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WADVN_SHIFT)) & EIM_CS1WCR1_WADVN_MASK) +#define EIM_CS1WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS1WCR1_WADVA_SHIFT (21U) +#define EIM_CS1WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WADVA_SHIFT)) & EIM_CS1WCR1_WADVA_MASK) +#define EIM_CS1WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS1WCR1_WWSC_SHIFT (24U) +#define EIM_CS1WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WWSC_SHIFT)) & EIM_CS1WCR1_WWSC_MASK) +#define EIM_CS1WCR1_WBED_MASK (0x40000000U) +#define EIM_CS1WCR1_WBED_SHIFT (30U) +#define EIM_CS1WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBED_SHIFT)) & EIM_CS1WCR1_WBED_MASK) +#define EIM_CS1WCR1_WAL_MASK (0x80000000U) +#define EIM_CS1WCR1_WAL_SHIFT (31U) +#define EIM_CS1WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WAL_SHIFT)) & EIM_CS1WCR1_WAL_MASK) + +/*! @name CS1WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS1WCR2_WBCDD_MASK (0x1U) +#define EIM_CS1WCR2_WBCDD_SHIFT (0U) +#define EIM_CS1WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR2_WBCDD_SHIFT)) & EIM_CS1WCR2_WBCDD_MASK) + +/*! @name CS2GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS2GCR1_CSEN_MASK (0x1U) +#define EIM_CS2GCR1_CSEN_SHIFT (0U) +#define EIM_CS2GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CSEN_SHIFT)) & EIM_CS2GCR1_CSEN_MASK) +#define EIM_CS2GCR1_SWR_MASK (0x2U) +#define EIM_CS2GCR1_SWR_SHIFT (1U) +#define EIM_CS2GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SWR_SHIFT)) & EIM_CS2GCR1_SWR_MASK) +#define EIM_CS2GCR1_SRD_MASK (0x4U) +#define EIM_CS2GCR1_SRD_SHIFT (2U) +#define EIM_CS2GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SRD_SHIFT)) & EIM_CS2GCR1_SRD_MASK) +#define EIM_CS2GCR1_MUM_MASK (0x8U) +#define EIM_CS2GCR1_MUM_SHIFT (3U) +#define EIM_CS2GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_MUM_SHIFT)) & EIM_CS2GCR1_MUM_MASK) +#define EIM_CS2GCR1_WFL_MASK (0x10U) +#define EIM_CS2GCR1_WFL_SHIFT (4U) +#define EIM_CS2GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WFL_SHIFT)) & EIM_CS2GCR1_WFL_MASK) +#define EIM_CS2GCR1_RFL_MASK (0x20U) +#define EIM_CS2GCR1_RFL_SHIFT (5U) +#define EIM_CS2GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_RFL_SHIFT)) & EIM_CS2GCR1_RFL_MASK) +#define EIM_CS2GCR1_CRE_MASK (0x40U) +#define EIM_CS2GCR1_CRE_SHIFT (6U) +#define EIM_CS2GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CRE_SHIFT)) & EIM_CS2GCR1_CRE_MASK) +#define EIM_CS2GCR1_CREP_MASK (0x80U) +#define EIM_CS2GCR1_CREP_SHIFT (7U) +#define EIM_CS2GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CREP_SHIFT)) & EIM_CS2GCR1_CREP_MASK) +#define EIM_CS2GCR1_BL_MASK (0x700U) +#define EIM_CS2GCR1_BL_SHIFT (8U) +#define EIM_CS2GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BL_SHIFT)) & EIM_CS2GCR1_BL_MASK) +#define EIM_CS2GCR1_WC_MASK (0x800U) +#define EIM_CS2GCR1_WC_SHIFT (11U) +#define EIM_CS2GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WC_SHIFT)) & EIM_CS2GCR1_WC_MASK) +#define EIM_CS2GCR1_BCD_MASK (0x3000U) +#define EIM_CS2GCR1_BCD_SHIFT (12U) +#define EIM_CS2GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BCD_SHIFT)) & EIM_CS2GCR1_BCD_MASK) +#define EIM_CS2GCR1_BCS_MASK (0xC000U) +#define EIM_CS2GCR1_BCS_SHIFT (14U) +#define EIM_CS2GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BCS_SHIFT)) & EIM_CS2GCR1_BCS_MASK) +#define EIM_CS2GCR1_DSZ_MASK (0x70000U) +#define EIM_CS2GCR1_DSZ_SHIFT (16U) +#define EIM_CS2GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_DSZ_SHIFT)) & EIM_CS2GCR1_DSZ_MASK) +#define EIM_CS2GCR1_SP_MASK (0x80000U) +#define EIM_CS2GCR1_SP_SHIFT (19U) +#define EIM_CS2GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SP_SHIFT)) & EIM_CS2GCR1_SP_MASK) +#define EIM_CS2GCR1_CSREC_MASK (0x700000U) +#define EIM_CS2GCR1_CSREC_SHIFT (20U) +#define EIM_CS2GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CSREC_SHIFT)) & EIM_CS2GCR1_CSREC_MASK) +#define EIM_CS2GCR1_AUS_MASK (0x800000U) +#define EIM_CS2GCR1_AUS_SHIFT (23U) +#define EIM_CS2GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_AUS_SHIFT)) & EIM_CS2GCR1_AUS_MASK) +#define EIM_CS2GCR1_GBC_MASK (0x7000000U) +#define EIM_CS2GCR1_GBC_SHIFT (24U) +#define EIM_CS2GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_GBC_SHIFT)) & EIM_CS2GCR1_GBC_MASK) +#define EIM_CS2GCR1_WP_MASK (0x8000000U) +#define EIM_CS2GCR1_WP_SHIFT (27U) +#define EIM_CS2GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WP_SHIFT)) & EIM_CS2GCR1_WP_MASK) +#define EIM_CS2GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS2GCR1_PSZ_SHIFT (28U) +#define EIM_CS2GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_PSZ_SHIFT)) & EIM_CS2GCR1_PSZ_MASK) + +/*! @name CS2GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS2GCR2_ADH_MASK (0x3U) +#define EIM_CS2GCR2_ADH_SHIFT (0U) +#define EIM_CS2GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_ADH_SHIFT)) & EIM_CS2GCR2_ADH_MASK) +#define EIM_CS2GCR2_DAPS_MASK (0xF0U) +#define EIM_CS2GCR2_DAPS_SHIFT (4U) +#define EIM_CS2GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAPS_SHIFT)) & EIM_CS2GCR2_DAPS_MASK) +#define EIM_CS2GCR2_DAE_MASK (0x100U) +#define EIM_CS2GCR2_DAE_SHIFT (8U) +#define EIM_CS2GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAE_SHIFT)) & EIM_CS2GCR2_DAE_MASK) +#define EIM_CS2GCR2_DAP_MASK (0x200U) +#define EIM_CS2GCR2_DAP_SHIFT (9U) +#define EIM_CS2GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAP_SHIFT)) & EIM_CS2GCR2_DAP_MASK) +#define EIM_CS2GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS2GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS2GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS2GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS2RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS2RCR1_RCSN_MASK (0x7U) +#define EIM_CS2RCR1_RCSN_SHIFT (0U) +#define EIM_CS2RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RCSN_SHIFT)) & EIM_CS2RCR1_RCSN_MASK) +#define EIM_CS2RCR1_RCSA_MASK (0x70U) +#define EIM_CS2RCR1_RCSA_SHIFT (4U) +#define EIM_CS2RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RCSA_SHIFT)) & EIM_CS2RCR1_RCSA_MASK) +#define EIM_CS2RCR1_OEN_MASK (0x700U) +#define EIM_CS2RCR1_OEN_SHIFT (8U) +#define EIM_CS2RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_OEN_SHIFT)) & EIM_CS2RCR1_OEN_MASK) +#define EIM_CS2RCR1_OEA_MASK (0x7000U) +#define EIM_CS2RCR1_OEA_SHIFT (12U) +#define EIM_CS2RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_OEA_SHIFT)) & EIM_CS2RCR1_OEA_MASK) +#define EIM_CS2RCR1_RADVN_MASK (0x70000U) +#define EIM_CS2RCR1_RADVN_SHIFT (16U) +#define EIM_CS2RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RADVN_SHIFT)) & EIM_CS2RCR1_RADVN_MASK) +#define EIM_CS2RCR1_RAL_MASK (0x80000U) +#define EIM_CS2RCR1_RAL_SHIFT (19U) +#define EIM_CS2RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RAL_SHIFT)) & EIM_CS2RCR1_RAL_MASK) +#define EIM_CS2RCR1_RADVA_MASK (0x700000U) +#define EIM_CS2RCR1_RADVA_SHIFT (20U) +#define EIM_CS2RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RADVA_SHIFT)) & EIM_CS2RCR1_RADVA_MASK) +#define EIM_CS2RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS2RCR1_RWSC_SHIFT (24U) +#define EIM_CS2RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RWSC_SHIFT)) & EIM_CS2RCR1_RWSC_MASK) + +/*! @name CS2RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS2RCR2_RBEN_MASK (0x7U) +#define EIM_CS2RCR2_RBEN_SHIFT (0U) +#define EIM_CS2RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBEN_SHIFT)) & EIM_CS2RCR2_RBEN_MASK) +#define EIM_CS2RCR2_RBE_MASK (0x8U) +#define EIM_CS2RCR2_RBE_SHIFT (3U) +#define EIM_CS2RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBE_SHIFT)) & EIM_CS2RCR2_RBE_MASK) +#define EIM_CS2RCR2_RBEA_MASK (0x70U) +#define EIM_CS2RCR2_RBEA_SHIFT (4U) +#define EIM_CS2RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBEA_SHIFT)) & EIM_CS2RCR2_RBEA_MASK) +#define EIM_CS2RCR2_RL_MASK (0x300U) +#define EIM_CS2RCR2_RL_SHIFT (8U) +#define EIM_CS2RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RL_SHIFT)) & EIM_CS2RCR2_RL_MASK) +#define EIM_CS2RCR2_PAT_MASK (0x7000U) +#define EIM_CS2RCR2_PAT_SHIFT (12U) +#define EIM_CS2RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_PAT_SHIFT)) & EIM_CS2RCR2_PAT_MASK) +#define EIM_CS2RCR2_APR_MASK (0x8000U) +#define EIM_CS2RCR2_APR_SHIFT (15U) +#define EIM_CS2RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_APR_SHIFT)) & EIM_CS2RCR2_APR_MASK) + +/*! @name CS2WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS2WCR1_WCSN_MASK (0x7U) +#define EIM_CS2WCR1_WCSN_SHIFT (0U) +#define EIM_CS2WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WCSN_SHIFT)) & EIM_CS2WCR1_WCSN_MASK) +#define EIM_CS2WCR1_WCSA_MASK (0x38U) +#define EIM_CS2WCR1_WCSA_SHIFT (3U) +#define EIM_CS2WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WCSA_SHIFT)) & EIM_CS2WCR1_WCSA_MASK) +#define EIM_CS2WCR1_WEN_MASK (0x1C0U) +#define EIM_CS2WCR1_WEN_SHIFT (6U) +#define EIM_CS2WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WEN_SHIFT)) & EIM_CS2WCR1_WEN_MASK) +#define EIM_CS2WCR1_WEA_MASK (0xE00U) +#define EIM_CS2WCR1_WEA_SHIFT (9U) +#define EIM_CS2WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WEA_SHIFT)) & EIM_CS2WCR1_WEA_MASK) +#define EIM_CS2WCR1_WBEN_MASK (0x7000U) +#define EIM_CS2WCR1_WBEN_SHIFT (12U) +#define EIM_CS2WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBEN_SHIFT)) & EIM_CS2WCR1_WBEN_MASK) +#define EIM_CS2WCR1_WBEA_MASK (0x38000U) +#define EIM_CS2WCR1_WBEA_SHIFT (15U) +#define EIM_CS2WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBEA_SHIFT)) & EIM_CS2WCR1_WBEA_MASK) +#define EIM_CS2WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS2WCR1_WADVN_SHIFT (18U) +#define EIM_CS2WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WADVN_SHIFT)) & EIM_CS2WCR1_WADVN_MASK) +#define EIM_CS2WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS2WCR1_WADVA_SHIFT (21U) +#define EIM_CS2WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WADVA_SHIFT)) & EIM_CS2WCR1_WADVA_MASK) +#define EIM_CS2WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS2WCR1_WWSC_SHIFT (24U) +#define EIM_CS2WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WWSC_SHIFT)) & EIM_CS2WCR1_WWSC_MASK) +#define EIM_CS2WCR1_WBED_MASK (0x40000000U) +#define EIM_CS2WCR1_WBED_SHIFT (30U) +#define EIM_CS2WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBED_SHIFT)) & EIM_CS2WCR1_WBED_MASK) +#define EIM_CS2WCR1_WAL_MASK (0x80000000U) +#define EIM_CS2WCR1_WAL_SHIFT (31U) +#define EIM_CS2WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WAL_SHIFT)) & EIM_CS2WCR1_WAL_MASK) + +/*! @name CS2WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS2WCR2_WBCDD_MASK (0x1U) +#define EIM_CS2WCR2_WBCDD_SHIFT (0U) +#define EIM_CS2WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR2_WBCDD_SHIFT)) & EIM_CS2WCR2_WBCDD_MASK) + +/*! @name CS3GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS3GCR1_CSEN_MASK (0x1U) +#define EIM_CS3GCR1_CSEN_SHIFT (0U) +#define EIM_CS3GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CSEN_SHIFT)) & EIM_CS3GCR1_CSEN_MASK) +#define EIM_CS3GCR1_SWR_MASK (0x2U) +#define EIM_CS3GCR1_SWR_SHIFT (1U) +#define EIM_CS3GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SWR_SHIFT)) & EIM_CS3GCR1_SWR_MASK) +#define EIM_CS3GCR1_SRD_MASK (0x4U) +#define EIM_CS3GCR1_SRD_SHIFT (2U) +#define EIM_CS3GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SRD_SHIFT)) & EIM_CS3GCR1_SRD_MASK) +#define EIM_CS3GCR1_MUM_MASK (0x8U) +#define EIM_CS3GCR1_MUM_SHIFT (3U) +#define EIM_CS3GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_MUM_SHIFT)) & EIM_CS3GCR1_MUM_MASK) +#define EIM_CS3GCR1_WFL_MASK (0x10U) +#define EIM_CS3GCR1_WFL_SHIFT (4U) +#define EIM_CS3GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WFL_SHIFT)) & EIM_CS3GCR1_WFL_MASK) +#define EIM_CS3GCR1_RFL_MASK (0x20U) +#define EIM_CS3GCR1_RFL_SHIFT (5U) +#define EIM_CS3GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_RFL_SHIFT)) & EIM_CS3GCR1_RFL_MASK) +#define EIM_CS3GCR1_CRE_MASK (0x40U) +#define EIM_CS3GCR1_CRE_SHIFT (6U) +#define EIM_CS3GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CRE_SHIFT)) & EIM_CS3GCR1_CRE_MASK) +#define EIM_CS3GCR1_CREP_MASK (0x80U) +#define EIM_CS3GCR1_CREP_SHIFT (7U) +#define EIM_CS3GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CREP_SHIFT)) & EIM_CS3GCR1_CREP_MASK) +#define EIM_CS3GCR1_BL_MASK (0x700U) +#define EIM_CS3GCR1_BL_SHIFT (8U) +#define EIM_CS3GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BL_SHIFT)) & EIM_CS3GCR1_BL_MASK) +#define EIM_CS3GCR1_WC_MASK (0x800U) +#define EIM_CS3GCR1_WC_SHIFT (11U) +#define EIM_CS3GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WC_SHIFT)) & EIM_CS3GCR1_WC_MASK) +#define EIM_CS3GCR1_BCD_MASK (0x3000U) +#define EIM_CS3GCR1_BCD_SHIFT (12U) +#define EIM_CS3GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BCD_SHIFT)) & EIM_CS3GCR1_BCD_MASK) +#define EIM_CS3GCR1_BCS_MASK (0xC000U) +#define EIM_CS3GCR1_BCS_SHIFT (14U) +#define EIM_CS3GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BCS_SHIFT)) & EIM_CS3GCR1_BCS_MASK) +#define EIM_CS3GCR1_DSZ_MASK (0x70000U) +#define EIM_CS3GCR1_DSZ_SHIFT (16U) +#define EIM_CS3GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_DSZ_SHIFT)) & EIM_CS3GCR1_DSZ_MASK) +#define EIM_CS3GCR1_SP_MASK (0x80000U) +#define EIM_CS3GCR1_SP_SHIFT (19U) +#define EIM_CS3GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SP_SHIFT)) & EIM_CS3GCR1_SP_MASK) +#define EIM_CS3GCR1_CSREC_MASK (0x700000U) +#define EIM_CS3GCR1_CSREC_SHIFT (20U) +#define EIM_CS3GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CSREC_SHIFT)) & EIM_CS3GCR1_CSREC_MASK) +#define EIM_CS3GCR1_AUS_MASK (0x800000U) +#define EIM_CS3GCR1_AUS_SHIFT (23U) +#define EIM_CS3GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_AUS_SHIFT)) & EIM_CS3GCR1_AUS_MASK) +#define EIM_CS3GCR1_GBC_MASK (0x7000000U) +#define EIM_CS3GCR1_GBC_SHIFT (24U) +#define EIM_CS3GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_GBC_SHIFT)) & EIM_CS3GCR1_GBC_MASK) +#define EIM_CS3GCR1_WP_MASK (0x8000000U) +#define EIM_CS3GCR1_WP_SHIFT (27U) +#define EIM_CS3GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WP_SHIFT)) & EIM_CS3GCR1_WP_MASK) +#define EIM_CS3GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS3GCR1_PSZ_SHIFT (28U) +#define EIM_CS3GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_PSZ_SHIFT)) & EIM_CS3GCR1_PSZ_MASK) + +/*! @name CS3GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS3GCR2_ADH_MASK (0x3U) +#define EIM_CS3GCR2_ADH_SHIFT (0U) +#define EIM_CS3GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_ADH_SHIFT)) & EIM_CS3GCR2_ADH_MASK) +#define EIM_CS3GCR2_DAPS_MASK (0xF0U) +#define EIM_CS3GCR2_DAPS_SHIFT (4U) +#define EIM_CS3GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAPS_SHIFT)) & EIM_CS3GCR2_DAPS_MASK) +#define EIM_CS3GCR2_DAE_MASK (0x100U) +#define EIM_CS3GCR2_DAE_SHIFT (8U) +#define EIM_CS3GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAE_SHIFT)) & EIM_CS3GCR2_DAE_MASK) +#define EIM_CS3GCR2_DAP_MASK (0x200U) +#define EIM_CS3GCR2_DAP_SHIFT (9U) +#define EIM_CS3GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAP_SHIFT)) & EIM_CS3GCR2_DAP_MASK) +#define EIM_CS3GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS3GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS3GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS3GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS3RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS3RCR1_RCSN_MASK (0x7U) +#define EIM_CS3RCR1_RCSN_SHIFT (0U) +#define EIM_CS3RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RCSN_SHIFT)) & EIM_CS3RCR1_RCSN_MASK) +#define EIM_CS3RCR1_RCSA_MASK (0x70U) +#define EIM_CS3RCR1_RCSA_SHIFT (4U) +#define EIM_CS3RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RCSA_SHIFT)) & EIM_CS3RCR1_RCSA_MASK) +#define EIM_CS3RCR1_OEN_MASK (0x700U) +#define EIM_CS3RCR1_OEN_SHIFT (8U) +#define EIM_CS3RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_OEN_SHIFT)) & EIM_CS3RCR1_OEN_MASK) +#define EIM_CS3RCR1_OEA_MASK (0x7000U) +#define EIM_CS3RCR1_OEA_SHIFT (12U) +#define EIM_CS3RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_OEA_SHIFT)) & EIM_CS3RCR1_OEA_MASK) +#define EIM_CS3RCR1_RADVN_MASK (0x70000U) +#define EIM_CS3RCR1_RADVN_SHIFT (16U) +#define EIM_CS3RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RADVN_SHIFT)) & EIM_CS3RCR1_RADVN_MASK) +#define EIM_CS3RCR1_RAL_MASK (0x80000U) +#define EIM_CS3RCR1_RAL_SHIFT (19U) +#define EIM_CS3RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RAL_SHIFT)) & EIM_CS3RCR1_RAL_MASK) +#define EIM_CS3RCR1_RADVA_MASK (0x700000U) +#define EIM_CS3RCR1_RADVA_SHIFT (20U) +#define EIM_CS3RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RADVA_SHIFT)) & EIM_CS3RCR1_RADVA_MASK) +#define EIM_CS3RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS3RCR1_RWSC_SHIFT (24U) +#define EIM_CS3RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RWSC_SHIFT)) & EIM_CS3RCR1_RWSC_MASK) + +/*! @name CS3RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS3RCR2_RBEN_MASK (0x7U) +#define EIM_CS3RCR2_RBEN_SHIFT (0U) +#define EIM_CS3RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBEN_SHIFT)) & EIM_CS3RCR2_RBEN_MASK) +#define EIM_CS3RCR2_RBE_MASK (0x8U) +#define EIM_CS3RCR2_RBE_SHIFT (3U) +#define EIM_CS3RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBE_SHIFT)) & EIM_CS3RCR2_RBE_MASK) +#define EIM_CS3RCR2_RBEA_MASK (0x70U) +#define EIM_CS3RCR2_RBEA_SHIFT (4U) +#define EIM_CS3RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBEA_SHIFT)) & EIM_CS3RCR2_RBEA_MASK) +#define EIM_CS3RCR2_RL_MASK (0x300U) +#define EIM_CS3RCR2_RL_SHIFT (8U) +#define EIM_CS3RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RL_SHIFT)) & EIM_CS3RCR2_RL_MASK) +#define EIM_CS3RCR2_PAT_MASK (0x7000U) +#define EIM_CS3RCR2_PAT_SHIFT (12U) +#define EIM_CS3RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_PAT_SHIFT)) & EIM_CS3RCR2_PAT_MASK) +#define EIM_CS3RCR2_APR_MASK (0x8000U) +#define EIM_CS3RCR2_APR_SHIFT (15U) +#define EIM_CS3RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_APR_SHIFT)) & EIM_CS3RCR2_APR_MASK) + +/*! @name CS3WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS3WCR1_WCSN_MASK (0x7U) +#define EIM_CS3WCR1_WCSN_SHIFT (0U) +#define EIM_CS3WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WCSN_SHIFT)) & EIM_CS3WCR1_WCSN_MASK) +#define EIM_CS3WCR1_WCSA_MASK (0x38U) +#define EIM_CS3WCR1_WCSA_SHIFT (3U) +#define EIM_CS3WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WCSA_SHIFT)) & EIM_CS3WCR1_WCSA_MASK) +#define EIM_CS3WCR1_WEN_MASK (0x1C0U) +#define EIM_CS3WCR1_WEN_SHIFT (6U) +#define EIM_CS3WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WEN_SHIFT)) & EIM_CS3WCR1_WEN_MASK) +#define EIM_CS3WCR1_WEA_MASK (0xE00U) +#define EIM_CS3WCR1_WEA_SHIFT (9U) +#define EIM_CS3WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WEA_SHIFT)) & EIM_CS3WCR1_WEA_MASK) +#define EIM_CS3WCR1_WBEN_MASK (0x7000U) +#define EIM_CS3WCR1_WBEN_SHIFT (12U) +#define EIM_CS3WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBEN_SHIFT)) & EIM_CS3WCR1_WBEN_MASK) +#define EIM_CS3WCR1_WBEA_MASK (0x38000U) +#define EIM_CS3WCR1_WBEA_SHIFT (15U) +#define EIM_CS3WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBEA_SHIFT)) & EIM_CS3WCR1_WBEA_MASK) +#define EIM_CS3WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS3WCR1_WADVN_SHIFT (18U) +#define EIM_CS3WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WADVN_SHIFT)) & EIM_CS3WCR1_WADVN_MASK) +#define EIM_CS3WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS3WCR1_WADVA_SHIFT (21U) +#define EIM_CS3WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WADVA_SHIFT)) & EIM_CS3WCR1_WADVA_MASK) +#define EIM_CS3WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS3WCR1_WWSC_SHIFT (24U) +#define EIM_CS3WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WWSC_SHIFT)) & EIM_CS3WCR1_WWSC_MASK) +#define EIM_CS3WCR1_WBED_MASK (0x40000000U) +#define EIM_CS3WCR1_WBED_SHIFT (30U) +#define EIM_CS3WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBED_SHIFT)) & EIM_CS3WCR1_WBED_MASK) +#define EIM_CS3WCR1_WAL_MASK (0x80000000U) +#define EIM_CS3WCR1_WAL_SHIFT (31U) +#define EIM_CS3WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WAL_SHIFT)) & EIM_CS3WCR1_WAL_MASK) + +/*! @name CS3WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS3WCR2_WBCDD_MASK (0x1U) +#define EIM_CS3WCR2_WBCDD_SHIFT (0U) +#define EIM_CS3WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR2_WBCDD_SHIFT)) & EIM_CS3WCR2_WBCDD_MASK) + +/*! @name CS4GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS4GCR1_CSEN_MASK (0x1U) +#define EIM_CS4GCR1_CSEN_SHIFT (0U) +#define EIM_CS4GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CSEN_SHIFT)) & EIM_CS4GCR1_CSEN_MASK) +#define EIM_CS4GCR1_SWR_MASK (0x2U) +#define EIM_CS4GCR1_SWR_SHIFT (1U) +#define EIM_CS4GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SWR_SHIFT)) & EIM_CS4GCR1_SWR_MASK) +#define EIM_CS4GCR1_SRD_MASK (0x4U) +#define EIM_CS4GCR1_SRD_SHIFT (2U) +#define EIM_CS4GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SRD_SHIFT)) & EIM_CS4GCR1_SRD_MASK) +#define EIM_CS4GCR1_MUM_MASK (0x8U) +#define EIM_CS4GCR1_MUM_SHIFT (3U) +#define EIM_CS4GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_MUM_SHIFT)) & EIM_CS4GCR1_MUM_MASK) +#define EIM_CS4GCR1_WFL_MASK (0x10U) +#define EIM_CS4GCR1_WFL_SHIFT (4U) +#define EIM_CS4GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WFL_SHIFT)) & EIM_CS4GCR1_WFL_MASK) +#define EIM_CS4GCR1_RFL_MASK (0x20U) +#define EIM_CS4GCR1_RFL_SHIFT (5U) +#define EIM_CS4GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_RFL_SHIFT)) & EIM_CS4GCR1_RFL_MASK) +#define EIM_CS4GCR1_CRE_MASK (0x40U) +#define EIM_CS4GCR1_CRE_SHIFT (6U) +#define EIM_CS4GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CRE_SHIFT)) & EIM_CS4GCR1_CRE_MASK) +#define EIM_CS4GCR1_CREP_MASK (0x80U) +#define EIM_CS4GCR1_CREP_SHIFT (7U) +#define EIM_CS4GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CREP_SHIFT)) & EIM_CS4GCR1_CREP_MASK) +#define EIM_CS4GCR1_BL_MASK (0x700U) +#define EIM_CS4GCR1_BL_SHIFT (8U) +#define EIM_CS4GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BL_SHIFT)) & EIM_CS4GCR1_BL_MASK) +#define EIM_CS4GCR1_WC_MASK (0x800U) +#define EIM_CS4GCR1_WC_SHIFT (11U) +#define EIM_CS4GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WC_SHIFT)) & EIM_CS4GCR1_WC_MASK) +#define EIM_CS4GCR1_BCD_MASK (0x3000U) +#define EIM_CS4GCR1_BCD_SHIFT (12U) +#define EIM_CS4GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BCD_SHIFT)) & EIM_CS4GCR1_BCD_MASK) +#define EIM_CS4GCR1_BCS_MASK (0xC000U) +#define EIM_CS4GCR1_BCS_SHIFT (14U) +#define EIM_CS4GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BCS_SHIFT)) & EIM_CS4GCR1_BCS_MASK) +#define EIM_CS4GCR1_DSZ_MASK (0x70000U) +#define EIM_CS4GCR1_DSZ_SHIFT (16U) +#define EIM_CS4GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_DSZ_SHIFT)) & EIM_CS4GCR1_DSZ_MASK) +#define EIM_CS4GCR1_SP_MASK (0x80000U) +#define EIM_CS4GCR1_SP_SHIFT (19U) +#define EIM_CS4GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SP_SHIFT)) & EIM_CS4GCR1_SP_MASK) +#define EIM_CS4GCR1_CSREC_MASK (0x700000U) +#define EIM_CS4GCR1_CSREC_SHIFT (20U) +#define EIM_CS4GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CSREC_SHIFT)) & EIM_CS4GCR1_CSREC_MASK) +#define EIM_CS4GCR1_AUS_MASK (0x800000U) +#define EIM_CS4GCR1_AUS_SHIFT (23U) +#define EIM_CS4GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_AUS_SHIFT)) & EIM_CS4GCR1_AUS_MASK) +#define EIM_CS4GCR1_GBC_MASK (0x7000000U) +#define EIM_CS4GCR1_GBC_SHIFT (24U) +#define EIM_CS4GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_GBC_SHIFT)) & EIM_CS4GCR1_GBC_MASK) +#define EIM_CS4GCR1_WP_MASK (0x8000000U) +#define EIM_CS4GCR1_WP_SHIFT (27U) +#define EIM_CS4GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WP_SHIFT)) & EIM_CS4GCR1_WP_MASK) +#define EIM_CS4GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS4GCR1_PSZ_SHIFT (28U) +#define EIM_CS4GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_PSZ_SHIFT)) & EIM_CS4GCR1_PSZ_MASK) + +/*! @name CS4GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS4GCR2_ADH_MASK (0x3U) +#define EIM_CS4GCR2_ADH_SHIFT (0U) +#define EIM_CS4GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_ADH_SHIFT)) & EIM_CS4GCR2_ADH_MASK) +#define EIM_CS4GCR2_DAPS_MASK (0xF0U) +#define EIM_CS4GCR2_DAPS_SHIFT (4U) +#define EIM_CS4GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAPS_SHIFT)) & EIM_CS4GCR2_DAPS_MASK) +#define EIM_CS4GCR2_DAE_MASK (0x100U) +#define EIM_CS4GCR2_DAE_SHIFT (8U) +#define EIM_CS4GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAE_SHIFT)) & EIM_CS4GCR2_DAE_MASK) +#define EIM_CS4GCR2_DAP_MASK (0x200U) +#define EIM_CS4GCR2_DAP_SHIFT (9U) +#define EIM_CS4GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAP_SHIFT)) & EIM_CS4GCR2_DAP_MASK) +#define EIM_CS4GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS4GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS4GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS4GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS4RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS4RCR1_RCSN_MASK (0x7U) +#define EIM_CS4RCR1_RCSN_SHIFT (0U) +#define EIM_CS4RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RCSN_SHIFT)) & EIM_CS4RCR1_RCSN_MASK) +#define EIM_CS4RCR1_RCSA_MASK (0x70U) +#define EIM_CS4RCR1_RCSA_SHIFT (4U) +#define EIM_CS4RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RCSA_SHIFT)) & EIM_CS4RCR1_RCSA_MASK) +#define EIM_CS4RCR1_OEN_MASK (0x700U) +#define EIM_CS4RCR1_OEN_SHIFT (8U) +#define EIM_CS4RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_OEN_SHIFT)) & EIM_CS4RCR1_OEN_MASK) +#define EIM_CS4RCR1_OEA_MASK (0x7000U) +#define EIM_CS4RCR1_OEA_SHIFT (12U) +#define EIM_CS4RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_OEA_SHIFT)) & EIM_CS4RCR1_OEA_MASK) +#define EIM_CS4RCR1_RADVN_MASK (0x70000U) +#define EIM_CS4RCR1_RADVN_SHIFT (16U) +#define EIM_CS4RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RADVN_SHIFT)) & EIM_CS4RCR1_RADVN_MASK) +#define EIM_CS4RCR1_RAL_MASK (0x80000U) +#define EIM_CS4RCR1_RAL_SHIFT (19U) +#define EIM_CS4RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RAL_SHIFT)) & EIM_CS4RCR1_RAL_MASK) +#define EIM_CS4RCR1_RADVA_MASK (0x700000U) +#define EIM_CS4RCR1_RADVA_SHIFT (20U) +#define EIM_CS4RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RADVA_SHIFT)) & EIM_CS4RCR1_RADVA_MASK) +#define EIM_CS4RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS4RCR1_RWSC_SHIFT (24U) +#define EIM_CS4RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RWSC_SHIFT)) & EIM_CS4RCR1_RWSC_MASK) + +/*! @name CS4RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS4RCR2_RBEN_MASK (0x7U) +#define EIM_CS4RCR2_RBEN_SHIFT (0U) +#define EIM_CS4RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBEN_SHIFT)) & EIM_CS4RCR2_RBEN_MASK) +#define EIM_CS4RCR2_RBE_MASK (0x8U) +#define EIM_CS4RCR2_RBE_SHIFT (3U) +#define EIM_CS4RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBE_SHIFT)) & EIM_CS4RCR2_RBE_MASK) +#define EIM_CS4RCR2_RBEA_MASK (0x70U) +#define EIM_CS4RCR2_RBEA_SHIFT (4U) +#define EIM_CS4RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBEA_SHIFT)) & EIM_CS4RCR2_RBEA_MASK) +#define EIM_CS4RCR2_RL_MASK (0x300U) +#define EIM_CS4RCR2_RL_SHIFT (8U) +#define EIM_CS4RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RL_SHIFT)) & EIM_CS4RCR2_RL_MASK) +#define EIM_CS4RCR2_PAT_MASK (0x7000U) +#define EIM_CS4RCR2_PAT_SHIFT (12U) +#define EIM_CS4RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_PAT_SHIFT)) & EIM_CS4RCR2_PAT_MASK) +#define EIM_CS4RCR2_APR_MASK (0x8000U) +#define EIM_CS4RCR2_APR_SHIFT (15U) +#define EIM_CS4RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_APR_SHIFT)) & EIM_CS4RCR2_APR_MASK) + +/*! @name CS4WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS4WCR1_WCSN_MASK (0x7U) +#define EIM_CS4WCR1_WCSN_SHIFT (0U) +#define EIM_CS4WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WCSN_SHIFT)) & EIM_CS4WCR1_WCSN_MASK) +#define EIM_CS4WCR1_WCSA_MASK (0x38U) +#define EIM_CS4WCR1_WCSA_SHIFT (3U) +#define EIM_CS4WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WCSA_SHIFT)) & EIM_CS4WCR1_WCSA_MASK) +#define EIM_CS4WCR1_WEN_MASK (0x1C0U) +#define EIM_CS4WCR1_WEN_SHIFT (6U) +#define EIM_CS4WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WEN_SHIFT)) & EIM_CS4WCR1_WEN_MASK) +#define EIM_CS4WCR1_WEA_MASK (0xE00U) +#define EIM_CS4WCR1_WEA_SHIFT (9U) +#define EIM_CS4WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WEA_SHIFT)) & EIM_CS4WCR1_WEA_MASK) +#define EIM_CS4WCR1_WBEN_MASK (0x7000U) +#define EIM_CS4WCR1_WBEN_SHIFT (12U) +#define EIM_CS4WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBEN_SHIFT)) & EIM_CS4WCR1_WBEN_MASK) +#define EIM_CS4WCR1_WBEA_MASK (0x38000U) +#define EIM_CS4WCR1_WBEA_SHIFT (15U) +#define EIM_CS4WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBEA_SHIFT)) & EIM_CS4WCR1_WBEA_MASK) +#define EIM_CS4WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS4WCR1_WADVN_SHIFT (18U) +#define EIM_CS4WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WADVN_SHIFT)) & EIM_CS4WCR1_WADVN_MASK) +#define EIM_CS4WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS4WCR1_WADVA_SHIFT (21U) +#define EIM_CS4WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WADVA_SHIFT)) & EIM_CS4WCR1_WADVA_MASK) +#define EIM_CS4WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS4WCR1_WWSC_SHIFT (24U) +#define EIM_CS4WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WWSC_SHIFT)) & EIM_CS4WCR1_WWSC_MASK) +#define EIM_CS4WCR1_WBED_MASK (0x40000000U) +#define EIM_CS4WCR1_WBED_SHIFT (30U) +#define EIM_CS4WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBED_SHIFT)) & EIM_CS4WCR1_WBED_MASK) +#define EIM_CS4WCR1_WAL_MASK (0x80000000U) +#define EIM_CS4WCR1_WAL_SHIFT (31U) +#define EIM_CS4WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WAL_SHIFT)) & EIM_CS4WCR1_WAL_MASK) + +/*! @name CS4WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS4WCR2_WBCDD_MASK (0x1U) +#define EIM_CS4WCR2_WBCDD_SHIFT (0U) +#define EIM_CS4WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR2_WBCDD_SHIFT)) & EIM_CS4WCR2_WBCDD_MASK) + +/*! @name CS5GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS5GCR1_CSEN_MASK (0x1U) +#define EIM_CS5GCR1_CSEN_SHIFT (0U) +#define EIM_CS5GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CSEN_SHIFT)) & EIM_CS5GCR1_CSEN_MASK) +#define EIM_CS5GCR1_SWR_MASK (0x2U) +#define EIM_CS5GCR1_SWR_SHIFT (1U) +#define EIM_CS5GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SWR_SHIFT)) & EIM_CS5GCR1_SWR_MASK) +#define EIM_CS5GCR1_SRD_MASK (0x4U) +#define EIM_CS5GCR1_SRD_SHIFT (2U) +#define EIM_CS5GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SRD_SHIFT)) & EIM_CS5GCR1_SRD_MASK) +#define EIM_CS5GCR1_MUM_MASK (0x8U) +#define EIM_CS5GCR1_MUM_SHIFT (3U) +#define EIM_CS5GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_MUM_SHIFT)) & EIM_CS5GCR1_MUM_MASK) +#define EIM_CS5GCR1_WFL_MASK (0x10U) +#define EIM_CS5GCR1_WFL_SHIFT (4U) +#define EIM_CS5GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WFL_SHIFT)) & EIM_CS5GCR1_WFL_MASK) +#define EIM_CS5GCR1_RFL_MASK (0x20U) +#define EIM_CS5GCR1_RFL_SHIFT (5U) +#define EIM_CS5GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_RFL_SHIFT)) & EIM_CS5GCR1_RFL_MASK) +#define EIM_CS5GCR1_CRE_MASK (0x40U) +#define EIM_CS5GCR1_CRE_SHIFT (6U) +#define EIM_CS5GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CRE_SHIFT)) & EIM_CS5GCR1_CRE_MASK) +#define EIM_CS5GCR1_CREP_MASK (0x80U) +#define EIM_CS5GCR1_CREP_SHIFT (7U) +#define EIM_CS5GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CREP_SHIFT)) & EIM_CS5GCR1_CREP_MASK) +#define EIM_CS5GCR1_BL_MASK (0x700U) +#define EIM_CS5GCR1_BL_SHIFT (8U) +#define EIM_CS5GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BL_SHIFT)) & EIM_CS5GCR1_BL_MASK) +#define EIM_CS5GCR1_WC_MASK (0x800U) +#define EIM_CS5GCR1_WC_SHIFT (11U) +#define EIM_CS5GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WC_SHIFT)) & EIM_CS5GCR1_WC_MASK) +#define EIM_CS5GCR1_BCD_MASK (0x3000U) +#define EIM_CS5GCR1_BCD_SHIFT (12U) +#define EIM_CS5GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BCD_SHIFT)) & EIM_CS5GCR1_BCD_MASK) +#define EIM_CS5GCR1_BCS_MASK (0xC000U) +#define EIM_CS5GCR1_BCS_SHIFT (14U) +#define EIM_CS5GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BCS_SHIFT)) & EIM_CS5GCR1_BCS_MASK) +#define EIM_CS5GCR1_DSZ_MASK (0x70000U) +#define EIM_CS5GCR1_DSZ_SHIFT (16U) +#define EIM_CS5GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_DSZ_SHIFT)) & EIM_CS5GCR1_DSZ_MASK) +#define EIM_CS5GCR1_SP_MASK (0x80000U) +#define EIM_CS5GCR1_SP_SHIFT (19U) +#define EIM_CS5GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SP_SHIFT)) & EIM_CS5GCR1_SP_MASK) +#define EIM_CS5GCR1_CSREC_MASK (0x700000U) +#define EIM_CS5GCR1_CSREC_SHIFT (20U) +#define EIM_CS5GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CSREC_SHIFT)) & EIM_CS5GCR1_CSREC_MASK) +#define EIM_CS5GCR1_AUS_MASK (0x800000U) +#define EIM_CS5GCR1_AUS_SHIFT (23U) +#define EIM_CS5GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_AUS_SHIFT)) & EIM_CS5GCR1_AUS_MASK) +#define EIM_CS5GCR1_GBC_MASK (0x7000000U) +#define EIM_CS5GCR1_GBC_SHIFT (24U) +#define EIM_CS5GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_GBC_SHIFT)) & EIM_CS5GCR1_GBC_MASK) +#define EIM_CS5GCR1_WP_MASK (0x8000000U) +#define EIM_CS5GCR1_WP_SHIFT (27U) +#define EIM_CS5GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WP_SHIFT)) & EIM_CS5GCR1_WP_MASK) +#define EIM_CS5GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS5GCR1_PSZ_SHIFT (28U) +#define EIM_CS5GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_PSZ_SHIFT)) & EIM_CS5GCR1_PSZ_MASK) + +/*! @name CS5GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS5GCR2_ADH_MASK (0x3U) +#define EIM_CS5GCR2_ADH_SHIFT (0U) +#define EIM_CS5GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_ADH_SHIFT)) & EIM_CS5GCR2_ADH_MASK) +#define EIM_CS5GCR2_DAPS_MASK (0xF0U) +#define EIM_CS5GCR2_DAPS_SHIFT (4U) +#define EIM_CS5GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAPS_SHIFT)) & EIM_CS5GCR2_DAPS_MASK) +#define EIM_CS5GCR2_DAE_MASK (0x100U) +#define EIM_CS5GCR2_DAE_SHIFT (8U) +#define EIM_CS5GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAE_SHIFT)) & EIM_CS5GCR2_DAE_MASK) +#define EIM_CS5GCR2_DAP_MASK (0x200U) +#define EIM_CS5GCR2_DAP_SHIFT (9U) +#define EIM_CS5GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAP_SHIFT)) & EIM_CS5GCR2_DAP_MASK) +#define EIM_CS5GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS5GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS5GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS5GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS5RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS5RCR1_RCSN_MASK (0x7U) +#define EIM_CS5RCR1_RCSN_SHIFT (0U) +#define EIM_CS5RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RCSN_SHIFT)) & EIM_CS5RCR1_RCSN_MASK) +#define EIM_CS5RCR1_RCSA_MASK (0x70U) +#define EIM_CS5RCR1_RCSA_SHIFT (4U) +#define EIM_CS5RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RCSA_SHIFT)) & EIM_CS5RCR1_RCSA_MASK) +#define EIM_CS5RCR1_OEN_MASK (0x700U) +#define EIM_CS5RCR1_OEN_SHIFT (8U) +#define EIM_CS5RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_OEN_SHIFT)) & EIM_CS5RCR1_OEN_MASK) +#define EIM_CS5RCR1_OEA_MASK (0x7000U) +#define EIM_CS5RCR1_OEA_SHIFT (12U) +#define EIM_CS5RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_OEA_SHIFT)) & EIM_CS5RCR1_OEA_MASK) +#define EIM_CS5RCR1_RADVN_MASK (0x70000U) +#define EIM_CS5RCR1_RADVN_SHIFT (16U) +#define EIM_CS5RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RADVN_SHIFT)) & EIM_CS5RCR1_RADVN_MASK) +#define EIM_CS5RCR1_RAL_MASK (0x80000U) +#define EIM_CS5RCR1_RAL_SHIFT (19U) +#define EIM_CS5RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RAL_SHIFT)) & EIM_CS5RCR1_RAL_MASK) +#define EIM_CS5RCR1_RADVA_MASK (0x700000U) +#define EIM_CS5RCR1_RADVA_SHIFT (20U) +#define EIM_CS5RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RADVA_SHIFT)) & EIM_CS5RCR1_RADVA_MASK) +#define EIM_CS5RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS5RCR1_RWSC_SHIFT (24U) +#define EIM_CS5RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RWSC_SHIFT)) & EIM_CS5RCR1_RWSC_MASK) + +/*! @name CS5RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS5RCR2_RBEN_MASK (0x7U) +#define EIM_CS5RCR2_RBEN_SHIFT (0U) +#define EIM_CS5RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBEN_SHIFT)) & EIM_CS5RCR2_RBEN_MASK) +#define EIM_CS5RCR2_RBE_MASK (0x8U) +#define EIM_CS5RCR2_RBE_SHIFT (3U) +#define EIM_CS5RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBE_SHIFT)) & EIM_CS5RCR2_RBE_MASK) +#define EIM_CS5RCR2_RBEA_MASK (0x70U) +#define EIM_CS5RCR2_RBEA_SHIFT (4U) +#define EIM_CS5RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBEA_SHIFT)) & EIM_CS5RCR2_RBEA_MASK) +#define EIM_CS5RCR2_RL_MASK (0x300U) +#define EIM_CS5RCR2_RL_SHIFT (8U) +#define EIM_CS5RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RL_SHIFT)) & EIM_CS5RCR2_RL_MASK) +#define EIM_CS5RCR2_PAT_MASK (0x7000U) +#define EIM_CS5RCR2_PAT_SHIFT (12U) +#define EIM_CS5RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_PAT_SHIFT)) & EIM_CS5RCR2_PAT_MASK) +#define EIM_CS5RCR2_APR_MASK (0x8000U) +#define EIM_CS5RCR2_APR_SHIFT (15U) +#define EIM_CS5RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_APR_SHIFT)) & EIM_CS5RCR2_APR_MASK) + +/*! @name CS5WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS5WCR1_WCSN_MASK (0x7U) +#define EIM_CS5WCR1_WCSN_SHIFT (0U) +#define EIM_CS5WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WCSN_SHIFT)) & EIM_CS5WCR1_WCSN_MASK) +#define EIM_CS5WCR1_WCSA_MASK (0x38U) +#define EIM_CS5WCR1_WCSA_SHIFT (3U) +#define EIM_CS5WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WCSA_SHIFT)) & EIM_CS5WCR1_WCSA_MASK) +#define EIM_CS5WCR1_WEN_MASK (0x1C0U) +#define EIM_CS5WCR1_WEN_SHIFT (6U) +#define EIM_CS5WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WEN_SHIFT)) & EIM_CS5WCR1_WEN_MASK) +#define EIM_CS5WCR1_WEA_MASK (0xE00U) +#define EIM_CS5WCR1_WEA_SHIFT (9U) +#define EIM_CS5WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WEA_SHIFT)) & EIM_CS5WCR1_WEA_MASK) +#define EIM_CS5WCR1_WBEN_MASK (0x7000U) +#define EIM_CS5WCR1_WBEN_SHIFT (12U) +#define EIM_CS5WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBEN_SHIFT)) & EIM_CS5WCR1_WBEN_MASK) +#define EIM_CS5WCR1_WBEA_MASK (0x38000U) +#define EIM_CS5WCR1_WBEA_SHIFT (15U) +#define EIM_CS5WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBEA_SHIFT)) & EIM_CS5WCR1_WBEA_MASK) +#define EIM_CS5WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS5WCR1_WADVN_SHIFT (18U) +#define EIM_CS5WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WADVN_SHIFT)) & EIM_CS5WCR1_WADVN_MASK) +#define EIM_CS5WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS5WCR1_WADVA_SHIFT (21U) +#define EIM_CS5WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WADVA_SHIFT)) & EIM_CS5WCR1_WADVA_MASK) +#define EIM_CS5WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS5WCR1_WWSC_SHIFT (24U) +#define EIM_CS5WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WWSC_SHIFT)) & EIM_CS5WCR1_WWSC_MASK) +#define EIM_CS5WCR1_WBED_MASK (0x40000000U) +#define EIM_CS5WCR1_WBED_SHIFT (30U) +#define EIM_CS5WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBED_SHIFT)) & EIM_CS5WCR1_WBED_MASK) +#define EIM_CS5WCR1_WAL_MASK (0x80000000U) +#define EIM_CS5WCR1_WAL_SHIFT (31U) +#define EIM_CS5WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WAL_SHIFT)) & EIM_CS5WCR1_WAL_MASK) + +/*! @name CS5WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS5WCR2_WBCDD_MASK (0x1U) +#define EIM_CS5WCR2_WBCDD_SHIFT (0U) +#define EIM_CS5WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR2_WBCDD_SHIFT)) & EIM_CS5WCR2_WBCDD_MASK) + +/*! @name WCR - EIM Configuration Register */ +#define EIM_WCR_BCM_MASK (0x1U) +#define EIM_WCR_BCM_SHIFT (0U) +#define EIM_WCR_BCM(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_BCM_SHIFT)) & EIM_WCR_BCM_MASK) +#define EIM_WCR_GBCD_MASK (0x6U) +#define EIM_WCR_GBCD_SHIFT (1U) +#define EIM_WCR_GBCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_GBCD_SHIFT)) & EIM_WCR_GBCD_MASK) +#define EIM_WCR_CONT_BCLK_SEL_MASK (0x8U) +#define EIM_WCR_CONT_BCLK_SEL_SHIFT (3U) +#define EIM_WCR_CONT_BCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_CONT_BCLK_SEL_SHIFT)) & EIM_WCR_CONT_BCLK_SEL_MASK) +#define EIM_WCR_INTEN_MASK (0x10U) +#define EIM_WCR_INTEN_SHIFT (4U) +#define EIM_WCR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_INTEN_SHIFT)) & EIM_WCR_INTEN_MASK) +#define EIM_WCR_INTPOL_MASK (0x20U) +#define EIM_WCR_INTPOL_SHIFT (5U) +#define EIM_WCR_INTPOL(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_INTPOL_SHIFT)) & EIM_WCR_INTPOL_MASK) +#define EIM_WCR_WDOG_EN_MASK (0x100U) +#define EIM_WCR_WDOG_EN_SHIFT (8U) +#define EIM_WCR_WDOG_EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_WDOG_EN_SHIFT)) & EIM_WCR_WDOG_EN_MASK) +#define EIM_WCR_WDOG_LIMIT_MASK (0x600U) +#define EIM_WCR_WDOG_LIMIT_SHIFT (9U) +#define EIM_WCR_WDOG_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_WDOG_LIMIT_SHIFT)) & EIM_WCR_WDOG_LIMIT_MASK) +#define EIM_WCR_FRUN_ACLK_EN_MASK (0x800U) +#define EIM_WCR_FRUN_ACLK_EN_SHIFT (11U) +#define EIM_WCR_FRUN_ACLK_EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_FRUN_ACLK_EN_SHIFT)) & EIM_WCR_FRUN_ACLK_EN_MASK) + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM base address */ +#define EIM_BASE (0x21B8000u) +/** Peripheral EIM base pointer */ +#define EIM ((EIM_Type *)EIM_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM } +/** Interrupt vectors for the EIM peripheral type */ +#define EIM_IRQS { WEIM_IRQn } + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */ + uint8_t RESERVED_9[20]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[56]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ + uint8_t RESERVED_12[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + uint8_t RESERVED_14[56]; + __I uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + __I uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_15[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + __I uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_16[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_17[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) + +/*! @name EIMR - Interrupt Mask Register */ +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) + +/*! @name RDAR - Receive Descriptor Active Register */ +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) + +/*! @name TDAR - Transmit Descriptor Active Register */ +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) + +/*! @name ECR - Ethernet Control Register */ +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) + +/*! @name MMFR - MII Management Frame Register */ +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) + +/*! @name MSCR - MII Speed Control Register */ +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) + +/*! @name MIBC - MIB Control Register */ +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) + +/*! @name RCR - Receive Control Register */ +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) + +/*! @name TCR - Transmit Control Register */ +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) + +/*! @name PALR - Physical Address Lower Register */ +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) + +/*! @name PAUR - Physical Address Upper Register */ +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) + +/*! @name OPD - Opcode/Pause Duration Register */ +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) + +/*! @name IALR - Descriptor Individual Lower Address Register */ +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) + +/*! @name GAUR - Descriptor Group Upper Address Register */ +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) + +/*! @name GALR - Descriptor Group Lower Address Register */ +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) + +/*! @name TFWR - Transmit FIFO Watermark Register */ +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) + +/*! @name RDSR - Receive Descriptor Ring Start Register */ +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) + +/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) + +/*! @name MRBR - Maximum Receive Buffer Size Register */ +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) + +/*! @name TIPG - Transmit Inter-Packet Gap */ +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) + +/*! @name FTRL - Frame Truncation Length */ +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) + +/*! @name TACC - Transmit Accelerator Function Configuration */ +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) + +/*! @name RACC - Receive Accelerator Function Configuration */ +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) + +/*! @name ATCR - Adjustable Timer Control Register */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) + +/*! @name ATVR - Timer Value Register */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) + +/*! @name ATOFF - Timer Offset Register */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) + +/*! @name ATPER - Timer Period Register */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) + +/*! @name ATCOR - Timer Correction Register */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) + +/*! @name ATINC - Time-Stamping Clock Period Register */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) + +/*! @name TGSR - Timer Global Status Register */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) + +/*! @name TCSR - Timer Control Status Register */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +#define ENET_TCSR_TPWC_MASK (0xF800U) +#define ENET_TCSR_TPWC_SHIFT (11U) +#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET1 base address */ +#define ENET1_BASE (0x2188000u) +/** Peripheral ENET1 base pointer */ +#define ENET1 ((ENET_Type *)ENET1_BASE) +/** Peripheral ENET2 base address */ +#define ENET2_BASE (0x20B4000u) +/** Peripheral ENET2 base pointer */ +#define ENET2 ((ENET_Type *)ENET2_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { 0u, ENET1_BASE, ENET2_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1, ENET2 } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EPIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Peripheral_Access_Layer EPIT Peripheral Access Layer + * @{ + */ + +/** EPIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control register, offset: 0x0 */ + __IO uint32_t SR; /**< Status register, offset: 0x4 */ + __IO uint32_t LR; /**< Load register, offset: 0x8 */ + __IO uint32_t CMPR; /**< Compare register, offset: 0xC */ + __I uint32_t CNR; /**< Counter register, offset: 0x10 */ +} EPIT_Type; + +/* ---------------------------------------------------------------------------- + -- EPIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Register_Masks EPIT Register Masks + * @{ + */ + +/*! @name CR - Control register */ +#define EPIT_CR_EN_MASK (0x1U) +#define EPIT_CR_EN_SHIFT (0U) +#define EPIT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_EN_SHIFT)) & EPIT_CR_EN_MASK) +#define EPIT_CR_ENMOD_MASK (0x2U) +#define EPIT_CR_ENMOD_SHIFT (1U) +#define EPIT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_ENMOD_SHIFT)) & EPIT_CR_ENMOD_MASK) +#define EPIT_CR_OCIEN_MASK (0x4U) +#define EPIT_CR_OCIEN_SHIFT (2U) +#define EPIT_CR_OCIEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_OCIEN_SHIFT)) & EPIT_CR_OCIEN_MASK) +#define EPIT_CR_RLD_MASK (0x8U) +#define EPIT_CR_RLD_SHIFT (3U) +#define EPIT_CR_RLD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_RLD_SHIFT)) & EPIT_CR_RLD_MASK) +#define EPIT_CR_PRESCALAR_MASK (0xFFF0U) +#define EPIT_CR_PRESCALAR_SHIFT (4U) +#define EPIT_CR_PRESCALAR(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_PRESCALAR_SHIFT)) & EPIT_CR_PRESCALAR_MASK) +#define EPIT_CR_SWR_MASK (0x10000U) +#define EPIT_CR_SWR_SHIFT (16U) +#define EPIT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_SWR_SHIFT)) & EPIT_CR_SWR_MASK) +#define EPIT_CR_IOVW_MASK (0x20000U) +#define EPIT_CR_IOVW_SHIFT (17U) +#define EPIT_CR_IOVW(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_IOVW_SHIFT)) & EPIT_CR_IOVW_MASK) +#define EPIT_CR_DBGEN_MASK (0x40000U) +#define EPIT_CR_DBGEN_SHIFT (18U) +#define EPIT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_DBGEN_SHIFT)) & EPIT_CR_DBGEN_MASK) +#define EPIT_CR_WAITEN_MASK (0x80000U) +#define EPIT_CR_WAITEN_SHIFT (19U) +#define EPIT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_WAITEN_SHIFT)) & EPIT_CR_WAITEN_MASK) +#define EPIT_CR_STOPEN_MASK (0x200000U) +#define EPIT_CR_STOPEN_SHIFT (21U) +#define EPIT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_STOPEN_SHIFT)) & EPIT_CR_STOPEN_MASK) +#define EPIT_CR_OM_MASK (0xC00000U) +#define EPIT_CR_OM_SHIFT (22U) +#define EPIT_CR_OM(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_OM_SHIFT)) & EPIT_CR_OM_MASK) +#define EPIT_CR_CLKSRC_MASK (0x3000000U) +#define EPIT_CR_CLKSRC_SHIFT (24U) +#define EPIT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_CLKSRC_SHIFT)) & EPIT_CR_CLKSRC_MASK) + +/*! @name SR - Status register */ +#define EPIT_SR_OCIF_MASK (0x1U) +#define EPIT_SR_OCIF_SHIFT (0U) +#define EPIT_SR_OCIF(x) (((uint32_t)(((uint32_t)(x)) << EPIT_SR_OCIF_SHIFT)) & EPIT_SR_OCIF_MASK) + +/*! @name LR - Load register */ +#define EPIT_LR_LOAD_MASK (0xFFFFFFFFU) +#define EPIT_LR_LOAD_SHIFT (0U) +#define EPIT_LR_LOAD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_LR_LOAD_SHIFT)) & EPIT_LR_LOAD_MASK) + +/*! @name CMPR - Compare register */ +#define EPIT_CMPR_COMPARE_MASK (0xFFFFFFFFU) +#define EPIT_CMPR_COMPARE_SHIFT (0U) +#define EPIT_CMPR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CMPR_COMPARE_SHIFT)) & EPIT_CMPR_COMPARE_MASK) + +/*! @name CNR - Counter register */ +#define EPIT_CNR_COUNT_MASK (0xFFFFFFFFU) +#define EPIT_CNR_COUNT_SHIFT (0U) +#define EPIT_CNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CNR_COUNT_SHIFT)) & EPIT_CNR_COUNT_MASK) + + +/*! + * @} + */ /* end of group EPIT_Register_Masks */ + + +/* EPIT - Peripheral instance base addresses */ +/** Peripheral EPIT1 base address */ +#define EPIT1_BASE (0x20D0000u) +/** Peripheral EPIT1 base pointer */ +#define EPIT1 ((EPIT_Type *)EPIT1_BASE) +/** Peripheral EPIT2 base address */ +#define EPIT2_BASE (0x20D4000u) +/** Peripheral EPIT2 base pointer */ +#define EPIT2 ((EPIT_Type *)EPIT2_BASE) +/** Array initializer of EPIT peripheral base addresses */ +#define EPIT_BASE_ADDRS { 0u, EPIT1_BASE, EPIT2_BASE } +/** Array initializer of EPIT peripheral base pointers */ +#define EPIT_BASE_PTRS { (EPIT_Type *)0u, EPIT1, EPIT2 } +/** Interrupt vectors for the EPIT peripheral type */ +#define EPIT_IRQS { NotAvail_IRQn, EPIT1_IRQn, EPIT2_IRQn } + +/*! + * @} + */ /* end of group EPIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ESAI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer + * @{ + */ + +/** ESAI - Register Layout Typedef */ +typedef struct { + __O uint32_t ETDR; /**< ESAI Transmit Data Register, offset: 0x0 */ + __I uint32_t ERDR; /**< ESAI Receive Data Register, offset: 0x4 */ + __IO uint32_t ECR; /**< ESAI Control Register, offset: 0x8 */ + __I uint32_t ESR; /**< ESAI Status Register, offset: 0xC */ + __IO uint32_t TFCR; /**< Transmit FIFO Configuration Register, offset: 0x10 */ + __I uint32_t TFSR; /**< Transmit FIFO Status Register, offset: 0x14 */ + __IO uint32_t RFCR; /**< Receive FIFO Configuration Register, offset: 0x18 */ + __I uint32_t RFSR; /**< Receive FIFO Status Register, offset: 0x1C */ + uint8_t RESERVED_0[96]; + __IO uint32_t TX[6]; /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */ + __IO uint32_t TSR; /**< ESAI Transmit Slot Register, offset: 0x98 */ + uint8_t RESERVED_1[4]; + __I uint32_t RX[4]; /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __I uint32_t SAISR; /**< Serial Audio Interface Status Register, offset: 0xCC */ + __IO uint32_t SAICR; /**< Serial Audio Interface Control Register, offset: 0xD0 */ + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xD4 */ + __IO uint32_t TCCR; /**< Transmit Clock Control Register, offset: 0xD8 */ + __IO uint32_t RCR; /**< Receive Control Register, offset: 0xDC */ + __IO uint32_t RCCR; /**< Receive Clock Control Register, offset: 0xE0 */ + __IO uint32_t TSMA; /**< Transmit Slot Mask Register A, offset: 0xE4 */ + __IO uint32_t TSMB; /**< Transmit Slot Mask Register B, offset: 0xE8 */ + __IO uint32_t RSMA; /**< Receive Slot Mask Register A, offset: 0xEC */ + __IO uint32_t RSMB; /**< Receive Slot Mask Register B, offset: 0xF0 */ + uint8_t RESERVED_3[4]; + __IO uint32_t PRRC; /**< Port C Direction Register, offset: 0xF8 */ + __IO uint32_t PCRC; /**< Port C Control Register, offset: 0xFC */ +} ESAI_Type; + +/* ---------------------------------------------------------------------------- + -- ESAI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Register_Masks ESAI Register Masks + * @{ + */ + +/*! @name ETDR - ESAI Transmit Data Register */ +#define ESAI_ETDR_ETDR_MASK (0xFFFFFFFFU) +#define ESAI_ETDR_ETDR_SHIFT (0U) +#define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ETDR_ETDR_SHIFT)) & ESAI_ETDR_ETDR_MASK) + +/*! @name ERDR - ESAI Receive Data Register */ +#define ESAI_ERDR_ERDR_MASK (0xFFFFFFFFU) +#define ESAI_ERDR_ERDR_SHIFT (0U) +#define ESAI_ERDR_ERDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ERDR_ERDR_SHIFT)) & ESAI_ERDR_ERDR_MASK) + +/*! @name ECR - ESAI Control Register */ +#define ESAI_ECR_ESAIEN_MASK (0x1U) +#define ESAI_ECR_ESAIEN_SHIFT (0U) +#define ESAI_ECR_ESAIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ESAIEN_SHIFT)) & ESAI_ECR_ESAIEN_MASK) +#define ESAI_ECR_ERST_MASK (0x2U) +#define ESAI_ECR_ERST_SHIFT (1U) +#define ESAI_ECR_ERST(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERST_SHIFT)) & ESAI_ECR_ERST_MASK) +#define ESAI_ECR_ERO_MASK (0x10000U) +#define ESAI_ECR_ERO_SHIFT (16U) +#define ESAI_ECR_ERO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERO_SHIFT)) & ESAI_ECR_ERO_MASK) +#define ESAI_ECR_ERI_MASK (0x20000U) +#define ESAI_ECR_ERI_SHIFT (17U) +#define ESAI_ECR_ERI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERI_SHIFT)) & ESAI_ECR_ERI_MASK) +#define ESAI_ECR_ETO_MASK (0x40000U) +#define ESAI_ECR_ETO_SHIFT (18U) +#define ESAI_ECR_ETO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETO_SHIFT)) & ESAI_ECR_ETO_MASK) +#define ESAI_ECR_ETI_MASK (0x80000U) +#define ESAI_ECR_ETI_SHIFT (19U) +#define ESAI_ECR_ETI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETI_SHIFT)) & ESAI_ECR_ETI_MASK) + +/*! @name ESR - ESAI Status Register */ +#define ESAI_ESR_RD_MASK (0x1U) +#define ESAI_ESR_RD_SHIFT (0U) +#define ESAI_ESR_RD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RD_SHIFT)) & ESAI_ESR_RD_MASK) +#define ESAI_ESR_RED_MASK (0x2U) +#define ESAI_ESR_RED_SHIFT (1U) +#define ESAI_ESR_RED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RED_SHIFT)) & ESAI_ESR_RED_MASK) +#define ESAI_ESR_RDE_MASK (0x4U) +#define ESAI_ESR_RDE_SHIFT (2U) +#define ESAI_ESR_RDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RDE_SHIFT)) & ESAI_ESR_RDE_MASK) +#define ESAI_ESR_RLS_MASK (0x8U) +#define ESAI_ESR_RLS_SHIFT (3U) +#define ESAI_ESR_RLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RLS_SHIFT)) & ESAI_ESR_RLS_MASK) +#define ESAI_ESR_TD_MASK (0x10U) +#define ESAI_ESR_TD_SHIFT (4U) +#define ESAI_ESR_TD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TD_SHIFT)) & ESAI_ESR_TD_MASK) +#define ESAI_ESR_TED_MASK (0x20U) +#define ESAI_ESR_TED_SHIFT (5U) +#define ESAI_ESR_TED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TED_SHIFT)) & ESAI_ESR_TED_MASK) +#define ESAI_ESR_TDE_MASK (0x40U) +#define ESAI_ESR_TDE_SHIFT (6U) +#define ESAI_ESR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TDE_SHIFT)) & ESAI_ESR_TDE_MASK) +#define ESAI_ESR_TLS_MASK (0x80U) +#define ESAI_ESR_TLS_SHIFT (7U) +#define ESAI_ESR_TLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TLS_SHIFT)) & ESAI_ESR_TLS_MASK) +#define ESAI_ESR_TFE_MASK (0x100U) +#define ESAI_ESR_TFE_SHIFT (8U) +#define ESAI_ESR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TFE_SHIFT)) & ESAI_ESR_TFE_MASK) +#define ESAI_ESR_RFF_MASK (0x200U) +#define ESAI_ESR_RFF_SHIFT (9U) +#define ESAI_ESR_RFF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RFF_SHIFT)) & ESAI_ESR_RFF_MASK) +#define ESAI_ESR_TINIT_MASK (0x400U) +#define ESAI_ESR_TINIT_SHIFT (10U) +#define ESAI_ESR_TINIT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TINIT_SHIFT)) & ESAI_ESR_TINIT_MASK) + +/*! @name TFCR - Transmit FIFO Configuration Register */ +#define ESAI_TFCR_TFE_MASK (0x1U) +#define ESAI_TFCR_TFE_SHIFT (0U) +#define ESAI_TFCR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFE_SHIFT)) & ESAI_TFCR_TFE_MASK) +#define ESAI_TFCR_TFR_MASK (0x2U) +#define ESAI_TFCR_TFR_SHIFT (1U) +#define ESAI_TFCR_TFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFR_SHIFT)) & ESAI_TFCR_TFR_MASK) +#define ESAI_TFCR_TE0_MASK (0x4U) +#define ESAI_TFCR_TE0_SHIFT (2U) +#define ESAI_TFCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE0_SHIFT)) & ESAI_TFCR_TE0_MASK) +#define ESAI_TFCR_TE1_MASK (0x8U) +#define ESAI_TFCR_TE1_SHIFT (3U) +#define ESAI_TFCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE1_SHIFT)) & ESAI_TFCR_TE1_MASK) +#define ESAI_TFCR_TE2_MASK (0x10U) +#define ESAI_TFCR_TE2_SHIFT (4U) +#define ESAI_TFCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE2_SHIFT)) & ESAI_TFCR_TE2_MASK) +#define ESAI_TFCR_TE3_MASK (0x20U) +#define ESAI_TFCR_TE3_SHIFT (5U) +#define ESAI_TFCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE3_SHIFT)) & ESAI_TFCR_TE3_MASK) +#define ESAI_TFCR_TE4_MASK (0x40U) +#define ESAI_TFCR_TE4_SHIFT (6U) +#define ESAI_TFCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE4_SHIFT)) & ESAI_TFCR_TE4_MASK) +#define ESAI_TFCR_TE5_MASK (0x80U) +#define ESAI_TFCR_TE5_SHIFT (7U) +#define ESAI_TFCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE5_SHIFT)) & ESAI_TFCR_TE5_MASK) +#define ESAI_TFCR_TFWM_MASK (0xFF00U) +#define ESAI_TFCR_TFWM_SHIFT (8U) +#define ESAI_TFCR_TFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFWM_SHIFT)) & ESAI_TFCR_TFWM_MASK) +#define ESAI_TFCR_TWA_MASK (0x70000U) +#define ESAI_TFCR_TWA_SHIFT (16U) +#define ESAI_TFCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TWA_SHIFT)) & ESAI_TFCR_TWA_MASK) +#define ESAI_TFCR_TIEN_MASK (0x80000U) +#define ESAI_TFCR_TIEN_SHIFT (19U) +#define ESAI_TFCR_TIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TIEN_SHIFT)) & ESAI_TFCR_TIEN_MASK) +#define ESAI_TFCR_TAENB_MASK (0x100000U) +#define ESAI_TFCR_TAENB_SHIFT (20U) +#define ESAI_TFCR_TAENB(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TAENB_SHIFT)) & ESAI_TFCR_TAENB_MASK) +#define ESAI_TFCR_TFIN_MASK (0x200000U) +#define ESAI_TFCR_TFIN_SHIFT (21U) +#define ESAI_TFCR_TFIN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFIN_SHIFT)) & ESAI_TFCR_TFIN_MASK) + +/*! @name TFSR - Transmit FIFO Status Register */ +#define ESAI_TFSR_TFCNT_MASK (0xFFU) +#define ESAI_TFSR_TFCNT_SHIFT (0U) +#define ESAI_TFSR_TFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_TFCNT_SHIFT)) & ESAI_TFSR_TFCNT_MASK) +#define ESAI_TFSR_NTFI_MASK (0x700U) +#define ESAI_TFSR_NTFI_SHIFT (8U) +#define ESAI_TFSR_NTFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFI_SHIFT)) & ESAI_TFSR_NTFI_MASK) +#define ESAI_TFSR_NTFO_MASK (0x7000U) +#define ESAI_TFSR_NTFO_SHIFT (12U) +#define ESAI_TFSR_NTFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFO_SHIFT)) & ESAI_TFSR_NTFO_MASK) + +/*! @name RFCR - Receive FIFO Configuration Register */ +#define ESAI_RFCR_RFE_MASK (0x1U) +#define ESAI_RFCR_RFE_SHIFT (0U) +#define ESAI_RFCR_RFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFE_SHIFT)) & ESAI_RFCR_RFE_MASK) +#define ESAI_RFCR_RFR_MASK (0x2U) +#define ESAI_RFCR_RFR_SHIFT (1U) +#define ESAI_RFCR_RFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFR_SHIFT)) & ESAI_RFCR_RFR_MASK) +#define ESAI_RFCR_RE0_MASK (0x4U) +#define ESAI_RFCR_RE0_SHIFT (2U) +#define ESAI_RFCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE0_SHIFT)) & ESAI_RFCR_RE0_MASK) +#define ESAI_RFCR_RE1_MASK (0x8U) +#define ESAI_RFCR_RE1_SHIFT (3U) +#define ESAI_RFCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE1_SHIFT)) & ESAI_RFCR_RE1_MASK) +#define ESAI_RFCR_RE2_MASK (0x10U) +#define ESAI_RFCR_RE2_SHIFT (4U) +#define ESAI_RFCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE2_SHIFT)) & ESAI_RFCR_RE2_MASK) +#define ESAI_RFCR_RE3_MASK (0x20U) +#define ESAI_RFCR_RE3_SHIFT (5U) +#define ESAI_RFCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE3_SHIFT)) & ESAI_RFCR_RE3_MASK) +#define ESAI_RFCR_RFWM_MASK (0xFF00U) +#define ESAI_RFCR_RFWM_SHIFT (8U) +#define ESAI_RFCR_RFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFWM_SHIFT)) & ESAI_RFCR_RFWM_MASK) +#define ESAI_RFCR_RWA_MASK (0x70000U) +#define ESAI_RFCR_RWA_SHIFT (16U) +#define ESAI_RFCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RWA_SHIFT)) & ESAI_RFCR_RWA_MASK) +#define ESAI_RFCR_REXT_MASK (0x80000U) +#define ESAI_RFCR_REXT_SHIFT (19U) +#define ESAI_RFCR_REXT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_REXT_SHIFT)) & ESAI_RFCR_REXT_MASK) +#define ESAI_RFCR_RAENB_MASK (0x100000U) +#define ESAI_RFCR_RAENB_SHIFT (20U) +#define ESAI_RFCR_RAENB(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RAENB_SHIFT)) & ESAI_RFCR_RAENB_MASK) +#define ESAI_RFCR_RFIN_MASK (0x200000U) +#define ESAI_RFCR_RFIN_SHIFT (21U) +#define ESAI_RFCR_RFIN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFIN_SHIFT)) & ESAI_RFCR_RFIN_MASK) + +/*! @name RFSR - Receive FIFO Status Register */ +#define ESAI_RFSR_RFCNT_MASK (0xFFU) +#define ESAI_RFSR_RFCNT_SHIFT (0U) +#define ESAI_RFSR_RFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_RFCNT_SHIFT)) & ESAI_RFSR_RFCNT_MASK) +#define ESAI_RFSR_NRFO_MASK (0x300U) +#define ESAI_RFSR_NRFO_SHIFT (8U) +#define ESAI_RFSR_NRFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFO_SHIFT)) & ESAI_RFSR_NRFO_MASK) +#define ESAI_RFSR_NRFI_MASK (0x3000U) +#define ESAI_RFSR_NRFI_SHIFT (12U) +#define ESAI_RFSR_NRFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFI_SHIFT)) & ESAI_RFSR_NRFI_MASK) + +/*! @name TX - Transmit Data Register n */ +#define ESAI_TX_TXn_MASK (0xFFFFFFU) +#define ESAI_TX_TXn_SHIFT (0U) +#define ESAI_TX_TXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TX_TXn_SHIFT)) & ESAI_TX_TXn_MASK) + +/* The count of ESAI_TX */ +#define ESAI_TX_COUNT (6U) + +/*! @name TSR - ESAI Transmit Slot Register */ +#define ESAI_TSR_TSR_MASK (0xFFFFFFU) +#define ESAI_TSR_TSR_SHIFT (0U) +#define ESAI_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSR_TSR_SHIFT)) & ESAI_TSR_TSR_MASK) + +/*! @name RX - Receive Data Register n */ +#define ESAI_RX_RXn_MASK (0xFFFFFFU) +#define ESAI_RX_RXn_SHIFT (0U) +#define ESAI_RX_RXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RX_RXn_SHIFT)) & ESAI_RX_RXn_MASK) + +/* The count of ESAI_RX */ +#define ESAI_RX_COUNT (4U) + +/*! @name SAISR - Serial Audio Interface Status Register */ +#define ESAI_SAISR_IF0_MASK (0x1U) +#define ESAI_SAISR_IF0_SHIFT (0U) +#define ESAI_SAISR_IF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF0_SHIFT)) & ESAI_SAISR_IF0_MASK) +#define ESAI_SAISR_IF1_MASK (0x2U) +#define ESAI_SAISR_IF1_SHIFT (1U) +#define ESAI_SAISR_IF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF1_SHIFT)) & ESAI_SAISR_IF1_MASK) +#define ESAI_SAISR_IF2_MASK (0x4U) +#define ESAI_SAISR_IF2_SHIFT (2U) +#define ESAI_SAISR_IF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF2_SHIFT)) & ESAI_SAISR_IF2_MASK) +#define ESAI_SAISR_RFS_MASK (0x40U) +#define ESAI_SAISR_RFS_SHIFT (6U) +#define ESAI_SAISR_RFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RFS_SHIFT)) & ESAI_SAISR_RFS_MASK) +#define ESAI_SAISR_ROE_MASK (0x80U) +#define ESAI_SAISR_ROE_SHIFT (7U) +#define ESAI_SAISR_ROE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_ROE_SHIFT)) & ESAI_SAISR_ROE_MASK) +#define ESAI_SAISR_RDF_MASK (0x100U) +#define ESAI_SAISR_RDF_SHIFT (8U) +#define ESAI_SAISR_RDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RDF_SHIFT)) & ESAI_SAISR_RDF_MASK) +#define ESAI_SAISR_REDF_MASK (0x200U) +#define ESAI_SAISR_REDF_SHIFT (9U) +#define ESAI_SAISR_REDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_REDF_SHIFT)) & ESAI_SAISR_REDF_MASK) +#define ESAI_SAISR_RODF_MASK (0x400U) +#define ESAI_SAISR_RODF_SHIFT (10U) +#define ESAI_SAISR_RODF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RODF_SHIFT)) & ESAI_SAISR_RODF_MASK) +#define ESAI_SAISR_TFS_MASK (0x2000U) +#define ESAI_SAISR_TFS_SHIFT (13U) +#define ESAI_SAISR_TFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TFS_SHIFT)) & ESAI_SAISR_TFS_MASK) +#define ESAI_SAISR_TUE_MASK (0x4000U) +#define ESAI_SAISR_TUE_SHIFT (14U) +#define ESAI_SAISR_TUE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TUE_SHIFT)) & ESAI_SAISR_TUE_MASK) +#define ESAI_SAISR_TDE_MASK (0x8000U) +#define ESAI_SAISR_TDE_SHIFT (15U) +#define ESAI_SAISR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TDE_SHIFT)) & ESAI_SAISR_TDE_MASK) +#define ESAI_SAISR_TEDE_MASK (0x10000U) +#define ESAI_SAISR_TEDE_SHIFT (16U) +#define ESAI_SAISR_TEDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TEDE_SHIFT)) & ESAI_SAISR_TEDE_MASK) +#define ESAI_SAISR_TODFE_MASK (0x20000U) +#define ESAI_SAISR_TODFE_SHIFT (17U) +#define ESAI_SAISR_TODFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TODFE_SHIFT)) & ESAI_SAISR_TODFE_MASK) + +/*! @name SAICR - Serial Audio Interface Control Register */ +#define ESAI_SAICR_OF0_MASK (0x1U) +#define ESAI_SAICR_OF0_SHIFT (0U) +#define ESAI_SAICR_OF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF0_SHIFT)) & ESAI_SAICR_OF0_MASK) +#define ESAI_SAICR_OF1_MASK (0x2U) +#define ESAI_SAICR_OF1_SHIFT (1U) +#define ESAI_SAICR_OF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF1_SHIFT)) & ESAI_SAICR_OF1_MASK) +#define ESAI_SAICR_OF2_MASK (0x4U) +#define ESAI_SAICR_OF2_SHIFT (2U) +#define ESAI_SAICR_OF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF2_SHIFT)) & ESAI_SAICR_OF2_MASK) +#define ESAI_SAICR_SYN_MASK (0x40U) +#define ESAI_SAICR_SYN_SHIFT (6U) +#define ESAI_SAICR_SYN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_SYN_SHIFT)) & ESAI_SAICR_SYN_MASK) +#define ESAI_SAICR_TEBE_MASK (0x80U) +#define ESAI_SAICR_TEBE_SHIFT (7U) +#define ESAI_SAICR_TEBE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_TEBE_SHIFT)) & ESAI_SAICR_TEBE_MASK) +#define ESAI_SAICR_ALC_MASK (0x100U) +#define ESAI_SAICR_ALC_SHIFT (8U) +#define ESAI_SAICR_ALC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_ALC_SHIFT)) & ESAI_SAICR_ALC_MASK) + +/*! @name TCR - Transmit Control Register */ +#define ESAI_TCR_TE0_MASK (0x1U) +#define ESAI_TCR_TE0_SHIFT (0U) +#define ESAI_TCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE0_SHIFT)) & ESAI_TCR_TE0_MASK) +#define ESAI_TCR_TE1_MASK (0x2U) +#define ESAI_TCR_TE1_SHIFT (1U) +#define ESAI_TCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE1_SHIFT)) & ESAI_TCR_TE1_MASK) +#define ESAI_TCR_TE2_MASK (0x4U) +#define ESAI_TCR_TE2_SHIFT (2U) +#define ESAI_TCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE2_SHIFT)) & ESAI_TCR_TE2_MASK) +#define ESAI_TCR_TE3_MASK (0x8U) +#define ESAI_TCR_TE3_SHIFT (3U) +#define ESAI_TCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE3_SHIFT)) & ESAI_TCR_TE3_MASK) +#define ESAI_TCR_TE4_MASK (0x10U) +#define ESAI_TCR_TE4_SHIFT (4U) +#define ESAI_TCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE4_SHIFT)) & ESAI_TCR_TE4_MASK) +#define ESAI_TCR_TE5_MASK (0x20U) +#define ESAI_TCR_TE5_SHIFT (5U) +#define ESAI_TCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE5_SHIFT)) & ESAI_TCR_TE5_MASK) +#define ESAI_TCR_TSHFD_MASK (0x40U) +#define ESAI_TCR_TSHFD_SHIFT (6U) +#define ESAI_TCR_TSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSHFD_SHIFT)) & ESAI_TCR_TSHFD_MASK) +#define ESAI_TCR_TWA_MASK (0x80U) +#define ESAI_TCR_TWA_SHIFT (7U) +#define ESAI_TCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TWA_SHIFT)) & ESAI_TCR_TWA_MASK) +#define ESAI_TCR_TMOD_MASK (0x300U) +#define ESAI_TCR_TMOD_SHIFT (8U) +#define ESAI_TCR_TMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TMOD_SHIFT)) & ESAI_TCR_TMOD_MASK) +#define ESAI_TCR_TSWS_MASK (0x7C00U) +#define ESAI_TCR_TSWS_SHIFT (10U) +#define ESAI_TCR_TSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSWS_SHIFT)) & ESAI_TCR_TSWS_MASK) +#define ESAI_TCR_TFSL_MASK (0x8000U) +#define ESAI_TCR_TFSL_SHIFT (15U) +#define ESAI_TCR_TFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSL_SHIFT)) & ESAI_TCR_TFSL_MASK) +#define ESAI_TCR_TFSR_MASK (0x10000U) +#define ESAI_TCR_TFSR_SHIFT (16U) +#define ESAI_TCR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSR_SHIFT)) & ESAI_TCR_TFSR_MASK) +#define ESAI_TCR_PADC_MASK (0x20000U) +#define ESAI_TCR_PADC_SHIFT (17U) +#define ESAI_TCR_PADC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_PADC_SHIFT)) & ESAI_TCR_PADC_MASK) +#define ESAI_TCR_TPR_MASK (0x80000U) +#define ESAI_TCR_TPR_SHIFT (19U) +#define ESAI_TCR_TPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TPR_SHIFT)) & ESAI_TCR_TPR_MASK) +#define ESAI_TCR_TEIE_MASK (0x100000U) +#define ESAI_TCR_TEIE_SHIFT (20U) +#define ESAI_TCR_TEIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEIE_SHIFT)) & ESAI_TCR_TEIE_MASK) +#define ESAI_TCR_TEDIE_MASK (0x200000U) +#define ESAI_TCR_TEDIE_SHIFT (21U) +#define ESAI_TCR_TEDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEDIE_SHIFT)) & ESAI_TCR_TEDIE_MASK) +#define ESAI_TCR_TIE_MASK (0x400000U) +#define ESAI_TCR_TIE_SHIFT (22U) +#define ESAI_TCR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TIE_SHIFT)) & ESAI_TCR_TIE_MASK) +#define ESAI_TCR_TLIE_MASK (0x800000U) +#define ESAI_TCR_TLIE_SHIFT (23U) +#define ESAI_TCR_TLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TLIE_SHIFT)) & ESAI_TCR_TLIE_MASK) + +/*! @name TCCR - Transmit Clock Control Register */ +#define ESAI_TCCR_TPM_MASK (0xFFU) +#define ESAI_TCCR_TPM_SHIFT (0U) +#define ESAI_TCCR_TPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPM_SHIFT)) & ESAI_TCCR_TPM_MASK) +#define ESAI_TCCR_TPSR_MASK (0x100U) +#define ESAI_TCCR_TPSR_SHIFT (8U) +#define ESAI_TCCR_TPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPSR_SHIFT)) & ESAI_TCCR_TPSR_MASK) +#define ESAI_TCCR_TDC_MASK (0x3E00U) +#define ESAI_TCCR_TDC_SHIFT (9U) +#define ESAI_TCCR_TDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TDC_SHIFT)) & ESAI_TCCR_TDC_MASK) +#define ESAI_TCCR_TFP_MASK (0x3C000U) +#define ESAI_TCCR_TFP_SHIFT (14U) +#define ESAI_TCCR_TFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFP_SHIFT)) & ESAI_TCCR_TFP_MASK) +#define ESAI_TCCR_TCKP_MASK (0x40000U) +#define ESAI_TCCR_TCKP_SHIFT (18U) +#define ESAI_TCCR_TCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKP_SHIFT)) & ESAI_TCCR_TCKP_MASK) +#define ESAI_TCCR_TFSP_MASK (0x80000U) +#define ESAI_TCCR_TFSP_SHIFT (19U) +#define ESAI_TCCR_TFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSP_SHIFT)) & ESAI_TCCR_TFSP_MASK) +#define ESAI_TCCR_THCKP_MASK (0x100000U) +#define ESAI_TCCR_THCKP_SHIFT (20U) +#define ESAI_TCCR_THCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKP_SHIFT)) & ESAI_TCCR_THCKP_MASK) +#define ESAI_TCCR_TCKD_MASK (0x200000U) +#define ESAI_TCCR_TCKD_SHIFT (21U) +#define ESAI_TCCR_TCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKD_SHIFT)) & ESAI_TCCR_TCKD_MASK) +#define ESAI_TCCR_TFSD_MASK (0x400000U) +#define ESAI_TCCR_TFSD_SHIFT (22U) +#define ESAI_TCCR_TFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSD_SHIFT)) & ESAI_TCCR_TFSD_MASK) +#define ESAI_TCCR_THCKD_MASK (0x800000U) +#define ESAI_TCCR_THCKD_SHIFT (23U) +#define ESAI_TCCR_THCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKD_SHIFT)) & ESAI_TCCR_THCKD_MASK) + +/*! @name RCR - Receive Control Register */ +#define ESAI_RCR_RE0_MASK (0x1U) +#define ESAI_RCR_RE0_SHIFT (0U) +#define ESAI_RCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE0_SHIFT)) & ESAI_RCR_RE0_MASK) +#define ESAI_RCR_RE1_MASK (0x2U) +#define ESAI_RCR_RE1_SHIFT (1U) +#define ESAI_RCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE1_SHIFT)) & ESAI_RCR_RE1_MASK) +#define ESAI_RCR_RE2_MASK (0x4U) +#define ESAI_RCR_RE2_SHIFT (2U) +#define ESAI_RCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE2_SHIFT)) & ESAI_RCR_RE2_MASK) +#define ESAI_RCR_RE3_MASK (0x8U) +#define ESAI_RCR_RE3_SHIFT (3U) +#define ESAI_RCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE3_SHIFT)) & ESAI_RCR_RE3_MASK) +#define ESAI_RCR_RSHFD_MASK (0x40U) +#define ESAI_RCR_RSHFD_SHIFT (6U) +#define ESAI_RCR_RSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSHFD_SHIFT)) & ESAI_RCR_RSHFD_MASK) +#define ESAI_RCR_RWA_MASK (0x80U) +#define ESAI_RCR_RWA_SHIFT (7U) +#define ESAI_RCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RWA_SHIFT)) & ESAI_RCR_RWA_MASK) +#define ESAI_RCR_RMOD_MASK (0x300U) +#define ESAI_RCR_RMOD_SHIFT (8U) +#define ESAI_RCR_RMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RMOD_SHIFT)) & ESAI_RCR_RMOD_MASK) +#define ESAI_RCR_RSWS_MASK (0x7C00U) +#define ESAI_RCR_RSWS_SHIFT (10U) +#define ESAI_RCR_RSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSWS_SHIFT)) & ESAI_RCR_RSWS_MASK) +#define ESAI_RCR_RFSL_MASK (0x8000U) +#define ESAI_RCR_RFSL_SHIFT (15U) +#define ESAI_RCR_RFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSL_SHIFT)) & ESAI_RCR_RFSL_MASK) +#define ESAI_RCR_RFSR_MASK (0x10000U) +#define ESAI_RCR_RFSR_SHIFT (16U) +#define ESAI_RCR_RFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSR_SHIFT)) & ESAI_RCR_RFSR_MASK) +#define ESAI_RCR_RPR_MASK (0x80000U) +#define ESAI_RCR_RPR_SHIFT (19U) +#define ESAI_RCR_RPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RPR_SHIFT)) & ESAI_RCR_RPR_MASK) +#define ESAI_RCR_REIE_MASK (0x100000U) +#define ESAI_RCR_REIE_SHIFT (20U) +#define ESAI_RCR_REIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REIE_SHIFT)) & ESAI_RCR_REIE_MASK) +#define ESAI_RCR_REDIE_MASK (0x200000U) +#define ESAI_RCR_REDIE_SHIFT (21U) +#define ESAI_RCR_REDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REDIE_SHIFT)) & ESAI_RCR_REDIE_MASK) +#define ESAI_RCR_RIE_MASK (0x400000U) +#define ESAI_RCR_RIE_SHIFT (22U) +#define ESAI_RCR_RIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RIE_SHIFT)) & ESAI_RCR_RIE_MASK) +#define ESAI_RCR_RLIE_MASK (0x800000U) +#define ESAI_RCR_RLIE_SHIFT (23U) +#define ESAI_RCR_RLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RLIE_SHIFT)) & ESAI_RCR_RLIE_MASK) + +/*! @name RCCR - Receive Clock Control Register */ +#define ESAI_RCCR_RPM_MASK (0xFFU) +#define ESAI_RCCR_RPM_SHIFT (0U) +#define ESAI_RCCR_RPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPM_SHIFT)) & ESAI_RCCR_RPM_MASK) +#define ESAI_RCCR_RPSR_MASK (0x100U) +#define ESAI_RCCR_RPSR_SHIFT (8U) +#define ESAI_RCCR_RPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPSR_SHIFT)) & ESAI_RCCR_RPSR_MASK) +#define ESAI_RCCR_RDC_MASK (0x3E00U) +#define ESAI_RCCR_RDC_SHIFT (9U) +#define ESAI_RCCR_RDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RDC_SHIFT)) & ESAI_RCCR_RDC_MASK) +#define ESAI_RCCR_RFP_MASK (0x3C000U) +#define ESAI_RCCR_RFP_SHIFT (14U) +#define ESAI_RCCR_RFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFP_SHIFT)) & ESAI_RCCR_RFP_MASK) +#define ESAI_RCCR_RCKP_MASK (0x40000U) +#define ESAI_RCCR_RCKP_SHIFT (18U) +#define ESAI_RCCR_RCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKP_SHIFT)) & ESAI_RCCR_RCKP_MASK) +#define ESAI_RCCR_RFSP_MASK (0x80000U) +#define ESAI_RCCR_RFSP_SHIFT (19U) +#define ESAI_RCCR_RFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSP_SHIFT)) & ESAI_RCCR_RFSP_MASK) +#define ESAI_RCCR_RHCKP_MASK (0x100000U) +#define ESAI_RCCR_RHCKP_SHIFT (20U) +#define ESAI_RCCR_RHCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKP_SHIFT)) & ESAI_RCCR_RHCKP_MASK) +#define ESAI_RCCR_RCKD_MASK (0x200000U) +#define ESAI_RCCR_RCKD_SHIFT (21U) +#define ESAI_RCCR_RCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKD_SHIFT)) & ESAI_RCCR_RCKD_MASK) +#define ESAI_RCCR_RFSD_MASK (0x400000U) +#define ESAI_RCCR_RFSD_SHIFT (22U) +#define ESAI_RCCR_RFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSD_SHIFT)) & ESAI_RCCR_RFSD_MASK) +#define ESAI_RCCR_RHCKD_MASK (0x800000U) +#define ESAI_RCCR_RHCKD_SHIFT (23U) +#define ESAI_RCCR_RHCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKD_SHIFT)) & ESAI_RCCR_RHCKD_MASK) + +/*! @name TSMA - Transmit Slot Mask Register A */ +#define ESAI_TSMA_TS_MASK (0xFFFFU) +#define ESAI_TSMA_TS_SHIFT (0U) +#define ESAI_TSMA_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMA_TS_SHIFT)) & ESAI_TSMA_TS_MASK) + +/*! @name TSMB - Transmit Slot Mask Register B */ +#define ESAI_TSMB_TS_MASK (0xFFFFU) +#define ESAI_TSMB_TS_SHIFT (0U) +#define ESAI_TSMB_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMB_TS_SHIFT)) & ESAI_TSMB_TS_MASK) + +/*! @name RSMA - Receive Slot Mask Register A */ +#define ESAI_RSMA_RS_MASK (0xFFFFU) +#define ESAI_RSMA_RS_SHIFT (0U) +#define ESAI_RSMA_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMA_RS_SHIFT)) & ESAI_RSMA_RS_MASK) + +/*! @name RSMB - Receive Slot Mask Register B */ +#define ESAI_RSMB_RS_MASK (0xFFFFU) +#define ESAI_RSMB_RS_SHIFT (0U) +#define ESAI_RSMB_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMB_RS_SHIFT)) & ESAI_RSMB_RS_MASK) + +/*! @name PRRC - Port C Direction Register */ +#define ESAI_PRRC_PDC_MASK (0xFFFU) +#define ESAI_PRRC_PDC_SHIFT (0U) +#define ESAI_PRRC_PDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PRRC_PDC_SHIFT)) & ESAI_PRRC_PDC_MASK) + +/*! @name PCRC - Port C Control Register */ +#define ESAI_PCRC_PC_MASK (0xFFFU) +#define ESAI_PCRC_PC_SHIFT (0U) +#define ESAI_PCRC_PC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PCRC_PC_SHIFT)) & ESAI_PCRC_PC_MASK) + + +/*! + * @} + */ /* end of group ESAI_Register_Masks */ + + +/* ESAI - Peripheral instance base addresses */ +/** Peripheral ESAI base address */ +#define ESAI_BASE (0x2024000u) +/** Peripheral ESAI base pointer */ +#define ESAI ((ESAI_Type *)ESAI_BASE) +/** Array initializer of ESAI peripheral base addresses */ +#define ESAI_BASE_ADDRS { ESAI_BASE } +/** Array initializer of ESAI peripheral base pointers */ +#define ESAI_BASE_PTRS { ESAI } +/** Interrupt vectors for the ESAI peripheral type */ +#define ESAI_IRQS { ESAI_IRQn } + +/*! + * @} + */ /* end of group ESAI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + __IO uint32_t PGR; /**< GPC Power Gating Register, offset: 0x4 */ + __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ + __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name CNTR - GPC Interface control register */ +#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) +#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) +#define GPC_CNTR_DISPLAY_PDN_REQ_MASK (0x10U) +#define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT (4U) +#define GPC_CNTR_DISPLAY_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_DISPLAY_PDN_REQ_SHIFT)) & GPC_CNTR_DISPLAY_PDN_REQ_MASK) +#define GPC_CNTR_DISPLAY_PUP_REQ_MASK (0x20U) +#define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT (5U) +#define GPC_CNTR_DISPLAY_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_DISPLAY_PUP_REQ_SHIFT)) & GPC_CNTR_DISPLAY_PUP_REQ_MASK) +#define GPC_CNTR_VADC_ANALOG_OFF_MASK (0x20000U) +#define GPC_CNTR_VADC_ANALOG_OFF_SHIFT (17U) +#define GPC_CNTR_VADC_ANALOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_VADC_ANALOG_OFF_SHIFT)) & GPC_CNTR_VADC_ANALOG_OFF_MASK) +#define GPC_CNTR_VADC_EXT_PWD_N_MASK (0x40000U) +#define GPC_CNTR_VADC_EXT_PWD_N_SHIFT (18U) +#define GPC_CNTR_VADC_EXT_PWD_N(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_VADC_EXT_PWD_N_SHIFT)) & GPC_CNTR_VADC_EXT_PWD_N_MASK) +#define GPC_CNTR_GPCIRQM_MASK (0x200000U) +#define GPC_CNTR_GPCIRQM_SHIFT (21U) +#define GPC_CNTR_GPCIRQM(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_GPCIRQM_SHIFT)) & GPC_CNTR_GPCIRQM_MASK) +#define GPC_CNTR_L2_PGE_MASK (0x400000U) +#define GPC_CNTR_L2_PGE_SHIFT (22U) +#define GPC_CNTR_L2_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_L2_PGE_SHIFT)) & GPC_CNTR_L2_PGE_MASK) + +/*! @name PGR - GPC Power Gating Register */ +#define GPC_PGR_DRCIC_MASK (0x60000000U) +#define GPC_PGR_DRCIC_SHIFT (29U) +#define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGR_DRCIC_SHIFT)) & GPC_PGR_DRCIC_MASK) + +/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR1_SHIFT (0U) +#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) +#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR2_SHIFT (0U) +#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) +#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR3_SHIFT (0U) +#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) +#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR4_SHIFT (0U) +#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) + +/* The count of GPC_IMR */ +#define GPC_IMR_COUNT (4U) + +/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR1_SHIFT (0U) +#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) +#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR2_SHIFT (0U) +#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) +#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR3_SHIFT (0U) +#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) +#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR4_SHIFT (0U) +#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) + +/* The count of GPC_ISR */ +#define GPC_ISR_COUNT (4U) + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x20DC000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) + +/*! @name GDIR - GPIO direction register */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) + +/*! @name PSR - GPIO pad status register */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) + +/*! @name IMR - GPIO interrupt mask register */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) + +/*! @name ISR - GPIO interrupt status register */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) + +/*! @name EDGE_SEL - GPIO edge select register */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x209C000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x20A0000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x20A4000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x20A8000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x20AC000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPMI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer + * @{ + */ + +/** GPMI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ + __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ + __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ + __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ + __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ + __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ + uint8_t RESERVED_2[12]; + __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */ + __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ + __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ + __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ + __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ + uint8_t RESERVED_8[12]; + __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */ + uint8_t RESERVED_9[12]; + __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ + uint8_t RESERVED_11[12]; + __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ + uint8_t RESERVED_13[12]; + __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */ + uint8_t RESERVED_14[12]; + __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ + uint8_t RESERVED_15[12]; + __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */ +} GPMI_Type; + +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/*! @name CTRL0 - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK) +#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK) +#define GPMI_CTRL0_CS_MASK (0x700000U) +#define GPMI_CTRL0_CS_SHIFT (20U) +#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK) +#define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK) +#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK) +#define GPMI_CTRL0_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_UDMA_SHIFT (26U) +#define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK) +#define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK) +#define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_RUN_SHIFT (29U) +#define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK) +#define GPMI_CTRL0_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK) +#define GPMI_CTRL0_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK) + +/*! @name CTRL0_SET - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK) +#define GPMI_CTRL0_SET_CS_MASK (0x700000U) +#define GPMI_CTRL0_SET_CS_SHIFT (20U) +#define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK) +#define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK) +#define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK) +#define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_SET_UDMA_SHIFT (26U) +#define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK) +#define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_SET_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK) +#define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_SET_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_SET_RUN_SHIFT (29U) +#define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK) +#define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK) +#define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SET_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK) + +/*! @name CTRL0_CLR - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK) +#define GPMI_CTRL0_CLR_CS_MASK (0x700000U) +#define GPMI_CTRL0_CLR_CS_SHIFT (20U) +#define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK) +#define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK) +#define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK) +#define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_CLR_UDMA_SHIFT (26U) +#define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK) +#define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_CLR_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_CLR_RUN_SHIFT (29U) +#define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK) +#define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK) +#define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK) + +/*! @name CTRL0_TOG - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK) +#define GPMI_CTRL0_TOG_CS_MASK (0x700000U) +#define GPMI_CTRL0_TOG_CS_SHIFT (20U) +#define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK) +#define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK) +#define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK) +#define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_TOG_UDMA_SHIFT (26U) +#define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK) +#define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_TOG_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_TOG_RUN_SHIFT (29U) +#define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK) +#define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK) +#define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK) + +/*! @name COMPARE - GPMI Compare Register Description */ +#define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU) +#define GPMI_COMPARE_REFERENCE_SHIFT (0U) +#define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK) +#define GPMI_COMPARE_MASK_MASK (0xFFFF0000U) +#define GPMI_COMPARE_MASK_SHIFT (16U) +#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK) + +/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD1_SHIFT)) & GPMI_ECCCTRL_RSVD1_MASK) +#define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK) +#define GPMI_ECCCTRL_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK) +#define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK) + +/*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_SET_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_SET_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD1_SHIFT)) & GPMI_ECCCTRL_SET_RSVD1_MASK) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK) +#define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK) +#define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK) + +/*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_CLR_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_CLR_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD1_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD1_MASK) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK) +#define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK) +#define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK) + +/*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_TOG_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_TOG_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD1_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD1_MASK) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK) +#define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK) +#define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK) + +/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */ +#define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU) +#define GPMI_ECCCOUNT_COUNT_SHIFT (0U) +#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK) +#define GPMI_ECCCOUNT_RSVD2_MASK (0xFFFF0000U) +#define GPMI_ECCCOUNT_RSVD2_SHIFT (16U) +#define GPMI_ECCCOUNT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RSVD2_SHIFT)) & GPMI_ECCCOUNT_RSVD2_MASK) + +/*! @name PAYLOAD - GPMI Payload Address Register Description */ +#define GPMI_PAYLOAD_RSVD0_MASK (0x3U) +#define GPMI_PAYLOAD_RSVD0_SHIFT (0U) +#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK) +#define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_PAYLOAD_ADDRESS_SHIFT (2U) +#define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK) + +/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */ +#define GPMI_AUXILIARY_RSVD0_MASK (0x3U) +#define GPMI_AUXILIARY_RSVD0_SHIFT (0U) +#define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK) +#define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_AUXILIARY_ADDRESS_SHIFT (2U) +#define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK) + +/*! @name CTRL1 - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK) +#define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK) +#define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK) +#define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK) +#define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK) +#define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK) +#define GPMI_CTRL1_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK) +#define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK) +#define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_SET - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_SET_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK) +#define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_SET_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_SET_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_SET_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_SET_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK) +#define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK) +#define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_SET_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK) +#define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_SET_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK) +#define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_SET_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_SET_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_SET_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SET_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK) +#define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_SET_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_SET_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_CLR - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_CLR_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK) +#define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CLR_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_CLR_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_CLR_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_CLR_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK) +#define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_CLR_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK) +#define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_CLR_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK) +#define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_CLR_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_CLR_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_CLR_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK) +#define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_CLR_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_TOG - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_TOG_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK) +#define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_TOG_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_TOG_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_TOG_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_TOG_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK) +#define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_TOG_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK) +#define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_TOG_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK) +#define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_TOG_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_TOG_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_TOG_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK) +#define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_TOG_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK) + +/*! @name TIMING0 - GPMI Timing Register 0 Description */ +#define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU) +#define GPMI_TIMING0_DATA_SETUP_SHIFT (0U) +#define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK) +#define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U) +#define GPMI_TIMING0_DATA_HOLD_SHIFT (8U) +#define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK) +#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U) +#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U) +#define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK) +#define GPMI_TIMING0_RSVD1_MASK (0xFF000000U) +#define GPMI_TIMING0_RSVD1_SHIFT (24U) +#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK) + +/*! @name TIMING1 - GPMI Timing Register 1 Description */ +#define GPMI_TIMING1_RSVD1_MASK (0xFFFFU) +#define GPMI_TIMING1_RSVD1_SHIFT (0U) +#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) + +/*! @name TIMING2 - GPMI Timing Register 2 Description */ +#define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU) +#define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U) +#define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK) +#define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U) +#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U) +#define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK) +#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U) +#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U) +#define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK) +#define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U) +#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U) +#define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK) +#define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U) +#define GPMI_TIMING2_CE_DELAY_SHIFT (16U) +#define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK) +#define GPMI_TIMING2_RSVD0_MASK (0xE00000U) +#define GPMI_TIMING2_RSVD0_SHIFT (21U) +#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK) +#define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U) +#define GPMI_TIMING2_READ_LATENCY_SHIFT (24U) +#define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK) +#define GPMI_TIMING2_TCR_MASK (0x18000000U) +#define GPMI_TIMING2_TCR_SHIFT (27U) +#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK) +#define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U) +#define GPMI_TIMING2_TRPSTH_SHIFT (29U) +#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK) + +/*! @name DATA - GPMI DMA Data Transfer Register Description */ +#define GPMI_DATA_DATA_MASK (0xFFFFFFFFU) +#define GPMI_DATA_DATA_SHIFT (0U) +#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK) + +/*! @name STAT - GPMI Status Register Description */ +#define GPMI_STAT_PRESENT_MASK (0x1U) +#define GPMI_STAT_PRESENT_SHIFT (0U) +#define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK) +#define GPMI_STAT_FIFO_FULL_MASK (0x2U) +#define GPMI_STAT_FIFO_FULL_SHIFT (1U) +#define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK) +#define GPMI_STAT_FIFO_EMPTY_MASK (0x4U) +#define GPMI_STAT_FIFO_EMPTY_SHIFT (2U) +#define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK) +#define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U) +#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U) +#define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK) +#define GPMI_STAT_ATA_IRQ_MASK (0x10U) +#define GPMI_STAT_ATA_IRQ_SHIFT (4U) +#define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK) +#define GPMI_STAT_RSVD1_MASK (0xE0U) +#define GPMI_STAT_RSVD1_SHIFT (5U) +#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK) +#define GPMI_STAT_DEV0_ERROR_MASK (0x100U) +#define GPMI_STAT_DEV0_ERROR_SHIFT (8U) +#define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK) +#define GPMI_STAT_DEV1_ERROR_MASK (0x200U) +#define GPMI_STAT_DEV1_ERROR_SHIFT (9U) +#define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK) +#define GPMI_STAT_DEV2_ERROR_MASK (0x400U) +#define GPMI_STAT_DEV2_ERROR_SHIFT (10U) +#define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK) +#define GPMI_STAT_DEV3_ERROR_MASK (0x800U) +#define GPMI_STAT_DEV3_ERROR_SHIFT (11U) +#define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK) +#define GPMI_STAT_DEV4_ERROR_MASK (0x1000U) +#define GPMI_STAT_DEV4_ERROR_SHIFT (12U) +#define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK) +#define GPMI_STAT_DEV5_ERROR_MASK (0x2000U) +#define GPMI_STAT_DEV5_ERROR_SHIFT (13U) +#define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK) +#define GPMI_STAT_DEV6_ERROR_MASK (0x4000U) +#define GPMI_STAT_DEV6_ERROR_SHIFT (14U) +#define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK) +#define GPMI_STAT_DEV7_ERROR_MASK (0x8000U) +#define GPMI_STAT_DEV7_ERROR_SHIFT (15U) +#define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK) +#define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U) +#define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U) +#define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK) +#define GPMI_STAT_READY_BUSY_MASK (0xFF000000U) +#define GPMI_STAT_READY_BUSY_SHIFT (24U) +#define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK) + +/*! @name DEBUG - GPMI Debug Information Register Description */ +#define GPMI_DEBUG_CMD_END_MASK (0xFFU) +#define GPMI_DEBUG_CMD_END_SHIFT (0U) +#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK) +#define GPMI_DEBUG_DMAREQ_MASK (0xFF00U) +#define GPMI_DEBUG_DMAREQ_SHIFT (8U) +#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK) +#define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U) +#define GPMI_DEBUG_DMA_SENSE_SHIFT (16U) +#define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK) +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U) +#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U) +#define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK) + +/*! @name VERSION - GPMI Version Register Description */ +#define GPMI_VERSION_STEP_MASK (0xFFFFU) +#define GPMI_VERSION_STEP_SHIFT (0U) +#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK) +#define GPMI_VERSION_MINOR_MASK (0xFF0000U) +#define GPMI_VERSION_MINOR_SHIFT (16U) +#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK) +#define GPMI_VERSION_MAJOR_MASK (0xFF000000U) +#define GPMI_VERSION_MAJOR_SHIFT (24U) +#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK) + +/*! @name DEBUG2 - GPMI Debug2 Information Register Description */ +#define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU) +#define GPMI_DEBUG2_RDN_TAP_SHIFT (0U) +#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK) +#define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U) +#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U) +#define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK) +#define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U) +#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U) +#define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK) +#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U) +#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U) +#define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK) +#define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U) +#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U) +#define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK) +#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U) +#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U) +#define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK) +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U) +#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U) +#define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK) +#define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U) +#define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U) +#define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK) +#define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U) +#define GPMI_DEBUG2_PIN_STATE_SHIFT (20U) +#define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK) +#define GPMI_DEBUG2_BUSY_MASK (0x800000U) +#define GPMI_DEBUG2_BUSY_SHIFT (23U) +#define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK) +#define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U) +#define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U) +#define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK) +#define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U) +#define GPMI_DEBUG2_RSVD1_SHIFT (28U) +#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK) + +/*! @name DEBUG3 - GPMI Debug3 Information Register Description */ +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU) +#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U) +#define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK) +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U) +#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U) +#define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK) + +/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */ +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */ +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */ +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK) +#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK) + +/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */ +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK) + + +/*! + * @} + */ /* end of group GPMI_Register_Masks */ + + +/* GPMI - Peripheral instance base addresses */ +/** Peripheral GPMI base address */ +#define GPMI_BASE (0x1806000u) +/** Peripheral GPMI base pointer */ +#define GPMI ((GPMI_Type *)GPMI_BASE) +/** Array initializer of GPMI peripheral base addresses */ +#define GPMI_BASE_ADDRS { GPMI_BASE } +/** Array initializer of GPMI peripheral base pointers */ +#define GPMI_BASE_PTRS { GPMI } +/** Interrupt vectors for the GPMI peripheral type */ +#define GPMI_IRQS { RAWNAND_GPMI_IRQn } + +/*! + * @} + */ /* end of group GPMI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) + +/*! @name PR - GPT Prescaler Register */ +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) + +/*! @name SR - GPT Status Register */ +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) + +/*! @name IR - GPT Interrupt Register */ +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x2098000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x20E8000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ + uint8_t RESERVED_0[2]; + __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ + uint8_t RESERVED_1[2]; + __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ + uint8_t RESERVED_2[2]; + __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ + uint8_t RESERVED_3[2]; + __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name IADR - I2C Address Register */ +#define I2C_IADR_ADR_MASK (0xFEU) +#define I2C_IADR_ADR_SHIFT (1U) +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK) + +/*! @name IFDR - I2C Frequency Divider Register */ +#define I2C_IFDR_IC_MASK (0x3FU) +#define I2C_IFDR_IC_SHIFT (0U) +#define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK) + +/*! @name I2CR - I2C Control Register */ +#define I2C_I2CR_RSTA_MASK (0x4U) +#define I2C_I2CR_RSTA_SHIFT (2U) +#define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK) +#define I2C_I2CR_TXAK_MASK (0x8U) +#define I2C_I2CR_TXAK_SHIFT (3U) +#define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK) +#define I2C_I2CR_MTX_MASK (0x10U) +#define I2C_I2CR_MTX_SHIFT (4U) +#define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK) +#define I2C_I2CR_MSTA_MASK (0x20U) +#define I2C_I2CR_MSTA_SHIFT (5U) +#define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK) +#define I2C_I2CR_IIEN_MASK (0x40U) +#define I2C_I2CR_IIEN_SHIFT (6U) +#define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK) +#define I2C_I2CR_IEN_MASK (0x80U) +#define I2C_I2CR_IEN_SHIFT (7U) +#define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK) + +/*! @name I2SR - I2C Status Register */ +#define I2C_I2SR_RXAK_MASK (0x1U) +#define I2C_I2SR_RXAK_SHIFT (0U) +#define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK) +#define I2C_I2SR_IIF_MASK (0x2U) +#define I2C_I2SR_IIF_SHIFT (1U) +#define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK) +#define I2C_I2SR_SRW_MASK (0x4U) +#define I2C_I2SR_SRW_SHIFT (2U) +#define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK) +#define I2C_I2SR_IAL_MASK (0x10U) +#define I2C_I2SR_IAL_SHIFT (4U) +#define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK) +#define I2C_I2SR_IBB_MASK (0x20U) +#define I2C_I2SR_IBB_SHIFT (5U) +#define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK) +#define I2C_I2SR_IAAS_MASK (0x40U) +#define I2C_I2SR_IAAS_SHIFT (6U) +#define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK) +#define I2C_I2SR_ICF_MASK (0x80U) +#define I2C_I2SR_ICF_SHIFT (7U) +#define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK) + +/*! @name I2DR - I2C Data I/O Register */ +#define I2C_I2DR_DATA_MASK (0xFFU) +#define I2C_I2DR_DATA_SHIFT (0U) +#define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK) + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x21A0000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x21A4000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x21A8000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x21F8000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[28]; + __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[28]; + __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name TCSR - SAI Transmit Control Register */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +#define I2S_TCR1_TFW_MASK (0x1FU) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0x10000U) +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) + +/*! @name TDR - SAI Transmit Data Register */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (1U) + +/*! @name TFR - SAI Transmit FIFO Register */ +#define I2S_TFR_RFP_MASK (0x3FU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0x3F0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (1U) + +/*! @name TMR - SAI Transmit Mask Register */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) + +/*! @name RCSR - SAI Receive Control Register */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +#define I2S_RCR1_RFW_MASK (0x1FU) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0x10000U) +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) + +/*! @name RDR - SAI Receive Data Register */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (1U) + +/*! @name RFR - SAI Receive FIFO Register */ +#define I2S_RFR_RFP_MASK (0x3FU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK (0x3F0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (1U) + +/*! @name RMR - SAI Receive Mask Register */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x2028000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +/** Peripheral I2S2 base address */ +#define I2S2_BASE (0x202C000u) +/** Peripheral I2S2 base pointer */ +#define I2S2 ((I2S_Type *)I2S2_BASE) +/** Peripheral I2S3 base address */ +#define I2S3_BASE (0x2030000u) +/** Peripheral I2S3 base pointer */ +#define I2S3 ((I2S_Type *)I2S3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, I2S1_BASE, I2S2_BASE, I2S3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, I2S1, I2S2, I2S3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[68]; + __IO uint32_t SW_MUX_CTL_PAD[112]; /**< SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register..SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register, array offset: 0x44, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD_DDR[34]; /**< SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register..SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register, array offset: 0x204, array step: 0x4 */ + uint8_t RESERVED_1[68]; + __IO uint32_t SW_PAD_CTL_PAD[112]; /**< SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register..SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register, array offset: 0x2D0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_GRP[10]; /**< SW_PAD_CTL_GRP_ADDDS SW GRP Register..SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register, array offset: 0x490, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[122]; /**< USB_OTG1_ID_SELECT_INPUT DAISY Register..USDHC2_WP_SELECT_INPUT DAISY Register, array offset: 0x4B8, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register..SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (112U) + +/*! @name SW_PAD_CTL_PAD_DDR - SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register..SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register */ +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_MASK (0x700U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_SHIFT (8U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_SHIFT (14U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK (0x20000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT (17U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_MASK (0xC0000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_SHIFT (18U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_MASK (0x300000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_SHIFT (20U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_MASK (0x3000000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_SHIFT (24U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_PAD_DDR */ +#define IOMUXC_SW_PAD_CTL_PAD_DDR_COUNT (34U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register..SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (112U) + +/*! @name SW_PAD_CTL_GRP - SW_PAD_CTL_GRP_ADDDS SW GRP Register..SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register */ +#define IOMUXC_SW_PAD_CTL_GRP_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_GRP_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_GRP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_GRP_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_GRP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_GRP_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_GRP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_GRP_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_GRP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_HYS_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_MASK (0x20000U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_SHIFT (17U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_MASK (0xC0000U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_SHIFT (18U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_GRP */ +#define IOMUXC_SW_PAD_CTL_GRP_COUNT (10U) + +/*! @name SELECT_INPUT - USB_OTG1_ID_SELECT_INPUT DAISY Register..USDHC2_WP_SELECT_INPUT DAISY Register */ +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (122U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x20E0000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + __IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + uint8_t RESERVED_0[12]; + __I uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + uint8_t RESERVED_1[12]; + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR0 - GPR0 General Purpose Register */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK (0x1U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT (0U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK (0x2U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT (1U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK (0x4U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT (2U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK (0x8U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT (3U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK (0x10U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT (4U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK (0x20U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT (5U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK (0x40U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT (6U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK (0x80U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT (7U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK (0x100U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT (8U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK (0x200U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT (9U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK (0x400U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT (10U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK (0x800U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT (11U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK (0x1000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT (12U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK (0x2000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT (13U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK (0x4000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT (14U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK (0x8000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT (15U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK (0x10000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT (16U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK (0x20000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT (17U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK (0x40000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT (18U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK (0x80000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT (19U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK (0x100000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT (20U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK (0x200000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT (21U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK (0x400000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT (22U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK) + +/*! @name GPR1 - GPR1 General Purpose Register */ +#define IOMUXC_GPR_GPR1_ACT_CS0_MASK (0x1U) +#define IOMUXC_GPR_GPR1_ACT_CS0_SHIFT (0U) +#define IOMUXC_GPR_GPR1_ACT_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS0_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS0_MASK) +#define IOMUXC_GPR_GPR1_ADDRS0_MASK (0x6U) +#define IOMUXC_GPR_GPR1_ADDRS0_SHIFT (1U) +#define IOMUXC_GPR_GPR1_ADDRS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS0_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS0_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS1_MASK (0x8U) +#define IOMUXC_GPR_GPR1_ACT_CS1_SHIFT (3U) +#define IOMUXC_GPR_GPR1_ACT_CS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS1_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS1_MASK) +#define IOMUXC_GPR_GPR1_ADDRS1_MASK (0x30U) +#define IOMUXC_GPR_GPR1_ADDRS1_SHIFT (4U) +#define IOMUXC_GPR_GPR1_ADDRS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS1_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS1_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS2_MASK (0x40U) +#define IOMUXC_GPR_GPR1_ACT_CS2_SHIFT (6U) +#define IOMUXC_GPR_GPR1_ACT_CS2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS2_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS2_MASK) +#define IOMUXC_GPR_GPR1_ADDRS2_MASK (0x180U) +#define IOMUXC_GPR_GPR1_ADDRS2_SHIFT (7U) +#define IOMUXC_GPR_GPR1_ADDRS2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS2_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS2_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS3_MASK (0x200U) +#define IOMUXC_GPR_GPR1_ACT_CS3_SHIFT (9U) +#define IOMUXC_GPR_GPR1_ACT_CS3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS3_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS3_MASK) +#define IOMUXC_GPR_GPR1_ADDRS3_MASK (0xC00U) +#define IOMUXC_GPR_GPR1_ADDRS3_SHIFT (10U) +#define IOMUXC_GPR_GPR1_ADDRS3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS3_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS3_MASK) +#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) +#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) +#define IOMUXC_GPR_GPR1_ADD_DS_MASK (0x10000U) +#define IOMUXC_GPR_GPR1_ADD_DS_SHIFT (16U) +#define IOMUXC_GPR_GPR1_ADD_DS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADD_DS_SHIFT)) & IOMUXC_GPR_GPR1_ADD_DS_MASK) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) +#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK (0x800000U) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT (23U) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_MASK (0x1000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_SHIFT (24U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_SHIFT (25U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_MASK (0x4000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_SHIFT (26U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_MASK) + +/*! @name GPR2 - GPR2 General Purpose Register */ +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK (0x1U) +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT (0U) +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK (0x2U) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT (1U) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK (0x4U) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT (2U) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK (0x8U) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT (3U) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK (0x10U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT (4U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK (0x20U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT (5U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK (0x40U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT (6U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK (0x80U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT (7U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK (0x100U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT (8U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK (0x200U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT (9U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK (0x400U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT (10U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK (0x800U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT (11U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK (0x2000U) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT (13U) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK (0x8000U) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT (15U) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) +#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK (0x8000000U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT (27U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK) +#define IOMUXC_GPR_GPR2_DRAM_RESET_MASK (0x10000000U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT (28U) +#define IOMUXC_GPR_GPR2_DRAM_RESET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_RESET_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE0_MASK (0x20000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT (29U) +#define IOMUXC_GPR_GPR2_DRAM_CKE0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE0_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE1_MASK (0x40000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT (30U) +#define IOMUXC_GPR_GPR2_DRAM_CKE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE1_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK (0x80000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT (31U) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK) + +/*! @name GPR3 - GPR3 General Purpose Register */ +#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) +#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) +#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK (0x2000U) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT (13U) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT)) & IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) + +/*! @name GPR4 - GPR4 General Purpose Register */ +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT (0U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT (3U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (4U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_MASK) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT (16U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT (19U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (20U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ARM_WFI_MASK (0x40000000U) +#define IOMUXC_GPR_GPR4_ARM_WFI_SHIFT (30U) +#define IOMUXC_GPR_GPR4_ARM_WFI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ARM_WFI_SHIFT)) & IOMUXC_GPR_GPR4_ARM_WFI_MASK) +#define IOMUXC_GPR_GPR4_ARM_WFE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR4_ARM_WFE_SHIFT (31U) +#define IOMUXC_GPR_GPR4_ARM_WFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ARM_WFE_SHIFT)) & IOMUXC_GPR_GPR4_ARM_WFE_MASK) + +/*! @name GPR5 - GPR5 General Purpose Register */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_MASK (0x300U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_SHIFT (8U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_MASK (0x3000U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_SHIFT (12U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK (0x30000U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT (16U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK) +#define IOMUXC_GPR_GPR5_WDOG3_MASK_MASK (0x100000U) +#define IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT (20U) +#define IOMUXC_GPR_GPR5_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG3_MASK_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK (0x2000000U) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT (25U) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK (0x40000000U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT (30U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT)) & IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK (0x80000000U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT (31U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT)) & IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK) + +/*! @name GPR9 - GPR9 General Purpose Register */ +#define IOMUXC_GPR_GPR9_TZASC1_BYP_MASK (0x1U) +#define IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT (0U) +#define IOMUXC_GPR_GPR9_TZASC1_BYP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT)) & IOMUXC_GPR_GPR9_TZASC1_BYP_MASK) + +/*! @name GPR10 - GPR10 General Purpose Register */ +#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (0U) +#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT (1U) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (10U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xF800U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (11U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) + +/*! @name GPR14 - GPR14 General Purpose Register */ +#define IOMUXC_GPR_GPR14_GPR_MASK (0xFFFFFFFCU) +#define IOMUXC_GPR_GPR14_GPR_SHIFT (2U) +#define IOMUXC_GPR_GPR14_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_SHIFT)) & IOMUXC_GPR_GPR14_GPR_MASK) + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x20E4000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD[12]; /**< SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register..SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register, array offset: 0x0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[17]; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register, array offset: 0x30, array step: 0x4 */ +} IOMUXC_SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register..SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_MASK) + +/* The count of IOMUXC_SNVS_SW_MUX_CTL_PAD */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_COUNT (12U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_MASK) + +/* The count of IOMUXC_SNVS_SW_PAD_CTL_PAD */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_COUNT (17U) + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Register_Masks */ + + +/* IOMUXC_SNVS - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS base address */ +#define IOMUXC_SNVS_BASE (0x2290000u) +/** Peripheral IOMUXC_SNVS base pointer */ +#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) +/** Array initializer of IOMUXC_SNVS peripheral base addresses */ +#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } +/** Array initializer of IOMUXC_SNVS peripheral base pointers */ +#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type; + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/*! @name KPCR - Keypad Control Register */ +#define KPP_KPCR_KRE_MASK (0xFFU) +#define KPP_KPCR_KRE_SHIFT (0U) +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK (0xFF00U) +#define KPP_KPCR_KCO_SHIFT (8U) +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) + +/*! @name KPSR - Keypad Status Register */ +#define KPP_KPSR_KPKD_MASK (0x1U) +#define KPP_KPSR_KPKD_SHIFT (0U) +#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) +#define KPP_KPSR_KPKR_MASK (0x2U) +#define KPP_KPSR_KPKR_SHIFT (1U) +#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) +#define KPP_KPSR_KDSC_MASK (0x4U) +#define KPP_KPSR_KDSC_SHIFT (2U) +#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) +#define KPP_KPSR_KRSS_MASK (0x8U) +#define KPP_KPSR_KRSS_SHIFT (3U) +#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) +#define KPP_KPSR_KDIE_MASK (0x100U) +#define KPP_KPSR_KDIE_SHIFT (8U) +#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) +#define KPP_KPSR_KRIE_MASK (0x200U) +#define KPP_KPSR_KRIE_SHIFT (9U) +#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) + +/*! @name KDDR - Keypad Data Direction Register */ +#define KPP_KDDR_KRDD_MASK (0xFFU) +#define KPP_KDDR_KRDD_SHIFT (0U) +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK (0xFF00U) +#define KPP_KDDR_KCDD_SHIFT (8U) +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) + +/*! @name KPDR - Keypad Data Register */ +#define KPP_KPDR_KRD_MASK (0xFFU) +#define KPP_KPDR_KRD_SHIFT (0U) +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK (0xFF00U) +#define KPP_KPDR_KCD_SHIFT (8U) +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) + + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x20B8000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +/** Array initializer of KPP peripheral base addresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } + +/*! + * @} + */ /* end of group KPP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< eLCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< eLCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< eLCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< eLCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< eLCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< eLCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< eLCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< eLCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< eLCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< eLCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t VDCTRL0; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + uint8_t RESERVED_4[12]; + __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ + uint8_t RESERVED_5[12]; + __IO uint32_t VDCTRL3; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t VDCTRL4; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + uint8_t RESERVED_23[76]; + __IO uint32_t THRES; /**< eLCDIF Threshold Register, offset: 0x200 */ + uint8_t RESERVED_24[12]; + __IO uint32_t AS_CTRL; /**< eLCDIF AS Buffer Control Register, offset: 0x210 */ + uint8_t RESERVED_25[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ + uint8_t RESERVED_26[12]; + __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ + uint8_t RESERVED_27[12]; + __IO uint32_t AS_CLRKEYLOW; /**< eLCDIF Overlay Color Key Low, offset: 0x240 */ + uint8_t RESERVED_28[12]; + __IO uint32_t AS_CLRKEYHIGH; /**< eLCDIF Overlay Color Key High, offset: 0x250 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - eLCDIF General Control Register */ +#define LCDIF_CTRL_RUN_MASK (0x1U) +#define LCDIF_CTRL_RUN_SHIFT (0U) +#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) +#define LCDIF_CTRL_MASTER_MASK (0x20U) +#define LCDIF_CTRL_MASTER_SHIFT (5U) +#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK) +#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK) +#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK) +#define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) +#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - eLCDIF General Control Register */ +#define LCDIF_CTRL_SET_RUN_MASK (0x1U) +#define LCDIF_CTRL_SET_RUN_SHIFT (0U) +#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) +#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) +#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) +#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_SET_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK) +#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_SET_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK) +#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_SET_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_SET_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK) +#define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) +#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - eLCDIF General Control Register */ +#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) +#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) +#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) +#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) +#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) +#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_CLR_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_CLR_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_CLR_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_CLR_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) +#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - eLCDIF General Control Register */ +#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) +#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) +#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) +#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) +#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) +#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_TOG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_TOG_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_TOG_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_TOG_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) +#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) + +/*! @name CTRL1 - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_RESET_MASK (0x1U) +#define LCDIF_CTRL1_RESET_SHIFT (0U) +#define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK) +#define LCDIF_CTRL1_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK) +#define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD1_SHIFT)) & LCDIF_CTRL1_RSRVD1_MASK) + +/*! @name CTRL1_SET - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_SET_RESET_MASK (0x1U) +#define LCDIF_CTRL1_SET_RESET_SHIFT (0U) +#define LCDIF_CTRL1_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK) +#define LCDIF_CTRL1_SET_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_SET_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_SET_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK) +#define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_SET_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_SET_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_SET_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD1_SHIFT)) & LCDIF_CTRL1_SET_RSRVD1_MASK) + +/*! @name CTRL1_CLR - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_CLR_RESET_MASK (0x1U) +#define LCDIF_CTRL1_CLR_RESET_SHIFT (0U) +#define LCDIF_CTRL1_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK) +#define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_CLR_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_CLR_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_CLR_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD1_MASK) + +/*! @name CTRL1_TOG - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_TOG_RESET_MASK (0x1U) +#define LCDIF_CTRL1_TOG_RESET_SHIFT (0U) +#define LCDIF_CTRL1_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK) +#define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_TOG_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_TOG_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_TOG_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD1_MASK) + +/*! @name CTRL2 - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) +#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) + +/*! @name CTRL2_SET - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) + +/*! @name CTRL2_CLR - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) + +/*! @name CTRL2_TOG - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) + +/*! @name TRANSFER_COUNT - eLCDIF Horizontal and Vertical Valid Data Count Register */ +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) + +/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) + +/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) + +/*! @name TIMING - LCD Interface Timing Register */ +#define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU) +#define LCDIF_TIMING_DATA_SETUP_SHIFT (0U) +#define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK) +#define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U) +#define LCDIF_TIMING_DATA_HOLD_SHIFT (8U) +#define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK) +#define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U) +#define LCDIF_TIMING_CMD_SETUP_SHIFT (16U) +#define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK) +#define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U) +#define LCDIF_TIMING_CMD_HOLD_SHIFT (24U) +#define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK) + +/*! @name VDCTRL0 - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) +#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) + +/*! @name VDCTRL0_SET - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) + +/*! @name VDCTRL0_CLR - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) + +/*! @name VDCTRL0_TOG - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) + +/*! @name VDCTRL1 - eLCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) + +/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) + +/*! @name VDCTRL3 - eLCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) +#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) +#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) + +/*! @name VDCTRL4 - eLCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) +#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) +#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) + +/*! @name DVICTRL0 - Digital Video Interface Control0 Register */ +#define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU) +#define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U) +#define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U) +#define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U) +#define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U) +#define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U) +#define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK) + +/*! @name DVICTRL1 - Digital Video Interface Control1 Register */ +#define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U) +#define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK) +#define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK) +#define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK) +#define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK) + +/*! @name DVICTRL2 - Digital Video Interface Control2 Register */ +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U) +#define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK) +#define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK) + +/*! @name DVICTRL3 - Digital Video Interface Control3 Register */ +#define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU) +#define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U) +#define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK) + +/*! @name DVICTRL4 - Digital Video Interface Control4 Register */ +#define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU) +#define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U) +#define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) + +/*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */ +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U) +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U) +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) +#define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU) +#define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U) +#define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK) +#define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF0_C0_SHIFT (16U) +#define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK) +#define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK) + +/*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */ +#define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU) +#define LCDIF_CSC_COEFF1_C1_SHIFT (0U) +#define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK) +#define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK) +#define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF1_C2_SHIFT (16U) +#define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK) +#define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK) + +/*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */ +#define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU) +#define LCDIF_CSC_COEFF2_C3_SHIFT (0U) +#define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK) +#define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK) +#define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF2_C4_SHIFT (16U) +#define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK) +#define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK) + +/*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */ +#define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU) +#define LCDIF_CSC_COEFF3_C5_SHIFT (0U) +#define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK) +#define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK) +#define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF3_C6_SHIFT (16U) +#define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK) +#define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK) + +/*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */ +#define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU) +#define LCDIF_CSC_COEFF4_C7_SHIFT (0U) +#define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK) +#define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK) +#define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF4_C8_SHIFT (16U) +#define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK) +#define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK) + +/*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */ +#define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU) +#define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U) +#define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U) +#define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U) +#define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U) +#define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U) +#define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK) + +/*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */ +#define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU) +#define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U) +#define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK) +#define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U) +#define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U) +#define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U) +#define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U) +#define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U) +#define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U) +#define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK) + +/*! @name DATA - LCD Interface Data Register */ +#define LCDIF_DATA_DATA_ZERO_MASK (0xFFU) +#define LCDIF_DATA_DATA_ZERO_SHIFT (0U) +#define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK) +#define LCDIF_DATA_DATA_ONE_MASK (0xFF00U) +#define LCDIF_DATA_DATA_ONE_SHIFT (8U) +#define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK) +#define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U) +#define LCDIF_DATA_DATA_TWO_SHIFT (16U) +#define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK) +#define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U) +#define LCDIF_DATA_DATA_THREE_SHIFT (24U) +#define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK) + +/*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) + +/*! @name CRC_STAT - CRC Status Register */ +#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) + +/*! @name STAT - LCD Interface Status Register */ +#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) +#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) +#define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U) +#define LCDIF_STAT_RSRVD0_SHIFT (9U) +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) +#define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U) +#define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U) +#define LCDIF_STAT_DVI_CURRENT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK) +#define LCDIF_STAT_BUSY_MASK (0x2000000U) +#define LCDIF_STAT_BUSY_SHIFT (25U) +#define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK) +#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) +#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) +#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) +#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) +#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) +#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) +#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) +#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) +#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) +#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) +#define LCDIF_STAT_PRESENT_MASK (0x80000000U) +#define LCDIF_STAT_PRESENT_SHIFT (31U) +#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) + +/*! @name THRES - eLCDIF Threshold Register */ +#define LCDIF_THRES_PANIC_MASK (0x1FFU) +#define LCDIF_THRES_PANIC_SHIFT (0U) +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) +#define LCDIF_THRES_RSRVD1_MASK (0xFE00U) +#define LCDIF_THRES_RSRVD1_SHIFT (9U) +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) +#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) +#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) +#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) +#define LCDIF_THRES_RSRVD2_SHIFT (25U) +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) + +/*! @name AS_CTRL - eLCDIF AS Buffer Control Register */ +#define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U) +#define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U) +#define LCDIF_AS_CTRL_AS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK) +#define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK) +#define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U) +#define LCDIF_AS_CTRL_FORMAT_SHIFT (4U) +#define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK) +#define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U) +#define LCDIF_AS_CTRL_ALPHA_SHIFT (8U) +#define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK) +#define LCDIF_AS_CTRL_ROP_MASK (0xF0000U) +#define LCDIF_AS_CTRL_ROP_SHIFT (16U) +#define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK) +#define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) +#define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U) +#define LCDIF_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U) +#define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U) +#define LCDIF_AS_CTRL_PS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK) +#define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U) +#define LCDIF_AS_CTRL_RVDS1_SHIFT (24U) +#define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK) + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +#define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK) + +/*! @name AS_NEXT_BUF - */ +#define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK) + +/*! @name AS_CLRKEYLOW - eLCDIF Overlay Color Key Low */ +#define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK) +#define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK) + +/*! @name AS_CLRKEYHIGH - eLCDIF Overlay Color Key High */ +#define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) + +/*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */ +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x21C8000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MMDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Peripheral_Access_Layer MMDC Peripheral Access Layer + * @{ + */ + +/** MMDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MDCTL; /**< MMDC Core Control Register, offset: 0x0 */ + __IO uint32_t MDPDC; /**< MMDC Core Power Down Control Register, offset: 0x4 */ + __IO uint32_t MDOTC; /**< MMDC Core ODT Timing Control Register, offset: 0x8 */ + __IO uint32_t MDCFG0; /**< MMDC Core Timing Configuration Register 0, offset: 0xC */ + __IO uint32_t MDCFG1; /**< MMDC Core Timing Configuration Register 1, offset: 0x10 */ + __IO uint32_t MDCFG2; /**< MMDC Core Timing Configuration Register 2, offset: 0x14 */ + __IO uint32_t MDMISC; /**< MMDC Core Miscellaneous Register, offset: 0x18 */ + __IO uint32_t MDSCR; /**< MMDC Core Special Command Register, offset: 0x1C */ + __IO uint32_t MDREF; /**< MMDC Core Refresh Control Register, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MDRWD; /**< MMDC Core Read/Write Command Delay Register, offset: 0x2C */ + __IO uint32_t MDOR; /**< MMDC Core Out of Reset Delays Register, offset: 0x30 */ + __I uint32_t MDMRR; /**< MMDC Core MRR Data Register, offset: 0x34 */ + __IO uint32_t MDCFG3LP; /**< MMDC Core Timing Configuration Register 3, offset: 0x38 */ + __IO uint32_t MDMR4; /**< MMDC Core MR4 Derating Register, offset: 0x3C */ + __IO uint32_t MDASP; /**< MMDC Core Address Space Partition Register, offset: 0x40 */ + uint8_t RESERVED_1[956]; + __IO uint32_t MAARCR; /**< MMDC Core AXI Reordering Control Register, offset: 0x400 */ + __IO uint32_t MAPSR; /**< MMDC Core Power Saving Control and Status Register, offset: 0x404 */ + __IO uint32_t MAEXIDR0; /**< MMDC Core Exclusive ID Monitor Register0, offset: 0x408 */ + __IO uint32_t MAEXIDR1; /**< MMDC Core Exclusive ID Monitor Register1, offset: 0x40C */ + __IO uint32_t MADPCR0; /**< MMDC Core Debug and Profiling Control Register 0, offset: 0x410 */ + __IO uint32_t MADPCR1; /**< MMDC Core Debug and Profiling Control Register 1, offset: 0x414 */ + __I uint32_t MADPSR0; /**< MMDC Core Debug and Profiling Status Register 0, offset: 0x418 */ + __I uint32_t MADPSR1; /**< MMDC Core Debug and Profiling Status Register 1, offset: 0x41C */ + __I uint32_t MADPSR2; /**< MMDC Core Debug and Profiling Status Register 2, offset: 0x420 */ + __I uint32_t MADPSR3; /**< MMDC Core Debug and Profiling Status Register 3, offset: 0x424 */ + __I uint32_t MADPSR4; /**< MMDC Core Debug and Profiling Status Register 4, offset: 0x428 */ + __I uint32_t MADPSR5; /**< MMDC Core Debug and Profiling Status Register 5, offset: 0x42C */ + __I uint32_t MASBS0; /**< MMDC Core Step By Step Address Register, offset: 0x430 */ + __I uint32_t MASBS1; /**< MMDC Core Step By Step Address Attributes Register, offset: 0x434 */ + uint8_t RESERVED_2[8]; + __IO uint32_t MAGENP; /**< MMDC Core General Purpose Register, offset: 0x440 */ + uint8_t RESERVED_3[956]; + __IO uint32_t MPZQHWCTRL; /**< MMDC PHY ZQ HW control register, offset: 0x800 */ + __IO uint32_t MPZQSWCTRL; /**< MMDC PHY ZQ SW control register, offset: 0x804 */ + __IO uint32_t MPWLGCR; /**< MMDC PHY Write Leveling Configuration and Error Status Register, offset: 0x808 */ + __IO uint32_t MPWLDECTRL0; /**< MMDC PHY Write Leveling Delay Control Register 0, offset: 0x80C */ + __IO uint32_t MPWLDECTRL1; /**< MMDC PHY Write Leveling Delay Control Register 1, offset: 0x810 */ + __I uint32_t MPWLDLST; /**< MMDC PHY Write Leveling delay-line Status Register, offset: 0x814 */ + __IO uint32_t MPODTCTRL; /**< MMDC PHY ODT control register, offset: 0x818 */ + __IO uint32_t MPRDDQBY0DL; /**< MMDC PHY Read DQ Byte0 Delay Register, offset: 0x81C */ + __IO uint32_t MPRDDQBY1DL; /**< MMDC PHY Read DQ Byte1 Delay Register, offset: 0x820 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MPWRDQBY0DL; /**< MMDC PHY Write DQ Byte0 Delay Register, offset: 0x82C */ + __IO uint32_t MPWRDQBY1DL; /**< MMDC PHY Write DQ Byte1 Delay Register, offset: 0x830 */ + __IO uint32_t MPWRDQBY2DL; /**< MMDC PHY Write DQ Byte2 Delay Register, offset: 0x834 */ + __IO uint32_t MPWRDQBY3DL; /**< MMDC PHY Write DQ Byte3 Delay Register, offset: 0x838 */ + __IO uint32_t MPDGCTRL0; /**< MMDC PHY Read DQS Gating Control Register 0, offset: 0x83C */ + uint8_t RESERVED_5[4]; + __I uint32_t MPDGDLST0; /**< MMDC PHY Read DQS Gating delay-line Status Register, offset: 0x844 */ + __IO uint32_t MPRDDLCTL; /**< MMDC PHY Read delay-lines Configuration Register, offset: 0x848 */ + __I uint32_t MPRDDLST; /**< MMDC PHY Read delay-lines Status Register, offset: 0x84C */ + __IO uint32_t MPWRDLCTL; /**< MMDC PHY Write delay-lines Configuration Register, offset: 0x850 */ + __I uint32_t MPWRDLST; /**< MMDC PHY Write delay-lines Status Register, offset: 0x854 */ + __IO uint32_t MPSDCTRL; /**< MMDC PHY CK Control Register, offset: 0x858 */ + __IO uint32_t MPZQLP2CTL; /**< MMDC ZQ LPDDR2 HW Control Register, offset: 0x85C */ + __IO uint32_t MPRDDLHWCTL; /**< MMDC PHY Read Delay HW Calibration Control Register, offset: 0x860 */ + __IO uint32_t MPWRDLHWCTL; /**< MMDC PHY Write Delay HW Calibration Control Register, offset: 0x864 */ + __I uint32_t MPRDDLHWST0; /**< MMDC PHY Read Delay HW Calibration Status Register 0, offset: 0x868 */ + uint8_t RESERVED_6[4]; + __I uint32_t MPWRDLHWST0; /**< MMDC PHY Write Delay HW Calibration Status Register 0, offset: 0x870 */ + uint8_t RESERVED_7[4]; + __I uint32_t MPWLHWERR; /**< MMDC PHY Write Leveling HW Error Register, offset: 0x878 */ + __I uint32_t MPDGHWST0; /**< MMDC PHY Read DQS Gating HW Status Register 0, offset: 0x87C */ + __I uint32_t MPDGHWST1; /**< MMDC PHY Read DQS Gating HW Status Register 1, offset: 0x880 */ + uint8_t RESERVED_8[8]; + __IO uint32_t MPPDCMPR1; /**< MMDC PHY Pre-defined Compare Register 1, offset: 0x88C */ + __IO uint32_t MPPDCMPR2; /**< MMDC PHY Pre-defined Compare and CA delay-line Configuration Register, offset: 0x890 */ + __IO uint32_t MPSWDAR0; /**< MMDC PHY SW Dummy Access Register, offset: 0x894 */ + __I uint32_t MPSWDRDR0; /**< MMDC PHY SW Dummy Read Data Register 0, offset: 0x898 */ + __I uint32_t MPSWDRDR1; /**< MMDC PHY SW Dummy Read Data Register 1, offset: 0x89C */ + __I uint32_t MPSWDRDR2; /**< MMDC PHY SW Dummy Read Data Register 2, offset: 0x8A0 */ + __I uint32_t MPSWDRDR3; /**< MMDC PHY SW Dummy Read Data Register 3, offset: 0x8A4 */ + __I uint32_t MPSWDRDR4; /**< MMDC PHY SW Dummy Read Data Register 4, offset: 0x8A8 */ + __I uint32_t MPSWDRDR5; /**< MMDC PHY SW Dummy Read Data Register 5, offset: 0x8AC */ + __I uint32_t MPSWDRDR6; /**< MMDC PHY SW Dummy Read Data Register 6, offset: 0x8B0 */ + __I uint32_t MPSWDRDR7; /**< MMDC PHY SW Dummy Read Data Register 7, offset: 0x8B4 */ + __IO uint32_t MPMUR0; /**< MMDC PHY Measure Unit Register, offset: 0x8B8 */ + __IO uint32_t MPWRCADL; /**< MMDC Write CA delay-line controller, offset: 0x8BC */ + __IO uint32_t MPDCCR; /**< MMDC Duty Cycle Control Register, offset: 0x8C0 */ +} MMDC_Type; + +/* ---------------------------------------------------------------------------- + -- MMDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Register_Masks MMDC Register Masks + * @{ + */ + +/*! @name MDCTL - MMDC Core Control Register */ +#define MMDC_MDCTL_DSIZ_MASK (0x30000U) +#define MMDC_MDCTL_DSIZ_SHIFT (16U) +#define MMDC_MDCTL_DSIZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_DSIZ_SHIFT)) & MMDC_MDCTL_DSIZ_MASK) +#define MMDC_MDCTL_BL_MASK (0x80000U) +#define MMDC_MDCTL_BL_SHIFT (19U) +#define MMDC_MDCTL_BL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_BL_SHIFT)) & MMDC_MDCTL_BL_MASK) +#define MMDC_MDCTL_COL_MASK (0x700000U) +#define MMDC_MDCTL_COL_SHIFT (20U) +#define MMDC_MDCTL_COL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_COL_SHIFT)) & MMDC_MDCTL_COL_MASK) +#define MMDC_MDCTL_ROW_MASK (0x7000000U) +#define MMDC_MDCTL_ROW_SHIFT (24U) +#define MMDC_MDCTL_ROW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_ROW_SHIFT)) & MMDC_MDCTL_ROW_MASK) +#define MMDC_MDCTL_SDE_1_MASK (0x40000000U) +#define MMDC_MDCTL_SDE_1_SHIFT (30U) +#define MMDC_MDCTL_SDE_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_1_SHIFT)) & MMDC_MDCTL_SDE_1_MASK) +#define MMDC_MDCTL_SDE_0_MASK (0x80000000U) +#define MMDC_MDCTL_SDE_0_SHIFT (31U) +#define MMDC_MDCTL_SDE_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_0_SHIFT)) & MMDC_MDCTL_SDE_0_MASK) + +/*! @name MDPDC - MMDC Core Power Down Control Register */ +#define MMDC_MDPDC_TCKSRE_MASK (0x7U) +#define MMDC_MDPDC_TCKSRE_SHIFT (0U) +#define MMDC_MDPDC_TCKSRE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKSRE_SHIFT)) & MMDC_MDPDC_TCKSRE_MASK) +#define MMDC_MDPDC_TCKSRX_MASK (0x38U) +#define MMDC_MDPDC_TCKSRX_SHIFT (3U) +#define MMDC_MDPDC_TCKSRX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKSRX_SHIFT)) & MMDC_MDPDC_TCKSRX_MASK) +#define MMDC_MDPDC_BOTH_CS_PD_MASK (0x40U) +#define MMDC_MDPDC_BOTH_CS_PD_SHIFT (6U) +#define MMDC_MDPDC_BOTH_CS_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_BOTH_CS_PD_SHIFT)) & MMDC_MDPDC_BOTH_CS_PD_MASK) +#define MMDC_MDPDC_SLOW_PD_MASK (0x80U) +#define MMDC_MDPDC_SLOW_PD_SHIFT (7U) +#define MMDC_MDPDC_SLOW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_SLOW_PD_SHIFT)) & MMDC_MDPDC_SLOW_PD_MASK) +#define MMDC_MDPDC_PWDT_0_MASK (0xF00U) +#define MMDC_MDPDC_PWDT_0_SHIFT (8U) +#define MMDC_MDPDC_PWDT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_0_SHIFT)) & MMDC_MDPDC_PWDT_0_MASK) +#define MMDC_MDPDC_PWDT_1_MASK (0xF000U) +#define MMDC_MDPDC_PWDT_1_SHIFT (12U) +#define MMDC_MDPDC_PWDT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_1_SHIFT)) & MMDC_MDPDC_PWDT_1_MASK) +#define MMDC_MDPDC_TCKE_MASK (0x70000U) +#define MMDC_MDPDC_TCKE_SHIFT (16U) +#define MMDC_MDPDC_TCKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKE_SHIFT)) & MMDC_MDPDC_TCKE_MASK) +#define MMDC_MDPDC_PRCT_0_MASK (0x7000000U) +#define MMDC_MDPDC_PRCT_0_SHIFT (24U) +#define MMDC_MDPDC_PRCT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_0_SHIFT)) & MMDC_MDPDC_PRCT_0_MASK) +#define MMDC_MDPDC_PRCT_1_MASK (0x70000000U) +#define MMDC_MDPDC_PRCT_1_SHIFT (28U) +#define MMDC_MDPDC_PRCT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_1_SHIFT)) & MMDC_MDPDC_PRCT_1_MASK) + +/*! @name MDOTC - MMDC Core ODT Timing Control Register */ +#define MMDC_MDOTC_TODT_IDLE_OFF_MASK (0x1F0U) +#define MMDC_MDOTC_TODT_IDLE_OFF_SHIFT (4U) +#define MMDC_MDOTC_TODT_IDLE_OFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TODT_IDLE_OFF_SHIFT)) & MMDC_MDOTC_TODT_IDLE_OFF_MASK) +#define MMDC_MDOTC_TODTLON_MASK (0x7000U) +#define MMDC_MDOTC_TODTLON_SHIFT (12U) +#define MMDC_MDOTC_TODTLON(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TODTLON_SHIFT)) & MMDC_MDOTC_TODTLON_MASK) +#define MMDC_MDOTC_TAXPD_MASK (0xF0000U) +#define MMDC_MDOTC_TAXPD_SHIFT (16U) +#define MMDC_MDOTC_TAXPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAXPD_SHIFT)) & MMDC_MDOTC_TAXPD_MASK) +#define MMDC_MDOTC_TANPD_MASK (0xF00000U) +#define MMDC_MDOTC_TANPD_SHIFT (20U) +#define MMDC_MDOTC_TANPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TANPD_SHIFT)) & MMDC_MDOTC_TANPD_MASK) +#define MMDC_MDOTC_TAONPD_MASK (0x7000000U) +#define MMDC_MDOTC_TAONPD_SHIFT (24U) +#define MMDC_MDOTC_TAONPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAONPD_SHIFT)) & MMDC_MDOTC_TAONPD_MASK) +#define MMDC_MDOTC_TAOFPD_MASK (0x38000000U) +#define MMDC_MDOTC_TAOFPD_SHIFT (27U) +#define MMDC_MDOTC_TAOFPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAOFPD_SHIFT)) & MMDC_MDOTC_TAOFPD_MASK) + +/*! @name MDCFG0 - MMDC Core Timing Configuration Register 0 */ +#define MMDC_MDCFG0_TCL_MASK (0xFU) +#define MMDC_MDCFG0_TCL_SHIFT (0U) +#define MMDC_MDCFG0_TCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TCL_SHIFT)) & MMDC_MDCFG0_TCL_MASK) +#define MMDC_MDCFG0_TFAW_MASK (0x1F0U) +#define MMDC_MDCFG0_TFAW_SHIFT (4U) +#define MMDC_MDCFG0_TFAW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TFAW_SHIFT)) & MMDC_MDCFG0_TFAW_MASK) +#define MMDC_MDCFG0_TXPDLL_MASK (0x1E00U) +#define MMDC_MDCFG0_TXPDLL_SHIFT (9U) +#define MMDC_MDCFG0_TXPDLL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXPDLL_SHIFT)) & MMDC_MDCFG0_TXPDLL_MASK) +#define MMDC_MDCFG0_TXP_MASK (0xE000U) +#define MMDC_MDCFG0_TXP_SHIFT (13U) +#define MMDC_MDCFG0_TXP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXP_SHIFT)) & MMDC_MDCFG0_TXP_MASK) +#define MMDC_MDCFG0_TXS_MASK (0xFF0000U) +#define MMDC_MDCFG0_TXS_SHIFT (16U) +#define MMDC_MDCFG0_TXS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXS_SHIFT)) & MMDC_MDCFG0_TXS_MASK) +#define MMDC_MDCFG0_TRFC_MASK (0xFF000000U) +#define MMDC_MDCFG0_TRFC_SHIFT (24U) +#define MMDC_MDCFG0_TRFC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TRFC_SHIFT)) & MMDC_MDCFG0_TRFC_MASK) + +/*! @name MDCFG1 - MMDC Core Timing Configuration Register 1 */ +#define MMDC_MDCFG1_TCWL_MASK (0x7U) +#define MMDC_MDCFG1_TCWL_SHIFT (0U) +#define MMDC_MDCFG1_TCWL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TCWL_SHIFT)) & MMDC_MDCFG1_TCWL_MASK) +#define MMDC_MDCFG1_TMRD_MASK (0x1E0U) +#define MMDC_MDCFG1_TMRD_SHIFT (5U) +#define MMDC_MDCFG1_TMRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TMRD_SHIFT)) & MMDC_MDCFG1_TMRD_MASK) +#define MMDC_MDCFG1_TWR_MASK (0xE00U) +#define MMDC_MDCFG1_TWR_SHIFT (9U) +#define MMDC_MDCFG1_TWR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TWR_SHIFT)) & MMDC_MDCFG1_TWR_MASK) +#define MMDC_MDCFG1_TRPA_MASK (0x8000U) +#define MMDC_MDCFG1_TRPA_SHIFT (15U) +#define MMDC_MDCFG1_TRPA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRPA_SHIFT)) & MMDC_MDCFG1_TRPA_MASK) +#define MMDC_MDCFG1_TRAS_MASK (0x1F0000U) +#define MMDC_MDCFG1_TRAS_SHIFT (16U) +#define MMDC_MDCFG1_TRAS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRAS_SHIFT)) & MMDC_MDCFG1_TRAS_MASK) +#define MMDC_MDCFG1_TRC_MASK (0x3E00000U) +#define MMDC_MDCFG1_TRC_SHIFT (21U) +#define MMDC_MDCFG1_TRC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRC_SHIFT)) & MMDC_MDCFG1_TRC_MASK) +#define MMDC_MDCFG1_TRP_MASK (0x1C000000U) +#define MMDC_MDCFG1_TRP_SHIFT (26U) +#define MMDC_MDCFG1_TRP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRP_SHIFT)) & MMDC_MDCFG1_TRP_MASK) +#define MMDC_MDCFG1_TRCD_MASK (0xE0000000U) +#define MMDC_MDCFG1_TRCD_SHIFT (29U) +#define MMDC_MDCFG1_TRCD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRCD_SHIFT)) & MMDC_MDCFG1_TRCD_MASK) + +/*! @name MDCFG2 - MMDC Core Timing Configuration Register 2 */ +#define MMDC_MDCFG2_TRRD_MASK (0x7U) +#define MMDC_MDCFG2_TRRD_SHIFT (0U) +#define MMDC_MDCFG2_TRRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TRRD_SHIFT)) & MMDC_MDCFG2_TRRD_MASK) +#define MMDC_MDCFG2_TWTR_MASK (0x38U) +#define MMDC_MDCFG2_TWTR_SHIFT (3U) +#define MMDC_MDCFG2_TWTR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TWTR_SHIFT)) & MMDC_MDCFG2_TWTR_MASK) +#define MMDC_MDCFG2_TRTP_MASK (0x1C0U) +#define MMDC_MDCFG2_TRTP_SHIFT (6U) +#define MMDC_MDCFG2_TRTP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TRTP_SHIFT)) & MMDC_MDCFG2_TRTP_MASK) +#define MMDC_MDCFG2_TDLLK_MASK (0x1FF0000U) +#define MMDC_MDCFG2_TDLLK_SHIFT (16U) +#define MMDC_MDCFG2_TDLLK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TDLLK_SHIFT)) & MMDC_MDCFG2_TDLLK_MASK) + +/*! @name MDMISC - MMDC Core Miscellaneous Register */ +#define MMDC_MDMISC_RST_MASK (0x2U) +#define MMDC_MDMISC_RST_SHIFT (1U) +#define MMDC_MDMISC_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RST_SHIFT)) & MMDC_MDMISC_RST_MASK) +#define MMDC_MDMISC_DDR_TYPE_MASK (0x18U) +#define MMDC_MDMISC_DDR_TYPE_SHIFT (3U) +#define MMDC_MDMISC_DDR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_TYPE_SHIFT)) & MMDC_MDMISC_DDR_TYPE_MASK) +#define MMDC_MDMISC_DDR_4_BANK_MASK (0x20U) +#define MMDC_MDMISC_DDR_4_BANK_SHIFT (5U) +#define MMDC_MDMISC_DDR_4_BANK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_4_BANK_SHIFT)) & MMDC_MDMISC_DDR_4_BANK_MASK) +#define MMDC_MDMISC_RALAT_MASK (0x1C0U) +#define MMDC_MDMISC_RALAT_SHIFT (6U) +#define MMDC_MDMISC_RALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RALAT_SHIFT)) & MMDC_MDMISC_RALAT_MASK) +#define MMDC_MDMISC_MIF3_MODE_MASK (0x600U) +#define MMDC_MDMISC_MIF3_MODE_SHIFT (9U) +#define MMDC_MDMISC_MIF3_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_MIF3_MODE_SHIFT)) & MMDC_MDMISC_MIF3_MODE_MASK) +#define MMDC_MDMISC_LPDDR2_S2_MASK (0x800U) +#define MMDC_MDMISC_LPDDR2_S2_SHIFT (11U) +#define MMDC_MDMISC_LPDDR2_S2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LPDDR2_S2_SHIFT)) & MMDC_MDMISC_LPDDR2_S2_MASK) +#define MMDC_MDMISC_BI_ON_MASK (0x1000U) +#define MMDC_MDMISC_BI_ON_SHIFT (12U) +#define MMDC_MDMISC_BI_ON(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_BI_ON_SHIFT)) & MMDC_MDMISC_BI_ON_MASK) +#define MMDC_MDMISC_WALAT_MASK (0x30000U) +#define MMDC_MDMISC_WALAT_SHIFT (16U) +#define MMDC_MDMISC_WALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_WALAT_SHIFT)) & MMDC_MDMISC_WALAT_MASK) +#define MMDC_MDMISC_LHD_MASK (0x40000U) +#define MMDC_MDMISC_LHD_SHIFT (18U) +#define MMDC_MDMISC_LHD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LHD_SHIFT)) & MMDC_MDMISC_LHD_MASK) +#define MMDC_MDMISC_ADDR_MIRROR_MASK (0x80000U) +#define MMDC_MDMISC_ADDR_MIRROR_SHIFT (19U) +#define MMDC_MDMISC_ADDR_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_ADDR_MIRROR_SHIFT)) & MMDC_MDMISC_ADDR_MIRROR_MASK) +#define MMDC_MDMISC_CALIB_PER_CS_MASK (0x100000U) +#define MMDC_MDMISC_CALIB_PER_CS_SHIFT (20U) +#define MMDC_MDMISC_CALIB_PER_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CALIB_PER_CS_SHIFT)) & MMDC_MDMISC_CALIB_PER_CS_MASK) +#define MMDC_MDMISC_CK1_GATING_MASK (0x200000U) +#define MMDC_MDMISC_CK1_GATING_SHIFT (21U) +#define MMDC_MDMISC_CK1_GATING(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CK1_GATING_SHIFT)) & MMDC_MDMISC_CK1_GATING_MASK) +#define MMDC_MDMISC_CS1_RDY_MASK (0x40000000U) +#define MMDC_MDMISC_CS1_RDY_SHIFT (30U) +#define MMDC_MDMISC_CS1_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS1_RDY_SHIFT)) & MMDC_MDMISC_CS1_RDY_MASK) +#define MMDC_MDMISC_CS0_RDY_MASK (0x80000000U) +#define MMDC_MDMISC_CS0_RDY_SHIFT (31U) +#define MMDC_MDMISC_CS0_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS0_RDY_SHIFT)) & MMDC_MDMISC_CS0_RDY_MASK) + +/*! @name MDSCR - MMDC Core Special Command Register */ +#define MMDC_MDSCR_CMD_BA_MASK (0x7U) +#define MMDC_MDSCR_CMD_BA_SHIFT (0U) +#define MMDC_MDSCR_CMD_BA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_BA_SHIFT)) & MMDC_MDSCR_CMD_BA_MASK) +#define MMDC_MDSCR_CMD_CS_MASK (0x8U) +#define MMDC_MDSCR_CMD_CS_SHIFT (3U) +#define MMDC_MDSCR_CMD_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_CS_SHIFT)) & MMDC_MDSCR_CMD_CS_MASK) +#define MMDC_MDSCR_CMD_MASK (0x70U) +#define MMDC_MDSCR_CMD_SHIFT (4U) +#define MMDC_MDSCR_CMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_SHIFT)) & MMDC_MDSCR_CMD_MASK) +#define MMDC_MDSCR_WL_EN_MASK (0x200U) +#define MMDC_MDSCR_WL_EN_SHIFT (9U) +#define MMDC_MDSCR_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_WL_EN_SHIFT)) & MMDC_MDSCR_WL_EN_MASK) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK (0x400U) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT (10U) +#define MMDC_MDSCR_MRR_READ_DATA_VALID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT)) & MMDC_MDSCR_MRR_READ_DATA_VALID_MASK) +#define MMDC_MDSCR_CON_ACK_MASK (0x4000U) +#define MMDC_MDSCR_CON_ACK_SHIFT (14U) +#define MMDC_MDSCR_CON_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_ACK_SHIFT)) & MMDC_MDSCR_CON_ACK_MASK) +#define MMDC_MDSCR_CON_REQ_MASK (0x8000U) +#define MMDC_MDSCR_CON_REQ_SHIFT (15U) +#define MMDC_MDSCR_CON_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_REQ_SHIFT)) & MMDC_MDSCR_CON_REQ_MASK) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK (0xFF0000U) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT (16U) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT)) & MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK (0xFF000000U) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT (24U) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT)) & MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK) + +/*! @name MDREF - MMDC Core Refresh Control Register */ +#define MMDC_MDREF_START_REF_MASK (0x1U) +#define MMDC_MDREF_START_REF_SHIFT (0U) +#define MMDC_MDREF_START_REF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_START_REF_SHIFT)) & MMDC_MDREF_START_REF_MASK) +#define MMDC_MDREF_REFR_MASK (0x3800U) +#define MMDC_MDREF_REFR_SHIFT (11U) +#define MMDC_MDREF_REFR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REFR_SHIFT)) & MMDC_MDREF_REFR_MASK) +#define MMDC_MDREF_REF_SEL_MASK (0xC000U) +#define MMDC_MDREF_REF_SEL_SHIFT (14U) +#define MMDC_MDREF_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_SEL_SHIFT)) & MMDC_MDREF_REF_SEL_MASK) +#define MMDC_MDREF_REF_CNT_MASK (0xFFFF0000U) +#define MMDC_MDREF_REF_CNT_SHIFT (16U) +#define MMDC_MDREF_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_CNT_SHIFT)) & MMDC_MDREF_REF_CNT_MASK) + +/*! @name MDRWD - MMDC Core Read/Write Command Delay Register */ +#define MMDC_MDRWD_RTR_DIFF_MASK (0x7U) +#define MMDC_MDRWD_RTR_DIFF_SHIFT (0U) +#define MMDC_MDRWD_RTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTR_DIFF_SHIFT)) & MMDC_MDRWD_RTR_DIFF_MASK) +#define MMDC_MDRWD_RTW_DIFF_MASK (0x38U) +#define MMDC_MDRWD_RTW_DIFF_SHIFT (3U) +#define MMDC_MDRWD_RTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_DIFF_SHIFT)) & MMDC_MDRWD_RTW_DIFF_MASK) +#define MMDC_MDRWD_WTW_DIFF_MASK (0x1C0U) +#define MMDC_MDRWD_WTW_DIFF_SHIFT (6U) +#define MMDC_MDRWD_WTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTW_DIFF_SHIFT)) & MMDC_MDRWD_WTW_DIFF_MASK) +#define MMDC_MDRWD_WTR_DIFF_MASK (0xE00U) +#define MMDC_MDRWD_WTR_DIFF_SHIFT (9U) +#define MMDC_MDRWD_WTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTR_DIFF_SHIFT)) & MMDC_MDRWD_WTR_DIFF_MASK) +#define MMDC_MDRWD_RTW_SAME_MASK (0x7000U) +#define MMDC_MDRWD_RTW_SAME_SHIFT (12U) +#define MMDC_MDRWD_RTW_SAME(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_SAME_SHIFT)) & MMDC_MDRWD_RTW_SAME_MASK) +#define MMDC_MDRWD_TDAI_MASK (0x1FFF0000U) +#define MMDC_MDRWD_TDAI_SHIFT (16U) +#define MMDC_MDRWD_TDAI(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_TDAI_SHIFT)) & MMDC_MDRWD_TDAI_MASK) + +/*! @name MDOR - MMDC Core Out of Reset Delays Register */ +#define MMDC_MDOR_RST_TO_CKE_MASK (0x3FU) +#define MMDC_MDOR_RST_TO_CKE_SHIFT (0U) +#define MMDC_MDOR_RST_TO_CKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_RST_TO_CKE_SHIFT)) & MMDC_MDOR_RST_TO_CKE_MASK) +#define MMDC_MDOR_SDE_TO_RST_MASK (0x3F00U) +#define MMDC_MDOR_SDE_TO_RST_SHIFT (8U) +#define MMDC_MDOR_SDE_TO_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_SDE_TO_RST_SHIFT)) & MMDC_MDOR_SDE_TO_RST_MASK) +#define MMDC_MDOR_TXPR_MASK (0xFF0000U) +#define MMDC_MDOR_TXPR_SHIFT (16U) +#define MMDC_MDOR_TXPR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_TXPR_SHIFT)) & MMDC_MDOR_TXPR_MASK) + +/*! @name MDMRR - MMDC Core MRR Data Register */ +#define MMDC_MDMRR_MRR_READ_DATA0_MASK (0xFFU) +#define MMDC_MDMRR_MRR_READ_DATA0_SHIFT (0U) +#define MMDC_MDMRR_MRR_READ_DATA0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA0_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA0_MASK) +#define MMDC_MDMRR_MRR_READ_DATA1_MASK (0xFF00U) +#define MMDC_MDMRR_MRR_READ_DATA1_SHIFT (8U) +#define MMDC_MDMRR_MRR_READ_DATA1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA1_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA1_MASK) + +/*! @name MDCFG3LP - MMDC Core Timing Configuration Register 3 */ +#define MMDC_MDCFG3LP_TRPAB_LP_MASK (0xFU) +#define MMDC_MDCFG3LP_TRPAB_LP_SHIFT (0U) +#define MMDC_MDCFG3LP_TRPAB_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRPAB_LP_SHIFT)) & MMDC_MDCFG3LP_TRPAB_LP_MASK) +#define MMDC_MDCFG3LP_TRPPB_LP_MASK (0xF0U) +#define MMDC_MDCFG3LP_TRPPB_LP_SHIFT (4U) +#define MMDC_MDCFG3LP_TRPPB_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRPPB_LP_SHIFT)) & MMDC_MDCFG3LP_TRPPB_LP_MASK) +#define MMDC_MDCFG3LP_TRCD_LP_MASK (0xF00U) +#define MMDC_MDCFG3LP_TRCD_LP_SHIFT (8U) +#define MMDC_MDCFG3LP_TRCD_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRCD_LP_SHIFT)) & MMDC_MDCFG3LP_TRCD_LP_MASK) +#define MMDC_MDCFG3LP_RC_LP_MASK (0x3F0000U) +#define MMDC_MDCFG3LP_RC_LP_SHIFT (16U) +#define MMDC_MDCFG3LP_RC_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_RC_LP_SHIFT)) & MMDC_MDCFG3LP_RC_LP_MASK) + +/*! @name MDMR4 - MMDC Core MR4 Derating Register */ +#define MMDC_MDMR4_UPDATE_DE_REQ_MASK (0x1U) +#define MMDC_MDMR4_UPDATE_DE_REQ_SHIFT (0U) +#define MMDC_MDMR4_UPDATE_DE_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_REQ_SHIFT)) & MMDC_MDMR4_UPDATE_DE_REQ_MASK) +#define MMDC_MDMR4_UPDATE_DE_ACK_MASK (0x2U) +#define MMDC_MDMR4_UPDATE_DE_ACK_SHIFT (1U) +#define MMDC_MDMR4_UPDATE_DE_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_ACK_SHIFT)) & MMDC_MDMR4_UPDATE_DE_ACK_MASK) +#define MMDC_MDMR4_TRCD_DE_MASK (0x10U) +#define MMDC_MDMR4_TRCD_DE_SHIFT (4U) +#define MMDC_MDMR4_TRCD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRCD_DE_SHIFT)) & MMDC_MDMR4_TRCD_DE_MASK) +#define MMDC_MDMR4_TRC_DE_MASK (0x20U) +#define MMDC_MDMR4_TRC_DE_SHIFT (5U) +#define MMDC_MDMR4_TRC_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRC_DE_SHIFT)) & MMDC_MDMR4_TRC_DE_MASK) +#define MMDC_MDMR4_TRAS_DE_MASK (0x40U) +#define MMDC_MDMR4_TRAS_DE_SHIFT (6U) +#define MMDC_MDMR4_TRAS_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRAS_DE_SHIFT)) & MMDC_MDMR4_TRAS_DE_MASK) +#define MMDC_MDMR4_TRP_DE_MASK (0x80U) +#define MMDC_MDMR4_TRP_DE_SHIFT (7U) +#define MMDC_MDMR4_TRP_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRP_DE_SHIFT)) & MMDC_MDMR4_TRP_DE_MASK) +#define MMDC_MDMR4_TRRD_DE_MASK (0x100U) +#define MMDC_MDMR4_TRRD_DE_SHIFT (8U) +#define MMDC_MDMR4_TRRD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRRD_DE_SHIFT)) & MMDC_MDMR4_TRRD_DE_MASK) + +/*! @name MDASP - MMDC Core Address Space Partition Register */ +#define MMDC_MDASP_CS0_END_MASK (0x7FU) +#define MMDC_MDASP_CS0_END_SHIFT (0U) +#define MMDC_MDASP_CS0_END(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDASP_CS0_END_SHIFT)) & MMDC_MDASP_CS0_END_MASK) + +/*! @name MAARCR - MMDC Core AXI Reordering Control Register */ +#define MMDC_MAARCR_ARCR_GUARD_MASK (0xFU) +#define MMDC_MAARCR_ARCR_GUARD_SHIFT (0U) +#define MMDC_MAARCR_ARCR_GUARD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_GUARD_SHIFT)) & MMDC_MAARCR_ARCR_GUARD_MASK) +#define MMDC_MAARCR_ARCR_DYN_MAX_MASK (0xF0U) +#define MMDC_MAARCR_ARCR_DYN_MAX_SHIFT (4U) +#define MMDC_MAARCR_ARCR_DYN_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_MAX_SHIFT)) & MMDC_MAARCR_ARCR_DYN_MAX_MASK) +#define MMDC_MAARCR_ARCR_DYN_JMP_MASK (0xF00U) +#define MMDC_MAARCR_ARCR_DYN_JMP_SHIFT (8U) +#define MMDC_MAARCR_ARCR_DYN_JMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_JMP_SHIFT)) & MMDC_MAARCR_ARCR_DYN_JMP_MASK) +#define MMDC_MAARCR_ARCR_ACC_HIT_MASK (0x70000U) +#define MMDC_MAARCR_ARCR_ACC_HIT_SHIFT (16U) +#define MMDC_MAARCR_ARCR_ACC_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_ACC_HIT_SHIFT)) & MMDC_MAARCR_ARCR_ACC_HIT_MASK) +#define MMDC_MAARCR_ARCR_PAG_HIT_MASK (0x700000U) +#define MMDC_MAARCR_ARCR_PAG_HIT_SHIFT (20U) +#define MMDC_MAARCR_ARCR_PAG_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_PAG_HIT_SHIFT)) & MMDC_MAARCR_ARCR_PAG_HIT_MASK) +#define MMDC_MAARCR_ARCR_RCH_EN_MASK (0x1000000U) +#define MMDC_MAARCR_ARCR_RCH_EN_SHIFT (24U) +#define MMDC_MAARCR_ARCR_RCH_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_RCH_EN_SHIFT)) & MMDC_MAARCR_ARCR_RCH_EN_MASK) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK (0x10000000U) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT (28U) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK (0x40000000U) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT (30U) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK (0x80000000U) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT (31U) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK) + +/*! @name MAPSR - MMDC Core Power Saving Control and Status Register */ +#define MMDC_MAPSR_PSD_MASK (0x1U) +#define MMDC_MAPSR_PSD_SHIFT (0U) +#define MMDC_MAPSR_PSD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSD_SHIFT)) & MMDC_MAPSR_PSD_MASK) +#define MMDC_MAPSR_PSS_MASK (0x10U) +#define MMDC_MAPSR_PSS_SHIFT (4U) +#define MMDC_MAPSR_PSS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSS_SHIFT)) & MMDC_MAPSR_PSS_MASK) +#define MMDC_MAPSR_RIS_MASK (0x20U) +#define MMDC_MAPSR_RIS_SHIFT (5U) +#define MMDC_MAPSR_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_RIS_SHIFT)) & MMDC_MAPSR_RIS_MASK) +#define MMDC_MAPSR_WIS_MASK (0x40U) +#define MMDC_MAPSR_WIS_SHIFT (6U) +#define MMDC_MAPSR_WIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_WIS_SHIFT)) & MMDC_MAPSR_WIS_MASK) +#define MMDC_MAPSR_PST_MASK (0xFF00U) +#define MMDC_MAPSR_PST_SHIFT (8U) +#define MMDC_MAPSR_PST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PST_SHIFT)) & MMDC_MAPSR_PST_MASK) +#define MMDC_MAPSR_LPMD_MASK (0x100000U) +#define MMDC_MAPSR_LPMD_SHIFT (20U) +#define MMDC_MAPSR_LPMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPMD_SHIFT)) & MMDC_MAPSR_LPMD_MASK) +#define MMDC_MAPSR_DVFS_MASK (0x200000U) +#define MMDC_MAPSR_DVFS_SHIFT (21U) +#define MMDC_MAPSR_DVFS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVFS_SHIFT)) & MMDC_MAPSR_DVFS_MASK) +#define MMDC_MAPSR_LPACK_MASK (0x1000000U) +#define MMDC_MAPSR_LPACK_SHIFT (24U) +#define MMDC_MAPSR_LPACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPACK_SHIFT)) & MMDC_MAPSR_LPACK_MASK) +#define MMDC_MAPSR_DVACK_MASK (0x2000000U) +#define MMDC_MAPSR_DVACK_SHIFT (25U) +#define MMDC_MAPSR_DVACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVACK_SHIFT)) & MMDC_MAPSR_DVACK_MASK) + +/*! @name MAEXIDR0 - MMDC Core Exclusive ID Monitor Register0 */ +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK (0xFFFFU) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT (0U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK (0xFFFF0000U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT (16U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK) + +/*! @name MAEXIDR1 - MMDC Core Exclusive ID Monitor Register1 */ +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK (0xFFFFU) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT (0U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK (0xFFFF0000U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT (16U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK) + +/*! @name MADPCR0 - MMDC Core Debug and Profiling Control Register 0 */ +#define MMDC_MADPCR0_DBG_EN_MASK (0x1U) +#define MMDC_MADPCR0_DBG_EN_SHIFT (0U) +#define MMDC_MADPCR0_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_EN_SHIFT)) & MMDC_MADPCR0_DBG_EN_MASK) +#define MMDC_MADPCR0_DBG_RST_MASK (0x2U) +#define MMDC_MADPCR0_DBG_RST_SHIFT (1U) +#define MMDC_MADPCR0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_RST_SHIFT)) & MMDC_MADPCR0_DBG_RST_MASK) +#define MMDC_MADPCR0_PRF_FRZ_MASK (0x4U) +#define MMDC_MADPCR0_PRF_FRZ_SHIFT (2U) +#define MMDC_MADPCR0_PRF_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_PRF_FRZ_SHIFT)) & MMDC_MADPCR0_PRF_FRZ_MASK) +#define MMDC_MADPCR0_CYC_OVF_MASK (0x8U) +#define MMDC_MADPCR0_CYC_OVF_SHIFT (3U) +#define MMDC_MADPCR0_CYC_OVF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_CYC_OVF_SHIFT)) & MMDC_MADPCR0_CYC_OVF_MASK) +#define MMDC_MADPCR0_SBS_EN_MASK (0x100U) +#define MMDC_MADPCR0_SBS_EN_SHIFT (8U) +#define MMDC_MADPCR0_SBS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_EN_SHIFT)) & MMDC_MADPCR0_SBS_EN_MASK) +#define MMDC_MADPCR0_SBS_MASK (0x200U) +#define MMDC_MADPCR0_SBS_SHIFT (9U) +#define MMDC_MADPCR0_SBS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_SHIFT)) & MMDC_MADPCR0_SBS_MASK) + +/*! @name MADPCR1 - MMDC Core Debug and Profiling Control Register 1 */ +#define MMDC_MADPCR1_PRF_AXI_ID_MASK (0xFFFFU) +#define MMDC_MADPCR1_PRF_AXI_ID_SHIFT (0U) +#define MMDC_MADPCR1_PRF_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_ID_SHIFT)) & MMDC_MADPCR1_PRF_AXI_ID_MASK) +#define MMDC_MADPCR1_PRF_AXI_IDMASK_MASK (0xFFFF0000U) +#define MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT (16U) +#define MMDC_MADPCR1_PRF_AXI_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT)) & MMDC_MADPCR1_PRF_AXI_IDMASK_MASK) + +/*! @name MADPSR0 - MMDC Core Debug and Profiling Status Register 0 */ +#define MMDC_MADPSR0_CYC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR0_CYC_COUNT_SHIFT (0U) +#define MMDC_MADPSR0_CYC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR0_CYC_COUNT_SHIFT)) & MMDC_MADPSR0_CYC_COUNT_MASK) + +/*! @name MADPSR1 - MMDC Core Debug and Profiling Status Register 1 */ +#define MMDC_MADPSR1_BUSY_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR1_BUSY_COUNT_SHIFT (0U) +#define MMDC_MADPSR1_BUSY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR1_BUSY_COUNT_SHIFT)) & MMDC_MADPSR1_BUSY_COUNT_MASK) + +/*! @name MADPSR2 - MMDC Core Debug and Profiling Status Register 2 */ +#define MMDC_MADPSR2_RD_ACC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR2_RD_ACC_COUNT_SHIFT (0U) +#define MMDC_MADPSR2_RD_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR2_RD_ACC_COUNT_SHIFT)) & MMDC_MADPSR2_RD_ACC_COUNT_MASK) + +/*! @name MADPSR3 - MMDC Core Debug and Profiling Status Register 3 */ +#define MMDC_MADPSR3_WR_ACC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR3_WR_ACC_COUNT_SHIFT (0U) +#define MMDC_MADPSR3_WR_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR3_WR_ACC_COUNT_SHIFT)) & MMDC_MADPSR3_WR_ACC_COUNT_MASK) + +/*! @name MADPSR4 - MMDC Core Debug and Profiling Status Register 4 */ +#define MMDC_MADPSR4_RD_BYTES_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT (0U) +#define MMDC_MADPSR4_RD_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT)) & MMDC_MADPSR4_RD_BYTES_COUNT_MASK) + +/*! @name MADPSR5 - MMDC Core Debug and Profiling Status Register 5 */ +#define MMDC_MADPSR5_WR_BYTES_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT (0U) +#define MMDC_MADPSR5_WR_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT)) & MMDC_MADPSR5_WR_BYTES_COUNT_MASK) + +/*! @name MASBS0 - MMDC Core Step By Step Address Register */ +#define MMDC_MASBS0_SBS_ADDR_MASK (0xFFFFFFFFU) +#define MMDC_MASBS0_SBS_ADDR_SHIFT (0U) +#define MMDC_MASBS0_SBS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS0_SBS_ADDR_SHIFT)) & MMDC_MASBS0_SBS_ADDR_MASK) + +/*! @name MASBS1 - MMDC Core Step By Step Address Attributes Register */ +#define MMDC_MASBS1_SBS_VLD_MASK (0x1U) +#define MMDC_MASBS1_SBS_VLD_SHIFT (0U) +#define MMDC_MASBS1_SBS_VLD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_VLD_SHIFT)) & MMDC_MASBS1_SBS_VLD_MASK) +#define MMDC_MASBS1_SBS_TYPE_MASK (0x2U) +#define MMDC_MASBS1_SBS_TYPE_SHIFT (1U) +#define MMDC_MASBS1_SBS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_TYPE_SHIFT)) & MMDC_MASBS1_SBS_TYPE_MASK) +#define MMDC_MASBS1_SBS_LOCK_MASK (0xCU) +#define MMDC_MASBS1_SBS_LOCK_SHIFT (2U) +#define MMDC_MASBS1_SBS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LOCK_SHIFT)) & MMDC_MASBS1_SBS_LOCK_MASK) +#define MMDC_MASBS1_SBS_PROT_MASK (0x70U) +#define MMDC_MASBS1_SBS_PROT_SHIFT (4U) +#define MMDC_MASBS1_SBS_PROT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_PROT_SHIFT)) & MMDC_MASBS1_SBS_PROT_MASK) +#define MMDC_MASBS1_SBS_SIZE_MASK (0x380U) +#define MMDC_MASBS1_SBS_SIZE_SHIFT (7U) +#define MMDC_MASBS1_SBS_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_SIZE_SHIFT)) & MMDC_MASBS1_SBS_SIZE_MASK) +#define MMDC_MASBS1_SBS_BURST_MASK (0xC00U) +#define MMDC_MASBS1_SBS_BURST_SHIFT (10U) +#define MMDC_MASBS1_SBS_BURST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BURST_SHIFT)) & MMDC_MASBS1_SBS_BURST_MASK) +#define MMDC_MASBS1_SBS_BUFF_MASK (0x1000U) +#define MMDC_MASBS1_SBS_BUFF_SHIFT (12U) +#define MMDC_MASBS1_SBS_BUFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BUFF_SHIFT)) & MMDC_MASBS1_SBS_BUFF_MASK) +#define MMDC_MASBS1_SBS_LEN_MASK (0xE000U) +#define MMDC_MASBS1_SBS_LEN_SHIFT (13U) +#define MMDC_MASBS1_SBS_LEN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LEN_SHIFT)) & MMDC_MASBS1_SBS_LEN_MASK) +#define MMDC_MASBS1_SBS_AXI_ID_MASK (0xFFFF0000U) +#define MMDC_MASBS1_SBS_AXI_ID_SHIFT (16U) +#define MMDC_MASBS1_SBS_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_AXI_ID_SHIFT)) & MMDC_MASBS1_SBS_AXI_ID_MASK) + +/*! @name MAGENP - MMDC Core General Purpose Register */ +#define MMDC_MAGENP_GP31_GP0_MASK (0xFFFFFFFFU) +#define MMDC_MAGENP_GP31_GP0_SHIFT (0U) +#define MMDC_MAGENP_GP31_GP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAGENP_GP31_GP0_SHIFT)) & MMDC_MAGENP_GP31_GP0_MASK) + +/*! @name MPZQHWCTRL - MMDC PHY ZQ HW control register */ +#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK (0x3U) +#define MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT (0U) +#define MMDC_MPZQHWCTRL_ZQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_MODE_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK (0x3CU) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT (2U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK (0x7C0U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT (6U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK (0xF800U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT (11U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK (0x10000U) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT (16U) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK) +#define MMDC_MPZQHWCTRL_TZQ_INIT_MASK (0xE0000U) +#define MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT (17U) +#define MMDC_MPZQHWCTRL_TZQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_INIT_MASK) +#define MMDC_MPZQHWCTRL_TZQ_OPER_MASK (0x700000U) +#define MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT (20U) +#define MMDC_MPZQHWCTRL_TZQ_OPER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_OPER_MASK) +#define MMDC_MPZQHWCTRL_TZQ_CS_MASK (0x3800000U) +#define MMDC_MPZQHWCTRL_TZQ_CS_SHIFT (23U) +#define MMDC_MPZQHWCTRL_TZQ_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_CS_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_CS_MASK) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK (0xF8000000U) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT (27U) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK) + +/*! @name MPZQSWCTRL - MMDC PHY ZQ SW control register */ +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK (0x1U) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT (0U) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK (0x2U) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT (1U) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK (0x7CU) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT (2U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK (0xF80U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT (7U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK (0x1000U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT (12U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK (0x2000U) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT (13U) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT)) & MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK (0x30000U) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT (16U) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK) + +/*! @name MPWLGCR - MMDC PHY Write Leveling Configuration and Error Status Register */ +#define MMDC_MPWLGCR_HW_WL_EN_MASK (0x1U) +#define MMDC_MPWLGCR_HW_WL_EN_SHIFT (0U) +#define MMDC_MPWLGCR_HW_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_HW_WL_EN_SHIFT)) & MMDC_MPWLGCR_HW_WL_EN_MASK) +#define MMDC_MPWLGCR_SW_WL_EN_MASK (0x2U) +#define MMDC_MPWLGCR_SW_WL_EN_SHIFT (1U) +#define MMDC_MPWLGCR_SW_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_SW_WL_EN_SHIFT)) & MMDC_MPWLGCR_SW_WL_EN_MASK) +#define MMDC_MPWLGCR_SW_WL_CNT_EN_MASK (0x4U) +#define MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT (2U) +#define MMDC_MPWLGCR_SW_WL_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT)) & MMDC_MPWLGCR_SW_WL_CNT_EN_MASK) +#define MMDC_MPWLGCR_WL_SW_RES0_MASK (0x10U) +#define MMDC_MPWLGCR_WL_SW_RES0_SHIFT (4U) +#define MMDC_MPWLGCR_WL_SW_RES0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_SW_RES0_SHIFT)) & MMDC_MPWLGCR_WL_SW_RES0_MASK) +#define MMDC_MPWLGCR_WL_SW_RES1_MASK (0x20U) +#define MMDC_MPWLGCR_WL_SW_RES1_SHIFT (5U) +#define MMDC_MPWLGCR_WL_SW_RES1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_SW_RES1_SHIFT)) & MMDC_MPWLGCR_WL_SW_RES1_MASK) +#define MMDC_MPWLGCR_WL_HW_ERR0_MASK (0x100U) +#define MMDC_MPWLGCR_WL_HW_ERR0_SHIFT (8U) +#define MMDC_MPWLGCR_WL_HW_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_HW_ERR0_SHIFT)) & MMDC_MPWLGCR_WL_HW_ERR0_MASK) +#define MMDC_MPWLGCR_WL_HW_ERR1_MASK (0x200U) +#define MMDC_MPWLGCR_WL_HW_ERR1_SHIFT (9U) +#define MMDC_MPWLGCR_WL_HW_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_HW_ERR1_SHIFT)) & MMDC_MPWLGCR_WL_HW_ERR1_MASK) + +/*! @name MPWLDECTRL0 - MMDC PHY Write Leveling Delay Control Register 0 */ +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK (0x100U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT (8U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT)) & MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK (0x600U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT (9U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT)) & MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK (0x7F0000U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT (16U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK (0x1000000U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT (24U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT)) & MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK (0x6000000U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT (25U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT)) & MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK) + +/*! @name MPWLDECTRL1 - MMDC PHY Write Leveling Delay Control Register 1 */ +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK (0x7FU) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT (0U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT)) & MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK (0x100U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT (8U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT)) & MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK (0x600U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT (9U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT)) & MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK (0x7F0000U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT (16U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT)) & MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK (0x1000000U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT (24U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT)) & MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK (0x6000000U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT (25U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT)) & MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK) + +/*! @name MPWLDLST - MMDC PHY Write Leveling delay-line Status Register */ +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT)) & MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT)) & MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK) + +/*! @name MPODTCTRL - MMDC PHY ODT control register */ +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK (0x1U) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT (0U) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK (0x2U) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT (1U) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK (0x4U) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT (2U) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK (0x8U) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT (3U) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK) +#define MMDC_MPODTCTRL_ODT0_INT_RES_MASK (0x70U) +#define MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT (4U) +#define MMDC_MPODTCTRL_ODT0_INT_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT)) & MMDC_MPODTCTRL_ODT0_INT_RES_MASK) +#define MMDC_MPODTCTRL_ODT1_INT_RES_MASK (0x700U) +#define MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT (8U) +#define MMDC_MPODTCTRL_ODT1_INT_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT)) & MMDC_MPODTCTRL_ODT1_INT_RES_MASK) + +/*! @name MPRDDQBY0DL - MMDC PHY Read DQ Byte0 Delay Register */ +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL_MASK (0x7U) +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL_SHIFT (0U) +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ0_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ0_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL_MASK (0x70U) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL_SHIFT (4U) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ1_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ1_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL_MASK (0x700U) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL_SHIFT (8U) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ2_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ2_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL_MASK (0x7000U) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL_SHIFT (12U) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ3_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ3_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL_MASK (0x70000U) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL_SHIFT (16U) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ4_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ4_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL_MASK (0x700000U) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL_SHIFT (20U) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ5_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ5_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL_MASK (0x7000000U) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL_SHIFT (24U) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ6_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ6_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL_MASK (0x70000000U) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL_SHIFT (28U) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ7_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ7_DEL_MASK) + +/*! @name MPRDDQBY1DL - MMDC PHY Read DQ Byte1 Delay Register */ +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL_MASK (0x7U) +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL_SHIFT (0U) +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ8_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ8_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL_MASK (0x70U) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL_SHIFT (4U) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ9_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ9_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL_MASK (0x700U) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL_SHIFT (8U) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ10_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ10_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL_MASK (0x7000U) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL_SHIFT (12U) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ11_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ11_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL_MASK (0x70000U) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL_SHIFT (16U) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ12_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ12_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL_MASK (0x700000U) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL_SHIFT (20U) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ13_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ13_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL_MASK (0x7000000U) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL_SHIFT (24U) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ14_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ14_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL_MASK (0x70000000U) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL_SHIFT (28U) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ15_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ15_DEL_MASK) + +/*! @name MPWRDQBY0DL - MMDC PHY Write DQ Byte0 Delay Register */ +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ0_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ1_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ2_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ3_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ4_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ5_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ6_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ7_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DM0_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK) + +/*! @name MPWRDQBY1DL - MMDC PHY Write DQ Byte1 Delay Register */ +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ8_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ9_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ10_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ11_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ12_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ13_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ14_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ15_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DM1_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK) + +/*! @name MPWRDQBY2DL - MMDC PHY Write DQ Byte2 Delay Register */ +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ16_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ17_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ18_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ19_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ20_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ21_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ22_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ23_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DM2_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK) + +/*! @name MPWRDQBY3DL - MMDC PHY Write DQ Byte3 Delay Register */ +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ24_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ25_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ26_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ27_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ28_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ29_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ30_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ31_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DM3_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK) + +/*! @name MPDGCTRL0 - MMDC PHY Read DQS Gating Control Register 0 */ +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK) +#define MMDC_MPDGCTRL0_DG_HC_DEL0_MASK (0xF00U) +#define MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT (8U) +#define MMDC_MPDGCTRL0_DG_HC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT)) & MMDC_MPDGCTRL0_DG_HC_DEL0_MASK) +#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK (0x1000U) +#define MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT (12U) +#define MMDC_MPDGCTRL0_HW_DG_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT)) & MMDC_MPDGCTRL0_HW_DG_ERR_MASK) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK (0x7F0000U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT (16U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK) +#define MMDC_MPDGCTRL0_DG_EXT_UP_MASK (0x800000U) +#define MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT (23U) +#define MMDC_MPDGCTRL0_DG_EXT_UP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT)) & MMDC_MPDGCTRL0_DG_EXT_UP_MASK) +#define MMDC_MPDGCTRL0_DG_HC_DEL1_MASK (0xF000000U) +#define MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT (24U) +#define MMDC_MPDGCTRL0_DG_HC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT)) & MMDC_MPDGCTRL0_DG_HC_DEL1_MASK) +#define MMDC_MPDGCTRL0_HW_DG_EN_MASK (0x10000000U) +#define MMDC_MPDGCTRL0_HW_DG_EN_SHIFT (28U) +#define MMDC_MPDGCTRL0_HW_DG_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_HW_DG_EN_SHIFT)) & MMDC_MPDGCTRL0_HW_DG_EN_MASK) +#define MMDC_MPDGCTRL0_DG_DIS_MASK (0x20000000U) +#define MMDC_MPDGCTRL0_DG_DIS_SHIFT (29U) +#define MMDC_MPDGCTRL0_DG_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DIS_SHIFT)) & MMDC_MPDGCTRL0_DG_DIS_MASK) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK (0x40000000U) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT (30U) +#define MMDC_MPDGCTRL0_DG_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT)) & MMDC_MPDGCTRL0_DG_CMP_CYC_MASK) +#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK (0x80000000U) +#define MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT (31U) +#define MMDC_MPDGCTRL0_RST_RD_FIFO(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT)) & MMDC_MPDGCTRL0_RST_RD_FIFO_MASK) + +/*! @name MPDGDLST0 - MMDC PHY Read DQS Gating delay-line Status Register */ +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT)) & MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT)) & MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK) + +/*! @name MPRDDLCTL - MMDC PHY Read delay-lines Configuration Register */ +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK (0x7F00U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT (8U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK) + +/*! @name MPRDDLST - MMDC PHY Read delay-lines Status Register */ +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK) + +/*! @name MPWRDLCTL - MMDC PHY Write delay-lines Configuration Register */ +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK (0x7F00U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT (8U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK) + +/*! @name MPWRDLST - MMDC PHY Write delay-lines Status Register */ +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK) + +/*! @name MPSDCTRL - MMDC PHY CK Control Register */ +#define MMDC_MPSDCTRL_SDCLK0_DEL_MASK (0x300U) +#define MMDC_MPSDCTRL_SDCLK0_DEL_SHIFT (8U) +#define MMDC_MPSDCTRL_SDCLK0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSDCTRL_SDCLK0_DEL_SHIFT)) & MMDC_MPSDCTRL_SDCLK0_DEL_MASK) +#define MMDC_MPSDCTRL_SDCLK1_DEL_MASK (0xC00U) +#define MMDC_MPSDCTRL_SDCLK1_DEL_SHIFT (10U) +#define MMDC_MPSDCTRL_SDCLK1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSDCTRL_SDCLK1_DEL_SHIFT)) & MMDC_MPSDCTRL_SDCLK1_DEL_MASK) + +/*! @name MPZQLP2CTL - MMDC ZQ LPDDR2 HW Control Register */ +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK (0x1FFU) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT (0U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK (0xFF0000U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT (16U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK (0x7F000000U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT (24U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK) + +/*! @name MPRDDLHWCTL - MMDC PHY Read Delay HW Calibration Control Register */ +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK (0x1U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT (0U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK (0x2U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT (1U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK (0x10U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT (4U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK (0x20U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT (5U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK) + +/*! @name MPWRDLHWCTL - MMDC PHY Write Delay HW Calibration Control Register */ +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK (0x1U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT (0U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK (0x2U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT (1U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK (0x10U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT (4U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK (0x20U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT (5U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK) + +/*! @name MPRDDLHWST0 - MMDC PHY Read Delay HW Calibration Status Register 0 */ +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK (0x7FU) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT (0U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK (0x7F00U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT (8U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK (0x7F0000U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT (16U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK (0x7F000000U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT (24U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK) + +/*! @name MPWRDLHWST0 - MMDC PHY Write Delay HW Calibration Status Register 0 */ +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK (0x7FU) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT (0U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK (0x7F00U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT (8U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK (0x7F0000U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT (16U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK (0x7F000000U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT (24U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK) + +/*! @name MPWLHWERR - MMDC PHY Write Leveling HW Error Register */ +#define MMDC_MPWLHWERR_HW_WL0_DQ_MASK (0xFFU) +#define MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT (0U) +#define MMDC_MPWLHWERR_HW_WL0_DQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT)) & MMDC_MPWLHWERR_HW_WL0_DQ_MASK) +#define MMDC_MPWLHWERR_HW_WL1_DQ_MASK (0xFF00U) +#define MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT (8U) +#define MMDC_MPWLHWERR_HW_WL1_DQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT)) & MMDC_MPWLHWERR_HW_WL1_DQ_MASK) + +/*! @name MPDGHWST0 - MMDC PHY Read DQS Gating HW Status Register 0 */ +#define MMDC_MPDGHWST0_HW_DG_LOW0_MASK (0x7FFU) +#define MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT (0U) +#define MMDC_MPDGHWST0_HW_DG_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT)) & MMDC_MPDGHWST0_HW_DG_LOW0_MASK) +#define MMDC_MPDGHWST0_HW_DG_UP0_MASK (0x7FF0000U) +#define MMDC_MPDGHWST0_HW_DG_UP0_SHIFT (16U) +#define MMDC_MPDGHWST0_HW_DG_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST0_HW_DG_UP0_SHIFT)) & MMDC_MPDGHWST0_HW_DG_UP0_MASK) + +/*! @name MPDGHWST1 - MMDC PHY Read DQS Gating HW Status Register 1 */ +#define MMDC_MPDGHWST1_HW_DG_LOW1_MASK (0x7FFU) +#define MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT (0U) +#define MMDC_MPDGHWST1_HW_DG_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT)) & MMDC_MPDGHWST1_HW_DG_LOW1_MASK) +#define MMDC_MPDGHWST1_HW_DG_UP1_MASK (0x7FF0000U) +#define MMDC_MPDGHWST1_HW_DG_UP1_SHIFT (16U) +#define MMDC_MPDGHWST1_HW_DG_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST1_HW_DG_UP1_SHIFT)) & MMDC_MPDGHWST1_HW_DG_UP1_MASK) + +/*! @name MPPDCMPR1 - MMDC PHY Pre-defined Compare Register 1 */ +#define MMDC_MPPDCMPR1_PDV1_MASK (0xFFFFU) +#define MMDC_MPPDCMPR1_PDV1_SHIFT (0U) +#define MMDC_MPPDCMPR1_PDV1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV1_SHIFT)) & MMDC_MPPDCMPR1_PDV1_MASK) +#define MMDC_MPPDCMPR1_PDV2_MASK (0xFFFF0000U) +#define MMDC_MPPDCMPR1_PDV2_SHIFT (16U) +#define MMDC_MPPDCMPR1_PDV2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV2_SHIFT)) & MMDC_MPPDCMPR1_PDV2_MASK) + +/*! @name MPPDCMPR2 - MMDC PHY Pre-defined Compare and CA delay-line Configuration Register */ +#define MMDC_MPPDCMPR2_MPR_CMP_MASK (0x1U) +#define MMDC_MPPDCMPR2_MPR_CMP_SHIFT (0U) +#define MMDC_MPPDCMPR2_MPR_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_CMP_MASK) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK (0x2U) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT (1U) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK (0x4U) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT (2U) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT)) & MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK (0x8U) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT (3U) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT)) & MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK (0xF0U) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT (4U) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK (0xF00U) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT (8U) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK (0x7F0000U) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT (16U) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK (0x7F000000U) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT (24U) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT)) & MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK) + +/*! @name MPSWDAR0 - MMDC PHY SW Dummy Access Register */ +#define MMDC_MPSWDAR0_SW_DUMMY_WR_MASK (0x1U) +#define MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT (0U) +#define MMDC_MPSWDAR0_SW_DUMMY_WR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_WR_MASK) +#define MMDC_MPSWDAR0_SW_DUMMY_RD_MASK (0x2U) +#define MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT (1U) +#define MMDC_MPSWDAR0_SW_DUMMY_RD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_RD_MASK) +#define MMDC_MPSWDAR0_SW_DUM_CMP0_MASK (0x4U) +#define MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT (2U) +#define MMDC_MPSWDAR0_SW_DUM_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP0_MASK) +#define MMDC_MPSWDAR0_SW_DUM_CMP1_MASK (0x8U) +#define MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT (3U) +#define MMDC_MPSWDAR0_SW_DUM_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP1_MASK) + +/*! @name MPSWDRDR0 - MMDC PHY SW Dummy Read Data Register 0 */ +#define MMDC_MPSWDRDR0_DUM_RD0_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR0_DUM_RD0_SHIFT (0U) +#define MMDC_MPSWDRDR0_DUM_RD0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR0_DUM_RD0_SHIFT)) & MMDC_MPSWDRDR0_DUM_RD0_MASK) + +/*! @name MPSWDRDR1 - MMDC PHY SW Dummy Read Data Register 1 */ +#define MMDC_MPSWDRDR1_DUM_RD1_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR1_DUM_RD1_SHIFT (0U) +#define MMDC_MPSWDRDR1_DUM_RD1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR1_DUM_RD1_SHIFT)) & MMDC_MPSWDRDR1_DUM_RD1_MASK) + +/*! @name MPSWDRDR2 - MMDC PHY SW Dummy Read Data Register 2 */ +#define MMDC_MPSWDRDR2_DUM_RD2_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR2_DUM_RD2_SHIFT (0U) +#define MMDC_MPSWDRDR2_DUM_RD2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR2_DUM_RD2_SHIFT)) & MMDC_MPSWDRDR2_DUM_RD2_MASK) + +/*! @name MPSWDRDR3 - MMDC PHY SW Dummy Read Data Register 3 */ +#define MMDC_MPSWDRDR3_DUM_RD3_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR3_DUM_RD3_SHIFT (0U) +#define MMDC_MPSWDRDR3_DUM_RD3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR3_DUM_RD3_SHIFT)) & MMDC_MPSWDRDR3_DUM_RD3_MASK) + +/*! @name MPSWDRDR4 - MMDC PHY SW Dummy Read Data Register 4 */ +#define MMDC_MPSWDRDR4_DUM_RD4_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR4_DUM_RD4_SHIFT (0U) +#define MMDC_MPSWDRDR4_DUM_RD4(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR4_DUM_RD4_SHIFT)) & MMDC_MPSWDRDR4_DUM_RD4_MASK) + +/*! @name MPSWDRDR5 - MMDC PHY SW Dummy Read Data Register 5 */ +#define MMDC_MPSWDRDR5_DUM_RD5_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR5_DUM_RD5_SHIFT (0U) +#define MMDC_MPSWDRDR5_DUM_RD5(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR5_DUM_RD5_SHIFT)) & MMDC_MPSWDRDR5_DUM_RD5_MASK) + +/*! @name MPSWDRDR6 - MMDC PHY SW Dummy Read Data Register 6 */ +#define MMDC_MPSWDRDR6_DUM_RD6_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR6_DUM_RD6_SHIFT (0U) +#define MMDC_MPSWDRDR6_DUM_RD6(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR6_DUM_RD6_SHIFT)) & MMDC_MPSWDRDR6_DUM_RD6_MASK) + +/*! @name MPSWDRDR7 - MMDC PHY SW Dummy Read Data Register 7 */ +#define MMDC_MPSWDRDR7_DUM_RD7_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR7_DUM_RD7_SHIFT (0U) +#define MMDC_MPSWDRDR7_DUM_RD7(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR7_DUM_RD7_SHIFT)) & MMDC_MPSWDRDR7_DUM_RD7_MASK) + +/*! @name MPMUR0 - MMDC PHY Measure Unit Register */ +#define MMDC_MPMUR0_MU_BYP_VAL_MASK (0x3FFU) +#define MMDC_MPMUR0_MU_BYP_VAL_SHIFT (0U) +#define MMDC_MPMUR0_MU_BYP_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_VAL_SHIFT)) & MMDC_MPMUR0_MU_BYP_VAL_MASK) +#define MMDC_MPMUR0_MU_BYP_EN_MASK (0x400U) +#define MMDC_MPMUR0_MU_BYP_EN_SHIFT (10U) +#define MMDC_MPMUR0_MU_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_EN_SHIFT)) & MMDC_MPMUR0_MU_BYP_EN_MASK) +#define MMDC_MPMUR0_FRC_MSR_MASK (0x800U) +#define MMDC_MPMUR0_FRC_MSR_SHIFT (11U) +#define MMDC_MPMUR0_FRC_MSR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_FRC_MSR_SHIFT)) & MMDC_MPMUR0_FRC_MSR_MASK) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK (0x3FF0000U) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT (16U) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT)) & MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK) + +/*! @name MPWRCADL - MMDC Write CA delay-line controller */ +#define MMDC_MPWRCADL_WR_CA0_DEL_MASK (0x3U) +#define MMDC_MPWRCADL_WR_CA0_DEL_SHIFT (0U) +#define MMDC_MPWRCADL_WR_CA0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA0_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA0_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA1_DEL_MASK (0xCU) +#define MMDC_MPWRCADL_WR_CA1_DEL_SHIFT (2U) +#define MMDC_MPWRCADL_WR_CA1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA1_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA1_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA2_DEL_MASK (0x30U) +#define MMDC_MPWRCADL_WR_CA2_DEL_SHIFT (4U) +#define MMDC_MPWRCADL_WR_CA2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA2_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA2_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA3_DEL_MASK (0xC0U) +#define MMDC_MPWRCADL_WR_CA3_DEL_SHIFT (6U) +#define MMDC_MPWRCADL_WR_CA3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA3_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA3_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA4_DEL_MASK (0x300U) +#define MMDC_MPWRCADL_WR_CA4_DEL_SHIFT (8U) +#define MMDC_MPWRCADL_WR_CA4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA4_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA4_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA5_DEL_MASK (0xC00U) +#define MMDC_MPWRCADL_WR_CA5_DEL_SHIFT (10U) +#define MMDC_MPWRCADL_WR_CA5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA5_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA5_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA6_DEL_MASK (0x3000U) +#define MMDC_MPWRCADL_WR_CA6_DEL_SHIFT (12U) +#define MMDC_MPWRCADL_WR_CA6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA6_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA6_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA7_DEL_MASK (0xC000U) +#define MMDC_MPWRCADL_WR_CA7_DEL_SHIFT (14U) +#define MMDC_MPWRCADL_WR_CA7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA7_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA7_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA8_DEL_MASK (0x30000U) +#define MMDC_MPWRCADL_WR_CA8_DEL_SHIFT (16U) +#define MMDC_MPWRCADL_WR_CA8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA8_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA8_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA9_DEL_MASK (0xC0000U) +#define MMDC_MPWRCADL_WR_CA9_DEL_SHIFT (18U) +#define MMDC_MPWRCADL_WR_CA9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA9_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA9_DEL_MASK) + +/*! @name MPDCCR - MMDC Duty Cycle Control Register */ +#define MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK (0x7U) +#define MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT (0U) +#define MMDC_MPDCCR_WR_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK (0x38U) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT (3U) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK) +#define MMDC_MPDCCR_CK_FT0_DCC_MASK (0x7000U) +#define MMDC_MPDCCR_CK_FT0_DCC_SHIFT (12U) +#define MMDC_MPDCCR_CK_FT0_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT0_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT0_DCC_MASK) +#define MMDC_MPDCCR_CK_FT1_DCC_MASK (0x70000U) +#define MMDC_MPDCCR_CK_FT1_DCC_SHIFT (16U) +#define MMDC_MPDCCR_CK_FT1_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT1_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT1_DCC_MASK) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK (0x380000U) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT (19U) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK (0x1C00000U) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT (22U) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK) + + +/*! + * @} + */ /* end of group MMDC_Register_Masks */ + + +/* MMDC - Peripheral instance base addresses */ +/** Peripheral MMDC base address */ +#define MMDC_BASE (0x21B0000u) +/** Peripheral MMDC base pointer */ +#define MMDC ((MMDC_Type *)MMDC_BASE) +/** Array initializer of MMDC peripheral base addresses */ +#define MMDC_BASE_ADDRS { MMDC_BASE } +/** Array initializer of MMDC peripheral base pointers */ +#define MMDC_BASE_PTRS { MMDC } +/* MMDC max frequency (MHz). */ +#define MMDC_MAX_FREQUENCY (400) +/* MMDC device start address. */ +#define MMDC_DEVICE_START_ADDRESS (0x80000000U) + + +/*! + * @} + */ /* end of group MMDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Read Control Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Fuse Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + __IO uint32_t CRC_ADDR; /**< OTP Controller CRC Test Address, offset: 0x70 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CRC_VALUE; /**< OTP Controller CRC Value Register, offset: 0x80 */ + uint8_t RESERVED_6[12]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_7[108]; + __IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */ + uint8_t RESERVED_8[764]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ + uint8_t RESERVED_16[12]; + __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t OTPMK0; /**< Value of OTP Bank2 Word0 (OTPMK Key), offset: 0x500 */ + uint8_t RESERVED_25[12]; + __IO uint32_t OTPMK1; /**< Value of OTP Bank2 Word1 (OTPMK Key), offset: 0x510 */ + uint8_t RESERVED_26[12]; + __IO uint32_t OTPMK2; /**< Value of OTP Bank2 Word2 (OTPMK Key), offset: 0x520 */ + uint8_t RESERVED_27[12]; + __IO uint32_t OTPMK3; /**< Value of OTP Bank2 Word3 (OTPMK Key), offset: 0x530 */ + uint8_t RESERVED_28[12]; + __IO uint32_t OTPMK4; /**< Value of OTP Bank2 Word4 (OTPMK Key), offset: 0x540 */ + uint8_t RESERVED_29[12]; + __IO uint32_t OTPMK5; /**< Value of OTP Bank2 Word5 (OTPMK Key), offset: 0x550 */ + uint8_t RESERVED_30[12]; + __IO uint32_t OTPMK6; /**< Value of OTP Bank2 Word6 (OTPMK Key), offset: 0x560 */ + uint8_t RESERVED_31[12]; + __IO uint32_t OTPMK7; /**< Value of OTP Bank2 Word7 (OTPMK Key), offset: 0x570 */ + uint8_t RESERVED_32[12]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_33[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_34[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_35[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_36[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_37[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_42[12]; + __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MAC; /**< Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED), offset: 0x640 */ + uint8_t RESERVED_45[12]; + __IO uint32_t CRC; /**< Value of OTP Bank4 Word5 (CRC Key), offset: 0x650 */ + uint8_t RESERVED_46[12]; + __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ + uint8_t RESERVED_47[12]; + __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ + uint8_t RESERVED_48[12]; + __IO uint32_t SW_GP0; /**< Value of OTP Bank5 Word0 (SW GP), offset: 0x680 */ + uint8_t RESERVED_49[12]; + __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word1 (SW GP), offset: 0x690 */ + uint8_t RESERVED_50[12]; + __IO uint32_t SW_GP2; /**< Value of OTP Bank5 Word2 (SW GP), offset: 0x6A0 */ + uint8_t RESERVED_51[12]; + __IO uint32_t SW_GP3; /**< Value of OTP Bank5 Word3 (SW GP), offset: 0x6B0 */ + uint8_t RESERVED_52[12]; + __IO uint32_t SW_GP4; /**< Value of OTP Bank5 Word4 (SW GP), offset: 0x6C0 */ + uint8_t RESERVED_53[12]; + __IO uint32_t MISC_CONF; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ + uint8_t RESERVED_54[12]; + __IO uint32_t FIELD_RETURN; /**< Value of OTP Bank5 Word6 (Field Return), offset: 0x6E0 */ + uint8_t RESERVED_55[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ + uint8_t RESERVED_56[268]; + __IO uint32_t ROM_PATCH0; /**< Value of OTP Bank6 Word0 (ROM Patch), offset: 0x800 */ + uint8_t RESERVED_57[12]; + __IO uint32_t ROM_PATCH1; /**< Value of OTP Bank6 Word1 (ROM Patch), offset: 0x810 */ + uint8_t RESERVED_58[12]; + __IO uint32_t ROM_PATCH2; /**< Value of OTP Bank6 Word2 (ROM Patch), offset: 0x820 */ + uint8_t RESERVED_59[12]; + __IO uint32_t ROM_PATCH3; /**< Value of OTP Bank6 Word3 (ROM Patch), offset: 0x830 */ + uint8_t RESERVED_60[12]; + __IO uint32_t ROM_PATCH4; /**< Value of OTP Bank6 Word4 (ROM Patch), offset: 0x840 */ + uint8_t RESERVED_61[12]; + __IO uint32_t ROM_PATCH5; /**< Value of OTP Bank6 Word5 (ROM Patch), offset: 0x850 */ + uint8_t RESERVED_62[12]; + __IO uint32_t ROM_PATCH6; /**< Value of OTP Bank6 Word6 (ROM Patch), offset: 0x860 */ + uint8_t RESERVED_63[12]; + __IO uint32_t ROM_PATCH7; /**< Value of OTP Bank6 Word7 (ROM Patch), offset: 0x870 */ + uint8_t RESERVED_64[12]; + __IO uint32_t GP3_0; /**< Value of OTP Bank7 Word0 (General Purpose Customer Defined Info), offset: 0x880 */ + uint8_t RESERVED_65[12]; + __IO uint32_t GP3_1; /**< Value of OTP Bank7 Word1 (General Purpose Customer Defined Info), offset: 0x890 */ + uint8_t RESERVED_66[12]; + __IO uint32_t GP3_2; /**< Value of OTP Bank7 Word2 (General Purpose Customer Defined Info), offset: 0x8A0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t GP3_3; /**< Value of OTP Bank7 Word3 (General Purpose Customer Defined Info), offset: 0x8B0 */ + uint8_t RESERVED_68[12]; + __IO uint32_t GP3_4; /**< Value of OTP Bank8 Word4 (General Purpose Customer Defined Info), offset: 0x8C0 */ + uint8_t RESERVED_69[12]; + __IO uint32_t GP4_0; /**< Value of OTP Bank7 Word5 (General Purpose Customer Defined Info), offset: 0x8D0 */ + uint8_t RESERVED_70[12]; + __IO uint32_t GP4_1; /**< Value of OTP Bank7 Word6 (General Purpose Customer Defined Info), offset: 0x8E0 */ + uint8_t RESERVED_71[12]; + __IO uint32_t GP4_2; /**< Value of OTP Bank7 Word7 (General Purpose Customer Defined Info), offset: 0x8F0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +#define OCOTP_CTRL_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD0_SHIFT)) & OCOTP_CTRL_RSVD0_MASK) +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_CTRL_CRC_TEST_MASK) +#define OCOTP_CTRL_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CRC_FAIL_MASK) +#define OCOTP_CTRL_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD1_SHIFT)) & OCOTP_CTRL_RSVD1_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) + +/*! @name CTRL_SET - OTP Controller Control Register */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_SET_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD0_SHIFT)) & OCOTP_CTRL_SET_RSVD0_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_SET_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_SET_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_SET_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_TEST_SHIFT)) & OCOTP_CTRL_SET_CRC_TEST_MASK) +#define OCOTP_CTRL_SET_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_SET_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_SET_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_FAIL_SHIFT)) & OCOTP_CTRL_SET_CRC_FAIL_MASK) +#define OCOTP_CTRL_SET_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_SET_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD1_SHIFT)) & OCOTP_CTRL_SET_RSVD1_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) + +/*! @name CTRL_CLR - OTP Controller Control Register */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_CLR_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD0_SHIFT)) & OCOTP_CTRL_CLR_RSVD0_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CLR_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CLR_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CLR_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_TEST_SHIFT)) & OCOTP_CTRL_CLR_CRC_TEST_MASK) +#define OCOTP_CTRL_CLR_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CLR_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CLR_CRC_FAIL_MASK) +#define OCOTP_CTRL_CLR_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_CLR_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD1_SHIFT)) & OCOTP_CTRL_CLR_RSVD1_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) + +/*! @name CTRL_TOG - OTP Controller Control Register */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_TOG_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD0_SHIFT)) & OCOTP_CTRL_TOG_RSVD0_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_TOG_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_TOG_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_TOG_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_TEST_SHIFT)) & OCOTP_CTRL_TOG_CRC_TEST_MASK) +#define OCOTP_CTRL_TOG_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_TOG_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_FAIL_SHIFT)) & OCOTP_CTRL_TOG_CRC_FAIL_MASK) +#define OCOTP_CTRL_TOG_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_TOG_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD1_SHIFT)) & OCOTP_CTRL_TOG_RSVD1_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) + +/*! @name TIMING - OTP Controller Timing Register */ +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +#define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U) +#define OCOTP_TIMING_RSRVD0_SHIFT (28U) +#define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK) + +/*! @name DATA - OTP Controller Write Data Register */ +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) + +/*! @name READ_CTRL - OTP Controller Read Control Register */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +#define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU) +#define OCOTP_READ_CTRL_RSVD0_SHIFT (1U) +#define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK) + +/*! @name READ_FUSE_DATA - OTP Controller Read Fuse Data Register */ +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) + +/*! @name SW_STICKY - Sticky bit Register */ +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) +#define OCOTP_SW_STICKY_RSVD0_MASK (0xFFFFFFE0U) +#define OCOTP_SW_STICKY_RSVD0_SHIFT (5U) +#define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK) + +/*! @name SCS - Software Controllable Signals Register */ +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) + +/*! @name SCS_SET - Software Controllable Signals Register */ +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) + +/*! @name SCS_CLR - Software Controllable Signals Register */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) + +/*! @name SCS_TOG - Software Controllable Signals Register */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) + +/*! @name CRC_ADDR - OTP Controller CRC Test Address */ +#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xFFU) +#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0U) +#define OCOTP_CRC_ADDR_DATA_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_START_ADDR_MASK) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xFF00U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_END_ADDR_MASK) +#define OCOTP_CRC_ADDR_CRC_ADDR_MASK (0x70000U) +#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16U) +#define OCOTP_CRC_ADDR_CRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)) & OCOTP_CRC_ADDR_CRC_ADDR_MASK) +#define OCOTP_CRC_ADDR_OTPMK_CRC_MASK (0x80000U) +#define OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT (19U) +#define OCOTP_CRC_ADDR_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT)) & OCOTP_CRC_ADDR_OTPMK_CRC_MASK) +#define OCOTP_CRC_ADDR_RSVD0_MASK (0xFFF00000U) +#define OCOTP_CRC_ADDR_RSVD0_SHIFT (20U) +#define OCOTP_CRC_ADDR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_RSVD0_SHIFT)) & OCOTP_CRC_ADDR_RSVD0_MASK) + +/*! @name CRC_VALUE - OTP Controller CRC Value Register */ +#define OCOTP_CRC_VALUE_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_CRC_VALUE_DATA_SHIFT (0U) +#define OCOTP_CRC_VALUE_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_VALUE_DATA_SHIFT)) & OCOTP_CRC_VALUE_DATA_MASK) + +/*! @name VERSION - OTP Controller Version Register */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) + +/*! @name TIMING2 - OTP Controller Timing Register 2 */ +#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) +#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) +#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) +#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) +#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) +#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) +#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) +#define OCOTP_TIMING2_RELAX1_SHIFT (22U) +#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) +#define OCOTP_LOCK_RSVD0_MASK (0x80U) +#define OCOTP_LOCK_RSVD0_SHIFT (7U) +#define OCOTP_LOCK_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_RSVD0_SHIFT)) & OCOTP_LOCK_RSVD0_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_GP1_MASK (0xC00U) +#define OCOTP_LOCK_GP1_SHIFT (10U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK (0x3000U) +#define OCOTP_LOCK_GP2_SHIFT (12U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_SRK_MASK (0x4000U) +#define OCOTP_LOCK_SRK_SHIFT (14U) +#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) +#define OCOTP_LOCK_GP3_MASK (0x8000U) +#define OCOTP_LOCK_GP3_SHIFT (15U) +#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) +#define OCOTP_LOCK_SW_GP_MASK (0x10000U) +#define OCOTP_LOCK_SW_GP_SHIFT (16U) +#define OCOTP_LOCK_SW_GP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP_SHIFT)) & OCOTP_LOCK_SW_GP_MASK) +#define OCOTP_LOCK_OTPMK_MASK (0x20000U) +#define OCOTP_LOCK_OTPMK_SHIFT (17U) +#define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK) +#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) +#define OCOTP_LOCK_ANALOG_SHIFT (18U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) +#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) +#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) +#define OCOTP_LOCK_ROM_PATCH_MASK (0x200000U) +#define OCOTP_LOCK_ROM_PATCH_SHIFT (21U) +#define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK) +#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) +#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) +#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) +#define OCOTP_LOCK_GP4_MASK (0x800000U) +#define OCOTP_LOCK_GP4_SHIFT (23U) +#define OCOTP_LOCK_GP4(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_SHIFT)) & OCOTP_LOCK_GP4_MASK) +#define OCOTP_LOCK_PIN_MASK (0x2000000U) +#define OCOTP_LOCK_PIN_SHIFT (25U) +#define OCOTP_LOCK_PIN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_PIN_SHIFT)) & OCOTP_LOCK_PIN_MASK) +#define OCOTP_LOCK_GP4_RLOCK_MASK (0x40000000U) +#define OCOTP_LOCK_GP4_RLOCK_SHIFT (30U) +#define OCOTP_LOCK_GP4_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_RLOCK_SHIFT)) & OCOTP_LOCK_GP4_RLOCK_MASK) +#define OCOTP_LOCK_GP3_RLOCK_MASK (0x80000000U) +#define OCOTP_LOCK_GP3_RLOCK_SHIFT (31U) +#define OCOTP_LOCK_GP3_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_RLOCK_SHIFT)) & OCOTP_LOCK_GP3_RLOCK_MASK) + +/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG0_BITS_SHIFT (0U) +#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) + +/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG1_BITS_SHIFT (0U) +#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) + +/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG2_BITS_SHIFT (0U) +#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) + +/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG3_BITS_SHIFT (0U) +#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) + +/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG4_BITS_SHIFT (0U) +#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) + +/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG5_BITS_SHIFT (0U) +#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) + +/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG6_BITS_SHIFT (0U) +#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) + +/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM0_BITS_SHIFT (0U) +#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) + +/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM1_BITS_SHIFT (0U) +#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) + +/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM2_BITS_SHIFT (0U) +#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) + +/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM3_BITS_SHIFT (0U) +#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) + +/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM4_BITS_SHIFT (0U) +#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) + +/*! @name ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) */ +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) + +/*! @name ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) */ +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) + +/*! @name ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) */ +#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA2_BITS_SHIFT (0U) +#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) + +/*! @name OTPMK0 - Value of OTP Bank2 Word0 (OTPMK Key) */ +#define OCOTP_OTPMK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK0_BITS_SHIFT (0U) +#define OCOTP_OTPMK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK0_BITS_SHIFT)) & OCOTP_OTPMK0_BITS_MASK) + +/*! @name OTPMK1 - Value of OTP Bank2 Word1 (OTPMK Key) */ +#define OCOTP_OTPMK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK1_BITS_SHIFT (0U) +#define OCOTP_OTPMK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK1_BITS_SHIFT)) & OCOTP_OTPMK1_BITS_MASK) + +/*! @name OTPMK2 - Value of OTP Bank2 Word2 (OTPMK Key) */ +#define OCOTP_OTPMK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK2_BITS_SHIFT (0U) +#define OCOTP_OTPMK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK2_BITS_SHIFT)) & OCOTP_OTPMK2_BITS_MASK) + +/*! @name OTPMK3 - Value of OTP Bank2 Word3 (OTPMK Key) */ +#define OCOTP_OTPMK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK3_BITS_SHIFT (0U) +#define OCOTP_OTPMK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK3_BITS_SHIFT)) & OCOTP_OTPMK3_BITS_MASK) + +/*! @name OTPMK4 - Value of OTP Bank2 Word4 (OTPMK Key) */ +#define OCOTP_OTPMK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK4_BITS_SHIFT (0U) +#define OCOTP_OTPMK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK4_BITS_SHIFT)) & OCOTP_OTPMK4_BITS_MASK) + +/*! @name OTPMK5 - Value of OTP Bank2 Word5 (OTPMK Key) */ +#define OCOTP_OTPMK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK5_BITS_SHIFT (0U) +#define OCOTP_OTPMK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK5_BITS_SHIFT)) & OCOTP_OTPMK5_BITS_MASK) + +/*! @name OTPMK6 - Value of OTP Bank2 Word6 (OTPMK Key) */ +#define OCOTP_OTPMK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK6_BITS_SHIFT (0U) +#define OCOTP_OTPMK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK6_BITS_SHIFT)) & OCOTP_OTPMK6_BITS_MASK) + +/*! @name OTPMK7 - Value of OTP Bank2 Word7 (OTPMK Key) */ +#define OCOTP_OTPMK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK7_BITS_SHIFT (0U) +#define OCOTP_OTPMK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK7_BITS_SHIFT)) & OCOTP_OTPMK7_BITS_MASK) + +/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) + +/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) + +/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) + +/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) + +/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) + +/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) + +/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) + +/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) + +/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) + +/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) + +/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC0_BITS_SHIFT (0U) +#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) + +/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC1_BITS_SHIFT (0U) +#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) + +/*! @name MAC - Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED) */ +#define OCOTP_MAC_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC_BITS_SHIFT (0U) +#define OCOTP_MAC_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_BITS_SHIFT)) & OCOTP_MAC_BITS_MASK) + +/*! @name CRC - Value of OTP Bank4 Word5 (CRC Key) */ +#define OCOTP_CRC_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CRC_BITS_SHIFT (0U) +#define OCOTP_CRC_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_BITS_SHIFT)) & OCOTP_CRC_BITS_MASK) + +/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP1_BITS_SHIFT (0U) +#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) + +/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP2_BITS_SHIFT (0U) +#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) + +/*! @name SW_GP0 - Value of OTP Bank5 Word0 (SW GP) */ +#define OCOTP_SW_GP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP0_BITS_SHIFT (0U) +#define OCOTP_SW_GP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP0_BITS_SHIFT)) & OCOTP_SW_GP0_BITS_MASK) + +/*! @name SW_GP1 - Value of OTP Bank5 Word1 (SW GP) */ +#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP1_BITS_SHIFT (0U) +#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) + +/*! @name SW_GP2 - Value of OTP Bank5 Word2 (SW GP) */ +#define OCOTP_SW_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP2_BITS_SHIFT (0U) +#define OCOTP_SW_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP2_BITS_SHIFT)) & OCOTP_SW_GP2_BITS_MASK) + +/*! @name SW_GP3 - Value of OTP Bank5 Word3 (SW GP) */ +#define OCOTP_SW_GP3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP3_BITS_SHIFT (0U) +#define OCOTP_SW_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP3_BITS_SHIFT)) & OCOTP_SW_GP3_BITS_MASK) + +/*! @name SW_GP4 - Value of OTP Bank5 Word4 (SW GP) */ +#define OCOTP_SW_GP4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP4_BITS_SHIFT (0U) +#define OCOTP_SW_GP4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP4_BITS_SHIFT)) & OCOTP_SW_GP4_BITS_MASK) + +/*! @name MISC_CONF - Value of OTP Bank5 Word5 (Misc Conf) */ +#define OCOTP_MISC_CONF_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF_BITS_SHIFT)) & OCOTP_MISC_CONF_BITS_MASK) + +/*! @name FIELD_RETURN - Value of OTP Bank5 Word6 (Field Return) */ +#define OCOTP_FIELD_RETURN_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_FIELD_RETURN_BITS_SHIFT (0U) +#define OCOTP_FIELD_RETURN_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FIELD_RETURN_BITS_SHIFT)) & OCOTP_FIELD_RETURN_BITS_MASK) + +/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) + +/*! @name ROM_PATCH0 - Value of OTP Bank6 Word0 (ROM Patch) */ +#define OCOTP_ROM_PATCH0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH0_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH0_BITS_SHIFT)) & OCOTP_ROM_PATCH0_BITS_MASK) + +/*! @name ROM_PATCH1 - Value of OTP Bank6 Word1 (ROM Patch) */ +#define OCOTP_ROM_PATCH1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH1_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH1_BITS_SHIFT)) & OCOTP_ROM_PATCH1_BITS_MASK) + +/*! @name ROM_PATCH2 - Value of OTP Bank6 Word2 (ROM Patch) */ +#define OCOTP_ROM_PATCH2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH2_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH2_BITS_SHIFT)) & OCOTP_ROM_PATCH2_BITS_MASK) + +/*! @name ROM_PATCH3 - Value of OTP Bank6 Word3 (ROM Patch) */ +#define OCOTP_ROM_PATCH3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH3_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH3_BITS_SHIFT)) & OCOTP_ROM_PATCH3_BITS_MASK) + +/*! @name ROM_PATCH4 - Value of OTP Bank6 Word4 (ROM Patch) */ +#define OCOTP_ROM_PATCH4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH4_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH4_BITS_SHIFT)) & OCOTP_ROM_PATCH4_BITS_MASK) + +/*! @name ROM_PATCH5 - Value of OTP Bank6 Word5 (ROM Patch) */ +#define OCOTP_ROM_PATCH5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH5_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH5_BITS_SHIFT)) & OCOTP_ROM_PATCH5_BITS_MASK) + +/*! @name ROM_PATCH6 - Value of OTP Bank6 Word6 (ROM Patch) */ +#define OCOTP_ROM_PATCH6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH6_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH6_BITS_SHIFT)) & OCOTP_ROM_PATCH6_BITS_MASK) + +/*! @name ROM_PATCH7 - Value of OTP Bank6 Word7 (ROM Patch) */ +#define OCOTP_ROM_PATCH7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH7_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH7_BITS_SHIFT)) & OCOTP_ROM_PATCH7_BITS_MASK) + +/*! @name GP3_0 - Value of OTP Bank7 Word0 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_0_BITS_SHIFT (0U) +#define OCOTP_GP3_0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_0_BITS_SHIFT)) & OCOTP_GP3_0_BITS_MASK) + +/*! @name GP3_1 - Value of OTP Bank7 Word1 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_1_BITS_SHIFT (0U) +#define OCOTP_GP3_1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_1_BITS_SHIFT)) & OCOTP_GP3_1_BITS_MASK) + +/*! @name GP3_2 - Value of OTP Bank7 Word2 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_2_BITS_SHIFT (0U) +#define OCOTP_GP3_2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_2_BITS_SHIFT)) & OCOTP_GP3_2_BITS_MASK) + +/*! @name GP3_3 - Value of OTP Bank7 Word3 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_3_BITS_SHIFT (0U) +#define OCOTP_GP3_3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_3_BITS_SHIFT)) & OCOTP_GP3_3_BITS_MASK) + +/*! @name GP3_4 - Value of OTP Bank8 Word4 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_4_BITS_SHIFT (0U) +#define OCOTP_GP3_4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_4_BITS_SHIFT)) & OCOTP_GP3_4_BITS_MASK) + +/*! @name GP4_0 - Value of OTP Bank7 Word5 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_0_BITS_SHIFT (0U) +#define OCOTP_GP4_0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_0_BITS_SHIFT)) & OCOTP_GP4_0_BITS_MASK) + +/*! @name GP4_1 - Value of OTP Bank7 Word6 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_1_BITS_SHIFT (0U) +#define OCOTP_GP4_1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_1_BITS_SHIFT)) & OCOTP_GP4_1_BITS_MASK) + +/*! @name GP4_2 - Value of OTP Bank7 Word7 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_2_BITS_SHIFT (0U) +#define OCOTP_GP4_2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_2_BITS_SHIFT)) & OCOTP_GP4_2_BITS_MASK) + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x21BC000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x0 */ + __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x4 */ + __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x8 */ + __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0xC */ + uint8_t RESERVED_0[112]; + __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x80 */ + __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x84 */ + __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x88 */ + __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x8C */ +} PGC_Type; + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/*! @name MEGA_CTRL - PGC Mega Control Register */ +#define PGC_MEGA_CTRL_PCR_MASK (0x1U) +#define PGC_MEGA_CTRL_PCR_SHIFT (0U) +#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) + +/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) +#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) +#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) +#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) + +/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) +#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) +#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) +#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) + +/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +#define PGC_MEGA_SR_PSR_MASK (0x1U) +#define PGC_MEGA_SR_PSR_SHIFT (0U) +#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) + +/*! @name CPU_CTRL - PGC CPU Control Register */ +#define PGC_CPU_CTRL_PCR_MASK (0x1U) +#define PGC_CPU_CTRL_PCR_SHIFT (0U) +#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) + +/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) +#define PGC_CPU_PUPSCR_SW_SHIFT (0U) +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) + +/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) +#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) + +/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +#define PGC_CPU_SR_PSR_MASK (0x1U) +#define PGC_CPU_SR_PSR_SHIFT (0U) +#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) + + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC base address */ +#define PGC_BASE (0x20DC220u) +/** Peripheral PGC base pointer */ +#define PGC ((PGC_Type *)PGC_BASE) +/** Array initializer of PGC peripheral base addresses */ +#define PGC_BASE_ADDRS { PGC_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC } + +/*! + * @} + */ /* end of group PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x30 */ + uint8_t RESERVED_3[300]; + __IO uint32_t LOWPWR_CTRL; /**< Low Power Control Register, offset: 0x160 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< Low Power Control Register, offset: 0x164 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< Low Power Control Register, offset: 0x168 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< Low Power Control Register, offset: 0x16C */ +} PMU_Type; + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/*! @name REG_1P1 - Regulator 1P1 Register */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) +#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) +#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) + +/*! @name REG_3P0 - Regulator 3P0 Register */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) +#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) +#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) + +/*! @name REG_2P5 - Regulator 2P5 Register */ +#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) +#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) +#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) +#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) + +/*! @name REG_CORE - Digital Regulator Core Register */ +#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) +#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) + +/*! @name LOWPWR_CTRL - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_SET - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_CLR - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_TOG - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) + + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (g_pmu_vbase) //(0x20C8110u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +/** Array initializer of PMU peripheral base addresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } +/** Interrupt vectors for the PMU peripheral type */ +#define PMU_IRQS { PMU_IRQ1_IRQn, PMU_IRQ2_IRQn } + +/*! + * @} + */ /* end of group PMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ + __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ + __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ + __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ + __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ + __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name PWMCR - PWM Control Register */ +#define PWM_PWMCR_EN_MASK (0x1U) +#define PWM_PWMCR_EN_SHIFT (0U) +#define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK) +#define PWM_PWMCR_REPEAT_MASK (0x6U) +#define PWM_PWMCR_REPEAT_SHIFT (1U) +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK) +#define PWM_PWMCR_SWR_MASK (0x8U) +#define PWM_PWMCR_SWR_SHIFT (3U) +#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK) +#define PWM_PWMCR_PRESCALER_MASK (0xFFF0U) +#define PWM_PWMCR_PRESCALER_SHIFT (4U) +#define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK) +#define PWM_PWMCR_CLKSRC_MASK (0x30000U) +#define PWM_PWMCR_CLKSRC_SHIFT (16U) +#define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK) +#define PWM_PWMCR_POUTC_MASK (0xC0000U) +#define PWM_PWMCR_POUTC_SHIFT (18U) +#define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK) +#define PWM_PWMCR_HCTR_MASK (0x100000U) +#define PWM_PWMCR_HCTR_SHIFT (20U) +#define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK) +#define PWM_PWMCR_BCTR_MASK (0x200000U) +#define PWM_PWMCR_BCTR_SHIFT (21U) +#define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK) +#define PWM_PWMCR_DBGEN_MASK (0x400000U) +#define PWM_PWMCR_DBGEN_SHIFT (22U) +#define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK) +#define PWM_PWMCR_WAITEN_MASK (0x800000U) +#define PWM_PWMCR_WAITEN_SHIFT (23U) +#define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK) +#define PWM_PWMCR_DOZEN_MASK (0x1000000U) +#define PWM_PWMCR_DOZEN_SHIFT (24U) +#define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK) +#define PWM_PWMCR_STOPEN_MASK (0x2000000U) +#define PWM_PWMCR_STOPEN_SHIFT (25U) +#define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK) +#define PWM_PWMCR_FWM_MASK (0xC000000U) +#define PWM_PWMCR_FWM_SHIFT (26U) +#define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK) + +/*! @name PWMSR - PWM Status Register */ +#define PWM_PWMSR_FIFOAV_MASK (0x7U) +#define PWM_PWMSR_FIFOAV_SHIFT (0U) +#define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK) +#define PWM_PWMSR_FE_MASK (0x8U) +#define PWM_PWMSR_FE_SHIFT (3U) +#define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK) +#define PWM_PWMSR_ROV_MASK (0x10U) +#define PWM_PWMSR_ROV_SHIFT (4U) +#define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK) +#define PWM_PWMSR_CMP_MASK (0x20U) +#define PWM_PWMSR_CMP_SHIFT (5U) +#define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK) +#define PWM_PWMSR_FWE_MASK (0x40U) +#define PWM_PWMSR_FWE_SHIFT (6U) +#define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK) + +/*! @name PWMIR - PWM Interrupt Register */ +#define PWM_PWMIR_FIE_MASK (0x1U) +#define PWM_PWMIR_FIE_SHIFT (0U) +#define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK) +#define PWM_PWMIR_RIE_MASK (0x2U) +#define PWM_PWMIR_RIE_SHIFT (1U) +#define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK) +#define PWM_PWMIR_CIE_MASK (0x4U) +#define PWM_PWMIR_CIE_SHIFT (2U) +#define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK) + +/*! @name PWMSAR - PWM Sample Register */ +#define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU) +#define PWM_PWMSAR_SAMPLE_SHIFT (0U) +#define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK) + +/*! @name PWMPR - PWM Period Register */ +#define PWM_PWMPR_PERIOD_MASK (0xFFFFU) +#define PWM_PWMPR_PERIOD_SHIFT (0U) +#define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK) + +/*! @name PWMCNR - PWM Counter Register */ +#define PWM_PWMCNR_COUNT_MASK (0xFFFFU) +#define PWM_PWMCNR_COUNT_SHIFT (0U) +#define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK) + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x2080000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x2084000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x2088000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x208C000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +/** Peripheral PWM5 base address */ +#define PWM5_BASE (0x20F0000u) +/** Peripheral PWM5 base pointer */ +#define PWM5 ((PWM_Type *)PWM5_BASE) +/** Peripheral PWM6 base address */ +#define PWM6_BASE (0x20F4000u) +/** Peripheral PWM6 base pointer */ +#define PWM6 ((PWM_Type *)PWM6_BASE) +/** Peripheral PWM7 base address */ +#define PWM7_BASE (0x20F8000u) +/** Peripheral PWM7 base pointer */ +#define PWM7 ((PWM_Type *)PWM7_BASE) +/** Peripheral PWM8 base address */ +#define PWM8_BASE (0x20FC000u) +/** Peripheral PWM8 base pointer */ +#define PWM8 ((PWM_Type *)PWM8_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE, PWM5_BASE, PWM6_BASE, PWM7_BASE, PWM8_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_IRQS { NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn, PWM5_IRQn, PWM6_IRQn, PWM7_IRQn, PWM8_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PXP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer + * @{ + */ + +/** PXP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */ + __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ + __IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */ + __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ + __IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */ + __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ + __IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */ + __IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */ + __IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */ + __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ + __IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */ + __IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */ + __IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */ + __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t PS_BACKGROUND_0; /**< PS Background Color, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t PS_CLRKEYLOW_0; /**< PS Color Key Low, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t PS_CLRKEYHIGH_0; /**< PS Color Key High, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t AS_CLRKEYLOW_0; /**< Overlay Color Key Low, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t AS_CLRKEYHIGH_0; /**< Overlay Color Key High, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CSC2_CTRL; /**< Color Space Conversion Control Register., offset: 0x1D0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CSC2_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CSC2_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CSC2_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CSC2_COEF3; /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CSC2_COEF4; /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */ + uint8_t RESERVED_30[12]; + __IO uint32_t CSC2_COEF5; /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */ + uint8_t RESERVED_31[12]; + __IO uint32_t LUT_CTRL; /**< Lookup Table Control Register., offset: 0x240 */ + uint8_t RESERVED_32[12]; + __IO uint32_t LUT_ADDR; /**< Lookup Table Control Register., offset: 0x250 */ + uint8_t RESERVED_33[12]; + __IO uint32_t LUT_DATA; /**< Lookup Table Data Register., offset: 0x260 */ + uint8_t RESERVED_34[12]; + __IO uint32_t LUT_EXTMEM; /**< Lookup Table External Memory Address Register., offset: 0x270 */ + uint8_t RESERVED_35[12]; + __IO uint32_t CFA; /**< Color Filter Array Register., offset: 0x280 */ + uint8_t RESERVED_36[12]; + __IO uint32_t ALPHA_A_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x290 */ + uint8_t RESERVED_37[44]; + __IO uint32_t PS_BACKGROUND_1; /**< PS Background Color 1, offset: 0x2C0 */ + uint8_t RESERVED_38[12]; + __IO uint32_t PS_CLRKEYLOW_1; /**< PS Color Key Low 1, offset: 0x2D0 */ + uint8_t RESERVED_39[12]; + __IO uint32_t PS_CLRKEYHIGH_1; /**< PS Color Key High 1, offset: 0x2E0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t AS_CLRKEYLOW_1; /**< Overlay Color Key Low, offset: 0x2F0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t AS_CLRKEYHIGH_1; /**< Overlay Color Key High, offset: 0x300 */ + uint8_t RESERVED_42[12]; + __IO uint32_t CTRL2; /**< Control Register 2, offset: 0x310 */ + __IO uint32_t CTRL2_SET; /**< Control Register 2, offset: 0x314 */ + __IO uint32_t CTRL2_CLR; /**< Control Register 2, offset: 0x318 */ + __IO uint32_t CTRL2_TOG; /**< Control Register 2, offset: 0x31C */ + __IO uint32_t POWER_REG0; /**< PXP Power Control Register., offset: 0x320 */ + uint8_t RESERVED_43[12]; + __IO uint32_t POWER_REG1; /**< PXP Power Control Register 1., offset: 0x330 */ + uint8_t RESERVED_44[12]; + __IO uint32_t DATA_PATH_CTRL0; /**< This register helps decide the data path gthrough the PXP., offset: 0x340 */ + __IO uint32_t DATA_PATH_CTRL0_SET; /**< This register helps decide the data path gthrough the PXP., offset: 0x344 */ + __IO uint32_t DATA_PATH_CTRL0_CLR; /**< This register helps decide the data path gthrough the PXP., offset: 0x348 */ + __IO uint32_t DATA_PATH_CTRL0_TOG; /**< This register helps decide the data path gthrough the PXP., offset: 0x34C */ + __IO uint32_t DATA_PATH_CTRL1; /**< This register helps decide the data path gthrough the PXP., offset: 0x350 */ + __IO uint32_t DATA_PATH_CTRL1_SET; /**< This register helps decide the data path gthrough the PXP., offset: 0x354 */ + __IO uint32_t DATA_PATH_CTRL1_CLR; /**< This register helps decide the data path gthrough the PXP., offset: 0x358 */ + __IO uint32_t DATA_PATH_CTRL1_TOG; /**< This register helps decide the data path gthrough the PXP., offset: 0x35C */ + __IO uint32_t INIT_MEM_CTRL; /**< Initialize memory buffer control Register, offset: 0x360 */ + __IO uint32_t INIT_MEM_CTRL_SET; /**< Initialize memory buffer control Register, offset: 0x364 */ + __IO uint32_t INIT_MEM_CTRL_CLR; /**< Initialize memory buffer control Register, offset: 0x368 */ + __IO uint32_t INIT_MEM_CTRL_TOG; /**< Initialize memory buffer control Register, offset: 0x36C */ + __IO uint32_t INIT_MEM_DATA; /**< Write data Register, offset: 0x370 */ + uint8_t RESERVED_45[12]; + __IO uint32_t INIT_MEM_DATA_HIGH; /**< Write data Register, offset: 0x380 */ + uint8_t RESERVED_46[12]; + __IO uint32_t IRQ_MASK; /**< PXP IRQ Mask Register, offset: 0x390 */ + __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ + __IO uint32_t IRQ_MASK_CLR; /**< PXP IRQ Mask Register, offset: 0x398 */ + __IO uint32_t IRQ_MASK_TOG; /**< PXP IRQ Mask Register, offset: 0x39C */ + __IO uint32_t IRQ; /**< PXP Interrupt Register, offset: 0x3A0 */ + __IO uint32_t IRQ_SET; /**< PXP Interrupt Register, offset: 0x3A4 */ + __IO uint32_t IRQ_CLR; /**< PXP Interrupt Register, offset: 0x3A8 */ + __IO uint32_t IRQ_TOG; /**< PXP Interrupt Register, offset: 0x3AC */ + __IO uint32_t NEXT_EN; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B0 */ + __IO uint32_t NEXT_EN_SET; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B4 */ + __IO uint32_t NEXT_EN_CLR; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B8 */ + __IO uint32_t NEXT_EN_TOG; /**< PXP NEXT Buffer Enable select Register, offset: 0x3BC */ + uint8_t RESERVED_47[64]; + __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ + uint8_t RESERVED_48[12]; + __IO uint32_t DEBUGCTRL; /**< Debug Control Register, offset: 0x410 */ + uint8_t RESERVED_49[12]; + __I uint32_t DEBUGr; /**< Debug Register, offset: 0x420 */ + uint8_t RESERVED_50[12]; + __I uint32_t VERSION; /**< Version Register, offset: 0x430 */ + uint8_t RESERVED_51[1484]; + __IO uint32_t DITHER_STORE_SIZE_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0xA00 */ + uint8_t RESERVED_52[1788]; + __IO uint32_t WFB_FETCH_CTRL; /**< Fetch engine Control for WFE B Register, offset: 0x1100 */ + __IO uint32_t WFB_FETCH_CTRL_SET; /**< Fetch engine Control for WFE B Register, offset: 0x1104 */ + __IO uint32_t WFB_FETCH_CTRL_CLR; /**< Fetch engine Control for WFE B Register, offset: 0x1108 */ + __IO uint32_t WFB_FETCH_CTRL_TOG; /**< Fetch engine Control for WFE B Register, offset: 0x110C */ + __IO uint32_t WFB_FETCH_BUF1_ADDR; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1110 */ + uint8_t RESERVED_53[12]; + __IO uint32_t WFB_FETCH_BUF1_PITCH; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1120 */ + uint8_t RESERVED_54[12]; + __IO uint32_t WFB_FETCH_BUF1_SIZE; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1130 */ + uint8_t RESERVED_55[12]; + __IO uint32_t WFB_FETCH_BUF2_ADDR; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1140 */ + uint8_t RESERVED_56[12]; + __IO uint32_t WFB_FETCH_BUF2_PITCH; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1150 */ + uint8_t RESERVED_57[12]; + __IO uint32_t WFB_FETCH_BUF2_SIZE; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1160 */ + uint8_t RESERVED_58[12]; + __IO uint32_t WFB_ARRAY_PIXEL0_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1170 */ + uint8_t RESERVED_59[12]; + __IO uint32_t WFB_ARRAY_PIXEL1_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1180 */ + uint8_t RESERVED_60[12]; + __IO uint32_t WFB_ARRAY_PIXEL2_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1190 */ + uint8_t RESERVED_61[12]; + __IO uint32_t WFB_ARRAY_PIXEL3_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11A0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t WFB_ARRAY_PIXEL4_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11B0 */ + uint8_t RESERVED_63[12]; + __IO uint32_t WFB_ARRAY_PIXEL5_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11C0 */ + uint8_t RESERVED_64[12]; + __IO uint32_t WFB_ARRAY_PIXEL6_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11D0 */ + uint8_t RESERVED_65[12]; + __IO uint32_t WFB_ARRAY_PIXEL7_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11E0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t WFB_ARRAY_FLAG0_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11F0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t WFB_ARRAY_FLAG1_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1200 */ + uint8_t RESERVED_68[12]; + __IO uint32_t WFB_ARRAY_FLAG2_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1210 */ + uint8_t RESERVED_69[12]; + __IO uint32_t WFB_ARRAY_FLAG3_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1220 */ + uint8_t RESERVED_70[12]; + __IO uint32_t WFB_ARRAY_FLAG4_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1230 */ + uint8_t RESERVED_71[12]; + __IO uint32_t WFB_ARRAY_FLAG5_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1240 */ + uint8_t RESERVED_72[12]; + __IO uint32_t WFB_ARRAY_FLAG6_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1250 */ + uint8_t RESERVED_73[12]; + __IO uint32_t WFB_ARRAY_FLAG7_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1260 */ + uint8_t RESERVED_74[12]; + __IO uint32_t WFB_FETCH_BUF1_CORD; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1270 */ + uint8_t RESERVED_75[12]; + __IO uint32_t WFB_FETCH_BUF2_CORD; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1280 */ + uint8_t RESERVED_76[12]; + __IO uint32_t WFB_ARRAY_FLAG8_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1290 */ + uint8_t RESERVED_77[12]; + __IO uint32_t WFB_ARRAY_FLAG9_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12A0 */ + uint8_t RESERVED_78[12]; + __IO uint32_t WFB_ARRAY_FLAG10_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12B0 */ + uint8_t RESERVED_79[12]; + __IO uint32_t WFB_ARRAY_FLAG11_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12C0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t WFB_ARRAY_FLAG12_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12D0 */ + uint8_t RESERVED_81[12]; + __IO uint32_t WFB_ARRAY_FLAG13_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12E0 */ + uint8_t RESERVED_82[12]; + __IO uint32_t WFB_ARRAY_FLAG14_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12F0 */ + uint8_t RESERVED_83[12]; + __IO uint32_t WFB_ARRAY_FLAG15_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1300 */ + uint8_t RESERVED_84[12]; + __IO uint32_t WFB_ARRAY_REG0; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1310 */ + uint8_t RESERVED_85[12]; + __IO uint32_t WFB_ARRAY_REG1; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1320 */ + uint8_t RESERVED_86[12]; + __IO uint32_t WFB_ARRAY_REG2; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1330 */ + uint8_t RESERVED_87[12]; + __IO uint32_t WFE_B_STORE_CTRL_CH0; /**< Store engine Control Channel 0 Register, offset: 0x1340 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_SET; /**< Store engine Control Channel 0 Register, offset: 0x1344 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_CLR; /**< Store engine Control Channel 0 Register, offset: 0x1348 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_TOG; /**< Store engine Control Channel 0 Register, offset: 0x134C */ + __IO uint32_t WFE_B_STORE_CTRL_CH1; /**< Store engine Control Channel 1 Register, offset: 0x1350 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_SET; /**< Store engine Control Channel 1 Register, offset: 0x1354 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_CLR; /**< Store engine Control Channel 1 Register, offset: 0x1358 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_TOG; /**< Store engine Control Channel 1 Register, offset: 0x135C */ + __I uint32_t WFE_B_STORE_STATUS_CH0; /**< Store engine status Channel 0 Register, offset: 0x1360 */ + uint8_t RESERVED_88[12]; + __I uint32_t WFE_B_STORE_STATUS_CH1; /**< Store engine status Channel 1 Register, offset: 0x1370 */ + uint8_t RESERVED_89[12]; + __IO uint32_t WFE_B_STORE_SIZE_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1380 */ + uint8_t RESERVED_90[12]; + __IO uint32_t WFE_B_STORE_SIZE_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1390 */ + uint8_t RESERVED_91[12]; + __IO uint32_t WFE_B_STORE_PITCH; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13A0 */ + uint8_t RESERVED_92[12]; + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B0 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_SET; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B4 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_CLR; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B8 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_TOG; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13BC */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C0 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_SET; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C4 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_CLR; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C8 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_TOG; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13CC */ + uint8_t RESERVED_93[64]; + __IO uint32_t WFE_B_STORE_ADDR_0_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1410 */ + uint8_t RESERVED_94[12]; + __IO uint32_t WFE_B_STORE_ADDR_1_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1420 */ + uint8_t RESERVED_95[12]; + __IO uint32_t WFE_B_STORE_FILL_DATA_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1430 */ + uint8_t RESERVED_96[12]; + __IO uint32_t WFE_B_STORE_ADDR_0_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1440 */ + uint8_t RESERVED_97[12]; + __IO uint32_t WFE_B_STORE_ADDR_1_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1450 */ + uint8_t RESERVED_98[12]; + __IO uint32_t WFE_B_STORE_D_MASK0_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1460 */ + uint8_t RESERVED_99[12]; + __IO uint32_t WFE_B_STORE_D_MASK0_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1470 */ + uint8_t RESERVED_100[12]; + __IO uint32_t WFE_B_STORE_D_MASK1_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1480 */ + uint8_t RESERVED_101[12]; + __IO uint32_t WFE_B_STORE_D_MASK1_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1490 */ + uint8_t RESERVED_102[12]; + __IO uint32_t WFE_B_STORE_D_MASK2_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14A0 */ + uint8_t RESERVED_103[12]; + __IO uint32_t WFE_B_STORE_D_MASK2_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14B0 */ + uint8_t RESERVED_104[12]; + __IO uint32_t WFE_B_STORE_D_MASK3_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14C0 */ + uint8_t RESERVED_105[12]; + __IO uint32_t WFE_B_STORE_D_MASK3_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14D0 */ + uint8_t RESERVED_106[12]; + __IO uint32_t WFE_B_STORE_D_MASK4_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14E0 */ + uint8_t RESERVED_107[12]; + __IO uint32_t WFE_B_STORE_D_MASK4_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14F0 */ + uint8_t RESERVED_108[12]; + __IO uint32_t WFE_B_STORE_D_MASK5_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1500 */ + uint8_t RESERVED_109[12]; + __IO uint32_t WFE_B_STORE_D_MASK5_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1510 */ + uint8_t RESERVED_110[12]; + __IO uint32_t WFE_B_STORE_D_MASK6_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1520 */ + uint8_t RESERVED_111[12]; + __IO uint32_t WFE_B_STORE_D_MASK6_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1530 */ + uint8_t RESERVED_112[12]; + __IO uint32_t WFE_B_STORE_D_MASK7_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1540 */ + uint8_t RESERVED_113[12]; + __IO uint32_t WFE_B_STORE_D_MASK7_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1550 */ + uint8_t RESERVED_114[12]; + __IO uint32_t WFE_B_STORE_D_SHIFT_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1560 */ + uint8_t RESERVED_115[12]; + __IO uint32_t WFE_B_STORE_D_SHIFT_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1570 */ + uint8_t RESERVED_116[12]; + __IO uint32_t WFE_B_STORE_F_SHIFT_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1580 */ + uint8_t RESERVED_117[12]; + __IO uint32_t WFE_B_STORE_F_SHIFT_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1590 */ + uint8_t RESERVED_118[12]; + __IO uint32_t WFE_B_STORE_F_MASK_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x15A0 */ + uint8_t RESERVED_119[12]; + __IO uint32_t WFE_B_STORE_F_MASK_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x15B0 */ + uint8_t RESERVED_120[28]; + __IO uint32_t FETCH_WFE_B_DEBUG; /**< This register holds the debug bits for the prefetch engine for WFE B., offset: 0x15D0 */ + uint8_t RESERVED_121[156]; + __IO uint32_t DITHER_CTRL; /**< Dither Control Register 0, offset: 0x1670 */ + __IO uint32_t DITHER_CTRL_SET; /**< Dither Control Register 0, offset: 0x1674 */ + __IO uint32_t DITHER_CTRL_CLR; /**< Dither Control Register 0, offset: 0x1678 */ + __IO uint32_t DITHER_CTRL_TOG; /**< Dither Control Register 0, offset: 0x167C */ + __IO uint32_t DITHER_FINAL_LUT_DATA0; /**< Final stage lookup value Register, offset: 0x1680 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_SET; /**< Final stage lookup value Register, offset: 0x1684 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_CLR; /**< Final stage lookup value Register, offset: 0x1688 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_TOG; /**< Final stage lookup value Register, offset: 0x168C */ + __IO uint32_t DITHER_FINAL_LUT_DATA1; /**< Final stage lookup value Register, offset: 0x1690 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_SET; /**< Final stage lookup value Register, offset: 0x1694 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_CLR; /**< Final stage lookup value Register, offset: 0x1698 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_TOG; /**< Final stage lookup value Register, offset: 0x169C */ + __IO uint32_t DITHER_FINAL_LUT_DATA2; /**< Final stage lookup value Register, offset: 0x16A0 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_SET; /**< Final stage lookup value Register, offset: 0x16A4 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_CLR; /**< Final stage lookup value Register, offset: 0x16A8 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_TOG; /**< Final stage lookup value Register, offset: 0x16AC */ + __IO uint32_t DITHER_FINAL_LUT_DATA3; /**< Final stage lookup value Register, offset: 0x16B0 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_SET; /**< Final stage lookup value Register, offset: 0x16B4 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_CLR; /**< Final stage lookup value Register, offset: 0x16B8 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_TOG; /**< Final stage lookup value Register, offset: 0x16BC */ + uint8_t RESERVED_122[1600]; + __IO uint32_t WFE_B_CTRL; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D00 */ + __IO uint32_t WFE_B_CTRL_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D04 */ + __IO uint32_t WFE_B_CTRL_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D08 */ + __IO uint32_t WFE_B_CTRL_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D0C */ + __IO uint32_t WFE_B_DIMENSIONS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D10 */ + uint8_t RESERVED_123[12]; + __IO uint32_t WFE_B_OFFSET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D20 */ + uint8_t RESERVED_124[12]; + __IO uint32_t WFE_B_SW_DATA_REGS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D30 */ + uint8_t RESERVED_125[12]; + __IO uint32_t WFE_B_SW_FLAG_REGS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D40 */ + uint8_t RESERVED_126[12]; + __IO uint32_t WFE_B_STAGE1_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D50 */ + __IO uint32_t WFE_B_STAGE1_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D54 */ + __IO uint32_t WFE_B_STAGE1_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D58 */ + __IO uint32_t WFE_B_STAGE1_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D5C */ + __IO uint32_t WFE_B_STAGE1_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D60 */ + __IO uint32_t WFE_B_STAGE1_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D64 */ + __IO uint32_t WFE_B_STAGE1_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D68 */ + __IO uint32_t WFE_B_STAGE1_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D6C */ + __IO uint32_t WFE_B_STAGE1_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D70 */ + __IO uint32_t WFE_B_STAGE1_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D74 */ + __IO uint32_t WFE_B_STAGE1_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D78 */ + __IO uint32_t WFE_B_STAGE1_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D7C */ + __IO uint32_t WFE_B_STAGE1_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D80 */ + __IO uint32_t WFE_B_STAGE1_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D84 */ + __IO uint32_t WFE_B_STAGE1_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D88 */ + __IO uint32_t WFE_B_STAGE1_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D8C */ + __IO uint32_t WFE_B_STAGE1_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D90 */ + __IO uint32_t WFE_B_STAGE1_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D94 */ + __IO uint32_t WFE_B_STAGE1_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D98 */ + __IO uint32_t WFE_B_STAGE1_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D9C */ + __IO uint32_t WFE_B_STAGE1_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA0 */ + __IO uint32_t WFE_B_STAGE1_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA4 */ + __IO uint32_t WFE_B_STAGE1_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA8 */ + __IO uint32_t WFE_B_STAGE1_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DAC */ + __IO uint32_t WFE_B_STAGE1_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB0 */ + __IO uint32_t WFE_B_STAGE1_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB4 */ + __IO uint32_t WFE_B_STAGE1_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB8 */ + __IO uint32_t WFE_B_STAGE1_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DBC */ + __IO uint32_t WFE_B_STAGE1_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC0 */ + __IO uint32_t WFE_B_STAGE1_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC4 */ + __IO uint32_t WFE_B_STAGE1_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC8 */ + __IO uint32_t WFE_B_STAGE1_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DCC */ + __IO uint32_t WFE_B_STAGE1_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD0 */ + __IO uint32_t WFE_B_STAGE1_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD4 */ + __IO uint32_t WFE_B_STAGE1_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD8 */ + __IO uint32_t WFE_B_STAGE1_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DDC */ + __IO uint32_t WFE_B_STAGE2_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE0 */ + __IO uint32_t WFE_B_STAGE2_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE4 */ + __IO uint32_t WFE_B_STAGE2_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE8 */ + __IO uint32_t WFE_B_STAGE2_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DEC */ + __IO uint32_t WFE_B_STAGE2_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF0 */ + __IO uint32_t WFE_B_STAGE2_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF4 */ + __IO uint32_t WFE_B_STAGE2_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF8 */ + __IO uint32_t WFE_B_STAGE2_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DFC */ + __IO uint32_t WFE_B_STAGE2_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E00 */ + __IO uint32_t WFE_B_STAGE2_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E04 */ + __IO uint32_t WFE_B_STAGE2_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E08 */ + __IO uint32_t WFE_B_STAGE2_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E0C */ + __IO uint32_t WFE_B_STAGE2_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E10 */ + __IO uint32_t WFE_B_STAGE2_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E14 */ + __IO uint32_t WFE_B_STAGE2_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E18 */ + __IO uint32_t WFE_B_STAGE2_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E1C */ + __IO uint32_t WFE_B_STAGE2_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E20 */ + __IO uint32_t WFE_B_STAGE2_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E24 */ + __IO uint32_t WFE_B_STAGE2_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E28 */ + __IO uint32_t WFE_B_STAGE2_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E2C */ + __IO uint32_t WFE_B_STAGE2_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E30 */ + __IO uint32_t WFE_B_STAGE2_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E34 */ + __IO uint32_t WFE_B_STAGE2_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E38 */ + __IO uint32_t WFE_B_STAGE2_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E3C */ + __IO uint32_t WFE_B_STAGE2_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E40 */ + __IO uint32_t WFE_B_STAGE2_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E44 */ + __IO uint32_t WFE_B_STAGE2_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E48 */ + __IO uint32_t WFE_B_STAGE2_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E4C */ + __IO uint32_t WFE_B_STAGE2_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E50 */ + __IO uint32_t WFE_B_STAGE2_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E54 */ + __IO uint32_t WFE_B_STAGE2_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E58 */ + __IO uint32_t WFE_B_STAGE2_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E5C */ + __IO uint32_t WFE_B_STAGE2_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E60 */ + __IO uint32_t WFE_B_STAGE2_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E64 */ + __IO uint32_t WFE_B_STAGE2_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E68 */ + __IO uint32_t WFE_B_STAGE2_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E6C */ + __IO uint32_t WFE_B_STAGE2_MUX9; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E70 */ + __IO uint32_t WFE_B_STAGE2_MUX9_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E74 */ + __IO uint32_t WFE_B_STAGE2_MUX9_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E78 */ + __IO uint32_t WFE_B_STAGE2_MUX9_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E7C */ + __IO uint32_t WFE_B_STAGE2_MUX10; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E80 */ + __IO uint32_t WFE_B_STAGE2_MUX10_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E84 */ + __IO uint32_t WFE_B_STAGE2_MUX10_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E88 */ + __IO uint32_t WFE_B_STAGE2_MUX10_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E8C */ + __IO uint32_t WFE_B_STAGE2_MUX11; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E90 */ + __IO uint32_t WFE_B_STAGE2_MUX11_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E94 */ + __IO uint32_t WFE_B_STAGE2_MUX11_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E98 */ + __IO uint32_t WFE_B_STAGE2_MUX11_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E9C */ + __IO uint32_t WFE_B_STAGE2_MUX12; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA0 */ + __IO uint32_t WFE_B_STAGE2_MUX12_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA4 */ + __IO uint32_t WFE_B_STAGE2_MUX12_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA8 */ + __IO uint32_t WFE_B_STAGE2_MUX12_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EAC */ + __IO uint32_t WFE_B_STAGE3_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB0 */ + __IO uint32_t WFE_B_STAGE3_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB4 */ + __IO uint32_t WFE_B_STAGE3_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB8 */ + __IO uint32_t WFE_B_STAGE3_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EBC */ + __IO uint32_t WFE_B_STAGE3_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC0 */ + __IO uint32_t WFE_B_STAGE3_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC4 */ + __IO uint32_t WFE_B_STAGE3_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC8 */ + __IO uint32_t WFE_B_STAGE3_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ECC */ + __IO uint32_t WFE_B_STAGE3_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED0 */ + __IO uint32_t WFE_B_STAGE3_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED4 */ + __IO uint32_t WFE_B_STAGE3_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED8 */ + __IO uint32_t WFE_B_STAGE3_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EDC */ + __IO uint32_t WFE_B_STAGE3_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE0 */ + __IO uint32_t WFE_B_STAGE3_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE4 */ + __IO uint32_t WFE_B_STAGE3_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE8 */ + __IO uint32_t WFE_B_STAGE3_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EEC */ + __IO uint32_t WFE_B_STAGE3_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF0 */ + __IO uint32_t WFE_B_STAGE3_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF4 */ + __IO uint32_t WFE_B_STAGE3_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF8 */ + __IO uint32_t WFE_B_STAGE3_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EFC */ + __IO uint32_t WFE_B_STAGE3_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F00 */ + __IO uint32_t WFE_B_STAGE3_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F04 */ + __IO uint32_t WFE_B_STAGE3_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F08 */ + __IO uint32_t WFE_B_STAGE3_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F0C */ + __IO uint32_t WFE_B_STAGE3_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F10 */ + __IO uint32_t WFE_B_STAGE3_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F14 */ + __IO uint32_t WFE_B_STAGE3_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F18 */ + __IO uint32_t WFE_B_STAGE3_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F1C */ + __IO uint32_t WFE_B_STAGE3_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F20 */ + __IO uint32_t WFE_B_STAGE3_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F24 */ + __IO uint32_t WFE_B_STAGE3_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F28 */ + __IO uint32_t WFE_B_STAGE3_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F2C */ + __IO uint32_t WFE_B_STAGE3_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F30 */ + __IO uint32_t WFE_B_STAGE3_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F34 */ + __IO uint32_t WFE_B_STAGE3_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F38 */ + __IO uint32_t WFE_B_STAGE3_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F3C */ + __IO uint32_t WFE_B_STAGE3_MUX9; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F40 */ + __IO uint32_t WFE_B_STAGE3_MUX9_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F44 */ + __IO uint32_t WFE_B_STAGE3_MUX9_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F48 */ + __IO uint32_t WFE_B_STAGE3_MUX9_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F4C */ + __IO uint32_t WFE_B_STAGE3_MUX10; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F50 */ + __IO uint32_t WFE_B_STAGE3_MUX10_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F54 */ + __IO uint32_t WFE_B_STAGE3_MUX10_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F58 */ + __IO uint32_t WFE_B_STAGE3_MUX10_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F5C */ + __IO uint32_t WFE_B_STG1_5X8_OUT0_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F60 */ + uint8_t RESERVED_127[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F70 */ + uint8_t RESERVED_128[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F80 */ + uint8_t RESERVED_129[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F90 */ + uint8_t RESERVED_130[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FA0 */ + uint8_t RESERVED_131[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FB0 */ + uint8_t RESERVED_132[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FC0 */ + uint8_t RESERVED_133[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FD0 */ + uint8_t RESERVED_134[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FE0 */ + uint8_t RESERVED_135[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FF0 */ + uint8_t RESERVED_136[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2000 */ + uint8_t RESERVED_137[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2010 */ + uint8_t RESERVED_138[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2020 */ + uint8_t RESERVED_139[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2030 */ + uint8_t RESERVED_140[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2040 */ + uint8_t RESERVED_141[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2050 */ + uint8_t RESERVED_142[12]; + __IO uint32_t WFE_B_STAGE1_5X8_MASKS_0; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x8 LUT., offset: 0x2060 */ + uint8_t RESERVED_143[12]; + __IO uint32_t WFE_B_STG1_5X1_OUT0; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 1., offset: 0x2070 */ + uint8_t RESERVED_144[12]; + __IO uint32_t WFE_B_STG1_5X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT., offset: 0x2080 */ + uint8_t RESERVED_145[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2090 */ + uint8_t RESERVED_146[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20A0 */ + uint8_t RESERVED_147[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20B0 */ + uint8_t RESERVED_148[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20C0 */ + uint8_t RESERVED_149[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20D0 */ + uint8_t RESERVED_150[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20E0 */ + uint8_t RESERVED_151[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20F0 */ + uint8_t RESERVED_152[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2100 */ + uint8_t RESERVED_153[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2110 */ + uint8_t RESERVED_154[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2120 */ + uint8_t RESERVED_155[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2130 */ + uint8_t RESERVED_156[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2140 */ + uint8_t RESERVED_157[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2150 */ + uint8_t RESERVED_158[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2160 */ + uint8_t RESERVED_159[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2170 */ + uint8_t RESERVED_160[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2180 */ + uint8_t RESERVED_161[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2190 */ + uint8_t RESERVED_162[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21A0 */ + uint8_t RESERVED_163[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21B0 */ + uint8_t RESERVED_164[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21C0 */ + uint8_t RESERVED_165[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21D0 */ + uint8_t RESERVED_166[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21E0 */ + uint8_t RESERVED_167[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21F0 */ + uint8_t RESERVED_168[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2200 */ + uint8_t RESERVED_169[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2210 */ + uint8_t RESERVED_170[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2220 */ + uint8_t RESERVED_171[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2230 */ + uint8_t RESERVED_172[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2240 */ + uint8_t RESERVED_173[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2250 */ + uint8_t RESERVED_174[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2260 */ + uint8_t RESERVED_175[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2270 */ + uint8_t RESERVED_176[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2280 */ + uint8_t RESERVED_177[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2290 */ + uint8_t RESERVED_178[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22A0 */ + uint8_t RESERVED_179[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22B0 */ + uint8_t RESERVED_180[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22C0 */ + uint8_t RESERVED_181[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22D0 */ + uint8_t RESERVED_182[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22E0 */ + uint8_t RESERVED_183[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22F0 */ + uint8_t RESERVED_184[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2300 */ + uint8_t RESERVED_185[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2310 */ + uint8_t RESERVED_186[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2320 */ + uint8_t RESERVED_187[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2330 */ + uint8_t RESERVED_188[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2340 */ + uint8_t RESERVED_189[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2350 */ + uint8_t RESERVED_190[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2360 */ + uint8_t RESERVED_191[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2370 */ + uint8_t RESERVED_192[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2380 */ + uint8_t RESERVED_193[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2390 */ + uint8_t RESERVED_194[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23A0 */ + uint8_t RESERVED_195[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23B0 */ + uint8_t RESERVED_196[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23C0 */ + uint8_t RESERVED_197[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23D0 */ + uint8_t RESERVED_198[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23E0 */ + uint8_t RESERVED_199[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23F0 */ + uint8_t RESERVED_200[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2400 */ + uint8_t RESERVED_201[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2410 */ + uint8_t RESERVED_202[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2420 */ + uint8_t RESERVED_203[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2430 */ + uint8_t RESERVED_204[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2440 */ + uint8_t RESERVED_205[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2450 */ + uint8_t RESERVED_206[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2460 */ + uint8_t RESERVED_207[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2470 */ + uint8_t RESERVED_208[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2480 */ + uint8_t RESERVED_209[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2490 */ + uint8_t RESERVED_210[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24A0 */ + uint8_t RESERVED_211[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24B0 */ + uint8_t RESERVED_212[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24C0 */ + uint8_t RESERVED_213[28]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24E0 */ + uint8_t RESERVED_214[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24F0 */ + uint8_t RESERVED_215[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2500 */ + uint8_t RESERVED_216[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2510 */ + uint8_t RESERVED_217[12]; + __IO uint32_t WFE_B_STAGE2_5X6_MASKS_0; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT., offset: 0x2520 */ + uint8_t RESERVED_218[12]; + __IO uint32_t WFE_B_STAGE2_5X6_ADDR_0; /**< Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT., offset: 0x2530 */ + uint8_t RESERVED_219[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT0; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2540 */ + uint8_t RESERVED_220[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT1; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2550 */ + uint8_t RESERVED_221[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT2; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2560 */ + uint8_t RESERVED_222[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT3; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2570 */ + uint8_t RESERVED_223[12]; + __IO uint32_t WFE_B_STG2_5X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT., offset: 0x2580 */ + uint8_t RESERVED_224[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2590 */ + uint8_t RESERVED_225[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25A0 */ + uint8_t RESERVED_226[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25B0 */ + uint8_t RESERVED_227[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25C0 */ + uint8_t RESERVED_228[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25D0 */ + uint8_t RESERVED_229[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25E0 */ + uint8_t RESERVED_230[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25F0 */ + uint8_t RESERVED_231[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2600 */ + uint8_t RESERVED_232[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2610 */ + uint8_t RESERVED_233[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2620 */ + uint8_t RESERVED_234[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2630 */ + uint8_t RESERVED_235[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2640 */ + uint8_t RESERVED_236[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2650 */ + uint8_t RESERVED_237[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2660 */ + uint8_t RESERVED_238[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2670 */ + uint8_t RESERVED_239[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2680 */ + uint8_t RESERVED_240[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2690 */ + uint8_t RESERVED_241[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26A0 */ + uint8_t RESERVED_242[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26B0 */ + uint8_t RESERVED_243[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26C0 */ + uint8_t RESERVED_244[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26D0 */ + uint8_t RESERVED_245[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26E0 */ + uint8_t RESERVED_246[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26F0 */ + uint8_t RESERVED_247[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2700 */ + uint8_t RESERVED_248[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2710 */ + uint8_t RESERVED_249[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2720 */ + uint8_t RESERVED_250[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2730 */ + uint8_t RESERVED_251[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2740 */ + uint8_t RESERVED_252[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2750 */ + uint8_t RESERVED_253[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2760 */ + uint8_t RESERVED_254[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2770 */ + uint8_t RESERVED_255[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2780 */ + uint8_t RESERVED_256[12]; + __IO uint32_t WFE_B_STG3_F8X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 8x1 LUT., offset: 0x2790 */ + uint8_t RESERVED_257[268]; + __IO uint32_t ALU_B_CTRL; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A0 */ + __IO uint32_t ALU_B_CTRL_SET; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A4 */ + __IO uint32_t ALU_B_CTRL_CLR; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A8 */ + __IO uint32_t ALU_B_CTRL_TOG; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28AC */ + __IO uint32_t ALU_B_BUF_SIZE; /**< This register defines the size of the buffer to be processed by the alu engine., offset: 0x28B0 */ + uint8_t RESERVED_258[12]; + __IO uint32_t ALU_B_INST_ENTRY; /**< This register defines the Entry Address for the Instruction Memory of the ALU., offset: 0x28C0 */ + uint8_t RESERVED_259[12]; + __IO uint32_t ALU_B_PARAM; /**< This register defines the parameter used by SW running on ALU., offset: 0x28D0 */ + uint8_t RESERVED_260[12]; + __IO uint32_t ALU_B_CONFIG; /**< This register defines the hw configuration options for the alu core., offset: 0x28E0 */ + uint8_t RESERVED_261[12]; + __IO uint32_t ALU_B_LUT_CONFIG; /**< This register defines the hw configuration options for the LUT, offset: 0x28F0 */ + __IO uint32_t ALU_B_LUT_CONFIG_SET; /**< This register defines the hw configuration options for the LUT, offset: 0x28F4 */ + __IO uint32_t ALU_B_LUT_CONFIG_CLR; /**< This register defines the hw configuration options for the LUT, offset: 0x28F8 */ + __IO uint32_t ALU_B_LUT_CONFIG_TOG; /**< This register defines the hw configuration options for the LUT, offset: 0x28FC */ + __IO uint32_t ALU_B_LUT_DATA0; /**< This register defines the lower 32-bit data for the LUT, offset: 0x2900 */ + uint8_t RESERVED_262[12]; + __IO uint32_t ALU_B_LUT_DATA1; /**< This register defines the higher 32-bit data for the LUT, offset: 0x2910 */ + uint8_t RESERVED_263[12]; + __IO uint32_t ALU_B_DBG; /**< This register is used for debugging alu block, offset: 0x2920 */ + uint8_t RESERVED_264[220]; + __IO uint32_t HIST_A_CTRL; /**< Histogram Control Register., offset: 0x2A00 */ + uint8_t RESERVED_265[12]; + __IO uint32_t HIST_A_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A10 */ + uint8_t RESERVED_266[12]; + __IO uint32_t HIST_A_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2A20 */ + uint8_t RESERVED_267[12]; + __I uint32_t HIST_A_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2A30 */ + uint8_t RESERVED_268[12]; + __I uint32_t HIST_A_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2A40 */ + uint8_t RESERVED_269[12]; + __I uint32_t HIST_A_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2A50 */ + uint8_t RESERVED_270[12]; + __I uint32_t HIST_A_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A60 */ + uint8_t RESERVED_271[12]; + __I uint32_t HIST_A_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A70 */ + uint8_t RESERVED_272[12]; + __IO uint32_t HIST_B_CTRL; /**< Histogram Control Register., offset: 0x2A80 */ + uint8_t RESERVED_273[12]; + __IO uint32_t HIST_B_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A90 */ + uint8_t RESERVED_274[12]; + __IO uint32_t HIST_B_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2AA0 */ + uint8_t RESERVED_275[12]; + __I uint32_t HIST_B_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2AB0 */ + uint8_t RESERVED_276[12]; + __I uint32_t HIST_B_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2AC0 */ + uint8_t RESERVED_277[12]; + __I uint32_t HIST_B_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2AD0 */ + uint8_t RESERVED_278[12]; + __I uint32_t HIST_B_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AE0 */ + uint8_t RESERVED_279[12]; + __I uint32_t HIST_B_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AF0 */ + uint8_t RESERVED_280[12]; + __IO uint32_t HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x2B00 */ + uint8_t RESERVED_281[12]; + __IO uint32_t HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x2B10 */ + uint8_t RESERVED_282[12]; + __IO uint32_t HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x2B20 */ + uint8_t RESERVED_283[12]; + __IO uint32_t HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x2B30 */ + uint8_t RESERVED_284[12]; + __IO uint32_t HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x2B40 */ + uint8_t RESERVED_285[12]; + __IO uint32_t HIST16_PARAM1; /**< 16-level Histogram Parameter 1 Register., offset: 0x2B50 */ + uint8_t RESERVED_286[12]; + __IO uint32_t HIST16_PARAM2; /**< 16-level Histogram Parameter 2 Register., offset: 0x2B60 */ + uint8_t RESERVED_287[12]; + __IO uint32_t HIST16_PARAM3; /**< 16-level Histogram Parameter 3 Register., offset: 0x2B70 */ + uint8_t RESERVED_288[12]; + __IO uint32_t HIST32_PARAM0; /**< 32-level Histogram Parameter 0 Register., offset: 0x2B80 */ + uint8_t RESERVED_289[12]; + __IO uint32_t HIST32_PARAM1; /**< 32-level Histogram Parameter 1 Register., offset: 0x2B90 */ + uint8_t RESERVED_290[12]; + __IO uint32_t HIST32_PARAM2; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BA0 */ + uint8_t RESERVED_291[12]; + __IO uint32_t HIST32_PARAM3; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BB0 */ + uint8_t RESERVED_292[12]; + __IO uint32_t HIST32_PARAM4; /**< 32-level Histogram Parameter 0 Register., offset: 0x2BC0 */ + uint8_t RESERVED_293[12]; + __IO uint32_t HIST32_PARAM5; /**< 32-level Histogram Parameter 1 Register., offset: 0x2BD0 */ + uint8_t RESERVED_294[12]; + __IO uint32_t HIST32_PARAM6; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BE0 */ + uint8_t RESERVED_295[12]; + __IO uint32_t HIST32_PARAM7; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BF0 */ + uint8_t RESERVED_296[252]; + __IO uint32_t HANDSHAKE_READY_MUX0; /**< This register defines the pxp subblock handshake signals ready mux on top level., offset: 0x2CF0 */ + uint8_t RESERVED_297[12]; + __IO uint32_t HANDSHAKE_READY_MUX1; /**< This register defines the pxp subblock handshake signals ready mux on top level., offset: 0x2D00 */ + uint8_t RESERVED_298[12]; + __IO uint32_t HANDSHAKE_DONE_MUX0; /**< This register defines the pxp subblock handshake signals done mux on top level., offset: 0x2D10 */ + uint8_t RESERVED_299[12]; + __IO uint32_t HANDSHAKE_DONE_MUX1; /**< This register defines the pxp subblock handshake signals done mux on top level., offset: 0x2D20 */ +} PXP_Type; + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/*! @name CTRL - Control Register 0 */ +#define PXP_CTRL_ENABLE_MASK (0x1U) +#define PXP_CTRL_ENABLE_SHIFT (0U) +#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) +#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_ROTATE0_MASK (0x300U) +#define PXP_CTRL_ROTATE0_SHIFT (8U) +#define PXP_CTRL_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE0_SHIFT)) & PXP_CTRL_ROTATE0_MASK) +#define PXP_CTRL_HFLIP0_MASK (0x400U) +#define PXP_CTRL_HFLIP0_SHIFT (10U) +#define PXP_CTRL_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP0_SHIFT)) & PXP_CTRL_HFLIP0_MASK) +#define PXP_CTRL_VFLIP0_MASK (0x800U) +#define PXP_CTRL_VFLIP0_SHIFT (11U) +#define PXP_CTRL_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP0_SHIFT)) & PXP_CTRL_VFLIP0_MASK) +#define PXP_CTRL_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_ROTATE1_SHIFT (12U) +#define PXP_CTRL_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE1_SHIFT)) & PXP_CTRL_ROTATE1_MASK) +#define PXP_CTRL_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_HFLIP1_SHIFT (14U) +#define PXP_CTRL_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP1_SHIFT)) & PXP_CTRL_HFLIP1_MASK) +#define PXP_CTRL_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_VFLIP1_SHIFT (15U) +#define PXP_CTRL_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP1_SHIFT)) & PXP_CTRL_VFLIP1_MASK) +#define PXP_CTRL_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_DITHER_SHIFT)) & PXP_CTRL_ENABLE_DITHER_MASK) +#define PXP_CTRL_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_ENABLE_WFE_B_MASK) +#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) +#define PXP_CTRL_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_CSC2_SHIFT)) & PXP_CTRL_ENABLE_CSC2_MASK) +#define PXP_CTRL_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LUT_SHIFT)) & PXP_CTRL_ENABLE_LUT_MASK) +#define PXP_CTRL_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) +#define PXP_CTRL_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) +#define PXP_CTRL_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SFTRST_SHIFT (31U) +#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - Control Register 0 */ +#define PXP_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) +#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL_SET_ROTATE0_SHIFT (8U) +#define PXP_CTRL_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE0_SHIFT)) & PXP_CTRL_SET_ROTATE0_MASK) +#define PXP_CTRL_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL_SET_HFLIP0_SHIFT (10U) +#define PXP_CTRL_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP0_SHIFT)) & PXP_CTRL_SET_HFLIP0_MASK) +#define PXP_CTRL_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL_SET_VFLIP0_SHIFT (11U) +#define PXP_CTRL_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP0_SHIFT)) & PXP_CTRL_SET_VFLIP0_MASK) +#define PXP_CTRL_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_SET_ROTATE1_SHIFT (12U) +#define PXP_CTRL_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE1_SHIFT)) & PXP_CTRL_SET_ROTATE1_MASK) +#define PXP_CTRL_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_SET_HFLIP1_SHIFT (14U) +#define PXP_CTRL_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP1_SHIFT)) & PXP_CTRL_SET_HFLIP1_MASK) +#define PXP_CTRL_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_SET_VFLIP1_SHIFT (15U) +#define PXP_CTRL_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP1_SHIFT)) & PXP_CTRL_SET_VFLIP1_MASK) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_SET_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_SET_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_SET_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL_SET_ENABLE_DITHER_MASK) +#define PXP_CTRL_SET_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_SET_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_SET_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_SET_ENABLE_WFE_B_MASK) +#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_SET_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL_SET_ENABLE_CSC2_MASK) +#define PXP_CTRL_SET_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_SET_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_SET_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL_SET_ENABLE_LUT_MASK) +#define PXP_CTRL_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) +#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_SET_CLKGATE_SHIFT (30U) +#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) +#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SET_SFTRST_SHIFT (31U) +#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - Control Register 0 */ +#define PXP_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) +#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL_CLR_ROTATE0_SHIFT (8U) +#define PXP_CTRL_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ROTATE0_MASK) +#define PXP_CTRL_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL_CLR_HFLIP0_SHIFT (10U) +#define PXP_CTRL_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP0_SHIFT)) & PXP_CTRL_CLR_HFLIP0_MASK) +#define PXP_CTRL_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL_CLR_VFLIP0_SHIFT (11U) +#define PXP_CTRL_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP0_SHIFT)) & PXP_CTRL_CLR_VFLIP0_MASK) +#define PXP_CTRL_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_CLR_ROTATE1_SHIFT (12U) +#define PXP_CTRL_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ROTATE1_MASK) +#define PXP_CTRL_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_CLR_HFLIP1_SHIFT (14U) +#define PXP_CTRL_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP1_SHIFT)) & PXP_CTRL_CLR_HFLIP1_MASK) +#define PXP_CTRL_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_CLR_VFLIP1_SHIFT (15U) +#define PXP_CTRL_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP1_SHIFT)) & PXP_CTRL_CLR_VFLIP1_MASK) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_CLR_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_CLR_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_CLR_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL_CLR_ENABLE_DITHER_MASK) +#define PXP_CTRL_CLR_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_CLR_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_CLR_ENABLE_WFE_B_MASK) +#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_CLR_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL_CLR_ENABLE_CSC2_MASK) +#define PXP_CTRL_CLR_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_CLR_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_CLR_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_LUT_MASK) +#define PXP_CTRL_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) +#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) +#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_CLR_SFTRST_SHIFT (31U) +#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - Control Register 0 */ +#define PXP_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) +#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL_TOG_ROTATE0_SHIFT (8U) +#define PXP_CTRL_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ROTATE0_MASK) +#define PXP_CTRL_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL_TOG_HFLIP0_SHIFT (10U) +#define PXP_CTRL_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP0_SHIFT)) & PXP_CTRL_TOG_HFLIP0_MASK) +#define PXP_CTRL_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL_TOG_VFLIP0_SHIFT (11U) +#define PXP_CTRL_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP0_SHIFT)) & PXP_CTRL_TOG_VFLIP0_MASK) +#define PXP_CTRL_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_TOG_ROTATE1_SHIFT (12U) +#define PXP_CTRL_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ROTATE1_MASK) +#define PXP_CTRL_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_TOG_HFLIP1_SHIFT (14U) +#define PXP_CTRL_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP1_SHIFT)) & PXP_CTRL_TOG_HFLIP1_MASK) +#define PXP_CTRL_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_TOG_VFLIP1_SHIFT (15U) +#define PXP_CTRL_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP1_SHIFT)) & PXP_CTRL_TOG_VFLIP1_MASK) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_TOG_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_TOG_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_TOG_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL_TOG_ENABLE_DITHER_MASK) +#define PXP_CTRL_TOG_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_TOG_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_TOG_ENABLE_WFE_B_MASK) +#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_TOG_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL_TOG_ENABLE_CSC2_MASK) +#define PXP_CTRL_TOG_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_TOG_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_TOG_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_LUT_MASK) +#define PXP_CTRL_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) +#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) +#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) +#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_TOG_SFTRST_SHIFT (31U) +#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) + +/*! @name STAT - Status Register */ +#define PXP_STAT_IRQ0_MASK (0x1U) +#define PXP_STAT_IRQ0_SHIFT (0U) +#define PXP_STAT_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ0_SHIFT)) & PXP_STAT_IRQ0_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) +#define PXP_STAT_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_BLOCKY_SHIFT (16U) +#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) +#define PXP_STAT_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_BLOCKX_SHIFT (24U) +#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) + +/*! @name STAT_SET - Status Register */ +#define PXP_STAT_SET_IRQ0_MASK (0x1U) +#define PXP_STAT_SET_IRQ0_SHIFT (0U) +#define PXP_STAT_SET_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ0_SHIFT)) & PXP_STAT_SET_IRQ0_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_SET_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_SET_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_SET_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_SET_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_SET_BLOCKY_SHIFT (16U) +#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) +#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_SET_BLOCKX_SHIFT (24U) +#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) + +/*! @name STAT_CLR - Status Register */ +#define PXP_STAT_CLR_IRQ0_MASK (0x1U) +#define PXP_STAT_CLR_IRQ0_SHIFT (0U) +#define PXP_STAT_CLR_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ0_SHIFT)) & PXP_STAT_CLR_IRQ0_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_CLR_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_CLR_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_CLR_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_CLR_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_CLR_BLOCKY_SHIFT (16U) +#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) +#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_CLR_BLOCKX_SHIFT (24U) +#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) + +/*! @name STAT_TOG - Status Register */ +#define PXP_STAT_TOG_IRQ0_MASK (0x1U) +#define PXP_STAT_TOG_IRQ0_SHIFT (0U) +#define PXP_STAT_TOG_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ0_SHIFT)) & PXP_STAT_TOG_IRQ0_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_TOG_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_TOG_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_TOG_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_TOG_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_TOG_BLOCKY_SHIFT (16U) +#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) +#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_TOG_BLOCKX_SHIFT (24U) +#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) + +/*! @name OUT_CTRL - Output Buffer Control Register */ +#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) + +/*! @name OUT_CTRL_SET - Output Buffer Control Register */ +#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) + +/*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) + +/*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) + +/*! @name OUT_BUF - Output Frame Buffer Pointer */ +#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF_ADDR_SHIFT (0U) +#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) + +/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ +#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF2_ADDR_SHIFT (0U) +#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) + +/*! @name OUT_PITCH - Output Buffer Pitch */ +#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_OUT_PITCH_PITCH_SHIFT (0U) +#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) + +/*! @name OUT_LRC - Output Surface Lower Right Coordinate */ +#define PXP_OUT_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_LRC_Y_SHIFT (0U) +#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) +#define PXP_OUT_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_LRC_X_SHIFT (16U) +#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) + +/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ +#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_ULC_Y_SHIFT (0U) +#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) +#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_ULC_X_SHIFT (16U) +#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) + +/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ +#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_LRC_Y_SHIFT (0U) +#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) +#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_LRC_X_SHIFT (16U) +#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) + +/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ +#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_ULC_Y_SHIFT (0U) +#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) +#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_ULC_X_SHIFT (16U) +#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) + +/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ +#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_LRC_Y_SHIFT (0U) +#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) +#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_LRC_X_SHIFT (16U) +#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) + +/*! @name PS_CTRL - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) +#define PXP_PS_CTRL_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) +#define PXP_PS_CTRL_DECY_MASK (0x300U) +#define PXP_PS_CTRL_DECY_SHIFT (8U) +#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) +#define PXP_PS_CTRL_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_DECX_SHIFT (10U) +#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) + +/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) +#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) +#define PXP_PS_CTRL_SET_DECY_MASK (0x300U) +#define PXP_PS_CTRL_SET_DECY_SHIFT (8U) +#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) +#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_SET_DECX_SHIFT (10U) +#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) + +/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) +#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) +#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) +#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) +#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) +#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) +#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) + +/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) +#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) +#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) +#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) +#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) +#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) +#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) + +/*! @name PS_BUF - PS Input Buffer Address */ +#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_BUF_ADDR_SHIFT (0U) +#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) + +/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ +#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_UBUF_ADDR_SHIFT (0U) +#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) + +/*! @name PS_VBUF - PS V/Cr Input Buffer Address */ +#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_VBUF_ADDR_SHIFT (0U) +#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) + +/*! @name PS_PITCH - Processed Surface Pitch */ +#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_PS_PITCH_PITCH_SHIFT (0U) +#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) + +/*! @name PS_BACKGROUND_0 - PS Background Color */ +#define PXP_PS_BACKGROUND_0_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_0_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_0_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_0_COLOR_SHIFT)) & PXP_PS_BACKGROUND_0_COLOR_MASK) + +/*! @name PS_SCALE - PS Scale Factor Register */ +#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) +#define PXP_PS_SCALE_XSCALE_SHIFT (0U) +#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) +#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) +#define PXP_PS_SCALE_YSCALE_SHIFT (16U) +#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) + +/*! @name PS_OFFSET - PS Scale Offset Register */ +#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) +#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) +#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) +#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) +#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U) +#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) + +/*! @name PS_CLRKEYLOW_0 - PS Color Key Low */ +#define PXP_PS_CLRKEYLOW_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_0_PIXEL_MASK) + +/*! @name PS_CLRKEYHIGH_0 - PS Color Key High */ +#define PXP_PS_CLRKEYHIGH_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_0_PIXEL_MASK) + +/*! @name AS_CTRL - Alpha Surface Control */ +#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) +#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) +#define PXP_AS_CTRL_FORMAT_MASK (0xF0U) +#define PXP_AS_CTRL_FORMAT_SHIFT (4U) +#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) +#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) +#define PXP_AS_CTRL_ALPHA_SHIFT (8U) +#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) +#define PXP_AS_CTRL_ROP_MASK (0xF0000U) +#define PXP_AS_CTRL_ROP_SHIFT (16U) +#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) +#define PXP_AS_CTRL_ALPHA0_INVERT_MASK (0x100000U) +#define PXP_AS_CTRL_ALPHA0_INVERT_SHIFT (20U) +#define PXP_AS_CTRL_ALPHA0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA0_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA0_INVERT_MASK) +#define PXP_AS_CTRL_ALPHA1_INVERT_MASK (0x200000U) +#define PXP_AS_CTRL_ALPHA1_INVERT_SHIFT (21U) +#define PXP_AS_CTRL_ALPHA1_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA1_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA1_INVERT_MASK) + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_AS_BUF_ADDR_SHIFT (0U) +#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) + +/*! @name AS_PITCH - Alpha Surface Pitch */ +#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_AS_PITCH_PITCH_SHIFT (0U) +#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) + +/*! @name AS_CLRKEYLOW_0 - Overlay Color Key Low */ +#define PXP_AS_CLRKEYLOW_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_0_PIXEL_MASK) + +/*! @name AS_CLRKEYHIGH_0 - Overlay Color Key High */ +#define PXP_AS_CLRKEYHIGH_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_0_PIXEL_MASK) + +/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ +#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) +#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) +#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) +#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) +#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) +#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) +#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) +#define PXP_CSC1_COEF0_C0_SHIFT (18U) +#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) +#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) +#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U) +#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) +#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) +#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) +#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) + +/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ +#define PXP_CSC1_COEF1_C4_MASK (0x7FFU) +#define PXP_CSC1_COEF1_C4_SHIFT (0U) +#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) +#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) +#define PXP_CSC1_COEF1_C1_SHIFT (16U) +#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) + +/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ +#define PXP_CSC1_COEF2_C3_MASK (0x7FFU) +#define PXP_CSC1_COEF2_C3_SHIFT (0U) +#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) +#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) +#define PXP_CSC1_COEF2_C2_SHIFT (16U) +#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) + +/*! @name CSC2_CTRL - Color Space Conversion Control Register. */ +#define PXP_CSC2_CTRL_BYPASS_MASK (0x1U) +#define PXP_CSC2_CTRL_BYPASS_SHIFT (0U) +#define PXP_CSC2_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_BYPASS_SHIFT)) & PXP_CSC2_CTRL_BYPASS_MASK) +#define PXP_CSC2_CTRL_CSC_MODE_MASK (0x6U) +#define PXP_CSC2_CTRL_CSC_MODE_SHIFT (1U) +#define PXP_CSC2_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_CSC_MODE_SHIFT)) & PXP_CSC2_CTRL_CSC_MODE_MASK) + +/*! @name CSC2_COEF0 - Color Space Conversion Coefficient Register 0 */ +#define PXP_CSC2_COEF0_A1_MASK (0x7FFU) +#define PXP_CSC2_COEF0_A1_SHIFT (0U) +#define PXP_CSC2_COEF0_A1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A1_SHIFT)) & PXP_CSC2_COEF0_A1_MASK) +#define PXP_CSC2_COEF0_A2_MASK (0x7FF0000U) +#define PXP_CSC2_COEF0_A2_SHIFT (16U) +#define PXP_CSC2_COEF0_A2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A2_SHIFT)) & PXP_CSC2_COEF0_A2_MASK) + +/*! @name CSC2_COEF1 - Color Space Conversion Coefficient Register 1 */ +#define PXP_CSC2_COEF1_A3_MASK (0x7FFU) +#define PXP_CSC2_COEF1_A3_SHIFT (0U) +#define PXP_CSC2_COEF1_A3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_A3_SHIFT)) & PXP_CSC2_COEF1_A3_MASK) +#define PXP_CSC2_COEF1_B1_MASK (0x7FF0000U) +#define PXP_CSC2_COEF1_B1_SHIFT (16U) +#define PXP_CSC2_COEF1_B1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_B1_SHIFT)) & PXP_CSC2_COEF1_B1_MASK) + +/*! @name CSC2_COEF2 - Color Space Conversion Coefficient Register 2 */ +#define PXP_CSC2_COEF2_B2_MASK (0x7FFU) +#define PXP_CSC2_COEF2_B2_SHIFT (0U) +#define PXP_CSC2_COEF2_B2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B2_SHIFT)) & PXP_CSC2_COEF2_B2_MASK) +#define PXP_CSC2_COEF2_B3_MASK (0x7FF0000U) +#define PXP_CSC2_COEF2_B3_SHIFT (16U) +#define PXP_CSC2_COEF2_B3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B3_SHIFT)) & PXP_CSC2_COEF2_B3_MASK) + +/*! @name CSC2_COEF3 - Color Space Conversion Coefficient Register 3 */ +#define PXP_CSC2_COEF3_C1_MASK (0x7FFU) +#define PXP_CSC2_COEF3_C1_SHIFT (0U) +#define PXP_CSC2_COEF3_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C1_SHIFT)) & PXP_CSC2_COEF3_C1_MASK) +#define PXP_CSC2_COEF3_C2_MASK (0x7FF0000U) +#define PXP_CSC2_COEF3_C2_SHIFT (16U) +#define PXP_CSC2_COEF3_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C2_SHIFT)) & PXP_CSC2_COEF3_C2_MASK) + +/*! @name CSC2_COEF4 - Color Space Conversion Coefficient Register 4 */ +#define PXP_CSC2_COEF4_C3_MASK (0x7FFU) +#define PXP_CSC2_COEF4_C3_SHIFT (0U) +#define PXP_CSC2_COEF4_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_C3_SHIFT)) & PXP_CSC2_COEF4_C3_MASK) +#define PXP_CSC2_COEF4_D1_MASK (0x1FF0000U) +#define PXP_CSC2_COEF4_D1_SHIFT (16U) +#define PXP_CSC2_COEF4_D1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_D1_SHIFT)) & PXP_CSC2_COEF4_D1_MASK) + +/*! @name CSC2_COEF5 - Color Space Conversion Coefficient Register 5 */ +#define PXP_CSC2_COEF5_D2_MASK (0x1FFU) +#define PXP_CSC2_COEF5_D2_SHIFT (0U) +#define PXP_CSC2_COEF5_D2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D2_SHIFT)) & PXP_CSC2_COEF5_D2_MASK) +#define PXP_CSC2_COEF5_D3_MASK (0x1FF0000U) +#define PXP_CSC2_COEF5_D3_SHIFT (16U) +#define PXP_CSC2_COEF5_D3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D3_SHIFT)) & PXP_CSC2_COEF5_D3_MASK) + +/*! @name LUT_CTRL - Lookup Table Control Register. */ +#define PXP_LUT_CTRL_DMA_START_MASK (0x1U) +#define PXP_LUT_CTRL_DMA_START_SHIFT (0U) +#define PXP_LUT_CTRL_DMA_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_DMA_START_SHIFT)) & PXP_LUT_CTRL_DMA_START_MASK) +#define PXP_LUT_CTRL_INVALID_MASK (0x100U) +#define PXP_LUT_CTRL_INVALID_SHIFT (8U) +#define PXP_LUT_CTRL_INVALID(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_INVALID_SHIFT)) & PXP_LUT_CTRL_INVALID_MASK) +#define PXP_LUT_CTRL_LRU_UPD_MASK (0x200U) +#define PXP_LUT_CTRL_LRU_UPD_SHIFT (9U) +#define PXP_LUT_CTRL_LRU_UPD(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LRU_UPD_SHIFT)) & PXP_LUT_CTRL_LRU_UPD_MASK) +#define PXP_LUT_CTRL_SEL_8KB_MASK (0x400U) +#define PXP_LUT_CTRL_SEL_8KB_SHIFT (10U) +#define PXP_LUT_CTRL_SEL_8KB(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_SEL_8KB_SHIFT)) & PXP_LUT_CTRL_SEL_8KB_MASK) +#define PXP_LUT_CTRL_OUT_MODE_MASK (0x30000U) +#define PXP_LUT_CTRL_OUT_MODE_SHIFT (16U) +#define PXP_LUT_CTRL_OUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_OUT_MODE_SHIFT)) & PXP_LUT_CTRL_OUT_MODE_MASK) +#define PXP_LUT_CTRL_LOOKUP_MODE_MASK (0x3000000U) +#define PXP_LUT_CTRL_LOOKUP_MODE_SHIFT (24U) +#define PXP_LUT_CTRL_LOOKUP_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LOOKUP_MODE_SHIFT)) & PXP_LUT_CTRL_LOOKUP_MODE_MASK) +#define PXP_LUT_CTRL_BYPASS_MASK (0x80000000U) +#define PXP_LUT_CTRL_BYPASS_SHIFT (31U) +#define PXP_LUT_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_BYPASS_SHIFT)) & PXP_LUT_CTRL_BYPASS_MASK) + +/*! @name LUT_ADDR - Lookup Table Control Register. */ +#define PXP_LUT_ADDR_ADDR_MASK (0x3FFFU) +#define PXP_LUT_ADDR_ADDR_SHIFT (0U) +#define PXP_LUT_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_ADDR_SHIFT)) & PXP_LUT_ADDR_ADDR_MASK) +#define PXP_LUT_ADDR_NUM_BYTES_MASK (0x7FFF0000U) +#define PXP_LUT_ADDR_NUM_BYTES_SHIFT (16U) +#define PXP_LUT_ADDR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_NUM_BYTES_SHIFT)) & PXP_LUT_ADDR_NUM_BYTES_MASK) + +/*! @name LUT_DATA - Lookup Table Data Register. */ +#define PXP_LUT_DATA_DATA_MASK (0xFFFFFFFFU) +#define PXP_LUT_DATA_DATA_SHIFT (0U) +#define PXP_LUT_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_DATA_DATA_SHIFT)) & PXP_LUT_DATA_DATA_MASK) + +/*! @name LUT_EXTMEM - Lookup Table External Memory Address Register. */ +#define PXP_LUT_EXTMEM_ADDR_MASK (0xFFFFFFFFU) +#define PXP_LUT_EXTMEM_ADDR_SHIFT (0U) +#define PXP_LUT_EXTMEM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_EXTMEM_ADDR_SHIFT)) & PXP_LUT_EXTMEM_ADDR_MASK) + +/*! @name CFA - Color Filter Array Register. */ +#define PXP_CFA_DATA_MASK (0xFFFFFFFFU) +#define PXP_CFA_DATA_SHIFT (0U) +#define PXP_CFA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_CFA_DATA_SHIFT)) & PXP_CFA_DATA_MASK) + +/*! @name ALPHA_A_CTRL - PXP Alpha Engine A Control Register. */ +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK (0x20U) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT (5U) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK (0x40U) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT (6U) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK (0x1000U) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT (12U) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK (0x2000U) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT (13U) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK) + +/*! @name PS_BACKGROUND_1 - PS Background Color 1 */ +#define PXP_PS_BACKGROUND_1_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_1_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_1_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_1_COLOR_SHIFT)) & PXP_PS_BACKGROUND_1_COLOR_MASK) + +/*! @name PS_CLRKEYLOW_1 - PS Color Key Low 1 */ +#define PXP_PS_CLRKEYLOW_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_1_PIXEL_MASK) + +/*! @name PS_CLRKEYHIGH_1 - PS Color Key High 1 */ +#define PXP_PS_CLRKEYHIGH_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_1_PIXEL_MASK) + +/*! @name AS_CLRKEYLOW_1 - Overlay Color Key Low */ +#define PXP_AS_CLRKEYLOW_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_1_PIXEL_MASK) + +/*! @name AS_CLRKEYHIGH_1 - Overlay Color Key High */ +#define PXP_AS_CLRKEYHIGH_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_1_PIXEL_MASK) + +/*! @name CTRL2 - Control Register 2 */ +#define PXP_CTRL2_ENABLE_MASK (0x1U) +#define PXP_CTRL2_ENABLE_SHIFT (0U) +#define PXP_CTRL2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_SHIFT)) & PXP_CTRL2_ENABLE_MASK) +#define PXP_CTRL2_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE0_SHIFT)) & PXP_CTRL2_ROTATE0_MASK) +#define PXP_CTRL2_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP0_SHIFT)) & PXP_CTRL2_HFLIP0_MASK) +#define PXP_CTRL2_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP0_SHIFT)) & PXP_CTRL2_VFLIP0_MASK) +#define PXP_CTRL2_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE1_SHIFT)) & PXP_CTRL2_ROTATE1_MASK) +#define PXP_CTRL2_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP1_SHIFT)) & PXP_CTRL2_HFLIP1_MASK) +#define PXP_CTRL2_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP1_SHIFT)) & PXP_CTRL2_VFLIP1_MASK) +#define PXP_CTRL2_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_ENABLE_DITHER_MASK) +#define PXP_CTRL2_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_BLOCK_SIZE_MASK) +#define PXP_CTRL2_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_ENABLE_CSC2_MASK) +#define PXP_CTRL2_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_LUT_SHIFT)) & PXP_CTRL2_ENABLE_LUT_MASK) +#define PXP_CTRL2_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_SET - Control Register 2 */ +#define PXP_CTRL2_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL2_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_SHIFT)) & PXP_CTRL2_SET_ENABLE_MASK) +#define PXP_CTRL2_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_SET_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ROTATE0_MASK) +#define PXP_CTRL2_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_SET_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP0_SHIFT)) & PXP_CTRL2_SET_HFLIP0_MASK) +#define PXP_CTRL2_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_SET_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP0_SHIFT)) & PXP_CTRL2_SET_VFLIP0_MASK) +#define PXP_CTRL2_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_SET_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ROTATE1_MASK) +#define PXP_CTRL2_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_SET_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP1_SHIFT)) & PXP_CTRL2_SET_HFLIP1_MASK) +#define PXP_CTRL2_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_SET_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP1_SHIFT)) & PXP_CTRL2_SET_VFLIP1_MASK) +#define PXP_CTRL2_SET_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_SET_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_SET_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_SET_ENABLE_DITHER_MASK) +#define PXP_CTRL2_SET_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_SET_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_SET_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_SET_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL2_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_SET_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_SET_ENABLE_CSC2_MASK) +#define PXP_CTRL2_SET_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_SET_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_SET_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL2_SET_ENABLE_LUT_MASK) +#define PXP_CTRL2_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_CLR - Control Register 2 */ +#define PXP_CTRL2_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL2_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_SHIFT)) & PXP_CTRL2_CLR_ENABLE_MASK) +#define PXP_CTRL2_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_CLR_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ROTATE0_MASK) +#define PXP_CTRL2_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_CLR_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP0_SHIFT)) & PXP_CTRL2_CLR_HFLIP0_MASK) +#define PXP_CTRL2_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_CLR_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP0_SHIFT)) & PXP_CTRL2_CLR_VFLIP0_MASK) +#define PXP_CTRL2_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_CLR_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ROTATE1_MASK) +#define PXP_CTRL2_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_CLR_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP1_SHIFT)) & PXP_CTRL2_CLR_HFLIP1_MASK) +#define PXP_CTRL2_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_CLR_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP1_SHIFT)) & PXP_CTRL2_CLR_VFLIP1_MASK) +#define PXP_CTRL2_CLR_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_CLR_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_CLR_ENABLE_DITHER_MASK) +#define PXP_CTRL2_CLR_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_CLR_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_CLR_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL2_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_CLR_ENABLE_CSC2_MASK) +#define PXP_CTRL2_CLR_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_CLR_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_CLR_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL2_CLR_ENABLE_LUT_MASK) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_TOG - Control Register 2 */ +#define PXP_CTRL2_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL2_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_SHIFT)) & PXP_CTRL2_TOG_ENABLE_MASK) +#define PXP_CTRL2_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_TOG_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ROTATE0_MASK) +#define PXP_CTRL2_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_TOG_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP0_SHIFT)) & PXP_CTRL2_TOG_HFLIP0_MASK) +#define PXP_CTRL2_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_TOG_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP0_SHIFT)) & PXP_CTRL2_TOG_VFLIP0_MASK) +#define PXP_CTRL2_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_TOG_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ROTATE1_MASK) +#define PXP_CTRL2_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_TOG_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP1_SHIFT)) & PXP_CTRL2_TOG_HFLIP1_MASK) +#define PXP_CTRL2_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_TOG_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP1_SHIFT)) & PXP_CTRL2_TOG_VFLIP1_MASK) +#define PXP_CTRL2_TOG_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_TOG_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_TOG_ENABLE_DITHER_MASK) +#define PXP_CTRL2_TOG_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_TOG_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_TOG_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL2_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_TOG_ENABLE_CSC2_MASK) +#define PXP_CTRL2_TOG_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_TOG_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_TOG_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL2_TOG_ENABLE_LUT_MASK) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK) + +/*! @name POWER_REG0 - PXP Power Control Register. */ +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK (0x7U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT (0U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK (0x38U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT (3U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK (0x1C0U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT (6U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT (9U) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK) +#define PXP_POWER_REG0_CTRL_MASK (0xFFFFF000U) +#define PXP_POWER_REG0_CTRL_SHIFT (12U) +#define PXP_POWER_REG0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_CTRL_SHIFT)) & PXP_POWER_REG0_CTRL_MASK) + +/*! @name POWER_REG1 - PXP Power Control Register 1. */ +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK (0x7U) +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT (0U) +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK (0x38U) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT (3U) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK (0x1C0U) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT (6U) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT (9U) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK (0x7000U) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT (12U) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK (0x38000U) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT (15U) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK (0x1C0000U) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT (18U) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK (0xE00000U) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT (21U) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK) + +/*! @name DATA_PATH_CTRL0 - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_SET - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_CLR - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_TOG - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL1 - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_SET - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_CLR - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_TOG - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK) + +/*! @name INIT_MEM_CTRL - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_START_SHIFT)) & PXP_INIT_MEM_CTRL_START_MASK) + +/*! @name INIT_MEM_CTRL_SET - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_SET_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_SET_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_SET_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SET_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_SET_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_SET_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_SET_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_START_SHIFT)) & PXP_INIT_MEM_CTRL_SET_START_MASK) + +/*! @name INIT_MEM_CTRL_CLR - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_CLR_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_CLR_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_CLR_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_CLR_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_START_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_START_MASK) + +/*! @name INIT_MEM_CTRL_TOG - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_TOG_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_TOG_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_TOG_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_TOG_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_START_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_START_MASK) + +/*! @name INIT_MEM_DATA - Write data Register */ +#define PXP_INIT_MEM_DATA_DATA_MASK (0xFFFFFFFFU) +#define PXP_INIT_MEM_DATA_DATA_SHIFT (0U) +#define PXP_INIT_MEM_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_DATA_SHIFT)) & PXP_INIT_MEM_DATA_DATA_MASK) + +/*! @name INIT_MEM_DATA_HIGH - Write data Register */ +#define PXP_INIT_MEM_DATA_HIGH_DATA_MASK (0xFFFFFFFFU) +#define PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT (0U) +#define PXP_INIT_MEM_DATA_HIGH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT)) & PXP_INIT_MEM_DATA_HIGH_DATA_MASK) + +/*! @name IRQ_MASK - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_SET - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_CLR - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_TOG - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ - PXP Interrupt Register */ +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_SET - PXP Interrupt Register */ +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_CLR - PXP Interrupt Register */ +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_TOG - PXP Interrupt Register */ +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK) + +/*! @name NEXT_EN - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_LEGACY_SHIFT)) & PXP_NEXT_EN_LEGACY_MASK) +#define PXP_NEXT_EN_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_WFEB_SHIFT)) & PXP_NEXT_EN_WFEB_MASK) + +/*! @name NEXT_EN_SET - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_SET_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_SET_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_SET_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_SET_LEGACY_SHIFT)) & PXP_NEXT_EN_SET_LEGACY_MASK) +#define PXP_NEXT_EN_SET_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_SET_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_SET_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_SET_WFEB_SHIFT)) & PXP_NEXT_EN_SET_WFEB_MASK) + +/*! @name NEXT_EN_CLR - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_CLR_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_CLR_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_CLR_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_CLR_LEGACY_SHIFT)) & PXP_NEXT_EN_CLR_LEGACY_MASK) +#define PXP_NEXT_EN_CLR_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_CLR_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_CLR_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_CLR_WFEB_SHIFT)) & PXP_NEXT_EN_CLR_WFEB_MASK) + +/*! @name NEXT_EN_TOG - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_TOG_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_TOG_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_TOG_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_TOG_LEGACY_SHIFT)) & PXP_NEXT_EN_TOG_LEGACY_MASK) +#define PXP_NEXT_EN_TOG_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_TOG_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_TOG_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_TOG_WFEB_SHIFT)) & PXP_NEXT_EN_TOG_WFEB_MASK) + +/*! @name NEXT - Next Frame Pointer */ +#define PXP_NEXT_ENABLED_MASK (0x1U) +#define PXP_NEXT_ENABLED_SHIFT (0U) +#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) +#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) +#define PXP_NEXT_POINTER_SHIFT (2U) +#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) + +/*! @name DEBUGCTRL - Debug Control Register */ +#define PXP_DEBUGCTRL_SELECT_MASK (0xFFU) +#define PXP_DEBUGCTRL_SELECT_SHIFT (0U) +#define PXP_DEBUGCTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUGCTRL_SELECT_SHIFT)) & PXP_DEBUGCTRL_SELECT_MASK) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_MASK (0xF00U) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_SHIFT (8U) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_SHIFT)) & PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_MASK) + +/*! @name DEBUG - Debug Register */ +#define PXP_DEBUG_DATA_MASK (0xFFFFFFFFU) +#define PXP_DEBUG_DATA_SHIFT (0U) +#define PXP_DEBUG_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUG_DATA_SHIFT)) & PXP_DEBUG_DATA_MASK) + +/*! @name VERSION - Version Register */ +#define PXP_VERSION_STEP_MASK (0xFFFFU) +#define PXP_VERSION_STEP_SHIFT (0U) +#define PXP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_STEP_SHIFT)) & PXP_VERSION_STEP_MASK) +#define PXP_VERSION_MINOR_MASK (0xFF0000U) +#define PXP_VERSION_MINOR_SHIFT (16U) +#define PXP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_MINOR_SHIFT)) & PXP_VERSION_MINOR_MASK) +#define PXP_VERSION_MAJOR_MASK (0xFF000000U) +#define PXP_VERSION_MAJOR_SHIFT (24U) +#define PXP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_MAJOR_SHIFT)) & PXP_VERSION_MAJOR_MASK) + +/*! @name DITHER_STORE_SIZE_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK) + +/*! @name WFB_FETCH_CTRL - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_SET - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_CLR - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_TOG - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_BUF1_ADDR - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT)) & PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_MASK) + +/*! @name WFB_FETCH_BUF1_PITCH - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_PITCH_PITCH_SHIFT)) & PXP_WFB_FETCH_BUF1_PITCH_PITCH_MASK) + +/*! @name WFB_FETCH_BUF1_SIZE - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_MASK) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK) + +/*! @name WFB_FETCH_BUF2_ADDR - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT)) & PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_MASK) + +/*! @name WFB_FETCH_BUF2_PITCH - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_PITCH_PITCH_SHIFT)) & PXP_WFB_FETCH_BUF2_PITCH_PITCH_MASK) + +/*! @name WFB_FETCH_BUF2_SIZE - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_MASK) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK) + +/*! @name WFB_ARRAY_PIXEL0_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL1_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL2_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL3_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL4_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL5_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL6_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL7_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG0_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG1_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG2_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG3_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG4_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG5_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG6_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG7_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_MASK) + +/*! @name WFB_FETCH_BUF1_CORD - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_CORD_XCORD_MASK (0x3FFFU) +#define PXP_WFB_FETCH_BUF1_CORD_XCORD_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_CORD_XCORD_SHIFT)) & PXP_WFB_FETCH_BUF1_CORD_XCORD_MASK) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD_MASK (0x3FFF0000U) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD_SHIFT (16U) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_CORD_YCORD_SHIFT)) & PXP_WFB_FETCH_BUF1_CORD_YCORD_MASK) + +/*! @name WFB_FETCH_BUF2_CORD - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_CORD_XCORD_MASK (0x3FFFU) +#define PXP_WFB_FETCH_BUF2_CORD_XCORD_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_CORD_XCORD_SHIFT)) & PXP_WFB_FETCH_BUF2_CORD_XCORD_MASK) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD_MASK (0x3FFF0000U) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD_SHIFT (16U) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_CORD_YCORD_SHIFT)) & PXP_WFB_FETCH_BUF2_CORD_YCORD_MASK) + +/*! @name WFB_ARRAY_FLAG8_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG9_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG10_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG11_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG12_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG13_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG14_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG15_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_REG0 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0_MASK (0xFFU) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0_SHIFT (0U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE0_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE0_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1_MASK (0xFF00U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1_SHIFT (8U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE1_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE1_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2_MASK (0xFF0000U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2_SHIFT (16U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE2_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE2_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3_MASK (0xFF000000U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3_SHIFT (24U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE3_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE3_MASK) + +/*! @name WFB_ARRAY_REG1 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4_MASK (0xFFU) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4_SHIFT (0U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE4_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE4_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5_MASK (0xFF00U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5_SHIFT (8U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE5_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE5_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6_MASK (0xFF0000U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6_SHIFT (16U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE6_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE6_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7_MASK (0xFF000000U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7_SHIFT (24U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE7_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE7_MASK) + +/*! @name WFB_ARRAY_REG2 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG2_SW_FLAG0_MASK (0x1U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG0_SHIFT (0U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG0_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG0_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1_MASK (0x2U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1_SHIFT (1U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG1_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG1_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2_MASK (0x4U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2_SHIFT (2U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG2_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG2_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3_MASK (0x8U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3_SHIFT (3U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG3_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG3_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4_MASK (0x10U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4_SHIFT (4U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG4_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG4_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5_MASK (0x20U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5_SHIFT (5U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG5_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG5_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6_MASK (0x40U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6_SHIFT (6U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG6_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG6_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7_MASK (0x80U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7_SHIFT (7U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG7_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG7_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8_MASK (0x100U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8_SHIFT (8U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG8_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG8_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9_MASK (0x200U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9_SHIFT (9U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG9_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG9_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10_MASK (0x400U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10_SHIFT (10U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG10_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG10_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11_MASK (0x800U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11_SHIFT (11U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG11_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG11_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12_MASK (0x1000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12_SHIFT (12U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG12_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG12_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13_MASK (0x2000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13_SHIFT (13U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG13_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG13_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14_MASK (0x4000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14_SHIFT (14U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG14_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG14_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15_MASK (0x8000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15_SHIFT (15U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG15_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG15_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0 - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_SET - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_CLR - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_TOG - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1 - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_SET - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_CLR - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_TOG - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_STATUS_CH0 - Store engine status Channel 0 Register */ +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT (0U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT (16U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK) + +/*! @name WFE_B_STORE_STATUS_CH1 - Store engine status Channel 1 Register */ +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT (0U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT (16U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK) + +/*! @name WFE_B_STORE_SIZE_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK) + +/*! @name WFE_B_STORE_SIZE_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT (0U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK) + +/*! @name WFE_B_STORE_PITCH - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT (0U) +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT (16U) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_SET - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_CLR - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_TOG - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_SET - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_CLR - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_TOG - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_ADDR_0_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK) + +/*! @name WFE_B_STORE_ADDR_1_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK) + +/*! @name WFE_B_STORE_FILL_DATA_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT)) & PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK) + +/*! @name WFE_B_STORE_ADDR_0_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK) + +/*! @name WFE_B_STORE_ADDR_1_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK) + +/*! @name WFE_B_STORE_D_MASK0_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK0_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK1_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK1_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK2_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK2_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK3_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK3_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK4_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK4_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK5_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK5_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK6_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK6_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK7_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK7_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_SHIFT_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK (0x3FU) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK (0x80U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT (7U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK (0x3F00U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT (8U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK (0x8000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT (15U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT (16U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK (0x800000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT (23U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT (24U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK (0x80000000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT (31U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK) + +/*! @name WFE_B_STORE_D_SHIFT_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK (0x3FU) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT (0U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK (0x80U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT (7U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK (0x3F00U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT (8U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK (0x8000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT (15U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT (16U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK (0x800000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT (23U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT (24U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK (0x80000000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT (31U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK) + +/*! @name WFE_B_STORE_F_SHIFT_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK (0x3FU) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT (0U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK (0x40U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT (6U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK (0x3F00U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT (8U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK (0x4000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT (14U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT (16U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK (0x400000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT (22U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT (24U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK (0x40000000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT (30U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK) + +/*! @name WFE_B_STORE_F_SHIFT_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK (0x3FU) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT (0U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK (0x40U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT (6U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK (0x3F00U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT (8U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK (0x4000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT (14U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT (16U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK (0x400000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT (22U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT (24U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK (0x40000000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT (30U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK) + +/*! @name WFE_B_STORE_F_MASK_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK (0xFFU) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT (0U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK (0xFF00U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT (8U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK (0xFF0000U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT (16U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK (0xFF000000U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT (24U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK) + +/*! @name WFE_B_STORE_F_MASK_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK (0xFFU) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT (0U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK (0xFF00U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT (8U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK (0xFF0000U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT (16U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK (0xFF000000U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT (24U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK) + +/*! @name FETCH_WFE_B_DEBUG - This register holds the debug bits for the prefetch engine for WFE B. */ +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK (0xFFFFFFU) +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT (0U) +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK (0xF000000U) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT (24U) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK (0x10000000U) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT (28U) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK) + +/*! @name DITHER_CTRL - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_ENABLE0_MASK) +#define PXP_DITHER_CTRL_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_ENABLE1_MASK) +#define PXP_DITHER_CTRL_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_ENABLE2_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY2_SHIFT)) & PXP_DITHER_CTRL_BUSY2_MASK) +#define PXP_DITHER_CTRL_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY1_SHIFT)) & PXP_DITHER_CTRL_BUSY1_MASK) +#define PXP_DITHER_CTRL_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY0_SHIFT)) & PXP_DITHER_CTRL_BUSY0_MASK) + +/*! @name DITHER_CTRL_SET - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_SET_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_SET_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_SET_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE0_MASK) +#define PXP_DITHER_CTRL_SET_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_SET_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_SET_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE1_MASK) +#define PXP_DITHER_CTRL_SET_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_SET_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_SET_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE2_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_SET_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_SET_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_SET_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_SET_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_SET_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY2_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY2_MASK) +#define PXP_DITHER_CTRL_SET_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_SET_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY1_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY1_MASK) +#define PXP_DITHER_CTRL_SET_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_SET_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_SET_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY0_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY0_MASK) + +/*! @name DITHER_CTRL_CLR - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_CLR_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_CLR_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE0_MASK) +#define PXP_DITHER_CTRL_CLR_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_CLR_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE1_MASK) +#define PXP_DITHER_CTRL_CLR_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_CLR_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE2_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_CLR_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_CLR_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_CLR_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_CLR_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY2_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY2_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_CLR_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY1_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY1_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_CLR_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_CLR_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY0_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY0_MASK) + +/*! @name DITHER_CTRL_TOG - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_TOG_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_TOG_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE0_MASK) +#define PXP_DITHER_CTRL_TOG_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_TOG_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE1_MASK) +#define PXP_DITHER_CTRL_TOG_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_TOG_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE2_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_TOG_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_TOG_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_TOG_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_TOG_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY2_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY2_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_TOG_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY1_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY1_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_TOG_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_TOG_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY0_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY0_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK) + +/*! @name WFE_B_CTRL - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_ENABLE_MASK) +#define PXP_WFE_B_CTRL_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_DONE_SHIFT)) & PXP_WFE_B_CTRL_DONE_MASK) + +/*! @name WFE_B_CTRL_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_SET_ENABLE_MASK) +#define PXP_WFE_B_CTRL_SET_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SET_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_SET_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_SET_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_DONE_SHIFT)) & PXP_WFE_B_CTRL_SET_DONE_MASK) + +/*! @name WFE_B_CTRL_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_CLR_ENABLE_MASK) +#define PXP_WFE_B_CTRL_CLR_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_CLR_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_CLR_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_CLR_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_DONE_SHIFT)) & PXP_WFE_B_CTRL_CLR_DONE_MASK) + +/*! @name WFE_B_CTRL_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_TOG_ENABLE_MASK) +#define PXP_WFE_B_CTRL_TOG_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_TOG_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_TOG_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_TOG_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_TOG_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_DONE_SHIFT)) & PXP_WFE_B_CTRL_TOG_DONE_MASK) + +/*! @name WFE_B_DIMENSIONS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_DIMENSIONS_WIDTH_MASK (0xFFFU) +#define PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT (0U) +#define PXP_WFE_B_DIMENSIONS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT)) & PXP_WFE_B_DIMENSIONS_WIDTH_MASK) +#define PXP_WFE_B_DIMENSIONS_HEIGHT_MASK (0xFFF0000U) +#define PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_DIMENSIONS_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT)) & PXP_WFE_B_DIMENSIONS_HEIGHT_MASK) + +/*! @name WFE_B_OFFSET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_OFFSET_X_OFFSET_MASK (0xFFFU) +#define PXP_WFE_B_OFFSET_X_OFFSET_SHIFT (0U) +#define PXP_WFE_B_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_X_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_X_OFFSET_MASK) +#define PXP_WFE_B_OFFSET_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT (16U) +#define PXP_WFE_B_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_Y_OFFSET_MASK) + +/*! @name WFE_B_SW_DATA_REGS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_SW_DATA_REGS_VAL0_MASK (0xFFU) +#define PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT (0U) +#define PXP_WFE_B_SW_DATA_REGS_VAL0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL0_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL1_MASK (0xFF00U) +#define PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT (8U) +#define PXP_WFE_B_SW_DATA_REGS_VAL1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL1_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL2_MASK (0xFF0000U) +#define PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT (16U) +#define PXP_WFE_B_SW_DATA_REGS_VAL2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL2_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL3_MASK (0xFF000000U) +#define PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT (24U) +#define PXP_WFE_B_SW_DATA_REGS_VAL3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL3_MASK) + +/*! @name WFE_B_SW_FLAG_REGS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK (0x1U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT (0U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK (0x2U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT (1U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK (0x4U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT (2U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK (0x8U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT (3U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK) + +/*! @name WFE_B_STAGE1_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK) + +/*! @name WFE_B_STAGE2_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX9 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX10 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX11 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX12 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK) + +/*! @name WFE_B_STAGE3_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX9 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX10 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK) + +/*! @name WFE_B_STAGE1_5X8_MASKS_0 - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x8 LUT. */ +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK) + +/*! @name WFE_B_STG1_5X1_OUT0 - This register defines the output values (new flag) for the 5x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_5X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */ +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK) + +/*! @name WFE_B_STAGE2_5X6_MASKS_0 - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT. */ +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK (0x1F0000U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK (0x1F000000U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK) + +/*! @name WFE_B_STAGE2_5X6_ADDR_0 - Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT. */ +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK) + +/*! @name WFE_B_STG2_5X1_OUT0 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT1 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT2 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT3 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */ +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK (0x1F0000U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK (0x1F000000U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 8x1 LUT. */ +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK (0xFFU) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK (0xFF00U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK (0xFF0000U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK (0xFF000000U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK) + +/*! @name ALU_B_CTRL - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_ENABLE_MASK) +#define PXP_ALU_B_CTRL_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_START_SHIFT)) & PXP_ALU_B_CTRL_START_MASK) +#define PXP_ALU_B_CTRL_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_BYPASS_MASK) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_SHIFT)) & PXP_ALU_B_CTRL_DONE_MASK) + +/*! @name ALU_B_CTRL_SET - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_SET_ENABLE_MASK) +#define PXP_ALU_B_CTRL_SET_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_SET_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_SET_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_START_SHIFT)) & PXP_ALU_B_CTRL_SET_START_MASK) +#define PXP_ALU_B_CTRL_SET_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SET_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_SET_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_SET_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_SET_BYPASS_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_SET_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_MASK) + +/*! @name ALU_B_CTRL_CLR - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_CLR_ENABLE_MASK) +#define PXP_ALU_B_CTRL_CLR_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_CLR_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_START_SHIFT)) & PXP_ALU_B_CTRL_CLR_START_MASK) +#define PXP_ALU_B_CTRL_CLR_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_CLR_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_CLR_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_CLR_BYPASS_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_CLR_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_MASK) + +/*! @name ALU_B_CTRL_TOG - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_TOG_ENABLE_MASK) +#define PXP_ALU_B_CTRL_TOG_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_TOG_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_START_SHIFT)) & PXP_ALU_B_CTRL_TOG_START_MASK) +#define PXP_ALU_B_CTRL_TOG_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_TOG_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_TOG_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_TOG_BYPASS_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_TOG_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_TOG_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_MASK) + +/*! @name ALU_B_BUF_SIZE - This register defines the size of the buffer to be processed by the alu engine. */ +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK (0xFFFU) +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK (0xFFF0000U) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK) + +/*! @name ALU_B_INST_ENTRY - This register defines the Entry Address for the Instruction Memory of the ALU. */ +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK (0xFFFFU) +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT (0U) +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT)) & PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK) + +/*! @name ALU_B_PARAM - This register defines the parameter used by SW running on ALU. */ +#define PXP_ALU_B_PARAM_PARAM0_MASK (0xFFU) +#define PXP_ALU_B_PARAM_PARAM0_SHIFT (0U) +#define PXP_ALU_B_PARAM_PARAM0(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM0_SHIFT)) & PXP_ALU_B_PARAM_PARAM0_MASK) +#define PXP_ALU_B_PARAM_PARAM1_MASK (0xFF00U) +#define PXP_ALU_B_PARAM_PARAM1_SHIFT (8U) +#define PXP_ALU_B_PARAM_PARAM1(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM1_SHIFT)) & PXP_ALU_B_PARAM_PARAM1_MASK) + +/*! @name ALU_B_CONFIG - This register defines the hw configuration options for the alu core. */ +#define PXP_ALU_B_CONFIG_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT (0U) +#define PXP_ALU_B_CONFIG_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT)) & PXP_ALU_B_CONFIG_BUF_ADDR_MASK) + +/*! @name ALU_B_LUT_CONFIG - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_SET - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_SET_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_CLR - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_TOG - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_TOG_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK) + +/*! @name ALU_B_LUT_DATA0 - This register defines the lower 32-bit data for the LUT */ +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT (0U) +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT)) & PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK) + +/*! @name ALU_B_LUT_DATA1 - This register defines the higher 32-bit data for the LUT */ +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT (0U) +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT)) & PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK) + +/*! @name ALU_B_DBG - This register is used for debugging alu block */ +#define PXP_ALU_B_DBG_DEBUG_VALUE_MASK (0xFFFFFFU) +#define PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT (0U) +#define PXP_ALU_B_DBG_DEBUG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT)) & PXP_ALU_B_DBG_DEBUG_VALUE_MASK) +#define PXP_ALU_B_DBG_DEBUG_SEL_MASK (0xFF000000U) +#define PXP_ALU_B_DBG_DEBUG_SEL_SHIFT (24U) +#define PXP_ALU_B_DBG_DEBUG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_SEL_SHIFT)) & PXP_ALU_B_DBG_DEBUG_SEL_MASK) + +/*! @name HIST_A_CTRL - Histogram Control Register. */ +#define PXP_HIST_A_CTRL_ENABLE_MASK (0x1U) +#define PXP_HIST_A_CTRL_ENABLE_SHIFT (0U) +#define PXP_HIST_A_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_ENABLE_SHIFT)) & PXP_HIST_A_CTRL_ENABLE_MASK) +#define PXP_HIST_A_CTRL_CLEAR_MASK (0x10U) +#define PXP_HIST_A_CTRL_CLEAR_SHIFT (4U) +#define PXP_HIST_A_CTRL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_CLEAR_SHIFT)) & PXP_HIST_A_CTRL_CLEAR_MASK) +#define PXP_HIST_A_CTRL_STATUS_MASK (0x1F00U) +#define PXP_HIST_A_CTRL_STATUS_SHIFT (8U) +#define PXP_HIST_A_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_STATUS_SHIFT)) & PXP_HIST_A_CTRL_STATUS_MASK) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK (0x7F0000U) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT (16U) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK (0x7000000U) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT (24U) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK) + +/*! @name HIST_A_MASK - Histogram Pixel Mask Register. */ +#define PXP_HIST_A_MASK_MASK_EN_MASK (0x1U) +#define PXP_HIST_A_MASK_MASK_EN_SHIFT (0U) +#define PXP_HIST_A_MASK_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_EN_SHIFT)) & PXP_HIST_A_MASK_MASK_EN_MASK) +#define PXP_HIST_A_MASK_MASK_MODE_MASK (0x30U) +#define PXP_HIST_A_MASK_MASK_MODE_SHIFT (4U) +#define PXP_HIST_A_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_MODE_SHIFT)) & PXP_HIST_A_MASK_MASK_MODE_MASK) +#define PXP_HIST_A_MASK_MASK_OFFSET_MASK (0x1FC0U) +#define PXP_HIST_A_MASK_MASK_OFFSET_SHIFT (6U) +#define PXP_HIST_A_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_A_MASK_MASK_OFFSET_MASK) +#define PXP_HIST_A_MASK_MASK_WIDTH_MASK (0xE000U) +#define PXP_HIST_A_MASK_MASK_WIDTH_SHIFT (13U) +#define PXP_HIST_A_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_A_MASK_MASK_WIDTH_MASK) +#define PXP_HIST_A_MASK_MASK_VALUE0_MASK (0xFF0000U) +#define PXP_HIST_A_MASK_MASK_VALUE0_SHIFT (16U) +#define PXP_HIST_A_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE0_MASK) +#define PXP_HIST_A_MASK_MASK_VALUE1_MASK (0xFF000000U) +#define PXP_HIST_A_MASK_MASK_VALUE1_SHIFT (24U) +#define PXP_HIST_A_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE1_MASK) + +/*! @name HIST_A_BUF_SIZE - Histogram Pixel Buffer Size Register. */ +#define PXP_HIST_A_BUF_SIZE_WIDTH_MASK (0xFFFU) +#define PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT (0U) +#define PXP_HIST_A_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_A_BUF_SIZE_WIDTH_MASK) +#define PXP_HIST_A_BUF_SIZE_HEIGHT_MASK (0xFFF0000U) +#define PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT (16U) +#define PXP_HIST_A_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_A_BUF_SIZE_HEIGHT_MASK) + +/*! @name HIST_A_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */ +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK (0xFFFFFFU) +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U) +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK) + +/*! @name HIST_A_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */ +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0xFFFU) +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U) +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) + +/*! @name HIST_A_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */ +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0xFFFU) +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) + +/*! @name HIST_A_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_A_RAW_STAT0_STAT0_MASK (0xFFFFFFFFU) +#define PXP_HIST_A_RAW_STAT0_STAT0_SHIFT (0U) +#define PXP_HIST_A_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_A_RAW_STAT0_STAT0_MASK) + +/*! @name HIST_A_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_A_RAW_STAT1_STAT1_MASK (0xFFFFFFFFU) +#define PXP_HIST_A_RAW_STAT1_STAT1_SHIFT (0U) +#define PXP_HIST_A_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_A_RAW_STAT1_STAT1_MASK) + +/*! @name HIST_B_CTRL - Histogram Control Register. */ +#define PXP_HIST_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_HIST_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_HIST_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_ENABLE_SHIFT)) & PXP_HIST_B_CTRL_ENABLE_MASK) +#define PXP_HIST_B_CTRL_CLEAR_MASK (0x10U) +#define PXP_HIST_B_CTRL_CLEAR_SHIFT (4U) +#define PXP_HIST_B_CTRL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_CLEAR_SHIFT)) & PXP_HIST_B_CTRL_CLEAR_MASK) +#define PXP_HIST_B_CTRL_STATUS_MASK (0x1F00U) +#define PXP_HIST_B_CTRL_STATUS_SHIFT (8U) +#define PXP_HIST_B_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_STATUS_SHIFT)) & PXP_HIST_B_CTRL_STATUS_MASK) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK (0x7F0000U) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT (16U) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK (0x7000000U) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT (24U) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK) + +/*! @name HIST_B_MASK - Histogram Pixel Mask Register. */ +#define PXP_HIST_B_MASK_MASK_EN_MASK (0x1U) +#define PXP_HIST_B_MASK_MASK_EN_SHIFT (0U) +#define PXP_HIST_B_MASK_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_EN_SHIFT)) & PXP_HIST_B_MASK_MASK_EN_MASK) +#define PXP_HIST_B_MASK_MASK_MODE_MASK (0x30U) +#define PXP_HIST_B_MASK_MASK_MODE_SHIFT (4U) +#define PXP_HIST_B_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_MODE_SHIFT)) & PXP_HIST_B_MASK_MASK_MODE_MASK) +#define PXP_HIST_B_MASK_MASK_OFFSET_MASK (0x1FC0U) +#define PXP_HIST_B_MASK_MASK_OFFSET_SHIFT (6U) +#define PXP_HIST_B_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_B_MASK_MASK_OFFSET_MASK) +#define PXP_HIST_B_MASK_MASK_WIDTH_MASK (0xE000U) +#define PXP_HIST_B_MASK_MASK_WIDTH_SHIFT (13U) +#define PXP_HIST_B_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_B_MASK_MASK_WIDTH_MASK) +#define PXP_HIST_B_MASK_MASK_VALUE0_MASK (0xFF0000U) +#define PXP_HIST_B_MASK_MASK_VALUE0_SHIFT (16U) +#define PXP_HIST_B_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE0_MASK) +#define PXP_HIST_B_MASK_MASK_VALUE1_MASK (0xFF000000U) +#define PXP_HIST_B_MASK_MASK_VALUE1_SHIFT (24U) +#define PXP_HIST_B_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE1_MASK) + +/*! @name HIST_B_BUF_SIZE - Histogram Pixel Buffer Size Register. */ +#define PXP_HIST_B_BUF_SIZE_WIDTH_MASK (0xFFFU) +#define PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT (0U) +#define PXP_HIST_B_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_B_BUF_SIZE_WIDTH_MASK) +#define PXP_HIST_B_BUF_SIZE_HEIGHT_MASK (0xFFF0000U) +#define PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT (16U) +#define PXP_HIST_B_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_B_BUF_SIZE_HEIGHT_MASK) + +/*! @name HIST_B_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */ +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK (0xFFFFFFU) +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U) +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK) + +/*! @name HIST_B_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */ +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0xFFFU) +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U) +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) + +/*! @name HIST_B_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */ +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0xFFFU) +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) + +/*! @name HIST_B_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_B_RAW_STAT0_STAT0_MASK (0xFFFFFFFFU) +#define PXP_HIST_B_RAW_STAT0_STAT0_SHIFT (0U) +#define PXP_HIST_B_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_B_RAW_STAT0_STAT0_MASK) + +/*! @name HIST_B_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_B_RAW_STAT1_STAT1_MASK (0xFFFFFFFFU) +#define PXP_HIST_B_RAW_STAT1_STAT1_SHIFT (0U) +#define PXP_HIST_B_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_B_RAW_STAT1_STAT1_MASK) + +/*! @name HIST2_PARAM - 2-level Histogram Parameter Register. */ +#define PXP_HIST2_PARAM_VALUE0_MASK (0x3FU) +#define PXP_HIST2_PARAM_VALUE0_SHIFT (0U) +#define PXP_HIST2_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE0_SHIFT)) & PXP_HIST2_PARAM_VALUE0_MASK) +#define PXP_HIST2_PARAM_VALUE1_MASK (0x3F00U) +#define PXP_HIST2_PARAM_VALUE1_SHIFT (8U) +#define PXP_HIST2_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE1_SHIFT)) & PXP_HIST2_PARAM_VALUE1_MASK) + +/*! @name HIST4_PARAM - 4-level Histogram Parameter Register. */ +#define PXP_HIST4_PARAM_VALUE0_MASK (0x3FU) +#define PXP_HIST4_PARAM_VALUE0_SHIFT (0U) +#define PXP_HIST4_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE0_SHIFT)) & PXP_HIST4_PARAM_VALUE0_MASK) +#define PXP_HIST4_PARAM_VALUE1_MASK (0x3F00U) +#define PXP_HIST4_PARAM_VALUE1_SHIFT (8U) +#define PXP_HIST4_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE1_SHIFT)) & PXP_HIST4_PARAM_VALUE1_MASK) +#define PXP_HIST4_PARAM_VALUE2_MASK (0x3F0000U) +#define PXP_HIST4_PARAM_VALUE2_SHIFT (16U) +#define PXP_HIST4_PARAM_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE2_SHIFT)) & PXP_HIST4_PARAM_VALUE2_MASK) +#define PXP_HIST4_PARAM_VALUE3_MASK (0x3F000000U) +#define PXP_HIST4_PARAM_VALUE3_SHIFT (24U) +#define PXP_HIST4_PARAM_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE3_SHIFT)) & PXP_HIST4_PARAM_VALUE3_MASK) + +/*! @name HIST8_PARAM0 - 8-level Histogram Parameter 0 Register. */ +#define PXP_HIST8_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST8_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST8_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE0_SHIFT)) & PXP_HIST8_PARAM0_VALUE0_MASK) +#define PXP_HIST8_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST8_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST8_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE1_SHIFT)) & PXP_HIST8_PARAM0_VALUE1_MASK) +#define PXP_HIST8_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST8_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST8_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE2_SHIFT)) & PXP_HIST8_PARAM0_VALUE2_MASK) +#define PXP_HIST8_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST8_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST8_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE3_SHIFT)) & PXP_HIST8_PARAM0_VALUE3_MASK) + +/*! @name HIST8_PARAM1 - 8-level Histogram Parameter 1 Register. */ +#define PXP_HIST8_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST8_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST8_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE4_SHIFT)) & PXP_HIST8_PARAM1_VALUE4_MASK) +#define PXP_HIST8_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST8_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST8_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE5_SHIFT)) & PXP_HIST8_PARAM1_VALUE5_MASK) +#define PXP_HIST8_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST8_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST8_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE6_SHIFT)) & PXP_HIST8_PARAM1_VALUE6_MASK) +#define PXP_HIST8_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST8_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST8_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE7_SHIFT)) & PXP_HIST8_PARAM1_VALUE7_MASK) + +/*! @name HIST16_PARAM0 - 16-level Histogram Parameter 0 Register. */ +#define PXP_HIST16_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST16_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST16_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE0_SHIFT)) & PXP_HIST16_PARAM0_VALUE0_MASK) +#define PXP_HIST16_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST16_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST16_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE1_SHIFT)) & PXP_HIST16_PARAM0_VALUE1_MASK) +#define PXP_HIST16_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST16_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST16_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE2_SHIFT)) & PXP_HIST16_PARAM0_VALUE2_MASK) +#define PXP_HIST16_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST16_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST16_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE3_SHIFT)) & PXP_HIST16_PARAM0_VALUE3_MASK) + +/*! @name HIST16_PARAM1 - 16-level Histogram Parameter 1 Register. */ +#define PXP_HIST16_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST16_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST16_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE4_SHIFT)) & PXP_HIST16_PARAM1_VALUE4_MASK) +#define PXP_HIST16_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST16_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST16_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE5_SHIFT)) & PXP_HIST16_PARAM1_VALUE5_MASK) +#define PXP_HIST16_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST16_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST16_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE6_SHIFT)) & PXP_HIST16_PARAM1_VALUE6_MASK) +#define PXP_HIST16_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST16_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST16_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE7_SHIFT)) & PXP_HIST16_PARAM1_VALUE7_MASK) + +/*! @name HIST16_PARAM2 - 16-level Histogram Parameter 2 Register. */ +#define PXP_HIST16_PARAM2_VALUE8_MASK (0x3FU) +#define PXP_HIST16_PARAM2_VALUE8_SHIFT (0U) +#define PXP_HIST16_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE8_SHIFT)) & PXP_HIST16_PARAM2_VALUE8_MASK) +#define PXP_HIST16_PARAM2_VALUE9_MASK (0x3F00U) +#define PXP_HIST16_PARAM2_VALUE9_SHIFT (8U) +#define PXP_HIST16_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE9_SHIFT)) & PXP_HIST16_PARAM2_VALUE9_MASK) +#define PXP_HIST16_PARAM2_VALUE10_MASK (0x3F0000U) +#define PXP_HIST16_PARAM2_VALUE10_SHIFT (16U) +#define PXP_HIST16_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE10_SHIFT)) & PXP_HIST16_PARAM2_VALUE10_MASK) +#define PXP_HIST16_PARAM2_VALUE11_MASK (0x3F000000U) +#define PXP_HIST16_PARAM2_VALUE11_SHIFT (24U) +#define PXP_HIST16_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE11_SHIFT)) & PXP_HIST16_PARAM2_VALUE11_MASK) + +/*! @name HIST16_PARAM3 - 16-level Histogram Parameter 3 Register. */ +#define PXP_HIST16_PARAM3_VALUE12_MASK (0x3FU) +#define PXP_HIST16_PARAM3_VALUE12_SHIFT (0U) +#define PXP_HIST16_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE12_SHIFT)) & PXP_HIST16_PARAM3_VALUE12_MASK) +#define PXP_HIST16_PARAM3_VALUE13_MASK (0x3F00U) +#define PXP_HIST16_PARAM3_VALUE13_SHIFT (8U) +#define PXP_HIST16_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE13_SHIFT)) & PXP_HIST16_PARAM3_VALUE13_MASK) +#define PXP_HIST16_PARAM3_VALUE14_MASK (0x3F0000U) +#define PXP_HIST16_PARAM3_VALUE14_SHIFT (16U) +#define PXP_HIST16_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE14_SHIFT)) & PXP_HIST16_PARAM3_VALUE14_MASK) +#define PXP_HIST16_PARAM3_VALUE15_MASK (0x3F000000U) +#define PXP_HIST16_PARAM3_VALUE15_SHIFT (24U) +#define PXP_HIST16_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE15_SHIFT)) & PXP_HIST16_PARAM3_VALUE15_MASK) + +/*! @name HIST32_PARAM0 - 32-level Histogram Parameter 0 Register. */ +#define PXP_HIST32_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST32_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST32_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE0_SHIFT)) & PXP_HIST32_PARAM0_VALUE0_MASK) +#define PXP_HIST32_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST32_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST32_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE1_SHIFT)) & PXP_HIST32_PARAM0_VALUE1_MASK) +#define PXP_HIST32_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST32_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST32_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE2_SHIFT)) & PXP_HIST32_PARAM0_VALUE2_MASK) +#define PXP_HIST32_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST32_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST32_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE3_SHIFT)) & PXP_HIST32_PARAM0_VALUE3_MASK) + +/*! @name HIST32_PARAM1 - 32-level Histogram Parameter 1 Register. */ +#define PXP_HIST32_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST32_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST32_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE4_SHIFT)) & PXP_HIST32_PARAM1_VALUE4_MASK) +#define PXP_HIST32_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST32_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST32_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE5_SHIFT)) & PXP_HIST32_PARAM1_VALUE5_MASK) +#define PXP_HIST32_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST32_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST32_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE6_SHIFT)) & PXP_HIST32_PARAM1_VALUE6_MASK) +#define PXP_HIST32_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST32_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST32_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE7_SHIFT)) & PXP_HIST32_PARAM1_VALUE7_MASK) + +/*! @name HIST32_PARAM2 - 32-level Histogram Parameter 2 Register. */ +#define PXP_HIST32_PARAM2_VALUE8_MASK (0x3FU) +#define PXP_HIST32_PARAM2_VALUE8_SHIFT (0U) +#define PXP_HIST32_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE8_SHIFT)) & PXP_HIST32_PARAM2_VALUE8_MASK) +#define PXP_HIST32_PARAM2_VALUE9_MASK (0x3F00U) +#define PXP_HIST32_PARAM2_VALUE9_SHIFT (8U) +#define PXP_HIST32_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE9_SHIFT)) & PXP_HIST32_PARAM2_VALUE9_MASK) +#define PXP_HIST32_PARAM2_VALUE10_MASK (0x3F0000U) +#define PXP_HIST32_PARAM2_VALUE10_SHIFT (16U) +#define PXP_HIST32_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE10_SHIFT)) & PXP_HIST32_PARAM2_VALUE10_MASK) +#define PXP_HIST32_PARAM2_VALUE11_MASK (0x3F000000U) +#define PXP_HIST32_PARAM2_VALUE11_SHIFT (24U) +#define PXP_HIST32_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE11_SHIFT)) & PXP_HIST32_PARAM2_VALUE11_MASK) + +/*! @name HIST32_PARAM3 - 32-level Histogram Parameter 3 Register. */ +#define PXP_HIST32_PARAM3_VALUE12_MASK (0x3FU) +#define PXP_HIST32_PARAM3_VALUE12_SHIFT (0U) +#define PXP_HIST32_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE12_SHIFT)) & PXP_HIST32_PARAM3_VALUE12_MASK) +#define PXP_HIST32_PARAM3_VALUE13_MASK (0x3F00U) +#define PXP_HIST32_PARAM3_VALUE13_SHIFT (8U) +#define PXP_HIST32_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE13_SHIFT)) & PXP_HIST32_PARAM3_VALUE13_MASK) +#define PXP_HIST32_PARAM3_VALUE14_MASK (0x3F0000U) +#define PXP_HIST32_PARAM3_VALUE14_SHIFT (16U) +#define PXP_HIST32_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE14_SHIFT)) & PXP_HIST32_PARAM3_VALUE14_MASK) +#define PXP_HIST32_PARAM3_VALUE15_MASK (0x3F000000U) +#define PXP_HIST32_PARAM3_VALUE15_SHIFT (24U) +#define PXP_HIST32_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE15_SHIFT)) & PXP_HIST32_PARAM3_VALUE15_MASK) + +/*! @name HIST32_PARAM4 - 32-level Histogram Parameter 0 Register. */ +#define PXP_HIST32_PARAM4_VALUE16_MASK (0x3FU) +#define PXP_HIST32_PARAM4_VALUE16_SHIFT (0U) +#define PXP_HIST32_PARAM4_VALUE16(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE16_SHIFT)) & PXP_HIST32_PARAM4_VALUE16_MASK) +#define PXP_HIST32_PARAM4_VALUE17_MASK (0x3F00U) +#define PXP_HIST32_PARAM4_VALUE17_SHIFT (8U) +#define PXP_HIST32_PARAM4_VALUE17(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE17_SHIFT)) & PXP_HIST32_PARAM4_VALUE17_MASK) +#define PXP_HIST32_PARAM4_VALUE18_MASK (0x3F0000U) +#define PXP_HIST32_PARAM4_VALUE18_SHIFT (16U) +#define PXP_HIST32_PARAM4_VALUE18(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE18_SHIFT)) & PXP_HIST32_PARAM4_VALUE18_MASK) +#define PXP_HIST32_PARAM4_VALUE19_MASK (0x3F000000U) +#define PXP_HIST32_PARAM4_VALUE19_SHIFT (24U) +#define PXP_HIST32_PARAM4_VALUE19(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE19_SHIFT)) & PXP_HIST32_PARAM4_VALUE19_MASK) + +/*! @name HIST32_PARAM5 - 32-level Histogram Parameter 1 Register. */ +#define PXP_HIST32_PARAM5_VALUE20_MASK (0x3FU) +#define PXP_HIST32_PARAM5_VALUE20_SHIFT (0U) +#define PXP_HIST32_PARAM5_VALUE20(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE20_SHIFT)) & PXP_HIST32_PARAM5_VALUE20_MASK) +#define PXP_HIST32_PARAM5_VALUE21_MASK (0x3F00U) +#define PXP_HIST32_PARAM5_VALUE21_SHIFT (8U) +#define PXP_HIST32_PARAM5_VALUE21(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE21_SHIFT)) & PXP_HIST32_PARAM5_VALUE21_MASK) +#define PXP_HIST32_PARAM5_VALUE22_MASK (0x3F0000U) +#define PXP_HIST32_PARAM5_VALUE22_SHIFT (16U) +#define PXP_HIST32_PARAM5_VALUE22(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE22_SHIFT)) & PXP_HIST32_PARAM5_VALUE22_MASK) +#define PXP_HIST32_PARAM5_VALUE23_MASK (0x3F000000U) +#define PXP_HIST32_PARAM5_VALUE23_SHIFT (24U) +#define PXP_HIST32_PARAM5_VALUE23(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE23_SHIFT)) & PXP_HIST32_PARAM5_VALUE23_MASK) + +/*! @name HIST32_PARAM6 - 32-level Histogram Parameter 2 Register. */ +#define PXP_HIST32_PARAM6_VALUE24_MASK (0x3FU) +#define PXP_HIST32_PARAM6_VALUE24_SHIFT (0U) +#define PXP_HIST32_PARAM6_VALUE24(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE24_SHIFT)) & PXP_HIST32_PARAM6_VALUE24_MASK) +#define PXP_HIST32_PARAM6_VALUE25_MASK (0x3F00U) +#define PXP_HIST32_PARAM6_VALUE25_SHIFT (8U) +#define PXP_HIST32_PARAM6_VALUE25(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE25_SHIFT)) & PXP_HIST32_PARAM6_VALUE25_MASK) +#define PXP_HIST32_PARAM6_VALUE26_MASK (0x3F0000U) +#define PXP_HIST32_PARAM6_VALUE26_SHIFT (16U) +#define PXP_HIST32_PARAM6_VALUE26(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE26_SHIFT)) & PXP_HIST32_PARAM6_VALUE26_MASK) +#define PXP_HIST32_PARAM6_VALUE27_MASK (0x3F000000U) +#define PXP_HIST32_PARAM6_VALUE27_SHIFT (24U) +#define PXP_HIST32_PARAM6_VALUE27(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE27_SHIFT)) & PXP_HIST32_PARAM6_VALUE27_MASK) + +/*! @name HIST32_PARAM7 - 32-level Histogram Parameter 3 Register. */ +#define PXP_HIST32_PARAM7_VALUE28_MASK (0x3FU) +#define PXP_HIST32_PARAM7_VALUE28_SHIFT (0U) +#define PXP_HIST32_PARAM7_VALUE28(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE28_SHIFT)) & PXP_HIST32_PARAM7_VALUE28_MASK) +#define PXP_HIST32_PARAM7_VALUE29_MASK (0x3F00U) +#define PXP_HIST32_PARAM7_VALUE29_SHIFT (8U) +#define PXP_HIST32_PARAM7_VALUE29(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE29_SHIFT)) & PXP_HIST32_PARAM7_VALUE29_MASK) +#define PXP_HIST32_PARAM7_VALUE30_MASK (0x3F0000U) +#define PXP_HIST32_PARAM7_VALUE30_SHIFT (16U) +#define PXP_HIST32_PARAM7_VALUE30(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE30_SHIFT)) & PXP_HIST32_PARAM7_VALUE30_MASK) +#define PXP_HIST32_PARAM7_VALUE31_MASK (0x3F000000U) +#define PXP_HIST32_PARAM7_VALUE31_SHIFT (24U) +#define PXP_HIST32_PARAM7_VALUE31(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE31_SHIFT)) & PXP_HIST32_PARAM7_VALUE31_MASK) + +/*! @name HANDSHAKE_READY_MUX0 - This register defines the pxp subblock handshake signals ready mux on top level. */ +#define PXP_HANDSHAKE_READY_MUX0_HSK0_MASK (0xFU) +#define PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT (0U) +#define PXP_HANDSHAKE_READY_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK0_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK1_MASK (0xF0U) +#define PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT (4U) +#define PXP_HANDSHAKE_READY_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK1_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK2_MASK (0xF00U) +#define PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT (8U) +#define PXP_HANDSHAKE_READY_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK2_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK3_MASK (0xF000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT (12U) +#define PXP_HANDSHAKE_READY_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK3_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK4_MASK (0xF0000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT (16U) +#define PXP_HANDSHAKE_READY_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK4_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK5_MASK (0xF00000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT (20U) +#define PXP_HANDSHAKE_READY_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK5_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK6_MASK (0xF000000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT (24U) +#define PXP_HANDSHAKE_READY_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK6_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK7_MASK (0xF0000000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT (28U) +#define PXP_HANDSHAKE_READY_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK7_MASK) + +/*! @name HANDSHAKE_READY_MUX1 - This register defines the pxp subblock handshake signals ready mux on top level. */ +#define PXP_HANDSHAKE_READY_MUX1_HSK8_MASK (0xFU) +#define PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT (0U) +#define PXP_HANDSHAKE_READY_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK8_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK9_MASK (0xF0U) +#define PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT (4U) +#define PXP_HANDSHAKE_READY_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK9_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK10_MASK (0xF00U) +#define PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT (8U) +#define PXP_HANDSHAKE_READY_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK10_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK11_MASK (0xF000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT (12U) +#define PXP_HANDSHAKE_READY_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK11_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK12_MASK (0xF0000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT (16U) +#define PXP_HANDSHAKE_READY_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK12_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK13_MASK (0xF00000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT (20U) +#define PXP_HANDSHAKE_READY_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK13_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK14_MASK (0xF000000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT (24U) +#define PXP_HANDSHAKE_READY_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK14_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK15_MASK (0xF0000000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT (28U) +#define PXP_HANDSHAKE_READY_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK15_MASK) + +/*! @name HANDSHAKE_DONE_MUX0 - This register defines the pxp subblock handshake signals done mux on top level. */ +#define PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK (0xFU) +#define PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT (0U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK (0xF0U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT (4U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK (0xF00U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT (8U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK (0xF000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT (12U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK (0xF0000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT (16U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK (0xF00000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT (20U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK (0xF000000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT (24U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK (0xF0000000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT (28U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK) + +/*! @name HANDSHAKE_DONE_MUX1 - This register defines the pxp subblock handshake signals done mux on top level. */ +#define PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK (0xFU) +#define PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT (0U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK (0xF0U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT (4U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK (0xF00U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT (8U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK (0xF000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT (12U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK (0xF0000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT (16U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK (0xF00000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT (20U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK (0xF000000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT (24U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK (0xF0000000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT (28U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK) + + +/*! + * @} + */ /* end of group PXP_Register_Masks */ + + +/* PXP - Peripheral instance base addresses */ +/** Peripheral PXP base address */ +#define PXP_BASE (0x21CC000u) +/** Peripheral PXP base pointer */ +#define PXP ((PXP_Type *)PXP_BASE) +/** Array initializer of PXP peripheral base addresses */ +#define PXP_BASE_ADDRS { PXP_BASE } +/** Array initializer of PXP peripheral base pointers */ +#define PXP_BASE_PTRS { PXP } +/** Interrupt vectors for the PXP peripheral type */ +#define PXP_IRQ0_IRQS { PXP_IRQ0_IRQn } +#define PXP_IRQ1_IRQS { PXP_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PXP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- QuadSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer + * @{ + */ + +/** QuadSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ + __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ + __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ + __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ + __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ + __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ + __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ + __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ + __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ + uint8_t RESERVED_2[196]; + __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ + __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ + __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ + uint8_t RESERVED_4[60]; + __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ + __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ + uint8_t RESERVED_5[4]; + __I uint32_t SR; /**< Status Register, offset: 0x15C */ + __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ + __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ + __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ + __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ + uint8_t RESERVED_6[16]; + __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ + __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ + __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ + __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ + uint8_t RESERVED_7[112]; + __IO uint32_t RBDR[32]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[128]; + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ + __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ + uint8_t RESERVED_9[8]; + __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ +} QuadSPI_Type; + +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define QuadSPI_MCR_SWRSTSD_MASK (0x1U) +#define QuadSPI_MCR_SWRSTSD_SHIFT (0U) +#define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) +#define QuadSPI_MCR_SWRSTHD_MASK (0x2U) +#define QuadSPI_MCR_SWRSTHD_SHIFT (1U) +#define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) +#define QuadSPI_MCR_END_CFG_MASK (0xCU) +#define QuadSPI_MCR_END_CFG_SHIFT (2U) +#define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) +#define QuadSPI_MCR_DQS_EN_MASK (0x40U) +#define QuadSPI_MCR_DQS_EN_SHIFT (6U) +#define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) +#define QuadSPI_MCR_DDR_EN_MASK (0x80U) +#define QuadSPI_MCR_DDR_EN_SHIFT (7U) +#define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) +#define QuadSPI_MCR_CLR_RXF_MASK (0x400U) +#define QuadSPI_MCR_CLR_RXF_SHIFT (10U) +#define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) +#define QuadSPI_MCR_CLR_TXF_MASK (0x800U) +#define QuadSPI_MCR_CLR_TXF_SHIFT (11U) +#define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) +#define QuadSPI_MCR_MDIS_MASK (0x4000U) +#define QuadSPI_MCR_MDIS_SHIFT (14U) +#define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) +#define QuadSPI_MCR_DQS_LOOPBACK_EN_MASK (0x1000000U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT (24U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_EN_MASK) +#define QuadSPI_MCR_DQS_PHASE_EN_MASK (0x40000000U) +#define QuadSPI_MCR_DQS_PHASE_EN_SHIFT (30U) +#define QuadSPI_MCR_DQS_PHASE_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_PHASE_EN_SHIFT)) & QuadSPI_MCR_DQS_PHASE_EN_MASK) + +/*! @name IPCR - IP Configuration Register */ +#define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) +#define QuadSPI_IPCR_IDATSZ_SHIFT (0U) +#define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) +#define QuadSPI_IPCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_IPCR_PAR_EN_SHIFT (16U) +#define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK) +#define QuadSPI_IPCR_SEQID_MASK (0xF000000U) +#define QuadSPI_IPCR_SEQID_SHIFT (24U) +#define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) + +/*! @name FLSHCR - Flash Configuration Register */ +#define QuadSPI_FLSHCR_TCSS_MASK (0xFU) +#define QuadSPI_FLSHCR_TCSS_SHIFT (0U) +#define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) +#define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) +#define QuadSPI_FLSHCR_TCSH_SHIFT (8U) +#define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) + +/*! @name BUF0CR - Buffer0 Configuration Register */ +#define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) +#define QuadSPI_BUF0CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) +#define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) +#define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) +#define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) + +/*! @name BUF1CR - Buffer1 Configuration Register */ +#define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) +#define QuadSPI_BUF1CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) + +/*! @name BUF2CR - Buffer2 Configuration Register */ +#define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) +#define QuadSPI_BUF2CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) + +/*! @name BUF3CR - Buffer3 Configuration Register */ +#define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) +#define QuadSPI_BUF3CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) +#define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) +#define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) +#define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) + +/*! @name BFGENCR - Buffer Generic Configuration Register */ +#define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) +#define QuadSPI_BFGENCR_SEQID_SHIFT (12U) +#define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) +#define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U) +#define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK) + +/*! @name BUF0IND - Buffer0 Top Index Register */ +#define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) +#define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) + +/*! @name BUF1IND - Buffer1 Top Index Register */ +#define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) +#define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) + +/*! @name BUF2IND - Buffer2 Top Index Register */ +#define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) +#define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) + +/*! @name SFAR - Serial Flash Address Register */ +#define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) +#define QuadSPI_SFAR_SFADR_SHIFT (0U) +#define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) + +/*! @name SMPR - Sampling Register */ +#define QuadSPI_SMPR_SDRSMP_MASK (0x60U) +#define QuadSPI_SMPR_SDRSMP_SHIFT (5U) +#define QuadSPI_SMPR_SDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_SDRSMP_SHIFT)) & QuadSPI_SMPR_SDRSMP_MASK) +#define QuadSPI_SMPR_DDRSMP_MASK (0x70000U) +#define QuadSPI_SMPR_DDRSMP_SHIFT (16U) +#define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK) + +/*! @name RBSR - RX Buffer Status Register */ +#define QuadSPI_RBSR_RDBFL_MASK (0x3F00U) +#define QuadSPI_RBSR_RDBFL_SHIFT (8U) +#define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) +#define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) +#define QuadSPI_RBSR_RDCTR_SHIFT (16U) +#define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) + +/*! @name RBCT - RX Buffer Control Register */ +#define QuadSPI_RBCT_WMRK_MASK (0x1FU) +#define QuadSPI_RBCT_WMRK_SHIFT (0U) +#define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) +#define QuadSPI_RBCT_RXBRD_MASK (0x100U) +#define QuadSPI_RBCT_RXBRD_SHIFT (8U) +#define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) + +/*! @name TBSR - TX Buffer Status Register */ +#define QuadSPI_TBSR_TRBFL_MASK (0x1F00U) +#define QuadSPI_TBSR_TRBFL_SHIFT (8U) +#define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) +#define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) +#define QuadSPI_TBSR_TRCTR_SHIFT (16U) +#define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) + +/*! @name TBDR - TX Buffer Data Register */ +#define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_TBDR_TXDATA_SHIFT (0U) +#define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) + +/*! @name SR - Status Register */ +#define QuadSPI_SR_BUSY_MASK (0x1U) +#define QuadSPI_SR_BUSY_SHIFT (0U) +#define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) +#define QuadSPI_SR_IP_ACC_MASK (0x2U) +#define QuadSPI_SR_IP_ACC_SHIFT (1U) +#define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) +#define QuadSPI_SR_AHB_ACC_MASK (0x4U) +#define QuadSPI_SR_AHB_ACC_SHIFT (2U) +#define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) +#define QuadSPI_SR_AHBGNT_MASK (0x20U) +#define QuadSPI_SR_AHBGNT_SHIFT (5U) +#define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK) +#define QuadSPI_SR_AHBTRN_MASK (0x40U) +#define QuadSPI_SR_AHBTRN_SHIFT (6U) +#define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) +#define QuadSPI_SR_AHB0NE_MASK (0x80U) +#define QuadSPI_SR_AHB0NE_SHIFT (7U) +#define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) +#define QuadSPI_SR_AHB1NE_MASK (0x100U) +#define QuadSPI_SR_AHB1NE_SHIFT (8U) +#define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) +#define QuadSPI_SR_AHB2NE_MASK (0x200U) +#define QuadSPI_SR_AHB2NE_SHIFT (9U) +#define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) +#define QuadSPI_SR_AHB3NE_MASK (0x400U) +#define QuadSPI_SR_AHB3NE_SHIFT (10U) +#define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) +#define QuadSPI_SR_AHB0FUL_MASK (0x800U) +#define QuadSPI_SR_AHB0FUL_SHIFT (11U) +#define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) +#define QuadSPI_SR_AHB1FUL_MASK (0x1000U) +#define QuadSPI_SR_AHB1FUL_SHIFT (12U) +#define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) +#define QuadSPI_SR_AHB2FUL_MASK (0x2000U) +#define QuadSPI_SR_AHB2FUL_SHIFT (13U) +#define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) +#define QuadSPI_SR_AHB3FUL_MASK (0x4000U) +#define QuadSPI_SR_AHB3FUL_SHIFT (14U) +#define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) +#define QuadSPI_SR_RXWE_MASK (0x10000U) +#define QuadSPI_SR_RXWE_SHIFT (16U) +#define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) +#define QuadSPI_SR_RXFULL_MASK (0x80000U) +#define QuadSPI_SR_RXFULL_SHIFT (19U) +#define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) +#define QuadSPI_SR_RXDMA_MASK (0x800000U) +#define QuadSPI_SR_RXDMA_SHIFT (23U) +#define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) +#define QuadSPI_SR_TXEDA_MASK (0x1000000U) +#define QuadSPI_SR_TXEDA_SHIFT (24U) +#define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) +#define QuadSPI_SR_TXFULL_MASK (0x8000000U) +#define QuadSPI_SR_TXFULL_SHIFT (27U) +#define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) +#define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) +#define QuadSPI_SR_DLPSMP_SHIFT (29U) +#define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK) + +/*! @name FR - Flag Register */ +#define QuadSPI_FR_TFF_MASK (0x1U) +#define QuadSPI_FR_TFF_SHIFT (0U) +#define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) +#define QuadSPI_FR_IPGEF_MASK (0x10U) +#define QuadSPI_FR_IPGEF_SHIFT (4U) +#define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK) +#define QuadSPI_FR_IPIEF_MASK (0x40U) +#define QuadSPI_FR_IPIEF_SHIFT (6U) +#define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) +#define QuadSPI_FR_IPAEF_MASK (0x80U) +#define QuadSPI_FR_IPAEF_SHIFT (7U) +#define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) +#define QuadSPI_FR_IUEF_MASK (0x800U) +#define QuadSPI_FR_IUEF_SHIFT (11U) +#define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK) +#define QuadSPI_FR_ABOF_MASK (0x1000U) +#define QuadSPI_FR_ABOF_SHIFT (12U) +#define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) +#define QuadSPI_FR_ABSEF_MASK (0x8000U) +#define QuadSPI_FR_ABSEF_SHIFT (15U) +#define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) +#define QuadSPI_FR_RBDF_MASK (0x10000U) +#define QuadSPI_FR_RBDF_SHIFT (16U) +#define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) +#define QuadSPI_FR_RBOF_MASK (0x20000U) +#define QuadSPI_FR_RBOF_SHIFT (17U) +#define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) +#define QuadSPI_FR_ILLINE_MASK (0x800000U) +#define QuadSPI_FR_ILLINE_SHIFT (23U) +#define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) +#define QuadSPI_FR_TBUF_MASK (0x4000000U) +#define QuadSPI_FR_TBUF_SHIFT (26U) +#define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) +#define QuadSPI_FR_TBFF_MASK (0x8000000U) +#define QuadSPI_FR_TBFF_SHIFT (27U) +#define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) +#define QuadSPI_FR_DLPFF_MASK (0x80000000U) +#define QuadSPI_FR_DLPFF_SHIFT (31U) +#define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK) + +/*! @name RSER - Interrupt and DMA Request Select and Enable Register */ +#define QuadSPI_RSER_TFIE_MASK (0x1U) +#define QuadSPI_RSER_TFIE_SHIFT (0U) +#define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) +#define QuadSPI_RSER_IPGEIE_MASK (0x10U) +#define QuadSPI_RSER_IPGEIE_SHIFT (4U) +#define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK) +#define QuadSPI_RSER_IPIEIE_MASK (0x40U) +#define QuadSPI_RSER_IPIEIE_SHIFT (6U) +#define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) +#define QuadSPI_RSER_IPAEIE_MASK (0x80U) +#define QuadSPI_RSER_IPAEIE_SHIFT (7U) +#define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) +#define QuadSPI_RSER_IUEIE_MASK (0x800U) +#define QuadSPI_RSER_IUEIE_SHIFT (11U) +#define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK) +#define QuadSPI_RSER_ABOIE_MASK (0x1000U) +#define QuadSPI_RSER_ABOIE_SHIFT (12U) +#define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) +#define QuadSPI_RSER_ABSEIE_MASK (0x8000U) +#define QuadSPI_RSER_ABSEIE_SHIFT (15U) +#define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) +#define QuadSPI_RSER_RBDIE_MASK (0x10000U) +#define QuadSPI_RSER_RBDIE_SHIFT (16U) +#define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) +#define QuadSPI_RSER_RBOIE_MASK (0x20000U) +#define QuadSPI_RSER_RBOIE_SHIFT (17U) +#define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) +#define QuadSPI_RSER_RBDDE_MASK (0x200000U) +#define QuadSPI_RSER_RBDDE_SHIFT (21U) +#define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) +#define QuadSPI_RSER_ILLINIE_MASK (0x800000U) +#define QuadSPI_RSER_ILLINIE_SHIFT (23U) +#define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) +#define QuadSPI_RSER_TBUIE_MASK (0x4000000U) +#define QuadSPI_RSER_TBUIE_SHIFT (26U) +#define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) +#define QuadSPI_RSER_TBFIE_MASK (0x8000000U) +#define QuadSPI_RSER_TBFIE_SHIFT (27U) +#define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) +#define QuadSPI_RSER_DLPFIE_MASK (0x80000000U) +#define QuadSPI_RSER_DLPFIE_SHIFT (31U) +#define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK) + +/*! @name SPNDST - Sequence Suspend Status Register */ +#define QuadSPI_SPNDST_SUSPND_MASK (0x1U) +#define QuadSPI_SPNDST_SUSPND_SHIFT (0U) +#define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) +#define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) +#define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) +#define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) +#define QuadSPI_SPNDST_DATLFT_MASK (0xFE00U) +#define QuadSPI_SPNDST_DATLFT_SHIFT (9U) +#define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) + +/*! @name SPTRCLR - Sequence Pointer Clear Register */ +#define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) +#define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) +#define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) +#define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) +#define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) +#define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) + +/*! @name SFA1AD - Serial Flash A1 Top Address */ +#define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) +#define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) +#define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) + +/*! @name SFA2AD - Serial Flash A2 Top Address */ +#define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) +#define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) +#define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) + +/*! @name SFB1AD - Serial Flash B1Top Address */ +#define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) +#define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) +#define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) + +/*! @name SFB2AD - Serial Flash B2Top Address */ +#define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) +#define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) +#define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) + +/*! @name RBDR - RX Buffer Data Register */ +#define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_RBDR_RXDATA_SHIFT (0U) +#define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) + +/* The count of QuadSPI_RBDR */ +#define QuadSPI_RBDR_COUNT (32U) + +/*! @name LUTKEY - LUT Key Register */ +#define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define QuadSPI_LUTKEY_KEY_SHIFT (0U) +#define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) + +/*! @name LCKCR - LUT Lock Configuration Register */ +#define QuadSPI_LCKCR_LOCK_MASK (0x1U) +#define QuadSPI_LCKCR_LOCK_SHIFT (0U) +#define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) +#define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) +#define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) +#define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) + +/*! @name LUT - Look-up Table register */ +#define QuadSPI_LUT_OPRND0_MASK (0xFFU) +#define QuadSPI_LUT_OPRND0_SHIFT (0U) +#define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) +#define QuadSPI_LUT_PAD0_MASK (0x300U) +#define QuadSPI_LUT_PAD0_SHIFT (8U) +#define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) +#define QuadSPI_LUT_INSTR0_MASK (0xFC00U) +#define QuadSPI_LUT_INSTR0_SHIFT (10U) +#define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) +#define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) +#define QuadSPI_LUT_OPRND1_SHIFT (16U) +#define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) +#define QuadSPI_LUT_PAD1_MASK (0x3000000U) +#define QuadSPI_LUT_PAD1_SHIFT (24U) +#define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) +#define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) +#define QuadSPI_LUT_INSTR1_SHIFT (26U) +#define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) + +/* The count of QuadSPI_LUT */ +#define QuadSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group QuadSPI_Register_Masks */ + + +/* QuadSPI - Peripheral instance base addresses */ +/** Peripheral QuadSPI base address */ +#define QuadSPI_BASE (0x21E0000u) +/** Peripheral QuadSPI base pointer */ +#define QuadSPI ((QuadSPI_Type *)QuadSPI_BASE) +/** Array initializer of QuadSPI peripheral base addresses */ +#define QuadSPI_BASE_ADDRS { QuadSPI_BASE } +/** Array initializer of QuadSPI peripheral base pointers */ +#define QuadSPI_BASE_PTRS { QuadSPI } +/** Interrupt vectors for the QuadSPI peripheral type */ +#define QuadSPI_IRQS { QSPI_IRQn } + +/*! + * @} + */ /* end of group QuadSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t VER; /**< RNGB version ID register, offset: 0x0 */ + __IO uint32_t CMD; /**< RNGB command register, offset: 0x4 */ + __IO uint32_t CR; /**< RNGB control register, offset: 0x8 */ + __I uint32_t SR; /**< RNGB status register, offset: 0xC */ + __I uint32_t ESR; /**< RNGB error status register, offset: 0x10 */ + __I uint32_t OUT; /**< RNGB Output FIFO, offset: 0x14 */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name VER - RNGB version ID register */ +#define RNG_VER_MINOR_MASK (0xFFU) +#define RNG_VER_MINOR_SHIFT (0U) +#define RNG_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_MINOR_SHIFT)) & RNG_VER_MINOR_MASK) +#define RNG_VER_MAJOR_MASK (0xFF00U) +#define RNG_VER_MAJOR_SHIFT (8U) +#define RNG_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_MAJOR_SHIFT)) & RNG_VER_MAJOR_MASK) +#define RNG_VER_TYPE_MASK (0xF0000000U) +#define RNG_VER_TYPE_SHIFT (28U) +#define RNG_VER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_TYPE_SHIFT)) & RNG_VER_TYPE_MASK) + +/*! @name CMD - RNGB command register */ +#define RNG_CMD_ST_MASK (0x1U) +#define RNG_CMD_ST_SHIFT (0U) +#define RNG_CMD_ST(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_ST_SHIFT)) & RNG_CMD_ST_MASK) +#define RNG_CMD_GS_MASK (0x2U) +#define RNG_CMD_GS_SHIFT (1U) +#define RNG_CMD_GS(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_GS_SHIFT)) & RNG_CMD_GS_MASK) +#define RNG_CMD_CI_MASK (0x10U) +#define RNG_CMD_CI_SHIFT (4U) +#define RNG_CMD_CI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_CI_SHIFT)) & RNG_CMD_CI_MASK) +#define RNG_CMD_CE_MASK (0x20U) +#define RNG_CMD_CE_SHIFT (5U) +#define RNG_CMD_CE(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_CE_SHIFT)) & RNG_CMD_CE_MASK) +#define RNG_CMD_SR_MASK (0x40U) +#define RNG_CMD_SR_SHIFT (6U) +#define RNG_CMD_SR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_SR_SHIFT)) & RNG_CMD_SR_MASK) + +/*! @name CR - RNGB control register */ +#define RNG_CR_FUFMOD_MASK (0x3U) +#define RNG_CR_FUFMOD_SHIFT (0U) +#define RNG_CR_FUFMOD(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_FUFMOD_SHIFT)) & RNG_CR_FUFMOD_MASK) +#define RNG_CR_AR_MASK (0x10U) +#define RNG_CR_AR_SHIFT (4U) +#define RNG_CR_AR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_AR_SHIFT)) & RNG_CR_AR_MASK) +#define RNG_CR_MASKDONE_MASK (0x20U) +#define RNG_CR_MASKDONE_SHIFT (5U) +#define RNG_CR_MASKDONE(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_MASKDONE_SHIFT)) & RNG_CR_MASKDONE_MASK) +#define RNG_CR_MASKERR_MASK (0x40U) +#define RNG_CR_MASKERR_SHIFT (6U) +#define RNG_CR_MASKERR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_MASKERR_SHIFT)) & RNG_CR_MASKERR_MASK) + +/*! @name SR - RNGB status register */ +#define RNG_SR_BUSY_MASK (0x2U) +#define RNG_SR_BUSY_SHIFT (1U) +#define RNG_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_BUSY_SHIFT)) & RNG_SR_BUSY_MASK) +#define RNG_SR_SLP_MASK (0x4U) +#define RNG_SR_SLP_SHIFT (2U) +#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) +#define RNG_SR_RS_MASK (0x8U) +#define RNG_SR_RS_SHIFT (3U) +#define RNG_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_RS_SHIFT)) & RNG_SR_RS_MASK) +#define RNG_SR_STDN_MASK (0x10U) +#define RNG_SR_STDN_SHIFT (4U) +#define RNG_SR_STDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_STDN_SHIFT)) & RNG_SR_STDN_MASK) +#define RNG_SR_SDN_MASK (0x20U) +#define RNG_SR_SDN_SHIFT (5U) +#define RNG_SR_SDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SDN_SHIFT)) & RNG_SR_SDN_MASK) +#define RNG_SR_NSDN_MASK (0x40U) +#define RNG_SR_NSDN_SHIFT (6U) +#define RNG_SR_NSDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_NSDN_SHIFT)) & RNG_SR_NSDN_MASK) +#define RNG_SR_FIFO_LVL_MASK (0xF00U) +#define RNG_SR_FIFO_LVL_SHIFT (8U) +#define RNG_SR_FIFO_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_FIFO_LVL_SHIFT)) & RNG_SR_FIFO_LVL_MASK) +#define RNG_SR_FIFO_SIZE_MASK (0xF000U) +#define RNG_SR_FIFO_SIZE_SHIFT (12U) +#define RNG_SR_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_FIFO_SIZE_SHIFT)) & RNG_SR_FIFO_SIZE_MASK) +#define RNG_SR_ERR_MASK (0x10000U) +#define RNG_SR_ERR_SHIFT (16U) +#define RNG_SR_ERR(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERR_SHIFT)) & RNG_SR_ERR_MASK) +#define RNG_SR_ST_PF_MASK (0xE00000U) +#define RNG_SR_ST_PF_SHIFT (21U) +#define RNG_SR_ST_PF(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ST_PF_SHIFT)) & RNG_SR_ST_PF_MASK) +#define RNG_SR_STATPF_MASK (0xFF000000U) +#define RNG_SR_STATPF_SHIFT (24U) +#define RNG_SR_STATPF(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_STATPF_SHIFT)) & RNG_SR_STATPF_MASK) + +/*! @name ESR - RNGB error status register */ +#define RNG_ESR_LFE_MASK (0x1U) +#define RNG_ESR_LFE_SHIFT (0U) +#define RNG_ESR_LFE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_LFE_SHIFT)) & RNG_ESR_LFE_MASK) +#define RNG_ESR_OSCE_MASK (0x2U) +#define RNG_ESR_OSCE_SHIFT (1U) +#define RNG_ESR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_OSCE_SHIFT)) & RNG_ESR_OSCE_MASK) +#define RNG_ESR_STE_MASK (0x4U) +#define RNG_ESR_STE_SHIFT (2U) +#define RNG_ESR_STE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_STE_SHIFT)) & RNG_ESR_STE_MASK) +#define RNG_ESR_SATE_MASK (0x8U) +#define RNG_ESR_SATE_SHIFT (3U) +#define RNG_ESR_SATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_SATE_SHIFT)) & RNG_ESR_SATE_MASK) +#define RNG_ESR_FUFE_MASK (0x10U) +#define RNG_ESR_FUFE_SHIFT (4U) +#define RNG_ESR_FUFE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_FUFE_SHIFT)) & RNG_ESR_FUFE_MASK) + +/*! @name OUT - RNGB Output FIFO */ +#define RNG_OUT_RANDOUT_MASK (0xFFFFFFFFU) +#define RNG_OUT_RANDOUT_SHIFT (0U) +#define RNG_OUT_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OUT_RANDOUT_SHIFT)) & RNG_OUT_RANDOUT_MASK) + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +/** Peripheral RNG base address */ +#define RNG_BASE (0x2284000u) +/** Peripheral RNG base pointer */ +#define RNG ((RNG_Type *)RNG_BASE) +/** Array initializer of RNG peripheral base addresses */ +#define RNG_BASE_ADDRS { RNG_BASE } +/** Array initializer of RNG peripheral base pointers */ +#define RNG_BASE_PTRS { RNG } + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + __I uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) + +/*! @name ROMPATCHA - ROMC Address Registers */ +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x21AC000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDMAARM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer + * @{ + */ + +/** SDMAARM - Register Layout Typedef */ +typedef struct { + __IO uint32_t MC0PTR; /**< ARM platform Channel 0 Pointer, offset: 0x0 */ + __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ + __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ + __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */ + __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */ + __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */ + __IO uint32_t HOSTOVR; /**< Channel ARM platform Override, offset: 0x18 */ + __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */ + uint8_t RESERVED_0[4]; + __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ + __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ + __IO uint32_t INTRMASK; /**< Channel ARM platform Interrupt Mask, offset: 0x2C */ + __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */ + __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ + __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */ + __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */ + __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */ + __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */ + __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */ + __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */ + __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */ + __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */ + __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */ + __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */ + uint8_t RESERVED_2[8]; + __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */ + __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */ + uint8_t RESERVED_3[136]; + __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_4[128]; + __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ +} SDMAARM_Type; + +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/*! @name MC0PTR - ARM platform Channel 0 Pointer */ +#define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU) +#define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U) +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK) + +/*! @name INTR - Channel Interrupts */ +#define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU) +#define SDMAARM_INTR_HI_SHIFT (0U) +#define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK) + +/*! @name STOP_STAT - Channel Stop/Channel Status */ +#define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_STOP_STAT_HE_SHIFT (0U) +#define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK) + +/*! @name HSTART - Channel Start */ +#define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_HSTART_HSTART_HE_SHIFT (0U) +#define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK) + +/*! @name EVTOVR - Channel Event Override */ +#define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTOVR_EO_SHIFT (0U) +#define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK) + +/*! @name DSPOVR - Channel BP Override */ +#define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU) +#define SDMAARM_DSPOVR_DO_SHIFT (0U) +#define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK) + +/*! @name HOSTOVR - Channel ARM platform Override */ +#define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU) +#define SDMAARM_HOSTOVR_HO_SHIFT (0U) +#define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK) + +/*! @name EVTPEND - Channel Event Pending */ +#define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTPEND_EP_SHIFT (0U) +#define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK) + +/*! @name RESET - Reset Register */ +#define SDMAARM_RESET_RESET_MASK (0x1U) +#define SDMAARM_RESET_RESET_SHIFT (0U) +#define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK) +#define SDMAARM_RESET_RESCHED_MASK (0x2U) +#define SDMAARM_RESET_RESCHED_SHIFT (1U) +#define SDMAARM_RESET_RESCHED(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK) + +/*! @name EVTERR - DMA Request Error Register */ +#define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERR_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK) + +/*! @name INTRMASK - Channel ARM platform Interrupt Mask */ +#define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU) +#define SDMAARM_INTRMASK_HIMASK_SHIFT (0U) +#define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK) + +/*! @name PSW - Schedule Status */ +#define SDMAARM_PSW_CCR_MASK (0xFU) +#define SDMAARM_PSW_CCR_SHIFT (0U) +#define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK) +#define SDMAARM_PSW_CCP_MASK (0xF0U) +#define SDMAARM_PSW_CCP_SHIFT (4U) +#define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK) +#define SDMAARM_PSW_NCR_MASK (0x1F00U) +#define SDMAARM_PSW_NCR_SHIFT (8U) +#define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK) +#define SDMAARM_PSW_NCP_MASK (0xE000U) +#define SDMAARM_PSW_NCP_SHIFT (13U) +#define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK) + +/*! @name EVTERRDBG - DMA Request Error Register */ +#define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK) + +/*! @name CONFIG - Configuration Register */ +#define SDMAARM_CONFIG_CSM_MASK (0x3U) +#define SDMAARM_CONFIG_CSM_SHIFT (0U) +#define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK) +#define SDMAARM_CONFIG_ACR_MASK (0x10U) +#define SDMAARM_CONFIG_ACR_SHIFT (4U) +#define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK) +#define SDMAARM_CONFIG_RTDOBS_MASK (0x800U) +#define SDMAARM_CONFIG_RTDOBS_SHIFT (11U) +#define SDMAARM_CONFIG_RTDOBS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK) +#define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U) +#define SDMAARM_CONFIG_DSPDMA_SHIFT (12U) +#define SDMAARM_CONFIG_DSPDMA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK) + +/*! @name SDMA_LOCK - SDMA LOCK */ +#define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U) +#define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U) +#define SDMAARM_SDMA_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK) + +/*! @name ONCE_ENB - OnCE Enable */ +#define SDMAARM_ONCE_ENB_ENB_MASK (0x1U) +#define SDMAARM_ONCE_ENB_ENB_SHIFT (0U) +#define SDMAARM_ONCE_ENB_ENB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK) + +/*! @name ONCE_DATA - OnCE Data Register */ +#define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU) +#define SDMAARM_ONCE_DATA_DATA_SHIFT (0U) +#define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK) + +/*! @name ONCE_INSTR - OnCE Instruction Register */ +#define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU) +#define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U) +#define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK) + +/*! @name ONCE_STAT - OnCE Status Register */ +#define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U) +#define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U) +#define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK) +#define SDMAARM_ONCE_STAT_MST_MASK (0x80U) +#define SDMAARM_ONCE_STAT_MST_SHIFT (7U) +#define SDMAARM_ONCE_STAT_MST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK) +#define SDMAARM_ONCE_STAT_SWB_MASK (0x100U) +#define SDMAARM_ONCE_STAT_SWB_SHIFT (8U) +#define SDMAARM_ONCE_STAT_SWB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK) +#define SDMAARM_ONCE_STAT_ODR_MASK (0x200U) +#define SDMAARM_ONCE_STAT_ODR_SHIFT (9U) +#define SDMAARM_ONCE_STAT_ODR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK) +#define SDMAARM_ONCE_STAT_EDR_MASK (0x400U) +#define SDMAARM_ONCE_STAT_EDR_SHIFT (10U) +#define SDMAARM_ONCE_STAT_EDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK) +#define SDMAARM_ONCE_STAT_RCV_MASK (0x800U) +#define SDMAARM_ONCE_STAT_RCV_SHIFT (11U) +#define SDMAARM_ONCE_STAT_RCV(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK) +#define SDMAARM_ONCE_STAT_PST_MASK (0xF000U) +#define SDMAARM_ONCE_STAT_PST_SHIFT (12U) +#define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK) + +/*! @name ONCE_CMD - OnCE Command Register */ +#define SDMAARM_ONCE_CMD_CMD_MASK (0xFU) +#define SDMAARM_ONCE_CMD_CMD_SHIFT (0U) +#define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK) + +/*! @name ILLINSTADDR - Illegal Instruction Trap Address */ +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK) + +/*! @name CHN0ADDR - Channel 0 Boot Address */ +#define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU) +#define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U) +#define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK) +#define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U) +#define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U) +#define SDMAARM_CHN0ADDR_SMSZ(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK) + +/*! @name EVT_MIRROR - DMA Requests */ +#define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU) +#define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U) +#define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK) + +/*! @name EVT_MIRROR2 - DMA Requests 2 */ +#define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU) +#define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U) +#define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK) + +/*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */ +#define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U) +#define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK) +#define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U) +#define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U) +#define SDMAARM_XTRIG_CONF1_CNF0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK) +#define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U) +#define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK) +#define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U) +#define SDMAARM_XTRIG_CONF1_CNF1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK) +#define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U) +#define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK) +#define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U) +#define SDMAARM_XTRIG_CONF1_CNF2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK) +#define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U) +#define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK) +#define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U) +#define SDMAARM_XTRIG_CONF1_CNF3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK) + +/*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */ +#define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U) +#define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK) +#define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U) +#define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U) +#define SDMAARM_XTRIG_CONF2_CNF4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK) +#define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U) +#define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK) +#define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U) +#define SDMAARM_XTRIG_CONF2_CNF5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK) +#define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U) +#define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK) +#define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U) +#define SDMAARM_XTRIG_CONF2_CNF6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK) +#define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U) +#define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK) +#define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U) +#define SDMAARM_XTRIG_CONF2_CNF7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK) + +/*! @name SDMA_CHNPRI - Channel Priority Registers */ +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK) + +/* The count of SDMAARM_SDMA_CHNPRI */ +#define SDMAARM_SDMA_CHNPRI_COUNT (32U) + +/*! @name CHNENBL - Channel Enable RAM */ +#define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU) +#define SDMAARM_CHNENBL_ENBLn_SHIFT (0U) +#define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK) + +/* The count of SDMAARM_CHNENBL */ +#define SDMAARM_CHNENBL_COUNT (48U) + + +/*! + * @} + */ /* end of group SDMAARM_Register_Masks */ + + +/* SDMAARM - Peripheral instance base addresses */ +/** Peripheral SDMAARM base address */ +#define SDMAARM_BASE (0x20EC000u) +/** Peripheral SDMAARM base pointer */ +#define SDMAARM ((SDMAARM_Type *)SDMAARM_BASE) +/** Array initializer of SDMAARM peripheral base addresses */ +#define SDMAARM_BASE_ADDRS { SDMAARM_BASE } +/** Array initializer of SDMAARM peripheral base pointers */ +#define SDMAARM_BASE_PTRS { SDMAARM } +/** Interrupt vectors for the SDMAARM peripheral type */ +#define SDMAARM_IRQS { SDMA_IRQn } + +/*! + * @} + */ /* end of group SDMAARM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control register, offset: 0x8 */ + uint8_t RESERVED_0[8]; + __IO uint32_t HPSR; /**< SNVS_HP Status register, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __IO uint32_t HPRTCMR; /**< SNVS_HP Real-Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real-Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + uint8_t RESERVED_2[16]; + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + uint8_t RESERVED_3[12]; + __IO uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __IO uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + uint8_t RESERVED_4[4]; + __IO uint32_t LPGPR; /**< SNVS_LP General-Purpose Register, offset: 0x68 */ + uint8_t RESERVED_5[2956]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock register */ +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) + +/*! @name HPCOMR - SNVS_HP Command register */ +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) + +/*! @name HPCR - SNVS_HP Control register */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) + +/*! @name HPSR - SNVS_HP Status register */ +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) + +/*! @name HPRTCMR - SNVS_HP Real-Time Counter MSB Register */ +#define SNVS_HPRTCMR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) + +/*! @name HPRTCLR - SNVS_HP Real-Time Counter LSB Register */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +#define SNVS_HPTAMR_HPTA_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_SHIFT (0U) +#define SNVS_HPTAMR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_SHIFT)) & SNVS_HPTAMR_HPTA_MASK) + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +#define SNVS_HPTALR_HPTA_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_SHIFT (0U) +#define SNVS_HPTALR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_SHIFT)) & SNVS_HPTALR_HPTA_MASK) + +/*! @name LPLR - SNVS_LP Lock Register */ +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) + +/*! @name LPCR - SNVS_LP Control Register */ +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) + +/*! @name LPSR - SNVS_LP Status Register */ +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) + +/*! @name LPGPR - SNVS_LP General-Purpose Register */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x20CC000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_Consolidated_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_Security_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPBA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer + * @{ + */ + +/** SPBA - Register Layout Typedef */ +typedef struct { + __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ +} SPBA_Type; + +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/*! @name PRR - Peripheral Rights Register */ +#define SPBA_PRR_RARA_MASK (0x1U) +#define SPBA_PRR_RARA_SHIFT (0U) +#define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK) +#define SPBA_PRR_RARB_MASK (0x2U) +#define SPBA_PRR_RARB_SHIFT (1U) +#define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK) +#define SPBA_PRR_RARC_MASK (0x4U) +#define SPBA_PRR_RARC_SHIFT (2U) +#define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK) +#define SPBA_PRR_ROI_MASK (0x30000U) +#define SPBA_PRR_ROI_SHIFT (16U) +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK) +#define SPBA_PRR_RMO_MASK (0xC0000000U) +#define SPBA_PRR_RMO_SHIFT (30U) +#define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK) + +/* The count of SPBA_PRR */ +#define SPBA_PRR_COUNT (32U) + + +/*! + * @} + */ /* end of group SPBA_Register_Masks */ + + +/* SPBA - Peripheral instance base addresses */ +/** Peripheral SPBA base address */ +#define SPBA_BASE (0x203C000u) +/** Peripheral SPBA base pointer */ +#define SPBA ((SPBA_Type *)SPBA_BASE) +/** Array initializer of SPBA peripheral base addresses */ +#define SPBA_BASE_ADDRS { SPBA_BASE } +/** Array initializer of SPBA peripheral base pointers */ +#define SPBA_BASE_PTRS { SPBA } + +/*! + * @} + */ /* end of group SPBA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __IO uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __IO uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __IO uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) + +/*! @name SRCD - CDText Control Register */ +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) + +/*! @name SRPC - PhaseConfig Register */ +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) + +/*! @name SIE - InterruptEn Register */ +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) + +/*! @name SIC - InterruptClear Register */ +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) + +/*! @name SIS - InterruptStat Register */ +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) + +/*! @name SRL - SPDIFRxLeft Register */ +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) + +/*! @name SRR - SPDIFRxRight Register */ +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) + +/*! @name SRU - UchannelRx Register */ +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) + +/*! @name SRQ - QchannelRx Register */ +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) + +/*! @name STL - SPDIFTxLeft Register */ +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) + +/*! @name STR - SPDIFTxRight Register */ +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) + +/*! @name SRFM - FreqMeas Register */ +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) + +/*! @name STC - SPDIFTxClk Register */ +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x2004000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { SPDIF_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ + uint8_t RESERVED_0[8]; + __I uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Control Register */ +#define SRC_SCR_WARM_RESET_ENABLE_MASK (0x1U) +#define SRC_SCR_WARM_RESET_ENABLE_SHIFT (0U) +#define SRC_SCR_WARM_RESET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WARM_RESET_ENABLE_SHIFT)) & SRC_SCR_WARM_RESET_ENABLE_MASK) +#define SRC_SCR_WARM_RST_BYPASS_COUNT_MASK (0x60U) +#define SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT (5U) +#define SRC_SCR_WARM_RST_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT)) & SRC_SCR_WARM_RST_BYPASS_COUNT_MASK) +#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) +#define SRC_SCR_EIM_RST_MASK (0x800U) +#define SRC_SCR_EIM_RST_SHIFT (11U) +#define SRC_SCR_EIM_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_EIM_RST_SHIFT)) & SRC_SCR_EIM_RST_MASK) +#define SRC_SCR_CORE0_RST_MASK (0x2000U) +#define SRC_SCR_CORE0_RST_SHIFT (13U) +#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) +#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) +#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) +#define SRC_SCR_CORES_DBG_RST_MASK (0x200000U) +#define SRC_SCR_CORES_DBG_RST_SHIFT (21U) +#define SRC_SCR_CORES_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORES_DBG_RST_SHIFT)) & SRC_SCR_CORES_DBG_RST_MASK) +#define SRC_SCR_WDOG3_RST_OPTN_MASK (0x1000000U) +#define SRC_SCR_WDOG3_RST_OPTN_SHIFT (24U) +#define SRC_SCR_WDOG3_RST_OPTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WDOG3_RST_OPTN_SHIFT)) & SRC_SCR_WDOG3_RST_OPTN_MASK) +#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) +#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) +#define SRC_SCR_MIX_RST_STRCH_MASK (0xC000000U) +#define SRC_SCR_MIX_RST_STRCH_SHIFT (26U) +#define SRC_SCR_MIX_RST_STRCH(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MIX_RST_STRCH_SHIFT)) & SRC_SCR_MIX_RST_STRCH_MASK) +#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) +#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) + +/*! @name SRSR - SRC Reset Status Register */ +#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) +#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) +#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +#define SRC_SRSR_WARM_BOOT_MASK (0x10000U) +#define SRC_SRSR_WARM_BOOT_SHIFT (16U) +#define SRC_SRSR_WARM_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WARM_BOOT_SHIFT)) & SRC_SRSR_WARM_BOOT_MASK) + +/*! @name SISR - SRC Interrupt Status Register */ +#define SRC_SISR_CORE0_WDOG_RST_REQ_MASK (0x20U) +#define SRC_SISR_CORE0_WDOG_RST_REQ_SHIFT (5U) +#define SRC_SISR_CORE0_WDOG_RST_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_CORE0_WDOG_RST_REQ_SHIFT)) & SRC_SISR_CORE0_WDOG_RST_REQ_MASK) + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x20D8000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +#define SRC_COMBINED_IRQS { SRC_Combined_IRQn } +/* Backward compatibility */ +#define SRC_SCR_WRE_MASK SRC_SCR_WARM_RESET_ENABLE_MASK +#define SRC_SCR_WRE_SHIFT SRC_SCR_WARM_RESET_ENABLE_SHIFT +#define SRC_SCR_WRE(x) SRC_SCR_WARM_RESET_ENABLE(x) +#define SRC_SCR_WRBC_MASK SRC_SCR_WARM_RST_BYPASS_COUNT_MASK +#define SRC_SCR_WRBC_SHIFT SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT +#define SRC_SCR_WRBC(x) SRC_SCR_WARM_RST_BYPASS_COUNT(x) +#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK +#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT +#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) +#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK +#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT +#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) +#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK +#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT +#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) +#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK +#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT +#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) +#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK +#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT +#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) +#define SRC_SRSR_WBI_MASK SRC_SRSR_WARM_BOOT_MASK +#define SRC_SRSR_WBI_SHIFT SRC_SRSR_WARM_BOOT_SHIFT +#define SRC_SRSR_WBI(x) SRC_SRSR_WARM_BOOT(x) +/* Extra definition */ +#define SRC_SRSR_W1C_BITS_MASK (SRC_SRSR_WDOG3_RST_B_MASK \ + | SRC_SRSR_JTAG_SW_RST_MASK \ + | SRC_SRSR_JTAG_RST_B_MASK \ + | SRC_SRSR_WDOG_RST_B_MASK \ + | SRC_SRSR_IPP_USER_RESET_B_MASK \ + | SRC_SRSR_CSU_RESET_B_MASK \ + | SRC_SRSR_IPP_RESET_B_MASK) + + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x0 */ + __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x4 */ + __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x8 */ + __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0xC */ + __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x10 */ + __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x14 */ + __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x18 */ + __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x1C */ + uint8_t RESERVED_0[240]; + __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x110 */ + __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x114 */ + __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x118 */ + __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x11C */ +} TEMPMON_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) + + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x20C8180u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +/** Array initializer of TEMPMON peripheral base addresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } +/** Interrupt vectors for the TEMPMON peripheral type */ +#define TEMPMON_IRQS { TEMPMON_IRQn } + +/*! + * @} + */ /* end of group TEMPMON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer + * @{ + */ + +/** TSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t BASIC_SETTING; /**< PS Input Buffer Address, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PS_INPUT_BUFFER_ADDR; /**< PS Input Buffer Address, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */ +} TSC_Type; + +/* ---------------------------------------------------------------------------- + -- TSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Register_Masks TSC Register Masks + * @{ + */ + +/*! @name BASIC_SETTING - PS Input Buffer Address */ +#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) +#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) +#define TSC_BASIC_SETTING__4_5_WIRE_MASK (0x10U) +#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT (4U) +#define TSC_BASIC_SETTING__4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING__4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING__4_5_WIRE_MASK) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) + +/*! @name PS_INPUT_BUFFER_ADDR - PS Input Buffer Address */ +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT)) & TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK) + +/*! @name FLOW_CONTROL - Flow Control */ +#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) +#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) +#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) +#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) +#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) +#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) +#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) +#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) +#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) +#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) +#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) + +/*! @name MEASEURE_VALUE - Measure Value */ +#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) +#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) +#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) +#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) +#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) +#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) + +/*! @name INT_EN - Interrupt Enable */ +#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) +#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) +#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) +#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) +#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) +#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) + +/*! @name INT_SIG_EN - Interrupt Signal Enable */ +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) +#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) +#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) + +/*! @name INT_STATUS - Intterrupt Status */ +#define TSC_INT_STATUS_MEASURE_MASK (0x1U) +#define TSC_INT_STATUS_MEASURE_SHIFT (0U) +#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) +#define TSC_INT_STATUS_DETECT_MASK (0x10U) +#define TSC_INT_STATUS_DETECT_SHIFT (4U) +#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) +#define TSC_INT_STATUS_VALID_MASK (0x100U) +#define TSC_INT_STATUS_VALID_SHIFT (8U) +#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) +#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) +#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) + +/*! @name DEBUG_MODE - */ +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U) +#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U) +#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK) +#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U) +#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U) +#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) +#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) +#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) +#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) +#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) + +/*! @name DEBUG_MODE2 - */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) +#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) +#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) +#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) +#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) + + +/*! + * @} + */ /* end of group TSC_Register_Masks */ + + +/* TSC - Peripheral instance base addresses */ +/** Peripheral TSC base address */ +#define TSC_BASE (0x2040000u) +/** Peripheral TSC base pointer */ +#define TSC ((TSC_Type *)TSC_BASE) +/** Array initializer of TSC peripheral base addresses */ +#define TSC_BASE_ADDRS { TSC_BASE } +/** Array initializer of TSC peripheral base pointers */ +#define TSC_BASE_PTRS { TSC } +/** Interrupt vectors for the TSC peripheral type */ +#define TSC_IRQS { TSC_IRQn } + +/*! + * @} + */ /* end of group TSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */ + uint8_t RESERVED_1[60]; + __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */ + __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ + __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */ + __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */ + __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ + __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */ + __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */ + __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */ + __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */ + __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */ + __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */ + __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */ + __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */ + __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ + __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/*! @name URXD - UART Receiver Register */ +#define UART_URXD_RX_DATA_MASK (0xFFU) +#define UART_URXD_RX_DATA_SHIFT (0U) +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK) +#define UART_URXD_PRERR_MASK (0x400U) +#define UART_URXD_PRERR_SHIFT (10U) +#define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK) +#define UART_URXD_BRK_MASK (0x800U) +#define UART_URXD_BRK_SHIFT (11U) +#define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK) +#define UART_URXD_FRMERR_MASK (0x1000U) +#define UART_URXD_FRMERR_SHIFT (12U) +#define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK) +#define UART_URXD_OVRRUN_MASK (0x2000U) +#define UART_URXD_OVRRUN_SHIFT (13U) +#define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK) +#define UART_URXD_ERR_MASK (0x4000U) +#define UART_URXD_ERR_SHIFT (14U) +#define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK) +#define UART_URXD_CHARRDY_MASK (0x8000U) +#define UART_URXD_CHARRDY_SHIFT (15U) +#define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK) + +/*! @name UTXD - UART Transmitter Register */ +#define UART_UTXD_TX_DATA_MASK (0xFFU) +#define UART_UTXD_TX_DATA_SHIFT (0U) +#define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK) + +/*! @name UCR1 - UART Control Register 1 */ +#define UART_UCR1_UARTEN_MASK (0x1U) +#define UART_UCR1_UARTEN_SHIFT (0U) +#define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK) +#define UART_UCR1_DOZE_MASK (0x2U) +#define UART_UCR1_DOZE_SHIFT (1U) +#define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK) +#define UART_UCR1_ATDMAEN_MASK (0x4U) +#define UART_UCR1_ATDMAEN_SHIFT (2U) +#define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK) +#define UART_UCR1_TXDMAEN_MASK (0x8U) +#define UART_UCR1_TXDMAEN_SHIFT (3U) +#define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK) +#define UART_UCR1_SNDBRK_MASK (0x10U) +#define UART_UCR1_SNDBRK_SHIFT (4U) +#define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK) +#define UART_UCR1_RTSDEN_MASK (0x20U) +#define UART_UCR1_RTSDEN_SHIFT (5U) +#define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK) +#define UART_UCR1_TXMPTYEN_MASK (0x40U) +#define UART_UCR1_TXMPTYEN_SHIFT (6U) +#define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK) +#define UART_UCR1_IREN_MASK (0x80U) +#define UART_UCR1_IREN_SHIFT (7U) +#define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK) +#define UART_UCR1_RXDMAEN_MASK (0x100U) +#define UART_UCR1_RXDMAEN_SHIFT (8U) +#define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK) +#define UART_UCR1_RRDYEN_MASK (0x200U) +#define UART_UCR1_RRDYEN_SHIFT (9U) +#define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK) +#define UART_UCR1_ICD_MASK (0xC00U) +#define UART_UCR1_ICD_SHIFT (10U) +#define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK) +#define UART_UCR1_IDEN_MASK (0x1000U) +#define UART_UCR1_IDEN_SHIFT (12U) +#define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK) +#define UART_UCR1_TRDYEN_MASK (0x2000U) +#define UART_UCR1_TRDYEN_SHIFT (13U) +#define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK) +#define UART_UCR1_ADBR_MASK (0x4000U) +#define UART_UCR1_ADBR_SHIFT (14U) +#define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK) +#define UART_UCR1_ADEN_MASK (0x8000U) +#define UART_UCR1_ADEN_SHIFT (15U) +#define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK) + +/*! @name UCR2 - UART Control Register 2 */ +#define UART_UCR2_SRST_MASK (0x1U) +#define UART_UCR2_SRST_SHIFT (0U) +#define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK) +#define UART_UCR2_RXEN_MASK (0x2U) +#define UART_UCR2_RXEN_SHIFT (1U) +#define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK) +#define UART_UCR2_TXEN_MASK (0x4U) +#define UART_UCR2_TXEN_SHIFT (2U) +#define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK) +#define UART_UCR2_ATEN_MASK (0x8U) +#define UART_UCR2_ATEN_SHIFT (3U) +#define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK) +#define UART_UCR2_RTSEN_MASK (0x10U) +#define UART_UCR2_RTSEN_SHIFT (4U) +#define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK) +#define UART_UCR2_WS_MASK (0x20U) +#define UART_UCR2_WS_SHIFT (5U) +#define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK) +#define UART_UCR2_STPB_MASK (0x40U) +#define UART_UCR2_STPB_SHIFT (6U) +#define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK) +#define UART_UCR2_PROE_MASK (0x80U) +#define UART_UCR2_PROE_SHIFT (7U) +#define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK) +#define UART_UCR2_PREN_MASK (0x100U) +#define UART_UCR2_PREN_SHIFT (8U) +#define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK) +#define UART_UCR2_RTEC_MASK (0x600U) +#define UART_UCR2_RTEC_SHIFT (9U) +#define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK) +#define UART_UCR2_ESCEN_MASK (0x800U) +#define UART_UCR2_ESCEN_SHIFT (11U) +#define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK) +#define UART_UCR2_CTS_MASK (0x1000U) +#define UART_UCR2_CTS_SHIFT (12U) +#define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK) +#define UART_UCR2_CTSC_MASK (0x2000U) +#define UART_UCR2_CTSC_SHIFT (13U) +#define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK) +#define UART_UCR2_IRTS_MASK (0x4000U) +#define UART_UCR2_IRTS_SHIFT (14U) +#define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK) +#define UART_UCR2_ESCI_MASK (0x8000U) +#define UART_UCR2_ESCI_SHIFT (15U) +#define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK) + +/*! @name UCR3 - UART Control Register 3 */ +#define UART_UCR3_ACIEN_MASK (0x1U) +#define UART_UCR3_ACIEN_SHIFT (0U) +#define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK) +#define UART_UCR3_INVT_MASK (0x2U) +#define UART_UCR3_INVT_SHIFT (1U) +#define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK) +#define UART_UCR3_RXDMUXSEL_MASK (0x4U) +#define UART_UCR3_RXDMUXSEL_SHIFT (2U) +#define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK) +#define UART_UCR3_DTRDEN_MASK (0x8U) +#define UART_UCR3_DTRDEN_SHIFT (3U) +#define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK) +#define UART_UCR3_AWAKEN_MASK (0x10U) +#define UART_UCR3_AWAKEN_SHIFT (4U) +#define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK) +#define UART_UCR3_AIRINTEN_MASK (0x20U) +#define UART_UCR3_AIRINTEN_SHIFT (5U) +#define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK) +#define UART_UCR3_RXDSEN_MASK (0x40U) +#define UART_UCR3_RXDSEN_SHIFT (6U) +#define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK) +#define UART_UCR3_ADNIMP_MASK (0x80U) +#define UART_UCR3_ADNIMP_SHIFT (7U) +#define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK) +#define UART_UCR3_RI_MASK (0x100U) +#define UART_UCR3_RI_SHIFT (8U) +#define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK) +#define UART_UCR3_DCD_MASK (0x200U) +#define UART_UCR3_DCD_SHIFT (9U) +#define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK) +#define UART_UCR3_DSR_MASK (0x400U) +#define UART_UCR3_DSR_SHIFT (10U) +#define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK) +#define UART_UCR3_FRAERREN_MASK (0x800U) +#define UART_UCR3_FRAERREN_SHIFT (11U) +#define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK) +#define UART_UCR3_PARERREN_MASK (0x1000U) +#define UART_UCR3_PARERREN_SHIFT (12U) +#define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK) +#define UART_UCR3_DTREN_MASK (0x2000U) +#define UART_UCR3_DTREN_SHIFT (13U) +#define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK) +#define UART_UCR3_DPEC_MASK (0xC000U) +#define UART_UCR3_DPEC_SHIFT (14U) +#define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK) + +/*! @name UCR4 - UART Control Register 4 */ +#define UART_UCR4_DREN_MASK (0x1U) +#define UART_UCR4_DREN_SHIFT (0U) +#define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK) +#define UART_UCR4_OREN_MASK (0x2U) +#define UART_UCR4_OREN_SHIFT (1U) +#define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK) +#define UART_UCR4_BKEN_MASK (0x4U) +#define UART_UCR4_BKEN_SHIFT (2U) +#define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK) +#define UART_UCR4_TCEN_MASK (0x8U) +#define UART_UCR4_TCEN_SHIFT (3U) +#define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK) +#define UART_UCR4_LPBYP_MASK (0x10U) +#define UART_UCR4_LPBYP_SHIFT (4U) +#define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK) +#define UART_UCR4_IRSC_MASK (0x20U) +#define UART_UCR4_IRSC_SHIFT (5U) +#define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK) +#define UART_UCR4_IDDMAEN_MASK (0x40U) +#define UART_UCR4_IDDMAEN_SHIFT (6U) +#define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK) +#define UART_UCR4_WKEN_MASK (0x80U) +#define UART_UCR4_WKEN_SHIFT (7U) +#define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK) +#define UART_UCR4_ENIRI_MASK (0x100U) +#define UART_UCR4_ENIRI_SHIFT (8U) +#define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK) +#define UART_UCR4_INVR_MASK (0x200U) +#define UART_UCR4_INVR_SHIFT (9U) +#define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK) +#define UART_UCR4_CTSTL_MASK (0xFC00U) +#define UART_UCR4_CTSTL_SHIFT (10U) +#define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK) + +/*! @name UFCR - UART FIFO Control Register */ +#define UART_UFCR_RXTL_MASK (0x3FU) +#define UART_UFCR_RXTL_SHIFT (0U) +#define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK) +#define UART_UFCR_DCEDTE_MASK (0x40U) +#define UART_UFCR_DCEDTE_SHIFT (6U) +#define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK) +#define UART_UFCR_RFDIV_MASK (0x380U) +#define UART_UFCR_RFDIV_SHIFT (7U) +#define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK) +#define UART_UFCR_TXTL_MASK (0xFC00U) +#define UART_UFCR_TXTL_SHIFT (10U) +#define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK) + +/*! @name USR1 - UART Status Register 1 */ +#define UART_USR1_SAD_MASK (0x8U) +#define UART_USR1_SAD_SHIFT (3U) +#define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK) +#define UART_USR1_AWAKE_MASK (0x10U) +#define UART_USR1_AWAKE_SHIFT (4U) +#define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK) +#define UART_USR1_AIRINT_MASK (0x20U) +#define UART_USR1_AIRINT_SHIFT (5U) +#define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK) +#define UART_USR1_RXDS_MASK (0x40U) +#define UART_USR1_RXDS_SHIFT (6U) +#define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK) +#define UART_USR1_DTRD_MASK (0x80U) +#define UART_USR1_DTRD_SHIFT (7U) +#define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK) +#define UART_USR1_AGTIM_MASK (0x100U) +#define UART_USR1_AGTIM_SHIFT (8U) +#define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK) +#define UART_USR1_RRDY_MASK (0x200U) +#define UART_USR1_RRDY_SHIFT (9U) +#define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK) +#define UART_USR1_FRAMERR_MASK (0x400U) +#define UART_USR1_FRAMERR_SHIFT (10U) +#define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK) +#define UART_USR1_ESCF_MASK (0x800U) +#define UART_USR1_ESCF_SHIFT (11U) +#define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK) +#define UART_USR1_RTSD_MASK (0x1000U) +#define UART_USR1_RTSD_SHIFT (12U) +#define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK) +#define UART_USR1_TRDY_MASK (0x2000U) +#define UART_USR1_TRDY_SHIFT (13U) +#define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK) +#define UART_USR1_RTSS_MASK (0x4000U) +#define UART_USR1_RTSS_SHIFT (14U) +#define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK) +#define UART_USR1_PARITYERR_MASK (0x8000U) +#define UART_USR1_PARITYERR_SHIFT (15U) +#define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK) + +/*! @name USR2 - UART Status Register 2 */ +#define UART_USR2_RDR_MASK (0x1U) +#define UART_USR2_RDR_SHIFT (0U) +#define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK) +#define UART_USR2_ORE_MASK (0x2U) +#define UART_USR2_ORE_SHIFT (1U) +#define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK) +#define UART_USR2_BRCD_MASK (0x4U) +#define UART_USR2_BRCD_SHIFT (2U) +#define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK) +#define UART_USR2_TXDC_MASK (0x8U) +#define UART_USR2_TXDC_SHIFT (3U) +#define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK) +#define UART_USR2_RTSF_MASK (0x10U) +#define UART_USR2_RTSF_SHIFT (4U) +#define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK) +#define UART_USR2_DCDIN_MASK (0x20U) +#define UART_USR2_DCDIN_SHIFT (5U) +#define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK) +#define UART_USR2_DCDDELT_MASK (0x40U) +#define UART_USR2_DCDDELT_SHIFT (6U) +#define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK) +#define UART_USR2_WAKE_MASK (0x80U) +#define UART_USR2_WAKE_SHIFT (7U) +#define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK) +#define UART_USR2_IRINT_MASK (0x100U) +#define UART_USR2_IRINT_SHIFT (8U) +#define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK) +#define UART_USR2_RIIN_MASK (0x200U) +#define UART_USR2_RIIN_SHIFT (9U) +#define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK) +#define UART_USR2_RIDELT_MASK (0x400U) +#define UART_USR2_RIDELT_SHIFT (10U) +#define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK) +#define UART_USR2_ACST_MASK (0x800U) +#define UART_USR2_ACST_SHIFT (11U) +#define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK) +#define UART_USR2_IDLE_MASK (0x1000U) +#define UART_USR2_IDLE_SHIFT (12U) +#define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK) +#define UART_USR2_DTRF_MASK (0x2000U) +#define UART_USR2_DTRF_SHIFT (13U) +#define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK) +#define UART_USR2_TXFE_MASK (0x4000U) +#define UART_USR2_TXFE_SHIFT (14U) +#define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK) +#define UART_USR2_ADET_MASK (0x8000U) +#define UART_USR2_ADET_SHIFT (15U) +#define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK) + +/*! @name UESC - UART Escape Character Register */ +#define UART_UESC_ESC_CHAR_MASK (0xFFU) +#define UART_UESC_ESC_CHAR_SHIFT (0U) +#define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK) + +/*! @name UTIM - UART Escape Timer Register */ +#define UART_UTIM_TIM_MASK (0xFFFU) +#define UART_UTIM_TIM_SHIFT (0U) +#define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK) + +/*! @name UBIR - UART BRM Incremental Register */ +#define UART_UBIR_INC_MASK (0xFFFFU) +#define UART_UBIR_INC_SHIFT (0U) +#define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK) + +/*! @name UBMR - UART BRM Modulator Register */ +#define UART_UBMR_MOD_MASK (0xFFFFU) +#define UART_UBMR_MOD_SHIFT (0U) +#define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK) + +/*! @name UBRC - UART Baud Rate Count Register */ +#define UART_UBRC_BCNT_MASK (0xFFFFU) +#define UART_UBRC_BCNT_SHIFT (0U) +#define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK) + +/*! @name ONEMS - UART One Millisecond Register */ +#define UART_ONEMS_ONEMS_MASK (0xFFFFFFU) +#define UART_ONEMS_ONEMS_SHIFT (0U) +#define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK) + +/*! @name UTS - UART Test Register */ +#define UART_UTS_SOFTRST_MASK (0x1U) +#define UART_UTS_SOFTRST_SHIFT (0U) +#define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK) +#define UART_UTS_RXFULL_MASK (0x8U) +#define UART_UTS_RXFULL_SHIFT (3U) +#define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK) +#define UART_UTS_TXFULL_MASK (0x10U) +#define UART_UTS_TXFULL_SHIFT (4U) +#define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK) +#define UART_UTS_RXEMPTY_MASK (0x20U) +#define UART_UTS_RXEMPTY_SHIFT (5U) +#define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK) +#define UART_UTS_TXEMPTY_MASK (0x40U) +#define UART_UTS_TXEMPTY_SHIFT (6U) +#define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK) +#define UART_UTS_RXDBG_MASK (0x200U) +#define UART_UTS_RXDBG_SHIFT (9U) +#define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK) +#define UART_UTS_LOOPIR_MASK (0x400U) +#define UART_UTS_LOOPIR_SHIFT (10U) +#define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK) +#define UART_UTS_DBGEN_MASK (0x800U) +#define UART_UTS_DBGEN_SHIFT (11U) +#define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK) +#define UART_UTS_LOOP_MASK (0x1000U) +#define UART_UTS_LOOP_SHIFT (12U) +#define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK) +#define UART_UTS_FRCPERR_MASK (0x2000U) +#define UART_UTS_FRCPERR_SHIFT (13U) +#define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK) + +/*! @name UMCR - UART RS-485 Mode Control Register */ +#define UART_UMCR_MDEN_MASK (0x1U) +#define UART_UMCR_MDEN_SHIFT (0U) +#define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK) +#define UART_UMCR_SLAM_MASK (0x2U) +#define UART_UMCR_SLAM_SHIFT (1U) +#define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK) +#define UART_UMCR_TXB8_MASK (0x4U) +#define UART_UMCR_TXB8_SHIFT (2U) +#define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK) +#define UART_UMCR_SADEN_MASK (0x8U) +#define UART_UMCR_SADEN_SHIFT (3U) +#define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK) +#define UART_UMCR_SLADDR_MASK (0xFF00U) +#define UART_UMCR_SLADDR_SHIFT (8U) +#define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK) + + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART1 base address */ +#define UART1_BASE (0x2020000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x21E8000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +/** Peripheral UART3 base address */ +#define UART3_BASE (0x21EC000u) +/** Peripheral UART3 base pointer */ +#define UART3 ((UART_Type *)UART3_BASE) +/** Peripheral UART4 base address */ +#define UART4_BASE (0x21F0000u) +/** Peripheral UART4 base pointer */ +#define UART4 ((UART_Type *)UART4_BASE) +/** Peripheral UART5 base address */ +#define UART5_BASE (0x21F4000u) +/** Peripheral UART5 base pointer */ +#define UART5 ((UART_Type *)UART5_BASE) +/** Peripheral UART6 base address */ +#define UART6_BASE (0x21FC000u) +/** Peripheral UART6 base pointer */ +#define UART6 ((UART_Type *)UART6_BASE) +/** Peripheral UART7 base address */ +#define UART7_BASE (0x2018000u) +/** Peripheral UART7 base pointer */ +#define UART7 ((UART_Type *)UART7_BASE) +/** Peripheral UART8 base address */ +#define UART8_BASE (0x2288000u) +/** Peripheral UART8 base pointer */ +#define UART8 ((UART_Type *)UART8_BASE) +/** Array initializer of UART peripheral base addresses */ +#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE, UART7_BASE, UART8_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2, UART3, UART4, UART5, UART6, UART7, UART8 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn, UART6_IRQn, UART7_IRQn, UART8_IRQn } + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification register */ +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) + +/*! @name HWGENERAL - Hardware General */ +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK (0x1C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK (0x600U) +#define USB_HWGENERAL_SM_SHIFT (9U) +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) + +/*! @name HWHOST - Host Hardware Parameters */ +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) + +/*! @name HWDEVICE - Device Hardware Parameters */ +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) + +/*! @name SBUSCFG - System Bus Config */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) + +/*! @name CAPLENGTH - Capability Registers Length */ +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) + +/*! @name HCIVERSION - Host Controller Interface Version */ +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) + +/*! @name DCIVERSION - Device Controller Interface Version */ +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) + +/*! @name USBCMD - USB Command Register */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ATDTW_MASK (0x1000U) +#define USB_USBCMD_ATDTW_SHIFT (12U) +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) + +/*! @name USBSTS - USB Status Register */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) + +/*! @name USBINTR - Interrupt Enable Register */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_ULPIE_MASK (0x400U) +#define USB_USBINTR_ULPIE_SHIFT (10U) +#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) + +/*! @name FRINDEX - USB Frame Index */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) + +/*! @name DEVICEADDR - Device Address */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) + +/*! @name BURSTSIZE - Programmable Burst Size */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) + +/*! @name ENDPTNAK - Endpoint NAK */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) + +/*! @name CONFIGFLAG - Configure Flag Register */ +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) + +/*! @name PORTSC1 - Port Status & Control */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) + +/*! @name OTGSC - On-The-Go Status & control */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) + +/*! @name USBMODE - USB Device Mode */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) + +/*! @name ENDPTPRIME - Endpoint Prime */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) + +/*! @name ENDPTFLUSH - Endpoint Flush */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) + +/*! @name ENDPTSTAT - Endpoint Status */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXD_MASK (0x2U) +#define USB_ENDPTCTRL_RXD_SHIFT (1U) +#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXI_MASK (0x20U) +#define USB_ENDPTCTRL_RXI_SHIFT (5U) +#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL_TXD_SHIFT (17U) +#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) +#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL_TXI_SHIFT (21U) +#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) +#define USB_ENDPTCTRL_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) + +/* The count of USB_ENDPTCTRL */ +#define USB_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB1 base address */ +#define USB1_BASE (g_usb1_base) //(0x2184000u) +/** Peripheral USB1 base pointer */ +#define USB1 ((USB_Type *)USB1_BASE) +/** Peripheral USB2 base address */ +#define USB2_BASE (g_usb2_base) //(0x2184200u) +/** Peripheral USB2 base pointer */ +#define USB2 ((USB_Type *)USB2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_ID_ID_MASK USB_ID_ID_MASK +#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT +#define USBHS_ID_ID(x) USB_ID_ID(x) +#define USBHS_ID_NID_MASK USB_ID_NID_MASK +#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT +#define USBHS_ID_NID(x) USB_ID_NID(x) +#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK +#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT +#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) +#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK +#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT +#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) +#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK +#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT +#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) +#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK +#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT +#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) +#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK +#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT +#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) +#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK +#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT +#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) +#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK +#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT +#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) +#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK +#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT +#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) +#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK +#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT +#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) +#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK +#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT +#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) +#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK +#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT +#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) +#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK +#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT +#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) +#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK +#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT +#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK +#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT +#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) +#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) +#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK +#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT +#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) +#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK +#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT +#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) +#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK +#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT +#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) +#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK +#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT +#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) +#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK +#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT +#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) +#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK +#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT +#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) +#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK +#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT +#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) +#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK +#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT +#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) +#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK +#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT +#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) +#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK +#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT +#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) +#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK +#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT +#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) +#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK +#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT +#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) +#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK +#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT +#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) +#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK +#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT +#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) +#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK +#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT +#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) +#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK +#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT +#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) +#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK +#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT +#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) +#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK +#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT +#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) +#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK +#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT +#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) +#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) +#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK +#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT +#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) +#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK +#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT +#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) +#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK +#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT +#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) +#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK +#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT +#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) +#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK +#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT +#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) +#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK +#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT +#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) +#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK +#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT +#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) +#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK +#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT +#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) +#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK +#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT +#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) +#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK +#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT +#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) +#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK +#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT +#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) +#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK +#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT +#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) +#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK +#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT +#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) +#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK +#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT +#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) +#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK +#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT +#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) +#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK +#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT +#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) +#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK +#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT +#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) +#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK +#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT +#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) +#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK +#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT +#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) +#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK +#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT +#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) +#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK +#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT +#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) +#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK +#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT +#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) +#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK +#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT +#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) +#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK +#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT +#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) +#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK +#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT +#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) +#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK +#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT +#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) +#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK +#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT +#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) +#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK +#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT +#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) +#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK +#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT +#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) +#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK +#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT +#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) +#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK +#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT +#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) +#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK +#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT +#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) +#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK +#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT +#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) +#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK +#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT +#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) +#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK +#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT +#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) +#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK +#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT +#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) +#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK +#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT +#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) +#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK +#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT +#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) +#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK +#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT +#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) +#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK +#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT +#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) +#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK +#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT +#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) +#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK +#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT +#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) +#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK +#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT +#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) +#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK +#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT +#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) +#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT +#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT +#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) +#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK +#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT +#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) +#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK +#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT +#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) +#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) +#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK +#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT +#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) +#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK +#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT +#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) +#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT +#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) +#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT +#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) +#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK +#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT +#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) +#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK +#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT +#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) +#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK +#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT +#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) +#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK +#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT +#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) +#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK +#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT +#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) +#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK +#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT +#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) +#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK +#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT +#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) +#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK +#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT +#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) +#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK +#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT +#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) +#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK +#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT +#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) +#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK +#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT +#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) +#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK +#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT +#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) +#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK +#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT +#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) +#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK +#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT +#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) +#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK +#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT +#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) +#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK +#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT +#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) +#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK +#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT +#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) +#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) +#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK +#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT +#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) +#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK +#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT +#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) +#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK +#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT +#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) +#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK +#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT +#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) +#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK +#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT +#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) +#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK +#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT +#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) +#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK +#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT +#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) +#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK +#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT +#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) +#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK +#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT +#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) +#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK +#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT +#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) +#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK +#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT +#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) +#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK +#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT +#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) +#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK +#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT +#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) +#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK +#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT +#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) +#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK +#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT +#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) +#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK +#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT +#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) +#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK +#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT +#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) +#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK +#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT +#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) +#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK +#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT +#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) +#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK +#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT +#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) +#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK +#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT +#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) +#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK +#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT +#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) +#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK +#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT +#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) +#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK +#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT +#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) +#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK +#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT +#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) +#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK +#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT +#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) +#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK +#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT +#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) +#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK +#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT +#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) +#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK +#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT +#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) +#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK +#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT +#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) +#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK +#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT +#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) +#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK +#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT +#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) +#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK +#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT +#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) +#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK +#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT +#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) +#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK +#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT +#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) +#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK +#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT +#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) +#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK +#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT +#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) +#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK +#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT +#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT +#define USBHS_Type USB_Type +#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } +#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + __IO uint32_t USB_OTGn_CTRL; /**< USB OTGn Control Register, offset: 0x0 */ + uint8_t RESERVED_0[20]; + __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTGn UTMI PHY Control 0 Register, offset: 0x18 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name USB_OTGn_CTRL - USB OTGn Control Register */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) + +/*! @name USB_OTGn_PHY_CTRL_0 - OTGn UTMI PHY Control 0 Register */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC1 base address */ +#define USBNC1_BASE (0x2184800u) +/** Peripheral USBNC1 base pointer */ +#define USBNC1 ((USBNC_Type *)USBNC1_BASE) +/** Peripheral USBNC2 base address */ +#define USBNC2_BASE (0x2184804u) +/** Peripheral USBNC2 base pointer */ +#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +#define USBPHY_PWD_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_RSVD0_SHIFT (0U) +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_RSVD1_SHIFT (13U) +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_RSVD2_SHIFT (21U) +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) + +/*! @name PWD_SET - USB PHY Power-Down Register */ +#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) + +/*! @name TX - USB PHY Transmitter Control Register */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK (0xF0U) +#define USBPHY_TX_RSVD0_SHIFT (4U) +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK (0xF000U) +#define USBPHY_TX_RSVD1_SHIFT (12U) +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_RSVD2_SHIFT (20U) +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_RSVD5_SHIFT (29U) +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) +#define USBPHY_TX_SET_RSVD0_SHIFT (4U) +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) +#define USBPHY_TX_SET_RSVD1_SHIFT (12U) +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_SET_RSVD2_SHIFT (20U) +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_SET_RSVD5_SHIFT (29U) +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) +#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) +#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) +#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) +#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) + +/*! @name RX - USB PHY Receiver Control Register */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK (0x8U) +#define USBPHY_RX_RSVD0_SHIFT (3U) +#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_RSVD1_SHIFT (7U) +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +#define USBPHY_RX_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_RSVD2_SHIFT (23U) +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) + +/*! @name RX_SET - USB PHY Receiver Control Register */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK (0x8U) +#define USBPHY_RX_SET_RSVD0_SHIFT (3U) +#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_SET_RSVD1_SHIFT (7U) +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_SET_RSVD2_SHIFT (23U) +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) +#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) +#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) +#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) +#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) + +/*! @name CTRL - USB PHY General Control Register */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - USB PHY General Control Register */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - USB PHY General Control Register */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - USB PHY General Control Register */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) + +/*! @name STATUS - USB PHY Status Register */ +#define USBPHY_STATUS_RSVD0_MASK (0x7U) +#define USBPHY_STATUS_RSVD0_SHIFT (0U) +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_RSVD1_MASK (0x30U) +#define USBPHY_STATUS_RSVD1_SHIFT (4U) +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RSVD2_MASK (0x80U) +#define USBPHY_STATUS_RSVD2_SHIFT (7U) +#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RSVD3_MASK (0x200U) +#define USBPHY_STATUS_RSVD3_SHIFT (9U) +#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) +#define USBPHY_STATUS_RSVD4_SHIFT (11U) +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) + +/*! @name DEBUG - USB PHY Debug Register */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) + +/*! @name DEBUG_SET - USB PHY Debug Register */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) + +/*! @name VERSION - UTMI RTL Version */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY1 base address */ +#define USBPHY1_BASE (g_usbphy1_base) //(0x20C9000u) +/** Peripheral USBPHY1 base pointer */ +#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) +/** Peripheral USBPHY2 base address */ +#define USBPHY2_BASE (g_usbphy2_base) //(0x20CA000u) +/** Peripheral USBPHY2 base pointer */ +#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) +/** Array initializer of USBPHY peripheral base addresses */ +#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x4, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x8, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0xC, array step: 0x60 */ + __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x10, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x14, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x18, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1C, array step: 0x60 */ + __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x20, array step: 0x60 */ + uint8_t RESERVED_0[12]; + __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x30, array step: 0x60 */ + uint8_t RESERVED_1[28]; + __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x50, array step: 0x60 */ + __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x54, array step: 0x60 */ + __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x58, array step: 0x60 */ + __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x5C, array step: 0x60 */ + } INSTANCE[2]; + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0xC0 */ +} USB_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/*! @name VBUS_DETECT - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT */ +#define USB_ANALOG_VBUS_DETECT_COUNT (2U) + +/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_SET */ +#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) + +/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_CLR */ +#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) + +/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_TOG */ +#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) + +/*! @name CHRG_DETECT - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT */ +#define USB_ANALOG_CHRG_DETECT_COUNT (2U) + +/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_SET */ +#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) + +/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_CLR */ +#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) + +/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_TOG */ +#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) + +/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_STAT */ +#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) + +/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_STAT */ +#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) + +/*! @name MISC - USB Misc Register */ +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC */ +#define USB_ANALOG_MISC_COUNT (2U) + +/*! @name MISC_SET - USB Misc Register */ +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_SET */ +#define USB_ANALOG_MISC_SET_COUNT (2U) + +/*! @name MISC_CLR - USB Misc Register */ +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_CLR */ +#define USB_ANALOG_MISC_CLR_COUNT (2U) + +/*! @name MISC_TOG - USB Misc Register */ +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_TOG */ +#define USB_ANALOG_MISC_TOG_COUNT (2U) + +/*! @name DIGPROG - Chip Silicon Version */ +#define USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU) +#define USB_ANALOG_DIGPROG_MINOR_SHIFT (0U) +#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT (8U) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT (16U) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) + + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (g_usb_analog_base) //(0x20C81A0u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +/** Array initializer of USB_ANALOG peripheral base addresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[84]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) + +/*! @name BLK_ATT - Block Attributes */ +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) + +/*! @name CMD_ARG - Command Argument */ +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) + +/*! @name CMD_RSP0 - Command Response0 */ +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) + +/*! @name CMD_RSP1 - Command Response1 */ +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) + +/*! @name CMD_RSP2 - Command Response2 */ +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) + +/*! @name CMD_RSP3 - Command Response3 */ +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) + +/*! @name PRES_STATE - Present State */ +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) +#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) +#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) +#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) +#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) +#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) +#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) +#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) +#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) + +/*! @name PROT_CTRL - Protocol Control */ +#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) +#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) +#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) +#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) +#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) +#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) +#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) +#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) + +/*! @name SYS_CTRL - System Control */ +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) + +/*! @name INT_STATUS - Interrupt Status */ +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) + +/*! @name WTMK_LVL - Watermark Level */ +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) +#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) +#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) +#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) +#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) +#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) + +/*! @name MIX_CTRL - Mixer Control */ +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) + +/*! @name FORCE_EVENT - Force Event */ +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) + +/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name DLL_STATUS - DLL Status */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) + +/*! @name VEND_SPEC - Vendor Specific Register */ +#define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U) +#define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U) +#define USDHC_VEND_SPEC_EXT_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK) +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) +#define USDHC_VEND_SPEC_DAT3_CD_POL_MASK (0x10U) +#define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT (4U) +#define USDHC_VEND_SPEC_DAT3_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK) +#define USDHC_VEND_SPEC_CD_POL_MASK (0x20U) +#define USDHC_VEND_SPEC_CD_POL_SHIFT (5U) +#define USDHC_VEND_SPEC_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK) +#define USDHC_VEND_SPEC_WP_POL_MASK (0x40U) +#define USDHC_VEND_SPEC_WP_POL_SHIFT (6U) +#define USDHC_VEND_SPEC_WP_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK (0x80U) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT (7U) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK (0x800U) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT (11U) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT (12U) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK (0x2000U) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK (0x4000U) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT (14U) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) +#define USDHC_VEND_SPEC_INT_ST_VAL_MASK (0xFF0000U) +#define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT (16U) +#define USDHC_VEND_SPEC_INT_ST_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) + +/*! @name MMC_BOOT - MMC Boot Register */ +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK (0x1U) +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U) +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK (0x2U) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT (1U) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK (0x4U) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT (2U) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x800000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (23U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) + +/*! @name TUNING_CTRL - Tuning Control Register */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x2190000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x2194000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) + +/*! @name WSR - Watchdog Service Register */ +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) + +/*! @name WRSR - Watchdog Reset Status Register */ +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) + +/*! @name WICR - Watchdog Interrupt Control Register */ +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x20BC000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x20C0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Peripheral WDOG3 base address */ +#define WDOG3_BASE (0x21E4000u) +/** Peripheral WDOG3 base pointer */ +#define WDOG3 ((WDOG_Type *)WDOG3_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer + * @{ + */ + +/** XTALOSC24M - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[336]; + __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x150 */ + __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x154 */ + __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x158 */ + __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x15C */ + __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x160 */ + __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x164 */ + __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x168 */ + __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x16C */ + __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x170 */ + __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x174 */ + __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x178 */ + __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x17C */ +} XTALOSC24M_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) + + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Masks */ + + +/* XTALOSC24M - Peripheral instance base addresses */ +/** Peripheral XTALOSC24M base address */ +#define XTALOSC24M_BASE (0x20C8150u) +/** Peripheral XTALOSC24M base pointer */ +#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) +/** Array initializer of XTALOSC24M peripheral base addresses */ +#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } +/** Array initializer of XTALOSC24M peripheral base pointers */ +#define XTALOSC24M_BASE_PTRS { XTALOSC24M } + +/*! + * @} + */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MCIMX6Y2_H_ */ + diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.xml b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.xml new file mode 100644 index 0000000000000000000000000000000000000000..6f0991e335bcca6a97f0e5615bfbffb659e13825 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.xml @@ -0,0 +1,162023 @@ + + + nxp.com + MCIMX6Y2 + 1.0 + MCIMX6Y0DVM05, MCIMX6Y0CVM05, MCIMX6Y1DVM05, MCIMX6Y1DVK05, MCIMX6Y1CVM05, MCIMX6Y1CVK05, MCIMX6Y2DVM05, MCIMX6Y7DVK05 + + other + r2p0 + little + false + false + true + 0 + false + + 8 + 32 + + + APBH + APBH Register Reference Index + APBH + APBH_ + 0x1804000 + + 0 + 0x804 + registers + + + APBH + 45 + + + + CTRL0 + AHB to APBH Bridge Control and Status Register 0 + 0 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 0x1C + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 0x1F + 1 + read-write + + + + + CTRL0_SET + AHB to APBH Bridge Control and Status Register 0 + 0x4 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 0x1C + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 0x1F + 1 + read-write + + + + + CTRL0_CLR + AHB to APBH Bridge Control and Status Register 0 + 0x8 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 0x1C + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 0x1F + 1 + read-write + + + + + CTRL0_TOG + AHB to APBH Bridge Control and Status Register 0 + 0xC + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 0x1C + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 0x1F + 1 + read-write + + + + + CTRL1 + AHB to APBH Bridge Control and Status Register 1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 0x1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 0x2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 0x3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 0x4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 0x5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 0x6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 0x7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 0x10 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 0x11 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 0x12 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 0x13 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 0x14 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 0x15 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 0x16 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 0x17 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 0x18 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 0x19 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 0x1A + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 0x1B + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 0x1C + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 0x1D + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 0x1E + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 0x1F + 1 + read-write + + + + + CTRL1_SET + AHB to APBH Bridge Control and Status Register 1 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 0x1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 0x2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 0x3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 0x4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 0x5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 0x6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 0x7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 0x10 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 0x11 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 0x12 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 0x13 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 0x14 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 0x15 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 0x16 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 0x17 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 0x18 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 0x19 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 0x1A + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 0x1B + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 0x1C + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 0x1D + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 0x1E + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 0x1F + 1 + read-write + + + + + CTRL1_CLR + AHB to APBH Bridge Control and Status Register 1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 0x1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 0x2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 0x3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 0x4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 0x5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 0x6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 0x7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 0x10 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 0x11 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 0x12 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 0x13 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 0x14 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 0x15 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 0x16 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 0x17 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 0x18 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 0x19 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 0x1A + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 0x1B + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 0x1C + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 0x1D + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 0x1E + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 0x1F + 1 + read-write + + + + + CTRL1_TOG + AHB to APBH Bridge Control and Status Register 1 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 0x1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 0x2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 0x3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 0x4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 0x5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 0x6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 0x7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 0x10 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 0x11 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 0x12 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 0x13 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 0x14 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 0x15 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 0x16 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 0x17 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 0x18 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 0x19 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 0x1A + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 0x1B + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 0x1C + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 0x1D + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 0x1E + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 0x1F + 1 + read-write + + + + + CTRL2 + AHB to APBH Bridge Control and Status Register 2 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 0x1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 0x2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 0x3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 0x4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 0x5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 0x6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 0x7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 0x10 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 0x11 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 0x12 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 0x13 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 0x14 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 0x15 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 0x16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 0x17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 0x18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 0x19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 0x1A + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 0x1B + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 0x1C + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 0x1D + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 0x1E + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 0x1F + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CTRL2_SET + AHB to APBH Bridge Control and Status Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 0x1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 0x2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 0x3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 0x4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 0x5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 0x6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 0x7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 0x10 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 0x11 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 0x12 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 0x13 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 0x14 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 0x15 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 0x16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 0x17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 0x18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 0x19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 0x1A + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 0x1B + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 0x1C + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 0x1D + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 0x1E + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 0x1F + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CTRL2_CLR + AHB to APBH Bridge Control and Status Register 2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 0x1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 0x2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 0x3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 0x4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 0x5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 0x6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 0x7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 0x10 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 0x11 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 0x12 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 0x13 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 0x14 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 0x15 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 0x16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 0x17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 0x18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 0x19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 0x1A + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 0x1B + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 0x1C + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 0x1D + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 0x1E + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 0x1F + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CTRL2_TOG + AHB to APBH Bridge Control and Status Register 2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 0x1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 0x2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 0x3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 0x4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 0x5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 0x6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 0x7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 0x10 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 0x11 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 0x12 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 0x13 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 0x14 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 0x15 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 0x16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 0x17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 0x18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 0x19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 0x1A + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 0x1B + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 0x1C + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 0x1D + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 0x1E + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 0x1F + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CHANNEL_CTRL + AHB to APBH Bridge Channel Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 0x10 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + + + CHANNEL_CTRL_SET + AHB to APBH Bridge Channel Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 0x10 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + + + CHANNEL_CTRL_CLR + AHB to APBH Bridge Channel Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 0x10 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + + + CHANNEL_CTRL_TOG + AHB to APBH Bridge Channel Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 0x10 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + + + DEVSEL + AHB to APBH DMA Device Assignment Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + DMA_BURST_SIZE + AHB to APBH DMA burst size + 0x50 + 32 + read-write + 0x555555 + 0xFFFFFFFF + + + CH0 + DMA burst size for GPMI channel 0. Do not change. GPMI only support burst size 4. + 0 + 2 + read-write + + + CH1 + DMA burst size for GPMI channel 1. Do not change. GPMI only support burst size 4. + 0x2 + 2 + read-write + + + CH2 + DMA burst size for GPMI channel 2. Do not change. GPMI only support burst size 4. + 0x4 + 2 + read-write + + + CH3 + DMA burst size for GPMI channel 3. Do not change. GPMI only support burst size 4. + 0x6 + 2 + read-write + + + CH4 + DMA burst size for GPMI channel 4. Do not change. GPMI only support burst size 4. + 0x8 + 2 + read-write + + + CH5 + DMA burst size for GPMI channel 5. Do not change. GPMI only support burst size 4. + 0xA + 2 + read-write + + + CH6 + DMA burst size for GPMI channel 6. Do not change. GPMI only support burst size 4. + 0xC + 2 + read-write + + + CH7 + DMA burst size for GPMI channel 7. Do not change. GPMI only support burst size 4. + 0xE + 2 + read-write + + + CH8 + DMA burst size for SSP. + 0x10 + 2 + read-write + + + BURST0 + no description available + 0 + + + BURST4 + no description available + 0x1 + + + BURST8 + no description available + 0x2 + + + + + + + DEBUG + AHB to APBH DMA Debug Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPMI_ONE_FIFO + Set to 0ne and the 8 GPMI channels will share the DMA FIFO, and when set to zero, the 8 GPMI channels will use its own DMA FIFO + 0 + 1 + read-write + + + + + 16 + 0x70 + CH%s_CURCMDAR + APBH DMA Channel n Current Command Address Register + 0x100 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMD_ADDR + Pointer to command structure currently being processed for channel n. + 0 + 32 + read-only + + + + + 16 + 0x70 + CH%s_NXTCMDAR + APBH DMA Channel n Next Command Address Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD_ADDR + Pointer to next command structure for channel n. + 0 + 32 + read-write + + + + + 16 + 0x70 + CH%s_CMD + APBH DMA Channel n Command Register + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + COMMAND + This bitfield indicates the type of current command: + 0 + 2 + read-only + + + NO_DMA_XFER + Perform any requested PIO word transfers but terminate command before any DMA transfer. + 0 + + + DMA_WRITE + Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + 0x1 + + + DMA_READ + Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + 0x2 + + + DMA_SENSE + Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. + 0x3 + + + + + CHAIN + A value of one indicates that another command is chained onto the end of the current command structure + 0x2 + 1 + read-only + + + IRQONCMPLT + A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i + 0x3 + 1 + read-only + + + NANDLOCK + A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels + 0x4 + 1 + read-only + + + NANDWAIT4READY + A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command + 0x5 + 1 + read-only + + + SEMAPHORE + A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure + 0x6 + 1 + read-only + + + WAIT4ENDCMD + A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command + 0x7 + 1 + read-only + + + HALTONTERMINATE + A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set + 0x8 + 1 + read-only + + + CMDWORDS + This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there + 0xC + 4 + read-only + + + XFER_COUNT + This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device + 0x10 + 16 + read-only + + + + + 16 + 0x70 + CH%s_BAR + APBH DMA Channel n Buffer Address Register + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDRESS + Address of system memory buffer to be read or written over the AHB bus. + 0 + 32 + read-only + + + + + 16 + 0x70 + CH%s_SEMA + APBH DMA Channel n Semaphore Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT_SEMA + The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + PHORE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + 16 + 0x70 + CH%s_DEBUG1 + AHB to APBH DMA Channel n Debug Information + 0x150 + 32 + read-only + 0xA00000 + 0xFFFFFFFF + + + STATEMACHINE + PIO Display of the DMA Channel n state machine state. + 0 + 5 + read-only + + + IDLE + This is the idle state of the DMA state machine. + 0 + + + REQ_CMD1 + State in which the DMA is waiting to receive the first word of a command. + 0x1 + + + REQ_CMD3 + State in which the DMA is waiting to receive the third word of a command. + 0x2 + + + REQ_CMD2 + State in which the DMA is waiting to receive the second word of a command. + 0x3 + + + XFER_DECODE + The state machine processes the descriptor command field in this state and branches accordingly. + 0x4 + + + REQ_WAIT + The state machine waits in this state for the PIO APB cycles to complete. + 0x5 + + + REQ_CMD4 + State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. + 0x6 + + + PIO_REQ + This state determines whether another PIO cycle needs to occur before starting DMA transfers. + 0x7 + + + READ_FLUSH + During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + 0x8 + + + READ_WAIT + When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + 0x9 + + + WRITE + During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + 0xC + + + READ_REQ + During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + 0xD + + + CHECK_CHAIN + Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + 0xE + + + XFER_COMPLETE + The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + 0xF + + + TERMINATE + When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + 0x14 + + + WAIT_END + When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + 0x15 + + + WRITE_WAIT + During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + 0x1C + + + HALT_AFTER_TERM + If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state + 0x1D + + + CHECK_WAIT + If the Chain bit is a 0, the state machine enters this state and effectively halts. + 0x1E + + + WAIT_READY + When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. + 0x1F + + + + + WR_FIFO_FULL + This bit reflects the current state of the DMA Channel's Write FIFO Full signal. + 0x14 + 1 + read-only + + + WR_FIFO_EMPTY + This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. + 0x15 + 1 + read-only + + + RD_FIFO_FULL + This bit reflects the current state of the DMA Channel's Read FIFO Full signal. + 0x16 + 1 + read-only + + + RD_FIFO_EMPTY + This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. + 0x17 + 1 + read-only + + + NEXTCMDADDRVALID + This bit reflects the internal bit which indicates whether the channel's next command address is valid + 0x18 + 1 + read-only + + + READY + This bit is reserved for this DMA Channel and always reads 0. + 0x1A + 1 + read-only + + + END + This bit reflects the current state of the DMA End Command Signal sent from the APB Device + 0x1C + 1 + read-only + + + KICK + This bit reflects the current state of the DMA Kick Signal sent to the APB Device + 0x1D + 1 + read-only + + + BURST + This bit reflects the current state of the DMA Burst Signal from the APB device + 0x1E + 1 + read-only + + + REQ + This bit reflects the current state of the DMA Request Signal from the APB device + 0x1F + 1 + read-only + + + + + 16 + 0x70 + CH%s_DEBUG2 + AHB to APBH DMA Channel n Debug Information + 0x160 + 32 + read-only + 0 + 0xFFFFFFFF + + + AHB_BYTES + This value reflects the current number of AHB bytes remaining to be transfered in the current transfer + 0 + 16 + read-only + + + APB_BYTES + This value reflects the current number of APB bytes remaining to be transfered in the current transfer + 0x10 + 16 + read-only + + + + + VERSION + APBH Bridge Version Register + 0x800 + 32 + read-only + 0x3010000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + + + GPMI + GPMI + GPMI + GPMI_ + 0x1806000 + + 0 + 0x134 + registers + + + RAWNAND_GPMI + 48 + + + + CTRL0 + GPMI Control Register 0 Description + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 0x10 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 0x11 + 3 + read-write + + + CS + Selects which chip select is active for this command + 0x14 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 0x17 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 0x18 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 0x1A + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 0x1B + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 0x1C + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 0x1D + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set to zero for normal operation + 0x1F + 1 + read-write + + + + + CTRL0_SET + GPMI Control Register 0 Description + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 0x10 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 0x11 + 3 + read-write + + + CS + Selects which chip select is active for this command + 0x14 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 0x17 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 0x18 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 0x1A + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 0x1B + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 0x1C + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 0x1D + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set to zero for normal operation + 0x1F + 1 + read-write + + + + + CTRL0_CLR + GPMI Control Register 0 Description + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 0x10 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 0x11 + 3 + read-write + + + CS + Selects which chip select is active for this command + 0x14 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 0x17 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 0x18 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 0x1A + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 0x1B + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 0x1C + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 0x1D + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set to zero for normal operation + 0x1F + 1 + read-write + + + + + CTRL0_TOG + GPMI Control Register 0 Description + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 0x10 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 0x11 + 3 + read-write + + + CS + Selects which chip select is active for this command + 0x14 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 0x17 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 0x18 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 0x1A + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 0x1B + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 0x1C + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 0x1D + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set to zero for normal operation + 0x1F + 1 + read-write + + + + + COMPARE + GPMI Compare Register Description + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + REFERENCE + 16-bit value which is XORed with data read from the NAND device. + 0 + 16 + read-write + + + MASK + 16-bit mask which is applied after the read data is XORed with the REFERENCE bit field. + 0x10 + 16 + read-write + + + + + ECCCTRL + GPMI Integrated ECC Control Register Description + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x9 + 3 + read-only + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 0xC + 1 + read-write + + + ECC_CMD + ECC Command information + 0xD + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0xF + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 0x10 + 16 + read-write + + + + + ECCCTRL_SET + GPMI Integrated ECC Control Register Description + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x9 + 3 + read-only + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 0xC + 1 + read-write + + + ECC_CMD + ECC Command information + 0xD + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0xF + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 0x10 + 16 + read-write + + + + + ECCCTRL_CLR + GPMI Integrated ECC Control Register Description + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x9 + 3 + read-only + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 0xC + 1 + read-write + + + ECC_CMD + ECC Command information + 0xD + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0xF + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 0x10 + 16 + read-write + + + + + ECCCTRL_TOG + GPMI Integrated ECC Control Register Description + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x9 + 3 + read-only + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 0xC + 1 + read-write + + + ECC_CMD + ECC Command information + 0xD + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0xF + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 0x10 + 16 + read-write + + + + + ECCCOUNT + GPMI Integrated ECC Transfer Count Register Description + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + Number of bytes to pass through ECC + 0 + 16 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0x10 + 16 + read-write + + + + + PAYLOAD + GPMI Payload Address Register Description + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Always write zeroes to this bit field. + 0 + 2 + read-only + + + ADDRESS + Pointer to an array of one or more 512 byte payload buffers. + 0x2 + 30 + read-write + + + + + AUXILIARY + GPMI Auxiliary Address Register Description + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Always write zeroes to this bit field. + 0 + 2 + read-only + + + ADDRESS + Pointer to ECC control structure and meta-data storage. + 0x2 + 30 + read-write + + + + + CTRL1 + GPMI Control Register 1 Description + 0x60 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 0x1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 0x2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 0x3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 0x4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 0x7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 0x8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 0x9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 0xA + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 0xB + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 0xC + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 0x10 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 0x11 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 0x12 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 0x13 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 0x14 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 0x15 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 0x16 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 0x18 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 0x19 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 0x1A + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 0x1B + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 0x1C + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 0x1D + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 0x1E + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 0x1F + 1 + read-write + + + + + CTRL1_SET + GPMI Control Register 1 Description + 0x64 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 0x1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 0x2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 0x3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 0x4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 0x7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 0x8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 0x9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 0xA + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 0xB + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 0xC + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 0x10 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 0x11 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 0x12 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 0x13 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 0x14 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 0x15 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 0x16 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 0x18 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 0x19 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 0x1A + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 0x1B + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 0x1C + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 0x1D + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 0x1E + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 0x1F + 1 + read-write + + + + + CTRL1_CLR + GPMI Control Register 1 Description + 0x68 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 0x1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 0x2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 0x3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 0x4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 0x7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 0x8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 0x9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 0xA + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 0xB + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 0xC + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 0x10 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 0x11 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 0x12 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 0x13 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 0x14 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 0x15 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 0x16 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 0x18 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 0x19 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 0x1A + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 0x1B + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 0x1C + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 0x1D + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 0x1E + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 0x1F + 1 + read-write + + + + + CTRL1_TOG + GPMI Control Register 1 Description + 0x6C + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 0x1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 0x2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 0x3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 0x4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 0x7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 0x8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 0x9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 0xA + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 0xB + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 0xC + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 0x10 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 0x11 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 0x12 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 0x13 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 0x14 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 0x15 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 0x16 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 0x18 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 0x19 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 0x1A + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 0x1B + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 0x1C + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 0x1D + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 0x1E + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 0x1F + 1 + read-write + + + + + TIMING0 + GPMI Timing Register 0 Description + 0x70 + 32 + read-write + 0x10203 + 0xFFFFFFFF + + + DATA_SETUP + Data bus setup time in GPMICLK cycles + 0 + 8 + read-write + + + DATA_HOLD + Data bus hold time in GPMICLK cycles + 0x8 + 8 + read-write + + + ADDRESS_SETUP + Number of GPMICLK cycles that the CE/ADDR signals are active before a strobe is asserted + 0x10 + 8 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x18 + 8 + write-only + + + + + TIMING1 + GPMI Timing Register 1 Description + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD1 + Always write zeroes to this bit field. + 0 + 16 + read-only + + + DEVICE_BUSY_TIMEOUT + Timeout waiting for NAND Ready/Busy or ATA IRQ + 0x10 + 16 + read-write + + + + + TIMING2 + GPMI Timing Register 2 Description + 0x90 + 32 + read-write + 0x3023336 + 0xFFFFFFFF + + + DATA_PAUSE + GPMI delay time from data pause to data resume in GPMICLK cycles + 0 + 4 + read-write + + + CMDADD_PAUSE + GPMI delay time from command or addres pause to command or address resume in GPMICLK cycles + 0x4 + 4 + read-write + + + POSTAMBLE_DELAY + GPMI post-amble delay in GPMICLK cycles. A value of zero is interpreted as 16. + 0x8 + 4 + read-write + + + PREAMBLE_DELAY + GPMI pre-amble delay in GPMICLK cycles. A value of zero is interpreted as 16. + 0xC + 4 + read-write + + + CE_DELAY + GPMI dealy from CEn assert to W/Rn changing edge. value of zero is interpreted as 32. + 0x10 + 5 + read-write + + + RSVD0 + Always write zeroes to this bit field. + 0x15 + 3 + read-only + + + READ_LATENCY + This field is for double data rate read latency configuration. others READ LATENCY is 3 + 0x18 + 3 + read-write + + + READ_LATENCY_0 + READ LATENCY is 0 + 0 + + + READ_LATENCY_1 + READ LATENCY is 1 + 0x1 + + + READ_LATENCY_2 + READ LATENCY is 2 + 0x2 + + + READ_LATENCY_3 + READ LATENCY is 3 + 0x3 + + + READ_LATENCY_4 + READ LATENCY is 4 + 0x4 + + + READ_LATENCY_5 + READ LATENCY is 5 + 0x5 + + + + + TCR + Only for Toggle NAND timing control delay (TCR+1) GPMICLK cycles for CEn_B low to RE_B low, 0 is less than or equal to TCR, which is less than the PREAMBLE_DELAY + 0x1B + 2 + read-write + + + TRPSTH + Only for Toggle NAND timing control delay TRPSTH GPMICLK cycles for CEn_B high to RE_B high, A value of zero is interpreted as 8 + 0x1D + 3 + read-write + + + + + DATA + GPMI DMA Data Transfer Register Description + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + In 8-bit mode, one, two, three or four bytes can can be accessed to send the same number of bus cycles + 0 + 32 + read-write + + + + + STAT + GPMI Status Register Description + 0xB0 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + PRESENT + UNAVAILABLE = 0x0 GPMI is not present in this product + 0 + 1 + read-only + + + PRESENT_0 + GPMI is not present in this product. + 0 + + + PRESENT_1 + GPMI is present is in this product. + 0x1 + + + + + FIFO_FULL + NOT_FULL = 0x0 FIFO is not full. FULL = 0x1 FIFO is full. + 0x1 + 1 + read-only + + + FIFO_FULL_0 + FIFO is not full. + 0 + + + FIFO_FULL_1 + FIFO is full. + 0x1 + + + + + FIFO_EMPTY + NOT_EMPTY = 0x0 FIFO is not empty. EMPTY = 0x1 FIFO is empty. + 0x2 + 1 + read-only + + + FIFO_EMPTY_0 + FIFO is not empty. + 0 + + + FIFO_EMPTY_1 + FIFO is empty. + 0x1 + + + + + INVALID_BUFFER_MASK + Buffer Mask Validity bit. + 0x3 + 1 + read-only + + + INVALID_BUFFER_MASK_0 + ECC Buffer Mask is not invalid. + 0 + + + INVALID_BUFFER_MASK_1 + ECC Buffer Mask is invalid. + 0x1 + + + + + ATA_IRQ + Status of the ATA_IRQ input pin. + 0x4 + 1 + read-only + + + RSVD1 + Always write zeroes to this bit field. + 0x5 + 3 + read-only + + + DEV0_ERROR + DMA channel 0 (Timeout or compare failure, depending on COMMAND_MODE). + 0x8 + 1 + read-only + + + DEV0_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 0. + 0 + + + DEV0_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV1_ERROR + DMA channel 1 (Timeout or compare failure, depending on COMMAND_MODE). + 0x9 + 1 + read-only + + + DEV1_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 1. + 0 + + + DEV1_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV2_ERROR + DMA channel 2 (Timeout or compare failure, depending on COMMAND_MODE). + 0xA + 1 + read-only + + + DEV2_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 2. + 0 + + + DEV2_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV3_ERROR + DMA channel 3 (Timeout or compare failure, depending on COMMAND_MODE). + 0xB + 1 + read-only + + + DEV3_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 3. + 0 + + + DEV3_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV4_ERROR + DMA channel 4 (Timeout or compare failure, depending on COMMAND_MODE). + 0xC + 1 + read-only + + + DEV4_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 4. + 0 + + + DEV4_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV5_ERROR + DMA channel 5 (Timeout or compare failure, depending on COMMAND_MODE). + 0xD + 1 + read-only + + + DEV5_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 5. + 0 + + + DEV5_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV6_ERROR + DMA channel 6 (Timeout or compare failure, depending on COMMAND_MODE). + 0xE + 1 + read-only + + + DEV6_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 6. + 0 + + + DEV6_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV7_ERROR + DMA channel 7 (Timeout or compare failure, depending on COMMAND_MODE). + 0xF + 1 + read-only + + + DEV7_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 7. + 0 + + + DEV7_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + RDY_TIMEOUT + State of the RDY/BUSY Timeout Flags + 0x10 + 8 + read-only + + + READY_BUSY + Read-only view of NAND Ready_Busy Input pins. + 0x18 + 8 + read-only + + + + + DEBUG + GPMI Debug Information Register Description + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMD_END + Read Only view of the Command End toggle signals to DMA. One per channel + 0 + 8 + read-only + + + DMAREQ + Read-only view of DMA request line for 8 DMA channels + 0x8 + 8 + read-only + + + DMA_SENSE + Read-only view of sense state of the 8 DMA channels + 0x10 + 8 + read-only + + + WAIT_FOR_READY_END + Read Only view of the Wait_For_Ready End toggle signals to DMA. One per channel + 0x18 + 8 + read-only + + + + + VERSION + GPMI Version Register Description + 0xD0 + 32 + read-only + 0x5020000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + DEBUG2 + GPMI Debug2 Information Register Description + 0xE0 + 32 + read-write + 0xF100 + 0xFFFFFFFF + + + RDN_TAP + This is the DLL tap calculated by the DLL controller + 0 + 6 + read-only + + + UPDATE_WINDOW + A 1 indicates that the DLL is busy generating the required delay. + 0x6 + 1 + read-only + + + VIEW_DELAYED_RDN + Set to a 1 to select the delayed feedback RE_B to drive the GPMI_ADDR[0] (Nand CLE) pin + 0x7 + 1 + read-write + + + SYND2GPMI_READY + Data handshake Input from BCH. + 0x8 + 1 + read-only + + + SYND2GPMI_VALID + Data handshake Input from BCH. + 0x9 + 1 + read-only + + + GPMI2SYND_READY + Data handshake output to BCH. + 0xA + 1 + read-only + + + GPMI2SYND_VALID + Data handshake output to BCH. + 0xB + 1 + read-only + + + SYND2GPMI_BE + Data byte enable Input from BCH. + 0xC + 4 + read-only + + + MAIN_STATE + parameter MSM_IDLE = 4'h0, MSM_BYTCNT = 4'h1, MSM_WAITFE = 4'h2, MSM_WAITFR = 4'h3, MSM_DMAREQ = 4'h4, MSM_DMAACK = 4'h5, MSM_WAITFF = 4'h6, MSM_LDFIFO = 4'h7, MSM_LDDMAR = 4'h8, MSM_RDCMP = 4'h9, MSM_DONE = 4'hA + 0x10 + 4 + read-only + + + PIN_STATE + parameter PSM_IDLE = 3'h0, PSM_BYTCNT = 3'h1, PSM_ADDR = 3'h2, PSM_STALL = 3'h3, PSM_STROBE = 3'h4, PSM_ATARDY = 3'h5, PSM_DHOLD = 3'h6, PSM_DONE = 3'h7 + 0x14 + 3 + read-only + + + BUSY + When asserted the GPMI is busy + 0x17 + 1 + read-only + + + UDMA_STATE + USM_IDLE = 4'h0, idle USM_DMARQ = 4'h1, DMA req USM_ACK = 4'h2, DMA ACK USM_FIFO_E = 4'h3, Fifo empty USM_WPAUSE = 4'h4, WR DMA Paused by device USM_TSTRB = 4'h5, Toggle HSTROBE USM_CAPTUR = 4'h6, Capture Stage, (data sampled with DSTROBE is valid) USM_DATOUT = 4'h7, Change Burst DATAOUT USM_CRC = 4'h8, Source CRC to Device USM_WAIT_R = 4'h9, Waiting for DDMARDY- USM_END = 4'ha; Negate DMAACK (end of DMA) USM_WAIT_S = 4'hb, Waiting for DSTROBE USM_RPAUSE = 4'hc, Rd DMA Paused by Host USM_RSTOP = 4'hd, Rd DMA Stopped by Host USM_WTERM = 4'he, Wr DMA Termination State USM_RTERM = 4'hf, Rd DMA Termination state + 0x18 + 4 + read-only + + + RSVD1 + Always write zeroes to this bit field. + 0x1C + 4 + read-write + + + + + DEBUG3 + GPMI Debug3 Information Register Description + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEV_WORD_CNTR + Reflects the number of bytes remains to be transferred on the ATA/Nand bus. + 0 + 16 + read-only + + + APB_WORD_CNTR + Reflects the number of bytes remains to be transferred on the APB bus. + 0x10 + 16 + read-only + + + + + READ_DDR_DLL_CTRL + GPMI Double Rate Read DLL Control Register Description + 0x100 + 32 + read-write + 0x38 + 0xFFFFFFFF + + + ENABLE + Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL + 0 + 1 + read-write + + + RESET + Setting this bit to 1 force a reset on DLL + 0x1 + 1 + read-write + + + SLV_FORCE_UPD + Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately + 0x2 + 1 + read-write + + + SLV_DLY_TARGET + The delay target for the read clock is can be programmed in 1/16th increments of an GPMICLK half-period + 0x3 + 4 + read-write + + + GATE_UPDATE + Setting this bit to 1, forces the slave delay line not update + 0x7 + 1 + read-write + + + REFCLK_ON + set this bit to 1 will turn on the reference clock + 0x8 + 1 + read-write + + + SLV_OVERRIDE + Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override + 0x9 + 1 + read-write + + + SLV_OVERRIDE_VAL + When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually + 0xA + 8 + read-write + + + RSVD1 + Reserved + 0x12 + 2 + read-only + + + SLV_UPDATE_INT + Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256 GPMICLK cycles + 0x14 + 8 + read-write + + + REF_UPDATE_INT + This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control) + 0x1C + 4 + read-write + + + + + WRITE_DDR_DLL_CTRL + GPMI Double Rate Write DLL Control Register Description + 0x110 + 32 + read-write + 0x38 + 0xFFFFFFFF + + + ENABLE + Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL + 0 + 1 + read-write + + + RESET + Setting this bit to 1 force a reset on DLL + 0x1 + 1 + read-write + + + SLV_FORCE_UPD + Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately + 0x2 + 1 + read-write + + + SLV_DLY_TARGET + The delay target for the read clock can be programmed in 1/16th increments of an GPMICLK half-period + 0x3 + 4 + read-write + + + GATE_UPDATE + Setting this bit to 1, forces the slave delay line not update + 0x7 + 1 + read-write + + + REFCLK_ON + set this bit to 1 will turn on the reference clock + 0x8 + 1 + read-write + + + SLV_OVERRIDE + Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override + 0x9 + 1 + read-write + + + SLV_OVERRIDE_VAL + When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually + 0xA + 8 + read-write + + + RSVD1 + Reserved + 0x12 + 2 + read-only + + + SLV_UPDATE_INT + Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256 GPMICLK cycles + 0x14 + 8 + read-write + + + REF_UPDATE_INT + This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control) + 0x1C + 4 + read-write + + + + + READ_DDR_DLL_STS + GPMI Double Rate Read DLL Status Register Description + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + SLV_SEL + Slave delay line select status + 0x1 + 8 + read-only + + + RSVD0 + Reserved + 0x9 + 7 + read-only + + + REF_LOCK + Reference DLL lock status + 0x10 + 1 + read-only + + + REF_SEL + Reference delay line select status. + 0x11 + 8 + read-only + + + RSVD1 + Reserved + 0x19 + 7 + read-only + + + + + WRITE_DDR_DLL_STS + GPMI Double Rate Write DLL Status Register Description + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + SLV_SEL + Slave delay line select status + 0x1 + 8 + read-only + + + RSVD0 + Reserved + 0x9 + 7 + read-only + + + REF_LOCK + Reference DLL lock status + 0x10 + 1 + read-only + + + REF_SEL + Reference delay line select status. + 0x11 + 8 + read-only + + + RSVD1 + Reserved + 0x19 + 7 + read-only + + + + + + + BCH + BCH Register Reference Index + BCH + BCH_ + 0x1808000 + + 0 + 0x180 + registers + + + RAWNAND_BCH + 47 + + + + CTRL + Hardware BCH ECC Accelerator Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 0x1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 0x2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 0x3 + 1 + read-write + + + RSVD1 + This field is reserved. + 0x4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 0x8 + 1 + read-write + + + RSVD2 + This field is reserved. + 0x9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 0xA + 1 + read-write + + + RSVD3 + This field is reserved. + 0xB + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 0x10 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 0x11 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 0x12 + 2 + read-write + + + RSVD4 + This field is reserved. + 0x14 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 0x16 + 1 + read-write + + + RSVD5 + This field is reserved. + 0x17 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 0x1E + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 0x1F + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + CTRL_SET + Hardware BCH ECC Accelerator Control Register + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 0x1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 0x2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 0x3 + 1 + read-write + + + RSVD1 + This field is reserved. + 0x4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 0x8 + 1 + read-write + + + RSVD2 + This field is reserved. + 0x9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 0xA + 1 + read-write + + + RSVD3 + This field is reserved. + 0xB + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 0x10 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 0x11 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 0x12 + 2 + read-write + + + RSVD4 + This field is reserved. + 0x14 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 0x16 + 1 + read-write + + + RSVD5 + This field is reserved. + 0x17 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 0x1E + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 0x1F + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + CTRL_CLR + Hardware BCH ECC Accelerator Control Register + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 0x1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 0x2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 0x3 + 1 + read-write + + + RSVD1 + This field is reserved. + 0x4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 0x8 + 1 + read-write + + + RSVD2 + This field is reserved. + 0x9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 0xA + 1 + read-write + + + RSVD3 + This field is reserved. + 0xB + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 0x10 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 0x11 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 0x12 + 2 + read-write + + + RSVD4 + This field is reserved. + 0x14 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 0x16 + 1 + read-write + + + RSVD5 + This field is reserved. + 0x17 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 0x1E + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 0x1F + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + CTRL_TOG + Hardware BCH ECC Accelerator Control Register + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 0x1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 0x2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 0x3 + 1 + read-write + + + RSVD1 + This field is reserved. + 0x4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 0x8 + 1 + read-write + + + RSVD2 + This field is reserved. + 0x9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 0xA + 1 + read-write + + + RSVD3 + This field is reserved. + 0xB + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 0x10 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 0x11 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 0x12 + 2 + read-write + + + RSVD4 + This field is reserved. + 0x14 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 0x16 + 1 + read-write + + + RSVD5 + This field is reserved. + 0x17 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 0x1E + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 0x1F + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + STATUS0 + Hardware ECC Accelerator Status Register 0 + 0x10 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 0x2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 0x3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 0x4 + 1 + read-only + + + RSVD1 + This field is reserved. + 0x5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 0x8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 0x10 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 0x14 + 12 + read-only + + + + + STATUS0_SET + Hardware ECC Accelerator Status Register 0 + 0x14 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 0x2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 0x3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 0x4 + 1 + read-only + + + RSVD1 + This field is reserved. + 0x5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 0x8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 0x10 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 0x14 + 12 + read-only + + + + + STATUS0_CLR + Hardware ECC Accelerator Status Register 0 + 0x18 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 0x2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 0x3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 0x4 + 1 + read-only + + + RSVD1 + This field is reserved. + 0x5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 0x8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 0x10 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 0x14 + 12 + read-only + + + + + STATUS0_TOG + Hardware ECC Accelerator Status Register 0 + 0x1C + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 0x2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 0x3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 0x4 + 1 + read-only + + + RSVD1 + This field is reserved. + 0x5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 0x8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 0x10 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 0x14 + 12 + read-only + + + + + MODE + Hardware ECC Accelerator Mode Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 0x8 + 24 + read-only + + + + + MODE_SET + Hardware ECC Accelerator Mode Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 0x8 + 24 + read-only + + + + + MODE_CLR + Hardware ECC Accelerator Mode Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 0x8 + 24 + read-only + + + + + MODE_TOG + Hardware ECC Accelerator Mode Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 0x8 + 24 + read-only + + + + + ENCODEPTR + Hardware BCH ECC Loopback Encode Buffer Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + ENCODEPTR_SET + Hardware BCH ECC Loopback Encode Buffer Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + ENCODEPTR_CLR + Hardware BCH ECC Loopback Encode Buffer Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + ENCODEPTR_TOG + Hardware BCH ECC Loopback Encode Buffer Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + DATAPTR + Hardware BCH ECC Loopback Data Buffer Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + DATAPTR_SET + Hardware BCH ECC Loopback Data Buffer Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + DATAPTR_CLR + Hardware BCH ECC Loopback Data Buffer Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + DATAPTR_TOG + Hardware BCH ECC Loopback Data Buffer Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + METAPTR + Hardware BCH ECC Loopback Metadata Buffer Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + METAPTR_SET + Hardware BCH ECC Loopback Metadata Buffer Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + METAPTR_CLR + Hardware BCH ECC Loopback Metadata Buffer Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + METAPTR_TOG + Hardware BCH ECC Loopback Metadata Buffer Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + LAYOUTSELECT + Hardware ECC Accelerator Layout Select Register + 0x70 + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 0x2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 0x4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 0x6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 0x8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 0xA + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 0xC + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 0xE + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 0x10 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 0x12 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 0x14 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 0x16 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 0x18 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 0x1A + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 0x1C + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 0x1E + 2 + read-write + + + + + LAYOUTSELECT_SET + Hardware ECC Accelerator Layout Select Register + 0x74 + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 0x2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 0x4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 0x6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 0x8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 0xA + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 0xC + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 0xE + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 0x10 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 0x12 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 0x14 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 0x16 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 0x18 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 0x1A + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 0x1C + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 0x1E + 2 + read-write + + + + + LAYOUTSELECT_CLR + Hardware ECC Accelerator Layout Select Register + 0x78 + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 0x2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 0x4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 0x6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 0x8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 0xA + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 0xC + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 0xE + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 0x10 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 0x12 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 0x14 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 0x16 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 0x18 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 0x1A + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 0x1C + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 0x1E + 2 + read-write + + + + + LAYOUTSELECT_TOG + Hardware ECC Accelerator Layout Select Register + 0x7C + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 0x2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 0x4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 0x6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 0x8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 0xA + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 0xC + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 0xE + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 0x10 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 0x12 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 0x14 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 0x16 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 0x18 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 0x1A + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 0x1C + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 0x1E + 2 + read-write + + + + + FLASH0LAYOUT0 + Hardware BCH ECC Flash 0 Layout 0 Register + 0x80 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH0LAYOUT0_SET + Hardware BCH ECC Flash 0 Layout 0 Register + 0x84 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH0LAYOUT0_CLR + Hardware BCH ECC Flash 0 Layout 0 Register + 0x88 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH0LAYOUT0_TOG + Hardware BCH ECC Flash 0 Layout 0 Register + 0x8C + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH0LAYOUT1 + Hardware BCH ECC Flash 0 Layout 1 Register + 0x90 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH0LAYOUT1_SET + Hardware BCH ECC Flash 0 Layout 1 Register + 0x94 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH0LAYOUT1_CLR + Hardware BCH ECC Flash 0 Layout 1 Register + 0x98 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH0LAYOUT1_TOG + Hardware BCH ECC Flash 0 Layout 1 Register + 0x9C + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH1LAYOUT0 + Hardware BCH ECC Flash 1 Layout 0 Register + 0xA0 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH1LAYOUT0_SET + Hardware BCH ECC Flash 1 Layout 0 Register + 0xA4 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH1LAYOUT0_CLR + Hardware BCH ECC Flash 1 Layout 0 Register + 0xA8 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH1LAYOUT0_TOG + Hardware BCH ECC Flash 1 Layout 0 Register + 0xAC + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH1LAYOUT1 + Hardware BCH ECC Flash 1 Layout 1 Register + 0xB0 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH1LAYOUT1_SET + Hardware BCH ECC Flash 1 Layout 1 Register + 0xB4 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH1LAYOUT1_CLR + Hardware BCH ECC Flash 1 Layout 1 Register + 0xB8 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH1LAYOUT1_TOG + Hardware BCH ECC Flash 1 Layout 1 Register + 0xBC + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH2LAYOUT0 + Hardware BCH ECC Flash 2 Layout 0 Register + 0xC0 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH2LAYOUT0_SET + Hardware BCH ECC Flash 2 Layout 0 Register + 0xC4 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH2LAYOUT0_CLR + Hardware BCH ECC Flash 2 Layout 0 Register + 0xC8 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH2LAYOUT0_TOG + Hardware BCH ECC Flash 2 Layout 0 Register + 0xCC + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH2LAYOUT1 + Hardware BCH ECC Flash 2 Layout 1 Register + 0xD0 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH2LAYOUT1_SET + Hardware BCH ECC Flash 2 Layout 1 Register + 0xD4 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH2LAYOUT1_CLR + Hardware BCH ECC Flash 2 Layout 1 Register + 0xD8 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH2LAYOUT1_TOG + Hardware BCH ECC Flash 2 Layout 1 Register + 0xDC + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH3LAYOUT0 + Hardware BCH ECC Flash 3 Layout 0 Register + 0xE0 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH3LAYOUT0_SET + Hardware BCH ECC Flash 3 Layout 0 Register + 0xE4 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH3LAYOUT0_CLR + Hardware BCH ECC Flash 3 Layout 0 Register + 0xE8 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH3LAYOUT0_TOG + Hardware BCH ECC Flash 3 Layout 0 Register + 0xEC + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH3LAYOUT1 + Hardware BCH ECC Flash 3 Layout 1 Register + 0xF0 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH3LAYOUT1_SET + Hardware BCH ECC Flash 3 Layout 1 Register + 0xF4 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH3LAYOUT1_CLR + Hardware BCH ECC Flash 3 Layout 1 Register + 0xF8 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH3LAYOUT1_TOG + Hardware BCH ECC Flash 3 Layout 1 Register + 0xFC + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + DEBUG0 + Hardware BCH ECC Debug Register0 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 0x6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 0x8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 0x9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 0xA + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 0xB + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 0xC + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 0xD + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 0xE + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 0xF + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 0x10 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 0x19 + 7 + read-only + + + + + DEBUG0_SET + Hardware BCH ECC Debug Register0 + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 0x6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 0x8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 0x9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 0xA + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 0xB + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 0xC + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 0xD + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 0xE + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 0xF + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 0x10 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 0x19 + 7 + read-only + + + + + DEBUG0_CLR + Hardware BCH ECC Debug Register0 + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 0x6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 0x8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 0x9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 0xA + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 0xB + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 0xC + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 0xD + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 0xE + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 0xF + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 0x10 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 0x19 + 7 + read-only + + + + + DEBUG0_TOG + Hardware BCH ECC Debug Register0 + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 0x6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 0x8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 0x9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 0xA + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 0xB + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 0xC + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 0xD + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 0xE + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 0xF + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 0x10 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 0x19 + 7 + read-only + + + + + DBGKESREAD + KES Debug Read Register + 0x110 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGKESREAD_SET + KES Debug Read Register + 0x114 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGKESREAD_CLR + KES Debug Read Register + 0x118 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGKESREAD_TOG + KES Debug Read Register + 0x11C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGCSFEREAD + Chien Search Debug Read Register + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGCSFEREAD_SET + Chien Search Debug Read Register + 0x124 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGCSFEREAD_CLR + Chien Search Debug Read Register + 0x128 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGCSFEREAD_TOG + Chien Search Debug Read Register + 0x12C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD + Syndrome Generator Debug Read Register + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD_SET + Syndrome Generator Debug Read Register + 0x134 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD_CLR + Syndrome Generator Debug Read Register + 0x138 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD_TOG + Syndrome Generator Debug Read Register + 0x13C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD + Bus Master and ECC Controller Debug Read Register + 0x140 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD_SET + Bus Master and ECC Controller Debug Read Register + 0x144 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD_CLR + Bus Master and ECC Controller Debug Read Register + 0x148 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD_TOG + Bus Master and ECC Controller Debug Read Register + 0x14C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + BLOCKNAME + Block Name Register + 0x150 + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + BLOCKNAME_SET + Block Name Register + 0x154 + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + BLOCKNAME_CLR + Block Name Register + 0x158 + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + BLOCKNAME_TOG + Block Name Register + 0x15C + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + VERSION + BCH Version Register + 0x160 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + VERSION_SET + BCH Version Register + 0x164 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + VERSION_CLR + BCH Version Register + 0x168 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + VERSION_TOG + BCH Version Register + 0x16C + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + DEBUG1 + Hardware BCH ECC Debug Register 1 + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 0x9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 0x1F + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + DEBUG1_SET + Hardware BCH ECC Debug Register 1 + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 0x9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 0x1F + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + DEBUG1_CLR + Hardware BCH ECC Debug Register 1 + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 0x9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 0x1F + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + DEBUG1_TOG + Hardware BCH ECC Debug Register 1 + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 0x9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 0x1F + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + + + SPDIF + SPDIF + SPDIF + SPDIF_ + 0x2004000 + + 0 + 0x54 + registers + + + SPDIF + 84 + + + + SCR + SPDIF Configuration Register + 0 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + USrc_Sel + no description available + 0 + 2 + read-write + + + USrc_Sel_0 + No embedded U channel + 0 + + + USrc_Sel_1 + U channel from SPDIF receive block (CD mode) + 0x1 + + + USrc_Sel_3 + U channel from on chip transmitter + 0x3 + + + + + TxSel + no description available + 0x2 + 3 + read-write + + + TxSel_0 + Off and output 0 + 0 + + + TxSel_1 + Feed-through SPDIFIN + 0x1 + + + TxSel_5 + Tx Normal operation + 0x5 + + + + + ValCtrl + no description available + 0x5 + 1 + read-write + + + ValCtrl_0 + Outgoing Validity always set + 0 + + + ValCtrl_1 + Outgoing Validity always clear + 0x1 + + + + + DMA_TX_En + DMA Transmit Request Enable (Tx FIFO empty) + 0x8 + 1 + read-write + + + DMA_Rx_En + DMA Receive Request Enable (RX FIFO full) + 0x9 + 1 + read-write + + + TxFIFO_Ctrl + no description available + 0xA + 2 + read-write + + + TxFIFO_Ctrl_0 + Send out digital zero on SPDIF Tx + 0 + + + TxFIFO_Ctrl_1 + Tx Normal operation + 0x1 + + + TxFIFO_Ctrl_2 + Reset to 1 sample remaining + 0x2 + + + + + soft_reset + When write 1 to this bit, it will cause SPDIF software reset + 0xC + 1 + read-write + + + LOW_POWER + When write 1 to this bit, it will cause SPDIF enter low-power mode + 0xD + 1 + read-write + + + TxFIFOEmpty_Sel + no description available + 0xF + 2 + read-write + + + TxFIFOEmpty_Sel_0 + Empty interrupt if 0 sample in Tx left and right FIFOs + 0 + + + TxFIFOEmpty_Sel_1 + Empty interrupt if at most 4 sample in Tx left and right FIFOs + 0x1 + + + TxFIFOEmpty_Sel_2 + Empty interrupt if at most 8 sample in Tx left and right FIFOs + 0x2 + + + TxFIFOEmpty_Sel_3 + Empty interrupt if at most 12 sample in Tx left and right FIFOs + 0x3 + + + + + TxAutoSync + no description available + 0x11 + 1 + read-write + + + TxAutoSync_0 + Tx FIFO auto sync off + 0 + + + TxAutoSync_1 + Tx FIFO auto sync on + 0x1 + + + + + RxAutoSync + no description available + 0x12 + 1 + read-write + + + RxAutoSync_0 + Rx FIFO auto sync off + 0 + + + RxAutoSync_1 + RxFIFO auto sync on + 0x1 + + + + + RxFIFOFull_Sel + no description available + 0x13 + 2 + read-write + + + RxFIFOFull_Sel_0 + Full interrupt if at least 1 sample in Rx left and right FIFOs + 0 + + + RxFIFOFull_Sel_1 + Full interrupt if at least 4 sample in Rx left and right FIFOs + 0x1 + + + RxFIFOFull_Sel_2 + Full interrupt if at least 8 sample in Rx left and right FIFOs + 0x2 + + + RxFIFOFull_Sel_3 + Full interrupt if at least 16 sample in Rx left and right FIFO + 0x3 + + + + + RxFIFO_Rst + no description available + 0x15 + 1 + read-write + + + RxFIFO_Rst_0 + Normal operation + 0 + + + RxFIFO_Rst_1 + Reset register to 1 sample remaining + 0x1 + + + + + RxFIFO_Off_On + no description available + 0x16 + 1 + read-write + + + RxFIFO_Off_On_0 + SPDIF Rx FIFO is on + 0 + + + RxFIFO_Off_On_1 + SPDIF Rx FIFO is off. Does not accept data from interface + 0x1 + + + + + RxFIFO_Ctrl + no description available + 0x17 + 1 + read-write + + + RxFIFO_Ctrl_0 + Normal operation + 0 + + + RxFIFO_Ctrl_1 + Always read zero from Rx data register + 0x1 + + + + + + + SRCD + CDText Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + USyncMode + no description available + 0x1 + 1 + read-write + + + USyncMode_0 + Non-CD data + 0 + + + USyncMode_1 + CD user channel subcode + 0x1 + + + + + + + SRPC + PhaseConfig Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GainSel + Gain selection: + 0x3 + 3 + read-write + + + GainSel_0 + 24*(2**10) + 0 + + + GainSel_1 + 16*(2**10) + 0x1 + + + GainSel_2 + 12*(2**10) + 0x2 + + + GainSel_3 + 8*(2**10) + 0x3 + + + GainSel_4 + 6*(2**10) + 0x4 + + + GainSel_5 + 4*(2**10) + 0x5 + + + GainSel_6 + 3*(2**10) + 0x6 + + + + + LOCK + LOCK bit to show that the internal DPLL is locked, read only + 0x6 + 1 + read-only + + + ClkSrc_Sel + Clock source selection, all other settings not shown are reserved: + 0x7 + 4 + read-write + + + ClkSrc_Sel_0 + if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + 0 + + + ClkSrc_Sel_1 + if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + 0x1 + + + ClkSrc_Sel_3 + if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + 0x3 + + + ClkSrc_Sel_5 + REF_CLK_32K (XTALOSC) + 0x5 + + + ClkSrc_Sel_6 + tx_clk (SPDIF0_CLK_ROOT) + 0x6 + + + ClkSrc_Sel_8 + SPDIF_EXT_CLK + 0x8 + + + + + + + SIE + InterruptEn Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-write + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 0x1 + 1 + read-write + + + LockLoss + SPDIF receiver loss of lock + 0x2 + 1 + read-write + + + RxFIFOResyn + Rx FIFO resync + 0x3 + 1 + read-write + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 0x4 + 1 + read-write + + + UQErr + U/Q Channel framing error + 0x5 + 1 + read-write + + + UQSync + U/Q Channel sync found + 0x6 + 1 + read-write + + + QRxOv + Q Channel receive register overrun + 0x7 + 1 + read-write + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 0x8 + 1 + read-write + + + URxOv + U Channel receive register overrun + 0x9 + 1 + read-write + + + URxFul + U Channel receive register full, can't be cleared with reg + 0xA + 1 + read-write + + + BitErr + SPDIF receiver found parity bit error + 0xE + 1 + read-write + + + SymErr + SPDIF receiver found illegal symbol + 0xF + 1 + read-write + + + ValNoGood + SPDIF validity flag no good + 0x10 + 1 + read-write + + + CNew + SPDIF receive change in value of control channel + 0x11 + 1 + read-write + + + TxResyn + SPDIF Tx FIFO resync + 0x12 + 1 + read-write + + + TxUnOv + SPDIF Tx FIFO under/overrun + 0x13 + 1 + read-write + + + Lock + SPDIF receiver's DPLL is locked + 0x14 + 1 + read-write + + + + + SIC + InterruptClear Register + SIC_SIS + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + LockLoss + SPDIF receiver loss of lock + 0x2 + 1 + write-only + + + RxFIFOResyn + Rx FIFO resync + 0x3 + 1 + write-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 0x4 + 1 + write-only + + + UQErr + U/Q Channel framing error + 0x5 + 1 + write-only + + + UQSync + U/Q Channel sync found + 0x6 + 1 + write-only + + + QRxOv + Q Channel receive register overrun + 0x7 + 1 + write-only + + + URxOv + U Channel receive register overrun + 0x9 + 1 + write-only + + + BitErr + SPDIF receiver found parity bit error + 0xE + 1 + write-only + + + SymErr + SPDIF receiver found illegal symbol + 0xF + 1 + write-only + + + ValNoGood + SPDIF validity flag no good + 0x10 + 1 + write-only + + + CNew + SPDIF receive change in value of control channel + 0x11 + 1 + write-only + + + TxResyn + SPDIF Tx FIFO resync + 0x12 + 1 + write-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 0x13 + 1 + write-only + + + Lock + SPDIF receiver's DPLL is locked + 0x14 + 1 + write-only + + + + + SIS + InterruptStat Register + SIC_SIS + 0x10 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-only + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 0x1 + 1 + read-only + + + LockLoss + SPDIF receiver loss of lock + 0x2 + 1 + read-only + + + RxFIFOResyn + Rx FIFO resync + 0x3 + 1 + read-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 0x4 + 1 + read-only + + + UQErr + U/Q Channel framing error + 0x5 + 1 + read-only + + + UQSync + U/Q Channel sync found + 0x6 + 1 + read-only + + + QRxOv + Q Channel receive register overrun + 0x7 + 1 + read-only + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 0x8 + 1 + read-only + + + URxOv + U Channel receive register overrun + 0x9 + 1 + read-only + + + URxFul + U Channel receive register full, can't be cleared with reg + 0xA + 1 + read-only + + + BitErr + SPDIF receiver found parity bit error + 0xE + 1 + read-only + + + SymErr + SPDIF receiver found illegal symbol + 0xF + 1 + read-only + + + ValNoGood + SPDIF validity flag no good + 0x10 + 1 + read-only + + + CNew + SPDIF receive change in value of control channel + 0x11 + 1 + read-only + + + TxResyn + SPDIF Tx FIFO resync + 0x12 + 1 + read-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 0x13 + 1 + read-only + + + Lock + SPDIF receiver's DPLL is locked + 0x14 + 1 + read-only + + + + + SRL + SPDIFRxLeft Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataLeft + Processor receive SPDIF data left + 0 + 24 + read-only + + + + + SRR + SPDIFRxRight Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataRight + Processor receive SPDIF data right + 0 + 24 + read-only + + + + + SRCSH + SPDIFRxCChannel_h Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_h + SPDIF receive C channel register, contains first 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRCSL + SPDIFRxCChannel_l Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_l + SPDIF receive C channel register, contains next 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRU + UchannelRx Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxUChannel + SPDIF receive U channel register, contains next 3 U channel bytes + 0 + 24 + read-only + + + + + SRQ + QchannelRx Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxQChannel + SPDIF receive Q channel register, contains next 3 Q channel bytes + 0 + 24 + read-only + + + + + STL + SPDIFTxLeft Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataLeft + SPDIF transmit left channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STR + SPDIFTxRight Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataRight + SPDIF transmit right channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STCSCH + SPDIFTxCChannelCons_h Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_h + SPDIF transmit Cons + 0 + 24 + read-write + + + + + STCSCL + SPDIFTxCChannelCons_l Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_l + SPDIF transmit Cons + 0 + 24 + read-write + + + + + SRFM + FreqMeas Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + FreqMeas + Frequency measurement data + 0 + 24 + read-only + + + + + STC + SPDIFTxClk Register + 0x50 + 32 + read-write + 0x20F00 + 0xFFFFFFFF + + + TxClk_DF + Divider factor (1-128) + 0 + 7 + read-write + + + TxClk_DF_0 + divider factor is 1 + 0 + + + TxClk_DF_1 + divider factor is 2 + 0x1 + + + TxClk_DF_127 + divider factor is 128 + 0x7F + + + + + tx_all_clk_en + Spdif transfer clock enable.When data is going to be transfered, this bit should be set to1. + 0x7 + 1 + read-write + + + tx_all_clk_en_0 + disable transfer clock. + 0 + + + tx_all_clk_en_1 + enable transfer clock. + 0x1 + + + + + TxClk_Source + no description available + 0x8 + 3 + read-write + + + TxClk_Source_0 + REF_CLK_32K input (XTALOSC 32 kHz clock) + 0 + + + TxClk_Source_1 + tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + 0x1 + + + TxClk_Source_3 + SPDIF_EXT_CLK, from pads + 0x3 + + + TxClk_Source_5 + ipg_clk input (frequency divided) + 0x5 + + + + + SYSCLK_DF + system clock divider factor, 2~512. + 0xB + 9 + read-write + + + SYSCLK_DF_0 + no clock signal + 0 + + + SYSCLK_DF_1 + divider factor is 2 + 0x1 + + + SYSCLK_DF_511 + divider factor is 512 + 0x1FF + + + + + + + + + ECSPI1 + ECSPI + ECSPI + ECSPI1_ + 0x2008000 + ECSPI + + 0 + 0x44 + registers + + + eCSPI1 + 63 + + + + RXDATA + Receive Data Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ECSPI_RXDATA + Receive Data + 0 + 32 + read-only + + + + + TXDATA + Transmit Data Register + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_TXDATA + Transmit Data + 0 + 32 + write-only + + + + + CONREG + Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + SPI Block Enable Control + 0 + 1 + read-write + + + EN_0 + Disable the block. + 0 + + + EN_1 + Enable the block. + 0x1 + + + + + HT + Hardware Trigger Enable + 0x1 + 1 + read-write + + + HT_0 + Disable HT mode. + 0 + + + HT_1 + Enable HT mode. + 0x1 + + + + + XCH + SPI Exchange Bit + 0x2 + 1 + read-write + + + XCH_0 + Idle. + 0 + + + XCH_1 + Initiates exchange (write) or busy (read). + 0x1 + + + + + SMC + Start Mode Control + 0x3 + 1 + read-write + + + SMC_0 + SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions. + 0 + + + SMC_1 + Immediately starts a SPI burst when data is written in TXFIFO. + 0x1 + + + + + CHANNEL_MODE + SPI CHANNEL MODE selects the mode for each SPI channel + 0x4 + 4 + read-write + + + CHANNEL_MODE_0 + Slave mode. + 0 + + + CHANNEL_MODE_1 + Master mode. + 0x1 + + + + + POST_DIVIDER + SPI Post Divider + 0x8 + 4 + read-write + + + POST_DIVIDER_0 + Divide by 1. + 0 + + + POST_DIVIDER_1 + Divide by 2. + 0x1 + + + POST_DIVIDER_2 + Divide by 4. + 0x2 + + + POST_DIVIDER_14 + Divide by 2 14 . + 0xE + + + POST_DIVIDER_15 + Divide by 2 15 . + 0xF + + + + + PRE_DIVIDER + SPI Pre Divider + 0xC + 4 + read-write + + + PRE_DIVIDER_0 + Divide by 1. + 0 + + + PRE_DIVIDER_1 + Divide by 2. + 0x1 + + + PRE_DIVIDER_2 + Divide by 3. + 0x2 + + + PRE_DIVIDER_13 + Divide by 14. + 0xD + + + PRE_DIVIDER_14 + Divide by 15. + 0xE + + + PRE_DIVIDER_15 + Divide by 16. + 0xF + + + + + DRCTL + SPI Data Ready Control + 0x10 + 2 + read-write + + + DRCTL_0 + The SPI_RDY signal is a don't care. + 0 + + + DRCTL_1 + Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). + 0x1 + + + DRCTL_2 + Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). + 0x2 + + + + + CHANNEL_SELECT + SPI CHANNEL SELECT bits + 0x12 + 2 + read-write + + + CHANNEL_SELECT_0 + Channel 0 is selected. Chip Select 0 (SS0) will be asserted. + 0 + + + CHANNEL_SELECT_1 + Channel 1 is selected. Chip Select 1 (SS1) will be asserted. + 0x1 + + + CHANNEL_SELECT_2 + Channel 2 is selected. Chip Select 2 (SS2) will be asserted. + 0x2 + + + CHANNEL_SELECT_3 + Channel 3 is selected. Chip Select 3 (SS3) will be asserted. + 0x3 + + + + + BURST_LENGTH + Burst Length + 0x14 + 12 + read-write + + + BURST_LENGTH_0 + A SPI burst contains the 1 LSB in a word. + 0 + + + BURST_LENGTH_1 + A SPI burst contains the 2 LSB in a word. + 0x1 + + + BURST_LENGTH_2 + A SPI burst contains the 3 LSB in a word. + 0x2 + + + BURST_LENGTH_31 + A SPI burst contains all 32 bits in a word. + 0x1F + + + BURST_LENGTH_32 + A SPI burst contains the 1 LSB in first word and all 32 bits in second word. + 0x20 + + + BURST_LENGTH_33 + A SPI burst contains the 2 LSB in first word and all 32 bits in second word. + 0x21 + + + BURST_LENGTH_4094 + A SPI burst contains the 31 LSB in first word and 2^7 -1 words. + 0xFFE + + + BURST_LENGTH_4095 + A SPI burst contains 2^7 words. + 0xFFF + + + + + + + CONFIGREG + Config Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SCLK_PHA + SPI Clock/Data Phase Control + 0 + 4 + read-write + + + SCLK_PHA_0 + Phase 0 operation. + 0 + + + SCLK_PHA_1 + Phase 1 operation. + 0x1 + + + + + SCLK_POL + SPI Clock Polarity Control + 0x4 + 4 + read-write + + + SCLK_POL_0 + Active high polarity (0 = Idle). + 0 + + + SCLK_POL_1 + Active low polarity (1 = Idle). + 0x1 + + + + + SS_CTL + SPI SS Wave Form Select + 0x8 + 4 + read-write + + + SS_CTL_0 + In master mode - only one SPI burst will be transmitted. + 0 + + + SS_CTL_1 + In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. + 0x1 + + + + + SS_POL + SPI SS Polarity Select + 0xC + 4 + read-write + + + SS_POL_0 + Active low. + 0 + + + SS_POL_1 + Active high. + 0x1 + + + + + DATA_CTL + DATA CTL + 0x10 + 4 + read-write + + + DATA_CTL_0 + Stay high. + 0 + + + DATA_CTL_1 + Stay low. + 0x1 + + + + + SCLK_CTL + SCLK CTL + 0x14 + 4 + read-write + + + SCLK_CTL_0 + Stay low. + 0 + + + SCLK_CTL_1 + Stay high. + 0x1 + + + + + HT_LENGTH + HT LENGTH + 0x18 + 5 + read-write + + + + + INTREG + Interrupt Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEEN + TXFIFO Empty Interrupt enable. This bit enables the TXFIFO Empty Interrupt. + 0 + 1 + read-write + + + TEEN_0 + Disable + 0 + + + TEEN_1 + Enable + 0x1 + + + + + TDREN + TXFIFO Data Request Interrupt enable + 0x1 + 1 + read-write + + + TDREN_0 + Disable + 0 + + + TDREN_1 + Enable + 0x1 + + + + + TFEN + TXFIFO Full Interrupt enable. This bit enables the TXFIFO Full Interrupt. + 0x2 + 1 + read-write + + + TFEN_0 + Disable + 0 + + + TFEN_1 + Enable + 0x1 + + + + + RREN + RXFIFO Ready Interrupt enable. This bit enables the RXFIFO Ready Interrupt. + 0x3 + 1 + read-write + + + RREN_0 + Disable + 0 + + + RREN_1 + Enable + 0x1 + + + + + RDREN + RXFIFO Data Request Interrupt enable + 0x4 + 1 + read-write + + + RDREN_0 + Disable + 0 + + + RDREN_1 + Enable + 0x1 + + + + + RFEN + RXFIFO Full Interrupt enable. This bit enables the RXFIFO Full Interrupt. + 0x5 + 1 + read-write + + + RFEN_0 + Disable + 0 + + + RFEN_1 + Enable + 0x1 + + + + + ROEN + RXFIFO Overflow Interrupt enable. This bit enables the RXFIFO Overflow Interrupt. + 0x6 + 1 + read-write + + + ROEN_0 + Disable + 0 + + + ROEN_1 + Enable + 0x1 + + + + + TCEN + Transfer Completed Interrupt enable. This bit enables the Transfer Completed Interrupt. + 0x7 + 1 + read-write + + + TCEN_0 + Disable + 0 + + + TCEN_1 + Enable + 0x1 + + + + + + + DMAREG + DMA Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_THRESHOLD + TX THRESHOLD + 0 + 6 + read-write + + + TEDEN + TXFIFO Empty DMA Request Enable. This bit enables/disables the TXFIFO Empty DMA Request. + 0x7 + 1 + read-write + + + TEDEN_0 + Disable + 0 + + + TEDEN_1 + Enable + 0x1 + + + + + RX_THRESHOLD + RX THRESHOLD + 0x10 + 6 + read-write + + + RXDEN + RXFIFO DMA Request Enable. This bit enables/disables the RXFIFO DMA Request. + 0x17 + 1 + read-write + + + RXDEN_0 + Disable + 0 + + + RXDEN_1 + Enable + 0x1 + + + + + RX_DMA_LENGTH + RX DMA LENGTH + 0x18 + 6 + read-write + + + RXTDEN + RXFIFO TAIL DMA Request/Interrupt Enable + 0x1F + 1 + read-write + + + RXTDEN_0 + Disable + 0 + + + RXTDEN_1 + Enable + 0x1 + + + + + + + STATREG + Status Register + 0x18 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + TE + TXFIFO Empty. This bit is set if the TXFIFO is empty. + 0 + 1 + read-only + + + TE_0 + TXFIFO contains one or more words. + 0 + + + TE_1 + TXFIFO is empty. + 0x1 + + + + + TDR + TXFIFO Data Request. + 0x1 + 1 + read-only + + + TDR_0 + Number of valid data slots in TXFIFO is greater than TX_THRESHOLD. + 0 + + + TDR_1 + Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD. + 0x1 + + + + + TF + TXFIFO Full. This bit is set when if the TXFIFO is full. + 0x2 + 1 + read-only + + + TF_0 + TXFIFO is not Full. + 0 + + + TF_1 + TXFIFO is Full. + 0x1 + + + + + RR + RXFIFO Ready. This bit is set when one or more words are stored in the RXFIFO. + 0x3 + 1 + read-only + + + RR_0 + No valid data in RXFIFO. + 0 + + + RR_1 + More than 1 word in RXFIFO. + 0x1 + + + + + RDR + RXFIFO Data Request. + 0x4 + 1 + read-only + + + RDR_0 + When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + 0 + + + RDR_1 + When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists. + 0x1 + + + + + RF + RXFIFO Full. This bit is set when the RXFIFO is full. + 0x5 + 1 + read-only + + + RF_0 + Not Full. + 0 + + + RF_1 + Full. + 0x1 + + + + + RO + RXFIFO Overflow + 0x6 + 1 + read-write + oneToClear + + + RO_0 + RXFIFO has no overflow. + 0 + + + RO_1 + RXFIFO has overflowed. + 0x1 + + + + + TC + Transfer Completed Status bit. Writing 1 to this bit clears it. + 0x7 + 1 + read-write + oneToClear + + + TC_0 + Transfer in progress. + 0 + + + TC_1 + Transfer completed. + 0x1 + + + + + + + PERIODREG + Sample Period Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE_PERIOD + Sample Period Control + 0 + 15 + read-write + + + SAMPLE_PERIOD_0 + 0 wait states inserted + 0 + + + SAMPLE_PERIOD_1 + 1 wait state inserted + 0x1 + + + SAMPLE_PERIOD_32766 + 32766 wait states inserted + 0x7FFE + + + SAMPLE_PERIOD_32767 + 32767 wait states inserted + 0x7FFF + + + + + CSRC + Clock Source Control. This bit selects the clock source for the sample period counter. + 0xF + 1 + read-write + + + CSRC_0 + SPI Clock (SCLK) + 0 + + + CSRC_1 + Low-Frequency Reference Clock (32.768 KHz) + 0x1 + + + + + CSD_CTL + Chip Select Delay Control bits + 0x10 + 6 + read-write + + + + + TESTREG + Test Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCNT + TXFIFO Counter. This field indicates the number of words in the TXFIFO. + 0 + 7 + read-write + + + RXCNT + RXFIFO Counter. This field indicates the number of words in the RXFIFO. + 0x8 + 7 + read-write + + + LBC + Loop Back Control + 0x1F + 1 + read-write + + + LBC_0 + Not connected. + 0 + + + LBC_1 + Transmitter and receiver sections internally connected for Loopback. + 0x1 + + + + + + + MSGDATA + Message Data Register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_MSGDATA + ECSPI_MSGDATA holds the top word of MSG Data FIFO + 0 + 32 + write-only + + + + + + + ECSPI2 + ECSPI + ECSPI + ECSPI2_ + 0x200C000 + + 0 + 0x44 + registers + + + eCSPI2 + 64 + + + + ECSPI3 + ECSPI + ECSPI + ECSPI3_ + 0x2010000 + + 0 + 0x44 + registers + + + eCSPI3 + 65 + + + + ECSPI4 + ECSPI + ECSPI + ECSPI4_ + 0x2014000 + + 0 + 0x44 + registers + + + eCSPI4 + 66 + + + + UART1 + UARTv2 + UART + UART1_ + 0x2020000 + UART + + 0 + 0xBC + registers + + + UART1 + 58 + + + + URXD + UART Receiver Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RX_DATA + Received Data + 0 + 8 + read-only + + + PRERR + In RS-485 mode, it holds the ninth data bit (bit [8]) of received 9-bit RS-485 data In RS232/IrDA mode, it is the Parity Error flag + 0xA + 1 + read-only + + + PRERR_0 + = No parity error was detected for data in the RX_DATA field + 0 + + + PRERR_1 + = A parity error was detected for data in the RX_DATA field + 0x1 + + + + + BRK + BREAK Detect + 0xB + 1 + read-only + + + BRK_0 + The current character is not a BREAK character + 0 + + + BRK_1 + The current character is a BREAK character + 0x1 + + + + + FRMERR + Frame Error + 0xC + 1 + read-only + + + FRMERR_0 + The current character has no framing error + 0 + + + FRMERR_1 + The current character has a framing error + 0x1 + + + + + OVRRUN + Receiver Overrun + 0xD + 1 + read-only + + + OVRRUN_0 + No RxFIFO overrun was detected + 0 + + + OVRRUN_1 + A RxFIFO overrun was detected + 0x1 + + + + + ERR + Error Detect + 0xE + 1 + read-only + + + ERR_0 + No error status was detected + 0 + + + ERR_1 + An error status was detected + 0x1 + + + + + CHARRDY + Character Ready + 0xF + 1 + read-only + + + CHARRDY_0 + Character in RX_DATA field and associated flags are invalid. + 0 + + + CHARRDY_1 + Character in RX_DATA field and associated flags valid and ready for reading. + 0x1 + + + + + + + UTXD + UART Transmitter Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATA + Transmit Data + 0 + 8 + write-only + + + + + UCR1 + UART Control Register 1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + UARTEN + UART Enable + 0 + 1 + read-write + + + UARTEN_0 + Disable the UART + 0 + + + UARTEN_1 + Enable the UART + 0x1 + + + + + DOZE + DOZE + 0x1 + 1 + read-write + + + DOZE_0 + The UART is enabled when in DOZE state + 0 + + + DOZE_1 + The UART is disabled when in DOZE state + 0x1 + + + + + ATDMAEN + Aging DMA Timer Enable + 0x2 + 1 + read-write + + + ATDMAEN_0 + Disable AGTIM DMA request + 0 + + + ATDMAEN_1 + Enable AGTIM DMA request + 0x1 + + + + + TXDMAEN + Transmitter Ready DMA Enable + 0x3 + 1 + read-write + + + TXDMAEN_0 + Disable transmit DMA request + 0 + + + TXDMAEN_1 + Enable transmit DMA request + 0x1 + + + + + SNDBRK + Send BREAK + 0x4 + 1 + read-write + + + SNDBRK_0 + Do not send a BREAK character + 0 + + + SNDBRK_1 + Send a BREAK character (continuous 0s) + 0x1 + + + + + RTSDEN + RTS Delta Interrupt Enable + 0x5 + 1 + read-write + + + RTSDEN_0 + Disable RTSD interrupt + 0 + + + RTSDEN_1 + Enable RTSD interrupt + 0x1 + + + + + TXMPTYEN + Transmitter Empty Interrupt Enable + 0x6 + 1 + read-write + + + TXMPTYEN_0 + Disable the transmitter FIFO empty interrupt + 0 + + + TXMPTYEN_1 + Enable the transmitter FIFO empty interrupt + 0x1 + + + + + IREN + Infrared Interface Enable + 0x7 + 1 + read-write + + + IREN_0 + Disable the IR interface + 0 + + + IREN_1 + Enable the IR interface + 0x1 + + + + + RXDMAEN + Receive Ready DMA Enable + 0x8 + 1 + read-write + + + RXDMAEN_0 + Disable DMA request + 0 + + + RXDMAEN_1 + Enable DMA request + 0x1 + + + + + RRDYEN + Receiver Ready Interrupt Enable + 0x9 + 1 + read-write + + + RRDYEN_0 + Disables the RRDY interrupt + 0 + + + RRDYEN_1 + Enables the RRDY interrupt + 0x1 + + + + + ICD + Idle Condition Detect + 0xA + 2 + read-write + + + ICD_0 + Idle for more than 4 frames + 0 + + + ICD_1 + Idle for more than 8 frames + 0x1 + + + ICD_2 + Idle for more than 16 frames + 0x2 + + + ICD_3 + Idle for more than 32 frames + 0x3 + + + + + IDEN + Idle Condition Detected Interrupt Enable + 0xC + 1 + read-write + + + IDEN_0 + Disable the IDLE interrupt + 0 + + + IDEN_1 + Enable the IDLE interrupt + 0x1 + + + + + TRDYEN + Transmitter Ready Interrupt Enable + 0xD + 1 + read-write + + + TRDYEN_0 + Disable the transmitter ready interrupt + 0 + + + TRDYEN_1 + Enable the transmitter ready interrupt + 0x1 + + + + + ADBR + Automatic Detection of Baud Rate + 0xE + 1 + read-write + + + ADBR_0 + Disable automatic detection of baud rate + 0 + + + ADBR_1 + Enable automatic detection of baud rate + 0x1 + + + + + ADEN + Automatic Baud Rate Detection Interrupt Enable + 0xF + 1 + read-write + + + ADEN_0 + Disable the automatic baud rate detection interrupt + 0 + + + ADEN_1 + Enable the automatic baud rate detection interrupt + 0x1 + + + + + + + UCR2 + UART Control Register 2 + 0x84 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + SRST + Software Reset + 0 + 1 + read-write + + + SRST_0 + Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. + 0 + + + SRST_1 + No reset + 0x1 + + + + + RXEN + Receiver Enable + 0x1 + 1 + read-write + + + RXEN_0 + Disable the receiver + 0 + + + RXEN_1 + Enable the receiver + 0x1 + + + + + TXEN + Transmitter Enable + 0x2 + 1 + read-write + + + TXEN_0 + Disable the transmitter + 0 + + + TXEN_1 + Enable the transmitter + 0x1 + + + + + ATEN + Aging Timer Enable. This bit is used to enable the aging timer interrupt (triggered with AGTIM) + 0x3 + 1 + read-write + + + ATEN_0 + AGTIM interrupt disabled + 0 + + + ATEN_1 + AGTIM interrupt enabled + 0x1 + + + + + RTSEN + Request to Send Interrupt Enable + 0x4 + 1 + read-write + + + RTSEN_0 + Disable request to send interrupt + 0 + + + RTSEN_1 + Enable request to send interrupt + 0x1 + + + + + WS + Word Size + 0x5 + 1 + read-write + + + WS_0 + 7-bit transmit and receive character length (not including START, STOP or PARITY bits) + 0 + + + WS_1 + 8-bit transmit and receive character length (not including START, STOP or PARITY bits) + 0x1 + + + + + STPB + Stop + 0x6 + 1 + read-write + + + STPB_0 + The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + 0 + + + STPB_1 + The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + 0x1 + + + + + PROE + Parity Odd/Even + 0x7 + 1 + read-write + + + PROE_0 + Even parity + 0 + + + PROE_1 + Odd parity + 0x1 + + + + + PREN + Parity Enable + 0x8 + 1 + read-write + + + PREN_0 + Disable parity generator and checker + 0 + + + PREN_1 + Enable parity generator and checker + 0x1 + + + + + RTEC + Request to Send Edge Control + 0x9 + 2 + read-write + + + RTEC_0 + Trigger interrupt on a rising edge + 0 + + + RTEC_1 + Trigger interrupt on a falling edge + 0x1 + + + + + ESCEN + Escape Enable. Enables/Disables the escape sequence detection logic. + 0xB + 1 + read-write + + + ESCEN_0 + Disable escape sequence detection + 0 + + + ESCEN_1 + Enable escape sequence detection + 0x1 + + + + + CTS + Clear to Send + 0xC + 1 + read-write + + + CTS_0 + The CTS_B pin is high (inactive) + 0 + + + CTS_1 + The CTS_B pin is low (active) + 0x1 + + + + + CTSC + CTS Pin Control + 0xD + 1 + read-write + + + CTSC_0 + The CTS_B pin is controlled by the CTS bit + 0 + + + CTSC_1 + The CTS_B pin is controlled by the receiver + 0x1 + + + + + IRTS + Ignore RTS Pin + 0xE + 1 + read-write + + + IRTS_0 + Transmit only when the RTS pin is asserted + 0 + + + IRTS_1 + Ignore the RTS pin + 0x1 + + + + + ESCI + Escape Sequence Interrupt Enable. Enables/Disables the ESCF bit to generate an interrupt. + 0xF + 1 + read-write + + + ESCI_0 + Disable the escape sequence interrupt + 0 + + + ESCI_1 + Enable the escape sequence interrupt + 0x1 + + + + + + + UCR3 + UART Control Register 3 + 0x88 + 32 + read-write + 0x700 + 0xFFFFFFFF + + + ACIEN + Autobaud Counter Interrupt Enable + 0 + 1 + read-write + + + ACIEN_0 + ACST interrupt disabled + 0 + + + ACIEN_1 + ACST interrupt enabled + 0x1 + + + + + INVT + Invert TXD output in RS-232/RS-485 mode, set TXD active level in IrDA mode + 0x1 + 1 + read-write + + + INVT_0 + TXD is not inverted + 0 + + + INVT_1 + TXD is inverted + 0x1 + + + + + RXDMUXSEL + RXD Muxed Input Selected + 0x2 + 1 + read-write + + + DTRDEN + Data Terminal Ready Delta Enable + 0x3 + 1 + read-write + + + DTRDEN_0 + Disable DTRD interrupt + 0 + + + DTRDEN_1 + Enable DTRD interrupt + 0x1 + + + + + AWAKEN + Asynchronous WAKE Interrupt Enable + 0x4 + 1 + read-write + + + AWAKEN_0 + Disable the AWAKE interrupt + 0 + + + AWAKEN_1 + Enable the AWAKE interrupt + 0x1 + + + + + AIRINTEN + Asynchronous IR WAKE Interrupt Enable + 0x5 + 1 + read-write + + + AIRINTEN_0 + Disable the AIRINT interrupt + 0 + + + AIRINTEN_1 + Enable the AIRINT interrupt + 0x1 + + + + + RXDSEN + Receive Status Interrupt Enable + 0x6 + 1 + read-write + + + RXDSEN_0 + Disable the RXDS interrupt + 0 + + + RXDSEN_1 + Enable the RXDS interrupt + 0x1 + + + + + ADNIMP + Autobaud Detection Not Improved- + 0x7 + 1 + read-write + + + ADNIMP_0 + Autobaud detection new features selected + 0 + + + ADNIMP_1 + Keep old autobaud detection mechanism + 0x1 + + + + + RI + Ring Indicator + 0x8 + 1 + read-write + + + RI_0 + RI_B pin is logic zero (DCE mode) + 0 + + + RI_1 + RI_B pin is logic one (DCE mode) + 0x1 + + + + + DCD + Data Carrier Detect + 0x9 + 1 + read-write + + + DCD_0 + DCD_B pin is logic zero (DCE mode) + 0 + + + DCD_1 + DCD_B pin is logic one (DCE mode) + 0x1 + + + + + DSR + Data Set Ready + 0xA + 1 + read-write + + + DSR_0 + DSR/ DTR pin is logic zero + 0 + + + DSR_1 + DSR/ DTR pin is logic one + 0x1 + + + + + FRAERREN + Frame Error Interrupt Enable + 0xB + 1 + read-write + + + FRAERREN_0 + Disable the frame error interrupt + 0 + + + FRAERREN_1 + Enable the frame error interrupt + 0x1 + + + + + PARERREN + Parity Error Interrupt Enable + 0xC + 1 + read-write + + + PARERREN_0 + Disable the parity error interrupt + 0 + + + PARERREN_1 + Enable the parity error interrupt + 0x1 + + + + + DTREN + Data Terminal Ready Interrupt Enable + 0xD + 1 + read-write + + + DTREN_0 + Data Terminal Ready Interrupt Disabled + 0 + + + DTREN_1 + Data Terminal Ready Interrupt Enabled + 0x1 + + + + + DPEC + DTR/DSR Interrupt Edge Control + 0xE + 2 + read-write + + + DPEC_0 + interrupt generated on rising edge + 0 + + + DPEC_1 + interrupt generated on falling edge + 0x1 + + + + + + + UCR4 + UART Control Register 4 + 0x8C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DREN + Receive Data Ready Interrupt Enable. Enables/Disables the RDR bit to generate an interrupt. + 0 + 1 + read-write + + + DREN_0 + Disable RDR interrupt + 0 + + + DREN_1 + Enable RDR interrupt + 0x1 + + + + + OREN + Receiver Overrun Interrupt Enable. Enables/Disables the ORE bit to generate an interrupt. + 0x1 + 1 + read-write + + + OREN_0 + Disable ORE interrupt + 0 + + + OREN_1 + Enable ORE interrupt + 0x1 + + + + + BKEN + BREAK Condition Detected Interrupt Enable. Enables/Disables the BRCD bit to generate an interrupt. + 0x2 + 1 + read-write + + + BKEN_0 + Disable the BRCD interrupt + 0 + + + BKEN_1 + Enable the BRCD interrupt + 0x1 + + + + + TCEN + Transmit Complete Interrupt Enable + 0x3 + 1 + read-write + + + TCEN_0 + Disable TXDC interrupt + 0 + + + TCEN_1 + Enable TXDC interrupt + 0x1 + + + + + LPBYP + Low Power Bypass. Allows to bypass the low power new features in UART. To use during debug phase. + 0x4 + 1 + read-write + + + LPBYP_0 + Low power features enabled + 0 + + + LPBYP_1 + Low power features disabled + 0x1 + + + + + IRSC + IR Special Case + 0x5 + 1 + read-write + + + IRSC_0 + The vote logic uses the sampling clock (16x baud rate) for normal operation + 0 + + + IRSC_1 + The vote logic uses the UART reference clock + 0x1 + + + + + IDDMAEN + DMA IDLE Condition Detected Interrupt Enable Enables/Disables the receive DMA request dma_req_rx for the IDLE interrupt (triggered with IDLE flag in USR2[12]) + 0x6 + 1 + read-write + + + IDDMAEN_0 + DMA IDLE interrupt disabled + 0 + + + IDDMAEN_1 + DMA IDLE interrupt enabled + 0x1 + + + + + WKEN + WAKE Interrupt Enable + 0x7 + 1 + read-write + + + WKEN_0 + Disable the WAKE interrupt + 0 + + + WKEN_1 + Enable the WAKE interrupt + 0x1 + + + + + ENIRI + Serial Infrared Interrupt Enable. Enables/Disables the serial infrared interrupt. + 0x8 + 1 + read-write + + + ENIRI_0 + Serial infrared Interrupt disabled + 0 + + + ENIRI_1 + Serial infrared Interrupt enabled + 0x1 + + + + + INVR + Invert RXD input in RS-232/RS-485 Mode, determine RXD input logic level being sampled in In IrDA mode + 0x9 + 1 + read-write + + + INVR_0 + RXD input is not inverted + 0 + + + INVR_1 + RXD input is inverted + 0x1 + + + + + CTSTL + CTS Trigger Level + 0xA + 6 + read-write + + + CTSTL_0 + 0 characters received + 0 + + + CTSTL_1 + 1 characters in the RxFIFO + 0x1 + + + CTSTL_32 + 32 characters in the RxFIFO (maximum) + 0x20 + + + + + + + UFCR + UART FIFO Control Register + 0x90 + 32 + read-write + 0x801 + 0xFFFFFFFF + + + RXTL + Receiver Trigger Level + 0 + 6 + read-write + + + RXTL_0 + 0 characters received + 0 + + + RXTL_1 + RxFIFO has 1 character + 0x1 + + + RXTL_31 + RxFIFO has 31 characters + 0x1F + + + RXTL_32 + RxFIFO has 32 characters (maximum) + 0x20 + + + + + DCEDTE + DCE/DTE mode select + 0x6 + 1 + read-write + + + DCEDTE_0 + DCE mode selected + 0 + + + DCEDTE_1 + DTE mode selected + 0x1 + + + + + RFDIV + Reference Frequency Divider + 0x7 + 3 + read-write + + + RFDIV_0 + Divide input clock by 6 + 0 + + + RFDIV_1 + Divide input clock by 5 + 0x1 + + + RFDIV_2 + Divide input clock by 4 + 0x2 + + + RFDIV_3 + Divide input clock by 3 + 0x3 + + + RFDIV_4 + Divide input clock by 2 + 0x4 + + + RFDIV_5 + Divide input clock by 1 + 0x5 + + + RFDIV_6 + Divide input clock by 7 + 0x6 + + + + + TXTL + Transmitter Trigger Level + 0xA + 6 + read-write + + + TXTL_2 + TxFIFO has 2 or fewer characters + 0x2 + + + TXTL_31 + TxFIFO has 31 or fewer characters + 0x1F + + + TXTL_32 + TxFIFO has 32 characters (maximum) + 0x20 + + + + + + + USR1 + UART Status Register 1 + 0x94 + 32 + read-write + 0x2040 + 0xFFFFFFFF + + + SAD + RS-485 Slave Address Detected Interrupt Flag + 0x3 + 1 + read-write + oneToClear + + + SAD_0 + No slave address detected + 0 + + + SAD_1 + Slave address detected + 0x1 + + + + + AWAKE + Asynchronous WAKE Interrupt Flag + 0x4 + 1 + read-write + oneToClear + + + AWAKE_0 + No falling edge was detected on the RXD Serial pin + 0 + + + AWAKE_1 + A falling edge was detected on the RXD Serial pin + 0x1 + + + + + AIRINT + Asynchronous IR WAKE Interrupt Flag + 0x5 + 1 + read-write + oneToClear + + + AIRINT_0 + No pulse was detected on the RXD IrDA pin + 0 + + + AIRINT_1 + A pulse was detected on the RXD IrDA pin + 0x1 + + + + + RXDS + Receiver IDLE Interrupt Flag + 0x6 + 1 + read-only + + + RXDS_0 + Receive in progress + 0 + + + RXDS_1 + Receiver is IDLE + 0x1 + + + + + DTRD + DTR Delta + 0x7 + 1 + read-write + oneToClear + + + DTRD_0 + DTR_B (DCE) or DSR_B (DTE) pin did not change state since last cleared + 0 + + + DTRD_1 + DTR_B (DCE) or DSR_B (DTE) pin changed state (write 1 to clear) + 0x1 + + + + + AGTIM + Ageing Timer Interrupt Flag + 0x8 + 1 + read-write + oneToClear + + + AGTIM_0 + AGTIM is not active + 0 + + + AGTIM_1 + AGTIM is active (write 1 to clear) + 0x1 + + + + + RRDY + Receiver Ready Interrupt / DMA Flag + 0x9 + 1 + read-only + + + RRDY_0 + No character ready + 0 + + + RRDY_1 + Character(s) ready (interrupt posted) + 0x1 + + + + + FRAMERR + Frame Error Interrupt Flag + 0xA + 1 + read-write + oneToClear + + + FRAMERR_0 + No frame error detected + 0 + + + FRAMERR_1 + Frame error detected (write 1 to clear) + 0x1 + + + + + ESCF + Escape Sequence Interrupt Flag + 0xB + 1 + read-write + oneToClear + + + ESCF_0 + No escape sequence detected + 0 + + + ESCF_1 + Escape sequence detected (write 1 to clear). + 0x1 + + + + + RTSD + RTS Delta + 0xC + 1 + read-write + oneToClear + + + RTSD_0 + RTS_B pin did not change state since last cleared + 0 + + + RTSD_1 + RTS_B pin changed state (write 1 to clear) + 0x1 + + + + + TRDY + Transmitter Ready Interrupt / DMA Flag + 0xD + 1 + read-only + + + TRDY_0 + The transmitter does not require data + 0 + + + TRDY_1 + The transmitter requires data (interrupt posted) + 0x1 + + + + + RTSS + RTS_B Pin Status + 0xE + 1 + read-only + + + RTSS_0 + The RTS_B module input is high (inactive) + 0 + + + RTSS_1 + The RTS_B module input is low (active) + 0x1 + + + + + PARITYERR + Parity Error Interrupt Flag + 0xF + 1 + read-write + oneToClear + + + PARITYERR_0 + No parity error detected + 0 + + + PARITYERR_1 + Parity error detected (write 1 to clear) + 0x1 + + + + + + + USR2 + UART Status Register 2 + 0x98 + 32 + read-write + 0x4028 + 0xFFFFFFFF + + + RDR + Receive Data Ready-Indicates that at least 1 character is received and written to the RxFIFO + 0 + 1 + read-only + + + RDR_0 + No receive data ready + 0 + + + RDR_1 + Receive data ready + 0x1 + + + + + ORE + Overrun Error + 0x1 + 1 + read-write + oneToClear + + + ORE_0 + No overrun error + 0 + + + ORE_1 + Overrun error (write 1 to clear) + 0x1 + + + + + BRCD + BREAK Condition Detected + 0x2 + 1 + read-write + oneToClear + + + BRCD_0 + No BREAK condition was detected + 0 + + + BRCD_1 + A BREAK condition was detected (write 1 to clear) + 0x1 + + + + + TXDC + Transmitter Complete + 0x3 + 1 + read-only + + + TXDC_0 + Transmit is incomplete + 0 + + + TXDC_1 + Transmit is complete + 0x1 + + + + + RTSF + RTS Edge Triggered Interrupt Flag + 0x4 + 1 + read-write + oneToClear + + + RTSF_0 + Programmed edge not detected on RTS_B + 0 + + + RTSF_1 + Programmed edge detected on RTS_B (write 1 to clear) + 0x1 + + + + + DCDIN + Data Carrier Detect Input + 0x5 + 1 + read-only + + + DCDIN_0 + Carrier signal Detected + 0 + + + DCDIN_1 + No Carrier signal Detected + 0x1 + + + + + DCDDELT + Data Carrier Detect Delta + 0x6 + 1 + read-write + oneToClear + + + DCDDELT_0 + Data Carrier Detect input has not changed state + 0 + + + DCDDELT_1 + Data Carrier Detect input has changed state (write 1 to clear) + 0x1 + + + + + WAKE + Wake + 0x7 + 1 + read-write + oneToClear + + + WAKE_0 + start bit not detected + 0 + + + WAKE_1 + start bit detected (write 1 to clear) + 0x1 + + + + + IRINT + Serial Infrared Interrupt Flag + 0x8 + 1 + read-write + oneToClear + + + IRINT_0 + no edge detected + 0 + + + IRINT_1 + valid edge detected (write 1 to clear) + 0x1 + + + + + RIIN + Ring Indicator Input + 0x9 + 1 + read-only + + + RIIN_0 + Ring Detected + 0 + + + RIIN_1 + No Ring Detected + 0x1 + + + + + RIDELT + Ring Indicator Delta + 0xA + 1 + read-write + oneToClear + + + RIDELT_0 + Ring Indicator input has not changed state + 0 + + + RIDELT_1 + Ring Indicator input has changed state (write 1 to clear) + 0x1 + + + + + ACST + Autobaud Counter Stopped + 0xB + 1 + read-write + oneToClear + + + ACST_0 + Measurement of bit length not finished (in autobaud) + 0 + + + ACST_1 + Measurement of bit length finished (in autobaud). (write 1 to clear) + 0x1 + + + + + IDLE + Idle Condition + 0xC + 1 + read-write + oneToClear + + + IDLE_0 + No idle condition detected + 0 + + + IDLE_1 + Idle condition detected (write 1 to clear) + 0x1 + + + + + DTRF + DTR edge triggered interrupt flag + 0xD + 1 + read-write + oneToClear + + + DTRF_0 + Programmed edge not detected on DTR/DSR + 0 + + + DTRF_1 + Programmed edge detected on DTR/DSR (write 1 to clear) + 0x1 + + + + + TXFE + Transmit Buffer FIFO Empty + 0xE + 1 + read-only + + + TXFE_0 + The transmit buffer (TxFIFO) is not empty + 0 + + + TXFE_1 + The transmit buffer (TxFIFO) is empty + 0x1 + + + + + ADET + Automatic Baud Rate Detect Complete + 0xF + 1 + read-write + oneToClear + + + ADET_0 + ASCII "A" or "a" was not received + 0 + + + ADET_1 + ASCII "A" or "a" was received (write 1 to clear) + 0x1 + + + + + + + UESC + UART Escape Character Register + 0x9C + 32 + read-write + 0x2B + 0xFFFFFFFF + + + ESC_CHAR + UART Escape Character + 0 + 8 + read-write + + + + + UTIM + UART Escape Timer Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIM + UART Escape Timer + 0 + 12 + read-write + + + + + UBIR + UART BRM Incremental Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Incremental Numerator + 0 + 16 + read-write + + + + + UBMR + UART BRM Modulator Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MOD + Modulator Denominator + 0 + 16 + read-write + + + + + UBRC + UART Baud Rate Count Register + 0xAC + 32 + read-only + 0x4 + 0xFFFFFFFF + + + BCNT + Baud Rate Count Register + 0 + 16 + read-only + + + + + ONEMS + UART One Millisecond Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ONEMS + One Millisecond Register + 0 + 24 + read-write + + + + + UTS + UART Test Register + 0xB4 + 32 + read-write + 0x60 + 0xFFFFFFFF + + + SOFTRST + Software Reset. Indicates the status of the software reset (SRST_B bit of UCR2). + 0 + 1 + read-write + + + SOFTRST_0 + Software reset inactive + 0 + + + SOFTRST_1 + Software reset active + 0x1 + + + + + RXFULL + RxFIFO FULL. Indicates the RxFIFO is full. + 0x3 + 1 + read-write + + + RXFULL_0 + The RxFIFO is not full + 0 + + + RXFULL_1 + The RxFIFO is full + 0x1 + + + + + TXFULL + TxFIFO FULL. Indicates the TxFIFO is full. + 0x4 + 1 + read-write + + + TXFULL_0 + The TxFIFO is not full + 0 + + + TXFULL_1 + The TxFIFO is full + 0x1 + + + + + RXEMPTY + RxFIFO Empty. Indicates the RxFIFO is empty. + 0x5 + 1 + read-write + + + RXEMPTY_0 + The RxFIFO is not empty + 0 + + + RXEMPTY_1 + The RxFIFO is empty + 0x1 + + + + + TXEMPTY + TxFIFO Empty. Indicates that the TxFIFO is empty. + 0x6 + 1 + read-write + + + TXEMPTY_0 + The TxFIFO is not empty + 0 + + + TXEMPTY_1 + The TxFIFO is empty + 0x1 + + + + + RXDBG + RX_fifo_debug_mode. This bit controls the operation of the RX fifo read counter when in debug mode. + 0x9 + 1 + read-write + + + RXDBG_0 + rx fifo read pointer does not increment + 0 + + + RXDBG_1 + rx_fifo read pointer increments as normal + 0x1 + + + + + LOOPIR + Loop TX and RX for IR Test (LOOPIR) + 0xA + 1 + read-write + + + LOOPIR_0 + No IR loop + 0 + + + LOOPIR_1 + Connect IR transmitter to IR receiver + 0x1 + + + + + DBGEN + debug_enable_B. This bit controls whether to respond to the debug_req input signal. + 0xB + 1 + read-write + + + DBGEN_0 + UART will go into debug mode when debug_req is HIGH + 0 + + + DBGEN_1 + UART will not go into debug mode even if debug_req is HIGH + 0x1 + + + + + LOOP + Loop TX and RX for Test + 0xC + 1 + read-write + + + LOOP_0 + Normal receiver operation + 0 + + + LOOP_1 + Internally connect the transmitter output to the receiver input + 0x1 + + + + + FRCPERR + Force Parity Error + 0xD + 1 + read-write + + + FRCPERR_0 + Generate normal parity + 0 + + + FRCPERR_1 + Generate inverted parity (error) + 0x1 + + + + + + + UMCR + UART RS-485 Mode Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MDEN + 9-bit data or Multidrop Mode (RS-485) Enable. + 0 + 1 + read-write + + + MDEN_0 + Normal RS-232 or IrDA mode, see for detail. + 0 + + + MDEN_1 + Enable RS-485 mode, see for detail + 0x1 + + + + + SLAM + RS-485 Slave Address Detect Mode Selection. + 0x1 + 1 + read-write + + + SLAM_0 + Select Normal Address Detect mode + 0 + + + SLAM_1 + Select Automatic Address Detect mode + 0x1 + + + + + TXB8 + Transmit RS-485 bit 8 (the ninth bit or 9th bit) + 0x2 + 1 + read-write + + + TXB8_0 + 0 will be transmitted as the RS485 9th data bit + 0 + + + TXB8_1 + 1 will be transmitted as the RS485 9th data bit + 0x1 + + + + + SADEN + RS-485 Slave Address Detected Interrupt Enable. + 0x3 + 1 + read-write + + + SADEN_0 + Disable RS-485 Slave Address Detected Interrupt + 0 + + + SADEN_1 + Enable RS-485 Slave Address Detected Interrupt + 0x1 + + + + + SLADDR + RS-485 Slave Address Character + 0x8 + 8 + read-write + + + + + + + UART7 + UARTv2 + UART + UART7_ + 0x2018000 + + 0 + 0xBC + registers + + + UART7 + 71 + + + + UART2 + UARTv2 + UART + UART2_ + 0x21E8000 + + 0 + 0xBC + registers + + + UART2 + 59 + + + + UART3 + UARTv2 + UART + UART3_ + 0x21EC000 + + 0 + 0xBC + registers + + + UART3 + 60 + + + + UART4 + UARTv2 + UART + UART4_ + 0x21F0000 + + 0 + 0xBC + registers + + + UART4 + 61 + + + + UART5 + UARTv2 + UART + UART5_ + 0x21F4000 + + 0 + 0xBC + registers + + + UART5 + 62 + + + + UART6 + UARTv2 + UART + UART6_ + 0x21FC000 + + 0 + 0xBC + registers + + + UART6 + 49 + + + + UART8 + UARTv2 + UART + UART8_ + 0x2288000 + + 0 + 0xBC + registers + + + UART8 + 72 + + + + ESAI + Enhanced Serial Audio Interface + ESAI + ESAI_ + 0x2024000 + + 0 + 0x100 + registers + + + ESAI + 83 + + + + ETDR + ESAI Transmit Data Register + 0 + 32 + write-only + 0 + 0xFFFFFFFF + + + ETDR + ESAI Transmit Data Register + 0 + 32 + write-only + + + + + ERDR + ESAI Receive Data Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERDR + ESAI Receive Data Register + 0 + 32 + read-only + + + + + ECR + ESAI Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ESAIEN + ESAI Enable + 0 + 1 + read-write + + + ESAIEN_0 + ESAI disabled. + 0 + + + ESAIEN_1 + ESAI enabled. + 0x1 + + + + + ERST + ESAI Reset. Reset the ESAI core logic (including configuration registers) but not the ESAI FIFOs. + 0x1 + 1 + read-write + + + ERST_0 + ESAI not reset. + 0 + + + ERST_1 + ESAI reset. + 0x1 + + + + + ERO + EXTAL Receiver Out. Drive the EXTAL input on the High Frequency Receiver Clock pin. + 0x10 + 1 + read-write + + + ERO_0 + HCKR pin has normal function. + 0 + + + ERO_1 + EXTAL driven onto HCKR pin. + 0x1 + + + + + ERI + EXTAL Receiver In + 0x11 + 1 + read-write + + + ERI_0 + HCKR pin has normal function. + 0 + + + ERI_1 + EXTAL muxed into HCKR input. + 0x1 + + + + + ETO + EXTAL Transmitter Out. Drive the EXTAL input on the High Frequency Transmitter Clock pin. + 0x12 + 1 + read-write + + + ETO_0 + HCKT pin has normal function. + 0 + + + ETO_1 + EXTAL driven onto HCKT pin. + 0x1 + + + + + ETI + EXTAL Transmitter In + 0x13 + 1 + read-write + + + ETI_0 + HCKT pin has normal function. + 0 + + + ETI_1 + EXTAL muxed into HCKT input. + 0x1 + + + + + + + ESR + ESAI Status Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + RD + Receive Data. + 0 + 1 + read-only + + + RD_0 + RD is not the highest priority active interrupt. + 0 + + + RD_1 + RD is the highest priority active interrupt. + 0x1 + + + + + RED + Receive Even Data. + 0x1 + 1 + read-only + + + RED_0 + RED is not the highest priority active interrupt. + 0 + + + RED_1 + RED is the highest priority active interrupt. + 0x1 + + + + + RDE + Receive Data Exception. + 0x2 + 1 + read-only + + + RDE_0 + RDE is not the highest priority active interrupt. + 0 + + + RDE_1 + RDE is the highest priority active interrupt. + 0x1 + + + + + RLS + Receive Last Slot + 0x3 + 1 + read-only + + + RLS_0 + RLS is not the highest priority active interrupt. + 0 + + + RLS_1 + RLS is the highest priority active interrupt. + 0x1 + + + + + TD + Transmit Data. + 0x4 + 1 + read-only + + + TD_0 + TD is not the highest priority active interrupt. + 0 + + + TD_1 + TD is the highest priority active interrupt. + 0x1 + + + + + TED + Transmit Even Data. + 0x5 + 1 + read-only + + + TED_0 + TED is not the highest priority active interrupt. + 0 + + + TED_1 + TED is the highest priority active interrupt. + 0x1 + + + + + TDE + Transmit Data Exception. + 0x6 + 1 + read-only + + + TDE_0 + TDE is not the highest priority active interrupt. + 0 + + + TDE_1 + TDE is the highest priority active interrupt. + 0x1 + + + + + TLS + Transmit Last Slot + 0x7 + 1 + read-only + + + TLS_0 + TLS is not the highest priority active interrupt. + 0 + + + TLS_1 + TLS is the highest priority active interrupt. + 0x1 + + + + + TFE + Transmit FIFO Empty + 0x8 + 1 + read-only + + + TFE_0 + Number of empty slots in Transmit FIFO less than Transmit FIFO watermark. + 0 + + + TFE_1 + Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark. + 0x1 + + + + + RFF + Receive FIFO Full + 0x9 + 1 + read-only + + + RFF_0 + Number of words in Receive FIFO less than Receive FIFO watermark. + 0 + + + RFF_1 + Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark. + 0x1 + + + + + TINIT + Transmit Initialization + 0xA + 1 + read-only + + + TINIT_0 + Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or Transmit Initialization is not enabled). + 0 + + + TINIT_1 + Transmitter has not finished initializing the Transmit Data Registers. + 0x1 + + + + + + + TFCR + Transmit FIFO Configuration Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFE + Transmit FIFO Enable. This bit enables the use of the Transmit FIFO. + 0 + 1 + read-write + + + TFE_0 + Transmit FIFO disabled. + 0 + + + TFE_1 + Transmit FIFO enabled. + 0x1 + + + + + TFR + Transmit FIFO Reset. This bit resets the Transmit FIFO pointers. + 0x1 + 1 + read-write + + + TFR_0 + Transmit FIFO not reset. + 0 + + + TFR_1 + Transmit FIFO reset. + 0x1 + + + + + TE0 + Transmitter #0 FIFO Enable + 0x2 + 1 + read-write + + + TE0_0 + Transmitter #0 is not using the Transmit FIFO. + 0 + + + TE0_1 + Transmitter #0 is using the Transmit FIFO. + 0x1 + + + + + TE1 + Transmitter #1 FIFO Enable + 0x3 + 1 + read-write + + + TE1_0 + Transmitter #1 is not using the Transmit FIFO. + 0 + + + TE1_1 + Transmitter #1 is using the Transmit FIFO. + 0x1 + + + + + TE2 + Transmitter #2 FIFO Enable + 0x4 + 1 + read-write + + + TE2_0 + Transmitter #2 is not using the Transmit FIFO. + 0 + + + TE2_1 + Transmitter #2 is using the Transmit FIFO. + 0x1 + + + + + TE3 + Transmitter #3 FIFO Enable + 0x5 + 1 + read-write + + + TE3_0 + Transmitter #3 is not using the Transmit FIFO. + 0 + + + TE3_1 + Transmitter #3 is using the Transmit FIFO. + 0x1 + + + + + TE4 + Transmitter #4 FIFO Enable + 0x6 + 1 + read-write + + + TE4_0 + Transmitter #4 is not using the Transmit FIFO. + 0 + + + TE4_1 + Transmitter #4 is using the Transmit FIFO. + 0x1 + + + + + TE5 + Transmitter #5 FIFO Enable + 0x7 + 1 + read-write + + + TE5_0 + Transmitter #5 is not using the Transmit FIFO. + 0 + + + TE5_1 + Transmitter #5 is using the Transmit FIFO. + 0x1 + + + + + TFWM + Transmit FIFO Watermark + 0x8 + 8 + read-write + + + TWA + Transmit Word Alignment + 0x10 + 3 + read-write + + + TWA_0 + MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register. + 0 + + + TWA_1 + MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register. + 0x1 + + + TWA_2 + MSB of data is bit 23. + 0x2 + + + TWA_3 + MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed. + 0x3 + + + TWA_4 + MSB of data is bit 15. Bottom 8 bits of transmit shift register are zeroed. + 0x4 + + + TWA_5 + MSB of data is bit 11. Bottom 12 bits of transmit shift register are zeroed. + 0x5 + + + TWA_6 + MSB of data is bit 7. Bottom 16 bits of transmit shift register are zeroed. + 0x6 + + + TWA_7 + MSB of data is bit 3. Bottom 20 bits of transmit shift register are zeroed. + 0x7 + + + + + TIEN + Transmitter Initialization Enable + 0x13 + 1 + read-write + + + TIEN_0 + Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software must manually initialize the Transmit Data Registers separately. + 0 + + + TIEN_1 + Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled. + 0x1 + + + + + TAENB + Tx FIFO Align Enable + 0x14 + 1 + read-write + + + TFIN + Tx FIFO Interrupt Enable + 0x15 + 1 + read-write + + + + + TFSR + Transmit FIFO Status Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + TFCNT + Transmit FIFO Counter. These bits indicate the number of data words stored in the Transmit FIFO. + 0 + 8 + read-only + + + NTFI + Next Transmitter FIFO In. Indicates which transmitter receives the next word written to the FIFO. + 0x8 + 3 + read-only + + + NTFI_0 + Transmitter #0 receives next word written to the Transmit FIFO. + 0 + + + NTFI_1 + Transmitter #1 receives next word written to the Transmit FIFO. + 0x1 + + + NTFI_2 + Transmitter #2 receives next word written to the Transmit FIFO. + 0x2 + + + NTFI_3 + Transmitter #3 receives next word written to the Transmit FIFO. + 0x3 + + + NTFI_4 + Transmitter #4 receives next word written to the Transmit FIFO. + 0x4 + + + NTFI_5 + Transmitter #5 receives next word written to the Transmit FIFO. + 0x5 + + + + + NTFO + Next Transmitter FIFO Out + 0xC + 3 + read-only + + + NTFO_0 + Transmitter #0 receives next word from the Transmit FIFO. + 0 + + + NTFO_1 + Transmitter #1 receives next word from the Transmit FIFO. + 0x1 + + + NTFO_2 + Transmitter #2 receives next word from the Transmit FIFO. + 0x2 + + + NTFO_3 + Transmitter #3 receives next word from the Transmit FIFO. + 0x3 + + + NTFO_4 + Transmitter #4 receives next word from the Transmit FIFO. + 0x4 + + + NTFO_5 + Transmitter #5 receives next word from the Transmit FIFO. + 0x5 + + + + + + + RFCR + Receive FIFO Configuration Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + RFE + Receive FIFO Enable. This bit enables the use of the Receive FIFO. + 0 + 1 + read-write + + + RFE_0 + Receive FIFO disabled. + 0 + + + RFE_1 + Receive FIFO enabled. + 0x1 + + + + + RFR + Receive FIFO Reset. This bit resets the Receive FIFO pointers. + 0x1 + 1 + read-write + + + RFR_0 + Receive FIFO not reset. + 0 + + + RFR_1 + Receive FIFO reset. + 0x1 + + + + + RE0 + Receiver #0 FIFO Enable + 0x2 + 1 + read-write + + + RE0_0 + Receiver #0 is not using the Receive FIFO. + 0 + + + RE0_1 + Receiver #0 is using the Receive FIFO. + 0x1 + + + + + RE1 + Receiver #1 FIFO Enable + 0x3 + 1 + read-write + + + RE1_0 + Receiver #1 is not using the Receive FIFO. + 0 + + + RE1_1 + Receiver #1 is using the Receive FIFO. + 0x1 + + + + + RE2 + Receiver #2 FIFO Enable + 0x4 + 1 + read-write + + + RE2_0 + Receiver #2 is not using the Receive FIFO. + 0 + + + RE2_1 + Receiver #2 is using the Receive FIFO. + 0x1 + + + + + RE3 + Receiver #3 FIFO Enable + 0x5 + 1 + read-write + + + RE3_0 + Receiver #3 is not using the Receive FIFO. + 0 + + + RE3_1 + Receiver #3 is using the Receive FIFO. + 0x1 + + + + + RFWM + Receive FIFO Watermark + 0x8 + 8 + read-write + + + RWA + Receive Word Alignment + 0x10 + 3 + read-write + + + RWA_0 + MSB of data is at bit 31. Data bits 7-0 are zeroed. + 0 + + + RWA_1 + MSB of data is at bit 27. Data bits 3-0 are zeroed. + 0x1 + + + RWA_2 + MSB of data is at bit 23. + 0x2 + + + RWA_3 + MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored. + 0x3 + + + RWA_4 + MSB of data is at bit 15. Data bits 7-0 from receive shift register are ignored. + 0x4 + + + RWA_5 + MSB of data is at bit 11. Data bits 11-0 from receive shift register are ignored. + 0x5 + + + RWA_6 + MSB of data is at bit 7. Data bits 15-0 from receive shift register are ignored. + 0x6 + + + RWA_7 + MSB of data is at bit 3. Data bits 19-0 from receive shift register are ignored. + 0x7 + + + + + REXT + Receive Extension + 0x13 + 1 + read-write + + + REXT_0 + Receive data is zero extended. + 0 + + + REXT_1 + Receive data is sign extended. + 0x1 + + + + + RAENB + Rx FIFO Align Enable + 0x14 + 1 + read-write + + + RFIN + Rx FIFO Interrupt Enable + 0x15 + 1 + read-write + + + + + RFSR + Receive FIFO Status Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RFCNT + Receive FIFO Counter. These bits indicate the number of data words stored in the Receive FIFO. + 0 + 8 + read-only + + + NRFO + Next Receiver FIFO Out. Indicates which receiver returns the top word of the Receive FIFO. + 0x8 + 2 + read-only + + + NRFO_0 + Receiver #0 returns next word from the Receive FIFO. + 0 + + + NRFO_1 + Receiver #1 returns next word from the Receive FIFO. + 0x1 + + + NRFO_2 + Receiver #2 returns next word from the Receive FIFO. + 0x2 + + + NRFO_3 + Receiver #3 returns next word from the Receive FIFO. + 0x3 + + + + + NRFI + Next Receiver FIFO In + 0xC + 2 + read-only + + + NRFI_0 + Receiver #0 returns next word to the Receive FIFO. + 0 + + + NRFI_1 + Receiver #1 returns next word to the Receive FIFO. + 0x1 + + + NRFI_2 + Receiver #2 returns next word to the Receive FIFO. + 0x2 + + + NRFI_3 + Receiver #3 returns next word to the Receive FIFO. + 0x3 + + + + + + + 6 + 0x4 + TX%s + Transmit Data Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXn + Stores the data to be transmitted and is automatically transferred to the transmit shift registers + 0 + 24 + write-only + + + + + TSR + ESAI Transmit Slot Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSR + The write-only Transmit Slot Register (ESAI_TSR) is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot + 0 + 24 + write-only + + + + + 4 + 0x4 + RX%s + Receive Data Register n + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RXn + Accept data from the receive shift registers when they become full See ESAI Receive Shift Registers + 0 + 24 + read-only + + + + + SAISR + Serial Audio Interface Status Register + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + IF0 + ESAI_SAISR Serial Input Flag 0 + 0 + 1 + read-only + + + IF1 + ESAI_SAISR Serial Inout Flag 1 + 0x1 + 1 + read-only + + + IF2 + ESAI_SAISR Serial Input Flag 2 + 0x2 + 1 + read-only + + + RFS + ESAI_SAISR Receive Frame Sync Flag + 0x6 + 1 + read-only + + + ROE + ESAI_SAISR Receive Overrun Error Flag + 0x7 + 1 + read-only + + + RDF + ESAI_SAISR Receive Data Register Full + 0x8 + 1 + read-only + + + REDF + ESAI_SAISR Receive Even-Data Register Full + 0x9 + 1 + read-only + + + RODF + ESAI_SAISR Receive Odd-Data Register Full + 0xA + 1 + read-only + + + TFS + ESAI_SAISR Transmit Frame Sync Flag + 0xD + 1 + read-only + + + TUE + ESAI_SAISR Transmit Underrun Error Flag + 0xE + 1 + read-only + + + TDE + ESAI_SAISR Transmit Data Register Empty + 0xF + 1 + read-only + + + TEDE + ESAI_SAISR Transmit Even-DataRegister Empty + 0x10 + 1 + read-only + + + TODFE + ESAI_SAISR Transmit Odd-Data Register Empty + 0x11 + 1 + read-only + + + + + SAICR + Serial Audio Interface Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF0 + ESAI_SAICR Serial Output Flag 0 + 0 + 1 + read-write + + + OF1 + ESAI_SAICR Serial Output Flag 1 + 0x1 + 1 + read-write + + + OF2 + ESAI_SAICR Serial Output Flag 2 + 0x2 + 1 + read-write + + + SYN + ESAI_SAICR Synchronous Mode Selection + 0x6 + 1 + read-write + + + TEBE + ESAI_SAICR Transmit External Buffer Enable + 0x7 + 1 + read-write + + + ALC + ESAI_SAICR Alignment Control + 0x8 + 1 + read-write + + + + + TCR + Transmit Control Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TE0 + ESAI_TCR ESAI Transmit 0 Enable + 0 + 1 + read-write + + + TE1 + ESAI_TCR ESAI Transmit 1 Enable + 0x1 + 1 + read-write + + + TE2 + ESAI_TCR ESAI Transmit 2 Enable + 0x2 + 1 + read-write + + + TE3 + ESAI_TCR ESAI Transmit 3 Enable + 0x3 + 1 + read-write + + + TE4 + ESAI_TCR ESAI Transmit 4 Enable + 0x4 + 1 + read-write + + + TE5 + ESAI_TCR ESAI Transmit 5 Enable + 0x5 + 1 + read-write + + + TSHFD + ESAI_TCR Transmit Shift Direction + 0x6 + 1 + read-write + + + TWA + ESAI_TCR Transmit Word Alignment Control + 0x7 + 1 + read-write + + + TMOD + ESAI_TCR Transmit Network Mode Control (TMOD1-TMOD0) + 0x8 + 2 + read-write + + + TSWS + ESAI_TCR Tx Slot and Word Length Select (TSWS4-TSWS0) + 0xA + 5 + read-write + + + TFSL + ESAI_TCR Transmit Frame Sync Length + 0xF + 1 + read-write + + + TFSR + ESAI_TCR Transmit Frame Sync Relative Timing + 0x10 + 1 + read-write + + + PADC + ESAI_TCR Transmit Zero Padding Control + 0x11 + 1 + read-write + + + TPR + ESAI_TCR Transmit Section Personal Reset + 0x13 + 1 + read-write + + + TEIE + ESAI_TCR Transmit Exception Interrupt Enable + 0x14 + 1 + read-write + + + TEDIE + ESAI_TCR Transmit Even Slot Data Interrupt Enable + 0x15 + 1 + read-write + + + TIE + ESAI_TCR Transmit Interrupt Enable + 0x16 + 1 + read-write + + + TLIE + ESAI_TCR Transmit Last Slot Interrupt Enable + 0x17 + 1 + read-write + + + + + TCCR + Transmit Clock Control Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPM + ESAI_TCCR Transmit Prescale Modulus Select + 0 + 8 + read-write + + + TPSR + ESAI_TCCR Transmit Prescaler Range + 0x8 + 1 + read-write + + + TDC + ESAI_TCCR Tx Frame Rate Divider Control + 0x9 + 5 + read-write + + + TFP + ESAI_TCCR Tx High Frequency Clock Divider + 0xE + 4 + read-write + + + TCKP + ESAI_TCCR Transmit Clock Polarity + 0x12 + 1 + read-write + + + TFSP + ESAI_TCCR Transmit Frame Sync Polarity + 0x13 + 1 + read-write + + + THCKP + ESAI_TCCR Transmit High Frequency Clock Polarity The Transmitter High Frequency Clock Polarity (THCKP) bit controls the polarity of the HCKT + 0x14 + 1 + read-write + + + TCKD + ESAI_TCCR Transmit Clock Source Direction + 0x15 + 1 + read-write + + + TFSD + ESAI_TCCR Transmit Frame Sync Signal Direction + 0x16 + 1 + read-write + + + THCKD + ESAI_TCCR Transmit High Frequency Clock Direction + 0x17 + 1 + read-write + + + + + RCR + Receive Control Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + RE0 + ESAI_RCR ESAI Receiver 0 Enable + 0 + 1 + read-write + + + RE1 + ESAI_RCR ESAI Receiver 1 Enable + 0x1 + 1 + read-write + + + RE2 + ESAI_RCR ESAI Receiver 2 Enable + 0x2 + 1 + read-write + + + RE3 + ESAI_RCR ESAI Receiver 3 Enable + 0x3 + 1 + read-write + + + RSHFD + ESAI_RCR Receiver Shift Direction + 0x6 + 1 + read-write + + + RWA + ESAI_RCR Receiver Word Alignment Control + 0x7 + 1 + read-write + + + RMOD + ESAI_RCR Receiver Network Mode Control + 0x8 + 2 + read-write + + + RSWS + ESAI_RCR Receiver Slot and Word Select + 0xA + 5 + read-write + + + RFSL + ESAI_RCR Receiver Frame Sync Length + 0xF + 1 + read-write + + + RFSR + ESAI_RCR Receiver Frame Sync Relative Timing + 0x10 + 1 + read-write + + + RPR + ESAI_RCR Receiver Section Personal Reset + 0x13 + 1 + read-write + + + REIE + ESAI_RCR Receive Exception Interrupt Enable + 0x14 + 1 + read-write + + + REDIE + ESAI_RCR Receive Even Slot Data Interrupt Enable + 0x15 + 1 + read-write + + + RIE + ESAI_RCR Receive Interrupt Enable + 0x16 + 1 + read-write + + + RLIE + ESAI_RCR Receive Last Slot Interrupt Enable + 0x17 + 1 + read-write + + + + + RCCR + Receive Clock Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RPM + ESAI_RCCR Receiver Prescale Modulus Select + 0 + 8 + read-write + + + RPSR + ESAI_RCCR Receiver Prescaler Range + 0x8 + 1 + read-write + + + RDC + ESAI_RCCR Rx Frame Rate Divider Control + 0x9 + 5 + read-write + + + RFP + ESAI_RCCR Rx High Frequency Clock Divider + 0xE + 4 + read-write + + + RCKP + The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in + 0x12 + 1 + read-write + + + RFSP + ESAI_RCCR Receiver Frame Sync Polarity + 0x13 + 1 + read-write + + + RHCKP + ESAI_RCCR Receiver High Frequency Clock Polarity + 0x14 + 1 + read-write + + + RCKD + ESAI_RCCR Receiver Clock Source Direction + 0x15 + 1 + read-write + + + RFSD + ESAI_RCCR Receiver Frame Sync Signal Direction + 0x16 + 1 + read-write + + + RHCKD + ESAI_RCCR Receiver High Frequency Clock Direction + 0x17 + 1 + read-write + + + + + TSMA + Transmit Slot Mask Register A + 0xE4 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + TS + Lower 16 bits of TS + 0 + 16 + read-write + + + + + TSMB + Transmit Slot Mask Register B + 0xE8 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + TS + When bit number N in ESAI_TSMB is cleared, all the transmit data pins of the enabled transmitters are tri-stated during transmit time slot number N + 0 + 16 + read-write + + + + + RSMA + Receive Slot Mask Register A + 0xEC + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + RS + When bit number N in the ESAI_RSMA register is cleared, the data from the enabled receivers input pins are shifted into their receive shift registers during slot number N + 0 + 16 + read-write + + + + + RSMB + Receive Slot Mask Register B + 0xF0 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + RS + When bit number N in the ESAI_RSMB register is cleared, the data from the enabled receivers input pins are shifted into their receive shift registers during slot number N + 0 + 16 + read-write + + + + + PRRC + Port C Direction Register + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDC + See . + 0 + 12 + read-write + + + + + PCRC + Port C Control Register + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + PC + See . + 0 + 12 + read-write + + + + + + + I2S1 + Inter-IC Sound / Synchronous Audio Interface + I2S + I2S1_ + 0x2028000 + I2S + + 0 + 0xE4 + registers + + + SAI1 + 129 + + + + TCSR + SAI Transmit Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 0x1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 0x8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 0x9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 0xA + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 0xB + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 0xC + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 0x10 + 1 + read-only + + + FRF_0 + Transmit FIFO watermark has not been reached. + 0 + + + FRF_1 + Transmit FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 0x11 + 1 + read-only + + + FWF_0 + No enabled transmit FIFO is empty. + 0 + + + FWF_1 + Enabled transmit FIFO is empty. + 0x1 + + + + + FEF + FIFO Error Flag + 0x12 + 1 + read-write + oneToClear + + + FEF_0 + Transmit underrun not detected. + 0 + + + FEF_1 + Transmit underrun detected. + 0x1 + + + + + SEF + Sync Error Flag + 0x13 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 0x14 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 0x18 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 0x19 + 1 + write-only + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 0x1C + 1 + read-write + + + BCE_0 + Transmit bit clock is disabled. + 0 + + + BCE_1 + Transmit bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 0x1D + 1 + read-write + + + DBGE_0 + Transmitter is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Transmitter is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 0x1E + 1 + read-write + + + STOPE_0 + Transmitter disabled in Stop mode. + 0 + + + STOPE_1 + Transmitter enabled in Stop mode. + 0x1 + + + + + TE + Transmitter Enable + 0x1F + 1 + read-write + + + TE_0 + Transmitter is disabled. + 0 + + + TE_1 + Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + TCR1 + SAI Transmit Configuration 1 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFW + Transmit FIFO Watermark + 0 + 5 + read-write + + + + + TCR2 + SAI Transmit Configuration 2 Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 0x18 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 0x19 + 1 + read-write + + + BCP_0 + Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 0x1A + 2 + read-write + + + MSEL_0 + Master Clock (MCLK) 1 option selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 0x1C + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 0x1D + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 0x1E + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with receiver. + 0x1 + + + + + + + TCR3 + SAI Transmit Configuration 3 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + TCE + Transmit Channel Enable + 0x10 + 1 + read-write + + + TCE_0 + Transmit data channel N is disabled. + 0 + + + TCE_1 + Transmit data channel N is enabled. + 0x1 + + + + + + + TCR4 + SAI Transmit Configuration 4 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 0x1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + FSE + Frame Sync Early + 0x3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 0x4 + 1 + read-write + + + MF_0 + LSB is transmitted first. + 0 + + + MF_1 + MSB is transmitted first. + 0x1 + + + + + SYWD + Sync Width + 0x8 + 5 + read-write + + + FRSZ + Frame size + 0x10 + 5 + read-write + + + + + TCR5 + SAI Transmit Configuration 5 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 0x8 + 5 + read-write + + + W0W + Word 0 Width + 0x10 + 5 + read-write + + + WNW + Word N Width + 0x18 + 5 + read-write + + + + + TDR + SAI Transmit Data Register + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + TDR + Transmit Data Register + 0 + 32 + write-only + + + + + TFR + SAI Transmit FIFO Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 0x10 + 6 + read-only + + + + + TMR + SAI Transmit Mask Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TWM + Transmit Word Mask + 0 + 32 + read-write + + + TWM_0 + Word N is enabled. + 0 + + + TWM_1 + Word N is masked. The transmit data pins are tri-stated when masked. + 0x1 + + + + + + + RCSR + SAI Receive Control Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 0x1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 0x8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 0x9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 0xA + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 0xB + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 0xC + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 0x10 + 1 + read-only + + + FRF_0 + Receive FIFO watermark not reached. + 0 + + + FRF_1 + Receive FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 0x11 + 1 + read-only + + + FWF_0 + No enabled receive FIFO is full. + 0 + + + FWF_1 + Enabled receive FIFO is full. + 0x1 + + + + + FEF + FIFO Error Flag + 0x12 + 1 + read-write + oneToClear + + + FEF_0 + Receive overflow not detected. + 0 + + + FEF_1 + Receive overflow detected. + 0x1 + + + + + SEF + Sync Error Flag + 0x13 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 0x14 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 0x18 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 0x19 + 1 + write-only + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 0x1C + 1 + read-write + + + BCE_0 + Receive bit clock is disabled. + 0 + + + BCE_1 + Receive bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 0x1D + 1 + read-write + + + DBGE_0 + Receiver is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Receiver is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 0x1E + 1 + read-write + + + STOPE_0 + Receiver disabled in Stop mode. + 0 + + + STOPE_1 + Receiver enabled in Stop mode. + 0x1 + + + + + RE + Receiver Enable + 0x1F + 1 + read-write + + + RE_0 + Receiver is disabled. + 0 + + + RE_1 + Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + RCR1 + SAI Receive Configuration 1 Register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + RFW + Receive FIFO Watermark + 0 + 5 + read-write + + + + + RCR2 + SAI Receive Configuration 2 Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 0x18 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 0x19 + 1 + read-write + + + BCP_0 + Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 0x1A + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 0x1C + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 0x1D + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 0x1E + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with transmitter. + 0x1 + + + + + + + RCR3 + SAI Receive Configuration 3 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + RCE + Receive Channel Enable + 0x10 + 1 + read-write + + + RCE_0 + Receive data channel N is disabled. + 0 + + + RCE_1 + Receive data channel N is enabled. + 0x1 + + + + + + + RCR4 + SAI Receive Configuration 4 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame Sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame Sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 0x1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + FSE + Frame Sync Early + 0x3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 0x4 + 1 + read-write + + + MF_0 + LSB is received first. + 0 + + + MF_1 + MSB is received first. + 0x1 + + + + + SYWD + Sync Width + 0x8 + 5 + read-write + + + FRSZ + Frame Size + 0x10 + 5 + read-write + + + + + RCR5 + SAI Receive Configuration 5 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 0x8 + 5 + read-write + + + W0W + Word 0 Width + 0x10 + 5 + read-write + + + WNW + Word N Width + 0x18 + 5 + read-write + + + + + RDR + SAI Receive Data Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDR + Receive Data Register + 0 + 32 + read-only + + + + + RFR + SAI Receive FIFO Register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 0x10 + 6 + read-only + + + + + RMR + SAI Receive Mask Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RWM + Receive Word Mask + 0 + 32 + read-write + + + RWM_0 + Word N is enabled. + 0 + + + RWM_1 + Word N is masked. + 0x1 + + + + + + + + + I2S2 + Inter-IC Sound / Synchronous Audio Interface + I2S + I2S2_ + 0x202C000 + + 0 + 0xE4 + registers + + + SAI2 + 130 + + + + I2S3 + Inter-IC Sound / Synchronous Audio Interface + I2S + I2S3_ + 0x2030000 + + 0 + 0xE4 + registers + + + SAI3_RX + 56 + + + SAI3_TX + 57 + + + + ASRC + ASRC Registers + ASRC + ASRC_ + 0x2034000 + + 0 + 0xCC + registers + + + ASRC + 82 + + + + ASRCTR + ASRC Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASRCEN + ASRC Enable Enable the operation of ASRC. + 0 + 1 + read-write + + + ASREA + ASRC Enable A Enable the operation of the conversion A of ASRC + 0x1 + 1 + read-write + + + ASREB + ASRC Enable B Enable the operation of the conversion B of ASRC + 0x2 + 1 + read-write + + + ASREC + ASRC Enable C Enable the operation of the conversion C of ASRC + 0x3 + 1 + read-write + + + SRST + Software Reset This bit is self-clear bit + 0x4 + 1 + write-only + + + IDRA + Use Ideal Ratio for Pair A When USRA=0, this bit has no usage + 0xD + 1 + read-write + + + USRA + Use Ratio for Pair A Use ratio as the input to ASRC + 0xE + 1 + read-write + + + IDRB + Use Ideal Ratio for Pair B When USRB=0, this bit has no usage + 0xF + 1 + read-write + + + USRB + Use Ratio for Pair B Use ratio as the input to ASRC + 0x10 + 1 + read-write + + + IDRC + Use Ideal Ratio for Pair C When USRC=0, this bit has no usage + 0x11 + 1 + read-write + + + USRC + Use Ratio for Pair C Use ratio as the input to ASRC + 0x12 + 1 + read-write + + + ATSA + ASRC Pair A Automatic Selection For Processing Options When this bit is 1, pair A will automatic update its pre-processing and post-processing options (ASRCFG: PREMODA, ASRCFG:POSTMODA see ASRC Misc Control Register 1 for Pair CASRC Filter Configuration Status Register ) based on the frequencies it detected + 0x14 + 1 + read-write + + + ATSB + ASRC Pair B Automatic Selection For Processing Options When this bit is 1, pair B will automatic update its pre-processing and post-processing options (ASRCFG: PREMODB, ASRCFG:POSTMODB see ASRC Misc Control Register 1 for Pair CASRC Filter Configuration Status Register ) based on the frequencies it detected + 0x15 + 1 + read-write + + + ATSC + ASRC Pair C Automatic Selection For Processing Options When this bit is 1, pair C will automatic update its pre-processing and post-processing options (ASRCFG: PREMODC, ASRCFG:POSTMODC see ASRC Misc Control Register 1 for Pair CASRC Filter Configuration Status Register ) based on the frequencies it detected + 0x16 + 1 + read-write + + + + + ASRIER + ASRC Interrupt Enable Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADIEA + Data Input A Interrupt Enable Enables the data input A Interrupt. + 0 + 1 + read-write + + + ADIEA_0 + interrupt disabled + 0 + + + ADIEA_1 + interrupt enabled + 0x1 + + + + + ADIEB + Data Input B Interrupt Enable Enables the data input B interrupt. + 0x1 + 1 + read-write + + + ADIEB_0 + interrupt disabled + 0 + + + ADIEB_1 + interrupt enabled + 0x1 + + + + + ADIEC + Data Input C Interrupt Enable Enables the data input C interrupt. + 0x2 + 1 + read-write + + + ADIEC_0 + interrupt disabled + 0 + + + ADIEC_1 + interrupt enabled + 0x1 + + + + + ADOEA + Data Output A Interrupt Enable Enables the data output A interrupt. + 0x3 + 1 + read-write + + + ADOEA_0 + interrupt disabled + 0 + + + ADOEA_1 + interrupt enabled + 0x1 + + + + + ADOEB + Data Output B Interrupt Enable Enables the data output B interrupt. + 0x4 + 1 + read-write + + + ADOEB_0 + interrupt disabled + 0 + + + ADOEB_1 + interrupt enabled + 0x1 + + + + + ADOEC + Data Output C Interrupt Enable Enables the data output C interrupt. + 0x5 + 1 + read-write + + + ADOEC_0 + interrupt disabled + 0 + + + ADOEC_1 + interrupt enabled + 0x1 + + + + + AOLIE + Overload Interrupt Enable Enables the overload interrupt. + 0x6 + 1 + read-write + + + AOLIE_0 + interrupt disabled + 0 + + + AOLIE_1 + interrupt enabled + 0x1 + + + + + AFPWE + FP in Wait State Interrupt Enable Enables the FP in wait state interrupt. + 0x7 + 1 + read-write + + + AFPWE_0 + interrupt disabled + 0 + + + AFPWE_1 + interrupt enabled + 0x1 + + + + + + + ASRCNCR + ASRC Channel Number Configuration Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ANCA + Number of A Channels + 0 + 4 + read-write + + + ANCA_0 + 0 channels in A (Pair A is disabled) + 0 + + + ANCA_1 + 1 channel in A + 0x1 + + + ANCA_2 + 2 channels in A + 0x2 + + + ANCA_3 + 3 channels in A + 0x3 + + + ANCA_4 + 4 channels in A + 0x4 + + + ANCA_5 + 5 channels in A + 0x5 + + + ANCA_6 + 6 channels in A + 0x6 + + + ANCA_7 + 7 channels in A + 0x7 + + + ANCA_8 + 8 channels in A + 0x8 + + + ANCA_9 + 9 channels in A + 0x9 + + + ANCA_10 + 10 channels in A + 0xA + + + + + ANCB + Number of B Channels + 0x4 + 4 + read-write + + + ANCB_0 + 0 channels in B (Pair B is disabled) + 0 + + + ANCB_1 + 1 channel in B + 0x1 + + + ANCB_2 + 2 channels in B + 0x2 + + + ANCB_3 + 3 channels in B + 0x3 + + + ANCB_4 + 4 channels in B + 0x4 + + + ANCB_5 + 5 channels in B + 0x5 + + + ANCB_6 + 6 channels in B + 0x6 + + + ANCB_7 + 7 channels in B + 0x7 + + + ANCB_8 + 8 channels in B + 0x8 + + + ANCB_9 + 9 channels in B + 0x9 + + + ANCB_10 + 10 channels in B + 0xA + + + + + ANCC + Number of C ChannelsANCC+ANCB+ANCA<=10 + 0x8 + 4 + read-write + + + ANCC_0 + 0 channels in C (Pair C is disabled) + 0 + + + ANCC_1 + 1 channel in C + 0x1 + + + ANCC_2 + 2 channels in C + 0x2 + + + ANCC_3 + 3 channels in C + 0x3 + + + ANCC_4 + 4 channels in C + 0x4 + + + ANCC_5 + 5 channels in C + 0x5 + + + ANCC_6 + 6 channels in C + 0x6 + + + ANCC_7 + 7 channels in C + 0x7 + + + ANCC_8 + 8 channels in C + 0x8 + + + ANCC_9 + 9 channels in C + 0x9 + + + ANCC_10 + 10 channels in C + 0xA + + + + + + + ASRCFG + ASRC Filter Configuration Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PREMODA + Pre-Processing Configuration for Conversion Pair A These bits will be read/write by user if ASRCTR:ATSA=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSA=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0x6 + 2 + read-write + + + PREMODA_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + PREMODA_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + PREMODA_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + PREMODA_3 + Select passthrough mode. In this case, POSTMODA[1-0] have no use. + 0x3 + + + + + POSTMODA + Post-Processing Configuration for Conversion Pair A These bits will be read/write by user if ASRCTR:ATSA=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSA=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0x8 + 2 + read-write + + + POSTMODA_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + POSTMODA_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + POSTMODA_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + + + PREMODB + Pre-Processing Configuration for Conversion Pair B These bits will be read/write by user if ASRCTR:ATSB=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSB=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0xA + 2 + read-write + + + PREMODB_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + PREMODB_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + PREMODB_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + PREMODB_3 + Select passthrough mode. In this case, POSTMODB[1-0] have no use. + 0x3 + + + + + POSTMODB + Post-Processing Configuration for Conversion Pair B These bits will be read/write by user if ASRCTR:ATSB=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSB=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0xC + 2 + read-write + + + POSTMODB_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + POSTMODB_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + POSTMODB_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + + + PREMODC + Pre-Processing Configuration for Conversion Pair C These bits will be read/write by user if ASRCTR:ATSC=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSC=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0xE + 2 + read-write + + + PREMODC_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + PREMODC_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + PREMODC_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + PREMODC_3 + Select passthrough mode. In this case, POSTMODC[1-0] have no use. + 0x3 + + + + + POSTMODC + Post-Processing Configuration for Conversion Pair C These bits will be read/write by user if ASRCTR:ATSC=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSC=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0x10 + 2 + read-write + + + POSTMODC_0 + Select Upsampling-by-2 as defined in Signal Processing Flow. + 0 + + + POSTMODC_1 + Select Direct-Connection as defined in Signal Processing Flow. + 0x1 + + + POSTMODC_2 + Select Downsampling-by-2 as defined in Signal Processing Flow. + 0x2 + + + + + NDPRA + Not Use Default Parameters for RAM-stored Parameters For Conversion Pair A + 0x12 + 1 + read-write + + + NDPRA_0 + Use default parameters for RAM-stored parameters. Override any parameters already in RAM. + 0 + + + NDPRA_1 + Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. + 0x1 + + + + + NDPRB + Not Use Default Parameters for RAM-stored Parameters For Conversion Pair B + 0x13 + 1 + read-write + + + NDPRB_0 + Use default parameters for RAM-stored parameters. Override any parameters already in RAM. + 0 + + + NDPRB_1 + Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM. + 0x1 + + + + + NDPRC + Not Use Default Parameters for RAM-stored Parameters For Conversion Pair C + 0x14 + 1 + read-write + + + NDPRC_0 + Use default parameters for RAM-stored parameters. Override any parameters already in RAM. + 0 + + + NDPRC_1 + Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. + 0x1 + + + + + INIRQA + Initialization for Conversion Pair A is served When this bit is 1, it means the initialization for conversion pair A is served + 0x15 + 1 + read-only + + + INIRQB + Initialization for Conversion Pair B is served When this bit is 1, it means the initialization for conversion pair B is served + 0x16 + 1 + read-only + + + INIRQC + Initialization for Conversion Pair C is served When this bit is 1, it means the initialization for conversion pair C is served + 0x17 + 1 + read-only + + + + + ASRCSR + ASRC Clock Source Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AICSA + Input Clock Source A + 0 + 4 + read-write + + + AICSA_0 + bit clock 0 + 0 + + + AICSA_1 + bit clock 1 + 0x1 + + + AICSA_2 + bit clock 2 + 0x2 + + + AICSA_3 + bit clock 3 + 0x3 + + + AICSA_4 + bit clock 4 + 0x4 + + + AICSA_5 + bit clock 5 + 0x5 + + + AICSA_6 + bit clock 6 + 0x6 + + + AICSA_7 + bit clock 7 + 0x7 + + + AICSA_8 + bit clock 8 + 0x8 + + + AICSA_9 + bit clock 9 + 0x9 + + + AICSA_10 + bit clock A + 0xA + + + AICSA_11 + bit clock B + 0xB + + + AICSA_12 + bit clock C + 0xC + + + AICSA_13 + bit clock D + 0xD + + + AICSA_14 + bit clock E + 0xE + + + AICSA_15 + clock disabled, connected to zero + 0xF + + + + + AICSB + Input Clock Source B + 0x4 + 4 + read-write + + + AICSB_0 + bit clock 0 + 0 + + + AICSB_1 + bit clock 1 + 0x1 + + + AICSB_2 + bit clock 2 + 0x2 + + + AICSB_3 + bit clock 3 + 0x3 + + + AICSB_4 + bit clock 4 + 0x4 + + + AICSB_5 + bit clock 5 + 0x5 + + + AICSB_6 + bit clock 6 + 0x6 + + + AICSB_7 + bit clock 7 + 0x7 + + + AICSB_8 + bit clock 8 + 0x8 + + + AICSB_9 + bit clock 9 + 0x9 + + + AICSB_10 + bit clock A + 0xA + + + AICSB_11 + bit clock B + 0xB + + + AICSB_12 + bit clock C + 0xC + + + AICSB_13 + bit clock D + 0xD + + + AICSB_14 + bit clock E + 0xE + + + AICSB_15 + clock disabled, connected to zero + 0xF + + + + + AICSC + Input Clock Source C + 0x8 + 4 + read-write + + + AICSC_0 + bit clock 0 + 0 + + + AICSC_1 + bit clock 1 + 0x1 + + + AICSC_2 + bit clock 2 + 0x2 + + + AICSC_3 + bit clock 3 + 0x3 + + + AICSC_4 + bit clock 4 + 0x4 + + + AICSC_5 + bit clock 5 + 0x5 + + + AICSC_6 + bit clock 6 + 0x6 + + + AICSC_7 + bit clock 7 + 0x7 + + + AICSC_8 + bit clock 8 + 0x8 + + + AICSC_9 + bit clock 9 + 0x9 + + + AICSC_10 + bit clock A + 0xA + + + AICSC_11 + bit clock B + 0xB + + + AICSC_12 + bit clock C + 0xC + + + AICSC_13 + bit clock D + 0xD + + + AICSC_14 + bit clock E + 0xE + + + AICSC_15 + clock disabled, connected to zero + 0xF + + + + + AOCSA + Output Clock Source A + 0xC + 4 + read-write + + + AOCSA_0 + bit clock 0 + 0 + + + AOCSA_1 + bit clock 1 + 0x1 + + + AOCSA_2 + bit clock 2 + 0x2 + + + AOCSA_3 + bit clock 3 + 0x3 + + + AOCSA_4 + bit clock 4 + 0x4 + + + AOCSA_5 + bit clock 5 + 0x5 + + + AOCSA_6 + bit clock 6 + 0x6 + + + AOCSA_7 + bit clock 7 + 0x7 + + + AOCSA_8 + bit clock 8 + 0x8 + + + AOCSA_9 + bit clock 9 + 0x9 + + + AOCSA_10 + bit clock A + 0xA + + + AOCSA_11 + bit clock B + 0xB + + + AOCSA_12 + bit clock C + 0xC + + + AOCSA_13 + bit clock D + 0xD + + + AOCSA_14 + bit clock E + 0xE + + + AOCSA_15 + clock disabled, connected to zero + 0xF + + + + + AOCSB + Output Clock Source B + 0x10 + 4 + read-write + + + AOCSB_0 + bit clock 0 + 0 + + + AOCSB_1 + bit clock 1 + 0x1 + + + AOCSB_2 + bit clock 2 + 0x2 + + + AOCSB_3 + bit clock 3 + 0x3 + + + AOCSB_4 + bit clock 4 + 0x4 + + + AOCSB_5 + bit clock 5 + 0x5 + + + AOCSB_6 + bit clock 6 + 0x6 + + + AOCSB_7 + bit clock 7 + 0x7 + + + AOCSB_8 + bit clock 8 + 0x8 + + + AOCSB_9 + bit clock 9 + 0x9 + + + AOCSB_10 + bit clock A + 0xA + + + AOCSB_11 + bit clock B + 0xB + + + AOCSB_12 + bit clock C + 0xC + + + AOCSB_13 + bit clock D + 0xD + + + AOCSB_14 + bit clock E + 0xE + + + AOCSB_15 + clock disabled, connected to zero + 0xF + + + + + AOCSC + Output Clock Source C + 0x14 + 4 + read-write + + + AOCSC_0 + bit clock 0 + 0 + + + AOCSC_1 + bit clock 1 + 0x1 + + + AOCSC_2 + bit clock 2 + 0x2 + + + AOCSC_3 + bit clock 3 + 0x3 + + + AOCSC_4 + bit clock 4 + 0x4 + + + AOCSC_5 + bit clock 5 + 0x5 + + + AOCSC_6 + bit clock 6 + 0x6 + + + AOCSC_7 + bit clock 7 + 0x7 + + + AOCSC_8 + bit clock 8 + 0x8 + + + AOCSC_9 + bit clock 9 + 0x9 + + + AOCSC_10 + bit clock A + 0xA + + + AOCSC_11 + bit clock B + 0xB + + + AOCSC_12 + bit clock C + 0xC + + + AOCSC_13 + bit clock D + 0xD + + + AOCSC_14 + bit clock E + 0xE + + + AOCSC_15 + clock disabled, connected to zero + 0xF + + + + + + + ASRCDR1 + ASRC Clock Divider Register 1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AICPA + Input Clock Prescaler A Specify the prescaling factor of the input prescaler A + 0 + 3 + read-write + + + AICDA + Input Clock Divider A Specify the divide ratio of the input clock divider A + 0x3 + 3 + read-write + + + AICPB + Input Clock Prescaler B Specify the prescaling factor of the input prescaler B + 0x6 + 3 + read-write + + + AICDB + Input Clock Divider B Specify the divide ratio of the input clock divider B + 0x9 + 3 + read-write + + + AOCPA + Output Clock Prescaler A Specify the prescaling factor of the output prescaler A + 0xC + 3 + read-write + + + AOCDA + Output Clock Divider A Specify the divide ratio of the output clock divider A + 0xF + 3 + read-write + + + AOCPB + Output Clock Prescaler B Specify the prescaling factor of the output prescaler B + 0x12 + 3 + read-write + + + AOCDB + Output Clock Divider B Specify the divide ratio of the output clock divider B + 0x15 + 3 + read-write + + + + + ASRCDR2 + ASRC Clock Divider Register 2 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AICPC + Input Clock Prescaler C Specify the prescaling factor of the input prescaler C + 0 + 3 + read-write + + + AICDC + Input Clock Divider C Specify the divide ratio of the input clock divider C + 0x3 + 3 + read-write + + + AOCPC + Output Clock Prescaler C Specify the prescaling factor of the output prescaler C + 0x6 + 3 + read-write + + + AOCDC + Output Clock Divider C Specify the divide ratio of the output clock divider C + 0x9 + 3 + read-write + + + + + ASRSTR + ASRC Status Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + AIDEA + Number of data in Input Data Buffer A is less than threshold When set, this bit indicates that number of data still available in ASRDIRA is less than threshold and the processor can write data to ASRDIRA + 0 + 1 + read-only + + + AIDEB + Number of data in Input Data Buffer B is less than threshold When set, this bit indicates that number of data still available in ASRDIRB is less than threshold and the processor can write data to ASRDIRB + 0x1 + 1 + read-only + + + AIDEC + Number of data in Input Data Buffer C is less than threshold When set, this bit indicates that number of data still available in ASRDIRC is less than threshold and the processor can write data to ASRDIRC + 0x2 + 1 + read-only + + + AODFA + Number of data in Output Data Buffer A is greater than threshold When set, this bit indicates that number of data already existing in ASRDORA is greater than threshold and the processor can read data from ASRDORA + 0x3 + 1 + read-only + + + AODFB + Number of data in Output Data Buffer B is greater than threshold When set, this bit indicates that number of data already existing in ASRDORB is greater than threshold and the processor can read data from ASRDORB + 0x4 + 1 + read-only + + + AODFC + Number of data in Output Data Buffer C is greater than threshold When set, this bit indicates that number of data already existing in ASRDORC is greater than threshold and the processor can read data from ASRDORC + 0x5 + 1 + read-only + + + AOLE + Overload Error Flag When set, this bit indicates that the task rate is too high for the ASRC to handle + 0x6 + 1 + read-only + + + FPWT + FP is in wait states This bit is for debug only + 0x7 + 1 + read-only + + + AIDUA + Input Data Buffer A has underflowed When set, this bit indicates that input data buffer A has underflowed + 0x8 + 1 + read-only + + + AIDUB + Input Data Buffer B has underflowed When set, this bit indicates that input data buffer B has underflowed + 0x9 + 1 + read-only + + + AIDUC + Input Data Buffer C has underflowed When set, this bit indicates that input data buffer C has underflowed + 0xA + 1 + read-only + + + AODOA + Output Data Buffer A has overflowed When set, this bit indicates that output data buffer A has overflowed + 0xB + 1 + read-only + + + AODOB + Output Data Buffer B has overflowed When set, this bit indicates that output data buffer B has overflowed + 0xC + 1 + read-only + + + AODOC + Output Data Buffer C has overflowed When set, this bit indicates that output data buffer C has overflowed + 0xD + 1 + read-only + + + AIOLA + Pair A Input Task Overload When set, this bit indicates that pair A input task is oveloaded + 0xE + 1 + read-only + + + AIOLB + Pair B Input Task Overload When set, this bit indicates that pair B input task is oveloaded + 0xF + 1 + read-only + + + AIOLC + Pair C Input Task Overload When set, this bit indicates that pair C input task is oveloaded + 0x10 + 1 + read-only + + + AOOLA + Pair A Output Task Overload When set, this bit indicates that pair A output task is oveloaded + 0x11 + 1 + read-only + + + AOOLB + Pair B Output Task Overload When set, this bit indicates that pair B output task is oveloaded + 0x12 + 1 + read-only + + + AOOLC + Pair C Output Task Overload When set, this bit indicates that pair C output task is oveloaded + 0x13 + 1 + read-only + + + ATQOL + Task Queue FIFO overload When set, this bit indicates that task queue FIFO logic is oveloaded + 0x14 + 1 + read-only + + + DSLCNT + DSL Counter Input to FIFO ready When set, this bit indicates that new DSL counter information is stored in the internal ASRC FIFO + 0x15 + 1 + read-only + + + + + 5 + 0x4 + 1,2,3,4,5 + ASRPMn%s + ASRC Parameter Register n + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARAMETER_VALUE + See recommended values table. + 0 + 24 + read-write + + + + + ASRTFR1 + ASRC ASRC Task Queue FIFO Register 1 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + TF_BASE + Base address for task queue FIFO. Set to 0x7C. + 0x6 + 7 + read-write + + + TF_FILL + Current number of entries in task queue FIFO. + 0xD + 7 + read-only + + + + + ASRCCR + ASRC Channel Counter Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACIA + The channel counter for Pair A's input FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair A's input FIFO's usage + 0 + 4 + read-write + + + ACIB + The channel counter for Pair B's input FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair B's input FIFO's usage + 0x4 + 4 + read-write + + + ACIC + The channel counter for Pair C's input FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair C's input FIFO's usage + 0x8 + 4 + read-write + + + ACOA + The channel counter for Pair A's output FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair A's output FIFO's usage + 0xC + 4 + read-write + + + ACOB + The channel counter for Pair B's output FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair B's output FIFO's usage + 0x10 + 4 + read-write + + + ACOC + The channel counter for Pair C's output FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair C's output FIFO's usage + 0x14 + 4 + read-write + + + + + 3 + 0x8 + A,B,C + ASRDI%s + ASRC Data Input Register for Pair x + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Audio data input + 0 + 24 + write-only + + + + + 3 + 0x8 + A,B,C + ASRDO%s + ASRC Data Output Register for Pair x + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Audio data output + 0 + 24 + read-only + + + + + ASRIDRHA + ASRC Ideal Ratio for Pair A-High Part + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOA + IDRATIOA[31:24]. High part of ideal ratio value for pair A + 0 + 8 + read-write + + + + + ASRIDRLA + ASRC Ideal Ratio for Pair A -Low Part + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOA + IDRATIOA[23:0]. Low part of ideal ratio value for pair A + 0 + 24 + read-write + + + + + ASRIDRHB + ASRC Ideal Ratio for Pair B-High Part + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOB + IDRATIOB[31:24]. High part of ideal ratio value for pair B. + 0 + 8 + read-write + + + + + ASRIDRLB + ASRC Ideal Ratio for Pair B-Low Part + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOB + IDRATIOB[23:0]. Low part of ideal ratio value for pair B. + 0 + 24 + read-write + + + + + ASRIDRHC + ASRC Ideal Ratio for Pair C-High Part + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOC + IDRATIOC[31:24]. High part of ideal ratio value for pair C. + 0 + 8 + read-write + + + + + ASRIDRLC + ASRC Ideal Ratio for Pair C-Low Part + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOC + IDRATIOC[23:0]. Low part of ideal ratio value for pair C. + 0 + 24 + read-write + + + + + ASR76K + ASRC 76 kHz Period in terms of ASRC processing clock + 0x98 + 32 + read-write + 0xA47 + 0xFFFFFFFF + + + ASR76K + Value for the period of the 76 kHz sampling clock. + 0 + 17 + read-write + + + + + ASR56K + ASRC 56 kHz Period in terms of ASRC processing clock + 0x9C + 32 + read-write + 0xDF3 + 0xFFFFFFFF + + + ASR56K + Value for the period of the 56 kHz sampling clock + 0 + 17 + read-write + + + + + ASRMCRA + ASRC Misc Control Register for Pair A + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INFIFO_THRESHOLDA + The threshold for Pair A's input FIFO per channel These bits stand for the threshold for Pair A's input FIFO per channel + 0 + 6 + read-write + + + RSYNOFA + Re-sync Output FIFO Channel Counter If bit set, force ASRCCR:ACOA=0 + 0xA + 1 + read-write + + + RSYNIFA + Re-sync Input FIFO Channel Counter If bit set, force ASRCCR:ACIA=0 + 0xB + 1 + read-write + + + OUTFIFO_THRESHOLDA + The threshold for Pair A's output FIFO per channel These bits stand for the threshold for Pair A's output FIFO per channel + 0xC + 6 + read-write + + + BYPASSPOLYA + Bypass Polyphase Filtering for Pair A This bit will determine whether the polyphase filtering part of Pair A conversion will be bypassed + 0x14 + 1 + read-write + + + BYPASSPOLYA_0 + Don't bypass polyphase filtering. + 0 + + + BYPASSPOLYA_1 + Bypass polyphase filtering. + 0x1 + + + + + BUFSTALLA + Stall Pair A conversion in case of Buffer Near Empty/Full Condition This bit will determine whether the near empty/full FIFO condition will stall the rate conversion for pair A + 0x15 + 1 + read-write + + + BUFSTALLA_0 + Don't stall Pair A conversion even in case of near empty/full FIFO conditions. + 0 + + + BUFSTALLA_1 + Stall Pair A conversion in case of near empty/full FIFO conditions. + 0x1 + + + + + EXTTHRSHA + Use external thresholds for FIFO control of Pair A This bit will determine whether the FIFO thresholds externally defined in this register is used to control ASRC internal FIFO logic for pair A + 0x16 + 1 + read-write + + + EXTTHRSHA_0 + Use default thresholds. + 0 + + + EXTTHRSHA_1 + Use external defined thresholds. + 0x1 + + + + + ZEROBUFA + Initialize buf of Pair A when pair A is enabled + 0x17 + 1 + read-write + + + ZEROBUFA_0 + Zeroize the buffer + 0 + + + ZEROBUFA_1 + Don't zeroize the buffer + 0x1 + + + + + + + ASRFSTA + ASRC FIFO Status Register for Pair A + 0xA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + INFIFO_FILLA + The fillings for Pair A's input FIFO per channel These bits stand for the fillings for Pair A's input FIFO per channel + 0 + 7 + read-only + + + IAEA + Input FIFO is near Empty for Pair A This bit is to indicate whether the input FIFO of Pair A is near empty + 0xB + 1 + read-only + + + OUTFIFO_FILLA + The fillings for Pair A's output FIFO per channel These bits stand for the fillings for Pair A's output FIFO per channel + 0xC + 7 + read-only + + + OAFA + Output FIFO is near Full for Pair A This bit is to indicate whether the output FIFO of Pair A is near full + 0x17 + 1 + read-only + + + + + ASRMCRB + ASRC Misc Control Register for Pair B + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + INFIFO_THRESHOLDB + The threshold for Pair B's input FIFO per channel These bits stand for the threshold for Pair B's input FIFO per channel + 0 + 6 + read-write + + + RSYNOFB + Re-sync Output FIFO Channel Counter If bit set, force ASRCCR:ACOB=0 + 0xA + 1 + read-write + + + RSYNIFB + Re-sync Input FIFO Channel Counter If bit set, force ASRCCR:ACIB=0 + 0xB + 1 + read-write + + + OUTFIFO_THRESHOLDB + The threshold for Pair B's output FIFO per channel These bits stand for the threshold for Pair B's output FIFO per channel + 0xC + 6 + read-write + + + BYPASSPOLYB + Bypass Polyphase Filtering for Pair B This bit will determine whether the polyphase filtering part of Pair B conversion will be bypassed + 0x14 + 1 + read-write + + + BYPASSPOLYB_0 + Don't bypass polyphase filtering. + 0 + + + BYPASSPOLYB_1 + Bypass polyphase filtering. + 0x1 + + + + + BUFSTALLB + Stall Pair B conversion in case of Buffer Near Empty/Full Condition This bit will determine whether the near empty/full FIFO condition will stall the rate conversion for pair B + 0x15 + 1 + read-write + + + BUFSTALLB_0 + Don't stall Pair B conversion even in case of near empty/full FIFO conditions. + 0 + + + BUFSTALLB_1 + Stall Pair B conversion in case of near empty/full FIFO conditions. + 0x1 + + + + + EXTTHRSHB + Use external thresholds for FIFO control of Pair B This bit will determine whether the FIFO thresholds externally defined in this register is used to control ASRC internal FIFO logic for pair B + 0x16 + 1 + read-write + + + EXTTHRSHB_0 + Use default thresholds. + 0 + + + EXTTHRSHB_1 + Use external defined thresholds. + 0x1 + + + + + ZEROBUFB + Initialize buf of Pair B when pair B is enabled This bit is used to control whether the buffer is to be zeroized when pair B is enabled + 0x17 + 1 + read-write + + + ZEROBUFB_0 + Zeroize the buffer + 0 + + + ZEROBUFB_1 + Don't zeroize the buffer + 0x1 + + + + + + + ASRFSTB + ASRC FIFO Status Register for Pair B + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + INFIFO_FILLB + The fillings for Pair B's input FIFO per channel These bits stand for the fillings for Pair B's input FIFO per channel + 0 + 7 + read-only + + + IAEB + Input FIFO is near Empty for Pair B This bit is to indicate whether the input FIFO of Pair B is near empty + 0xB + 1 + read-only + + + OUTFIFO_FILLB + The fillings for Pair B's output FIFO per channel These bits stand for the fillings for Pair B's output FIFO per channel + 0xC + 7 + read-only + + + OAFB + Output FIFO is near Full for Pair B This bit is to indicate whether the output FIFO of Pair B is near full + 0x17 + 1 + read-only + + + + + ASRMCRC + ASRC Misc Control Register for Pair C + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INFIFO_THRESHOLDC + The threshold for Pair C's input FIFO per channel These bits stand for the threshold for Pair C's input FIFO per channel + 0 + 6 + read-write + + + RSYNOFC + Re-sync Output FIFO Channel Counter If bit set, force ASRCCR:ACOC=0 + 0xA + 1 + read-write + + + RSYNIFC + Re-sync Input FIFO Channel Counter If bit set, force ASRCCR:ACIC=0 + 0xB + 1 + read-write + + + OUTFIFO_THRESHOLDC + The threshold for Pair C's output FIFO per channel These bits stand for the threshold for Pair C's output FIFO per channel + 0xC + 6 + read-write + + + BYPASSPOLYC + Bypass Polyphase Filtering for Pair C This bit will determine whether the polyphase filtering part of Pair C conversion will be bypassed + 0x14 + 1 + read-write + + + BYPASSPOLYC_0 + Don't bypass polyphase filtering. + 0 + + + BYPASSPOLYC_1 + Bypass polyphase filtering. + 0x1 + + + + + BUFSTALLC + Stall Pair C conversion in case of Buffer Near Empty/Full Condition This bit will determine whether the near empty/full FIFO condition will stall the rate conversion for pair C + 0x15 + 1 + read-write + + + BUFSTALLC_0 + Don't stall Pair C conversion even in case of near empty/full FIFO conditions. + 0 + + + BUFSTALLC_1 + Stall Pair C conversion in case of near empty/full FIFO conditions. + 0x1 + + + + + EXTTHRSHC + Use external thresholds for FIFO control of Pair C This bit will determine whether the FIFO thresholds externally defined in this register is used to control ASRC internal FIFO logic for pair C + 0x16 + 1 + read-write + + + EXTTHRSHC_0 + Use default thresholds. + 0 + + + EXTTHRSHC_1 + Use external defined thresholds. + 0x1 + + + + + ZEROBUFC + Initialize buf of Pair C when pair C is enabled This bit is used to control whether the buffer is to be zeroized when pair C is enabled + 0x17 + 1 + read-write + + + ZEROBUFC_0 + Zeroize the buffer + 0 + + + ZEROBUFC_1 + Don't zeroize the buffer + 0x1 + + + + + + + ASRFSTC + ASRC FIFO Status Register for Pair C + 0xB4 + 32 + read-only + 0 + 0xFFFFFFFF + + + INFIFO_FILLC + The fillings for Pair C's input FIFO per channel These bits stand for the fillings for Pair C's input FIFO per channel + 0 + 7 + read-only + + + IAEC + Input FIFO is near Empty for Pair C This bit is to indicate whether the input FIFO of Pair C is near empty + 0xB + 1 + read-only + + + OUTFIFO_FILLC + The fillings for Pair C's output FIFO per channel These bits stand for the fillings for Pair C's output FIFO per channel + 0xC + 7 + read-only + + + OAFC + Output FIFO is near Full for Pair C This bit is to indicate whether the output FIFO of Pair C is near full + 0x17 + 1 + read-only + + + + + 3 + 0x4 + A,B,C + ASRMCR1%s + ASRC Misc Control Register 1 for Pair X + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OW16 + Bit Width Option of the output FIFO This bit will determine the bit width option of the output FIFO + 0 + 1 + read-write + + + OW16_0 + 24-bit output data. + 0 + + + OW16_1 + 16-bit output data + 0x1 + + + + + OSGN + Sign Extension Option of the output FIFO This bit will determine the sign extension option of the output FIFO + 0x1 + 1 + read-write + + + OSGN_0 + No sign extension. + 0 + + + OSGN_1 + Sign extension. + 0x1 + + + + + OMSB + Data Alignment of the output FIFO This bit will determine the data alignment of the output FIFO. + 0x2 + 1 + read-write + + + OMSB_0 + LSB aligned. + 0 + + + OMSB_1 + MSB aligned. + 0x1 + + + + + IMSB + Data Alignment of the input FIFO This bit will determine the data alignment of the input FIFO. + 0x8 + 1 + read-write + + + IMSB_0 + LSB aligned. + 0 + + + IMSB_1 + MSB aligned. + 0x1 + + + + + IWD + Data Width of the input FIFO These three bits will determine the bitwidth for the audio data into ASRC All other settings not shown are reserved + 0x9 + 3 + read-write + + + + + + + SPBA + Temperature Monitor + SPBA + SPBA_ + 0x203C000 + + 0 + 0x80 + registers + + + + 32 + 0x4 + PRR%s + Peripheral Rights Register + 0 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + RARA + Resource Access Right + 0 + 1 + read-write + + + PROHIBITED + Access to peripheral is not allowed. + 0 + + + ALLOWED + Access to peripheral is granted. + 0x1 + + + + + RARB + Resource Access Right + 0x1 + 1 + read-write + + + PROHIBITED + Access to peripheral is not allowed. + 0 + + + ALLOWED + Access to peripheral is granted. + 0x1 + + + + + RARC + Resource Access Right + 0x2 + 1 + read-write + + + PROHIBITED + Access to peripheral is not allowed. + 0 + + + ALLOWED + Access to peripheral is granted. + 0x1 + + + + + ROI + Resource Owner ID + 0x10 + 2 + read-only + + + UNOWNED + Unowned resource. + 0 + + + MASTER_A + The resource is owned by master A port. + 0x1 + + + MASTER_B + The resource is owned by master B port. + 0x2 + + + MASTER_C + The resource is owned by master C port. + 0x3 + + + + + RMO + Requesting Master Owner + 0x1E + 2 + read-only + + + UNOWNED + The resource is unowned. + 0 + + + ANOTHER_MASTER + The resource is owned by another master. + 0x2 + + + REQUESTING_MASTER + The resource is owned by the requesting master. + 0x3 + + + + + + + + + TSC + Touch Screen Controller + TSC + TSC_ + 0x2040000 + + 0 + 0x84 + registers + + + TSC + 35 + + + + BASIC_SETTING + PS Input Buffer Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTO_MEASURE + Auto Measure + 0 + 1 + read-write + + + AUTO_MEASURE_0 + Disable Auto Measure + 0 + + + AUTO_MEASURE_1 + Auto Measure + 0x1 + + + + + _4_5_WIRE + 4/5 Wire detection + 0x4 + 1 + read-write + + + _4_5_WIRE_0 + 4-Wire Detection Mode + 0 + + + _4_5_WIRE_1 + 5-Wire Detection Mode + 0x1 + + + + + MEASURE_DELAY_TIME + Measure Delay Time + 0x8 + 24 + read-write + + + + + PS_INPUT_BUFFER_ADDR + PS Input Buffer Address + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_CHARGE_TIME + Auto Measure + 0 + 32 + read-write + + + PRE_CHARGE_TIME_0 + Disable Auto Measure + 0 + + + PRE_CHARGE_TIME_1 + Auto Measure + 0x1 + + + + + + + FLOW_CONTROL + Flow Control + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_RST + Soft Reset + 0 + 1 + read-write + + + START_MEASURE + Start Measure + 0x4 + 1 + read-write + + + START_MEASURE_0 + Do not start measure for now + 0 + + + START_MEASURE_1 + Start measure the X/Y coordinate value + 0x1 + + + + + DROP_MEASURE + Drop Measure + 0x8 + 1 + read-write + + + DROP_MEASURE_0 + Do not drop measure for now + 0 + + + DROP_MEASURE_1 + Drop the measure and controller return to idle status + 0x1 + + + + + START_SENSE + Start Sense + 0xC + 1 + read-write + + + START_SENSE_0 + Stay at idle status + 0 + + + START_SENSE_1 + Start sense detection and (if auto_measure set to 1) measure after detect a touch + 0x1 + + + + + DISABLE + This bit is for SW disable registers + 0x10 + 1 + read-write + + + DISABLE_0 + Leave HW state machine control + 0 + + + DISABLE_1 + SW set to idle status + 0x1 + + + + + + + MEASEURE_VALUE + Measure Value + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + Y_VALUE + Y Value + 0 + 12 + read-only + + + X_VALUE + X Value + 0x10 + 12 + read-only + + + + + INT_EN + Interrupt Enable + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_INT_EN + Measure Interrupt Enable + 0 + 1 + read-write + + + MEASURE_INT_EN_0 + Disable measure + 0 + + + + + DETECT_INT_EN + Detect Interrupt Enable + 0x4 + 1 + read-write + + + DETECT_INT_EN_0 + Disable detect interrupt + 0 + + + DETECT_INT_EN_1 + Enable detect interrupt + 0x1 + + + + + IDLE_SW_INT_EN + Idle Software Interrupt Enable + 0xC + 1 + read-write + + + IDLE_SW_INT_EN_0 + Disable idle software interrupt + 0 + + + IDLE_SW_INT_EN_1 + Enable idle software interrupt + 0x1 + + + + + + + INT_SIG_EN + Interrupt Signal Enable + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_SIG_EN + Measure Signal Enable + 0 + 1 + read-write + + + DETECT_SIG_EN + Detect Signal Enable + 0x4 + 1 + read-write + + + DETECT_SIG_EN_0 + Disable detect signal + 0 + + + DETECT_SIG_EN_1 + Enable detect signal + 0x1 + + + + + VALID_SIG_EN + Valid Signal Enable + 0x8 + 1 + read-write + + + VALID_SIG_EN_0 + Disable valid signal + 0 + + + VALID_SIG_EN_1 + Enable valid signal + 0x1 + + + + + IDLE_SW_SIG_EN + Idle Software Signal Enable + 0xC + 1 + read-write + + + IDLE_SW_SIG_EN_0 + Disable idle software signal + 0 + + + IDLE_SW_SIG_EN_1 + Enable idle software signal + 0x1 + + + + + + + INT_STATUS + Intterrupt Status + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE + Measure Signal + 0 + 1 + read-write + + + MEASURE_0 + Does not exist a measure signal + 0 + + + MEASURE_1 + Exist a measure signal + 0x1 + + + + + DETECT + Detect Signal + 0x4 + 1 + read-write + + + DETECT_0 + Does not exist a detect signal + 0 + + + DETECT_1 + Exist detect signal + 0x1 + + + + + VALID + Valid Signal + 0x8 + 1 + read-write + + + VALID_0 + There is no touch detected after measurement, indicates that the measured value is not valid + 0 + + + VALID_1 + There is touch detection after measurement, indicates that the measure is valid + 0x1 + + + + + IDLE_SW + Idle Software + 0xC + 1 + read-write + + + IDLE_SW_0 + Haven't return to idle status + 0 + + + IDLE_SW_1 + Already return to idle status + 0x1 + + + + + + + DEBUG_MODE + no description available + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC_CONV_VALUE + ADC Conversion Value + 0 + 12 + read-only + + + ADC_COCO + ADC COCO Signal + 0xC + 1 + read-only + + + EXT_HWTS + Hardware Trigger Select Signal + 0x10 + 5 + read-write + + + TRIGGER + Trigger + 0x18 + 1 + read-write + + + TRIGGER_0 + No hardware trigger signal + 0 + + + TRIGGER_1 + Hardware trigger signal, the signal must last at least 1 ips clock period + 0x1 + + + + + ADC_COCO_CLEAR + ADC Coco Clear + 0x19 + 1 + read-write + + + ADC_COCO_CLEAR_0 + No ADC COCO clear + 0 + + + ADC_COCO_CLEAR_1 + Set ADC COCO clear + 0x1 + + + + + ADC_COCO_CLEAR_DISABLE + ADC COCO Clear Disable + 0x1A + 1 + read-write + + + ADC_COCO_CLEAR_DISABLE_0 + Allow TSC hardware generates ADC COCO clear + 0 + + + ADC_COCO_CLEAR_DISABLE_1 + Prevent TSC from generate ADC COCO clear signal + 0x1 + + + + + DEBUG_EN + Debug Enable + 0x1C + 1 + read-write + + + DEBUG_EN_0 + Enable debug mode + 0 + + + DEBUG_EN_1 + Disable debug mode + 0x1 + + + + + + + DEBUG_MODE2 + no description available + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + XPUL_PULL_DOWN + XPUL Wire Pull Down Switch + 0 + 1 + read-write + + + XPUL_PULL_DOWN_0 + Close the switch + 0 + + + XPUL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XPUL_PULL_UP + XPUL Wire Pull Up Switch + 0x1 + 1 + read-write + + + XPUL_PULL_UP_0 + Close the switch + 0 + + + XPUL_PULL_UP_1 + Open up the switch + 0x1 + + + + + XPUL_200K_PULL_UP + XPUL Wire 200K Pull Up Switch + 0x2 + 1 + read-write + + + XPUL_200K_PULL_UP_0 + Close the switch + 0 + + + XPUL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_DOWN + XNUR Wire Pull Down Switch + 0x3 + 1 + read-write + + + XNUR_PULL_DOWN_0 + Close the switch + 0 + + + XNUR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_UP + XNUR Wire Pull Up Switch + 0x4 + 1 + read-write + + + XNUR_PULL_UP_0 + Close the switch + 0 + + + XNUR_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_200K_PULL_UP + XNUR Wire 200K Pull Up Switch + 0x5 + 1 + read-write + + + XNUR_200K_PULL_UP_0 + Close the switch + 0 + + + XNUR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_DOWN + YPLL Wire Pull Down Switch + 0x6 + 1 + read-write + + + YPLL_PULL_DOWN_0 + Close the switch + 0 + + + YPLL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_UP + YPLL Wire Pull Up Switch + 0x7 + 1 + read-write + + + YPLL_PULL_UP_0 + Close the switch + 0 + + + YPLL_PULL_UP_1 + Open the switch + 0x1 + + + + + YPLL_200K_PULL_UP + YPLL Wire 200K Pull Up Switch + 0x8 + 1 + read-write + + + YPLL_200K_PULL_UP_0 + Close the switch + 0 + + + YPLL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_DOWN + YNLR Wire Pull Down Switch + 0x9 + 1 + read-write + + + YNLR_PULL_DOWN_0 + Close the switch + 0 + + + YNLR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_UP + YNLR Wire Pull Up Switch + 0xA + 1 + read-write + + + YNLR_PULL_UP_0 + Close the switch + 0 + + + YNLR_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_200K_PULL_UP + YNLR Wire 200K Pull Up Switch + 0xB + 1 + read-write + + + YNLR_200K_PULL_UP_0 + Close the switch + 0 + + + YNLR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_DOWN + Wiper Wire Pull Down Switch + 0xC + 1 + read-write + + + WIPER_PULL_DOWN_0 + Close the switch + 0 + + + WIPER_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_UP + Wiper Wire Pull Up Switch + 0xD + 1 + read-write + + + WIPER_PULL_UP_0 + Close the switch + 0 + + + WIPER_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_200K_PULL_UP + Wiper Wire 200K Pull Up Switch + 0xE + 1 + read-write + + + WIPER_200K_PULL_UP_0 + Close the switch + 0 + + + WIPER_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + DETECT_FOUR_WIRE + Detect Four Wire + 0x10 + 1 + read-only + + + DETECT_FOUR_WIRE_0 + No detect signal + 0 + + + DETECT_FOUR_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + DETECT_FIVE_WIRE + Detect Five Wire + 0x11 + 1 + read-only + + + DETECT_FIVE_WIRE_0 + No detect signal + 0 + + + DETECT_FIVE_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + STATE_MACHINE + State Machine + 0x14 + 3 + read-only + + + STATE_MACHINE_0 + Idle + 0 + + + STATE_MACHINE_1 + Pre-charge + 0x1 + + + STATE_MACHINE_2 + Detect + 0x2 + + + STATE_MACHINE_3 + X-measure + 0x3 + + + STATE_MACHINE_4 + Y-measure + 0x4 + + + STATE_MACHINE_5 + Pre-charge + 0x5 + + + STATE_MACHINE_6 + Detect + 0x6 + + + + + INTERMEDIATE + Intermediate State + 0x17 + 1 + read-only + + + INTERMEDIATE_0 + Not in intermedia + 0 + + + INTERMEDIATE_1 + Intermedia + 0x1 + + + + + DETECT_ENABLE_FOUR_WIRE + Detect Enable Four Wire + 0x18 + 1 + read-write + + + DETECT_ENABLE_FOUR_WIRE_0 + Do not read four wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FOUR_WIRE_1 + Read four wire detect status from analogue + 0x1 + + + + + DETECT_ENABLE_FIVE_WIRE + Detect Enable Five Wire + 0x1C + 1 + read-write + + + DETECT_ENABLE_FIVE_WIRE_0 + Do not read five wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FIVE_WIRE_1 + Read five wire detect status from analogue + 0x1 + + + + + DE_GLITCH + This field indicates glitch threshold + 0x1D + 2 + read-only + + + DE_GLITCH_0 + Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + 0 + + + DE_GLITCH_1 + Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + 0x1 + + + DE_GLITCH_2 + Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + 0x2 + + + DE_GLITCH_3 + Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + 0x3 + + + + + + + + + AIPSTZ1 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ1_ + 0x207C000 + AIPSTZ + + 0 + 0x54 + registers + + + + MPR + Master Priviledge Registers + 0 + 32 + read-write + 0x77000000 + 0xFFFFFFFF + + + MPROT5 + Master 5 Priviledge, Buffer, Read, Write Control. + 0x8 + 4 + read-write + + + MPROT3 + Master 3 Priviledge, Buffer, Read, Write Control. + 0x10 + 4 + read-write + + + MPROT2 + Master 2 Priviledge, Buffer, Read, Write Control + 0x14 + 4 + read-write + + + MPROT1 + Master 1 Priviledge, Buffer, Read, Write Control + 0x18 + 4 + read-write + + + MPROT0 + Master 0 Priviledge, Buffer, Read, Write Control + 0x1C + 4 + read-write + + + + + OPACR + Off-Platform Peripheral Access Control Registers + 0x40 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC7 + Off-platform Peripheral Access Control 7 + 0 + 4 + read-write + + + OPAC6 + Off-platform Peripheral Access Control 6 + 0x4 + 4 + read-write + + + OPAC5 + Off-platform Peripheral Access Control 5 + 0x8 + 4 + read-write + + + OPAC4 + Off-platform Peripheral Access Control 4 + 0xC + 4 + read-write + + + OPAC3 + Off-platform Peripheral Access Control 3 + 0x10 + 4 + read-write + + + OPAC2 + Off-platform Peripheral Access Control 2 + 0x14 + 4 + read-write + + + OPAC1 + Off-platform Peripheral Access Control 1 + 0x18 + 4 + read-write + + + OPAC0 + Off-platform Peripheral Access Control 0 + 0x1C + 4 + read-write + + + + + OPACR1 + Off-Platform Peripheral Access Control Registers + 0x44 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC15 + Off-platform Peripheral Access Control 15 + 0 + 4 + read-write + + + OPAC14 + Off-platform Peripheral Access Control 14 + 0x4 + 4 + read-write + + + OPAC13 + Off-platform Peripheral Access Control 13 + 0x8 + 4 + read-write + + + OPAC12 + Off-platform Peripheral Access Control 12 + 0xC + 4 + read-write + + + OPAC11 + Off-platform Peripheral Access Control 11 + 0x10 + 4 + read-write + + + OPAC10 + Off-platform Peripheral Access Control 10 + 0x14 + 4 + read-write + + + OPAC9 + Off-platform Peripheral Access Control 9 + 0x18 + 4 + read-write + + + OPAC8 + Off-platform Peripheral Access Control 8 + 0x1C + 4 + read-write + + + + + OPACR2 + Off-Platform Peripheral Access Control Registers + 0x48 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC23 + Off-platform Peripheral Access Control 23 + 0 + 4 + read-write + + + OPAC22 + Off-platform Peripheral Access Control 22 + 0x4 + 4 + read-write + + + OPAC21 + Off-platform Peripheral Access Control 21 + 0x8 + 4 + read-write + + + OPAC20 + Off-platform Peripheral Access Control 20 + 0xC + 4 + read-write + + + OPAC19 + Off-platform Peripheral Access Control 19 + 0x10 + 4 + read-write + + + OPAC18 + Off-platform Peripheral Access Control 18 + 0x14 + 4 + read-write + + + OPAC17 + Off-platform Peripheral Access Control 17 + 0x18 + 4 + read-write + + + OPAC16 + Off-platform Peripheral Access Control 16 + 0x1C + 4 + read-write + + + + + OPACR3 + Off-Platform Peripheral Access Control Registers + 0x4C + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC31 + Off-platform Peripheral Access Control 31 + 0 + 4 + read-write + + + OPAC30 + Off-platform Peripheral Access Control 30 + 0x4 + 4 + read-write + + + OPAC29 + Off-platform Peripheral Access Control 29 + 0x8 + 4 + read-write + + + OPAC28 + Off-platform Peripheral Access Control 28 + 0xC + 4 + read-write + + + OPAC27 + Off-platform Peripheral Access Control 27 + 0x10 + 4 + read-write + + + OPAC26 + Off-platform Peripheral Access Control 26 + 0x14 + 4 + read-write + + + OPAC25 + Off-platform Peripheral Access Control 25 + 0x18 + 4 + read-write + + + OPAC24 + Off-platform Peripheral Access Control 24 + 0x1C + 4 + read-write + + + + + OPACR4 + Off-Platform Peripheral Access Control Registers + 0x50 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC33 + Off-platform Peripheral Access Control 33 + 0x18 + 4 + read-write + + + OPAC32 + Off-platform Peripheral Access Control 32 + 0x1C + 4 + read-write + + + + + + + AIPSTZ2 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ2_ + 0x217C000 + + 0 + 0x54 + registers + + + + AIPSTZ3 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ3_ + 0x227C000 + + 0 + 0x54 + registers + + + + PWM1 + PWM + PWM + PWM1_ + 0x2080000 + PWM + + 0 + 0x18 + registers + + + PWM1 + 115 + + + + PWMCR + PWM Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + PWM Enable + 0 + 1 + read-write + + + EN_0 + PWM disabled + 0 + + + EN_1 + PWM enabled + 0x1 + + + + + REPEAT + Sample Repeat + 0x1 + 2 + read-write + + + REPEAT_0 + Use each sample once + 0 + + + REPEAT_1 + Use each sample twice + 0x1 + + + REPEAT_2 + Use each sample four times + 0x2 + + + REPEAT_3 + Use each sample eight times + 0x3 + + + + + SWR + Software Reset + 0x3 + 1 + read-write + + + SWR_0 + PWM is out of reset + 0 + + + SWR_1 + PWM is undergoing reset + 0x1 + + + + + PRESCALER + Counter Clock Prescaler Value + 0x4 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + CLKSRC + Select Clock Source + 0x10 + 2 + read-write + + + CLKSRC_0 + Clock is off + 0 + + + CLKSRC_1 + ipg_clk + 0x1 + + + CLKSRC_2 + ipg_clk_highfreq + 0x2 + + + CLKSRC_3 + ipg_clk_32k + 0x3 + + + + + POUTC + PWM Output Configuration. This bit field determines the mode of PWM output on the output pin. + 0x12 + 2 + read-write + + + POUTC_0 + Output pin is set at rollover and cleared at comparison + 0 + + + POUTC_1 + Output pin is cleared at rollover and set at comparison + 0x1 + + + POUTC_2 + PWM output is disconnected + 0x2 + + + POUTC_3 + PWM output is disconnected + 0x3 + + + + + HCTR + Half-word Data Swap Control + 0x14 + 1 + read-write + + + HCTR_0 + Half word swapping does not take place + 0 + + + HCTR_1 + Half words from write data bus are swapped + 0x1 + + + + + BCTR + Byte Data Swap Control + 0x15 + 1 + read-write + + + BCTR_0 + byte ordering remains the same + 0 + + + BCTR_1 + byte ordering is reversed + 0x1 + + + + + DBGEN + Debug Mode Enable + 0x16 + 1 + read-write + + + DBGEN_0 + Inactive in debug mode + 0 + + + DBGEN_1 + Active in debug mode + 0x1 + + + + + WAITEN + Wait Mode Enable + 0x17 + 1 + read-write + + + WAITEN_0 + Inactive in wait mode + 0 + + + WAITEN_1 + Active in wait mode + 0x1 + + + + + DOZEN + Doze Mode Enable + 0x18 + 1 + read-write + + + DOZEN_0 + Inactive in doze mode + 0 + + + DOZEN_1 + Active in doze mode + 0x1 + + + + + STOPEN + Stop Mode Enable + 0x19 + 1 + read-write + + + STOPEN_0 + Inactive in stop mode + 0 + + + STOPEN_1 + Active in stop mode + 0x1 + + + + + FWM + FIFO Water Mark + 0x1A + 2 + read-write + + + FWM_0 + FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO + 0 + + + FWM_1 + FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO + 0x1 + + + FWM_2 + FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO + 0x2 + + + FWM_3 + FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO + 0x3 + + + + + + + PWMSR + PWM Status Register + 0x4 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOAV + FIFO Available + 0 + 3 + read-only + + + FIFOAV_0 + No data available + 0 + + + FIFOAV_1 + 1 word of data in FIFO + 0x1 + + + FIFOAV_2 + 2 words of data in FIFO + 0x2 + + + FIFOAV_3 + 3 words of data in FIFO + 0x3 + + + FIFOAV_4 + 4 words of data in FIFO + 0x4 + + + FIFOAV_5 + unused + 0x5 + + + FIFOAV_6 + unused + 0x6 + + + FIFOAV_7 + unused + 0x7 + + + + + FE + FIFO Empty Status Bit + 0x3 + 1 + read-write + oneToClear + + + FE_0 + Data level is above water mark + 0 + + + FE_1 + When the data level falls below the mark set by FWM field + 0x1 + + + + + ROV + Roll-over Status. This bit shows that a roll-over event has occurred. + 0x4 + 1 + read-write + oneToClear + + + ROV_0 + Roll-over event not occurred + 0 + + + ROV_1 + Roll-over event occurred + 0x1 + + + + + CMP + Compare Status. This bit shows that a compare event has occurred. + 0x5 + 1 + read-write + oneToClear + + + CMP_0 + Compare event not occurred + 0 + + + CMP_1 + Compare event occurred + 0x1 + + + + + FWE + FIFO Write Error Status + 0x6 + 1 + read-write + oneToClear + + + FWE_0 + FIFO write error not occurred + 0 + + + FWE_1 + FIFO write error occurred + 0x1 + + + + + + + PWMIR + PWM Interrupt Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIE + FIFO Empty Interrupt Enable. This bit controls the generation of the FIFO Empty interrupt. + 0 + 1 + read-write + + + FIE_0 + FIFO Empty interrupt disabled + 0 + + + FIE_1 + FIFO Empty interrupt enabled + 0x1 + + + + + RIE + Roll-over Interrupt Enable. This bit controls the generation of the Rollover interrupt. + 0x1 + 1 + read-write + + + RIE_0 + Roll-over interrupt not enabled + 0 + + + RIE_1 + Roll-over Interrupt enabled + 0x1 + + + + + CIE + Compare Interrupt Enable. This bit controls the generation of the Compare interrupt. + 0x2 + 1 + read-write + + + CIE_0 + Compare Interrupt not enabled + 0 + + + CIE_1 + Compare Interrupt enabled + 0x1 + + + + + + + PWMSAR + PWM Sample Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE + Sample Value + 0 + 16 + read-write + + + + + PWMPR + PWM Period Register + 0x10 + 32 + read-write + 0xFFFE + 0xFFFFFFFF + + + PERIOD + Period Value + 0 + 16 + read-write + + + + + PWMCNR + PWM Counter Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value + 0 + 16 + read-only + + + + + + + PWM2 + PWM + PWM + PWM2_ + 0x2084000 + + 0 + 0x18 + registers + + + PWM2 + 116 + + + + PWM3 + PWM + PWM + PWM3_ + 0x2088000 + + 0 + 0x18 + registers + + + PWM3 + 117 + + + + PWM4 + PWM + PWM + PWM4_ + 0x208C000 + + 0 + 0x18 + registers + + + PWM4 + 118 + + + + PWM5 + PWM + PWM + PWM5_ + 0x20F0000 + + 0 + 0x18 + registers + + + PWM5 + 146 + + + + PWM6 + PWM + PWM + PWM6_ + 0x20F4000 + + 0 + 0x18 + registers + + + PWM6 + 147 + + + + PWM7 + PWM + PWM + PWM7_ + 0x20F8000 + + 0 + 0x18 + registers + + + PWM7 + 148 + + + + PWM8 + PWM + PWM + PWM8_ + 0x20FC000 + + 0 + 0x18 + registers + + + PWM8 + 149 + + + + CAN1 + CAN + CAN + CAN1_ + 0x2090000 + CAN + + 0 + 0x9E4 + registers + + + CAN1 + 142 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x5980000F + 0xFFFFFFFF + + + MAXMB + This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes + 0 + 7 + read-write + + + IDAM + This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below + 0x8 + 2 + read-write + + + IDAM_0 + Format A One full ID (standard or extended) per ID filter Table element. + 0 + + + IDAM_1 + Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + 0x1 + + + IDAM_2 + Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + 0x2 + + + IDAM_3 + Format D All frames rejected. + 0x3 + + + + + AEN + This bit is supplied for backwards compatibility reasons + 0xC + 1 + read-write + + + AEN_0 + Abort disabled + 0 + + + AEN_1 + Abort enabled + 0x1 + + + + + LPRIOEN + This bit is provided for backwards compatibility reasons + 0xD + 1 + read-write + + + LPRIOEN_0 + Local Priority disabled + 0 + + + LPRIOEN_1 + Local Priority enabled + 0x1 + + + + + IRMQ + This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK + 0x10 + 1 + read-write + + + IRMQ_0 + Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + 0 + + + IRMQ_1 + Individual Rx masking and queue feature are enabled. + 0x1 + + + + + SRXDIS + This bit defines whether FlexCAN is allowed to receive frames transmitted by itself + 0x11 + 1 + read-write + + + SRXDIS_0 + Self reception enabled + 0 + + + SRXDIS_1 + Self reception disabled + 0x1 + + + + + WAKSRC + This bit defines whether the integrated low-pass filter is applied to protect the CAN_RX input from spurious wake up + 0x13 + 1 + read-write + + + WAKSRC_0 + CAN uses the unfiltered CAN_RX input to detect recessive to dominant edges on the CAN bus. + 0 + + + WAKSRC_1 + CAN uses the filtered CAN_RX input to detect recessive to dominant edges on the CAN bus + 0x1 + + + + + LPMACK + This read-only bit indicates that CAN is either in Disable Mode or Stop Mode + 0x14 + 1 + read-only + + + LPMACK_0 + CAN not in any of the low power modes + 0 + + + LPMACK_1 + CAN is either in Disable Mode, or Stop mode + 0x1 + + + + + WRNEN + When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register + 0x15 + 1 + read-write + + + WRNEN_0 + TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + 0 + + + WRNEN_1 + TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + 0x1 + + + + + SLFWAK + This bit enables the Self Wake Up feature when CAN is in Stop Mode + 0x16 + 1 + read-write + + + SLFWAK_0 + CAN Self Wake Up feature is disabled + 0 + + + SLFWAK_1 + CAN Self Wake Up feature is enabled + 0x1 + + + + + SUPV + This bit configures some of the CAN registers to be either in Supervisor or User Mode + 0x17 + 1 + read-write + + + SUPV_0 + FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + 0 + + + SUPV_1 + FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + 0x1 + + + + + FRZACK + This read-only bit indicates that CAN is in Freeze Mode and its prescaler is stopped + 0x18 + 1 + read-only + + + FRZACK_0 + CAN not in Freeze Mode, prescaler running + 0 + + + FRZACK_1 + CAN in Freeze Mode, prescaler stopped + 0x1 + + + + + SOFTRST + When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers + 0x19 + 1 + read-write + + + SOFTRST_0 + No reset request + 0 + + + SOFTRST_1 + Reset the registers + 0x1 + + + + + WAKMSK + This bit enables the Wake Up Interrupt generation. + 0x1A + 1 + read-write + + + WAKMSK_0 + Wake Up Interrupt is disabled + 0 + + + WAKMSK_1 + Wake Up Interrupt is enabled + 0x1 + + + + + NOTRDY + This read-only bit indicates that CAN is either in Disable Mode, Stop Mode or Freeze Mode + 0x1B + 1 + read-only + + + NOTRDY_0 + CAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + 0 + + + NOTRDY_1 + CAN module is either in Disable Mode, Stop Mode or Freeze Mode + 0x1 + + + + + HALT + Assertion of this bit puts the CAN module into Freeze Mode + 0x1C + 1 + read-write + + + HALT_0 + No Freeze Mode request. + 0 + + + HALT_1 + Enters Freeze Mode if the FRZ bit is asserted. + 0x1 + + + + + RFEN + This bit controls whether the Rx FIFO feature is enabled or not + 0x1D + 1 + read-write + + + RFEN_0 + FIFO not enabled + 0 + + + RFEN_1 + FIFO enabled + 0x1 + + + + + FRZ + The FRZ bit specifies the CAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at ARM level + 0x1E + 1 + read-write + + + FRZ_0 + Not enabled to enter Freeze Mode + 0 + + + FRZ_1 + Enabled to enter Freeze Mode + 0x1 + + + + + MDIS + This bit controls whether CAN is enabled or not + 0x1F + 1 + read-write + + + MDIS_0 + Enable the CAN module + 0 + + + MDIS_1 + Disable the CAN module + 0x1 + + + + + + + CTRL1 + Control 1 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROPSEG + This 3-bit field defines the length of the Propagation Segment in the bit time + 0 + 3 + read-write + + + LOM + This bit configures CAN to operate in Listen Only Mode + 0x3 + 1 + read-write + + + LOM_0 + Listen Only Mode is deactivated + 0 + + + LOM_1 + CAN module operates in Listen Only Mode + 0x1 + + + + + LBUF + This bit defines the ordering mechanism for Message Buffer transmission + 0x4 + 1 + read-write + + + LBUF_0 + Buffer with highest priority is transmitted first + 0 + + + LBUF_1 + Lowest number buffer is transmitted first + 0x1 + + + + + TSYN + This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0 + 0x5 + 1 + read-write + + + TSYN_0 + Timer Sync feature disabled + 0 + + + TSYN_1 + Timer Sync feature enabled + 0x1 + + + + + BOFFREC + This bit defines how CAN recovers from Bus Off state + 0x6 + 1 + read-write + + + BOFFREC_0 + Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + 0 + + + BOFFREC_1 + Automatic recovering from Bus Off state disabled + 0x1 + + + + + SMP + This bit defines the sampling mode of CAN bits at the CAN_RX + 0x7 + 1 + read-write + + + SMP_0 + Just one sample is used to determine the bit value + 0 + + + SMP_1 + Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + 0x1 + + + + + RWRNMSK + This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register + 0xA + 1 + read-write + + + RWRNMSK_0 + Rx Warning Interrupt disabled + 0 + + + RWRNMSK_1 + Rx Warning Interrupt enabled + 0x1 + + + + + TWRNMSK + This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register + 0xB + 1 + read-write + + + TWRNMSK_0 + Tx Warning Interrupt disabled + 0 + + + TWRNMSK_1 + Tx Warning Interrupt enabled + 0x1 + + + + + LPB + This bit configures FlexCAN to operate in Loop-Back Mode + 0xC + 1 + read-write + + + LPB_0 + Loop Back disabled + 0 + + + LPB_1 + Loop Back enabled + 0x1 + + + + + ERRMSK + This bit provides a mask for the Error Interrupt. + 0xE + 1 + read-write + + + ERRMSK_0 + Error interrupt disabled + 0 + + + ERRMSK_1 + Error interrupt enabled + 0x1 + + + + + BOFFMSK + This bit provides a mask for the Bus Off Interrupt. + 0xF + 1 + read-write + + + BOFFMSK_0 + Bus Off interrupt disabled + 0 + + + BOFFMSK_1 + Bus Off interrupt enabled + 0x1 + + + + + PSEG2 + This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time + 0x10 + 3 + read-write + + + PSEG1 + This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time + 0x13 + 3 + read-write + + + RJW + This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period + 0x16 + 2 + read-write + + + PRESDIV + This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency + 0x18 + 8 + read-write + + + + + TIMER + Free Running Timer Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER + TIMER + 0 + 16 + read-write + + + + + RXMGMASK + Rx Mailboxes Global Mask Register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MG + These bits mask the Mailbox filter bits as shown in the figure above + 0 + 32 + read-write + + + MG_0 + the corresponding bit in the filter is "don't care" + 0 + + + MG_1 + The corresponding bit in the filter is checked against the one received + 0x1 + + + + + + + RX14MASK + Rx Buffer 14 Mask Register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX14M + These bits mask Mailbox 14 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX14M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX14M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RX15MASK + Rx Buffer 15 Mask Register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX15M + These bits mask Mailbox 15 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX15M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX15M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + ECR + Error Counter Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_ERR_COUNTER + Tx_Err_Counter + 0 + 8 + read-write + + + RX_ERR_COUNTER + Rx_Err_Counter + 0x8 + 8 + read-write + + + + + ESR1 + Error and Status 1 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAKINT + When CAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the ARM + 0 + 1 + read-write + + + WAKINT_0 + No such occurrence + 0 + + + WAKINT_1 + Indicates a recessive to dominant transition received on the CAN bus when the CAN module is in Stop Mode + 0x1 + + + + + ERRINT + This bit indicates that at least one of the Error Bits (bits 15-10) is set + 0x1 + 1 + read-write + + + ERRINT_0 + No such occurrence + 0 + + + ERRINT_1 + Indicates setting of any Error Bit in the Error and Status Register + 0x1 + + + + + BOFFINT + This bit is set when CAN enters 'Bus Off' state + 0x2 + 1 + read-write + + + BOFFINT_0 + No such occurrence + 0 + + + BOFFINT_1 + CAN module entered 'Bus Off' state + 0x1 + + + + + RX + This bit indicates if FlexCAN is receiving a message. Refer to . + 0x3 + 1 + read-only + + + RX_0 + CAN is receiving a message + 0 + + + RX_1 + CAN is transmitting a message + 0x1 + + + + + FLTCONF + If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate "Error Passive" + 0x4 + 2 + read-only + + + FLTCONF_0 + Error Active + 0 + + + FLTCONF_1 + Error Passive + 0x1 + + + + + TX + This bit indicates if CAN is transmitting a message.Refer to . + 0x6 + 1 + read-only + + + TX_0 + CAN is receiving a message + 0 + + + TX_1 + CAN is transmitting a message + 0x1 + + + + + IDLE + This bit indicates when CAN bus is in IDLE state.Refer to . + 0x7 + 1 + read-only + + + IDLE_0 + No such occurrence + 0 + + + IDLE_1 + CAN bus is now IDLE + 0x1 + + + + + RXWRN + This bit indicates when repetitive errors are occurring during message reception. + 0x8 + 1 + read-only + + + RXWRN_0 + No such occurrence + 0 + + + RXWRN_1 + Rx_Err_Counter >= 96 + 0x1 + + + + + TXWRN + This bit indicates when repetitive errors are occurring during message transmission. + 0x9 + 1 + read-only + + + TXWRN_0 + No such occurrence + 0 + + + TXWRN_1 + TX_Err_Counter >= 96 + 0x1 + + + + + STFERR + This bit indicates that a Stuffing Error has been detected. + 0xA + 1 + read-only + + + STFERR_0 + No such occurrence. + 0 + + + STFERR_1 + A Stuffing Error occurred since last read of this register. + 0x1 + + + + + FRMERR + This bit indicates that a Form Error has been detected by the receiver node, i + 0xB + 1 + read-only + + + FRMERR_0 + No such occurrence + 0 + + + FRMERR_1 + A Form Error occurred since last read of this register + 0x1 + + + + + CRCERR + This bit indicates that a CRC Error has been detected by the receiver node, i + 0xC + 1 + read-only + + + CRCERR_0 + No such occurrence + 0 + + + CRCERR_1 + A CRC error occurred since last read of this register. + 0x1 + + + + + ACKERR + This bit indicates that an Acknowledge Error has been detected by the transmitter node, i + 0xD + 1 + read-only + + + ACKERR_0 + No such occurrence + 0 + + + ACKERR_1 + An ACK error occurred since last read of this register + 0x1 + + + + + BIT0ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 0xE + 1 + read-only + + + BIT0ERR_0 + No such occurrence + 0 + + + BIT0ERR_1 + At least one bit sent as dominant is received as recessive + 0x1 + + + + + BIT1ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 0xF + 1 + read-only + + + BIT1ERR_0 + No such occurrence + 0 + + + BIT1ERR_1 + At least one bit sent as recessive is received as dominant + 0x1 + + + + + RWRNINT + If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0' to '1', meaning that the Rx error counters reached 96 + 0x10 + 1 + read-write + + + RWRNINT_0 + No such occurrence + 0 + + + RWRNINT_1 + The Rx error counter transition from < 96 to >= 96 + 0x1 + + + + + TWRNINT + If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0' to '1', meaning that the Tx error counter reached 96 + 0x11 + 1 + read-write + + + TWRNINT_0 + No such occurrence + 0 + + + TWRNINT_1 + The Tx error counter transition from < 96 to >= 96 + 0x1 + + + + + SYNCH + This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process + 0x12 + 1 + read-only + + + SYNCH_0 + FlexCAN is not synchronized to the CAN bus + 0 + + + SYNCH_1 + FlexCAN is synchronized to the CAN bus + 0x1 + + + + + + + IMASK2 + Interrupt Masks 2 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHM + Each bit enables or disables the respective CAN Message Buffer (MB32 to MB63) Interrupt + 0 + 32 + read-write + + + BUFHM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFHM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IMASK1 + Interrupt Masks 1 Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFLM + Each bit enables or disables the respective CAN Message Buffer (MB0 to MB31) Interrupt + 0 + 32 + read-write + + + BUFLM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFLM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IFLAG2 + Interrupt Flags 2 Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHI + Each bit flags the respective CAN Message Buffer (MB32 to MB63) interrupt. + 0 + 32 + read-write + + + BUFHI_0 + No such occurrence + 0 + + + BUFHI_1 + The corresponding buffer has successfully completed transmission or reception + 0x1 + + + + + + + IFLAG1 + Interrupt Flags 1 Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF4TO0I + If the Rx FIFO is not enabled, these bits flag the interrupts for MB0 to MB4 + 0 + 5 + read-write + + + BUF4TO0I_0 + No such occurrence + 0 + + + BUF4TO0I_1 + Corresponding MB completed transmission/reception + 0x1 + + + + + BUF5I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB5 + 0x5 + 1 + read-write + + + BUF5I_0 + No such occurrence + 0 + + + BUF5I_1 + MB5 completed transmission/reception or frames available in the FIFO + 0x1 + + + + + BUF6I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB6 + 0x6 + 1 + read-write + + + BUF6I_0 + No such occurrence + 0 + + + BUF6I_1 + MB6 completed transmission/reception or FIFO almost full + 0x1 + + + + + BUF7I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB7 + 0x7 + 1 + read-write + + + BUF7I_0 + No such occurrence + 0 + + + BUF7I_1 + MB7 completed transmission/reception or FIFO overflow + 0x1 + + + + + BUF31TO8I + Each bit flags the respective CAN Message Buffer (MB8 to MB31) interrupt. + 0x8 + 24 + read-write + + + BUF31TO8I_0 + No such occurrence + 0 + + + BUF31TO8I_1 + The corresponding MB has successfully completed transmission or reception + 0x1 + + + + + + + CTRL2 + Control 2 Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + EACEN + This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process + 0x10 + 1 + read-write + + + EACEN_0 + Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + 0 + + + EACEN_1 + Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + 0x1 + + + + + RRS + If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the corresponding Message Buffer in the same fashion of a Data Frame + 0x11 + 1 + read-write + + + RRS_0 + Remote Response Frame is generated + 0 + + + RRS_1 + Remote Request Frame is stored + 0x1 + + + + + MRP + If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO + 0x12 + 1 + read-write + + + MRP_0 + Matching starts from Rx FIFO and continues on Mailboxes + 0 + + + MRP_1 + Matching starts from Mailboxes and continues on Rx FIFO + 0x1 + + + + + TASD + This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus + 0x13 + 5 + read-write + + + RFFN + This 4-bit field defines the number of Rx FIFO filters according to + 0x18 + 4 + read-write + + + WRMFRZ + Enable unrestricted write access to FlexCAN memory in Freeze mode + 0x1C + 1 + read-write + + + WRMFRZ_0 + Keep the write access restricted in some regions of FlexCAN memory + 0 + + + WRMFRZ_1 + Enable unrestricted write access to FlexCAN memory + 0x1 + + + + + + + ESR2 + Error and Status 2 Register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMB + If ESR2[VPS] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either 0b1000 or 0b0000) + 0xD + 1 + read-only + + + IMB_0 + If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + 0 + + + IMB_1 + If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + 0x1 + + + + + VPS + This bit indicates whether IMB and LPTM contents are currently valid or not + 0xE + 1 + read-only + + + VPS_0 + Contents of IMB and LPTM are invalid + 0 + + + VPS_1 + Contents of IMB and LPTM are valid + 0x1 + + + + + LPTM + If ESR2[VPS] is asserted, his 7-bit field indicates the lowest number inactive Mailbox (refer to IMB bit description) + 0x10 + 7 + read-only + + + + + CRCR + CRC Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCRC + This field indicates the CRC value of the last message transmitted + 0 + 15 + read-only + + + MBCRC + This field indicates the number of the Mailbox corresponding to the value in TXCRC field. + 0x10 + 7 + read-only + + + + + RXFGMASK + Rx FIFO Global Mask Register + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FGM + These bits mask the ID Filter Table elements bits in a perfect alignment + 0 + 32 + read-write + + + FGM_0 + The corresponding bit in the filter is "don't care" + 0 + + + FGM_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RXFIR + Rx FIFO Information Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IDHIT + This 9-bit field indicates which Identifier Acceptance Filter (see Rx FIFO Structure) was hit by the received message that is in the output of the Rx FIFO + 0 + 9 + read-only + + + + + CS0 + Message Buffer 0 CS Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID0 + Message Buffer 0 ID Register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD00 + Message Buffer 0 WORD0 Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD10 + Message Buffer 0 WORD1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS1 + Message Buffer 1 CS Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID1 + Message Buffer 1 ID Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD01 + Message Buffer 1 WORD0 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD11 + Message Buffer 1 WORD1 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS2 + Message Buffer 2 CS Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID2 + Message Buffer 2 ID Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD02 + Message Buffer 2 WORD0 Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD12 + Message Buffer 2 WORD1 Register + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS3 + Message Buffer 3 CS Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID3 + Message Buffer 3 ID Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD03 + Message Buffer 3 WORD0 Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD13 + Message Buffer 3 WORD1 Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS4 + Message Buffer 4 CS Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID4 + Message Buffer 4 ID Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD04 + Message Buffer 4 WORD0 Register + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD14 + Message Buffer 4 WORD1 Register + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS5 + Message Buffer 5 CS Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID5 + Message Buffer 5 ID Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD05 + Message Buffer 5 WORD0 Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD15 + Message Buffer 5 WORD1 Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS6 + Message Buffer 6 CS Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID6 + Message Buffer 6 ID Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD06 + Message Buffer 6 WORD0 Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD16 + Message Buffer 6 WORD1 Register + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS7 + Message Buffer 7 CS Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID7 + Message Buffer 7 ID Register + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD07 + Message Buffer 7 WORD0 Register + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD17 + Message Buffer 7 WORD1 Register + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS8 + Message Buffer 8 CS Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID8 + Message Buffer 8 ID Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD08 + Message Buffer 8 WORD0 Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD18 + Message Buffer 8 WORD1 Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS9 + Message Buffer 9 CS Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID9 + Message Buffer 9 ID Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD09 + Message Buffer 9 WORD0 Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD19 + Message Buffer 9 WORD1 Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS10 + Message Buffer 10 CS Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID10 + Message Buffer 10 ID Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD010 + Message Buffer 10 WORD0 Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD110 + Message Buffer 10 WORD1 Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS11 + Message Buffer 11 CS Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID11 + Message Buffer 11 ID Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD011 + Message Buffer 11 WORD0 Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD111 + Message Buffer 11 WORD1 Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS12 + Message Buffer 12 CS Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID12 + Message Buffer 12 ID Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD012 + Message Buffer 12 WORD0 Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD112 + Message Buffer 12 WORD1 Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS13 + Message Buffer 13 CS Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID13 + Message Buffer 13 ID Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD013 + Message Buffer 13 WORD0 Register + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD113 + Message Buffer 13 WORD1 Register + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS14 + Message Buffer 14 CS Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID14 + Message Buffer 14 ID Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD014 + Message Buffer 14 WORD0 Register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD114 + Message Buffer 14 WORD1 Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS15 + Message Buffer 15 CS Register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID15 + Message Buffer 15 ID Register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD015 + Message Buffer 15 WORD0 Register + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD115 + Message Buffer 15 WORD1 Register + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS16 + Message Buffer 16 CS Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID16 + Message Buffer 16 ID Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD016 + Message Buffer 16 WORD0 Register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD116 + Message Buffer 16 WORD1 Register + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS17 + Message Buffer 17 CS Register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID17 + Message Buffer 17 ID Register + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD017 + Message Buffer 17 WORD0 Register + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD117 + Message Buffer 17 WORD1 Register + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS18 + Message Buffer 18 CS Register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID18 + Message Buffer 18 ID Register + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD018 + Message Buffer 18 WORD0 Register + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD118 + Message Buffer 18 WORD1 Register + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS19 + Message Buffer 19 CS Register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID19 + Message Buffer 19 ID Register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD019 + Message Buffer 19 WORD0 Register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD119 + Message Buffer 19 WORD1 Register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS20 + Message Buffer 20 CS Register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID20 + Message Buffer 20 ID Register + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD020 + Message Buffer 20 WORD0 Register + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD120 + Message Buffer 20 WORD1 Register + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS21 + Message Buffer 21 CS Register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID21 + Message Buffer 21 ID Register + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD021 + Message Buffer 21 WORD0 Register + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD121 + Message Buffer 21 WORD1 Register + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS22 + Message Buffer 22 CS Register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID22 + Message Buffer 22 ID Register + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD022 + Message Buffer 22 WORD0 Register + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD122 + Message Buffer 22 WORD1 Register + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS23 + Message Buffer 23 CS Register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID23 + Message Buffer 23 ID Register + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD023 + Message Buffer 23 WORD0 Register + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD123 + Message Buffer 23 WORD1 Register + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS24 + Message Buffer 24 CS Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID24 + Message Buffer 24 ID Register + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD024 + Message Buffer 24 WORD0 Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD124 + Message Buffer 24 WORD1 Register + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS25 + Message Buffer 25 CS Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID25 + Message Buffer 25 ID Register + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD025 + Message Buffer 25 WORD0 Register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD125 + Message Buffer 25 WORD1 Register + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS26 + Message Buffer 26 CS Register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID26 + Message Buffer 26 ID Register + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD026 + Message Buffer 26 WORD0 Register + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD126 + Message Buffer 26 WORD1 Register + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS27 + Message Buffer 27 CS Register + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID27 + Message Buffer 27 ID Register + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD027 + Message Buffer 27 WORD0 Register + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD127 + Message Buffer 27 WORD1 Register + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS28 + Message Buffer 28 CS Register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID28 + Message Buffer 28 ID Register + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD028 + Message Buffer 28 WORD0 Register + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD128 + Message Buffer 28 WORD1 Register + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS29 + Message Buffer 29 CS Register + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID29 + Message Buffer 29 ID Register + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD029 + Message Buffer 29 WORD0 Register + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD129 + Message Buffer 29 WORD1 Register + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS30 + Message Buffer 30 CS Register + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID30 + Message Buffer 30 ID Register + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD030 + Message Buffer 30 WORD0 Register + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD130 + Message Buffer 30 WORD1 Register + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS31 + Message Buffer 31 CS Register + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID31 + Message Buffer 31 ID Register + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD031 + Message Buffer 31 WORD0 Register + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD131 + Message Buffer 31 WORD1 Register + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS32 + Message Buffer 32 CS Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID32 + Message Buffer 32 ID Register + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD032 + Message Buffer 32 WORD0 Register + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD132 + Message Buffer 32 WORD1 Register + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS33 + Message Buffer 33 CS Register + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID33 + Message Buffer 33 ID Register + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD033 + Message Buffer 33 WORD0 Register + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD133 + Message Buffer 33 WORD1 Register + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS34 + Message Buffer 34 CS Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID34 + Message Buffer 34 ID Register + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD034 + Message Buffer 34 WORD0 Register + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD134 + Message Buffer 34 WORD1 Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS35 + Message Buffer 35 CS Register + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID35 + Message Buffer 35 ID Register + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD035 + Message Buffer 35 WORD0 Register + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD135 + Message Buffer 35 WORD1 Register + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS36 + Message Buffer 36 CS Register + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID36 + Message Buffer 36 ID Register + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD036 + Message Buffer 36 WORD0 Register + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD136 + Message Buffer 36 WORD1 Register + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS37 + Message Buffer 37 CS Register + 0x2D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID37 + Message Buffer 37 ID Register + 0x2D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD037 + Message Buffer 37 WORD0 Register + 0x2D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD137 + Message Buffer 37 WORD1 Register + 0x2DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS38 + Message Buffer 38 CS Register + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID38 + Message Buffer 38 ID Register + 0x2E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD038 + Message Buffer 38 WORD0 Register + 0x2E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD138 + Message Buffer 38 WORD1 Register + 0x2EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS39 + Message Buffer 39 CS Register + 0x2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID39 + Message Buffer 39 ID Register + 0x2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD039 + Message Buffer 39 WORD0 Register + 0x2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD139 + Message Buffer 39 WORD1 Register + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS40 + Message Buffer 40 CS Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID40 + Message Buffer 40 ID Register + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD040 + Message Buffer 40 WORD0 Register + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD140 + Message Buffer 40 WORD1 Register + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS41 + Message Buffer 41 CS Register + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID41 + Message Buffer 41 ID Register + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD041 + Message Buffer 41 WORD0 Register + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD141 + Message Buffer 41 WORD1 Register + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS42 + Message Buffer 42 CS Register + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID42 + Message Buffer 42 ID Register + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD042 + Message Buffer 42 WORD0 Register + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD142 + Message Buffer 42 WORD1 Register + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS43 + Message Buffer 43 CS Register + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID43 + Message Buffer 43 ID Register + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD043 + Message Buffer 43 WORD0 Register + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD143 + Message Buffer 43 WORD1 Register + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS44 + Message Buffer 44 CS Register + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID44 + Message Buffer 44 ID Register + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD044 + Message Buffer 44 WORD0 Register + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD144 + Message Buffer 44 WORD1 Register + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS45 + Message Buffer 45 CS Register + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID45 + Message Buffer 45 ID Register + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD045 + Message Buffer 45 WORD0 Register + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD145 + Message Buffer 45 WORD1 Register + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS46 + Message Buffer 46 CS Register + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID46 + Message Buffer 46 ID Register + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD046 + Message Buffer 46 WORD0 Register + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD146 + Message Buffer 46 WORD1 Register + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS47 + Message Buffer 47 CS Register + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID47 + Message Buffer 47 ID Register + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD047 + Message Buffer 47 WORD0 Register + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD147 + Message Buffer 47 WORD1 Register + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS48 + Message Buffer 48 CS Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID48 + Message Buffer 48 ID Register + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD048 + Message Buffer 48 WORD0 Register + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD148 + Message Buffer 48 WORD1 Register + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS49 + Message Buffer 49 CS Register + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID49 + Message Buffer 49 ID Register + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD049 + Message Buffer 49 WORD0 Register + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD149 + Message Buffer 49 WORD1 Register + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS50 + Message Buffer 50 CS Register + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID50 + Message Buffer 50 ID Register + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD050 + Message Buffer 50 WORD0 Register + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD150 + Message Buffer 50 WORD1 Register + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS51 + Message Buffer 51 CS Register + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID51 + Message Buffer 51 ID Register + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD051 + Message Buffer 51 WORD0 Register + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD151 + Message Buffer 51 WORD1 Register + 0x3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS52 + Message Buffer 52 CS Register + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID52 + Message Buffer 52 ID Register + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD052 + Message Buffer 52 WORD0 Register + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD152 + Message Buffer 52 WORD1 Register + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS53 + Message Buffer 53 CS Register + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID53 + Message Buffer 53 ID Register + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD053 + Message Buffer 53 WORD0 Register + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD153 + Message Buffer 53 WORD1 Register + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS54 + Message Buffer 54 CS Register + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID54 + Message Buffer 54 ID Register + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD054 + Message Buffer 54 WORD0 Register + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD154 + Message Buffer 54 WORD1 Register + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS55 + Message Buffer 55 CS Register + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID55 + Message Buffer 55 ID Register + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD055 + Message Buffer 55 WORD0 Register + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD155 + Message Buffer 55 WORD1 Register + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS56 + Message Buffer 56 CS Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID56 + Message Buffer 56 ID Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD056 + Message Buffer 56 WORD0 Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD156 + Message Buffer 56 WORD1 Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS57 + Message Buffer 57 CS Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID57 + Message Buffer 57 ID Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD057 + Message Buffer 57 WORD0 Register + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD157 + Message Buffer 57 WORD1 Register + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS58 + Message Buffer 58 CS Register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID58 + Message Buffer 58 ID Register + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD058 + Message Buffer 58 WORD0 Register + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD158 + Message Buffer 58 WORD1 Register + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS59 + Message Buffer 59 CS Register + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID59 + Message Buffer 59 ID Register + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD059 + Message Buffer 59 WORD0 Register + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD159 + Message Buffer 59 WORD1 Register + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS60 + Message Buffer 60 CS Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID60 + Message Buffer 60 ID Register + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD060 + Message Buffer 60 WORD0 Register + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD160 + Message Buffer 60 WORD1 Register + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS61 + Message Buffer 61 CS Register + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID61 + Message Buffer 61 ID Register + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD061 + Message Buffer 61 WORD0 Register + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD161 + Message Buffer 61 WORD1 Register + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS62 + Message Buffer 62 CS Register + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID62 + Message Buffer 62 ID Register + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD062 + Message Buffer 62 WORD0 Register + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD162 + Message Buffer 62 WORD1 Register + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS63 + Message Buffer 63 CS Register + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID63 + Message Buffer 63 ID Register + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD063 + Message Buffer 63 WORD0 Register + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD163 + Message Buffer 63 WORD1 Register + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + 64 + 0x4 + RXIMR%s + Rx Individual Mask Registers + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + MI + These bits mask both Mailbox filter and Rx FIFO ID Filter Table element in distinct ways + 0 + 32 + read-write + + + MI_0 + the corresponding bit in the filter is "don't care" + 0 + + + MI_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + GFWR + Glitch Filter Width Registers + 0x9E0 + 32 + read-write + 0x7F + 0xFFFFFFFF + + + GFWR + It determines the Glitch Filter Width + 0 + 8 + read-write + + + + + + + CAN2 + CAN + CAN + CAN2_ + 0x2094000 + + 0 + 0x9E4 + registers + + + CAN2 + 143 + + + + GPT1 + GPT + GPT + GPT1_ + 0x2098000 + GPT + + 0 + 0x28 + registers + + + GPT1 + 87 + + + + CR + GPT Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + GPT Enable + 0 + 1 + read-write + + + EN_0 + GPT is disabled. + 0 + + + EN_1 + GPT is enabled. + 0x1 + + + + + ENMOD + GPT Enable mode + 0x1 + 1 + read-write + + + ENMOD_0 + GPT counter will retain its value when it is disabled. + 0 + + + ENMOD_1 + GPT counter value is reset to 0 when it is disabled. + 0x1 + + + + + DBGEN + GPT debug mode enable + 0x2 + 1 + read-write + + + DBGEN_0 + GPT is disabled in debug mode. + 0 + + + DBGEN_1 + GPT is enabled in debug mode. + 0x1 + + + + + WAITEN + GPT Wait Mode enable + 0x3 + 1 + read-write + + + WAITEN_0 + GPT is disabled in wait mode. + 0 + + + WAITEN_1 + GPT is enabled in wait mode. + 0x1 + + + + + DOZEEN + GPT Doze Mode Enable + 0x4 + 1 + read-write + + + DOZEEN_0 + GPT is disabled in doze mode. + 0 + + + DOZEEN_1 + GPT is enabled in doze mode. + 0x1 + + + + + STOPEN + GPT Stop Mode enable + 0x5 + 1 + read-write + + + STOPEN_0 + GPT is disabled in Stop mode. + 0 + + + STOPEN_1 + GPT is enabled in Stop mode. + 0x1 + + + + + CLKSRC + Clock Source select + 0x6 + 3 + read-write + + + CLKSRC_0 + No clock + 0 + + + CLKSRC_1 + Peripheral Clock (ipg_clk) + 0x1 + + + CLKSRC_2 + High Frequency Reference Clock (ipg_clk_highfreq) + 0x2 + + + CLKSRC_3 + External Clock + 0x3 + + + CLKSRC_4 + Low Frequency Reference Clock (ipg_clk_32k) + 0x4 + + + CLKSRC_5 + Crystal oscillator as Reference Clock (ipg_clk_24M) + 0x5 + + + + + FRR + Free-Run or Restart mode + 0x9 + 1 + read-write + + + FRR_0 + Restart mode + 0 + + + FRR_1 + Free-Run mode + 0x1 + + + + + EN_24M + Enable 24 MHz clock input from crystal + 0xA + 1 + read-write + + + EN_24M_0 + 24M clock disabled + 0 + + + EN_24M_1 + 24M clock enabled + 0x1 + + + + + SWR + Software reset + 0xF + 1 + read-write + + + SWR_0 + GPT is not in reset state + 0 + + + SWR_1 + GPT is in reset state + 0x1 + + + + + IM1 + See IM2 + 0x10 + 2 + read-write + + + IM2 + IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event + 0x12 + 2 + read-write + + + IM2_0 + capture disabled + 0 + + + IM2_1 + capture on rising edge only + 0x1 + + + IM2_2 + capture on falling edge only + 0x2 + + + IM2_3 + capture on both edges + 0x3 + + + + + OM1 + See OM3 + 0x14 + 3 + read-write + + + OM2 + See OM3 + 0x17 + 3 + read-write + + + OM3 + OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode + 0x1A + 3 + read-write + + + OM3_0 + Output disconnected. No response on pin. + 0 + + + OM3_1 + Toggle output pin + 0x1 + + + OM3_2 + Clear output pin + 0x2 + + + OM3_3 + Set output pin + 0x3 + + + + + FO1 + See F03 + 0x1D + 1 + write-only + + + FO2 + See F03 + 0x1E + 1 + write-only + + + FO3 + FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register) + 0x1F + 1 + write-only + + + FO3_0 + Writing a 0 has no effect. + 0 + + + FO3_1 + Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + 0x1 + + + + + + + PR + GPT Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALER + Prescaler bits + 0 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + PRESCALER24M + Prescaler bits + 0xC + 4 + read-write + + + PRESCALER24M_0 + Divide by 1 + 0 + + + PRESCALER24M_1 + Divide by 2 + 0x1 + + + PRESCALER24M_15 + Divide by 16 + 0xF + + + + + + + SR + GPT Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1 + See OF3 + 0 + 1 + read-write + oneToClear + + + OF2 + See OF3 + 0x1 + 1 + read-write + oneToClear + + + OF3 + OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n + 0x2 + 1 + read-write + oneToClear + + + OF3_0 + Compare event has not occurred. + 0 + + + OF3_1 + Compare event has occurred. + 0x1 + + + + + IF1 + See IF2 + 0x3 + 1 + read-write + oneToClear + + + IF2 + IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n + 0x4 + 1 + read-write + oneToClear + + + IF2_0 + Capture event has not occurred. + 0 + + + IF2_1 + Capture event has occurred. + 0x1 + + + + + ROV + Rollover Flag + 0x5 + 1 + read-write + oneToClear + + + ROV_0 + Rollover has not occurred. + 0 + + + ROV_1 + Rollover has occurred. + 0x1 + + + + + + + IR + GPT Interrupt Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1IE + See OF3IE + 0 + 1 + read-write + + + OF2IE + See OF3IE + 0x1 + 1 + read-write + + + OF3IE + OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt + 0x2 + 1 + read-write + + + OF3IE_0 + Output Compare Channel n interrupt is disabled. + 0 + + + OF3IE_1 + Output Compare Channel n interrupt is enabled. + 0x1 + + + + + IF1IE + See IF2IE + 0x3 + 1 + read-write + + + IF2IE + IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable + 0x4 + 1 + read-write + + + IF2IE_0 + IF2IE Input Capture n Interrupt Enable is disabled. + 0 + + + IF2IE_1 + IF2IE Input Capture n Interrupt Enable is enabled. + 0x1 + + + + + ROVIE + Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt. + 0x5 + 1 + read-write + + + ROVIE_0 + Rollover interrupt is disabled. + 0 + + + ROVIE_1 + Rollover interrupt enabled. + 0x1 + + + + + + + OCR1 + GPT Output Compare Register 1 + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR2 + GPT Output Compare Register 2 + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR3 + GPT Output Compare Register 3 + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + ICR1 + GPT Input Capture Register 1 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + ICR2 + GPT Input Capture Register 2 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + CNT + GPT Counter Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value. The COUNT bits show the current count value of the GPT counter. + 0 + 32 + read-only + + + + + + + GPT2 + GPT + GPT + GPT2_ + 0x20E8000 + + 0 + 0x28 + registers + + + GPT2 + 141 + + + + GPIO1 + GPIO + GPIO + GPIO1_ + 0x209C000 + GPIO + + 0 + 0x20 + registers + + + GPIO1_INT7 + 90 + + + GPIO1_INT6 + 91 + + + GPIO1_INT5 + 92 + + + GPIO1_INT4 + 93 + + + GPIO1_INT3 + 94 + + + GPIO1_INT2 + 95 + + + GPIO1_INT1 + 96 + + + GPIO1_INT0 + 97 + + + GPIO1_Combined_0_15 + 98 + + + GPIO1_Combined_16_31 + 99 + + + + DR + GPIO data register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DR + Data bits + 0 + 32 + read-write + + + + + GDIR + GPIO direction register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDIR + GPIO direction bits + 0 + 32 + read-write + + + INPUT + GPIO is configured as input. + 0 + + + OUTPUT + GPIO is configured as output. + 0x1 + + + + + + + PSR + GPIO pad status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PSR + GPIO pad status bits (status bits) + 0 + 32 + read-only + + + + + ICR1 + GPIO interrupt configuration register1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR0 + Interrupt configuration 1 fields + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR1 + Interrupt configuration 1 fields + 0x2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR2 + Interrupt configuration 1 fields + 0x4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR3 + Interrupt configuration 1 fields + 0x6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR4 + Interrupt configuration 1 fields + 0x8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR5 + Interrupt configuration 1 fields + 0xA + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR6 + Interrupt configuration 1 fields + 0xC + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR7 + Interrupt configuration 1 fields + 0xE + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR8 + Interrupt configuration 1 fields + 0x10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR9 + Interrupt configuration 1 fields + 0x12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR10 + Interrupt configuration 1 fields + 0x14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR11 + Interrupt configuration 1 fields + 0x16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR12 + Interrupt configuration 1 fields + 0x18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR13 + Interrupt configuration 1 fields + 0x1A + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR14 + Interrupt configuration 1 fields + 0x1C + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR15 + Interrupt configuration 1 fields + 0x1E + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + ICR2 + GPIO interrupt configuration register2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR16 + Interrupt configuration 2 fields + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR17 + Interrupt configuration 2 fields + 0x2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR18 + Interrupt configuration 2 fields + 0x4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR19 + Interrupt configuration 2 fields + 0x6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR20 + Interrupt configuration 2 fields + 0x8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR21 + Interrupt configuration 2 fields + 0xA + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR22 + Interrupt configuration 2 fields + 0xC + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR23 + Interrupt configuration 2 fields + 0xE + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR24 + Interrupt configuration 2 fields + 0x10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR25 + Interrupt configuration 2 fields + 0x12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR26 + Interrupt configuration 2 fields + 0x14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR27 + Interrupt configuration 2 fields + 0x16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR28 + Interrupt configuration 2 fields + 0x18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR29 + Interrupt configuration 2 fields + 0x1A + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR30 + Interrupt configuration 2 fields + 0x1C + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR31 + Interrupt configuration 2 fields + 0x1E + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + IMR + GPIO interrupt mask register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR + Interrupt Mask bits + 0 + 32 + read-write + + + UNMASKED + Interrupt n is disabled. + 0 + + + MASKED + Interrupt n is enabled. + 0x1 + + + + + + + ISR + GPIO interrupt status register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISR + Interrupt status bits - Bit n of this register is asserted (active high) when the active condition (as determined by the corresponding ICR bit) is detected on the GPIO input and is waiting for service + 0 + 32 + read-write + oneToClear + + + + + EDGE_SEL + GPIO edge select register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_EDGE_SEL + Edge select + 0 + 32 + read-write + + + + + + + GPIO2 + GPIO + GPIO + GPIO2_ + 0x20A0000 + + 0 + 0x20 + registers + + + GPIO2_Combined_0_15 + 100 + + + GPIO2_Combined_16_31 + 101 + + + + GPIO3 + GPIO + GPIO + GPIO3_ + 0x20A4000 + + 0 + 0x20 + registers + + + GPIO3_Combined_0_15 + 102 + + + GPIO3_Combined_16_31 + 103 + + + + GPIO4 + GPIO + GPIO + GPIO4_ + 0x20A8000 + + 0 + 0x20 + registers + + + GPIO4_Combined_0_15 + 104 + + + GPIO4_Combined_16_31 + 105 + + + + GPIO5 + GPIO + GPIO + GPIO5_ + 0x20AC000 + + 0 + 0x20 + registers + + + GPIO5_Combined_0_15 + 106 + + + GPIO5_Combined_16_31 + 107 + + + + SNVS + SNVS + SNVS + SNVS_ + 0x20B0000 + + 0 + 0xC00 + registers + + + SNVS + 36 + + + SNVS_Consolidated + 51 + + + SNVS_Security + 52 + + + + HPLR + SNVS_HP Lock register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MC_SL + Monotonic Counter Soft Lock When set, it prevents any writes (increments) to the MC registers and the MC_ENV bit + 0x4 + 1 + read-write + + + MC_SL_0 + Write access (increment) is allowed. + 0 + + + MC_SL_1 + Write access (increment) is not allowed. + 0x1 + + + + + GPR_SL + General-Purpose Register Soft Lock When set, it prevents any writes to the GPR + 0x5 + 1 + read-write + + + GPR_SL_0 + Write access is allowed. + 0 + + + GPR_SL_1 + Write access is not allowed. + 0x1 + + + + + + + HPCOMR + SNVS_HP Command register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + LP_SWR + LP Software Reset When set, it resets the SNVS_LP section + 0x4 + 1 + write-only + + + LP_SWR_0 + No action + 0 + + + LP_SWR_1 + Reset LP section + 0x1 + + + + + LP_SWR_DIS + LP Software Reset Disable When set, it disables the LP software reset + 0x5 + 1 + read-write + + + LP_SWR_DIS_0 + LP software reset is enabled. + 0 + + + LP_SWR_DIS_1 + LP software reset is disabled. + 0x1 + + + + + NPSWA_EN + Non-Privileged Software Access Enable When set, it allows non-privileged software to access all SNVS registers, including those that are privileged-software read/write access only + 0x1F + 1 + read-write + + + + + HPCR + SNVS_HP Control register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC_EN + HP Real-Time Counter Enable + 0 + 1 + read-write + + + RTC_EN_0 + RTC is disabled. + 0 + + + RTC_EN_1 + RTC is enabled. + 0x1 + + + + + HPTA_EN + HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP time alarm registers is equal to the value of the HP real-time counter + 0x1 + 1 + read-write + + + HPTA_EN_0 + HP time alarm interrupt is disabled. + 0 + + + HPTA_EN_1 + HP time alarm interrupt is enabled. + 0x1 + + + + + PI_EN + HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP real-time counter is enabled + 0x3 + 1 + read-write + + + PI_EN_0 + HP periodic interrupt is disabled. + 0 + + + PI_EN_1 + HP periodic interrupt is enabled. + 0x1 + + + + + PI_FREQ + Periodic Interrupt Frequency Defines the frequency of the periodic interrupt + 0x4 + 4 + read-write + + + PI_FREQ_0 + - Bit 0 of the RTC is selected as the source of the periodic interrupt. + 0 + + + PI_FREQ_1 + - Bit 1 of the RTC is selected as the source of the periodic interrupt. + 0x1 + + + PI_FREQ_2 + - Bit 2 of the RTC is selected as the source of the periodic interrupt. + 0x2 + + + PI_FREQ_3 + - Bit 3 of the RTC is selected as the source of the periodic interrupt. + 0x3 + + + PI_FREQ_4 + - Bit 4 of the RTC is selected as the source of the periodic interrupt. + 0x4 + + + PI_FREQ_5 + - Bit 5 of the RTC is selected as the source of the periodic interrupt. + 0x5 + + + PI_FREQ_6 + - Bit 6 of the RTC is selected as the source of the periodic interrupt. + 0x6 + + + PI_FREQ_7 + - Bit 7 of the RTC is selected as the source of the periodic interrupt. + 0x7 + + + PI_FREQ_8 + - Bit 8 of the RTC is selected as the source of the periodic interrupt. + 0x8 + + + PI_FREQ_9 + - Bit 9 of the RTC is selected as the source of the periodic interrupt. + 0x9 + + + PI_FREQ_10 + - Bit 10 of the RTC is selected as the source of the periodic interrupt. + 0xA + + + PI_FREQ_11 + - Bit 11 of the RTC is selected as the source of the periodic interrupt. + 0xB + + + PI_FREQ_12 + - Bit 12 of the RTC is selected as the source of the periodic interrupt. + 0xC + + + PI_FREQ_13 + - Bit 13 of the RTC is selected as the source of the periodic interrupt. + 0xD + + + PI_FREQ_14 + - Bit 14 of the RTC is selected as the source of the periodic interrupt. + 0xE + + + PI_FREQ_15 + - Bit 15 of the RTC is selected as the source of the periodic interrupt. + 0xF + + + + + HPCALB_EN + HP Real-Time Counter Calibration Enabled Indicates that the time-calibration mechanism is enabled. + 0x8 + 1 + read-write + + + HPCALB_EN_0 + HP timer calibration is disabled. + 0 + + + HPCALB_EN_1 + HP timer calibration is enabled. + 0x1 + + + + + HPCALB_VAL + HP Calibration Value Defines the signed calibration value for the HP real-time counter + 0xA + 5 + read-write + + + HPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter + 0 + + + HPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter + 0x1 + + + HPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter + 0x2 + + + HPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter + 0xF + + + HPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter + 0x10 + + + HPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter + 0x11 + + + HPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter + 0x1E + + + HPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter + 0x1F + + + + + BTN_CONFIG + Button configuration + 0x18 + 3 + read-write + + + BTN_MASK + Button interrupt mask + 0x1B + 1 + read-write + + + + + HPSR + SNVS_HP Status register + 0x14 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + BTN + Value of the BTN input + 0x6 + 1 + read-only + + + BI + Button interrupt. The ipi_snvs_btn_int_b signal was asserted. + 0x7 + 1 + read-write + oneToClear + + + + + HPRTCMR + SNVS_HP Real-Time Counter MSB Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real-Time Counter Most significant 32 bits + 0 + 32 + read-write + + + + + HPRTCLR + SNVS_HP Real-Time Counter LSB Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real-Time Counter Least significant 32 bits + 0 + 32 + read-write + + + + + HPTAMR + SNVS_HP Time Alarm MSB Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA + HP Time Alarm Most significant 15 bits + 0 + 15 + read-write + + + + + HPTALR + SNVS_HP Time Alarm LSB Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA + HP Time Alarm The least significant bits + 0 + 32 + read-write + + + + + LPLR + SNVS_LP Lock Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MC_HL + Monotonic Counter Hard Lock When set, it blocks any writes (increments) to the MC registers and the MC_ENV bit + 0x4 + 1 + read-write + + + MC_HL_0 + Write access (increment) is allowed. + 0 + + + MC_HL_1 + Write access (increment) is not allowed. + 0x1 + + + + + GPR_HL + General-Purpose Register Hard Lock When set, it blocks any writes to the GPR + 0x5 + 1 + read-write + + + GPR_HL_0 + Write access is allowed. + 0 + + + GPR_HL_1 + Write access is not allowed. + 0x1 + + + + + + + LPCR + SNVS_LP Control Register + 0x38 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + MC_ENV + Monotonic Counter Enable and Valid When set, the MC can be incremented (by a write transaction to the LPSMCMR or LPSMCLR) + 0x2 + 1 + read-write + + + MC_ENV_0 + MC is disabled or invalid. + 0 + + + MC_ENV_1 + MC is enabled and valid. + 0x1 + + + + + DP_EN + Dumb PMIC Enabled When set, the software can control the system power + 0x5 + 1 + read-write + + + DP_EN_0 + Smart PMIC is enabled. + 0 + + + DP_EN_1 + Dumb PMIC is enabled. + 0x1 + + + + + TOP + Turn off System Power Asserting this bit causes a signal to be sent to the power management IC to turn the system power off + 0x6 + 1 + read-write + + + TOP_0 + Leave the system power on. + 0 + + + TOP_1 + Turn the system power off. + 0x1 + + + + + PWR_GLITCH_EN + By default, the detection of a power glitch does not cause the pmic_en_b signal to be asserted + 0x7 + 1 + read-write + + + BTN_PRESS_TIME + Button press timeout values for the PMIC logic + 0x10 + 2 + read-write + + + DEBOUNCE + This field configures the amount of debounce time for the BTN input signal + 0x12 + 2 + read-write + + + ON_TIME + The ON_TIME field is used to configure the period of time after the BTN is asserted before the pmic_en_b is asserted to turn on the SoC power + 0x14 + 2 + read-write + + + PK_EN + PMIC On Request Enable + 0x16 + 1 + read-write + + + PK_OVERRIDE + PMIC On Request Override + 0x17 + 1 + read-write + + + + + LPSR + SNVS_LP Status Register + 0x4C + 32 + read-write + 0x8 + 0xFFFFFFFF + + + MCR + Monotonic Counter Rollover + 0x2 + 1 + read-write + oneToClear + + + MCR_0 + MC did not reach its maximum value. + 0 + + + MCR_1 + MC reached its maximum value. + 0x1 + + + + + EO + Emergency Off This bit is set when a power off is requested. + 0x11 + 1 + read-write + oneToClear + + + EO_0 + Emergency off is not detected. + 0 + + + EO_1 + Emergency off is detected. + 0x1 + + + + + SPO + Set Power Off The SPO bit is set when the set_pwr_off_irq interrupt is triggered, which happens when the software writes a 1 to the TOP bit in the LPCR or when the power button is pressed longer than the configured debounce time + 0x12 + 1 + read-write + oneToClear + + + SPO_0 + Emergency off is not detected. + 0 + + + SPO_1 + Emergency off is detected. + 0x1 + + + + + + + LPSMCMR + SNVS_LP Secure Monotonic Counter MSB Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter Most-Significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR register or the LPSMCLR register is detected + 0 + 16 + read-write + + + MC_ERA_BITS + Monotonic Counter Era Bits These bits are the inputs to the module and are typically connected to the fuses + 0x10 + 16 + read-write + + + + + LPSMCLR + SNVS_LP Secure Monotonic Counter LSB Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR register or the LPSMCLR register is detected + 0 + 32 + read-write + + + + + LPGPR + SNVS_LP General-Purpose Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General-Purpose Register When the GPR_SL or GPR_HL bit is set, the register can't be programmed. + 0 + 32 + read-write + + + + + HPVIDR1 + SNVS_HP Version ID Register 1 + 0xBF8 + 32 + read-only + 0x3E0300 + 0xFFFFFFFF + + + MINOR_REV + SNVS block minor version number + 0 + 8 + read-only + + + MAJOR_REV + SNVS block major version number + 0x8 + 8 + read-only + + + IP_ID + SNVS block ID + 0x10 + 16 + read-only + + + + + HPVIDR2 + SNVS_HP Version ID Register 2 + 0xBFC + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + CONFIG_OPT + SNVS Configuration Option + 0 + 8 + read-only + + + ECO_REV + SNVS ECO Revision + 0x8 + 8 + read-only + + + INTG_OPT + SNVS Integration Option + 0x10 + 8 + read-only + + + IP_ERA + Era of the IP design + 0x18 + 8 + read-only + + + + + + + KPP + KPP Registers + KPP + KPP_ + 0x20B8000 + + 0 + 0x8 + registers + + + KPP + 114 + + + + KPCR + Keypad Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + KRE + Keypad Row Enable + 0 + 8 + read-write + + + KRE_0 + Row is not included in the keypad key press detect. + 0 + + + KRE_1 + Row is included in the keypad key press detect. + 0x1 + + + + + KCO + Keypad Column Strobe Open-Drain Enable + 0x8 + 8 + read-write + + + TOTEM_POLE + Column strobe output is totem pole drive. + 0 + + + OPEN_DRAIN + Column strobe output is open drain. + 0x1 + + + + + + + KPSR + Keypad Status Register + 0x2 + 16 + read-write + 0x400 + 0xFFFF + + + KPKD + Keypad Key Depress + 0 + 1 + read-write + oneToClear + + + KPKD_0 + No key presses detected + 0 + + + KPKD_1 + A key has been depressed + 0x1 + + + + + KPKR + Keypad Key Release + 0x1 + 1 + read-write + oneToClear + + + KPKR_0 + No key release detected + 0 + + + KPKR_1 + All keys have been released + 0x1 + + + + + KDSC + Key Depress Synchronizer Clear + 0x2 + 1 + write-only + + + KDSC_0 + No effect + 0 + + + KDSC_1 + Set bits that clear the keypad depress synchronizer chain + 0x1 + + + + + KRSS + Key Release Synchronizer Set + 0x3 + 1 + write-only + + + KRSS_0 + No effect + 0 + + + KRSS_1 + Set bits which sets keypad release synchronizer chain + 0x1 + + + + + KDIE + Keypad Key Depress Interrupt Enable + 0x8 + 1 + read-write + + + KDIE_0 + No interrupt request is generated when KPKD is set. + 0 + + + KDIE_1 + An interrupt request is generated when KPKD is set. + 0x1 + + + + + KRIE + Keypad Release Interrupt Enable + 0x9 + 1 + read-write + + + KRIE_0 + No interrupt request is generated when KPKR is set. + 0 + + + KRIE_1 + An interrupt request is generated when KPKR is set. + 0x1 + + + + + + + KDDR + Keypad Data Direction Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + KRDD + Keypad Row Data Direction + 0 + 8 + read-write + + + INPUT + ROWn pin configured as an input. + 0 + + + OUTPUT + ROWn pin configured as an output. + 0x1 + + + + + KCDD + Keypad Column Data Direction Register + 0x8 + 8 + read-write + + + INPUT + COLn pin is configured as an input. + 0 + + + OUTPUT + COLn pin is configured as an output. + 0x1 + + + + + + + KPDR + Keypad Data Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + KRD + Keypad Row Data + 0 + 8 + read-write + + + KCD + Keypad Column Data + 0x8 + 8 + read-write + + + + + + + WDOG1 + WDOG + WDOG + WDOG1_ + 0x20BC000 + WDOG + + 0 + 0xA + registers + + + WDOG1 + 112 + + + + WCR + Watchdog Control Register + 0 + 16 + read-write + 0x30 + 0xFFFF + + + WDZST + Watchdog Low Power + 0 + 1 + read-write + + + WDZST_0 + Continue timer operation (Default). + 0 + + + WDZST_1 + Suspend the watchdog timer. + 0x1 + + + + + WDBG + Watchdog DEBUG Enable + 0x1 + 1 + read-write + + + WDBG_0 + Continue WDOG timer operation (Default). + 0 + + + WDBG_1 + Suspend the watchdog timer. + 0x1 + + + + + WDE + Watchdog Enable + 0x2 + 1 + read-write + + + WDE_0 + Disable the Watchdog (Default). + 0 + + + WDE_1 + Enable the Watchdog. + 0x1 + + + + + WDT + WDOG_B Time-out assertion + 0x3 + 1 + read-write + + + WDT_0 + No effect on WDOG_B (Default). + 0 + + + WDT_1 + Assert WDOG_B upon a Watchdog Time-out event. + 0x1 + + + + + SRS + Software Reset Signal + 0x4 + 1 + read-write + + + SRS_0 + Assert system reset signal. + 0 + + + SRS_1 + No effect on the system (Default). + 0x1 + + + + + WDA + WDOG_B assertion. Controls the software assertion of the WDOG_B signal. + 0x5 + 1 + read-write + + + WDA_0 + Assert WDOG_B output. + 0 + + + WDA_1 + No effect on system (Default). + 0x1 + + + + + SRE + software reset extension, an option way to generate software reset + 0x6 + 1 + read-write + + + SRE_0 + using original way to generate software reset (default) + 0 + + + SRE_1 + using new way to generate software reset. + 0x1 + + + + + WDW + Watchdog Disable for Wait + 0x7 + 1 + read-write + + + WDW_0 + Continue WDOG timer operation (Default). + 0 + + + WDW_1 + Suspend WDOG timer operation. + 0x1 + + + + + WT + Watchdog Time-out Field + 0x8 + 8 + read-write + + + WT_0 + - 0.5 Seconds (Default). + 0 + + + WT_1 + - 1.0 Seconds. + 0x1 + + + WT_2 + - 1.5 Seconds. + 0x2 + + + WT_3 + - 2.0 Seconds. + 0x3 + + + WT_255 + - 128 Seconds. + 0xFF + + + + + + + WSR + Watchdog Service Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + WSR + Watchdog Service Register + 0 + 16 + read-write + + + WSR_21845 + Write to the Watchdog Service Register (WDOG_WSR). + 0x5555 + + + WSR_43690 + Write to the Watchdog Service Register (WDOG_WSR). + 0xAAAA + + + + + + + WRSR + Watchdog Reset Status Register + 0x4 + 16 + read-only + 0 + 0xFFFF + + + SFTW + Software Reset + 0 + 1 + read-only + + + SFTW_0 + Reset is not the result of a software reset. + 0 + + + SFTW_1 + Reset is the result of a software reset. + 0x1 + + + + + TOUT + Timeout. Indicates whether the reset is the result of a WDOG timeout. + 0x1 + 1 + read-only + + + TOUT_0 + Reset is not the result of a WDOG timeout. + 0 + + + TOUT_1 + Reset is the result of a WDOG timeout. + 0x1 + + + + + POR + Power On Reset. Indicates whether the reset is the result of a power on reset. + 0x4 + 1 + read-only + + + POR_0 + Reset is not the result of a power on reset. + 0 + + + POR_1 + Reset is the result of a power on reset. + 0x1 + + + + + + + WICR + Watchdog Interrupt Control Register + 0x6 + 16 + read-write + 0x4 + 0xFFFF + + + WICT + Watchdog Interrupt Count Time-out (WICT) field determines, how long before the counter time-out must the interrupt occur + 0 + 8 + read-write + + + WICT_0 + WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + 0 + + + WICT_1 + WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + 0x1 + + + WICT_4 + WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + 0x4 + + + WICT_255 + WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + 0xFF + + + + + WTIS + Watchdog TImer Interrupt Status bit will reflect the timer interrupt status, whether interrupt has occurred or not + 0xE + 1 + read-write + oneToClear + + + WTIS_0 + No interrupt has occurred (Default). + 0 + + + WTIS_1 + Interrupt has occurred + 0x1 + + + + + WIE + Watchdog Timer Interrupt enable bit + 0xF + 1 + read-write + + + WIE_0 + Disable Interrupt (Default). + 0 + + + WIE_1 + Enable Interrupt. + 0x1 + + + + + + + WMCR + Watchdog Miscellaneous Control Register + 0x8 + 16 + read-write + 0x1 + 0xFFFF + + + PDE + Power Down Enable bit + 0 + 1 + read-write + + + PDE_0 + Power Down Counter of WDOG is disabled. + 0 + + + PDE_1 + Power Down Counter of WDOG is enabled (Default). + 0x1 + + + + + + + + + WDOG2 + WDOG + WDOG + WDOG2_ + 0x20C0000 + + 0 + 0xA + registers + + + WDOG2 + 113 + + + + WDOG3 + WDOG + WDOG + WDOG3_ + 0x21E4000 + + 0 + 0xA + registers + + + WDOG3 + 43 + + + + CCM + CCM + CCM + CCM_ + 0x20C4000 + + 0 + 0x8C + registers + + + CCM_IRQ1 + 119 + + + CCM_IRQ2 + 120 + + + + CCR + CCM Control Register + 0 + 32 + read-write + 0x401167F + 0xFFFFFFFF + + + OSCNT + Oscillator ready counter value + 0 + 7 + read-write + + + OSCNT_0 + count 1 ckil + 0 + + + OSCNT_127 + count 128 ckil's + 0x7F + + + + + COSC_EN + On chip oscillator enable bit - this bit value is reflected on the output cosc_en + 0xC + 1 + read-write + + + COSC_EN_0 + disable on chip oscillator + 0 + + + COSC_EN_1 + enable on chip oscillator + 0x1 + + + + + REG_BYPASS_COUNT + Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ + 0x15 + 6 + read-write + + + REG_BYPASS_COUNT_0 + no delay + 0 + + + REG_BYPASS_COUNT_1 + 1 CKIL clock period delay + 0x1 + + + REG_BYPASS_COUNT_63 + 63 CKIL clock periods delay + 0x3F + + + + + RBC_EN + Enable for REG_BYPASS_COUNTER + 0x1B + 1 + read-write + + + RBC_EN_0 + REG_BYPASS_COUNTER disabled + 0 + + + RBC_EN_1 + REG_BYPASS_COUNTER enabled. + 0x1 + + + + + + + CCDR + CCM Control Divider Register + 0x4 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + MMDC_MASK + During divider ratio mmdc_axi_podf change or sync mux periph2_clk_sel change (but not jtag) or SRC request during warm reset, mask handshake with mmdc module + 0x10 + 1 + read-write + + + MMDC_MASK_0 + Allow handshake with mmdc module. + 0 + + + MMDC_MASK_1 + Mask handshake with mmdc. Request signal will not be generated. + 0x1 + + + + + + + CSR + CCM Status Register + 0x8 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + REF_EN_B + Status of the value of CCM_REF_EN_B output of ccm + 0 + 1 + read-only + + + REF_EN_B_0 + value of CCM_REF_EN_B is '0' + 0 + + + REF_EN_B_1 + value of CCM_REF_EN_B is '1' + 0x1 + + + + + COSC_READY + Status indication of on board oscillator + 0x5 + 1 + read-only + + + COSC_READY_0 + on board oscillator is not ready. + 0 + + + COSC_READY_1 + on board oscillator is ready. + 0x1 + + + + + + + CCSR + CCM Clock Switcher Register + 0xC + 32 + read-write + 0x100 + 0xFFFFFFFF + + + PLL3_SW_CLK_SEL + Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes. + 0 + 1 + read-write + + + PLL3_SW_CLK_SEL_0 + pll3_main_clk + 0 + + + PLL3_SW_CLK_SEL_1 + pll3 bypass clock + 0x1 + + + + + PLL1_SW_CLK_SEL + Selects source to generate pll1_sw_clk. + 0x2 + 1 + read-write + + + PLL1_SW_CLK_SEL_0 + pll1_main_clk + 0 + + + PLL1_SW_CLK_SEL_1 + step_clk + 0x1 + + + + + SECONDARY_CLK_SEL + Select source to generate secondary_clk + 0x3 + 1 + read-write + + + SECONDARY_CLK_SEL_0 + PLL2 PFD2 (400 M) + 0 + + + SECONDARY_CLK_SEL_1 + PLL2 (528 M) + 0x1 + + + + + STEP_SEL + Selects the option to be chosen for the step frequency when shifting ARM frequency + 0x8 + 1 + read-write + + + STEP_SEL_0 + derive clock from osc_clk (24M) - source for lp_apm. + 0 + + + STEP_SEL_1 + derive clock from secondary_clk + 0x1 + + + + + + + CACRR + CCM Arm Clock Root Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARM_PODF + Divider for ARM clock root + 0 + 3 + read-write + + + ARM_PODF_0 + divide by 1 + 0 + + + ARM_PODF_1 + divide by 2 + 0x1 + + + ARM_PODF_2 + divide by 3 + 0x2 + + + ARM_PODF_3 + divide by 4 + 0x3 + + + ARM_PODF_4 + divide by 5 + 0x4 + + + ARM_PODF_5 + divide by 6 + 0x5 + + + ARM_PODF_6 + divide by 7 + 0x6 + + + ARM_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCDR + CCM Bus Clock Divider Register + 0x14 + 32 + read-write + 0x18D00 + 0xFFFFFFFF + + + PERIPH2_CLK2_PODF + Divider for periph2_clk2 podf. Divider should be updated when output clock is gated. + 0 + 3 + read-write + + + PERIPH2_CLK2_PODF_0 + divide by 1 + 0 + + + PERIPH2_CLK2_PODF_1 + divide by 2 + 0x1 + + + PERIPH2_CLK2_PODF_2 + divide by 3 + 0x2 + + + PERIPH2_CLK2_PODF_3 + divide by 4 + 0x3 + + + PERIPH2_CLK2_PODF_4 + divide by 5 + 0x4 + + + PERIPH2_CLK2_PODF_5 + divide by 6 + 0x5 + + + PERIPH2_CLK2_PODF_6 + divide by 7 + 0x6 + + + PERIPH2_CLK2_PODF_7 + divide by 8 + 0x7 + + + + + FABRIC_MMDC_PODF + Post divider for fabric / mmdc clock. + 0x3 + 3 + read-write + + + FABRIC_MMDC_PODF_0 + divide by 1 + 0 + + + FABRIC_MMDC_PODF_1 + divide by 2 + 0x1 + + + FABRIC_MMDC_PODF_2 + divide by 3 + 0x2 + + + FABRIC_MMDC_PODF_3 + divide by 4 + 0x3 + + + FABRIC_MMDC_PODF_4 + divide by 5 + 0x4 + + + FABRIC_MMDC_PODF_5 + divide by 6 + 0x5 + + + FABRIC_MMDC_PODF_6 + divide by 7 + 0x6 + + + FABRIC_MMDC_PODF_7 + divide by 8 + 0x7 + + + + + AXI_CLK_SEL + AXI clock source select + 0x6 + 1 + read-write + + + AXI_CLK_SEL_0 + Periph_clk output will be used as AXI clock root + 0 + + + AXI_CLK_SEL_1 + AXI alternative clock will be used as AXI clock root + 0x1 + + + + + AXI_ALT_CLK_SEL + AXI alternative clock select + 0x7 + 1 + read-write + + + AXI_ALT_CLK_SEL_0 + PLL2 PFD2 will be selected as alternative clock for AXI root clock + 0 + + + AXI_ALT_CLK_SEL_1 + PLL3 PFD1 will be selected as alternative clock for AXI root clock + 0x1 + + + + + IPG_PODF + Divider for ipg podf + 0x8 + 2 + read-write + + + IPG_PODF_0 + divide by 1 + 0 + + + IPG_PODF_1 + divide by 2 + 0x1 + + + IPG_PODF_2 + divide by 3 + 0x2 + + + IPG_PODF_3 + divide by 4 + 0x3 + + + + + AHB_PODF + Divider for AHB PODF + 0xA + 3 + read-write + + + AHB_PODF_0 + divide by 1 + 0 + + + AHB_PODF_1 + divide by 2 + 0x1 + + + AHB_PODF_2 + divide by 3 + 0x2 + + + AHB_PODF_3 + divide by 4 + 0x3 + + + AHB_PODF_4 + divide by 5 + 0x4 + + + AHB_PODF_5 + divide by 6 + 0x5 + + + AHB_PODF_6 + divide by 7 + 0x6 + + + AHB_PODF_7 + divide by 8 + 0x7 + + + + + AXI_PODF + Post divider for axi clock + 0x10 + 3 + read-write + + + AXI_PODF_0 + Divide by 1 + 0 + + + AXI_PODF_1 + Divide by 2 + 0x1 + + + AXI_PODF_2 + Divide by 3 + 0x2 + + + AXI_PODF_3 + Divide by 4 + 0x3 + + + AXI_PODF_4 + Divide by 5 + 0x4 + + + AXI_PODF_5 + Divide by 6 + 0x5 + + + AXI_PODF_6 + Divide by 7 + 0x6 + + + AXI_PODF_7 + Divide by 8 + 0x7 + + + + + PERIPH_CLK_SEL + Selector for peripheral main clock) + 0x19 + 1 + read-write + + + PERIPH_CLK_SEL_0 + PLL2 (pll2_main_clk) + 0 + + + PERIPH_CLK_SEL_1 + derive clock from periph_clk2_clk clock source. + 0x1 + + + + + PERIPH2_CLK_SEL + Selector for peripheral2 main clock (source of mmdc_clk_root ) + 0x1A + 1 + read-write + + + PERIPH2_CLK_SEL_0 + PLL2 (pll2_main_clk) + 0 + + + PERIPH2_CLK_SEL_1 + derive clock from periph2_clk2_clk clock source. + 0x1 + + + + + PERIPH_CLK2_PODF + Divider for periph_clk2_podf. + 0x1B + 3 + read-write + + + PERIPH_CLK2_PODF_0 + divide by 1 + 0 + + + PERIPH_CLK2_PODF_1 + divide by 2 + 0x1 + + + PERIPH_CLK2_PODF_2 + divide by 3 + 0x2 + + + PERIPH_CLK2_PODF_3 + divide by 4 + 0x3 + + + PERIPH_CLK2_PODF_4 + divide by 5 + 0x4 + + + PERIPH_CLK2_PODF_5 + divide by 6 + 0x5 + + + PERIPH_CLK2_PODF_6 + divide by 7 + 0x6 + + + PERIPH_CLK2_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCMR + CCM Bus Clock Multiplexer Register + 0x18 + 32 + read-write + 0x24860324 + 0xFFFFFFFF + + + PERIPH_CLK2_SEL + Selector for peripheral clk2 clock multiplexer + 0xC + 2 + read-write + + + PERIPH_CLK2_SEL_0 + derive clock from pll3_sw_clk + 0 + + + PERIPH_CLK2_SEL_1 + derive clock from osc_clk (pll1_ref_clk) + 0x1 + + + PERIPH_CLK2_SEL_2 + derive clock from pll2_bypass_clk + 0x2 + + + + + PRE_PERIPH_CLK_SEL + Selector for pre_periph clock multiplexer + 0x12 + 2 + read-write + + + PRE_PERIPH_CLK_SEL_0 + derive clock from PLL2 + 0 + + + PRE_PERIPH_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + PRE_PERIPH_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + PRE_PERIPH_CLK_SEL_3 + derive clock from divided (/2) PLL2 PFD2 + 0x3 + + + + + PERIPH2_CLK2_SEL + Selector for periph2_clk2 clock multiplexer + 0x14 + 1 + read-write + + + PERIPH2_CLK2_SEL_0 + derive clock from pll3_sw_clk + 0 + + + PERIPH2_CLK2_SEL_1 + derive clock fromOSC + 0x1 + + + + + PRE_PERIPH2_CLK_SEL + Selector for pre_periph2 clock multiplexer + 0x15 + 2 + read-write + + + PRE_PERIPH2_CLK_SEL_0 + derive clock from PLL2 + 0 + + + PRE_PERIPH2_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + PRE_PERIPH2_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + PRE_PERIPH2_CLK_SEL_3 + derive clock from PLL4 + 0x3 + + + + + LCDIF1_PODF + Post-divider for lcdif1 clock. + 0x17 + 3 + read-write + + + LCDIF1_PODF_0 + divide by 1 + 0 + + + LCDIF1_PODF_1 + divide by 2 + 0x1 + + + LCDIF1_PODF_2 + divide by 3 + 0x2 + + + LCDIF1_PODF_3 + divide by 4 + 0x3 + + + LCDIF1_PODF_4 + divide by 5 + 0x4 + + + LCDIF1_PODF_5 + divide by 6 + 0x5 + + + LCDIF1_PODF_6 + divide by 7 + 0x6 + + + LCDIF1_PODF_7 + divide by 8 + 0x7 + + + + + + + CSCMR1 + CCM Serial Clock Multiplexer Register 1 + 0x1C + 32 + read-write + 0x4900080 + 0xFFFFFFFF + + + PERCLK_PODF + Divider for perclk podf. + 0 + 6 + read-write + + + PERCLK_PODF_0 + divide by 1 + 0 + + + PERCLK_PODF_1 + divide by 2 + 0x1 + + + PERCLK_PODF_2 + divide by 3 + 0x2 + + + PERCLK_PODF_3 + divide by 4 + 0x3 + + + PERCLK_PODF_4 + divide by 5 + 0x4 + + + PERCLK_PODF_5 + divide by 6 + 0x5 + + + PERCLK_PODF_6 + divide by 7 + 0x6 + + + PERCLK_PODF_7 + divide by 8 + 0x7 + + + + + PERCLK_CLK_SEL + Selector for the perclk clock multiplexor + 0x6 + 1 + read-write + + + PERCLK_CLK_SEL_0 + derive clock from ipg clk root + 0 + + + PERCLK_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + QSPI1_CLK_SEL + QSPI1 clock select + 0x7 + 3 + read-write + + + QSPI1_CLK_SEL_0 + Derive clock from PLL3 + 0 + + + QSPI1_CLK_SEL_1 + Derive clock from PLL2 PFD0 + 0x1 + + + QSPI1_CLK_SEL_2 + Derive clock from PLL2 PFD2 + 0x2 + + + QSPI1_CLK_SEL_3 + Derive clock from PLL2 + 0x3 + + + QSPI1_CLK_SEL_4 + Derive clock from PLL3 PFD3 + 0x4 + + + QSPI1_CLK_SEL_5 + Derive clock from PLL3 PFD2 + 0x5 + + + + + SAI1_CLK_SEL + Selector for sai1 clock multiplexer + 0xA + 2 + read-write + + + SAI1_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI1_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI1_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI2_CLK_SEL + Selector for sai2 clock multiplexer + 0xC + 2 + read-write + + + SAI2_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI2_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI2_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI3_CLK_SEL + Selector for sai3 clock multiplexer + 0xE + 2 + read-write + + + SAI3_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI3_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI3_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + USDHC1_CLK_SEL + Selector for usdhc1 clock multiplexer + 0x10 + 1 + read-write + + + USDHC1_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC1_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + USDHC2_CLK_SEL + Selector for usdhc2 clock multiplexer + 0x11 + 1 + read-write + + + USDHC2_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC2_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + BCH_CLK_SEL + Selector for bch clock multiplexer + 0x12 + 1 + read-write + + + BCH_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + BCH_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + GPMI_CLK_SEL + Selector for gpmi clock multiplexer + 0x13 + 1 + read-write + + + GPMI_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + GPMI_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + ACLK_EIM_SLOW_PODF + Divider for aclk_eim_slow clock root. + 0x17 + 3 + read-write + + + ACLK_EIM_SLOW_PODF_0 + divide by 1 + 0 + + + ACLK_EIM_SLOW_PODF_1 + divide by 2 + 0x1 + + + ACLK_EIM_SLOW_PODF_2 + divide by 3 + 0x2 + + + ACLK_EIM_SLOW_PODF_3 + divide by 4 + 0x3 + + + ACLK_EIM_SLOW_PODF_4 + divide by 5 + 0x4 + + + ACLK_EIM_SLOW_PODF_5 + divide by 6 + 0x5 + + + ACLK_EIM_SLOW_PODF_6 + divide by 7 + 0x6 + + + ACLK_EIM_SLOW_PODF_7 + divide by 8 + 0x7 + + + + + QSPI1_PODF + Divider for QSPI1 clock root + 0x1A + 3 + read-write + + + QSPI1_PODF_0 + divide by 1 + 0 + + + QSPI1_PODF_1 + divide by 2 + 0x1 + + + QSPI1_PODF_7 + divide by 8 + 0x7 + + + + + ACLK_EIM_SLOW_SEL + Selector for aclk_eim_slow root clock multiplexer + 0x1D + 2 + read-write + + + ACLK_EIM_SLOW_SEL_0 + derive clock from AXI + 0 + + + ACLK_EIM_SLOW_SEL_1 + derive clock from pll3_sw_clk + 0x1 + + + ACLK_EIM_SLOW_SEL_2 + derive clock from PLL2 PFD2 + 0x2 + + + ACLK_EIM_SLOW_SEL_3 + derive clock from PLL3 PFD0 + 0x3 + + + + + + + CSCMR2 + CCM Serial Clock Multiplexer Register 2 + 0x20 + 32 + read-write + 0x3192F06 + 0xFFFFFFFF + + + CAN_CLK_PODF + Divider for can clock podf. + 0x2 + 6 + read-write + + + CAN_CLK_PODF_0 + divide by 1 + 0 + + + CAN_CLK_PODF_7 + divide by 8 + 0x7 + + + CAN_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + CAN_CLK_SEL + Selector for FlexCAN clock multiplexer + 0x8 + 2 + read-write + + + CAN_CLK_SEL_0 + derive clock from pll3_sw_clk divided clock (60M) + 0 + + + CAN_CLK_SEL_1 + derive clock from osc_clk (24M) + 0x1 + + + CAN_CLK_SEL_2 + derive clock from pll3_sw_clk divided clock (80M) + 0x2 + + + CAN_CLK_SEL_3 + Disable FlexCAN clock + 0x3 + + + + + LDB_DI0_DIV + Control for divider of ldb clock for di0 + 0xA + 1 + read-write + + + LDB_DI0_DIV_0 + divide by 3.5 + 0 + + + LDB_DI0_DIV_1 + divide by 7 + 0x1 + + + + + LDB_DI1_DIV + Control for divider of ldb clock for di1 + 0xB + 1 + read-write + + + LDB_DI1_DIV_0 + divide by 3.5 + 0 + + + LDB_DI1_DIV_1 + divide by 7 + 0x1 + + + + + ESAI_CLK_SEL + Selector for the ESAI clock + 0x13 + 2 + read-write + + + VID_CLK_SEL + Selector for vid clock multiplexer + 0x15 + 3 + read-write + + + VID_CLK_SEL_0 + PLL3 PFD1 + 0 + + + VID_CLK_SEL_1 + PLL3 + 0x1 + + + VID_CLK_SEL_2 + PLL3 PFD3 + 0x2 + + + VID_CLK_SEL_3 + PLL4 + 0x3 + + + VID_CLK_SEL_4 + PLL5 + 0x4 + + + + + VID_CLK_PRE_PODF + Post-divider for vid clock root + 0x18 + 2 + read-write + + + VID_CLK_PRE_PODF_0 + divide by 1 + 0 + + + VID_CLK_PRE_PODF_1 + divide by 2 + 0x1 + + + VID_CLK_PRE_PODF_2 + divide by 3 + 0x2 + + + VID_CLK_PRE_PODF_3 + divide by 4 + 0x3 + + + + + VID_CLK_PODF + Post-divider for vid clock root + 0x1A + 3 + read-write + + + VID_CLK_PODF_0 + divide by 1 + 0 + + + VID_CLK_PODF_1 + divide by 2 + 0x1 + + + VID_CLK_PODF_2 + divide by 3 + 0x2 + + + VID_CLK_PODF_3 + divide by 4 + 0x3 + + + VID_CLK_PODF_4 + divide by 5 + 0x4 + + + VID_CLK_PODF_5 + divide by 6 + 0x5 + + + VID_CLK_PODF_6 + divide by 7 + 0x6 + + + VID_CLK_PODF_7 + divide by 8 + 0x7 + + + + + + + CSCDR1 + CCM Serial Clock Divider Register 1 + 0x24 + 32 + read-write + 0x490B00 + 0xFFFFFFFF + + + UART_CLK_PODF + Divider for uart clock podf. + 0 + 6 + read-write + + + UART_CLK_PODF_0 + divide by 1 + 0 + + + UART_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + UART_CLK_SEL + Selector for the UART clock multiplexor + 0x6 + 1 + read-write + + + UART_CLK_SEL_0 + derive clock from pll3_80m + 0 + + + UART_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + USDHC1_PODF + Divider for usdhc1 clock podf. Divider should be updated when output clock is gated. + 0xB + 3 + read-write + + + USDHC1_PODF_0 + divide by 1 + 0 + + + USDHC1_PODF_1 + divide by 2 + 0x1 + + + USDHC1_PODF_2 + divide by 3 + 0x2 + + + USDHC1_PODF_3 + divide by 4 + 0x3 + + + USDHC1_PODF_4 + divide by 5 + 0x4 + + + USDHC1_PODF_5 + divide by 6 + 0x5 + + + USDHC1_PODF_6 + divide by 7 + 0x6 + + + USDHC1_PODF_7 + divide by 8 + 0x7 + + + + + USDHC2_PODF + Divider for usdhc2 clock. Divider should be updated when output clock is gated. + 0x10 + 3 + read-write + + + USDHC2_PODF_0 + divide by 1 + 0 + + + USDHC2_PODF_1 + divide by 2 + 0x1 + + + USDHC2_PODF_2 + divide by 3 + 0x2 + + + USDHC2_PODF_3 + divide by 4 + 0x3 + + + USDHC2_PODF_4 + divide by 5 + 0x4 + + + USDHC2_PODF_5 + divide by 6 + 0x5 + + + USDHC2_PODF_6 + divide by 7 + 0x6 + + + USDHC2_PODF_7 + divide by 8 + 0x7 + + + + + BCH_PODF + Divider for bch clock podf. Divider should be updated when output clock is gated. + 0x13 + 3 + read-write + + + BCH_PODF_0 + divide by 1 + 0 + + + BCH_PODF_1 + divide by 2 + 0x1 + + + BCH_PODF_2 + divide by 3 + 0x2 + + + BCH_PODF_3 + divide by 4 + 0x3 + + + BCH_PODF_4 + divide by 5 + 0x4 + + + BCH_PODF_5 + divide by 6 + 0x5 + + + BCH_PODF_6 + divide by 7 + 0x6 + + + BCH_PODF_7 + divide by 8 + 0x7 + + + + + GPMI_PODF + Divider for gpmi clock pred. Divider should be updated when output clock is gated. + 0x16 + 3 + read-write + + + GPMI_PODF_0 + divide by 1 + 0 + + + GPMI_PODF_1 + divide by 2 + 0x1 + + + GPMI_PODF_2 + divide by 3 + 0x2 + + + GPMI_PODF_3 + divide by 4 + 0x3 + + + GPMI_PODF_4 + divide by 5 + 0x4 + + + GPMI_PODF_5 + divide by 6 + 0x5 + + + GPMI_PODF_6 + divide by 7 + 0x6 + + + GPMI_PODF_7 + divide by 8 + 0x7 + + + + + + + CS1CDR + CCM SAI1 Clock Divider Register + 0x28 + 32 + read-write + 0xEC102C1 + 0xFFFFFFFF + + + SAI1_CLK_PODF + Divider for sai1 clock podf + 0 + 6 + read-write + + + SAI1_CLK_PODF_0 + divide by 1 + 0 + + + SAI1_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + SAI1_CLK_PRED + Divider for sai1 clock pred. + 0x6 + 3 + read-write + + + SAI1_CLK_PRED_0 + divide by 1 + 0 + + + SAI1_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI1_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI1_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI1_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI1_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI1_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI1_CLK_PRED_7 + divide by 8 + 0x7 + + + + + ESAI_CLK_PRED + Divider for ESAI clock pred + 0x9 + 3 + read-write + + + ESAI_CLK_PRED_0 + Divide by 1 + 0 + + + ESAI_CLK_PRED_1 + Divide by 2 + 0x1 + + + ESAI_CLK_PRED_2 + Divide by 3 + 0x2 + + + ESAI_CLK_PRED_3 + Divide by 4 + 0x3 + + + ESAI_CLK_PRED_4 + Divide by 5 + 0x4 + + + ESAI_CLK_PRED_5 + Divide by 6 + 0x5 + + + ESAI_CLK_PRED_6 + Divide by 7 + 0x6 + + + ESAI_CLK_PRED_7 + Divide by 8 + 0x7 + + + + + SAI3_CLK_PODF + Divider for sai3 clock podf + 0x10 + 6 + read-write + + + SAI3_CLK_PODF_0 + divide by 1 + 0 + + + SAI3_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + SAI3_CLK_PRED + Divider for sai3 clock pred. + 0x16 + 3 + read-write + + + SAI3_CLK_PRED_0 + divide by 1 + 0 + + + SAI3_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI3_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI3_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI3_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI3_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI3_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI3_CLK_PRED_7 + divide by 8 + 0x7 + + + + + ESAI_CLK_PODF + Divider for ESAI clock + 0x19 + 3 + read-write + + + ESAI_CLK_PODF_0 + Divide by 1 + 0 + + + ESAI_CLK_PODF_1 + Divide by 2 + 0x1 + + + ESAI_CLK_PODF_2 + Divide by 3 + 0x2 + + + ESAI_CLK_PODF_3 + Divide by 4 + 0x3 + + + ESAI_CLK_PODF_4 + Divide by 5 + 0x4 + + + ESAI_CLK_PODF_5 + Divide by 6 + 0x5 + + + ESAI_CLK_PODF_6 + Divide by 7 + 0x6 + + + ESAI_CLK_PODF_7 + Divide by 8 + 0x7 + + + + + + + CS2CDR + CCM SAI2 Clock Divider Register + 0x2C + 32 + read-write + 0x336C1 + 0xFFFFFFFF + + + SAI2_CLK_PODF + Divider for sai2 clock podf + 0 + 6 + read-write + + + SAI2_CLK_PODF_0 + divide by 1 + 0 + + + SAI2_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + SAI2_CLK_PRED + Divider for sai2 clock pred.Divider should be updated when output clock is gated. + 0x6 + 3 + read-write + + + SAI2_CLK_PRED_0 + divide by 1 + 0 + + + SAI2_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI2_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI2_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI2_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI2_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI2_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI2_CLK_PRED_7 + divide by 8 + 0x7 + + + + + LDB_DI0_CLK_SEL + Selector for ldb_di0 clock multiplexerMultiplexor should be updated when both input and output clocks are gated + 0x9 + 3 + read-write + + + LDB_DI0_CLK_SEL_0 + PLL5 clock + 0 + + + LDB_DI0_CLK_SEL_1 + PLL2 PFD0 + 0x1 + + + LDB_DI0_CLK_SEL_2 + PLL2 PFD2 + 0x2 + + + LDB_DI0_CLK_SEL_3 + PLL2 PFD3 + 0x3 + + + LDB_DI0_CLK_SEL_4 + PLL2 PFD1 + 0x4 + + + LDB_DI0_CLK_SEL_5 + PLL3 PFD3 + 0x5 + + + + + ENFC_CLK_SEL + Selector for enfc clock multiplexer Multiplexor should be updated when output clock is gated. + 0xF + 3 + read-write + + + ENFC_CLK_SEL_0 + derive clock from PLL2 PFD0 + 0 + + + ENFC_CLK_SEL_1 + derive clock from PLL2 + 0x1 + + + ENFC_CLK_SEL_2 + derive clock from pll3_sw_clk + 0x2 + + + ENFC_CLK_SEL_3 + derive clock from PLL2 PFD2 + 0x3 + + + ENFC_CLK_SEL_4 + derive clock from PLL3 PFD3 + 0x4 + + + + + ENFC_CLK_PRED + Divider for enfc clock pred divider.Divider should be updated when output clock is gated. + 0x12 + 3 + read-write + + + ENFC_CLK_PRED_0 + divide by 1 + 0 + + + ENFC_CLK_PRED_1 + divide by 2 + 0x1 + + + ENFC_CLK_PRED_2 + divide by 3 + 0x2 + + + ENFC_CLK_PRED_3 + divide by 4 + 0x3 + + + ENFC_CLK_PRED_4 + divide by 5 + 0x4 + + + ENFC_CLK_PRED_5 + divide by 6 + 0x5 + + + ENFC_CLK_PRED_6 + divide by 7 + 0x6 + + + ENFC_CLK_PRED_7 + divide by 8 + 0x7 + + + + + ENFC_CLK_PODF + Divider for enfc clock divider. + 0x15 + 6 + read-write + + + ENFC_CLK_PODF_0 + divide by 1 + 0 + + + ENFC_CLK_PODF_1 + divide by 2 + 0x1 + + + ENFC_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + + + CDCDR + CCM D1 Clock Divider Register + 0x30 + 32 + read-write + 0x33F71F92 + 0xFFFFFFFF + + + SPDIF0_CLK_SEL + Selector for spdif0 clock multiplexer + 0x14 + 2 + read-write + + + SPDIF0_CLK_SEL_0 + derive clock from PLL4 + 0 + + + SPDIF0_CLK_SEL_1 + derive clock from PLL3 PFD2 + 0x1 + + + SPDIF0_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + SPDIF0_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + SPDIF0_CLK_PODF + Divider for spdif0 clock podf. Divider should be updated when output clock is gated. + 0x16 + 3 + read-write + + + SPDIF0_CLK_PODF_0 + divide by 1 + 0 + + + SPDIF0_CLK_PODF_7 + divide by 8 + 0x7 + + + + + SPDIF0_CLK_PRED + Divider for spdif0 clock pred. Divider should be updated when output clock is gated. + 0x19 + 3 + read-write + + + SPDIF0_CLK_PRED_0 + divide by 1 (do not use with high input frequencies) + 0 + + + SPDIF0_CLK_PRED_1 + divide by 2 + 0x1 + + + SPDIF0_CLK_PRED_2 + divide by 3 + 0x2 + + + SPDIF0_CLK_PRED_7 + divide by 8 + 0x7 + + + + + + + CHSCCDR + CCM HSC Clock Divider Register + 0x34 + 32 + read-write + 0x29148 + 0xFFFFFFFF + + + EPDC_CLK_SEL + Selector for EPDC root clock multiplexer + 0x9 + 3 + read-write + + + EPDC_CLK_SEL_0 + Derive clock from divided pre-muxed EPDC clock + 0 + + + EPDC_CLK_SEL_1 + Derive clock from ipp_di0_clk + 0x1 + + + EPDC_CLK_SEL_2 + Derive clock from ipp_di1_clk + 0x2 + + + EPDC_CLK_SEL_3 + Derive clock from ldb_di0_clk + 0x3 + + + EPDC_CLK_SEL_4 + Derive clock from ldb_di1_clk + 0x4 + + + + + EPDC_PODF + Divider for EPDC clock divider. Divider should be updated when output clock is gated. + 0xC + 3 + read-write + + + EPDC_PODF_0 + Divide by 1 + 0 + + + EPDC_PODF_1 + Divide by 2 + 0x1 + + + EPDC_PODF_2 + Divide by 3 + 0x2 + + + EPDC_PODF_3 + Divide by 4 + 0x3 + + + EPDC_PODF_4 + Divide by 5 + 0x4 + + + EPDC_PODF_5 + Divide by 6 + 0x5 + + + EPDC_PODF_6 + Divide by 7 + 0x6 + + + EPDC_PODF_7 + Divide by 8 + 0x7 + + + + + EPDC_PRE_CLK_SEL + Selector for EPDC root clock pre-multiplexer + 0xF + 3 + read-write + + + EPDC_PRE_CLK_SEL_0 + Derive clock from PLL2 + 0 + + + EPDC_PRE_CLK_SEL_1 + Derive clock from PLL3_SW_CLK + 0x1 + + + EPDC_PRE_CLK_SEL_2 + Derive clock from PLL5 + 0x2 + + + EPDC_PRE_CLK_SEL_3 + Derive clock from PLL2 PFD0 + 0x3 + + + EPDC_PRE_CLK_SEL_4 + Derive clock from PLL2 PFD2 + 0x4 + + + EPDC_PRE_CLK_SEL_5 + Derive clock from PLL3 PFD2 + 0x5 + + + + + + + CSCDR2 + CCM Serial Clock Divider Register 2 + 0x38 + 32 + read-write + 0x29B48 + 0xFFFFFFFF + + + LCDIF1_CLK_SEL + Selector for lcdif1 root clock multiplexer + 0x9 + 3 + read-write + + + LCDIF1_CLK_SEL_0 + derive clock from divided pre-muxed lcdif1 clock + 0 + + + LCDIF1_CLK_SEL_1 + derive clock from ipp_di0_clk + 0x1 + + + LCDIF1_CLK_SEL_2 + derive clock from ipp_di1_clk + 0x2 + + + LCDIF1_CLK_SEL_3 + derive clock from ldb_di0_clk + 0x3 + + + LCDIF1_CLK_SEL_4 + derive clock from ldb_di1_clk + 0x4 + + + + + LCDIF1_PRED + Pre-divider for lcdif1 clock. Divider should be updated when output clock is gated. + 0xC + 3 + read-write + + + LCDIF1_PRED_0 + divide by 1 + 0 + + + LCDIF1_PRED_1 + divide by 2 + 0x1 + + + LCDIF1_PRED_2 + divide by 3 + 0x2 + + + LCDIF1_PRED_3 + divide by 4 + 0x3 + + + LCDIF1_PRED_4 + divide by 5 + 0x4 + + + LCDIF1_PRED_5 + divide by 6 + 0x5 + + + LCDIF1_PRED_6 + divide by 7 + 0x6 + + + LCDIF1_PRED_7 + divide by 8 + 0x7 + + + + + LCDIF1_PRE_CLK_SEL + Selector for lcdif1 root clock pre-multiplexer + 0xF + 3 + read-write + + + LCDIF1_PRE_CLK_SEL_0 + derive clock from PLL2 + 0 + + + LCDIF1_PRE_CLK_SEL_1 + derive clock from PLL3 PFD3 + 0x1 + + + LCDIF1_PRE_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + LCDIF1_PRE_CLK_SEL_3 + derive clock from PLL2 PFD0 + 0x3 + + + LCDIF1_PRE_CLK_SEL_4 + derive clock from PLL2 PFD1 + 0x4 + + + LCDIF1_PRE_CLK_SEL_5 + derive clock from PLL3 PFD1 + 0x5 + + + + + ECSPI_CLK_SEL + Selector for the ECSPI clock multiplexor + 0x12 + 1 + read-write + + + ECSPI_CLK_SEL_0 + derive clock from pll3_60m + 0 + + + ECSPI_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + ECSPI_CLK_PODF + Divider for ecspi clock podf + 0x13 + 6 + read-write + + + ECSPI_CLK_PODF_0 + divide by 1 + 0 + + + ECSPI_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + + + CSCDR3 + CCM Serial Clock Divider Register 3 + 0x3C + 32 + read-write + 0x14841 + 0xFFFFFFFF + + + CSI_CLK_SEL + Selector for csi clock multiplexer + 0x9 + 2 + read-write + + + CSI_CLK_SEL_0 + derive clock from osc_clk (24M) + 0 + + + CSI_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + CSI_CLK_SEL_2 + derive clock from pll3_120M + 0x2 + + + CSI_CLK_SEL_3 + derive clock from PLL3 PFD1 + 0x3 + + + + + CSI_PODF + Post divider for csi_core clock. Divider should be updated when output clock is gated. + 0xB + 3 + read-write + + + CSI_PODF_0 + divide by 1 + 0 + + + CSI_PODF_1 + divide by 2 + 0x1 + + + CSI_PODF_2 + divide by 3 + 0x2 + + + CSI_PODF_3 + divide by 4 + 0x3 + + + CSI_PODF_4 + divide by 5 + 0x4 + + + CSI_PODF_5 + divide by 6 + 0x5 + + + CSI_PODF_6 + divide by 7 + 0x6 + + + CSI_PODF_7 + divide by 8 + 0x7 + + + + + + + CWDR + CCM Wakeup Detector Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDHIPR + CCM Divider Handshake In-Process Register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + AXI_PODF_BUSY + Busy indicator for axi_podf. + 0 + 1 + read-only + + + AXI_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + AXI_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the axi_podf will be applied. + 0x1 + + + + + AHB_PODF_BUSY + Busy indicator for ahb_podf. + 0x1 + 1 + read-only + + + AHB_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + AHB_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + 0x1 + + + + + MMDC_PODF_BUSY + Busy indicator for mmdc_axi_podf. + 0x2 + 1 + read-only + + + MMDC_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + MMDC_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the mmdc_axi_podf will be applied. + 0x1 + + + + + PERIPH2_CLK_SEL_BUSY + Busy indicator for periph2_clk_sel mux control. + 0x3 + 1 + read-only + + + PERIPH2_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH2_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + 0x1 + + + + + PERIPH_CLK_SEL_BUSY + Busy indicator for periph_clk_sel mux control. + 0x5 + 1 + read-only + + + PERIPH_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + 0x1 + + + + + ARM_PODF_BUSY + Busy indicator for arm_podf. + 0x10 + 1 + read-only + + + ARM_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + ARM_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied. + 0x1 + + + + + + + CLPCR + CCM Low Power Control Register + 0x54 + 32 + read-write + 0x79 + 0xFFFFFFFF + + + LPM + Setting the low power mode that system will enter on next assertion of dsm_request signal. + 0 + 2 + read-write + + + LPM_0 + Remain in run mode + 0 + + + LPM_1 + Transfer to wait mode + 0x1 + + + LPM_2 + Transfer to stop mode + 0x2 + + + + + ARM_CLK_DIS_ON_LPM + Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode + 0x5 + 1 + read-write + + + ARM_CLK_DIS_ON_LPM_0 + ARM clock enabled on wait mode. + 0 + + + ARM_CLK_DIS_ON_LPM_1 + ARM clock disabled on wait mode. . + 0x1 + + + + + SBYOS + Standby clock oscillator bit + 0x6 + 1 + read-write + + + SBYOS_0 + On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + 0 + + + SBYOS_1 + On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + 0x1 + + + + + DIS_REF_OSC + dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i + 0x7 + 1 + read-write + + + DIS_REF_OSC_0 + external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + 0 + + + DIS_REF_OSC_1 + external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + 0x1 + + + + + VSTBY + Voltage standby request bit + 0x8 + 1 + read-write + + + VSTBY_0 + Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + 0 + + + VSTBY_1 + Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + 0x1 + + + + + STBY_COUNT + Standby counter definition + 0x9 + 2 + read-write + + + STBY_COUNT_0 + CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + 0 + + + STBY_COUNT_1 + CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + 0x1 + + + STBY_COUNT_2 + CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + 0x2 + + + STBY_COUNT_3 + CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + 0x3 + + + + + COSC_PWRDOWN + In run mode, software can manually control powering down of on chip oscillator, i + 0xB + 1 + read-write + + + COSC_PWRDOWN_0 + On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + 0 + + + COSC_PWRDOWN_1 + On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + 0x1 + + + + + BYPASS_MMDC_LPM_HS + Bypass handshake with mmdc on next entrance to low power mode (STOP or WAIT) + 0x15 + 1 + read-write + + + BYPASS_MMDC_LPM_HS_0 + handshake with mmdc on next entrance to low power mode will be performed. . + 0 + + + BYPASS_MMDC_LPM_HS_1 + handshake with mmdc on next entrance to low power mode will be bypassed. + 0x1 + + + + + MASK_CORE0_WFI + Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 0x16 + 1 + read-write + + + MASK_CORE0_WFI_0 + WFI of core0 is not masked + 0 + + + MASK_CORE0_WFI_1 + WFI of core0 is masked + 0x1 + + + + + MASK_SCU_IDLE + Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 0x1A + 1 + read-write + + + MASK_SCU_IDLE_0 + SCU IDLE is not masked + 0 + + + MASK_SCU_IDLE_1 + SCU IDLE is masked + 0x1 + + + + + MASK_L2CC_IDLE + Mask L2CC IDLE for entering low power mode + 0x1B + 1 + read-write + + + MASK_L2CC_IDLE_0 + L2CC IDLE is not masked + 0 + + + MASK_L2CC_IDLE_1 + L2CC IDLE is masked + 0x1 + + + + + + + CISR + CCM Interrupt Status Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRF_PLL + CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs + 0 + 1 + read-write + oneToClear + + + LRF_PLL_0 + interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + 0 + + + LRF_PLL_1 + interrupt generated due to lock ready of all enabled and not bypaseed PLLs + 0x1 + + + + + COSC_READY + CCM interrupt request 2 generated due to on board oscillator ready, i + 0x6 + 1 + read-write + oneToClear + + + COSC_READY_0 + interrupt is not generated due to on board oscillator ready + 0 + + + COSC_READY_1 + interrupt generated due to on board oscillator ready + 0x1 + + + + + AXI_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of axi_podf + 0x11 + 1 + read-write + oneToClear + + + AXI_PODF_LOADED_0 + interrupt is not generated due to frequency change of axi_podf + 0 + + + AXI_PODF_LOADED_1 + interrupt generated due to frequency change of axi_podf + 0x1 + + + + + PERIPH2_CLK_SEL_LOADED + CCM interrupt request 1 generated due to frequency change of periph2_clk_sel + 0x13 + 1 + read-write + oneToClear + + + PERIPH2_CLK_SEL_LOADED_0 + interrupt is not generated due to frequency change of periph2_clk_sel + 0 + + + PERIPH2_CLK_SEL_LOADED_1 + interrupt generated due to frequency change of periph2_clk_sel + 0x1 + + + + + AHB_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of ahb_podf + 0x14 + 1 + read-write + oneToClear + + + AHB_PODF_LOADED_0 + interrupt is not generated due to frequency change of ahb_podf + 0 + + + AHB_PODF_LOADED_1 + interrupt generated due to frequency change of ahb_podf + 0x1 + + + + + MMDC_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of mmdc_podf_ loaded + 0x15 + 1 + read-write + oneToClear + + + MMDC_PODF_LOADED_0 + interrupt is not generated due to frequency change of mmdc_podf_ loaded + 0 + + + MMDC_PODF_LOADED_1 + interrupt generated due to frequency change of mmdc_podf_ loaded + 0x1 + + + + + PERIPH_CLK_SEL_LOADED + CCM interrupt request 1 generated due to update of periph_clk_sel. + 0x16 + 1 + read-write + oneToClear + + + PERIPH_CLK_SEL_LOADED_0 + interrupt is not generated due to update of periph_clk_sel. + 0 + + + PERIPH_CLK_SEL_LOADED_1 + interrupt generated due to update of periph_clk_sel. + 0x1 + + + + + ARM_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of arm_podf + 0x1A + 1 + read-write + oneToClear + + + ARM_PODF_LOADED_0 + interrupt is not generated due to frequency change of arm_podf + 0 + + + ARM_PODF_LOADED_1 + interrupt generated due to frequency change of arm_podf + 0x1 + + + + + + + CIMR + CCM Interrupt Mask Register + 0x5C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MASK_LRF_PLL + mask interrupt generation due to lrf of PLLs + 0 + 1 + read-write + + + MASK_LRF_PLL_0 + don't mask interrupt due to lrf of PLLs - interrupt will be created + 0 + + + MASK_LRF_PLL_1 + mask interrupt due to lrf of PLLs + 0x1 + + + + + MASK_COSC_READY + mask interrupt generation due to on board oscillator ready + 0x6 + 1 + read-write + + + MASK_COSC_READY_0 + don't mask interrupt due to on board oscillator ready - interrupt will be created + 0 + + + MASK_COSC_READY_1 + mask interrupt due to on board oscillator ready + 0x1 + + + + + MASK_AXI_PODF_LOADED + mask interrupt generation due to frequency change of axi_podf + 0x11 + 1 + read-write + + + MASK_AXI_PODF_LOADED_0 + don't mask interrupt due to frequency change of axi_podf - interrupt will be created + 0 + + + MASK_AXI_PODF_LOADED_1 + mask interrupt due to frequency change of axi_podf + 0x1 + + + + + MASK_PERIPH2_CLK_SEL_LOADED + mask interrupt generation due to update of periph2_clk_sel. + 0x13 + 1 + read-write + + + MASK_PERIPH2_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH2_CLK_SEL_LOADED_1 + mask interrupt due to update of periph2_clk_sel + 0x1 + + + + + MASK_AHB_PODF_LOADED + mask interrupt generation due to frequency change of ahb_podf + 0x14 + 1 + read-write + + + MASK_AHB_PODF_LOADED_0 + don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + 0 + + + MASK_AHB_PODF_LOADED_1 + mask interrupt due to frequency change of ahb_podf + 0x1 + + + + + MASK_MMDC_PODF_LOADED + mask interrupt generation due to update of mask_mmdc_podf + 0x15 + 1 + read-write + + + MASK_MMDC_PODF_LOADED_0 + don't mask interrupt due to update of mask_mmdc_podf - interrupt will be created + 0 + + + MASK_MMDC_PODF_LOADED_1 + mask interrupt due to update of mask_mmdc_podf + 0x1 + + + + + MASK_PERIPH_CLK_SEL_LOADED + mask interrupt generation due to update of periph_clk_sel. + 0x16 + 1 + read-write + + + MASK_PERIPH_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH_CLK_SEL_LOADED_1 + mask interrupt due to update of periph_clk_sel + 0x1 + + + + + ARM_PODF_LOADED + mask interrupt generation due to frequency change of arm_podf + 0x1A + 1 + read-write + + + ARM_PODF_LOADED_0 + don't mask interrupt due to frequency change of arm_podf - interrupt will be created + 0 + + + ARM_PODF_LOADED_1 + mask interrupt due to frequency change of arm_podf + 0x1 + + + + + + + CCOSR + CCM Clock Output Source Register + 0x60 + 32 + read-write + 0xA0001 + 0xFFFFFFFF + + + CLKO_SEL + Selection of the clock to be generated on CCM_CLKO1 + 0 + 4 + read-write + + + CLKO_SEL_5 + axi_clk_root + 0x5 + + + CLKO_SEL_6 + enfc_clk_root + 0x6 + + + CLKO_SEL_7 + no description available + 0x7 + + + CLKO_SEL_8 + epdc_clk_root + 0x8 + + + CLKO_SEL_9 + no description available + 0x9 + + + CLKO_SEL_10 + lcdif_pix_clk_root + 0xA + + + CLKO_SEL_11 + ahb_clk_root + 0xB + + + CLKO_SEL_12 + ipg_clk_root + 0xC + + + CLKO_SEL_13 + perclk_root + 0xD + + + CLKO_SEL_14 + ckil_sync_clk_root + 0xE + + + CLKO_SEL_15 + pll4_main_clk + 0xF + + + + + CLKO1_DIV + Setting the divider of CCM_CLKO1 + 0x4 + 3 + read-write + + + CLKO1_DIV_0 + divide by 1 + 0 + + + CLKO1_DIV_1 + divide by 2 + 0x1 + + + CLKO1_DIV_2 + divide by 3 + 0x2 + + + CLKO1_DIV_3 + divide by 4 + 0x3 + + + CLKO1_DIV_4 + divide by 5 + 0x4 + + + CLKO1_DIV_5 + divide by 6 + 0x5 + + + CLKO1_DIV_6 + divide by 7 + 0x6 + + + CLKO1_DIV_7 + divide by 8 + 0x7 + + + + + CLKO1_EN + Enable of CCM_CLKO1 clock + 0x7 + 1 + read-write + + + CLKO1_EN_0 + CCM_CLKO1 disabled. + 0 + + + CLKO1_EN_1 + CCM_CLKO1 enabled. + 0x1 + + + + + CLK_OUT_SEL + CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks + 0x8 + 1 + read-write + + + CLK_OUT_SEL_0 + CCM_CLKO1 output drives CCM_CLKO1 clock + 0 + + + CLK_OUT_SEL_1 + CCM_CLKO1 output drives CCM_CLKO2 clock + 0x1 + + + + + CLKO2_SEL + Selection of the clock to be generated on CCM_CLKO2 + 0x10 + 5 + read-write + + + CLKO2_SEL_1 + mmdc_clk_root + 0x1 + + + CLKO2_SEL_2 + gpmi_clk_root + 0x2 + + + CLKO2_SEL_3 + usdhc1_clk_root + 0x3 + + + CLKO2_SEL_5 + wrck_clk_root + 0x5 + + + CLKO2_SEL_6 + ecspi_clk_root + 0x6 + + + CLKO2_SEL_8 + bch_clk_root + 0x8 + + + CLKO2_SEL_10 + arm_clk_root + 0xA + + + CLKO2_SEL_11 + csi_core + 0xB + + + CLKO2_SEL_14 + osc_clk + 0xE + + + CLKO2_SEL_17 + usdhc2_clk_root + 0x11 + + + CLKO2_SEL_18 + sai1_clk_root + 0x12 + + + CLKO2_SEL_19 + sai2_clk_root + 0x13 + + + CLKO2_SEL_20 + sai3_clk_root + 0x14 + + + CLKO2_SEL_23 + can_clk_root + 0x17 + + + CLKO2_SEL_25 + qspi1_clk_root + 0x19 + + + CLKO2_SEL_27 + aclk_eim_slow_clk_root + 0x1B + + + CLKO2_SEL_28 + uart_clk_root + 0x1C + + + CLKO2_SEL_29 + spdif0_clk_root + 0x1D + + + + + CLKO2_DIV + Setting the divider of CCM_CLKO2 + 0x15 + 3 + read-write + + + CLKO2_DIV_0 + divide by 1 + 0 + + + CLKO2_DIV_1 + divide by 2 + 0x1 + + + CLKO2_DIV_2 + divide by 3 + 0x2 + + + CLKO2_DIV_3 + divide by 4 + 0x3 + + + CLKO2_DIV_4 + divide by 5 + 0x4 + + + CLKO2_DIV_5 + divide by 6 + 0x5 + + + CLKO2_DIV_6 + divide by 7 + 0x6 + + + CLKO2_DIV_7 + divide by 8 + 0x7 + + + + + CLKO2_EN + Enable of CCM_CLKO2 clock + 0x18 + 1 + read-write + + + CLKO2_EN_0 + CCM_CLKO2 disabled. + 0 + + + CLKO2_EN_1 + CCM_CLKO2 enabled. + 0x1 + + + + + + + CGPR + CCM General Purpose Register + 0x64 + 32 + read-write + 0xFE62 + 0xFFFFFFFF + + + PMIC_DELAY_SCALER + Defines clock dividion of clock for stby_count (pmic delay counter) + 0 + 1 + read-write + + + PMIC_DELAY_SCALER_0 + clock is not divided + 0 + + + PMIC_DELAY_SCALER_1 + clock is divided /8 + 0x1 + + + + + MMDC_EXT_CLK_DIS + Disable external clock driver of MMDC during STOP mode + 0x2 + 1 + read-write + + + MMDC_EXT_CLK_DIS_0 + don't disable during stop mode. + 0 + + + MMDC_EXT_CLK_DIS_1 + disable during stop mode + 0x1 + + + + + EFUSE_PROG_SUPPLY_GATE + Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing + 0x4 + 1 + read-write + + + EFUSE_PROG_SUPPLY_GATE_0 + fuse programing supply voltage is gated off to the efuse module + 0 + + + EFUSE_PROG_SUPPLY_GATE_1 + allow fuse programing. + 0x1 + + + + + SYS_MEM_DS_CTRL + System memory DS control + 0xE + 2 + read-write + + + SYS_MEM_DS_CTRL_0 + Disable memory DS mode always + 0 + + + SYS_MEM_DS_CTRL_1 + Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + 0x1 + + + + + FPL + Fast PLL enable. + 0x10 + 1 + read-write + + + FPL_0 + Engage PLL enable default way. + 0 + + + FPL_1 + Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + 0x1 + + + + + INT_MEM_CLK_LPM + Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal + 0x11 + 1 + read-write + + + INT_MEM_CLK_LPM_0 + Disable the clock to the ARM platform memories when entering Low Power Mode + 0 + + + INT_MEM_CLK_LPM_1 + Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + 0x1 + + + + + + + CCGR0 + CCM Clock Gating Register 0 + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + aips_tz1 clocks (aips_tz1_clk_enable) + 0 + 2 + read-write + + + CG1 + aips_tz2 clocks (aips_tz2_clk_enable) + 0x2 + 2 + read-write + + + CG2 + apbhdma hclk clock (apbhdma_hclk_enable) + 0x4 + 2 + read-write + + + CG3 + asrc clock (asrc_clk_enable) + 0x6 + 2 + read-write + + + CG4 + Reserved + 0x8 + 2 + read-write + + + CG5 + dcp clock (dcp_clk_enable) + 0xA + 2 + read-write + + + CG6 + enet clock (enet_clk_enable) + 0xC + 2 + read-write + + + CG7 + can1 clock (can1_clk_enable) + 0xE + 2 + read-write + + + CG8 + can1_serial clock (can1_serial_clk_enable) + 0x10 + 2 + read-write + + + CG9 + can2 clock (can2_clk_enable) + 0x12 + 2 + read-write + + + CG10 + can2_serial clock (can2_serial_clk_enable) + 0x14 + 2 + read-write + + + CG11 + CPU debug clocks (arm_dbg_clk_enable) + 0x16 + 2 + read-write + + + CG12 + dcic1 clocks (dcic1_clk_enable) gpt2 bus clocks (gpt2_bus_clk_enable) + 0x18 + 2 + read-write + + + CG13 + gpt2 serial clocks (gpt2_serial_clk_enable) + 0x1A + 2 + read-write + + + CG14 + uart2 clock (uart2_clk_enable) + 0x1C + 2 + read-write + + + CG15 + gpio2_clocks (gpio2_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR1 + CCM Clock Gating Register 1 + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + ecspi1 clocks (ecspi1_clk_enable) + 0 + 2 + read-write + + + CG1 + ecspi2 clocks (ecspi2_clk_enable) + 0x2 + 2 + read-write + + + CG2 + ecspi3 clocks (ecspi3_clk_enable) + 0x4 + 2 + read-write + + + CG3 + ecspi4 clocks (ecspi4_clk_enable) + 0x6 + 2 + read-write + + + CG4 + adc2 clock (adc2_clk_enable) + 0x8 + 2 + read-write + + + CG5 + uart3 clock (uart3_clk_enable) + 0xA + 2 + read-write + + + CG6 + epit1 clocks (epit1_clk_enable) + 0xC + 2 + read-write + + + CG7 + epit2 clocks (epit2_clk_enable) + 0xE + 2 + read-write + + + CG8 + adc1 clock (adc1_clk_enable) + 0x10 + 2 + read-write + + + CG9 + sim_s clock (sim_s_clk_enable) + 0x12 + 2 + read-write + + + CG10 + gpt bus clock (gpt_clk_enable) + 0x14 + 2 + read-write + + + CG11 + gpt serial clock (gpt_serial_clk_enable) + 0x16 + 2 + read-write + + + CG12 + uart4 clock (uart4_clk_enable) + 0x18 + 2 + read-write + + + CG13 + gpio1 clock (gpio1_clk_enable) + 0x1A + 2 + read-write + + + CG14 + csu clock (csu_clk_enable) + 0x1C + 2 + read-write + + + CG15 + gpio5 clock (gpio5_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR2 + CCM Clock Gating Register 2 + 0x70 + 32 + read-write + 0xFC3FFFFF + 0xFFFFFFFF + + + CG0 + esai clock (esai_clk_enable) + 0 + 2 + read-write + + + CG1 + csi clock (csi_clk_enable) + 0x2 + 2 + read-write + + + CG2 + iomuxc_snvs clock (iomuxc_snvs_clk_enable) + 0x4 + 2 + read-write + + + CG3 + i2c1_serial clock (i2c1_serial_clk_enable) + 0x6 + 2 + read-write + + + CG4 + i2c2_serial clock (i2c2_serial_clk_enable) + 0x8 + 2 + read-write + + + CG5 + i2c3_serial clock (i2c3_serial_clk_enable) + 0xA + 2 + read-write + + + CG6 + OCOTP_CTRL clock (iim_clk_enable) + 0xC + 2 + read-write + + + CG7 + iomux_ipt_clk_io clock (iomux_ipt_clk_io_enable) + 0xE + 2 + read-write + + + CG8 + ipmux1 clock (ipmux1_clk_enable) + 0x10 + 2 + read-write + + + CG9 + ipmux2 clock (ipmux2_clk_enable) + 0x12 + 2 + read-write + + + CG10 + ipmux3 clock (ipmux3_clk_enable) + 0x14 + 2 + read-write + + + CG11 + ipsync_ip2apb_tzasc1_ipg clocks (ipsync_ip2apb_tzasc1_ipg_master_clk_enable) + 0x16 + 2 + read-write + + + CG12 + Reserved + 0x18 + 2 + read-write + + + CG13 + gpio3 clock (gpio3_clk_enable) + 0x1A + 2 + read-write + + + CG14 + lcd clocks (lcd_clk_enable) + 0x1C + 2 + read-write + + + CG15 + pxp clocks (pxp_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR3 + CCM Clock Gating Register 3 + 0x74 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + Reserved + 0 + 2 + read-write + + + CG1 + uart5 clock (uart5_clk_enable) + 0x2 + 2 + read-write + + + CG2 + epdc clock (epdc_clk_enable) + 0x4 + 2 + read-write + + + CG3 + uart6 clock (uart6_clk_enable) + 0x6 + 2 + read-write + + + CG4 + CA7 CCM DAP clock (ccm_dap_clk_enable) + 0x8 + 2 + read-write + + + CG5 + lcdif1 pix clock (lcdif1_pix_clk_enable) + 0xA + 2 + read-write + + + CG6 + gpio4 clock (gpio4_clk_enable) + 0xC + 2 + read-write + + + CG7 + qspi1 clock (qspi1_clk_enable) + 0xE + 2 + read-write + + + CG8 + wdog1 clock (wdog1_clk_enable) + 0x10 + 2 + read-write + + + CG9 + a7 clkdiv patch clock (a7_clkdiv_patch_clk_enable) + 0x12 + 2 + read-write + + + CG10 + mmdc_core_aclk_fast_core_p0 clock (mmdc_core_aclk_fast_core_p0_enable) + 0x14 + 2 + read-write + + + CG11 + Reserved + 0x16 + 2 + read-write + + + CG12 + mmdc_core_ipg_clk_p0 clock (mmdc_core_ipg_clk_p0_enable) + 0x18 + 2 + read-write + + + CG13 + mmdc_core_ipg_clk_p1 clock (mmdc_core_ipg_clk_p1_enable) + 0x1A + 2 + read-write + + + CG14 + axi clock (axi_clk_enable) + 0x1C + 2 + read-write + + + CG15 + iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR4 + CCM Clock Gating Register 4 + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + Reserved + 0 + 2 + read-write + + + CG1 + iomuxc clock (iomuxc_clk_enable) + 0x2 + 2 + read-write + + + CG2 + iomuxc gpr clock (iomuxc_gpr_clk_enable) + 0x4 + 2 + read-write + + + CG3 + sim_cpu clock (sim_cpu_clk_enable) + 0x6 + 2 + read-write + + + CG4 + cxapbsyncbridge slave clock (cxapbsyncbridge_slave_clk_enable) + 0x8 + 2 + read-write + + + CG5 + tsc_dig clock (tsc_clk_enable) + 0xA + 2 + read-write + + + CG6 + pl301_mx6qper1_bch clocks (pl301_mx6qper1_bchclk_enable) This gates bch_clk_root to sim_m fabric. + 0xC + 2 + read-write + + + CG7 + pl301_mx6qper2_mainclk_enable (pl301_mx6qper2_mainclk_enable) + 0xE + 2 + read-write + + + CG8 + pwm1 clocks (pwm1_clk_enable) + 0x10 + 2 + read-write + + + CG9 + pwm2 clocks (pwm2_clk_enable) + 0x12 + 2 + read-write + + + CG10 + pwm3 clocks (pwm3_clk_enable) + 0x14 + 2 + read-write + + + CG11 + pwm4 clocks (pwm4_clk_enable) + 0x16 + 2 + read-write + + + CG12 + rawnand_u_bch_input_apb clock (rawnand_u_bch_input_apb_clk_enable) + 0x18 + 2 + read-write + + + CG13 + rawnand_u_gpmi_bch_input_bch clock (rawnand_u_gpmi_bch_input_bch_clk_enable) + 0x1A + 2 + read-write + + + CG14 + rawnand_u_gpmi_bch_input_gpmi_io clock (rawnand_u_gpmi_bch_input_gpmi_io_clk_enable) + 0x1C + 2 + read-write + + + CG15 + rawnand_u_gpmi_input_apb clock (rawnand_u_gpmi_input_apb_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR5 + CCM Clock Gating Register 5 + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + rom clock (rom_clk_enable) + 0 + 2 + read-write + + + CG1 + stcr clock (stcr_clk_enable) + 0x2 + 2 + read-write + + + CG2 + snvs dryice clock (snvs_dryice_clk_enable) + 0x4 + 2 + read-write + + + CG3 + sdma clock (sdma_clk_enable) + 0x6 + 2 + read-write + + + CG4 + kpp clock (kpp_clk_enable) + 0x8 + 2 + read-write + + + CG5 + wdog2 clock (wdog2_clk_enable) + 0xA + 2 + read-write + + + CG6 + spba clock (spba_clk_enable) + 0xC + 2 + read-write + + + CG7 + spdif / audio clock (spdif_clk_enable, audio_clk_root) + 0xE + 2 + read-write + + + CG8 + sim_main clock (sim_main_clk_enable) + 0x10 + 2 + read-write + + + CG9 + snvs_hp clock (snvs_hp_clk_enable) + 0x12 + 2 + read-write + + + CG10 + snvs_lp clock (snvs_lp_clk_enable) + 0x14 + 2 + read-write + + + CG11 + sai3 clock (sai3_clk_enable) + 0x16 + 2 + read-write + + + CG12 + uart1 clock (uart1_clk_enable) + 0x18 + 2 + read-write + + + CG13 + uart7 clock (uart7_clk_enable) + 0x1A + 2 + read-write + + + CG14 + sai1 clock (sai1_clk_enable) + 0x1C + 2 + read-write + + + CG15 + sai2 clock (sai2_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR6 + CCM Clock Gating Register 6 + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + usboh3 clock (usboh3_clk_enable) + 0 + 2 + read-write + + + CG1 + usdhc1 clocks (usdhc1_clk_enable) + 0x2 + 2 + read-write + + + CG2 + usdhc2 clocks (usdhc2_clk_enable) + 0x4 + 2 + read-write + + + CG3 + Reserved + 0x6 + 2 + read-write + + + CG4 + ipmux4 clock (ipmux4_clk_enable) + 0x8 + 2 + read-write + + + CG5 + eim_slow clocks (eim_slow_clk_enable) + 0xA + 2 + read-write + + + CG6 + Reserved + 0xC + 2 + read-write + + + CG7 + uart8 clocks (uart8_clk_enable) + 0xE + 2 + read-write + + + CG8 + pwm8 clocks (pwm8_clk_enable) + 0x10 + 2 + read-write + + + CG9 + aips_tz3 clock (aips_tz3_clk_enable) + 0x12 + 2 + read-write + + + CG10 + wdog3 clock (wdog3_clk_enable) + 0x14 + 2 + read-write + + + CG11 + anadig clocks (anadig_clk_enable) + 0x16 + 2 + read-write + + + CG12 + i2c4 serial clock (i2c4_serial_clk_enable) + 0x18 + 2 + read-write + + + CG13 + pwm5 clocks (pwm5_clk_enable) + 0x1A + 2 + read-write + + + CG14 + pwm6 clocks (pwm6_clk_enable) + 0x1C + 2 + read-write + + + CG15 + pwm7 clocks (pwm7_clk_enable) + 0x1E + 2 + read-write + + + + + CMEOR + CCM Module Enable Overide Register + 0x88 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MOD_EN_OV_GPT + Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk' + 0x5 + 1 + read-write + + + MOD_EN_OV_GPT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_GPT_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_EPIT + Overide clock enable signal from EPIT - clock will not be gated based on EPIT's signal 'ipg_enable_clk' + 0x6 + 1 + read-write + + + MOD_EN_OV_EPIT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_EPIT_1 + override module enable signal + 0x1 + + + + + MOD_EN_USDHC + overide clock enable signal from USDHC. + 0x7 + 1 + read-write + + + MOD_EN_USDHC_0 + don't override module enable signal + 0 + + + MOD_EN_USDHC_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN2_CPI + Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 0x1C + 1 + read-write + + + MOD_EN_OV_CAN2_CPI_0 + don't override module enable signal + 0 + + + MOD_EN_OV_CAN2_CPI_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN1_CPI + Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 0x1E + 1 + read-write + + + MOD_EN_OV_CAN1_CPI_0 + don't overide module enable signal + 0 + + + MOD_EN_OV_CAN1_CPI_1 + overide module enable signal + 0x1 + + + + + + + + + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG_ + 0x20C8000 + + 0 + 0x180 + registers + + + + PLL_ARM + Analog ARM PLL control Register + 0 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable the clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PLL_SEL + Reserved + 0x13 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ARM_SET + Analog ARM PLL control Register + 0x4 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable the clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PLL_SEL + Reserved + 0x13 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ARM_CLR + Analog ARM PLL control Register + 0x8 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable the clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PLL_SEL + Reserved + 0x13 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ARM_TOG + Analog ARM PLL control Register + 0xC + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable the clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PLL_SEL + Reserved + 0x13 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB1 + Analog USB1 480MHz PLL Control Register + 0x10 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 0x6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB1_SET + Analog USB1 480MHz PLL Control Register + 0x14 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 0x6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB1_CLR + Analog USB1 480MHz PLL Control Register + 0x18 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 0x6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB1_TOG + Analog USB1 480MHz PLL Control Register + 0x1C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 0x6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB2 + Analog USB2 480MHz PLL Control Register + 0x20 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 0x6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB2_SET + Analog USB2 480MHz PLL Control Register + 0x24 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 0x6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB2_CLR + Analog USB2 480MHz PLL Control Register + 0x28 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 0x6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB2_TOG + Analog USB2 480MHz PLL Control Register + 0x2C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 0x6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS + Analog System PLL Control Register + 0x30 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS_SET + Analog System PLL Control Register + 0x34 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS_CLR + Analog System PLL Control Register + 0x38 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS_TOG + Analog System PLL Control Register + 0x3C + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS_SS + 528MHz System PLL Spread Spectrum Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP + Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 0 + 15 + read-write + + + ENABLE + no description available + 0xF + 1 + read-write + + + ENABLE_0 + Spread spectrum modulation disabled + 0 + + + ENABLE_1 + Soread spectrum modulation enabled + 0x1 + + + + + STOP + Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 0x10 + 16 + read-write + + + + + PLL_SYS_NUM + Numerator of 528MHz System PLL Fractional Loop Divider Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + A + 30 bit numerator (A) of fractional loop divider (signed integer). + 0 + 30 + read-write + + + + + PLL_SYS_DENOM + Denominator of 528MHz System PLL Fractional Loop Divider Register + 0x60 + 32 + read-write + 0x12 + 0xFFFFFFFF + + + B + 30 bit Denominator (B) of fractional loop divider (unsigned integer). + 0 + 30 + read-write + + + + + PLL_AUDIO + Analog Audio PLL control Register + 0x70 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_AUDIO_SET + Analog Audio PLL control Register + 0x74 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_AUDIO_CLR + Analog Audio PLL control Register + 0x78 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_AUDIO_TOG + Analog Audio PLL control Register + 0x7C + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_AUDIO_NUM + Numerator of Audio PLL Fractional Loop Divider Register + 0x80 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_AUDIO_DENOM + Denominator of Audio PLL Fractional Loop Divider Register + 0x90 + 32 + read-write + 0x2964619C + 0xFFFFFFFF + + + B + 30 bit Denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_VIDEO + Analog Video PLL control Register + 0xA0 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enalbe PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_VIDEO_SET + Analog Video PLL control Register + 0xA4 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enalbe PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_VIDEO_CLR + Analog Video PLL control Register + 0xA8 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enalbe PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_VIDEO_TOG + Analog Video PLL control Register + 0xAC + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enalbe PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_VIDEO_NUM + Numerator of Video PLL Fractional Loop Divider Register + 0xB0 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider(Signed number), absolute value should be less than denominator + 0 + 30 + read-write + + + + + PLL_VIDEO_DENOM + Denominator of Video PLL Fractional Loop Divider Register + 0xC0 + 32 + read-write + 0x10A24447 + 0xFFFFFFFF + + + B + 30 bit Denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_ENET + Analog ENET PLL Control Register + 0xE0 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + ENET0_DIV_SELECT + Controls the frequency of the ethernet0 reference clock. + 0 + 2 + read-write + + + ENET0_DIV_SELECT_0 + 25MHz + 0 + + + ENET0_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET0_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET0_DIV_SELECT_3 + 125MHz + 0x3 + + + + + ENET1_DIV_SELECT + Controls the frequency of the ethernet1 reference clock. + 0x2 + 2 + read-write + + + ENET1_DIV_SELECT_0 + 25MHz + 0 + + + ENET1_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET1_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET1_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENET1_125M_EN + Enable the PLL providing the ENET1 125 MHz reference clock. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + ENABLE_125M + Enables an offset in the phase frequency detector. + 0x13 + 1 + read-write + + + ENET2_125M_EN + Enable the PLL providing the ENET2 125 MHz reference clock + 0x14 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 0x15 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ENET_SET + Analog ENET PLL Control Register + 0xE4 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + ENET0_DIV_SELECT + Controls the frequency of the ethernet0 reference clock. + 0 + 2 + read-write + + + ENET0_DIV_SELECT_0 + 25MHz + 0 + + + ENET0_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET0_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET0_DIV_SELECT_3 + 125MHz + 0x3 + + + + + ENET1_DIV_SELECT + Controls the frequency of the ethernet1 reference clock. + 0x2 + 2 + read-write + + + ENET1_DIV_SELECT_0 + 25MHz + 0 + + + ENET1_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET1_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET1_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENET1_125M_EN + Enable the PLL providing the ENET1 125 MHz reference clock. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + ENABLE_125M + Enables an offset in the phase frequency detector. + 0x13 + 1 + read-write + + + ENET2_125M_EN + Enable the PLL providing the ENET2 125 MHz reference clock + 0x14 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 0x15 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ENET_CLR + Analog ENET PLL Control Register + 0xE8 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + ENET0_DIV_SELECT + Controls the frequency of the ethernet0 reference clock. + 0 + 2 + read-write + + + ENET0_DIV_SELECT_0 + 25MHz + 0 + + + ENET0_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET0_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET0_DIV_SELECT_3 + 125MHz + 0x3 + + + + + ENET1_DIV_SELECT + Controls the frequency of the ethernet1 reference clock. + 0x2 + 2 + read-write + + + ENET1_DIV_SELECT_0 + 25MHz + 0 + + + ENET1_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET1_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET1_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENET1_125M_EN + Enable the PLL providing the ENET1 125 MHz reference clock. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + ENABLE_125M + Enables an offset in the phase frequency detector. + 0x13 + 1 + read-write + + + ENET2_125M_EN + Enable the PLL providing the ENET2 125 MHz reference clock + 0x14 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 0x15 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ENET_TOG + Analog ENET PLL Control Register + 0xEC + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + ENET0_DIV_SELECT + Controls the frequency of the ethernet0 reference clock. + 0 + 2 + read-write + + + ENET0_DIV_SELECT_0 + 25MHz + 0 + + + ENET0_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET0_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET0_DIV_SELECT_3 + 125MHz + 0x3 + + + + + ENET1_DIV_SELECT + Controls the frequency of the ethernet1 reference clock. + 0x2 + 2 + read-write + + + ENET1_DIV_SELECT_0 + 25MHz + 0 + + + ENET1_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET1_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET1_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENET1_125M_EN + Enable the PLL providing the ENET1 125 MHz reference clock. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + ENABLE_125M + Enables an offset in the phase frequency detector. + 0x13 + 1 + read-write + + + ENET2_125M_EN + Enable the PLL providing the ENET2 125 MHz reference clock + 0x14 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 0x15 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PFD_480 + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF0 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_480_SET + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF4 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_480_CLR + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF8 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_480_TOG + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xFC + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_528 + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x100 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_528_SET + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x104 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_528_CLR + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x108 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_528_TOG + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x10C + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 0x3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 0x4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 0x7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 0xA + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 0xC + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 0xD + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 0xF + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 0x10 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 0x19 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 0x1A + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 0x1D + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 0x1E + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 0x1F + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 0x3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 0x4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 0x7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 0xA + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 0xC + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 0xD + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 0xF + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 0x10 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 0x19 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 0x1A + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 0x1D + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 0x1E + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 0x1F + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 0x3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 0x4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 0x7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 0xA + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 0xC + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 0xD + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 0xF + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 0x10 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 0x19 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 0x1A + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 0x1D + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 0x1E + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 0x1F + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 0x3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 0x4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 0x7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 0xA + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 0xC + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 0xD + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 0xF + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 0x10 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 0x19 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 0x1A + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 0x1D + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 0x1E + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 0x1F + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 0xA + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 0xC + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 0x10 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 0x11 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 0x1B + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 0x1C + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 0x1D + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 0x1E + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 0x1F + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 0xA + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 0xC + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 0x10 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 0x11 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 0x1B + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 0x1C + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 0x1D + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 0x1E + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 0x1F + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 0xA + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 0xC + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 0x10 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 0x11 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 0x1B + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 0x1C + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 0x1D + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 0x1E + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 0x1F + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 0xA + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 0xC + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 0x10 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 0x11 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 0x1B + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 0x1C + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 0x1D + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 0x1E + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 0x1F + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Register 2 + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x5 + 1 + read-write + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 0x7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 0xB + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0xD + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 0xF + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x10 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x13 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x15 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 0x16 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 0x17 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x18 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1A + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1C + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 0x1E + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Register 2 + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x5 + 1 + read-write + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 0x7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 0xB + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0xD + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 0xF + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x10 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x13 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x15 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 0x16 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 0x17 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x18 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1A + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1C + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 0x1E + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Register 2 + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x5 + 1 + read-write + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 0x7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 0xB + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0xD + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 0xF + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x10 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x13 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x15 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 0x16 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 0x17 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x18 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1A + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1C + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 0x1E + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Register 2 + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x5 + 1 + read-write + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 0x7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 0xB + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0xD + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 0xF + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x10 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x13 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x15 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 0x16 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 0x17 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x18 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1A + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1C + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 0x1E + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + + + PMU + PMU + PMU + PMU_ + 0x20C8110 + + 0 + 0x170 + registers + + + PMU_IRQ1 + 86 + + + PMU_IRQ2 + 159 + + + + REG_1P1 + Regulator 1P1 Register + 0 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 0x1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 0x2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 0x3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 0x4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 0x8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 0x10 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 0x11 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 0x12 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 0x13 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_CAP voltage + 0x1 + + + + + + + REG_3P0 + Regulator 3P0 Register + 0x10 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 0x1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 0x2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 0x4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 0x7 + 1 + read-write + + + USB_OTG1_VBUS + Utilize VBUS OTG1 for power + 0 + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 0x8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 0x10 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 0x11 + 1 + read-only + + + + + REG_2P5 + Regulator 2P5 Register + 0x20 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 0x1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 0x2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 0x3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 0x4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 0x8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 0x10 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 0x11 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 0x12 + 1 + read-write + + + + + REG_CORE + Digital Regulator Core Register + 0x30 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 0x12 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + RAMP_RATE + Regulator voltage ramp rate. + 0x1B + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 0x1D + 1 + read-write + + + + + LOWPWR_CTRL + Low Power Control Register + 0x160 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + RC_OSC_PROG + RC osc. tuning values. + 0x1 + 3 + read-write + + + OSC_SEL + Select the source for the 24MHz clock. + 0x4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 0x5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 0x6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 0x7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 0x8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 0x9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 0xA + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 0xB + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 0xD + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 0xE + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 0x10 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 0x11 + 1 + read-write + + + + + LOWPWR_CTRL_SET + Low Power Control Register + 0x164 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. Not related to PMU. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + RC_OSC_PROG + RC osc. tuning values. Not related to PMU. + 0x1 + 3 + read-write + + + OSC_SEL + Select the source for the 24MHz clock. Not related to PMU. + 0x4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. + 0x5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. + 0x6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. + 0x7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. + 0x8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. + 0x9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override.Test purpose only + 0xA + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. + 0xB + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 0xD + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 0xE + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. Not related to PMU. + 0x10 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 0x11 + 1 + read-write + + + + + LOWPWR_CTRL_CLR + Low Power Control Register + 0x168 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. Not related to PMU. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + RC_OSC_PROG + RC osc. tuning values. Not related to PMU. + 0x1 + 3 + read-write + + + OSC_SEL + Select the source for the 24MHz clock. Not related to PMU. + 0x4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. + 0x5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. + 0x6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. + 0x7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. + 0x8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. + 0x9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override.Test purpose only + 0xA + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. + 0xB + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 0xD + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 0xE + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. Not related to PMU. + 0x10 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 0x11 + 1 + read-write + + + + + LOWPWR_CTRL_TOG + Low Power Control Register + 0x16C + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. Not related to PMU. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + RC_OSC_PROG + RC osc. tuning values. Not related to PMU. + 0x1 + 3 + read-write + + + OSC_SEL + Select the source for the 24MHz clock. Not related to PMU. + 0x4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. + 0x5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. + 0x6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. + 0x7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. + 0x8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. + 0x9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override.Test purpose only + 0xA + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. + 0xB + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 0xD + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 0xE + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. Not related to PMU. + 0x10 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 0x11 + 1 + read-write + + + + + + + TEMPMON + Temperature Monitor + TEMPMON + TEMPMON_ + 0x20C8180 + + 0 + 0x120 + registers + + + TEMPMON + 81 + + + + TEMPSENSE0 + Tempsensor Control Register 0 + 0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 0x1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 0x2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 0x8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 0x14 + 12 + read-write + + + + + TEMPSENSE0_SET + Tempsensor Control Register 0 + 0x4 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 0x1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 0x2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 0x8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 0x14 + 12 + read-write + + + + + TEMPSENSE0_CLR + Tempsensor Control Register 0 + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 0x1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 0x2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 0x8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 0x14 + 12 + read-write + + + + + TEMPSENSE0_TOG + Tempsensor Control Register 0 + 0xC + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 0x1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 0x2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 0x8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 0x14 + 12 + read-write + + + + + TEMPSENSE1 + Tempsensor Control Register 1 + 0x10 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_SET + Tempsensor Control Register 1 + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_CLR + Tempsensor Control Register 1 + 0x18 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_TOG + Tempsensor Control Register 1 + 0x1C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE2 + Tempsensor Control Register 2 + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 0x10 + 12 + read-write + + + + + TEMPSENSE2_SET + Tempsensor Control Register 2 + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 0x10 + 12 + read-write + + + + + TEMPSENSE2_CLR + Tempsensor Control Register 2 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 0x10 + 12 + read-write + + + + + TEMPSENSE2_TOG + Tempsensor Control Register 2 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 0x10 + 12 + read-write + + + + + + + USB_ANALOG + USB Analog + USB_ANALOG + USB_ANALOG_ + 0x20C81A0 + + 0 + 0xC4 + registers + + + + USB1_VBUS_DETECT + USB VBUS Detect Register + 0 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB1_VBUS_DETECT_SET + USB VBUS Detect Register + 0x4 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB1_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x8 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB1_VBUS_DETECT_TOG + USB VBUS Detect Register + 0xC + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB1_CHRG_DETECT + USB Charger Detect Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_SET + USB Charger Detect Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_CLR + USB Charger Detect Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_TOG + USB Charger Detect Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 0x1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 0x2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 0x3 + 1 + read-only + + + + + USB1_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 0x1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 0x2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 0x3 + 1 + read-only + + + + + USB1_MISC + USB Misc Register + 0x50 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB1_MISC_SET + USB Misc Register + 0x54 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB1_MISC_CLR + USB Misc Register + 0x58 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB1_MISC_TOG + USB Misc Register + 0x5C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB2_VBUS_DETECT + USB VBUS Detect Register + 0x60 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB2_VBUS_DETECT_SET + USB VBUS Detect Register + 0x64 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB2_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x68 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB2_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x6C + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB2_CHRG_DETECT + USB Charger Detect Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_SET + USB Charger Detect Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_CLR + USB Charger Detect Register + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_TOG + USB Charger Detect Register + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 0x1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 0x2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 0x3 + 1 + read-only + + + + + USB2_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 0x1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 0x2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 0x3 + 1 + read-only + + + + + USB2_MISC + USB Misc Register + 0xB0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB2_MISC_SET + USB Misc Register + 0xB4 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB2_MISC_CLR + USB Misc Register + 0xB8 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB2_MISC_TOG + USB Misc Register + 0xBC + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + DIGPROG + Chip Silicon Version + 0xC0 + 32 + read-only + 0x640000 + 0xFFFFFFFF + + + MINOR + MINOR lower byte - Read-only value representing a minor silicon revision. + 0 + 8 + read-only + + + MINOR_0 + silicon revision x.0 + 0 + + + MINOR_1 + silicon revision x.1 + 0x1 + + + MINOR_2 + silicon revision x.2 + 0x2 + + + MINOR_3 + silicon revision x.3 + 0x3 + + + + + MAJOR_LOWER + MAJOR lower byte - Read-only value representing a major silicon revision. + 0x8 + 8 + read-only + + + MAJOR_LOWER_0 + silicon revision 1.x + 0 + + + MAJOR_LOWER_1 + silicon revision 2.x + 0x1 + + + + + MAJOR_UPPER + MAJOR upper byte-Read-only value representing the chip type. + 0x10 + 8 + read-only + + + MAJOR_UPPER_101 + i.MX 6ULL + 0x65 + + + + + + + + + XTALOSC24M + XTALOSC24M + XTALOSC24M + XTALOSC24M_ + 0x20C82A0 + + 0 + 0x30 + registers + + + + OSC_CONFIG0 + XTAL OSC Configuration 0 Register + 0 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 0x1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 0x2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 0x3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 0x4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 0xC + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 0x10 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 0x18 + 8 + read-write + + + + + OSC_CONFIG0_SET + XTAL OSC Configuration 0 Register + 0x4 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 0x1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 0x2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 0x3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 0x4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 0xC + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 0x10 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 0x18 + 8 + read-write + + + + + OSC_CONFIG0_CLR + XTAL OSC Configuration 0 Register + 0x8 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 0x1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 0x2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 0x3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 0x4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 0xC + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 0x10 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 0x18 + 8 + read-write + + + + + OSC_CONFIG0_TOG + XTAL OSC Configuration 0 Register + 0xC + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 0x1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 0x2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 0x3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 0x4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 0xC + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 0x10 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 0x18 + 8 + read-write + + + + + OSC_CONFIG1 + XTAL OSC Configuration 1 Register + 0x10 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 0x14 + 12 + read-write + + + + + OSC_CONFIG1_SET + XTAL OSC Configuration 1 Register + 0x14 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 0x14 + 12 + read-write + + + + + OSC_CONFIG1_CLR + XTAL OSC Configuration 1 Register + 0x18 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 0x14 + 12 + read-write + + + + + OSC_CONFIG1_TOG + XTAL OSC Configuration 1 Register + 0x1C + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 0x14 + 12 + read-write + + + + + OSC_CONFIG2 + XTAL OSC Configuration 2 Register + 0x20 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 0x10 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output. + 0x11 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32KHz period + 0x1F + 1 + read-write + + + + + OSC_CONFIG2_SET + XTAL OSC Configuration 2 Register + 0x24 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 0x10 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output. + 0x11 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32KHz period + 0x1F + 1 + read-write + + + + + OSC_CONFIG2_CLR + XTAL OSC Configuration 2 Register + 0x28 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 0x10 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output. + 0x11 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32KHz period + 0x1F + 1 + read-write + + + + + OSC_CONFIG2_TOG + XTAL OSC Configuration 2 Register + 0x2C + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 0x10 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output. + 0x11 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32KHz period + 0x1F + 1 + read-write + + + + + + + USBPHY1 + USBPHY Register Reference Index + USBPHY + USBPHY1_ + 0x20C9000 + USBPHY + + 0 + 0x84 + registers + + + USB_PHY1 + 76 + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 0xA + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 0xB + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 0x11 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 0x12 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 0x13 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 0x14 + 1 + read-write + + + RSVD2 + Reserved. + 0x15 + 11 + read-only + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 0xA + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 0xB + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 0x11 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 0x12 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 0x13 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 0x14 + 1 + read-write + + + RSVD2 + Reserved. + 0x15 + 11 + read-only + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 0xA + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 0xB + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 0x11 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 0x12 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 0x13 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 0x14 + 1 + read-write + + + RSVD2 + Reserved. + 0x15 + 11 + read-only + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 0xA + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 0xB + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 0x11 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 0x12 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 0x13 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 0x14 + 1 + read-write + + + RSVD2 + Reserved. + 0x15 + 11 + read-only + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0x4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 0x8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 0xC + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 0x10 + 4 + read-write + + + RSVD2 + Reserved. + 0x14 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 0x1A + 3 + read-write + + + RSVD5 + Reserved. + 0x1D + 3 + read-only + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0x4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 0x8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 0xC + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 0x10 + 4 + read-write + + + RSVD2 + Reserved. + 0x14 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 0x1A + 3 + read-write + + + RSVD5 + Reserved. + 0x1D + 3 + read-only + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0x4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 0x8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 0xC + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 0x10 + 4 + read-write + + + RSVD2 + Reserved. + 0x14 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 0x1A + 3 + read-write + + + RSVD5 + Reserved. + 0x1D + 3 + read-only + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0x4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 0x8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 0xC + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 0x10 + 4 + read-write + + + RSVD2 + Reserved. + 0x14 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 0x1A + 3 + read-write + + + RSVD5 + Reserved. + 0x1D + 3 + read-only + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 0x3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 0x4 + 3 + read-write + + + RSVD1 + Reserved. + 0x7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 0x16 + 1 + read-write + + + RSVD2 + Reserved. + 0x17 + 9 + read-only + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 0x3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 0x4 + 3 + read-write + + + RSVD1 + Reserved. + 0x7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 0x16 + 1 + read-write + + + RSVD2 + Reserved. + 0x17 + 9 + read-only + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 0x3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 0x4 + 3 + read-write + + + RSVD1 + Reserved. + 0x7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 0x16 + 1 + read-write + + + RSVD2 + Reserved. + 0x17 + 9 + read-only + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 0x3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 0x4 + 3 + read-write + + + RSVD1 + Reserved. + 0x7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 0x16 + 1 + read-write + + + RSVD2 + Reserved. + 0x17 + 9 + read-only + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 0x1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 0x2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 0x3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 0x4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 0x5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 0x6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 0x7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 0x8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 0x9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 0xA + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 0xB + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 0xC + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 0xD + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 0xE + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 0xF + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 0x10 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 0x11 + 1 + read-write + + + RSVD0 + Reserved. + 0x12 + 1 + read-only + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 0x13 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 0x14 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 0x15 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 0x16 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 0x17 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 0x18 + 1 + read-write + + + RSVD1 + Reserved. + 0x19 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 0x1B + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 0x1C + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 0x1D + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 0x1E + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 0x1F + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 0x1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 0x2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 0x3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 0x4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 0x5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 0x6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 0x7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 0x8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 0x9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 0xA + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 0xB + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 0xC + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 0xD + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 0xE + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 0xF + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 0x10 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 0x11 + 1 + read-write + + + RSVD0 + Reserved. + 0x12 + 1 + read-only + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 0x13 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 0x14 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 0x15 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 0x16 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 0x17 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 0x18 + 1 + read-write + + + RSVD1 + Reserved. + 0x19 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 0x1B + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 0x1C + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 0x1D + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 0x1E + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 0x1F + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 0x1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 0x2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 0x3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 0x4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 0x5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 0x6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 0x7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 0x8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 0x9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 0xA + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 0xB + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 0xC + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 0xD + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 0xE + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 0xF + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 0x10 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 0x11 + 1 + read-write + + + RSVD0 + Reserved. + 0x12 + 1 + read-only + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 0x13 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 0x14 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 0x15 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 0x16 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 0x17 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 0x18 + 1 + read-write + + + RSVD1 + Reserved. + 0x19 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 0x1B + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 0x1C + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 0x1D + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 0x1E + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 0x1F + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 0x1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 0x2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 0x3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 0x4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 0x5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 0x6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 0x7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 0x8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 0x9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 0xA + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 0xB + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 0xC + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 0xD + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 0xE + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 0xF + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 0x10 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 0x11 + 1 + read-write + + + RSVD0 + Reserved. + 0x12 + 1 + read-only + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 0x13 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 0x14 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 0x15 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 0x16 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 0x17 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 0x18 + 1 + read-write + + + RSVD1 + Reserved. + 0x19 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 0x1B + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 0x1C + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 0x1D + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 0x1E + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 0x1F + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 3 + read-only + + + HOSTDISCONDETECT_STATUS + Indicates that the device has disconnected while in high-speed host mode. + 0x3 + 1 + read-only + + + RSVD1 + Reserved. + 0x4 + 2 + read-only + + + DEVPLUGIN_STATUS + Indicates that the device has been connected on the USB_DP and USB_DM lines. + 0x6 + 1 + read-only + + + RSVD2 + Reserved. + 0x7 + 1 + read-only + + + OTGID_STATUS + Indicates the results of ID pin on MiniAB plug + 0x8 + 1 + read-write + + + RSVD3 + Reserved. + 0x9 + 1 + read-only + + + RESUME_STATUS + Indicates that the host is sending a wake-up after suspend and has triggered an interrupt. + 0xA + 1 + read-only + + + RSVD4 + Reserved. + 0xB + 21 + read-only + + + + + DEBUG + USB PHY Debug Register + 0x50 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 0x1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 0x2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 0x4 + 2 + read-write + + + RSVD0 + Reserved. + 0x6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 0x8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 0x10 + 5 + read-write + + + RSVD2 + Reserved. + 0x15 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 0x18 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 0x19 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 0x1D + 1 + read-write + + + CLKGATE + Gate Test Clocks + 0x1E + 1 + read-write + + + RSVD3 + Reserved. + 0x1F + 1 + read-only + + + + + DEBUG_SET + USB PHY Debug Register + 0x54 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 0x1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 0x2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 0x4 + 2 + read-write + + + RSVD0 + Reserved. + 0x6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 0x8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 0x10 + 5 + read-write + + + RSVD2 + Reserved. + 0x15 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 0x18 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 0x19 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 0x1D + 1 + read-write + + + CLKGATE + Gate Test Clocks + 0x1E + 1 + read-write + + + RSVD3 + Reserved. + 0x1F + 1 + read-only + + + + + DEBUG_CLR + USB PHY Debug Register + 0x58 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 0x1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 0x2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 0x4 + 2 + read-write + + + RSVD0 + Reserved. + 0x6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 0x8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 0x10 + 5 + read-write + + + RSVD2 + Reserved. + 0x15 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 0x18 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 0x19 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 0x1D + 1 + read-write + + + CLKGATE + Gate Test Clocks + 0x1E + 1 + read-write + + + RSVD3 + Reserved. + 0x1F + 1 + read-only + + + + + DEBUG_TOG + USB PHY Debug Register + 0x5C + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 0x1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 0x2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 0x4 + 2 + read-write + + + RSVD0 + Reserved. + 0x6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 0x8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 0x10 + 5 + read-write + + + RSVD2 + Reserved. + 0x15 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 0x18 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 0x19 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 0x1D + 1 + read-write + + + CLKGATE + Gate Test Clocks + 0x1E + 1 + read-write + + + RSVD3 + Reserved. + 0x1F + 1 + read-only + + + + + DEBUG0_STATUS + UTMI Debug Status Register 0 + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOOP_BACK_FAIL_COUNT + Running count of the failed pseudo-random generator loopback + 0 + 16 + read-only + + + UTMI_RXERROR_FAIL_COUNT + Running count of the UTMI_RXERROR. + 0x10 + 10 + read-only + + + SQUELCH_COUNT + Running count of the squelch reset instead of normal end for HS RX. + 0x1A + 6 + read-only + + + + + DEBUG1 + UTMI Debug Status Register 1 + 0x70 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 0xD + 2 + read-write + + + RSVD1 + Reserved. + 0xF + 17 + read-only + + + + + DEBUG1_SET + UTMI Debug Status Register 1 + 0x74 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 0xD + 2 + read-write + + + RSVD1 + Reserved. + 0xF + 17 + read-only + + + + + DEBUG1_CLR + UTMI Debug Status Register 1 + 0x78 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 0xD + 2 + read-write + + + RSVD1 + Reserved. + 0xF + 17 + read-only + + + + + DEBUG1_TOG + UTMI Debug Status Register 1 + 0x7C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 0xD + 2 + read-write + + + RSVD1 + Reserved. + 0xF + 17 + read-only + + + + + VERSION + UTMI RTL Version + 0x80 + 32 + read-only + 0x4020000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + + + USBPHY2 + USBPHY Register Reference Index + USBPHY + USBPHY2_ + 0x20CA000 + + 0 + 0x84 + registers + + + USB_PHY2 + 77 + + + + EPIT1 + EPIT + EPIT + EPIT1_ + 0x20D0000 + EPIT + + 0 + 0x14 + registers + + + EPIT1 + 88 + + + + CR + Control register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + This bit enables the EPIT + 0 + 1 + read-write + + + EN_0 + EPIT is disabled + 0 + + + EN_1 + EPIT is enabled + 0x1 + + + + + ENMOD + EPIT enable mode + 0x1 + 1 + read-write + + + ENMOD_0 + Counter starts counting from the value it had when it was disabled. + 0 + + + ENMOD_1 + Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0) + 0x1 + + + + + OCIEN + Output compare interrupt enable + 0x2 + 1 + read-write + + + OCIEN_0 + Compare interrupt disabled + 0 + + + OCIEN_1 + Compare interrupt enabled + 0x1 + + + + + RLD + Counter reload control + 0x3 + 1 + read-write + + + RLD_0 + When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode) + 0 + + + RLD_1 + When the counter reaches zero it reloads from the modulus register (set-and-forget mode) + 0x1 + + + + + PRESCALAR + Counter clock prescaler value + 0x4 + 12 + read-write + + + PRESCALAR_0 + Divide by 1 + 0 + + + PRESCALAR_1 + Divide by 2... + 0x1 + + + PRESCALAR_4095 + Divide by 4096 + 0xFFF + + + + + SWR + Software reset + 0x10 + 1 + read-write + + + SWR_0 + EPIT is out of reset + 0 + + + SWR_1 + EPIT is undergoing reset + 0x1 + + + + + IOVW + EPIT counter overwrite enable + 0x11 + 1 + read-write + + + IOVW_0 + Write to load register does not result in counter value being overwritten. + 0 + + + IOVW_1 + Write to load register results in immediate overwriting of counter value. + 0x1 + + + + + DBGEN + This bit is used to keep the EPIT functional in debug mode + 0x12 + 1 + read-write + + + DBGEN_0 + Inactive in debug mode + 0 + + + DBGEN_1 + Active in debug mode + 0x1 + + + + + WAITEN + This read/write control bit enables the operation of the EPIT during wait mode + 0x13 + 1 + read-write + + + WAITEN_0 + EPIT is disabled in wait mode + 0 + + + WAITEN_1 + EPIT is enabled in wait mode + 0x1 + + + + + STOPEN + EPIT stop mode enable + 0x15 + 1 + read-write + + + STOPEN_0 + EPIT is disabled in stop mode + 0 + + + STOPEN_1 + EPIT is enabled in stop mode + 0x1 + + + + + OM + EPIT output mode.This bit field determines the mode of EPIT output on the output pin. + 0x16 + 2 + read-write + + + OM_0 + EPIT output is disconnected from pad + 0 + + + OM_1 + Toggle output pin + 0x1 + + + OM_2 + Clear output pin + 0x2 + + + OM_3 + Set output pin + 0x3 + + + + + CLKSRC + Select clock source These bits determine which clock input is to be selected for running the counter + 0x18 + 2 + read-write + + + CLKSRC_0 + Clock is off + 0 + + + CLKSRC_1 + Peripheral clock + 0x1 + + + CLKSRC_2 + High-frequency reference clock + 0x2 + + + CLKSRC_3 + Low-frequency reference clock + 0x3 + + + + + + + SR + Status register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + OCIF + Output compare interrupt flag + 0 + 1 + read-write + oneToClear + + + OCIF_0 + Compare event has not occurred + 0 + + + OCIF_1 + Compare event occurred + 0x1 + + + + + + + LR + Load register + 0x8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + LOAD + Load value. Value that is loaded into the counter at the start of each count cycle. + 0 + 32 + read-write + + + + + CMPR + Compare register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPARE + Compare Value. When the counter value equals this bit field value a compare event is generated. + 0 + 32 + read-write + + + + + CNR + Counter register + 0x10 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + COUNT + Counter value. This contains the current value of the counter. + 0 + 32 + read-only + + + + + + + EPIT2 + EPIT + EPIT + EPIT2_ + 0x20D4000 + + 0 + 0x14 + registers + + + EPIT2 + 89 + + + + SRC + SRC + SRC + SRC_ + 0x20D8000 + + 0 + 0x48 + registers + + + SRC + 123 + + + SRC_Combined + 128 + + + + SCR + SRC Control Register + 0 + 32 + read-write + 0x521 + 0xFFFFFFFF + + + warm_reset_enable + WARM reset enable bit + 0 + 1 + read-write + + + warm_reset_enable_0 + WARM reset disabled + 0 + + + warm_reset_enable_1 + WARM reset enabled + 0x1 + + + + + warm_rst_bypass_count + Defines the XTALI cycles to count before bypassing the MMDC acknowledge for WARM reset + 0x5 + 2 + read-write + + + warm_rst_bypass_count_0 + Counter not to be used - system will wait until MMDC acknowledge until it is asserted. + 0 + + + warm_rst_bypass_count_1 + Wait 16 XTALI cycles before changing WARM reset to a COLD reset. + 0x1 + + + warm_rst_bypass_count_2 + Wait 32 XTALI cycles before changing WARM reset to a COLD reset. + 0x2 + + + warm_rst_bypass_count_3 + Wait 64 XTALI cycles before changing WARM reset to a COLD reset + 0x3 + + + + + mask_wdog_rst + Mask wdog_rst_b source + 0x7 + 4 + read-write + + + mask_wdog_rst_5 + wdog_rst_b is masked + 0x5 + + + mask_wdog_rst_10 + wdog_rst_b is not masked (default) + 0xA + + + + + eim_rst + EIM reset is needed in order to reconfigure the eim chip select + 0xB + 1 + read-write + + + core0_rst + Software reset for core0 only + 0xD + 1 + read-write + + + core0_rst_0 + do not assert core0 reset + 0 + + + core0_rst_1 + assert core0 reset + 0x1 + + + + + core0_dbg_rst + Software reset for core0 debug only + 0x11 + 1 + read-write + + + core0_dbg_rst_0 + do not assert core0 debug reset + 0 + + + core0_dbg_rst_1 + assert core0 debug reset + 0x1 + + + + + cores_dbg_rst + Software reset for debug of arm platform only + 0x15 + 1 + read-write + + + cores_dbg_rst_0 + do not assert arm platform debug reset + 0 + + + cores_dbg_rst_1 + assert arm platform debug reset + 0x1 + + + + + wdog3_rst_optn + Wdog3_rst_b option + 0x18 + 1 + read-write + + + wdog3_rst_optn_0 + Wdog3_rst_b asserts M4 reset (default) + 0 + + + wdog3_rst_optn_1 + Wdog3_rst_b asserts global reset + 0x1 + + + + + dbg_rst_msk_pg + Do not assert debug resets after power gating event of core + 0x19 + 1 + read-write + + + dbg_rst_msk_pg_0 + do not mask core debug resets (debug resets will be asserted after power gating event) + 0 + + + dbg_rst_msk_pg_1 + mask core debug resets (debug resets won't be asserted after power gating event) + 0x1 + + + + + mix_rst_strch + SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset stretch mix reset width = (mix_rst_strtch +1)* 88 ipg_clk cycles + 0x1A + 2 + read-write + + + mix_rst_strch_0 + mix reset width is 88 ipg_cycle cycles + 0 + + + mix_rst_strch_1 + mix reset width is 2 * 88 ipg_cycle cycles + 0x1 + + + mix_rst_strch_2 + mix reset width is 3 * 88 ipg_cycle cycles + 0x2 + + + mix_rst_strch_3 + mix reset width is 4 * 88 ipg_cycle cycles + 0x3 + + + + + mask_wdog3_rst + Mask wdog3_rst_b source + 0x1C + 4 + read-write + + + mask_wdog3_rst_5 + wdog3_rst_b is masked + 0x5 + + + mask_wdog3_rst_10 + wdog3_rst_b is not masked + 0xA + + + + + + + SBMR1 + SRC Boot Mode Register 1 + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + BOOT_CFG1 + Refer to fusemap. + 0 + 8 + read-only + + + BOOT_CFG2 + Refer to fusemap. + 0x8 + 8 + read-only + + + BOOT_CFG3 + Refer to fusemap. + 0x10 + 8 + read-only + + + BOOT_CFG4 + Refer to fusemap. + 0x18 + 8 + read-only + + + + + SRSR + SRC Reset Status Register + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ipp_reset_b + Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) + 0 + 1 + read-write + oneToClear + + + ipp_reset_b_0 + Reset is not a result of ipp_reset_b pin. + 0 + + + ipp_reset_b_1 + Reset is a result of ipp_reset_b pin. + 0x1 + + + + + csu_reset_b + Indicates whether the reset was the result of the csu_reset_b input + 0x2 + 1 + read-write + oneToClear + + + csu_reset_b_0 + Reset is not a result of the csu_reset_b event. + 0 + + + csu_reset_b_1 + Reset is a result of the csu_reset_b event. + 0x1 + + + + + ipp_user_reset_b + Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. + 0x3 + 1 + read-write + oneToClear + + + ipp_user_reset_b_0 + Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + 0 + + + ipp_user_reset_b_1 + Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + 0x1 + + + + + wdog_rst_b + IC Watchdog Time-out reset + 0x4 + 1 + read-write + oneToClear + + + wdog_rst_b_0 + Reset is not a result of the watchdog time-out event. + 0 + + + wdog_rst_b_1 + Reset is a result of the watchdog time-out event. + 0x1 + + + + + jtag_rst_b + HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. + 0x5 + 1 + read-write + oneToClear + + + jtag_rst_b_0 + Reset is not a result of HIGH-Z reset from JTAG. + 0 + + + jtag_rst_b_1 + Reset is a result of HIGH-Z reset from JTAG. + 0x1 + + + + + jtag_sw_rst + JTAG software reset. Indicates whether the reset was the result of software reset from JTAG. + 0x6 + 1 + read-write + oneToClear + + + jtag_sw_rst_0 + Reset is not a result of software reset from JTAG. + 0 + + + jtag_sw_rst_1 + Reset is a result of software reset from JTAG. + 0x1 + + + + + wdog3_rst_b + IC Watchdog3 Time-out reset + 0x7 + 1 + read-write + oneToClear + + + wdog3_rst_b_0 + Reset is not a result of the watchdog3 time-out event. + 0 + + + wdog3_rst_b_1 + Reset is a result of the watchdog3 time-out event. + 0x1 + + + + + tempsense_rst_b + Temper Sensor software reset + 0x8 + 1 + read-write + + + tempsense_rst_b_0 + Reset is not a result of software reset from Temperature Sensor. + 0 + + + tempsense_rst_b_1 + Reset is a result of software reset from Temperature Sensor. + 0x1 + + + + + warm_boot + WARM boot indication shows that WARM boot was initiated by software + 0x10 + 1 + read-write + + + warm_boot_0 + WARM boot process not initiated by software. + 0 + + + warm_boot_1 + WARM boot initiated by software. + 0x1 + + + + + + + SISR + SRC Interrupt Status Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + core0_wdog_rst_req + WDOG reset request from core0. Read-only status bit. + 0x5 + 1 + read-only + + + + + SBMR2 + SRC Boot Mode Register 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_CONFIG + SECONFIG[1] shows the state of the SECONFIG[1] fuse + 0 + 2 + read-only + + + DIR_BT_DIS + DIR_BT_DIS shows the state of the DIR_BT_DIS fuse + 0x3 + 1 + read-only + + + BT_FUSE_SEL + BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse + 0x4 + 1 + read-only + + + BMOD + BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B + 0x18 + 2 + read-only + + + + + GPR1 + SRC General Purpose Register 1 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY0 + Holds entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR2 + SRC General Purpose Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG0 + Holds argument of entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR3 + SRC General Purpose Register 3 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR4 + SRC General Purpose Register 4 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR5 + SRC General Purpose Register 5 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR6 + SRC General Purpose Register 6 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR7 + SRC General Purpose Register 7 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR8 + SRC General Purpose Register 8 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR9 + SRC General Purpose Register 9 + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + SRC General Purpose Register 10 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + + + GPC + GPC + GPC + GPC_ + 0x20DC000 + + 0 + 0x28 + registers + + + GPC + 121 + + + + CNTR + GPC Interface control register + 0 + 32 + read-write + 0x520000 + 0xFFFFFFFF + + + MEGA_PDN_REQ + MEGA domain power down request + 0x2 + 1 + read-write + + + MEGA_PDN_REQ_0 + No Request + 0 + + + MEGA_PDN_REQ_1 + Request power down sequence + 0x1 + + + + + MEGA_PUP_REQ + MEGA domain power up request + 0x3 + 1 + read-write + + + MEGA_PUP_REQ_0 + No Request + 0 + + + MEGA_PUP_REQ_1 + Request power up sequence + 0x1 + + + + + DISPLAY_PDN_REQ + Display Power Down request + 0x4 + 1 + read-write + + + DISPLAY_PDN_REQ_0 + no request + 0 + + + DISPLAY_PDN_REQ_1 + Request Power Down sequence to start for Display + 0x1 + + + + + DISPLAY_PUP_REQ + Display Power Up request + 0x5 + 1 + read-write + + + DISPLAY_PUP_REQ_0 + no request + 0 + + + DISPLAY_PUP_REQ_1 + Request Power Up sequence to start for Display + 0x1 + + + + + DVFS0CR + DVFS0 (ARM) Change request (bit is read-only) + 0x10 + 1 + read-only + + + DVFS0CR_0 + DVFS0 has no request + 0 + + + DVFS0CR_1 + DVFS0 is requesting for frequency/voltage update + 0x1 + + + + + VADC_ANALOG_OFF + Indication to VADC whether the analog power to VADC is available or not + 0x11 + 1 + read-write + + + VADC_ANALOG_OFF_0 + VADC analog power is on + 0 + + + VADC_ANALOG_OFF_1 + VADC analog power is off + 0x1 + + + + + VADC_EXT_PWD_N + VADC power down bit + 0x12 + 1 + read-write + + + VADC_EXT_PWD_N_0 + VADC power down + 0 + + + VADC_EXT_PWD_N_1 + VADC not power down + 0x1 + + + + + GPCIRQM + GPC interrupt/event masking + 0x15 + 1 + read-write + + + GPCIRQM_0 + not masked + 0 + + + GPCIRQM_1 + interrupt/event is masked + 0x1 + + + + + L2_PGE + L2 Cache Power Gate Enable + 0x16 + 1 + read-write + + + L2_PGE_0 + L2 cache will keep power on even if CPU core is power down and will not be hardware invalidated when CPU core is re-power up the reset value is 1'b1 + 0 + + + L2_PGE_1 + L2 cache power gate off request, L2 cache will be power down once when CPU core is power down and will be hardware invalidated automatically when CPU core is re-power up + 0x1 + + + + + + + PGR + GPC Power Gating Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRCIC + Debug ref cir in mux control + 0x1D + 2 + read-write + + + DRCIC_0 + ccm_cosr_1_clk_in + 0 + + + DRCIC_1 + ccm_cosr_2_clk_in + 0x1 + + + DRCIC_2 + restricted + 0x2 + + + DRCIC_3 + restricted + 0x3 + + + + + + + IMR1 + IRQ masking register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1 + IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR2 + IRQ masking register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2 + IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR3 + IRQ masking register 3 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3 + IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR4 + IRQ masking register 4 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4 + IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR1 + IRQ status resister 1 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR1 + IRQ[63:32] status, read only + 0 + 32 + read-only + + + + + ISR2 + IRQ status resister 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR2 + IRQ[95:64] status, read only + 0 + 32 + read-only + + + + + ISR3 + IRQ status resister 3 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR3 + IRQ[127:96] status, read only + 0 + 32 + read-only + + + + + ISR4 + IRQ status resister 4 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + IRQ[159:128] status, read only + 0 + 32 + read-only + + + + + + + DVFSC + DVFSC + DVFSC + DVFSC_ + 0x20DC180 + + 0 + 0x44 + registers + + + + THRS + DVFS Thresholds + 0 + 32 + read-write + 0xFAF003E + 0xFFFFFFFF + + + PNCTHR + Panic threshold for load tracking + 0 + 6 + read-write + + + DWTHR + Down threshold for load tracking + 0x10 + 6 + read-write + + + UPTHR + Upper threshold for load tracking + 0x16 + 6 + read-write + + + + + COUN + DVFS Counters thresholds + 0x4 + 32 + read-write + 0x70020 + 0xFFFFFFFF + + + UPCNT + UP counter threshold value + 0 + 8 + read-write + + + DN_CNT + Down counter threshold value + 0x10 + 8 + read-write + + + + + SIG1 + DVFS general purpose bits weight + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + WSW6 + General purpose load tracking signal weight dvfs_w_sig[6] + 0x2 + 3 + read-write + + + WSW7 + General purpose load tracking signal weight dvfs_w_sig[7] + 0x5 + 3 + read-write + + + WSW8 + General purpose load tracking signal weight dvfs_w_sig[8] + 0x8 + 3 + read-write + + + WSW9 + General purpose load tracking signal weight dvfs_w_sig[9] + 0xB + 3 + read-write + + + WSW10 + General purpose load tracking signal weight dvfs_w_sig[10] + 0xE + 3 + read-write + + + WSW11 + General purpose load tracking signal weight dvfs_w_sig[11] + 0x11 + 3 + read-write + + + WSW12 + General purpose load tracking signal weight dvfs_w_sig[12] + 0x14 + 3 + read-write + + + WSW13 + General purpose load tracking signal weight dvfs_w_sig[13] + 0x17 + 3 + read-write + + + WSW14 + General purpose load tracking signal weight dvfs_w_sig[14] + 0x1A + 3 + read-write + + + WSW15 + General purpose load tracking signal weight dvfs_w_sig[15] + 0x1D + 3 + read-write + + + + + DVFSSIG0 + DVFS general purpose bits weight + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WSW0 + General purpose load tracking signal weight dvfs_w_sig[0] + 0 + 6 + read-write + + + WSW1 + General purpose load tracking signal weight dvfs_w_sig[1] + 0x6 + 6 + read-write + + + WSW2 + General purpose load tracking signal weight dvfs_w_sig[2] + 0x14 + 3 + read-write + + + WSW3 + General purpose load tracking signal weight dvfs_w_sig[3] + 0x17 + 3 + read-write + + + WSW4 + General purpose load tracking signal weight dvfs_w_sig[4] + 0x1A + 3 + read-write + + + WSW5 + General purpose load tracking signal weight dvfs_w_sig[5] + 0x1D + 3 + read-write + + + + + DVFSGPC0 + DVFS general purpose bit 0 weight counter + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPBC0 + GPBC0 - General Purpose bits Counter 0 During period of this counter the GeP bit 0 will be set and WSW0 will be added to the calculations + 0 + 17 + read-write + + + C0ACT + C0ACT - Counter 0 active indicator + 0x1E + 1 + read-only + + + C0ACT_0 + General Purpose bit0 counter reached value of "0" - the instead of WSW0, "0" (zero) is provided to DVFS calculation + 0 + + + C0ACT_1 + General Purpose bit0 counter didn't reach value of "0" - the WSW0 is provided to DVFS calculation + 0x1 + + + + + C0STRT + C0STRT - Counter 0 start Setting of this bit will initialize down counting of the GPC0 value + 0x1F + 1 + read-write + + + + + DVFSGPC1 + DVFS general purpose bit 1 weight counter + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPBC1 + GPBC1 - General Purpose bits Counter 1 During period of this counter the GeP bit 1 will be set and WSW1 will be added to the calculations + 0 + 17 + read-write + + + C1ACT + C1ACT - Counter 1 active indicator + 0x1E + 1 + read-only + + + C1ACT_0 + General Purpose bit1 counter reached value of "0" - the instead of WSW1, "0" (zero) is provided to DVFS calculation + 0 + + + C1ACT_1 + General Purpose bit1 counter didn't reach value of "0" - the WSW1 is provided to DVFS calculation + 0x1 + + + + + C1STRT + C1STRT - Counter 1start Setting of this bit will initialize down counting of the GPC1 value + 0x1F + 1 + read-write + + + + + DVFSGPBT + DVFS general purpose bits enables + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPB0 + General purpose bit 0 + 0 + 1 + read-write + + + GPB1 + General purpose bit 1 + 0x1 + 1 + read-write + + + GPB2 + General purpose bit 2. Its weight is set by WSW2 value. + 0x2 + 1 + read-write + + + GPB3 + General purpose bit 3. Its weight is set by WSW3 value. + 0x3 + 1 + read-write + + + GPB4 + General purpose bit 4. Its weight is set by WSW4 value. + 0x4 + 1 + read-write + + + GPB5 + General purpose bit 5. Its weight is set by WSW5 value. + 0x5 + 1 + read-write + + + GPB6 + General purpose bit 6. Its weight is set by WSW6 value. + 0x6 + 1 + read-write + + + GPB7 + General purpose bit 7. Its weight is set by WSW7 value. + 0x7 + 1 + read-write + + + GPB8 + General purpose bit 8. Its weight is set by WSW8 value. + 0x8 + 1 + read-write + + + GPB9 + General purpose bit 9. Its weight is set by WSW9 value. + 0x9 + 1 + read-write + + + GPB10 + General purpose bit 10. Its weight is set by WSW10 value. + 0xA + 1 + read-write + + + GPB11 + General purpose bit 11. Its weight is set by WSW11 value. + 0xB + 1 + read-write + + + GPB12 + General purpose bit 12. Its weight is set by WSW12 value. + 0xC + 1 + read-write + + + GPB13 + General purpose bit 13. Its weight is set by WSW13 value. + 0xD + 1 + read-write + + + GPB14 + General purpose bit 14. Its weight is set by WSW14 value. + 0xE + 1 + read-write + + + GPB15 + General purpose bit 15. Its weight is set by WSW15 value. + 0xF + 1 + read-write + + + + + DVFSEMAC + DVFS EMAC settings + 0x1C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + EMAC + EMAC - EMA control value + 0 + 9 + read-write + + + DVFEN0 + DVFS tracking for core0 enable. + 0x9 + 1 + read-write + + + DVFEN0_0 + DVFS disabled. + 0 + + + DVFEN0_1 + DVFS enabled. + 0x1 + + + + + FSVAI0 + DVFS Frequency adjustment status of core 0 + 0x10 + 2 + read-only + + + FSVAI0_0 + no change + 0 + + + FSVAI0_1 + frequency should be increased. Low priority source for interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + 0x1 + + + FSVAI0_2 + frequency should be decreased. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MINF= 1 (lowest frequency). + 0x2 + + + FSVAI0_3 + frequency should be increased immediately. High priority source of interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + 0x3 + + + + + WFIM0 + DVFS Wait for Interrupt of core 0 mask bit + 0x18 + 1 + read-write + + + WFIM0_0 + Wait for interrupt of core 0 isn't masked + 0 + + + WFIM0_1 + Wait for interrupt of core 0 is masked. + 0x1 + + + + + + + CNTR + DVFS Control + 0x20 + 32 + read-write + 0x900000E + 0xFFFFFFFF + + + LTBRSR + LTBRSR - Load Tracking Buffer Register Source: + 0x3 + 2 + read-write + + + LTBRSR_0 + pre_ld_add + 0 + + + LTBRSR_1 + ld_add + 0x1 + + + LTBRSR_2 + ema_ld + 0x2 + + + + + LTBRSH + LTBRSH - Load Tracking Buffer Register Shift: + 0x5 + 1 + read-write + + + LTBRSH_0 + values of [5:2] of the selected input are saving in Load Tracking Buffer + 0 + + + LTBRSH_1 + values of [4:1] of the selected input are saving in Load Tracking Buffer + 0x1 + + + + + PFUS + PFUS - Periodic Frequency Update Status + 0x6 + 3 + read-only + + + PFUS_0 + no update + 0 + + + PFUS_4 + DVFSPT0 period, previous finished(can be performance level decrease) + 0x4 + + + PFUS_5 + DVFSPT1 period, previous finished(can be EMA-detected performance level) + 0x5 + + + PFUS_6 + DVFSPT2 period, previous finished(can be performance level increase) + 0x6 + + + PFUS_7 + DVFSPT3 period, previous finished (can be EMA-detected performance level) + 0x7 + + + + + PFUE + PFUE - Period Frequency Update Enable + 0x9 + 1 + read-write + + + PFUE_0 + disabled + 0 + + + PFUE_1 + enabled + 0x1 + + + + + DIV_RATIO + DIV_RATIO - Divider value. Divider divides the input ARM clock, following the table + 0xB + 6 + read-write + + + MINF + Minimum frequency reached + 0x11 + 1 + read-write + + + MINF_0 + min frequency not reached + 0 + + + MINF_1 + min frequency reached + 0x1 + + + + + MAXF + Maximum frequency reached + 0x12 + 1 + read-write + + + MAXF_0 + max frequency not reached + 0 + + + MAXF_1 + max frequency reached + 0x1 + + + + + FSVAI + FSVAI DVFS Frequency adjustment interrupt + 0x14 + 2 + read-only + + + FSVAI_0 + no interrupt + 0 + + + FSVAI_1 + frequency should be increased. Low priority interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + 0x1 + + + FSVAI_2 + frequency should be decreased. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MINF= 1 (lowest frequency). + 0x2 + + + FSVAI_3 + frequency should be increased immediately. High priority interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + 0x3 + + + + + FSVAIM + DVFS Frequency adjustment interrupt mask + 0x16 + 1 + read-write + + + FSVAIM_0 + interrupt is enabled. + 0 + + + FSVAIM_1 + interrupt is masked. + 0x1 + + + + + PIRQS + PIRQS - Pattern IRQ Source * write '1' to clear + 0x17 + 1 + read-write + + + PIRQS_0 + DVFS IRQ source was not from pattern + 0 + + + PIRQS_1 + DVFS IRQ source was from pattern + 0x1 + + + + + DVFIS + DVFS Interrupt select. These bits define destination of DVFS interrupts. + 0x18 + 1 + read-write + + + DVFIS_0 + SDMA interrupt will be generated for DVFS events. + 0 + + + DVFIS_1 + MCU interrupt will be generated for DVFS events. + 0x1 + + + + + LBFL0 + Load buffer 0 - full status bit + 0x19 + 1 + read-write + + + LBFL0_0 + Load buffer1 is not full. + 0 + + + LBFL0_1 + Load buffer1 is full. + 0x1 + + + + + LBFL1 + Load buffer 1 - full status bit + 0x1A + 1 + read-write + + + LBFL1_0 + Load buffer0 is not full. + 0 + + + LBFL1_1 + Load buffer0 is full. + 0x1 + + + + + LBMI + Load buffer full mask interrupt + 0x1B + 1 + read-write + + + DVFEV + Always give a DVFS event. + 0x1C + 1 + read-write + + + DVFEV_0 + Do not give an event always. + 0 + + + DVFEV_1 + Always give event. + 0x1 + + + + + DIV3CK + DIV3CK - div_3_clk division ratio inside the DVFS module. According to the + 0x1D + 3 + read-write + + + + + DVFSLTR0_0 + DVFS Load Tracking Register 0, portion 0 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS0_0 + core 0 Load Tracking Sample 0 + 0 + 4 + read-only + + + LTS0_1 + core 0 Load Tracking Sample 1 + 0x4 + 4 + read-only + + + LTS0_2 + core 0 Load Tracking Sample 2 + 0x8 + 4 + read-only + + + LTS0_3 + core 0 Load Tracking Sample 3 + 0xC + 4 + read-only + + + LTS0_4 + core 0 Load Tracking Sample 4 + 0x10 + 4 + read-only + + + LTS0_5 + core 0 Load Tracking Sample 5 + 0x14 + 4 + read-only + + + LTS0_6 + core 0 Load Tracking Sample 6 + 0x18 + 4 + read-only + + + LTS0_7 + core 0 Load Tracking Sample 7 + 0x1C + 4 + read-only + + + + + DVFSLTR0_1 + DVFS Load Tracking Register 0, portion 1 + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS0_8 + core 0 Load Tracking Sample 8 + 0 + 4 + read-only + + + LTS0_9 + core 0 Load Tracking Sample 9 + 0x4 + 4 + read-only + + + LTS0_10 + core 0 Load Tracking Sample 10 + 0x8 + 4 + read-only + + + LTS0_11 + core 0 Load Tracking Sample 11 + 0xC + 4 + read-only + + + LTS0_12 + core 0 Load Tracking Sample 12 + 0x10 + 4 + read-only + + + LTS0_13 + core 0 Load Tracking Sample 13 + 0x14 + 4 + read-only + + + LTS0_14 + core 0 Load Tracking Sample 14 + 0x18 + 4 + read-only + + + LTS0_15 + core 0 Load Tracking Sample 15 + 0x1C + 4 + read-only + + + + + DVFSLTR1_0 + DVFS Load Tracking Register 1, portion 0 + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS1_0 + core 0 Load Tracking Sample 0 + 0 + 4 + read-only + + + LTS1_1 + core 0 Load Tracking Sample 1 + 0x4 + 4 + read-only + + + LTS1_2 + core 0 Load Tracking Sample 2 + 0x8 + 4 + read-only + + + LTS1_3 + core 0 Load Tracking Sample 3 + 0xC + 4 + read-only + + + LTS1_4 + core 0 Load Tracking Sample 4 + 0x10 + 4 + read-only + + + LTS1_5 + core 0 Load Tracking Sample 5 + 0x14 + 4 + read-only + + + LTS1_6 + core 0 Load Tracking Sample 6 + 0x18 + 4 + read-only + + + LTS1_7 + core 0 Load Tracking Sample 7 + 0x1C + 4 + read-only + + + + + DVFSLTR1_1 + DVFS Load Tracking Register 3, portion 1 + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS1_8 + core 0 Load Tracking Sample 8 + 0 + 4 + read-only + + + LTS1_9 + core 0 Load Tracking Sample 9 + 0x4 + 4 + read-only + + + LTS1_10 + core 0 Load Tracking Sample 10 + 0x8 + 4 + read-only + + + LTS1_11 + core 0 Load Tracking Sample 11 + 0xC + 4 + read-only + + + LTS1_12 + core 0 Load Tracking Sample 12 + 0x10 + 4 + read-only + + + LTS1_13 + core 0 Load Tracking Sample 13 + 0x14 + 4 + read-only + + + LTS1_14 + core 0 Load Tracking Sample 14 + 0x18 + 4 + read-only + + + LTS1_15 + core 0 Load Tracking Sample 15 + 0x1C + 4 + read-only + + + + + DVFSPT0 + DVFS pattern 0 length + 0x34 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN0 + FPTN0 - Frequency pattern 0 counter During period of this counter the frequency will be reduced from the EMA-detected level + 0 + 17 + read-write + + + PT0A + PT0A - Pattern 0 currently active (read-only) + 0x11 + 1 + read-only + + + PT0A_0 + non-active + 0 + + + PT0A_1 + active + 0x1 + + + + + + + DVFSPT1 + DVFS pattern 1 length + 0x38 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN1 + FPTN1 - Frequency pattern 1 counter During period of this counter the frequency will be set to the EMA-detected level + 0 + 17 + read-write + + + PT1A + PT1A - Pattern 1 currently active (read-only) + 0x11 + 1 + read-only + + + PT1A_0 + non-active + 0 + + + PT1A_1 + active + 0x1 + + + + + + + DVFSPT2 + DVFS pattern 2 length + 0x3C + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN2 + FPTN2 - Frequency pattern 2 counter During period of this counter the frequency will be increased to higher, than detected by the EMA-detected level + 0 + 17 + read-write + + + PT2A + PT2A - Pattern 2 currently active (read-only) + 0x11 + 1 + read-only + + + PT2A_0 + non-active + 0 + + + PT2A_1 + active + 0x1 + + + + + P2THR + P2THR - Pattern 2 Threshold Threshold of current DVFS load (after EMA), for generating interrupts with PFUS indicators 110, 111 + 0x1A + 6 + read-write + + + + + DVFSPT3 + DVFS pattern 3 length + 0x40 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN3 + FPTN3 - Frequency pattern 3 counter During period of this counter the frequency will be set to the EMA-detected level + 0 + 17 + read-write + + + PT3A + PT3A - Pattern 3 currently active (read-only) + 0x11 + 1 + read-only + + + PT3A_0 + non-active + 0 + + + PT3A_1 + active + 0x1 + + + + + + + + + PGC + PGC + PGC + PGC_ + 0x20DC220 + + 0 + 0x90 + registers + + + + MEGA_CTRL + PGC Mega Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + MEGA_PUPSCR + PGC Mega Power Up Sequence Control Register + 0x4 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b) + 0 + 6 + read-write + + + SW2ISO + After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation + 0x8 + 6 + read-write + + + + + MEGA_PDNSCR + PGC Mega Pull Down Sequence Control Register + 0x8 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b) + 0x8 + 6 + read-write + + + + + MEGA_SR + PGC Mega Power Gating Controller Status Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + CPU_CTRL + PGC CPU Control Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + CPU_PUPSCR + PGC CPU Power Up Sequence Control Register + 0x84 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + There are two different silicon revisions: 1 + 0 + 6 + read-write + + + SW2ISO + There are two different silicon revisions: 1 + 0x8 + 6 + read-write + + + + + CPU_PDNSCR + PGC CPU Pull Down Sequence Control Register + 0x88 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating + 0x8 + 6 + read-write + + + + + CPU_SR + PGC CPU Power Gating Controller Status Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + + + IOMUXC + IOMUXC + IOMUXC + IOMUXC_ + 0x20E0000 + + 0 + 0x6A0 + registers + + + + SW_MUX_CTL_PAD_JTAG_MOD + SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_MOD of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CLK of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SPDIF_OUT of instance: spdif + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_REF_CLK_25M of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CCM_PMIC_RDY of instance: ccm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO10 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT00 of instance: sdma + 0x6 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_MOD + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TMS + SW_MUX_CTL_PAD_JTAG_TMS SW MUX Control Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TMS of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_CLKO1 of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CCM_WAIT of instance: ccm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO11 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT01 of instance: sdma + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: EPIT1_OUT of instance: epit1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TMS + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TDO + SW_MUX_CTL_PAD_JTAG_TDO SW MUX Control Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TDO of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_CLKO2 of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CCM_STOP of instance: ccm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: MQS_RIGHT of instance: mqs + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: EPIT2_OUT of instance: epit2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TDO + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TDI + SW_MUX_CTL_PAD_JTAG_TDI SW MUX Control Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TDI of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2 + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: PWM6_OUT of instance: pwm6 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: MQS_LEFT of instance: mqs + 0x6 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TDI + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TCK + SW_MUX_CTL_PAD_JTAG_TCK SW MUX Control Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TCK of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2 + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: PWM7_OUT of instance: pwm7 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO14 of instance: gpio1 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TCK + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TRST_B + SW_MUX_CTL_PAD_JTAG_TRST_B SW MUX Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TRSTB of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE3 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2 + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: PWM8_OUT of instance: pwm8 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TRST_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO00 + SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register + 0x5C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: I2C2_SCL of instance: i2c2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_CAPTURE1 of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ANATOP_OTG1_ID of instance: anatop + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_REF_CLK1 of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: MQS_RIGHT of instance: mqs + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET1_1588_EVENT0_IN of instance: enet1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: SRC_SYSTEM_RESET of instance: src + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG3_WDOG_B of instance: wdog3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO01 + SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register + 0x60 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: I2C2_SDA of instance: i2c2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_COMPARE1 of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG1_OC of instance: usb + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_REF_CLK2 of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: MQS_LEFT of instance: mqs + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET1_1588_EVENT0_OUT of instance: enet1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: SRC_EARLY_RESET of instance: src + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO02 + SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register + 0x64 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: I2C1_SCL of instance: i2c1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_COMPARE2 of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG2_PWR of instance: usb + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_REF_CLK_25M of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC1_WP of instance: usdhc1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT00 of instance: sdma + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: SRC_ANY_PU_RESET of instance: src + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: UART1_TX of instance: uart1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO03 + SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register + 0x68 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: I2C1_SDA of instance: i2c1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_COMPARE3 of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG2_OC of instance: usb + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC1_CD_B of instance: usdhc1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_DI0_EXT_CLK of instance: ccm + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: SRC_TESTER_ACK of instance: src ALT7 mode will be automatically active when system reset. The PAD setting will be 100 K pull down and input enable during reset period. Once system reset is completed, the state of GPIO1_IO03 will be output keeper and input enable. + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: UART1_RX of instance: uart1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO04 + SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register + 0x6C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_REF_CLK1 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM3_OUT of instance: pwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG1_PWR of instance: usb + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET2_1588_EVENT0_IN of instance: enet2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_TX of instance: uart5 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO05 + SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register + 0x70 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_REF_CLK2 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM4_OUT of instance: pwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ANATOP_OTG2_ID of instance: anatop + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_FIELD of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET2_1588_EVENT0_OUT of instance: enet2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_RX of instance: uart5 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO06 + SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register + 0x74 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_MDIO of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_MDIO of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG_PWR_WAKE of instance: usb + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_MCLK of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC2_WP of instance: usdhc2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO06 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_WAIT of instance: ccm + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: CCM_REF_EN_B of instance: ccm + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: UART1_CTS_B of instance: uart1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO07 + SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register + 0x78 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_MDC of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_MDC of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG_HOST_MODE of instance: usb + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_PIXCLK of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC2_CD_B of instance: usdhc2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO07 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_STOP of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART1_RTS_B of instance: uart1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO08 + SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register + 0x7C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: PWM1_OUT of instance: pwm1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SPDIF_OUT of instance: spdif + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_VSYNC of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC2_VSELECT of instance: usdhc2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO08 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_PMIC_RDY of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_RTS_B of instance: uart5 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO09 + SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register + 0x80 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: PWM2_OUT of instance: pwm2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: WDOG1_WDOG_ANY of instance: wdog1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SPDIF_IN of instance: spdif + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_HSYNC of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO09 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_CTS_B of instance: uart5 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_TX_DATA + SW_MUX_CTL_PAD_UART1_TX_DATA SW MUX Control Register + 0x84 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART1_TX of instance: uart1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_RDATA02 of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C3_SCL of instance: i2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA02 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_COMPARE1 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO16 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: SPDIF_OUT of instance: spdif + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: UART5_TX of instance: uart5 + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART1_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_RX_DATA + SW_MUX_CTL_PAD_UART1_RX_DATA SW MUX Control Register + 0x88 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART1_RX of instance: uart1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_RDATA03 of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C3_SDA of instance: i2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA03 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CLK of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: SPDIF_IN of instance: spdif + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: UART5_RX of instance: uart5 + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART1_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_CTS_B + SW_MUX_CTL_PAD_UART1_CTS_B SW MUX Control Register + 0x8C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART1_CTS_B of instance: uart1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_RX_CLK of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_WP of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA04 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_1588_EVENT1_IN of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO18 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_WP of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: UART5_CTS_B of instance: uart5 + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART1_CTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_RTS_B + SW_MUX_CTL_PAD_UART1_RTS_B SW MUX Control Register + 0x90 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART1_RTS_B of instance: uart1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_TX_ER of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_CD_B of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA05 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_1588_EVENT1_OUT of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO19 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_CD_B of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: UART5_RTS_B of instance: uart5 + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART1_RTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_TX_DATA + SW_MUX_CTL_PAD_UART2_TX_DATA SW MUX Control Register + 0x94 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART2_TX of instance: uart2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_TDATA02 of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C4_SCL of instance: i2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA06 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE1 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO20 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SS0 of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART2_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_RX_DATA + SW_MUX_CTL_PAD_UART2_RX_DATA SW MUX Control Register + 0x98 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART2_RX of instance: uart2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_TDATA03 of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C4_SDA of instance: i2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA07 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE2 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_DONE of instance: sjc + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SCLK of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART2_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_CTS_B + SW_MUX_CTL_PAD_UART2_CTS_B SW MUX Control Register + 0x9C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART2_CTS_B of instance: uart2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_CRS of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA08 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_COMPARE2 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO22 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_DE_B of instance: sjc + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_MOSI of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART2_CTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_RTS_B + SW_MUX_CTL_PAD_UART2_RTS_B SW MUX Control Register + 0xA0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART2_RTS_B of instance: uart2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_COL of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA09 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_COMPARE3 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO23 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_FAIL of instance: sjc + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_MISO of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART2_RTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_TX_DATA + SW_MUX_CTL_PAD_UART3_TX_DATA SW MUX Control Register + 0xA4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART3_TX of instance: uart3 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_RDATA02 of instance: enet2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA01 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: UART2_CTS_B of instance: uart2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO24 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_JTAG_ACT of instance: sjc ALT7 mode will be automatically active (output SJC.SJC_JTAG_ACT) when system reset. Once system reset is completed, the state of UART3_TX_DATA will be output keeper and input enenable. + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ANATOP_OTG1_ID of instance: anatop + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART3_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_RX_DATA + SW_MUX_CTL_PAD_UART3_RX_DATA SW MUX Control Register + 0xA8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART3_RX of instance: uart3 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_RDATA03 of instance: enet2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA00 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: UART2_RTS_B of instance: uart2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: EPIT1_OUT of instance: epit1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART3_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_CTS_B + SW_MUX_CTL_PAD_UART3_CTS_B SW MUX Control Register + 0xAC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART3_CTS_B of instance: uart3 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_RX_CLK of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA10 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_1588_EVENT1_IN of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO26 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: EPIT2_OUT of instance: epit2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART3_CTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_RTS_B + SW_MUX_CTL_PAD_UART3_RTS_B SW MUX Control Register + 0xB0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART3_RTS_B of instance: uart3 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_TX_ER of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA11 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_1588_EVENT1_OUT of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART3_RTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART4_TX_DATA + SW_MUX_CTL_PAD_UART4_TX_DATA SW MUX Control Register + 0xB4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART4_TX of instance: uart4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_TDATA02 of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C1_SCL of instance: i2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA12 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSU_CSU_ALARM_AUT02 of instance: csu + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO28 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SCLK of instance: ecspi2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART4_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART4_RX_DATA + SW_MUX_CTL_PAD_UART4_RX_DATA SW MUX Control Register + 0xB8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART4_RX of instance: uart4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_TDATA03 of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C1_SDA of instance: i2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA13 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSU_CSU_ALARM_AUT01 of instance: csu + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO29 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SS0 of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCTRL01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART4_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART5_TX_DATA + SW_MUX_CTL_PAD_UART5_TX_DATA SW MUX Control Register + 0xBC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART5_TX of instance: uart5 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_CRS of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C2_SCL of instance: i2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA14 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSU_CSU_ALARM_AUT00 of instance: csu + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO30 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_MOSI of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCTRL02 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART5_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART5_RX_DATA + SW_MUX_CTL_PAD_UART5_RX_DATA SW MUX Control Register + 0xC0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART5_RX of instance: uart5 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_COL of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C2_SDA of instance: i2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA15 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSU_CSU_INT_DEB of instance: csu + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO31 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_MISO of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCTRL03 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART5_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_RX_DATA0 + SW_MUX_CTL_PAD_ENET1_RX_DATA0 SW MUX Control Register + 0xC4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_RDATA00 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART4_RTS_B of instance: uart4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM1_OUT of instance: pwm1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA16 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW00 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_LCTL of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE04 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_RX_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_RX_DATA1 + SW_MUX_CTL_PAD_ENET1_RX_DATA1 SW MUX Control Register + 0xC8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_RDATA01 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART4_CTS_B of instance: uart4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM2_OUT of instance: pwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA17 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL00 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_LCTL of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE05 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_RX_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_RX_EN + SW_MUX_CTL_PAD_ENET1_RX_EN SW MUX Control Register + 0xCC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_RX_EN of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART5_RTS_B of instance: uart5 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA18 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW01 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE06 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_RX_EN + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_TX_DATA0 + SW_MUX_CTL_PAD_ENET1_TX_DATA0 SW MUX Control Register + 0xD0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_TDATA00 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART5_CTS_B of instance: uart5 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA19 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL01 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_VSELECT of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE07 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_TX_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_TX_DATA1 + SW_MUX_CTL_PAD_ENET1_TX_DATA1 SW MUX Control Register + 0xD4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_TDATA01 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART6_CTS_B of instance: uart6 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM5_OUT of instance: pwm5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA20 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_MDIO of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW02 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE08 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_TX_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_TX_EN + SW_MUX_CTL_PAD_ENET1_TX_EN SW MUX Control Register + 0xD8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_TX_EN of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART6_RTS_B of instance: uart6 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM6_OUT of instance: pwm6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA21 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_MDC of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL02 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG2_WDOG_RST_B_DEB of instance: wdog2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE09 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_TX_EN + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_TX_CLK + SW_MUX_CTL_PAD_ENET1_TX_CLK SW MUX Control Register + 0xDC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_TX_CLK of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_CTS_B of instance: uart7 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM7_OUT of instance: pwm7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA22 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_REF_CLK1 of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW03 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_CLK of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDOED of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_TX_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_RX_ER + SW_MUX_CTL_PAD_ENET1_RX_ER SW MUX Control Register + 0xE0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_RX_ER of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_RTS_B of instance: uart7 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM8_OUT of instance: pwm8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA23 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CRE of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL03 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_CAPTURE2 of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDOEZ of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_RX_ER + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_RX_DATA0 + SW_MUX_CTL_PAD_ENET2_RX_DATA0 SW MUX Control Register + 0xE4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_RDATA00 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART6_TX of instance: uart6 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C3_SCL of instance: i2c3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_MDIO of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW04 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG1_PWR of instance: usb + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO08 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_RX_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_RX_DATA1 + SW_MUX_CTL_PAD_ENET2_RX_DATA1 SW MUX Control Register + 0xE8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_RDATA01 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART6_RX of instance: uart6 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C3_SDA of instance: i2c3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_MDC of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL04 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG1_OC of instance: usb + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO09 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_RX_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_RX_EN + SW_MUX_CTL_PAD_ENET2_RX_EN SW MUX Control Register + 0xEC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_RX_EN of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_TX of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C4_SCL of instance: i2c4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR26 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW05 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET1_REF_CLK_25M of instance: enet1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO10 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_RX_EN + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_TX_DATA0 + SW_MUX_CTL_PAD_ENET2_TX_DATA0 SW MUX Control Register + 0xF0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_TDATA00 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_RX of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C4_SDA of instance: i2c4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_EB_B02 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL05 of instance: kpp + 0x6 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO11 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_TX_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_TX_DATA1 + SW_MUX_CTL_PAD_ENET2_TX_DATA1 SW MUX Control Register + 0xF4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_TDATA01 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_TX of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_SCLK of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_EB_B03 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW06 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG2_PWR of instance: usb + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO12 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_TX_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_TX_EN + SW_MUX_CTL_PAD_ENET2_TX_EN SW MUX Control Register + 0xF8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_TX_EN of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_RX of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_MOSI of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ACLK_FREERUN of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL06 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG2_OC of instance: usb + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO13 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_TX_EN + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_TX_CLK + SW_MUX_CTL_PAD_ENET2_TX_CLK SW MUX Control Register + 0xFC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_TX_CLK of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_CTS_B of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_MISO of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_REF_CLK2 of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO14 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW07 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ANATOP_OTG2_ID of instance: anatop + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO14 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_TX_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_RX_ER + SW_MUX_CTL_PAD_ENET2_RX_ER SW MUX Control Register + 0x100 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_RX_ER of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_RTS_B of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_SS0 of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR25 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO15 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL07 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_ANY of instance: wdog1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO15 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_RX_ER + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_CLK + SW_MUX_CTL_PAD_LCD_CLK SW MUX Control Register + 0x104 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_CLK of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_WR_RWN of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: UART4_TX of instance: uart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_MCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CS2_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO00 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCLK of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_ENABLE + SW_MUX_CTL_PAD_LCD_ENABLE SW MUX Control Register + 0x108 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_ENABLE of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_RD_E of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: UART4_RX of instance: uart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CS3_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_RDY of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDLE of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_ENABLE + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_HSYNC + SW_MUX_CTL_PAD_LCD_HSYNC SW MUX Control Register + 0x10C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_HSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_RS of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: UART4_CTS_B of instance: uart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG3_WDOG_RST_B_DEB of instance: wdog3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO02 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SS1 of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDOE of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_HSYNC + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_VSYNC + SW_MUX_CTL_PAD_LCD_VSYNC SW MUX Control Register + 0x110 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_VSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_BUSY of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: UART4_RTS_B of instance: uart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG2_WDOG_B of instance: wdog2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SS2 of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_VSYNC + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_RESET + SW_MUX_CTL_PAD_LCD_RESET SW MUX Control Register + 0x114 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_RESET of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_CS of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CA7_MX6ULL_EVENTI of instance: ca7_mx6ull + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG1_WDOG_ANY of instance: wdog1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO04 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SS3 of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_GDOE of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_RESET + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA00 + SW_MUX_CTL_PAD_LCD_DATA00 SW MUX Control Register + 0x118 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA00 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM1_OUT of instance: pwm1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_1588_EVENT2_IN of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: I2C3_SDA of instance: i2c3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO05 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_MCLK of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA01 + SW_MUX_CTL_PAD_LCD_DATA01 SW MUX Control Register + 0x11C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA01 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM2_OUT of instance: pwm2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_1588_EVENT2_OUT of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: I2C3_SCL of instance: i2c3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO06 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_TX_SYNC of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA02 + SW_MUX_CTL_PAD_LCD_DATA02 SW MUX Control Register + 0x120 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA02 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM3_OUT of instance: pwm3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_1588_EVENT3_IN of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: I2C4_SDA of instance: i2c4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_TX_BCLK of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO02 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA03 + SW_MUX_CTL_PAD_LCD_DATA03 SW MUX Control Register + 0x124 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA03 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM4_OUT of instance: pwm4 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_1588_EVENT3_OUT of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: I2C4_SCL of instance: i2c4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO08 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_RX_DATA of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO03 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA04 + SW_MUX_CTL_PAD_LCD_DATA04 SW MUX Control Register + 0x128 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA04 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_CTS_B of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_1588_EVENT2_IN of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: SPDIF_SR_CLK of instance: spdif + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG04 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_TX_DATA of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO04 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA05 + SW_MUX_CTL_PAD_LCD_DATA05 SW MUX Control Register + 0x12C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA05 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_RTS_B of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_1588_EVENT2_OUT of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: SPDIF_OUT of instance: spdif + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG05 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI1_SS1 of instance: ecspi1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO05 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA06 + SW_MUX_CTL_PAD_LCD_DATA06 SW MUX Control Register + 0x130 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA06 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_CTS_B of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_1588_EVENT3_IN of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: SPDIF_LOCK of instance: spdif + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG06 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI1_SS2 of instance: ecspi1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO06 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA07 + SW_MUX_CTL_PAD_LCD_DATA07 SW MUX Control Register + 0x134 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA07 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_RTS_B of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_1588_EVENT3_OUT of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: SPDIF_EXT_CLK of instance: spdif + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO12 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG07 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI1_SS3 of instance: ecspi1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO07 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA08 + SW_MUX_CTL_PAD_LCD_DATA08 SW MUX Control Register + 0x138 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA08 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SPDIF_IN of instance: spdif + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA16 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA00 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO13 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG08 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRIRQ of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA09 + SW_MUX_CTL_PAD_LCD_DATA09 SW MUX Control Register + 0x13C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA09 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_MCLK of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA17 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA01 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO14 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG09 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRWAKE of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA10 + SW_MUX_CTL_PAD_LCD_DATA10 SW MUX Control Register + 0x140 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA10 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_RX_SYNC of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA18 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA02 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO15 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG10 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCOM of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA11 + SW_MUX_CTL_PAD_LCD_DATA11 SW MUX Control Register + 0x144 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA11 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_RX_BCLK of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA19 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA03 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO16 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG11 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRSTAT of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA12 + SW_MUX_CTL_PAD_LCD_DATA12 SW MUX Control Register + 0x148 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA12 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_TX_SYNC of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA20 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA04 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO17 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG12 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI1_RDY of instance: ecspi1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCTRL00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA13 + SW_MUX_CTL_PAD_LCD_DATA13 SW MUX Control Register + 0x14C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA13 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_TX_BCLK of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA21 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA05 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO18 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG13 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_BDR00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA14 + SW_MUX_CTL_PAD_LCD_DATA14 SW MUX Control Register + 0x150 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA14 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_RX_DATA of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA22 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA06 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO19 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG14 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA4 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDSHR of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA15 + SW_MUX_CTL_PAD_LCD_DATA15 SW MUX Control Register + 0x154 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA15 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_TX_DATA of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA23 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA07 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO20 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG15 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA5 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_GDRL of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA16 + SW_MUX_CTL_PAD_LCD_DATA16 SW MUX Control Register + 0x158 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA16 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_TX of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA01 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA08 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG24 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA6 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_GDCLK of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA16 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA17 + SW_MUX_CTL_PAD_LCD_DATA17 SW MUX Control Register + 0x15C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA17 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_RX of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA00 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA09 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO22 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG25 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA7 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_GDSP of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA17 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA18 + SW_MUX_CTL_PAD_LCD_DATA18 SW MUX Control Register + 0x160 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA18 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM5_OUT of instance: pwm5 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CA7_MX6ULL_EVENTO of instance: ca7_mx6ull + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA10 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA10 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO23 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG26 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_CMD of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_BDR01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA18 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA19 + SW_MUX_CTL_PAD_LCD_DATA19 SW MUX Control Register + 0x164 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA19 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM6_OUT of instance: pwm6 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: WDOG1_WDOG_ANY of instance: wdog1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA11 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA11 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO24 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG27 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_CLK of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_VCOM00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA19 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA20 + SW_MUX_CTL_PAD_LCD_DATA20 SW MUX Control Register + 0x168 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA20 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_TX of instance: uart8 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ECSPI1_SCLK of instance: ecspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA12 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA12 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO25 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG28 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA0 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_VCOM01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA20 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA21 + SW_MUX_CTL_PAD_LCD_DATA21 SW MUX Control Register + 0x16C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA21 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_RX of instance: uart8 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ECSPI1_SS0 of instance: ecspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA13 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA13 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO26 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG29 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA1 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA21 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA22 + SW_MUX_CTL_PAD_LCD_DATA22 SW MUX Control Register + 0x170 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA22 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ECSPI1_MOSI of instance: ecspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA14 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA14 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG30 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA2 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE02 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA22 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA23 + SW_MUX_CTL_PAD_LCD_DATA23 SW MUX Control Register + 0x174 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA23 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ECSPI1_MISO of instance: ecspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA15 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA15 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO28 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG31 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA3 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE03 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA23 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_RE_B + SW_MUX_CTL_PAD_NAND_RE_B SW MUX Control Register + 0x178 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_RE_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CLK of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_SCLK of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW00 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_EB_B00 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SS2 of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_RE_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_WE_B + SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control Register + 0x17C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_WE_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CMD of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_SS0_B of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL00 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_EB_B01 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO01 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SS3 of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_WE_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA00 + SW_MUX_CTL_PAD_NAND_DATA00 SW MUX Control Register + 0x180 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA00 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA0 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_SS1_B of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW01 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD08 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO02 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI4_RDY of instance: ecspi4 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA01 + SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control Register + 0x184 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA01 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA1 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DQS of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL01 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD09 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO03 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI4_SS1 of instance: ecspi4 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA02 + SW_MUX_CTL_PAD_NAND_DATA02 SW MUX Control Register + 0x188 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA02 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA2 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DATA00 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW02 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD10 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI4_SS2 of instance: ecspi4 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA03 + SW_MUX_CTL_PAD_NAND_DATA03 SW MUX Control Register + 0x18C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA03 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA3 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DATA01 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL02 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD11 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI4_SS3 of instance: ecspi4 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA04 + SW_MUX_CTL_PAD_NAND_DATA04 SW MUX Control Register + 0x190 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA04 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA4 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DATA02 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_SCLK of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD12 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART2_TX of instance: uart2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA05 + SW_MUX_CTL_PAD_NAND_DATA05 SW MUX Control Register + 0x194 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA05 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA5 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DATA03 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_MOSI of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD13 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART2_RX of instance: uart2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA06 + SW_MUX_CTL_PAD_NAND_DATA06 SW MUX Control Register + 0x198 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA06 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA6 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_MISO of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD14 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART2_CTS_B of instance: uart2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA07 + SW_MUX_CTL_PAD_NAND_DATA07 SW MUX Control Register + 0x19C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA07 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA7 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_SS1_B of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_SS0 of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD15 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART2_RTS_B of instance: uart2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_ALE + SW_MUX_CTL_PAD_NAND_ALE SW MUX Control Register + 0x1A0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_ALE of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DQS of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: PWM3_OUT of instance: pwm3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR17 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO10 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SS1 of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_ALE + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_WP_B + SW_MUX_CTL_PAD_NAND_WP_B SW MUX Control Register + 0x1A4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_WP_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_SCLK of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: PWM4_OUT of instance: pwm4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_BCLK of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO11 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_RDY of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_WP_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_READY_B + SW_MUX_CTL_PAD_NAND_READY_B SW MUX Control Register + 0x1A8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_READY_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_DATA4 of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DATA00 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI3_SS0 of instance: ecspi3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CS1_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO12 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART3_TX of instance: uart3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_READY_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CE0_B + SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control Register + 0x1AC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_CE0_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_DATA5 of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DATA01 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI3_SCLK of instance: ecspi3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DTACK_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO13 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART3_RX of instance: uart3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_CE0_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CE1_B + SW_MUX_CTL_PAD_NAND_CE1_B SW MUX Control Register + 0x1B0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_CE1_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_DATA6 of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DATA02 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI3_MOSI of instance: ecspi3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR18 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO14 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART3_CTS_B of instance: uart3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_CE1_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CLE + SW_MUX_CTL_PAD_NAND_CLE SW MUX Control Register + 0x1B4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_CLE of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_DATA7 of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DATA03 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI3_MISO of instance: ecspi3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR16 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO15 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART3_RTS_B of instance: uart3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_CLE + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DQS + SW_MUX_CTL_PAD_NAND_DQS SW MUX Control Register + 0x1B8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DQS of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: CSI_FIELD of instance: csi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_SS0_B of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: PWM5_OUT of instance: pwm5 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_WAIT of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO16 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT01 of instance: sdma + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SPDIF_EXT_CLK of instance: spdif + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DQS + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_CMD + SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register + 0x1BC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CMD of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR19 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO16 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT00 of instance: sdma + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG1_PWR of instance: usb + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_CMD + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_CLK + SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register + 0x1C0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CLK of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR20 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO17 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG1_OC of instance: usb + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA0 + SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register + 0x1C4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE3 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR21 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ANATOP_OTG1_ID of instance: anatop + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA1 + SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register + 0x1C8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CLK of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR22 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG2_PWR of instance: usb + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA2 + SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register + 0x1CC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR23 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG2_OC of instance: usb + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_DATA2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA3 + SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register + 0x1D0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR24 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ANATOP_OTG2_ID of instance: anatop + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_DATA3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_MCLK + SW_MUX_CTL_PAD_CSI_MCLK SW MUX Control Register + 0x1D4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_MCLK of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CD_B of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: RAWNAND_CE2_B of instance: rawnand + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: I2C1_SDA of instance: i2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CS0_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO17 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART6_TX of instance: uart6 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX3_RX2 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_MCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_PIXCLK + SW_MUX_CTL_PAD_CSI_PIXCLK SW MUX Control Register + 0x1D8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_PIXCLK of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_WP of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: RAWNAND_CE3_B of instance: rawnand + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: I2C1_SCL of instance: i2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_OE of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_HP_VIO_5 of instance: snvs_hp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART6_RX of instance: uart6 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX2_RX3 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_PIXCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_VSYNC + SW_MUX_CTL_PAD_CSI_VSYNC SW MUX Control Register + 0x1DC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_VSYNC of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CLK of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C2_SDA of instance: i2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_RW of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: PWM7_OUT of instance: pwm7 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART6_RTS_B of instance: uart6 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX4_RX1 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_VSYNC + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_HSYNC + SW_MUX_CTL_PAD_CSI_HSYNC SW MUX Control Register + 0x1E0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_HSYNC of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CMD of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C2_SCL of instance: i2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_LBA_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO20 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: PWM8_OUT of instance: pwm8 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART6_CTS_B of instance: uart6 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX1 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_HSYNC + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA00 + SW_MUX_CTL_PAD_CSI_DATA00 SW MUX Control Register + 0x1E4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA02 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA0 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI2_SCLK of instance: ecspi2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD00 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO21 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_INT_BOOT of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_TX of instance: uart5 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX_HF_CLK of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA01 + SW_MUX_CTL_PAD_CSI_DATA01 SW MUX Control Register + 0x1E8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA03 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA1 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI2_SS0 of instance: ecspi2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD01 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO22 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_MCLK of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_RX of instance: uart5 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_RX_HF_CLK of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA02 + SW_MUX_CTL_PAD_CSI_DATA02 SW MUX Control Register + 0x1EC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA04 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA2 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI2_MOSI of instance: ecspi2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD02 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO23 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_RX_SYNC of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_RTS_B of instance: uart5 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_RX_FS of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA03 + SW_MUX_CTL_PAD_CSI_DATA03 SW MUX Control Register + 0x1F0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA05 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA3 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI2_MISO of instance: ecspi2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD03 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO24 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_RX_BCLK of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_CTS_B of instance: uart5 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_RX_CLK of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA04 + SW_MUX_CTL_PAD_CSI_DATA04 SW MUX Control Register + 0x1F4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA06 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA4 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI1_SCLK of instance: ecspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD04 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO25 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_TX_SYNC of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_WP of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX_FS of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA05 + SW_MUX_CTL_PAD_CSI_DATA05 SW MUX Control Register + 0x1F8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA07 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA5 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI1_SS0 of instance: ecspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD05 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO26 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_TX_BCLK of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_CD_B of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX_CLK of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA06 + SW_MUX_CTL_PAD_CSI_DATA06 SW MUX Control Register + 0x1FC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA08 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA6 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI1_MOSI of instance: ecspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD06 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO27 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_RX_DATA of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX5_RX0 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA07 + SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register + 0x200 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA09 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA7 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI1_MISO of instance: ecspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD07 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO28 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_TX_DATA of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX0 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA07 + 0x1 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR00 + SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register + 0x204 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR01 + SW_PAD_CTL_PAD_DRAM_ADDR01 SW PAD Control Register + 0x208 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR02 + SW_PAD_CTL_PAD_DRAM_ADDR02 SW PAD Control Register + 0x20C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR03 + SW_PAD_CTL_PAD_DRAM_ADDR03 SW PAD Control Register + 0x210 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR04 + SW_PAD_CTL_PAD_DRAM_ADDR04 SW PAD Control Register + 0x214 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR05 + SW_PAD_CTL_PAD_DRAM_ADDR05 SW PAD Control Register + 0x218 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR06 + SW_PAD_CTL_PAD_DRAM_ADDR06 SW PAD Control Register + 0x21C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR07 + SW_PAD_CTL_PAD_DRAM_ADDR07 SW PAD Control Register + 0x220 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR08 + SW_PAD_CTL_PAD_DRAM_ADDR08 SW PAD Control Register + 0x224 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR09 + SW_PAD_CTL_PAD_DRAM_ADDR09 SW PAD Control Register + 0x228 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR10 + SW_PAD_CTL_PAD_DRAM_ADDR10 SW PAD Control Register + 0x22C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR11 + SW_PAD_CTL_PAD_DRAM_ADDR11 SW PAD Control Register + 0x230 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR12 + SW_PAD_CTL_PAD_DRAM_ADDR12 SW PAD Control Register + 0x234 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR13 + SW_PAD_CTL_PAD_DRAM_ADDR13 SW PAD Control Register + 0x238 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR14 + SW_PAD_CTL_PAD_DRAM_ADDR14 SW PAD Control Register + 0x23C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR15 + SW_PAD_CTL_PAD_DRAM_ADDR15 SW PAD Control Register + 0x240 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_DQM0 + SW_PAD_CTL_PAD_DRAM_DQM0 SW PAD Control Register + 0x244 + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_DQM1 + SW_PAD_CTL_PAD_DRAM_DQM1 SW PAD Control Register + 0x248 + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_RAS_B + SW_PAD_CTL_PAD_DRAM_RAS_B SW PAD Control Register + 0x24C + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_CAS_B + SW_PAD_CTL_PAD_DRAM_CAS_B SW PAD Control Register + 0x250 + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_CS0_B + SW_PAD_CTL_PAD_DRAM_CS0_B SW PAD Control Register + 0x254 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_CS1_B + SW_PAD_CTL_PAD_DRAM_CS1_B SW PAD Control Register + 0x258 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDWE_B + SW_PAD_CTL_PAD_DRAM_SDWE_B SW PAD Control Register + 0x25C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ODT0 + SW_PAD_CTL_PAD_DRAM_ODT0 SW PAD Control Register + 0x260 + 32 + read-write + 0x3030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ODT1 + SW_PAD_CTL_PAD_DRAM_ODT1 SW PAD Control Register + 0x264 + 32 + read-write + 0x3030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDBA0 + SW_PAD_CTL_PAD_DRAM_SDBA0 SW PAD Control Register + 0x268 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDBA1 + SW_PAD_CTL_PAD_DRAM_SDBA1 SW PAD Control Register + 0x26C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDBA2 + SW_PAD_CTL_PAD_DRAM_SDBA2 SW PAD Control Register + 0x270 + 32 + read-write + 0xB000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDCKE0 + SW_PAD_CTL_PAD_DRAM_SDCKE0 SW PAD Control Register + 0x274 + 32 + read-write + 0x3000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDCKE1 + SW_PAD_CTL_PAD_DRAM_SDCKE1 SW PAD Control Register + 0x278 + 32 + read-write + 0x3000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDCLK0_P + SW_PAD_CTL_PAD_DRAM_SDCLK0_P SW PAD Control Register + 0x27C + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + DO_TRIM_PADN + do_trim_padn Field + 0x18 + 2 + read-write + + + DO_TRIM_PADN_0_min_delay + min delay + 0 + + + DO_TRIM_PADN_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_PADN_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_PADN_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDQS0_P + SW_PAD_CTL_PAD_DRAM_SDQS0_P SW PAD Control Register + 0x280 + 32 + read-write + 0x2030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-only + + + ODT + off + 0 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-only + + + HYS + Hysteresis Disabled + 0 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-only + + + DDR_INPUT + CMOS input type + 0 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + DO_TRIM_PADN + do_trim_padn Field + 0x18 + 2 + read-write + + + DO_TRIM_PADN_0_min_delay + min delay + 0 + + + DO_TRIM_PADN_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_PADN_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_PADN_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDQS1_P + SW_PAD_CTL_PAD_DRAM_SDQS1_P SW PAD Control Register + 0x284 + 32 + read-write + 0x2030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-only + + + ODT + off + 0 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-only + + + HYS + Hysteresis Disabled + 0 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-only + + + DDR_INPUT + CMOS input type + 0 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + DO_TRIM_PADN + do_trim_padn Field + 0x18 + 2 + read-write + + + DO_TRIM_PADN_0_min_delay + min delay + 0 + + + DO_TRIM_PADN_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_PADN_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_PADN_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_RESET + SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register + 0x288 + 32 + read-write + 0x83030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-write + + + DDR_SEL_2_LPDDR2_mode + LPDDR2 mode + 0x2 + + + DDR_SEL_3_DDR3_mode + DDR3 mode + 0x3 + + + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_JTAG_MOD + SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register + 0x2D0 + 32 + read-write + 0xB0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TMS + SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register + 0x2D4 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TDO + SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register + 0x2D8 + 32 + read-write + 0x90B1 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TDI + SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register + 0x2DC + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TCK + SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register + 0x2E0 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TRST_B + SW_PAD_CTL_PAD_JTAG_TRST_B SW PAD Control Register + 0x2E4 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO00 + SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register + 0x2E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO01 + SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control Register + 0x2EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO02 + SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control Register + 0x2F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO03 + SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control Register + 0x2F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO04 + SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control Register + 0x2F8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO05 + SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register + 0x2FC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO06 + SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register + 0x300 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO07 + SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register + 0x304 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO08 + SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control Register + 0x308 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO09 + SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control Register + 0x30C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_TX_DATA + SW_PAD_CTL_PAD_UART1_TX_DATA SW PAD Control Register + 0x310 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_RX_DATA + SW_PAD_CTL_PAD_UART1_RX_DATA SW PAD Control Register + 0x314 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_CTS_B + SW_PAD_CTL_PAD_UART1_CTS_B SW PAD Control Register + 0x318 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_RTS_B + SW_PAD_CTL_PAD_UART1_RTS_B SW PAD Control Register + 0x31C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_TX_DATA + SW_PAD_CTL_PAD_UART2_TX_DATA SW PAD Control Register + 0x320 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_RX_DATA + SW_PAD_CTL_PAD_UART2_RX_DATA SW PAD Control Register + 0x324 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_CTS_B + SW_PAD_CTL_PAD_UART2_CTS_B SW PAD Control Register + 0x328 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_RTS_B + SW_PAD_CTL_PAD_UART2_RTS_B SW PAD Control Register + 0x32C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART3_TX_DATA + SW_PAD_CTL_PAD_UART3_TX_DATA SW PAD Control Register + 0x330 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART3_RX_DATA + SW_PAD_CTL_PAD_UART3_RX_DATA SW PAD Control Register + 0x334 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART3_CTS_B + SW_PAD_CTL_PAD_UART3_CTS_B SW PAD Control Register + 0x338 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART3_RTS_B + SW_PAD_CTL_PAD_UART3_RTS_B SW PAD Control Register + 0x33C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART4_TX_DATA + SW_PAD_CTL_PAD_UART4_TX_DATA SW PAD Control Register + 0x340 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART4_RX_DATA + SW_PAD_CTL_PAD_UART4_RX_DATA SW PAD Control Register + 0x344 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART5_TX_DATA + SW_PAD_CTL_PAD_UART5_TX_DATA SW PAD Control Register + 0x348 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART5_RX_DATA + SW_PAD_CTL_PAD_UART5_RX_DATA SW PAD Control Register + 0x34C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_RX_DATA0 + SW_PAD_CTL_PAD_ENET1_RX_DATA0 SW PAD Control Register + 0x350 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_RX_DATA1 + SW_PAD_CTL_PAD_ENET1_RX_DATA1 SW PAD Control Register + 0x354 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_RX_EN + SW_PAD_CTL_PAD_ENET1_RX_EN SW PAD Control Register + 0x358 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_TX_DATA0 + SW_PAD_CTL_PAD_ENET1_TX_DATA0 SW PAD Control Register + 0x35C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_TX_DATA1 + SW_PAD_CTL_PAD_ENET1_TX_DATA1 SW PAD Control Register + 0x360 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_TX_EN + SW_PAD_CTL_PAD_ENET1_TX_EN SW PAD Control Register + 0x364 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_TX_CLK + SW_PAD_CTL_PAD_ENET1_TX_CLK SW PAD Control Register + 0x368 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_RX_ER + SW_PAD_CTL_PAD_ENET1_RX_ER SW PAD Control Register + 0x36C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_RX_DATA0 + SW_PAD_CTL_PAD_ENET2_RX_DATA0 SW PAD Control Register + 0x370 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_RX_DATA1 + SW_PAD_CTL_PAD_ENET2_RX_DATA1 SW PAD Control Register + 0x374 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_RX_EN + SW_PAD_CTL_PAD_ENET2_RX_EN SW PAD Control Register + 0x378 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_TX_DATA0 + SW_PAD_CTL_PAD_ENET2_TX_DATA0 SW PAD Control Register + 0x37C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_TX_DATA1 + SW_PAD_CTL_PAD_ENET2_TX_DATA1 SW PAD Control Register + 0x380 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_TX_EN + SW_PAD_CTL_PAD_ENET2_TX_EN SW PAD Control Register + 0x384 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_TX_CLK + SW_PAD_CTL_PAD_ENET2_TX_CLK SW PAD Control Register + 0x388 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_RX_ER + SW_PAD_CTL_PAD_ENET2_RX_ER SW PAD Control Register + 0x38C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_CLK + SW_PAD_CTL_PAD_LCD_CLK SW PAD Control Register + 0x390 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_ENABLE + SW_PAD_CTL_PAD_LCD_ENABLE SW PAD Control Register + 0x394 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_HSYNC + SW_PAD_CTL_PAD_LCD_HSYNC SW PAD Control Register + 0x398 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_VSYNC + SW_PAD_CTL_PAD_LCD_VSYNC SW PAD Control Register + 0x39C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_RESET + SW_PAD_CTL_PAD_LCD_RESET SW PAD Control Register + 0x3A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA00 + SW_PAD_CTL_PAD_LCD_DATA00 SW PAD Control Register + 0x3A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA01 + SW_PAD_CTL_PAD_LCD_DATA01 SW PAD Control Register + 0x3A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA02 + SW_PAD_CTL_PAD_LCD_DATA02 SW PAD Control Register + 0x3AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA03 + SW_PAD_CTL_PAD_LCD_DATA03 SW PAD Control Register + 0x3B0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA04 + SW_PAD_CTL_PAD_LCD_DATA04 SW PAD Control Register + 0x3B4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA05 + SW_PAD_CTL_PAD_LCD_DATA05 SW PAD Control Register + 0x3B8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA06 + SW_PAD_CTL_PAD_LCD_DATA06 SW PAD Control Register + 0x3BC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA07 + SW_PAD_CTL_PAD_LCD_DATA07 SW PAD Control Register + 0x3C0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA08 + SW_PAD_CTL_PAD_LCD_DATA08 SW PAD Control Register + 0x3C4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA09 + SW_PAD_CTL_PAD_LCD_DATA09 SW PAD Control Register + 0x3C8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA10 + SW_PAD_CTL_PAD_LCD_DATA10 SW PAD Control Register + 0x3CC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA11 + SW_PAD_CTL_PAD_LCD_DATA11 SW PAD Control Register + 0x3D0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA12 + SW_PAD_CTL_PAD_LCD_DATA12 SW PAD Control Register + 0x3D4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA13 + SW_PAD_CTL_PAD_LCD_DATA13 SW PAD Control Register + 0x3D8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA14 + SW_PAD_CTL_PAD_LCD_DATA14 SW PAD Control Register + 0x3DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA15 + SW_PAD_CTL_PAD_LCD_DATA15 SW PAD Control Register + 0x3E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA16 + SW_PAD_CTL_PAD_LCD_DATA16 SW PAD Control Register + 0x3E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA17 + SW_PAD_CTL_PAD_LCD_DATA17 SW PAD Control Register + 0x3E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA18 + SW_PAD_CTL_PAD_LCD_DATA18 SW PAD Control Register + 0x3EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA19 + SW_PAD_CTL_PAD_LCD_DATA19 SW PAD Control Register + 0x3F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA20 + SW_PAD_CTL_PAD_LCD_DATA20 SW PAD Control Register + 0x3F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA21 + SW_PAD_CTL_PAD_LCD_DATA21 SW PAD Control Register + 0x3F8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA22 + SW_PAD_CTL_PAD_LCD_DATA22 SW PAD Control Register + 0x3FC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA23 + SW_PAD_CTL_PAD_LCD_DATA23 SW PAD Control Register + 0x400 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_RE_B + SW_PAD_CTL_PAD_NAND_RE_B SW PAD Control Register + 0x404 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_WE_B + SW_PAD_CTL_PAD_NAND_WE_B SW PAD Control Register + 0x408 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA00 + SW_PAD_CTL_PAD_NAND_DATA00 SW PAD Control Register + 0x40C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA01 + SW_PAD_CTL_PAD_NAND_DATA01 SW PAD Control Register + 0x410 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA02 + SW_PAD_CTL_PAD_NAND_DATA02 SW PAD Control Register + 0x414 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA03 + SW_PAD_CTL_PAD_NAND_DATA03 SW PAD Control Register + 0x418 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA04 + SW_PAD_CTL_PAD_NAND_DATA04 SW PAD Control Register + 0x41C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA05 + SW_PAD_CTL_PAD_NAND_DATA05 SW PAD Control Register + 0x420 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA06 + SW_PAD_CTL_PAD_NAND_DATA06 SW PAD Control Register + 0x424 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA07 + SW_PAD_CTL_PAD_NAND_DATA07 SW PAD Control Register + 0x428 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_ALE + SW_PAD_CTL_PAD_NAND_ALE SW PAD Control Register + 0x42C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_WP_B + SW_PAD_CTL_PAD_NAND_WP_B SW PAD Control Register + 0x430 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_READY_B + SW_PAD_CTL_PAD_NAND_READY_B SW PAD Control Register + 0x434 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CE0_B + SW_PAD_CTL_PAD_NAND_CE0_B SW PAD Control Register + 0x438 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CE1_B + SW_PAD_CTL_PAD_NAND_CE1_B SW PAD Control Register + 0x43C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CLE + SW_PAD_CTL_PAD_NAND_CLE SW PAD Control Register + 0x440 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DQS + SW_PAD_CTL_PAD_NAND_DQS SW PAD Control Register + 0x444 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_CMD + SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register + 0x448 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_CLK + SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register + 0x44C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA0 + SW_PAD_CTL_PAD_SD1_DATA0 SW PAD Control Register + 0x450 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA1 + SW_PAD_CTL_PAD_SD1_DATA1 SW PAD Control Register + 0x454 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA2 + SW_PAD_CTL_PAD_SD1_DATA2 SW PAD Control Register + 0x458 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA3 + SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control Register + 0x45C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_MCLK + SW_PAD_CTL_PAD_CSI_MCLK SW PAD Control Register + 0x460 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_PIXCLK + SW_PAD_CTL_PAD_CSI_PIXCLK SW PAD Control Register + 0x464 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_VSYNC + SW_PAD_CTL_PAD_CSI_VSYNC SW PAD Control Register + 0x468 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_HSYNC + SW_PAD_CTL_PAD_CSI_HSYNC SW PAD Control Register + 0x46C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA00 + SW_PAD_CTL_PAD_CSI_DATA00 SW PAD Control Register + 0x470 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA01 + SW_PAD_CTL_PAD_CSI_DATA01 SW PAD Control Register + 0x474 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA02 + SW_PAD_CTL_PAD_CSI_DATA02 SW PAD Control Register + 0x478 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA03 + SW_PAD_CTL_PAD_CSI_DATA03 SW PAD Control Register + 0x47C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA04 + SW_PAD_CTL_PAD_CSI_DATA04 SW PAD Control Register + 0x480 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA05 + SW_PAD_CTL_PAD_CSI_DATA05 SW PAD Control Register + 0x484 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA06 + SW_PAD_CTL_PAD_CSI_DATA06 SW PAD Control Register + 0x488 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA07 + SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register + 0x48C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_GRP_ADDDS + SW_PAD_CTL_GRP_ADDDS SW GRP Register + 0x490 + 32 + read-write + 0x30 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + + + SW_PAD_CTL_GRP_DDRMODE_CTL + SW_PAD_CTL_GRP_DDRMODE_CTL SW GRP Register + 0x494 + 32 + read-write + 0 + 0xFFFFFFFF + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + + + SW_PAD_CTL_GRP_B0DS + SW_PAD_CTL_GRP_B0DS SW GRP Register + 0x498 + 32 + read-write + 0x30 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + + + SW_PAD_CTL_GRP_DDRPK + SW_PAD_CTL_GRP_DDRPK SW GRP Register + 0x49C + 32 + read-write + 0x2000 + 0xFFFFFFFF + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + + + SW_PAD_CTL_GRP_CTLDS + SW_PAD_CTL_GRP_CTLDS SW GRP Register + 0x4A0 + 32 + read-write + 0x30 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + + + SW_PAD_CTL_GRP_B1DS + SW_PAD_CTL_GRP_B1DS SW GRP Register + 0x4A4 + 32 + read-write + 0x30 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + + + SW_PAD_CTL_GRP_DDRHYS + SW_PAD_CTL_GRP_DDRHYS SW GRP Register + 0x4A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_GRP_DDRPKE + SW_PAD_CTL_GRP_DDRPKE SW GRP Register + 0x4AC + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + + + SW_PAD_CTL_GRP_DDRMODE + SW_PAD_CTL_GRP_DDRMODE SW GRP Register + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + + + SW_PAD_CTL_GRP_DDR_TYPE + SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register + 0x4B4 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-write + + + DDR_SEL_2_LPDDR2_mode + LPDDR2 mode + 0x2 + + + DDR_SEL_3_DDR3_mode + DDR3 mode + 0x3 + + + + + + + ANATOP_USB_OTG_ID_SELECT_INPUT + USB_OTG1_ID_SELECT_INPUT DAISY Register + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO00_ALT2 + Selecting Pad: GPIO1_IO00 for Mode: ALT2 + 0 + + + UART3_TX_DATA_ALT8 + Selecting Pad: UART3_TX_DATA for Mode: ALT8 + 0x1 + + + SD1_DATA0_ALT8 + Selecting Pad: SD1_DATA0 for Mode: ALT8 + 0x2 + + + + + + + USB_OTG2_ID_SELECT_INPUT + USB_OTG2_ID_SELECT_INPUT DAISY Register + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO05_ALT2 + Selecting Pad: GPIO1_IO05 for Mode: ALT2 + 0 + + + ENET2_TX_CLK_ALT8 + Selecting Pad: ENET2_TX_CLK for Mode: ALT8 + 0x1 + + + SD1_DATA3_ALT8 + Selecting Pad: SD1_DATA3 for Mode: ALT8 + 0x2 + + + + + + + CCM_PMIC_READY_SELECT_INPUT + CCM_PMIC_READY_SELECT_INPUT DAISY Register + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_MOD_ALT4 + Selecting Pad: JTAG_MOD for Mode: ALT4 + 0 + + + GPIO1_IO08_ALT6 + Selecting Pad: GPIO1_IO08 for Mode: ALT6 + 0x1 + + + + + + + CSI_DATA02_SELECT_INPUT + CSI_DATA02_SELECT_INPUT DAISY Register + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA00_ALT0 + Selecting Pad: CSI_DATA00 for Mode: ALT0 + 0 + + + UART1_TX_DATA_ALT3 + Selecting Pad: UART1_TX_DATA for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA03_SELECT_INPUT + CSI_DATA03_SELECT_INPUT DAISY Register + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA01_ALT0 + Selecting Pad: CSI_DATA01 for Mode: ALT0 + 0 + + + UART1_RX_DATA_ALT3 + Selecting Pad: UART1_RX_DATA for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA05_SELECT_INPUT + CSI_DATA05_SELECT_INPUT DAISY Register + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA03_ALT0 + Selecting Pad: CSI_DATA03 for Mode: ALT0 + 0 + + + UART1_RTS_B_ALT3 + Selecting Pad: UART1_RTS_B for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA00_SELECT_INPUT + CSI_DATA00_SELECT_INPUT DAISY Register + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART3_RX_DATA_ALT3 + Selecting Pad: UART3_RX_DATA for Mode: ALT3 + 0 + + + LCD_DATA17_ALT3 + Selecting Pad: LCD_DATA17 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA01_SELECT_INPUT + CSI_DATA01_SELECT_INPUT DAISY Register + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART3_TX_DATA_ALT3 + Selecting Pad: UART3_TX_DATA for Mode: ALT3 + 0 + + + LCD_DATA16_ALT3 + Selecting Pad: LCD_DATA16 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA04_SELECT_INPUT + CSI_DATA04_SELECT_INPUT DAISY Register + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART1_CTS_B_ALT3 + Selecting Pad: UART1_CTS_B for Mode: ALT3 + 0 + + + CSI_DATA02_ALT0 + Selecting Pad: CSI_DATA02 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA06_SELECT_INPUT + CSI_DATA06_SELECT_INPUT DAISY Register + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_TX_DATA_ALT3 + Selecting Pad: UART2_TX_DATA for Mode: ALT3 + 0 + + + CSI_DATA04_ALT0 + Selecting Pad: CSI_DATA04 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA07_SELECT_INPUT + CSI_DATA07_SELECT_INPUT DAISY Register + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RX_DATA_ALT3 + Selecting Pad: UART2_RX_DATA for Mode: ALT3 + 0 + + + CSI_DATA05_ALT0 + Selecting Pad: CSI_DATA05 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA08_SELECT_INPUT + CSI_DATA08_SELECT_INPUT DAISY Register + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_CTS_B_ALT3 + Selecting Pad: UART2_CTS_B for Mode: ALT3 + 0 + + + CSI_DATA06_ALT0 + Selecting Pad: CSI_DATA06 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA09_SELECT_INPUT + CSI_DATA09_SELECT_INPUT DAISY Register + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RTS_B_ALT3 + Selecting Pad: UART2_RTS_B for Mode: ALT3 + 0 + + + CSI_DATA07_ALT0 + Selecting Pad: CSI_DATA07 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA10_SELECT_INPUT + CSI_DATA10_SELECT_INPUT DAISY Register + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART3_CTS_B_ALT3 + Selecting Pad: UART3_CTS_B for Mode: ALT3 + 0 + + + LCD_DATA18_ALT3 + Selecting Pad: LCD_DATA18 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA11_SELECT_INPUT + CSI_DATA11_SELECT_INPUT DAISY Register + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART3_RTS_B_ALT3 + Selecting Pad: UART3_RTS_B for Mode: ALT3 + 0 + + + LCD_DATA19_ALT3 + Selecting Pad: LCD_DATA19 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA12_SELECT_INPUT + CSI_DATA12_SELECT_INPUT DAISY Register + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART4_TX_DATA_ALT3 + Selecting Pad: UART4_TX_DATA for Mode: ALT3 + 0 + + + LCD_DATA20_ALT3 + Selecting Pad: LCD_DATA20 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA13_SELECT_INPUT + CSI_DATA13_SELECT_INPUT DAISY Register + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART4_RX_DATA_ALT3 + Selecting Pad: UART4_RX_DATA for Mode: ALT3 + 0 + + + LCD_DATA21_ALT3 + Selecting Pad: LCD_DATA21 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA14_SELECT_INPUT + CSI_DATA14_SELECT_INPUT DAISY Register + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART5_TX_DATA_ALT3 + Selecting Pad: UART5_TX_DATA for Mode: ALT3 + 0 + + + LCD_DATA22_ALT3 + Selecting Pad: LCD_DATA22 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA15_SELECT_INPUT + CSI_DATA15_SELECT_INPUT DAISY Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART5_RX_DATA_ALT3 + Selecting Pad: UART5_RX_DATA for Mode: ALT3 + 0 + + + LCD_DATA23_ALT3 + Selecting Pad: LCD_DATA23 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA16_SELECT_INPUT + CSI_DATA16_SELECT_INPUT DAISY Register + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_DATA0_ALT3 + Selecting Pad: ENET1_RX_DATA0 for Mode: ALT3 + 0 + + + LCD_DATA08_ALT3 + Selecting Pad: LCD_DATA08 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA17_SELECT_INPUT + CSI_DATA17_SELECT_INPUT DAISY Register + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_DATA1_ALT3 + Selecting Pad: ENET1_RX_DATA1 for Mode: ALT3 + 0 + + + LCD_DATA09_ALT3 + Selecting Pad: LCD_DATA09 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA18_SELECT_INPUT + CSI_DATA18_SELECT_INPUT DAISY Register + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_EN_ALT3 + Selecting Pad: ENET1_RX_EN for Mode: ALT3 + 0 + + + LCD_DATA10_ALT3 + Selecting Pad: LCD_DATA10 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA19_SELECT_INPUT + CSI_DATA19_SELECT_INPUT DAISY Register + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_DATA0_ALT3 + Selecting Pad: ENET1_TX_DATA0 for Mode: ALT3 + 0 + + + LCD_DATA11_ALT3 + Selecting Pad: LCD_DATA11 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA20_SELECT_INPUT + CSI_DATA20_SELECT_INPUT DAISY Register + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_DATA1_ALT3 + Selecting Pad: ENET1_TX_DATA1 for Mode: ALT3 + 0 + + + LCD_DATA12_ALT3 + Selecting Pad: LCD_DATA12 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA21_SELECT_INPUT + CSI_DATA21_SELECT_INPUT DAISY Register + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_EN_ALT3 + Selecting Pad: ENET1_TX_EN for Mode: ALT3 + 0 + + + LCD_DATA13_ALT3 + Selecting Pad: LCD_DATA13 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA22_SELECT_INPUT + CSI_DATA22_SELECT_INPUT DAISY Register + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_CLK_ALT3 + Selecting Pad: ENET1_TX_CLK for Mode: ALT3 + 0 + + + LCD_DATA14_ALT3 + Selecting Pad: LCD_DATA14 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA23_SELECT_INPUT + CSI_DATA23_SELECT_INPUT DAISY Register + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_ER_ALT3 + Selecting Pad: ENET1_RX_ER for Mode: ALT3 + 0 + + + LCD_DATA15_ALT3 + Selecting Pad: LCD_DATA15 for Mode: ALT3 + 0x1 + + + + + + + CSI_HSYNC_SELECT_INPUT + CSI_HSYNC_SELECT_INPUT DAISY Register + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_HSYNC_ALT0 + Selecting Pad: CSI_HSYNC for Mode: ALT0 + 0 + + + GPIO1_IO09_ALT3 + Selecting Pad: GPIO1_IO09 for Mode: ALT3 + 0x1 + + + + + + + CSI_PIXCLK_SELECT_INPUT + CSI_PIXCLK_SELECT_INPUT DAISY Register + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO07_ALT3 + Selecting Pad: GPIO1_IO07 for Mode: ALT3 + 0 + + + CSI_PIXCLK_ALT0 + Selecting Pad: CSI_PIXCLK for Mode: ALT0 + 0x1 + + + + + + + CSI_VSYNC_SELECT_INPUT + CSI_VSYNC_SELECT_INPUT DAISY Register + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_VSYNC_ALT0 + Selecting Pad: CSI_VSYNC for Mode: ALT0 + 0 + + + GPIO1_IO08_ALT3 + Selecting Pad: GPIO1_IO08 for Mode: ALT3 + 0x1 + + + + + + + CSI_FIELD_SELECT_INPUT + CSI_FIELD_SELECT_INPUT DAISY Register + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO05_ALT3 + Selecting Pad: GPIO1_IO05 for Mode: ALT3 + 0 + + + NAND_DQS_ALT1 + Selecting Pad: NAND_DQS for Mode: ALT1 + 0x1 + + + + + + + ECSPI1_SCLK_SELECT_INPUT + ECSPI1_SCLK_SELECT_INPUT DAISY Register + 0x534 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA20_ALT2 + Selecting Pad: LCD_DATA20 for Mode: ALT2 + 0 + + + CSI_DATA04_ALT3 + Selecting Pad: CSI_DATA04 for Mode: ALT3 + 0x1 + + + + + + + ECSPI1_MISO_SELECT_INPUT + ECSPI1_MISO_SELECT_INPUT DAISY Register + 0x538 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA23_ALT2 + Selecting Pad: LCD_DATA23 for Mode: ALT2 + 0 + + + CSI_DATA07_ALT3 + Selecting Pad: CSI_DATA07 for Mode: ALT3 + 0x1 + + + + + + + ECSPI1_MOSI_SELECT_INPUT + ECSPI1_MOSI_SELECT_INPUT DAISY Register + 0x53C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA22_ALT2 + Selecting Pad: LCD_DATA22 for Mode: ALT2 + 0 + + + CSI_DATA06_ALT3 + Selecting Pad: CSI_DATA06 for Mode: ALT3 + 0x1 + + + + + + + ECSPI1_SS0_B_SELECT_INPUT + ECSPI1_SS0_B_SELECT_INPUT DAISY Register + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA21_ALT2 + Selecting Pad: LCD_DATA21 for Mode: ALT2 + 0 + + + CSI_DATA05_ALT3 + Selecting Pad: CSI_DATA05 for Mode: ALT3 + 0x1 + + + + + + + ECSPI2_SCLK_SELECT_INPUT + ECSPI2_SCLK_SELECT_INPUT DAISY Register + 0x544 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA00_ALT3 + Selecting Pad: CSI_DATA00 for Mode: ALT3 + 0 + + + UART4_TX_DATA_ALT8 + Selecting Pad: UART4_TX_DATA for Mode: ALT8 + 0x1 + + + + + + + ECSPI2_MISO_SELECT_INPUT + ECSPI2_MISO_SELECT_INPUT DAISY Register + 0x548 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA03_ALT3 + Selecting Pad: CSI_DATA03 for Mode: ALT3 + 0 + + + UART5_RX_DATA_ALT8 + Selecting Pad: UART5_RX_DATA for Mode: ALT8 + 0x1 + + + + + + + ECSPI2_MOSI_SELECT_INPUT + ECSPI2_MOSI_SELECT_INPUT DAISY Register + 0x54C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART5_TX_DATA_ALT8 + Selecting Pad: UART5_TX_DATA for Mode: ALT8 + 0 + + + CSI_DATA02_ALT3 + Selecting Pad: CSI_DATA02 for Mode: ALT3 + 0x1 + + + + + + + ECSPI2_SS0_B_SELECT_INPUT + ECSPI2_SS0_B_SELECT_INPUT DAISY Register + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA01_ALT3 + Selecting Pad: CSI_DATA01 for Mode: ALT3 + 0 + + + UART4_RX_DATA_ALT8 + Selecting Pad: UART4_RX_DATA for Mode: ALT8 + 0x1 + + + + + + + ECSPI3_SCLK_SELECT_INPUT + ECSPI3_SCLK_SELECT_INPUT DAISY Register + 0x554 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RX_DATA_ALT8 + Selecting Pad: UART2_RX_DATA for Mode: ALT8 + 0 + + + NAND_CE0_B_ALT3 + Selecting Pad: NAND_CE0_B for Mode: ALT3 + 0x1 + + + + + + + ECSPI3_MISO_SELECT_INPUT + ECSPI3_MISO_SELECT_INPUT DAISY Register + 0x558 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RTS_B_ALT8 + Selecting Pad: UART2_RTS_B for Mode: ALT8 + 0 + + + NAND_CLE_ALT3 + Selecting Pad: NAND_CLE for Mode: ALT3 + 0x1 + + + + + + + ECSPI3_MOSI_SELECT_INPUT + ECSPI3_MOSI_SELECT_INPUT DAISY Register + 0x55C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_CTS_B_ALT8 + Selecting Pad: UART2_CTS_B for Mode: ALT8 + 0 + + + NAND_CE1_B_ALT3 + Selecting Pad: NAND_CE1_B for Mode: ALT3 + 0x1 + + + + + + + ECSPI3_SS0_B_SELECT_INPUT + ECSPI3_SS0_B_SELECT_INPUT DAISY Register + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_TX_DATA_ALT8 + Selecting Pad: UART2_TX_DATA for Mode: ALT8 + 0 + + + NAND_READY_B_ALT3 + Selecting Pad: NAND_READY_B for Mode: ALT3 + 0x1 + + + + + + + ECSPI4_SCLK_SELECT_INPUT + ECSPI4_SCLK_SELECT_INPUT DAISY Register + 0x564 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET2_TX_DATA1_ALT3 + Selecting Pad: ENET2_TX_DATA1 for Mode: ALT3 + 0 + + + NAND_DATA04_ALT3 + Selecting Pad: NAND_DATA04 for Mode: ALT3 + 0x1 + + + + + + + ECSPI4_MISO_SELECT_INPUT + ECSPI4_MISO_SELECT_INPUT DAISY Register + 0x568 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET2_TX_CLK_ALT3 + Selecting Pad: ENET2_TX_CLK for Mode: ALT3 + 0 + + + NAND_DATA06_ALT3 + Selecting Pad: NAND_DATA06 for Mode: ALT3 + 0x1 + + + + + + + ECSPI4_MOSI_SELECT_INPUT + ECSPI4_MOSI_SELECT_INPUT DAISY Register + 0x56C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET2_TX_EN_ALT3 + Selecting Pad: ENET2_TX_EN for Mode: ALT3 + 0 + + + NAND_DATA05_ALT3 + Selecting Pad: NAND_DATA05 for Mode: ALT3 + 0x1 + + + + + + + ECSPI4_SS0_B_SELECT_INPUT + ECSPI4_SS0_B_SELECT_INPUT DAISY Register + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET2_RX_ER_ALT3 + Selecting Pad: ENET2_RX_ER for Mode: ALT3 + 0 + + + NAND_DATA07_ALT3 + Selecting Pad: NAND_DATA07 for Mode: ALT3 + 0x1 + + + + + + + ENET1_REF_CLK1_SELECT_INPUT + ENET1_REF_CLK1_SELECT_INPUT DAISY Register + 0x574 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO00_ALT3 + Selecting Pad: GPIO1_IO00 for Mode: ALT3 + 0 + + + GPIO1_IO04_ALT0 + Selecting Pad: GPIO1_IO04 for Mode: ALT0 + 0x1 + + + ENET1_TX_CLK_ALT4 + Selecting Pad: ENET1_TX_CLK for Mode: ALT4 + 0x2 + + + + + + + ENET1_MAC0_MDIO_SELECT_INPUT + ENET1_MAC0_MDIO_SELECT_INPUT DAISY Register + 0x578 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO06_ALT0 + Selecting Pad: GPIO1_IO06 for Mode: ALT0 + 0 + + + ENET2_RX_DATA0_ALT4 + Selecting Pad: ENET2_RX_DATA0 for Mode: ALT4 + 0x1 + + + + + + + ENET2_REF_CLK2_SELECT_INPUT + ENET2_REF_CLK2_SELECT_INPUT DAISY Register + 0x57C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO01_ALT3 + Selecting Pad: GPIO1_IO01 for Mode: ALT3 + 0 + + + GPIO1_IO05_ALT0 + Selecting Pad: GPIO1_IO05 for Mode: ALT0 + 0x1 + + + ENET2_TX_CLK_ALT4 + Selecting Pad: ENET2_TX_CLK for Mode: ALT4 + 0x2 + + + + + + + ENET2_MAC0_MDIO_SELECT_INPUT + ENET2_MAC0_MDIO_SELECT_INPUT DAISY Register + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO06_ALT1 + Selecting Pad: GPIO1_IO06 for Mode: ALT1 + 0 + + + ENET1_TX_DATA1_ALT4 + Selecting Pad: ENET1_TX_DATA1 for Mode: ALT4 + 0x1 + + + + + + + FLEXCAN1_RX_SELECT_INPUT + FLEXCAN1_RX_SELECT_INPUT DAISY Register + 0x584 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART3_RTS_B_ALT2 + Selecting Pad: UART3_RTS_B for Mode: ALT2 + 0 + + + ENET1_RX_DATA1_ALT4 + Selecting Pad: ENET1_RX_DATA1 for Mode: ALT4 + 0x1 + + + LCD_DATA09_ALT8 + Selecting Pad: LCD_DATA09 for Mode: ALT8 + 0x2 + + + SD1_DATA1_ALT3 + Selecting Pad: SD1_DATA1 for Mode: ALT3 + 0x3 + + + + + + + FLEXCAN2_RX_SELECT_INPUT + FLEXCAN2_RX_SELECT_INPUT DAISY Register + 0x588 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART2_RTS_B_ALT2 + Selecting Pad: UART2_RTS_B for Mode: ALT2 + 0 + + + ENET1_TX_DATA0_ALT4 + Selecting Pad: ENET1_TX_DATA0 for Mode: ALT4 + 0x1 + + + LCD_DATA11_ALT8 + Selecting Pad: LCD_DATA11 for Mode: ALT8 + 0x2 + + + SD1_DATA3_ALT3 + Selecting Pad: SD1_DATA3 for Mode: ALT3 + 0x3 + + + + + + + GPT1_CAPTURE1_SELECT_INPUT + GPT1_CAPTURE1_SELECT_INPUT DAISY Register + 0x58C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO00_ALT1 + Selecting Pad: GPIO1_IO00 for Mode: ALT1 + 0 + + + UART2_TX_DATA_ALT4 + Selecting Pad: UART2_TX_DATA for Mode: ALT4 + 0x1 + + + + + + + GPT1_CAPTURE2_SELECT_INPUT + GPT1_CAPTURE2_SELECT_INPUT DAISY Register + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RX_DATA_ALT4 + Selecting Pad: UART2_RX_DATA for Mode: ALT4 + 0 + + + ENET1_RX_ER_ALT8 + Selecting Pad: ENET1_RX_ER for Mode: ALT8 + 0x1 + + + + + + + GPT1_CLK_SELECT_INPUT + GPT1_CLK_SELECT_INPUT DAISY Register + 0x594 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART1_RX_DATA_ALT4 + Selecting Pad: UART1_RX_DATA for Mode: ALT4 + 0 + + + ENET1_TX_CLK_ALT8 + Selecting Pad: ENET1_TX_CLK for Mode: ALT8 + 0x1 + + + + + + + GPT2_CAPTURE1_SELECT_INPUT + GPT2_CAPTURE1_SELECT_INPUT DAISY Register + 0x598 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TMS_ALT1 + Selecting Pad: JTAG_TMS for Mode: ALT1 + 0 + + + SD1_DATA2_ALT1 + Selecting Pad: SD1_DATA2 for Mode: ALT1 + 0x1 + + + + + + + GPT2_CAPTURE2_SELECT_INPUT + GPT2_CAPTURE2_SELECT_INPUT DAISY Register + 0x59C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TDO_ALT1 + Selecting Pad: JTAG_TDO for Mode: ALT1 + 0 + + + SD1_DATA3_ALT1 + Selecting Pad: SD1_DATA3 for Mode: ALT1 + 0x1 + + + + + + + GPT2_CLK_SELECT_INPUT + GPT2_CLK_SELECT_INPUT DAISY Register + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_MOD_ALT1 + Selecting Pad: JTAG_MOD for Mode: ALT1 + 0 + + + SD1_DATA1_ALT1 + Selecting Pad: SD1_DATA1 for Mode: ALT1 + 0x1 + + + + + + + I2C1_SCL_SELECT_INPUT + I2C1_SCL_SELECT_INPUT DAISY Register + 0x5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO02_ALT0 + Selecting Pad: GPIO1_IO02 for Mode: ALT0 + 0 + + + UART4_TX_DATA_ALT2 + Selecting Pad: UART4_TX_DATA for Mode: ALT2 + 0x1 + + + CSI_PIXCLK_ALT3 + Selecting Pad: CSI_PIXCLK for Mode: ALT3 + 0x2 + + + + + + + I2C1_SDA_SELECT_INPUT + I2C1_SDA_SELECT_INPUT DAISY Register + 0x5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_MCLK_ALT3 + Selecting Pad: CSI_MCLK for Mode: ALT3 + 0 + + + GPIO1_IO03_ALT0 + Selecting Pad: GPIO1_IO03 for Mode: ALT0 + 0x1 + + + UART4_RX_DATA_ALT2 + Selecting Pad: UART4_RX_DATA for Mode: ALT2 + 0x2 + + + + + + + I2C2_SCL_SELECT_INPUT + I2C2_SCL_SELECT_INPUT DAISY Register + 0x5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_HSYNC_ALT3 + Selecting Pad: CSI_HSYNC for Mode: ALT3 + 0 + + + GPIO1_IO00_ALT0 + Selecting Pad: GPIO1_IO00 for Mode: ALT0 + 0x1 + + + UART5_TX_DATA_ALT2 + Selecting Pad: UART5_TX_DATA for Mode: ALT2 + 0x2 + + + + + + + I2C2_SDA_SELECT_INPUT + I2C2_SDA_SELECT_INPUT DAISY Register + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_VSYNC_ALT3 + Selecting Pad: CSI_VSYNC for Mode: ALT3 + 0 + + + GPIO1_IO01_ALT0 + Selecting Pad: GPIO1_IO01 for Mode: ALT0 + 0x1 + + + UART5_RX_DATA_ALT2 + Selecting Pad: UART5_RX_DATA for Mode: ALT2 + 0x2 + + + + + + + I2C3_SCL_SELECT_INPUT + I2C3_SCL_SELECT_INPUT DAISY Register + 0x5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART1_TX_DATA_ALT2 + Selecting Pad: UART1_TX_DATA for Mode: ALT2 + 0 + + + ENET2_RX_DATA0_ALT3 + Selecting Pad: ENET2_RX_DATA0 for Mode: ALT3 + 0x1 + + + LCD_DATA01_ALT4 + Selecting Pad: LCD_DATA01 for Mode: ALT4 + 0x2 + + + + + + + I2C3_SDA_SELECT_INPUT + I2C3_SDA_SELECT_INPUT DAISY Register + 0x5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART1_RX_DATA_ALT2 + Selecting Pad: UART1_RX_DATA for Mode: ALT2 + 0 + + + ENET2_RX_DATA1_ALT3 + Selecting Pad: ENET2_RX_DATA1 for Mode: ALT3 + 0x1 + + + LCD_DATA00_ALT4 + Selecting Pad: LCD_DATA00 for Mode: ALT4 + 0x2 + + + + + + + I2C4_SCL_SELECT_INPUT + I2C4_SCL_SELECT_INPUT DAISY Register + 0x5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART2_TX_DATA_ALT2 + Selecting Pad: UART2_TX_DATA for Mode: ALT2 + 0 + + + ENET2_RX_EN_ALT3 + Selecting Pad: ENET2_RX_EN for Mode: ALT3 + 0x1 + + + LCD_DATA03_ALT4 + Selecting Pad: LCD_DATA03 for Mode: ALT4 + 0x2 + + + + + + + I2C4_SDA_SELECT_INPUT + I2C4_SDA_SELECT_INPUT DAISY Register + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART2_RX_DATA_ALT2 + Selecting Pad: UART2_RX_DATA for Mode: ALT2 + 0 + + + ENET2_TX_DATA0_ALT3 + Selecting Pad: ENET2_TX_DATA0 for Mode: ALT3 + 0x1 + + + LCD_DATA02_ALT4 + Selecting Pad: LCD_DATA02 for Mode: ALT4 + 0x2 + + + + + + + KPP_COL0_SELECT_INPUT + KPP_COL0_SELECT_INPUT DAISY Register + 0x5C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_DATA1_ALT6 + Selecting Pad: ENET1_RX_DATA1 for Mode: ALT6 + 0 + + + NAND_WE_B_ALT3 + Selecting Pad: NAND_WE_B for Mode: ALT3 + 0x1 + + + + + + + KPP_COL1_SELECT_INPUT + KPP_COL1_SELECT_INPUT DAISY Register + 0x5C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_DATA0_ALT6 + Selecting Pad: ENET1_TX_DATA0 for Mode: ALT6 + 0 + + + NAND_DATA01_ALT3 + Selecting Pad: NAND_DATA01 for Mode: ALT3 + 0x1 + + + + + + + KPP_COL2_SELECT_INPUT + KPP_COL2_SELECT_INPUT DAISY Register + 0x5CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_EN_ALT6 + Selecting Pad: ENET1_TX_EN for Mode: ALT6 + 0 + + + NAND_DATA03_ALT3 + Selecting Pad: NAND_DATA03 for Mode: ALT3 + 0x1 + + + + + + + KPP_ROW0_SELECT_INPUT + KPP_ROW0_SELECT_INPUT DAISY Register + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_DATA0_ALT6 + Selecting Pad: ENET1_RX_DATA0 for Mode: ALT6 + 0 + + + NAND_RE_B_ALT3 + Selecting Pad: NAND_RE_B for Mode: ALT3 + 0x1 + + + + + + + KPP_ROW1_SELECT_INPUT + KPP_ROW1_SELECT_INPUT DAISY Register + 0x5D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_EN_ALT6 + Selecting Pad: ENET1_RX_EN for Mode: ALT6 + 0 + + + NAND_DATA00_ALT3 + Selecting Pad: NAND_DATA00 for Mode: ALT3 + 0x1 + + + + + + + KPP_ROW2_SELECT_INPUT + KPP_ROW2_SELECT_INPUT DAISY Register + 0x5D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_DATA1_ALT6 + Selecting Pad: ENET1_TX_DATA1 for Mode: ALT6 + 0 + + + NAND_DATA02_ALT3 + Selecting Pad: NAND_DATA02 for Mode: ALT3 + 0x1 + + + + + + + LCD_BUSY_SELECT_INPUT + LCD_BUSY_SELECT_INPUT DAISY Register + 0x5DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_HSYNC_ALT0 + Selecting Pad: LCD_HSYNC for Mode: ALT0 + 0 + + + LCD_VSYNC_ALT1 + Selecting Pad: LCD_VSYNC for Mode: ALT1 + 0x1 + + + + + + + SAI1_MCLK_SELECT_INPUT + SAI1_MCLK_SELECT_INPUT DAISY Register + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA01_ALT6 + Selecting Pad: CSI_DATA01 for Mode: ALT6 + 0 + + + LCD_DATA00_ALT8 + Selecting Pad: LCD_DATA00 for Mode: ALT8 + 0x1 + + + + + + + SAI1_RX_DATA_SELECT_INPUT + SAI1_RX_DATA_SELECT_INPUT DAISY Register + 0x5E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA03_ALT8 + Selecting Pad: LCD_DATA03 for Mode: ALT8 + 0 + + + CSI_DATA06_ALT6 + Selecting Pad: CSI_DATA06 for Mode: ALT6 + 0x1 + + + + + + + SAI1_TX_BCLK_SELECT_INPUT + SAI1_TX_BCLK_SELECT_INPUT DAISY Register + 0x5E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA02_ALT8 + Selecting Pad: LCD_DATA02 for Mode: ALT8 + 0 + + + CSI_DATA05_ALT6 + Selecting Pad: CSI_DATA05 for Mode: ALT6 + 0x1 + + + + + + + SAI1_TX_SYNC_SELECT_INPUT + SAI1_TX_SYNC_SELECT_INPUT DAISY Register + 0x5EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA01_ALT8 + Selecting Pad: LCD_DATA01 for Mode: ALT8 + 0 + + + CSI_DATA04_ALT6 + Selecting Pad: CSI_DATA04 for Mode: ALT6 + 0x1 + + + + + + + SAI2_MCLK_SELECT_INPUT + SAI2_MCLK_SELECT_INPUT DAISY Register + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TMS_ALT2 + Selecting Pad: JTAG_TMS for Mode: ALT2 + 0 + + + SD1_CLK_ALT2 + Selecting Pad: SD1_CLK for Mode: ALT2 + 0x1 + + + + + + + SAI2_RX_DATA_SELECT_INPUT + SAI2_RX_DATA_SELECT_INPUT DAISY Register + 0x5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TCK_ALT2 + Selecting Pad: JTAG_TCK for Mode: ALT2 + 0 + + + SD1_DATA2_ALT2 + Selecting Pad: SD1_DATA2 for Mode: ALT2 + 0x1 + + + + + + + SAI2_TX_BCLK_SELECT_INPUT + SAI2_TX_BCLK_SELECT_INPUT DAISY Register + 0x5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TDI_ALT2 + Selecting Pad: JTAG_TDI for Mode: ALT2 + 0 + + + SD1_DATA1_ALT2 + Selecting Pad: SD1_DATA1 for Mode: ALT2 + 0x1 + + + + + + + SAI2_TX_SYNC_SELECT_INPUT + SAI2_TX_SYNC_SELECT_INPUT DAISY Register + 0x5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TDO_ALT2 + Selecting Pad: JTAG_TDO for Mode: ALT2 + 0 + + + SD1_DATA0_ALT2 + Selecting Pad: SD1_DATA0 for Mode: ALT2 + 0x1 + + + + + + + SAI3_MCLK_SELECT_INPUT + SAI3_MCLK_SELECT_INPUT DAISY Register + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_CLK_ALT3 + Selecting Pad: LCD_CLK for Mode: ALT3 + 0 + + + LCD_DATA09_ALT1 + Selecting Pad: LCD_DATA09 for Mode: ALT1 + 0x1 + + + + + + + SAI3_RX_DATA_SELECT_INPUT + SAI3_RX_DATA_SELECT_INPUT DAISY Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_VSYNC_ALT3 + Selecting Pad: LCD_VSYNC for Mode: ALT3 + 0 + + + LCD_DATA14_ALT1 + Selecting Pad: LCD_DATA14 for Mode: ALT1 + 0x1 + + + + + + + SAI3_TX_BCLK_SELECT_INPUT + SAI3_TX_BCLK_SELECT_INPUT DAISY Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_HSYNC_ALT3 + Selecting Pad: LCD_HSYNC for Mode: ALT3 + 0 + + + LCD_DATA13_ALT1 + Selecting Pad: LCD_DATA13 for Mode: ALT1 + 0x1 + + + + + + + SAI3_TX_SYNC_SELECT_INPUT + SAI3_TX_SYNC_SELECT_INPUT DAISY Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_ENABLE_ALT3 + Selecting Pad: LCD_ENABLE for Mode: ALT3 + 0 + + + LCD_DATA12_ALT1 + Selecting Pad: LCD_DATA12 for Mode: ALT1 + 0x1 + + + + + + + SDMA_EVENTS0_SELECT_INPUT + SDMA_EVENTS0_SELECT_INPUT DAISY Register + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + JTAG_MOD_ALT6 + Selecting Pad: JTAG_MOD for Mode: ALT6 + 0 + + + GPIO1_IO02_ALT6 + Selecting Pad: GPIO1_IO02 for Mode: ALT6 + 0x1 + + + SD1_CMD_ALT6 + Selecting Pad: SD1_CMD for Mode: ALT6 + 0x2 + + + + + + + SDMA_EVENTS1_SELECT_INPUT + SDMA_EVENTS1_SELECT_INPUT DAISY Register + 0x614 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TMS_ALT6 + Selecting Pad: JTAG_TMS for Mode: ALT6 + 0 + + + NAND_DQS_ALT6 + Selecting Pad: NAND_DQS for Mode: ALT6 + 0x1 + + + + + + + SPDIF_IN_SELECT_INPUT + SPDIF_IN_SELECT_INPUT DAISY Register + 0x618 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO09_ALT2 + Selecting Pad: GPIO1_IO09 for Mode: ALT2 + 0 + + + UART1_RX_DATA_ALT8 + Selecting Pad: UART1_RX_DATA for Mode: ALT8 + 0x1 + + + LCD_DATA08_ALT1 + Selecting Pad: LCD_DATA08 for Mode: ALT1 + 0x2 + + + SD1_CLK_ALT3 + Selecting Pad: SD1_CLK for Mode: ALT3 + 0x3 + + + + + + + SPDIF_EXT_CLK_SELECT_INPUT + SPDIF_EXT_CLK_SELECT_INPUT DAISY Register + 0x61C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA07_ALT4 + Selecting Pad: LCD_DATA07 for Mode: ALT4 + 0 + + + NAND_DQS_ALT8 + Selecting Pad: NAND_DQS for Mode: ALT8 + 0x1 + + + + + + + UART1_RTS_B_SELECT_INPUT + UART1_RTS_B_SELECT_INPUT DAISY Register + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO06_ALT8 + Selecting Pad: GPIO1_IO06 for Mode: ALT8 + 0 + + + GPIO1_IO07_ALT8 + Selecting Pad: GPIO1_IO07 for Mode: ALT8 + 0x1 + + + UART1_CTS_B_ALT0 + Selecting Pad: UART1_CTS_B for Mode: ALT0 + 0x2 + + + UART1_RTS_B_ALT0 + Selecting Pad: UART1_RTS_B for Mode: ALT0 + 0x3 + + + + + + + UART1_RX_DATA_SELECT_INPUT + UART1_RX_DATA_SELECT_INPUT DAISY Register + 0x624 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO02_ALT8 + Selecting Pad: GPIO1_IO02 for Mode: ALT8 + 0 + + + GPIO1_IO03_ALT8 + Selecting Pad: GPIO1_IO03 for Mode: ALT8 + 0x1 + + + UART1_TX_DATA_ALT0 + Selecting Pad: UART1_TX_DATA for Mode: ALT0 + 0x2 + + + UART1_RX_DATA_ALT0 + Selecting Pad: UART1_RX_DATA for Mode: ALT0 + 0x3 + + + + + + + UART2_RTS_B_SELECT_INPUT + UART2_RTS_B_SELECT_INPUT DAISY Register + 0x628 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + UART2_CTS_B_ALT0 + Selecting Pad: UART2_CTS_B for Mode: ALT0 + 0 + + + UART2_RTS_B_ALT0 + Selecting Pad: UART2_RTS_B for Mode: ALT0 + 0x1 + + + UART3_TX_DATA_ALT4 + Selecting Pad: UART3_TX_DATA for Mode: ALT4 + 0x2 + + + UART3_RX_DATA_ALT4 + Selecting Pad: UART3_RX_DATA for Mode: ALT4 + 0x3 + + + NAND_DATA06_ALT8 + Selecting Pad: NAND_DATA06 for Mode: ALT8 + 0x4 + + + NAND_DATA07_ALT8 + Selecting Pad: NAND_DATA07 for Mode: ALT8 + 0x5 + + + + + + + UART2_RX_DATA_SELECT_INPUT + UART2_RX_DATA_SELECT_INPUT DAISY Register + 0x62C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART2_TX_DATA_ALT0 + Selecting Pad: UART2_TX_DATA for Mode: ALT0 + 0 + + + UART2_RX_DATA_ALT0 + Selecting Pad: UART2_RX_DATA for Mode: ALT0 + 0x1 + + + NAND_DATA04_ALT8 + Selecting Pad: NAND_DATA04 for Mode: ALT8 + 0x2 + + + NAND_DATA05_ALT8 + Selecting Pad: NAND_DATA05 for Mode: ALT8 + 0x3 + + + + + + + UART3_RTS_B_SELECT_INPUT + UART3_RTS_B_SELECT_INPUT DAISY Register + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART3_CTS_B_ALT0 + Selecting Pad: UART3_CTS_B for Mode: ALT0 + 0 + + + UART3_RTS_B_ALT0 + Selecting Pad: UART3_RTS_B for Mode: ALT0 + 0x1 + + + NAND_CE1_B_ALT8 + Selecting Pad: NAND_CE1_B for Mode: ALT8 + 0x2 + + + NAND_CLE_ALT8 + Selecting Pad: NAND_CLE for Mode: ALT8 + 0x3 + + + + + + + UART3_RX_DATA_SELECT_INPUT + UART3_RX_DATA_SELECT_INPUT DAISY Register + 0x634 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART3_TX_DATA_ALT0 + Selecting Pad: UART3_TX_DATA for Mode: ALT0 + 0 + + + UART3_RX_DATA_ALT0 + Selecting Pad: UART3_RX_DATA for Mode: ALT0 + 0x1 + + + NAND_READY_B_ALT8 + Selecting Pad: NAND_READY_B for Mode: ALT8 + 0x2 + + + NAND_CE0_B_ALT8 + Selecting Pad: NAND_CE0_B for Mode: ALT8 + 0x3 + + + + + + + UART4_RTS_B_SELECT_INPUT + UART4_RTS_B_SELECT_INPUT DAISY Register + 0x638 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET1_RX_DATA0_ALT1 + Selecting Pad: ENET1_RX_DATA0 for Mode: ALT1 + 0 + + + ENET1_RX_DATA1_ALT1 + Selecting Pad: ENET1_RX_DATA1 for Mode: ALT1 + 0x1 + + + LCD_HSYNC_ALT2 + Selecting Pad: LCD_HSYNC for Mode: ALT2 + 0x2 + + + LCD_VSYNC_ALT2 + Selecting Pad: LCD_VSYNC for Mode: ALT2 + 0x3 + + + + + + + UART4_RX_DATA_SELECT_INPUT + UART4_RX_DATA_SELECT_INPUT DAISY Register + 0x63C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART4_TX_DATA_ALT0 + Selecting Pad: UART4_TX_DATA for Mode: ALT0 + 0 + + + UART4_RX_DATA_ALT0 + Selecting Pad: UART4_RX_DATA for Mode: ALT0 + 0x1 + + + LCD_CLK_ALT2 + Selecting Pad: LCD_CLK for Mode: ALT2 + 0x2 + + + LCD_ENABLE_ALT2 + Selecting Pad: LCD_ENABLE for Mode: ALT2 + 0x3 + + + + + + + UART5_RTS_B_SELECT_INPUT + UART5_RTS_B_SELECT_INPUT DAISY Register + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + CSI_DATA03_ALT8 + Selecting Pad: CSI_DATA03 for Mode: ALT8 + 0 + + + GPIO1_IO08_ALT8 + Selecting Pad: GPIO1_IO08 for Mode: ALT8 + 0x1 + + + GPIO1_IO09_ALT8 + Selecting Pad: GPIO1_IO09 for Mode: ALT8 + 0x2 + + + UART1_CTS_B_ALT9 + Selecting Pad: UART1_CTS_B for Mode: ALT9 + 0x3 + + + UART1_RTS_B_ALT9 + Selecting Pad: UART1_RTS_B for Mode: ALT9 + 0x4 + + + ENET1_RX_EN_ALT1 + Selecting Pad: ENET1_RX_EN for Mode: ALT1 + 0x5 + + + ENET1_TX_DATA0_ALT1 + Selecting Pad: ENET1_TX_DATA0 for Mode: ALT1 + 0x6 + + + CSI_DATA02_ALT8 + Selecting Pad: CSI_DATA02 for Mode: ALT8 + 0x7 + + + + + + + UART5_RX_DATA_SELECT_INPUT + UART5_RX_DATA_SELECT_INPUT DAISY Register + 0x644 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + CSI_DATA00_ALT8 + Selecting Pad: CSI_DATA00 for Mode: ALT8 + 0 + + + CSI_DATA01_ALT8 + Selecting Pad: CSI_DATA01 for Mode: ALT8 + 0x1 + + + GPIO1_IO04_ALT8 + Selecting Pad: GPIO1_IO04 for Mode: ALT8 + 0x2 + + + GPIO1_IO05_ALT8 + Selecting Pad: GPIO1_IO05 for Mode: ALT8 + 0x3 + + + UART1_TX_DATA_ALT9 + Selecting Pad: UART1_TX_DATA for Mode: ALT9 + 0x4 + + + UART1_RX_DATA_ALT9 + Selecting Pad: UART1_RX_DATA for Mode: ALT9 + 0x5 + + + UART5_TX_DATA_ALT0 + Selecting Pad: UART5_TX_DATA for Mode: ALT0 + 0x6 + + + UART5_RX_DATA_ALT0 + Selecting Pad: UART5_RX_DATA for Mode: ALT0 + 0x7 + + + + + + + UART6_RTS_B_SELECT_INPUT + UART6_RTS_B_SELECT_INPUT DAISY Register + 0x648 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_VSYNC_ALT8 + Selecting Pad: CSI_VSYNC for Mode: ALT8 + 0 + + + CSI_HSYNC_ALT8 + Selecting Pad: CSI_HSYNC for Mode: ALT8 + 0x1 + + + ENET1_TX_DATA1_ALT1 + Selecting Pad: ENET1_TX_DATA1 for Mode: ALT1 + 0x2 + + + ENET1_TX_EN_ALT1 + Selecting Pad: ENET1_TX_EN for Mode: ALT1 + 0x3 + + + + + + + UART6_RX_DATA_SELECT_INPUT + UART6_RX_DATA_SELECT_INPUT DAISY Register + 0x64C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_MCLK_ALT8 + Selecting Pad: CSI_MCLK for Mode: ALT8 + 0 + + + ENET2_RX_DATA0_ALT1 + Selecting Pad: ENET2_RX_DATA0 for Mode: ALT1 + 0x1 + + + ENET2_RX_DATA1_ALT1 + Selecting Pad: ENET2_RX_DATA1 for Mode: ALT1 + 0x2 + + + CSI_PIXCLK_ALT8 + Selecting Pad: CSI_PIXCLK for Mode: ALT8 + 0x3 + + + + + + + UART7_RTS_B_SELECT_INPUT + UART7_RTS_B_SELECT_INPUT DAISY Register + 0x650 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET1_TX_CLK_ALT1 + Selecting Pad: ENET1_TX_CLK for Mode: ALT1 + 0 + + + ENET1_RX_ER_ALT1 + Selecting Pad: ENET1_RX_ER for Mode: ALT1 + 0x1 + + + LCD_DATA06_ALT1 + Selecting Pad: LCD_DATA06 for Mode: ALT1 + 0x2 + + + LCD_DATA07_ALT1 + Selecting Pad: LCD_DATA07 for Mode: ALT1 + 0x3 + + + + + + + UART7_RX_DATA_SELECT_INPUT + UART7_RX_DATA_SELECT_INPUT DAISY Register + 0x654 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET2_RX_EN_ALT1 + Selecting Pad: ENET2_RX_EN for Mode: ALT1 + 0 + + + ENET2_TX_DATA0_ALT1 + Selecting Pad: ENET2_TX_DATA0 for Mode: ALT1 + 0x1 + + + LCD_DATA16_ALT1 + Selecting Pad: LCD_DATA16 for Mode: ALT1 + 0x2 + + + LCD_DATA17_ALT1 + Selecting Pad: LCD_DATA17 for Mode: ALT1 + 0x3 + + + + + + + UART8_RTS_B_SELECT_INPUT + UART8_RTS_B_SELECT_INPUT DAISY Register + 0x658 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET2_TX_CLK_ALT1 + Selecting Pad: ENET2_TX_CLK for Mode: ALT1 + 0 + + + ENET2_RX_ER_ALT1 + Selecting Pad: ENET2_RX_ER for Mode: ALT1 + 0x1 + + + LCD_DATA04_ALT1 + Selecting Pad: LCD_DATA04 for Mode: ALT1 + 0x2 + + + LCD_DATA05_ALT1 + Selecting Pad: LCD_DATA05 for Mode: ALT1 + 0x3 + + + + + + + UART8_RX_DATA_SELECT_INPUT + UART8_RX_DATA_SELECT_INPUT DAISY Register + 0x65C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET2_TX_DATA1_ALT1 + Selecting Pad: ENET2_TX_DATA1 for Mode: ALT1 + 0 + + + ENET2_TX_EN_ALT1 + Selecting Pad: ENET2_TX_EN for Mode: ALT1 + 0x1 + + + LCD_DATA20_ALT1 + Selecting Pad: LCD_DATA20 for Mode: ALT1 + 0x2 + + + LCD_DATA21_ALT1 + Selecting Pad: LCD_DATA21 for Mode: ALT1 + 0x3 + + + + + + + USB_OTG2_OC_SELECT_INPUT + USB_OTG2_OC_SELECT_INPUT DAISY Register + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO03_ALT2 + Selecting Pad: GPIO1_IO03 for Mode: ALT2 + 0 + + + ENET2_TX_EN_ALT8 + Selecting Pad: ENET2_TX_EN for Mode: ALT8 + 0x1 + + + SD1_DATA2_ALT8 + Selecting Pad: SD1_DATA2 for Mode: ALT8 + 0x2 + + + + + + + USB_OTG_OC_SELECT_INPUT + USB_OTG_OC_SELECT_INPUT DAISY Register + 0x664 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO01_ALT2 + Selecting Pad: GPIO1_IO01 for Mode: ALT2 + 0 + + + ENET2_RX_DATA1_ALT8 + Selecting Pad: ENET2_RX_DATA1 for Mode: ALT8 + 0x1 + + + SD1_CLK_ALT8 + Selecting Pad: SD1_CLK for Mode: ALT8 + 0x2 + + + + + + + USDHC1_CD_B_SELECT_INPUT + USDHC1_CD_B_SELECT_INPUT DAISY Register + 0x668 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO03_ALT4 + Selecting Pad: GPIO1_IO03 for Mode: ALT4 + 0 + + + UART1_RTS_B_ALT2 + Selecting Pad: UART1_RTS_B for Mode: ALT2 + 0x1 + + + CSI_DATA05_ALT8 + Selecting Pad: CSI_DATA05 for Mode: ALT8 + 0x2 + + + + + + + USDHC1_WP_SELECT_INPUT + USDHC1_WP_SELECT_INPUT DAISY Register + 0x66C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO02_ALT4 + Selecting Pad: GPIO1_IO02 for Mode: ALT4 + 0 + + + UART1_CTS_B_ALT2 + Selecting Pad: UART1_CTS_B for Mode: ALT2 + 0x1 + + + CSI_DATA04_ALT8 + Selecting Pad: CSI_DATA04 for Mode: ALT8 + 0x2 + + + + + + + USDHC2_CLK_SELECT_INPUT + USDHC2_CLK_SELECT_INPUT DAISY Register + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_VSYNC_ALT1 + Selecting Pad: CSI_VSYNC for Mode: ALT1 + 0 + + + LCD_DATA19_ALT8 + Selecting Pad: LCD_DATA19 for Mode: ALT8 + 0x1 + + + NAND_RE_B_ALT1 + Selecting Pad: NAND_RE_B for Mode: ALT1 + 0x2 + + + + + + + USDHC2_CD_B_SELECT_INPUT + USDHC2_CD_B_SELECT_INPUT DAISY Register + 0x674 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_MCLK_ALT1 + Selecting Pad: CSI_MCLK for Mode: ALT1 + 0 + + + GPIO1_IO07_ALT4 + Selecting Pad: GPIO1_IO07 for Mode: ALT4 + 0x1 + + + UART1_RTS_B_ALT8 + Selecting Pad: UART1_RTS_B for Mode: ALT8 + 0x2 + + + + + + + USDHC2_CMD_SELECT_INPUT + USDHC2_CMD_SELECT_INPUT DAISY Register + 0x678 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_HSYNC_ALT1 + Selecting Pad: CSI_HSYNC for Mode: ALT1 + 0 + + + LCD_DATA18_ALT8 + Selecting Pad: LCD_DATA18 for Mode: ALT8 + 0x1 + + + NAND_WE_B_ALT1 + Selecting Pad: NAND_WE_B for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA0_SELECT_INPUT + USDHC2_DATA0_SELECT_INPUT DAISY Register + 0x67C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_DATA00_ALT1 + Selecting Pad: CSI_DATA00 for Mode: ALT1 + 0 + + + LCD_DATA20_ALT8 + Selecting Pad: LCD_DATA20 for Mode: ALT8 + 0x1 + + + NAND_DATA00_ALT1 + Selecting Pad: NAND_DATA00 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA1_SELECT_INPUT + USDHC2_DATA1_SELECT_INPUT DAISY Register + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_DATA01_ALT1 + Selecting Pad: CSI_DATA01 for Mode: ALT1 + 0 + + + LCD_DATA21_ALT8 + Selecting Pad: LCD_DATA21 for Mode: ALT8 + 0x1 + + + NAND_DATA01_ALT1 + Selecting Pad: NAND_DATA01 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA2_SELECT_INPUT + USDHC2_DATA2_SELECT_INPUT DAISY Register + 0x684 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA22_ALT8 + Selecting Pad: LCD_DATA22 for Mode: ALT8 + 0 + + + NAND_DATA02_ALT1 + Selecting Pad: NAND_DATA02 for Mode: ALT1 + 0x1 + + + CSI_DATA02_ALT1 + Selecting Pad: CSI_DATA02 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA3_SELECT_INPUT + USDHC2_DATA3_SELECT_INPUT DAISY Register + 0x688 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_DATA03_ALT1 + Selecting Pad: CSI_DATA03 for Mode: ALT1 + 0 + + + LCD_DATA23_ALT8 + Selecting Pad: LCD_DATA23 for Mode: ALT8 + 0x1 + + + NAND_DATA03_ALT1 + Selecting Pad: NAND_DATA03 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA4_SELECT_INPUT + USDHC2_DATA4_SELECT_INPUT DAISY Register + 0x68C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA14_ALT8 + Selecting Pad: LCD_DATA14 for Mode: ALT8 + 0 + + + NAND_DATA04_ALT1 + Selecting Pad: NAND_DATA04 for Mode: ALT1 + 0x1 + + + CSI_DATA04_ALT1 + Selecting Pad: CSI_DATA04 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA5_SELECT_INPUT + USDHC2_DATA5_SELECT_INPUT DAISY Register + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA15_ALT8 + Selecting Pad: LCD_DATA15 for Mode: ALT8 + 0 + + + NAND_DATA05_ALT1 + Selecting Pad: NAND_DATA05 for Mode: ALT1 + 0x1 + + + CSI_DATA05_ALT1 + Selecting Pad: CSI_DATA05 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA6_SELECT_INPUT + USDHC2_DATA6_SELECT_INPUT DAISY Register + 0x694 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA16_ALT8 + Selecting Pad: LCD_DATA16 for Mode: ALT8 + 0 + + + NAND_DATA06_ALT1 + Selecting Pad: NAND_DATA06 for Mode: ALT1 + 0x1 + + + CSI_DATA06_ALT1 + Selecting Pad: CSI_DATA06 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA7_SELECT_INPUT + USDHC2_DATA7_SELECT_INPUT DAISY Register + 0x698 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA17_ALT8 + Selecting Pad: LCD_DATA17 for Mode: ALT8 + 0 + + + NAND_DATA07_ALT1 + Selecting Pad: NAND_DATA07 for Mode: ALT1 + 0x1 + + + CSI_DATA07_ALT1 + Selecting Pad: CSI_DATA07 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_WP_SELECT_INPUT + USDHC2_WP_SELECT_INPUT DAISY Register + 0x69C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO06_ALT4 + Selecting Pad: GPIO1_IO06 for Mode: ALT4 + 0 + + + UART1_CTS_B_ALT8 + Selecting Pad: UART1_CTS_B for Mode: ALT8 + 0x1 + + + CSI_PIXCLK_ALT1 + Selecting Pad: CSI_PIXCLK for Mode: ALT1 + 0x2 + + + + + + + + + IOMUXC_GPR + IOMUXC + IOMUXC_GPR + IOMUXC_GPR_ + 0x20E4000 + + 0 + 0x3C + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMAREQ_MUX_SEL0 + Selects between two possible sources for SDMA_EVENT[2]: + 0 + 1 + read-write + + + DMAREQ_MUX_SEL0_0 + sim2.ipd_sim_tx_dmareq + 0 + + + DMAREQ_MUX_SEL0_1 + uart6.ipd_uart_tx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL1 + Selects between two possible sources for SDMA_EVENT[7]: + 0x1 + 1 + read-write + + + DMAREQ_MUX_SEL1_0 + sim2.ipd_sim_rx_dmareq + 0 + + + DMAREQ_MUX_SEL1_1 + uart6.ipd_uart_rx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL2 + Selects between two possible sources for SDMA_EVENT[8]: + 0x2 + 1 + read-write + + + DMAREQ_MUX_SEL2_0 + sim1.ipd_sim_tx_dmareq + 0 + + + DMAREQ_MUX_SEL2_1 + uart5.ipd_uart_tx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL3 + Selects between two possible sources for SDMA_EVENT[9]: + 0x3 + 1 + read-write + + + DMAREQ_MUX_SEL3_0 + sim1.ipd_sim_rx_dmareq + 0 + + + DMAREQ_MUX_SEL3_1 + uart5.ipd_uart_rx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL4 + Selects between two possible sources for SDMA_EVENT[10]: + 0x4 + 1 + read-write + + + DMAREQ_MUX_SEL4_0 + enet2.ipd_req_mac0_timer[1] + 0 + + + DMAREQ_MUX_SEL4_1 + uart8.ipd_uart_tx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL5 + Selects between two possible sources for SDMA_EVENT[16]: + 0x5 + 1 + read-write + + + DMAREQ_MUX_SEL5_0 + enet2.ipd_req_mac0_timer[0] + 0 + + + DMAREQ_MUX_SEL5_1 + uart8.ipd_uart_rx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL6 + Selects between two possible sources for SDMA_EVENT[24]: + 0x6 + 1 + read-write + + + DMAREQ_MUX_SEL6_0 + enet1.ipd_req_mac0_timer[1] + 0 + + + DMAREQ_MUX_SEL6_1 + uart7.ipd_uart_tx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL7 + Selects between two possible sources for SDMA_EVENT[13]: + 0x7 + 1 + read-write + + + DMAREQ_MUX_SEL7_0 + enet1.ipd_req_mac0_timer[0] + 0 + + + DMAREQ_MUX_SEL7_1 + uart7.ipd_uart_rx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL8 + Selects between two possible sources for SDMA_EVENT[43]: + 0x8 + 1 + read-write + + + DMAREQ_MUX_SEL8_0 + adc2.ipd_req + 0 + + + DMAREQ_MUX_SEL8_1 + tsc_dig.interrupt + 0x1 + + + + + DMAREQ_MUX_SEL9 + Selects between two possible sources for SDMA_EVENT[44]: + 0x9 + 1 + read-write + + + DMAREQ_MUX_SEL9_0 + gpt2.ipi_int_gpt + 0 + + + DMAREQ_MUX_SEL9_1 + lcdif.lcdif_irq + 0x1 + + + + + DMAREQ_MUX_SEL10 + Selects between two possible sources for SDMA_EVENT[45]: + 0xA + 1 + read-write + + + DMAREQ_MUX_SEL10_0 + epit1.ipi_int_epit_oc + 0 + + + DMAREQ_MUX_SEL10_1 + csi.ipi_csi_int + 0x1 + + + + + DMAREQ_MUX_SEL11 + Selects between two possible sources for SDMA_EVENT[46]: + 0xB + 1 + read-write + + + DMAREQ_MUX_SEL11_0 + ecspi4.ipd_req_cspi_tdma + 0 + + + DMAREQ_MUX_SEL11_1 + i2c4.ipi_int + 0x1 + + + + + DMAREQ_MUX_SEL12 + Selects between two possible sources for SDMA_EVENT[33]: + 0xC + 1 + read-write + + + DMAREQ_MUX_SEL12_0 + ecspi4.ipd_req_cspi_rdma + 0 + + + DMAREQ_MUX_SEL12_1 + i2c3.ipi_int + 0x1 + + + + + DMAREQ_MUX_SEL13 + Selects between two possible sources for SDMA_EVENT[34]: + 0xD + 1 + read-write + + + DMAREQ_MUX_SEL13_0 + ecspi3.ipd_req_cspi_tdma + 0 + + + DMAREQ_MUX_SEL13_1 + i2c2.ipi_int + 0x1 + + + + + DMAREQ_MUX_SEL14 + Selects between two possible sources for SDMA_EVENT[0]: + 0xE + 1 + read-write + + + DMAREQ_MUX_SEL14_0 + ecspi3.ipd_req_cspi_rdma + 0 + + + DMAREQ_MUX_SEL14_1 + i2c1.ipi_int + 0x1 + + + + + DMAREQ_MUX_SEL15 + Selects between two possible sources for SDMA_EVENT[47]: + 0xF + 1 + read-write + + + DMAREQ_MUX_SEL15_0 + epit2.ipi_int_epit_oc + 0 + + + DMAREQ_MUX_SEL15_1 + pxp.pxp_irq + 0x1 + + + + + DMAREQ_MUX_SEL16 + Selects between two possible sources for SDMA_EVENT[32]: + 0x10 + 1 + read-write + + + DMAREQ_MUX_SEL16_0 + uart4.ipd_uart_tx_dmareq_b (default) + 0 + + + DMAREQ_MUX_SEL16_1 + sai1.ipd_req_sai_tx + 0x1 + + + + + DMAREQ_MUX_SEL17 + Selects between two possible sources for SDMA_EVENT[33]: + 0x11 + 1 + read-write + + + DMAREQ_MUX_SEL17_0 + uart5.ipd_uart_rx_dmareq_b (default) + 0 + + + DMAREQ_MUX_SEL17_1 + sai2.ipd_req_sai_rx + 0x1 + + + + + DMAREQ_MUX_SEL18 + Selects between two possible sources for SDMA_EVENT[34]: + 0x12 + 1 + read-write + + + DMAREQ_MUX_SEL18_0 + uart5.ipd_uart_tx_dmareq_b (default) + 0 + + + DMAREQ_MUX_SEL18_1 + sai2.ipd_req_sai_tx + 0x1 + + + + + DMAREQ_MUX_SEL19 + Selects between two possible sources for SDMA_EVENT[47]: + 0x13 + 1 + read-write + + + DMAREQ_MUX_SEL19_0 + uart6.ipd_uart_tx_dmareq_b (default) + 0 + + + + + DMAREQ_MUX_SEL20 + Selects between two possible sources for SDMA_EVENT[2]: + 0x14 + 1 + read-write + + + DMAREQ_MUX_SEL20_0 + iomux_top.sdma_events[14] (default) + 0 + + + DMAREQ_MUX_SEL20_1 + csi2.ipi_csi_int_b + 0x1 + + + + + DMAREQ_MUX_SEL21 + Selects between two possible sources for SDMA_EVENT[29]: + 0x15 + 1 + read-write + + + DMAREQ_MUX_SEL21_0 + uart3.ipd_uart_rx_dmareq_b (default) + 0 + + + + + DMAREQ_MUX_SEL22 + Selects between two possible sources for SDMA_EVENT[30]: + 0x16 + 1 + read-write + + + DMAREQ_MUX_SEL22_0 + uart3.ipd_uart_tx_dmareq_b (default) + 0 + + + + + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-write + 0xF400005 + 0xFFFFFFFF + + + ACT_CS0 + See description for ADDRS3[10] + 0 + 1 + read-write + + + ADDRS0 + See description for ADDRS3[10] + 0x1 + 2 + read-write + + + ACT_CS1 + See description for ADDRS3[10] + 0x3 + 1 + read-write + + + ADDRS1 + See description for ADDRS3[10] + 0x4 + 2 + read-write + + + ACT_CS2 + See description for ADDRS3[10] + 0x6 + 1 + read-write + + + ADDRS2 + See description for ADDRS3[10] + 0x7 + 2 + read-write + + + ACT_CS3 + See description for ADDRS3[10] + 0x9 + 1 + read-write + + + ADDRS3 + Active Chip Select and Address Space + 0xA + 2 + read-write + + + ADDRS3_0 + 32 MByte + 0 + + + ADDRS3_1 + 64 MByte + 0x1 + + + ADDRS3_2 + 128 MByte + 0x2 + + + + + GINT + Global interrupt "0" bit (connected to ARM A7 IRQ#0 and GPC) + 0xC + 1 + read-write + + + GINT_0 + Global interrupt request is not asserted + 0 + + + GINT_1 + Global interrupt request is asserted + 0x1 + + + + + ENET1_CLK_SEL + ENET1 reference clock mode select. + 0xD + 1 + read-write + + + ENET1_CLK_SEL_0 + ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + 0 + + + ENET1_CLK_SEL_1 + Gets ENET1 TX reference clk from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller + 0x1 + + + + + ENET2_CLK_SEL + ENET2 reference clock mode select. + 0xE + 1 + read-write + + + ENET2_CLK_SEL_0 + ENET2 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK2 function. + 0 + + + ENET2_CLK_SEL_1 + Gets ENET2 TX reference clk from the ENET2_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller + 0x1 + + + + + USB_EXP_MODE + USB Exposure mode + 0xF + 1 + read-write + + + USB_EXP_MODE_0 + Exposure mode is disabled. + 0 + + + USB_EXP_MODE_1 + Exposure mode is enabled. + 0x1 + + + + + ADD_DS + Setting ADD_DS to 0 will make the output driver of the SD3 pins ~10% stronger at highest drive strength (DSE=111). This is for use if the I/O buffer operation at WCS and 200 MHz is marginal. + 0x10 + 1 + read-write + + + ADD_DS_0 + output driver ~10% stronger + 0 + + + ADD_DS_1 + output driver is normal + 0x1 + + + + + ENET1_TX_CLK_DIR + ENET1_TX_CLK data direction control when anatop. ENET_REF_CLK1 is selected (ALT1) + 0x11 + 1 + read-write + + + ENET1_TX_CLK_DIR_0 + ENET1_TX_CLK output driver is disabled when configured for ALT1 + 0 + + + ENET1_TX_CLK_DIR_1 + ENET1_TX_CLK output driver is enabled when configured for ALT1 + 0x1 + + + + + ENET2_TX_CLK_DIR + ENET2_TX_CLK data direction control when anatop. ENET_REF_CLK2 is selected (ALT1) + 0x12 + 1 + read-write + + + ENET2_TX_CLK_DIR_0 + ENET2_TX_CLK output driver is disabled when configured for ALT1 + 0 + + + ENET2_TX_CLK_DIR_1 + ENET2_TX_CLK output driver is enabled when configured for ALT1 + 0x1 + + + + + SAI1_MCLK_DIR + LCD_DATA00 data direction control when sai1.MCLK is selected (ALT8) + 0x13 + 1 + read-write + + + SAI1_MCLK_DIR_0 + LCD_DATA00 output driver is disabled when configured for ALT8 + 0 + + + SAI1_MCLK_DIR_1 + LCD_DATA00 output driver is enabled when configured for ALT8 + 0x1 + + + + + SAI2_MCLK_DIR + SD1_CLK data direction control when sai2.MCLK is selected (ALT2) + 0x14 + 1 + read-write + + + SAI2_MCLK_DIR_0 + SD1_CLK output driver is disabled when configured for ALT2 + 0 + + + SAI2_MCLK_DIR_1 + SD1_CLK output driver is enabled when configured for ALT2 + 0x1 + + + + + SAI3_MCLK_DIR + LCD_CLK data direction control when sai3.MCLK is selected (ALT3) + 0x15 + 1 + read-write + + + SAI3_MCLK_DIR_0 + LCD_CLK output driver is disabled when configured for ALT3 + 0 + + + SAI3_MCLK_DIR_1 + LCD_CLK output driver is enabled when configured for ALT3 + 0x1 + + + + + EXC_MON + Exclusive monitor response select of illegal command + 0x16 + 1 + read-write + + + EXC_MON_0 + OKAY response + 0 + + + EXC_MON_1 + SLVError response (default) + 0x1 + + + + + TZASC1_BOOT_LOCK + TZASC-1 secure boot lock + 0x17 + 1 + read-write + + + TZASC1_BOOT_LOCK_0 + secure boot lock is disabled + 0 + + + TZASC1_BOOT_LOCK_1 + secure boot lock is enabled + 0x1 + + + + + ARMA7_CLK_APB_DBG_EN + ARM A7 platform APB clock enable + 0x18 + 1 + read-write + + + ARMA7_CLK_APB_DBG_EN_0 + APB clock is not running (gated) + 0 + + + ARMA7_CLK_APB_DBG_EN_1 + APB clock is running (enabled) + 0x1 + + + + + ARMA7_CLK_ATB_EN + ARM A7 platform ATB clock enable + 0x19 + 1 + read-write + + + ARMA7_CLK_ATB_EN_0 + ATB clock is not running (gated) + 0 + + + ARMA7_CLK_ATB_EN_1 + ATB clock is running (enabled) + 0x1 + + + + + ARMA7_CLK_AHB_EN + ARM A7 platform AHB clock enable + 0x1A + 1 + read-write + + + ARMA7_CLK_AHB_EN_0 + AHB clock is not running (gated) + 0 + + + ARMA7_CLK_AHB_EN_1 + AHB clock is running (enabled) + 0x1 + + + + + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PXP_MEM_EN_POWERSAVING + enable power saving features on PXP memory + 0 + 1 + read-write + + + PXP_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + PXP_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + 0x1 + + + + + PXP_MEM_SHUTDOWN + set to bring memory to shutdown state (most power saving state, Shut Down periphery and core, no memory retention) + 0x1 + 1 + read-write + + + PXP_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 0x2 + 1 + read-write + + + PXP_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + PXP_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + PXP_MEM_LIGHTSLEEP + set to bring memory to light sleep state (Low leakage mode, maintain memory contents, no change to memory output) + 0x3 + 1 + read-write + + + LCDIF1_MEM_EN_POWERSAVING + enable power saving features on LCDIF memory + 0x4 + 1 + read-write + + + LCDIF1_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + LCDIF1_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + 0x1 + + + + + LCDIF1_MEM_SHUTDOWN + set to bring memory to shutdown state (most power saving state, Shut Down periphery and core, no memory retention) + 0x5 + 1 + read-write + + + LCDIF1_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 0x6 + 1 + read-write + + + LCDIF1_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + LCDIF1_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + LCDIF1_MEM_LIGHTSLEEP + set to bring memory to light sleep state (Low leakage mode, maintain memory contents, no change to memory output) + 0x7 + 1 + read-write + + + LCDIF2_MEM_EN_POWERSAVING + enable power saving features on LCDIF memory + 0x8 + 1 + read-write + + + LCDIF2_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + LCDIF2_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + 0x1 + + + + + LCDIF2_MEM_SHUTDOWN + set to bring memory to shutdown state (most power saving state, Shut Down periphery and core, no memory retention) + 0x9 + 1 + read-write + + + LCDIF2_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 0xA + 1 + read-write + + + LCDIF2_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + LCDIF2_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + LCDIF2_MEM_LIGHTSLEEP + set to bring memory to light sleep state (Low leakage mode, maintain memory contents, no change to memory output) + 0xB + 1 + read-write + + + L2_MEM_EN_POWERSAVING + enable power saving features on L2 memory + 0xC + 1 + read-write + + + L2_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + L2_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + 0x1 + + + + + L2_MEM_SHUTDOWN + set to bring memory to shutdown state (most power saving state, Shut Down periphery and core, no memory retention) + 0xD + 1 + read-write + + + L2_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 0xE + 1 + read-write + + + L2_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + L2_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + L2_MEM_LIGHTSLEEP + set to bring memory to light sleep state (Low leakage mode, maintain memory contents, no change to memory output) + 0xF + 1 + read-write + + + MQS_CLK_DIV + Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. + 0x10 + 8 + read-write + + + MQS_CLK_DIV_0 + mclk frequency = hmclk frequency + 0 + + + MQS_CLK_DIV_1 + mclk frequency = 1/2 * hmclk frequency + 0x1 + + + MQS_CLK_DIV_2 + mclk frequency = 1/3 * hmclk frequency + 0x2 + + + MQS_CLK_DIV_255 + mclk frequency = 1/256 * hmclk frequency + 0xFF + + + + + MQS_SW_RST + MQS software reset. + 0x18 + 1 + read-write + + + MQS_SW_RST_0 + Exit software reset for MQS + 0 + + + MQS_SW_RST_1 + Enable software reset for MQS + 0x1 + + + + + MQS_EN + MQS enable. + 0x19 + 1 + read-write + + + MQS_EN_0 + Disable MQS + 0 + + + MQS_EN_1 + Enable MQS + 0x1 + + + + + MQS_OVERSAMPLE + Used to control the PWM oversampling rate compared with mclk. + 0x1A + 1 + read-write + + + MQS_OVERSAMPLE_0 + 32 + 0 + + + MQS_OVERSAMPLE_1 + 64 + 0x1 + + + + + DRAM_RESET_BYPASS + DRAM Reset Bypass Select + 0x1B + 1 + read-write + + + DRAM_RESET_BYPASS_0 + DRAM reset driven by MMDC PHY Controller + 0 + + + DRAM_RESET_BYPASS_1 + DRAM reset driven by GPR2 register bit [28] + 0x1 + + + + + DRAM_RESET + DRAM Reset Value + 0x1C + 1 + read-write + + + DRAM_RESET_0 + Drive DRAM reset with 0 + 0 + + + DRAM_RESET_1 + Drive DRAM reset with 1 + 0x1 + + + + + DRAM_CKE0 + CKE0 Bypass Value + 0x1D + 1 + read-write + + + DRAM_CKE0_0 + Drive CKE0 with 0 + 0 + + + DRAM_CKE0_1 + Drive CKE0 with 1 + 0x1 + + + + + DRAM_CKE1 + CKE1 Bypass Value + 0x1E + 1 + read-write + + + DRAM_CKE1_0 + Drive CKE1 with 0 + 0 + + + DRAM_CKE1_1 + Drive CKE1 with 1 + 0x1 + + + + + DRAM_CKE_BYPASS + DRAM CKE Bypass Select + 0x1F + 1 + read-write + + + DRAM_CKE_BYPASS_0 + DRAM CKE1, CKE0 driven by MMDC PHY Controller + 0 + + + DRAM_CKE_BYPASS_1 + DRAM CKE1, CKE0 driven by GPR2 register bits [30:29] + 0x1 + + + + + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0xFFF + 0xFFFFFFFF + + + OCRAM_CTL + OCRAM_CTL[3] write address pipeline control bit + 0 + 4 + read-write + + + OCRAM_CTL_0 + read data pipeline is disabled + 0 + + + OCRAM_CTL_1 + read data pipeline is enabled + 0x1 + + + + + CORE_DBG_ACK_EN + Mask control of Core debug acknowledge to global debug acknowledge + 0xD + 1 + read-write + + + CORE_DBG_ACK_EN_0 + Core debug acknowledge is part of global acknowledge. + 0 + + + CORE_DBG_ACK_EN_1 + Core debug acknowledge is masked by this bit, and it is not part of global acknowledge. + 0x1 + + + + + OCRAM_STATUS + This field shows the OCRAM pipeline settings status, controlled by OCRAM_CTL[24:21] bits respectively + 0x10 + 4 + read-only + + + OCRAM_STATUS_0 + read data pipeline configuration valid + 0 + + + OCRAM_STATUS_1 + read data pipeline control bit changed + 0x1 + + + + + + + GPR4 + GPR4 General Purpose Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDMA_STOP_REQ + SDMA stop request. + 0 + 1 + read-only + + + SDMA_STOP_REQ_0 + stop request off + 0 + + + SDMA_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN1_STOP_REQ + CAN1 stop request. + 0x1 + 1 + read-only + + + CAN1_STOP_REQ_0 + stop request off + 0 + + + CAN1_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN2_STOP_REQ + CAN2 stop request. + 0x2 + 1 + read-only + + + CAN2_STOP_REQ_0 + stop request off + 0 + + + CAN2_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET1_STOP_REQ + ENET1 stop request. + 0x3 + 1 + read-only + + + ENET1_STOP_REQ_0 + stop request off + 0 + + + ENET1_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET2_STOP_REQ + ENET2 stop request. + 0x4 + 1 + read-only + + + ENET2_STOP_REQ_0 + stop request off + 0 + + + ENET2_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI1_STOP_REQ + SAI1 stop request. + 0x5 + 1 + read-only + + + SAI1_STOP_REQ_0 + stop request off + 0 + + + SAI1_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI2_STOP_REQ + SAI2 stop request. + 0x6 + 1 + read-only + + + SAI2_STOP_REQ_0 + stop request off + 0 + + + SAI2_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI3_STOP_REQ + SAI3 stop request. + 0x7 + 1 + read-only + + + SAI3_STOP_REQ_0 + stop request off + 0 + + + SAI3_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET_IPG_CLK_S_EN + ENET ipg_clk_s clock gating enable + 0x8 + 1 + read-write + + + ENET_IPG_CLK_S_EN_0 + ipg_clk_s is gated when there's no IPS access + 0 + + + ENET_IPG_CLK_S_EN_1 + ipg_clk_s is always on + 0x1 + + + + + SDMA_STOP_ACK + SDMA stop acknowledge. This is a status (read-only) bit + 0x10 + 1 + read-only + + + SDMA_STOP_ACK_0 + SDMA stop acknowledge is not asserted + 0 + + + SDMA_STOP_ACK_1 + SDMA stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + CAN1_STOP_ACK + CAN1 stop acknowledge. This is a status (read-only) bit + 0x11 + 1 + read-only + + + CAN1_STOP_ACK_0 + CAN1 stop acknowledge is not asserted + 0 + + + CAN1_STOP_ACK_1 + CAN1 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + CAN2_STOP_ACK + CAN2 stop acknowledge. This is a status (read-only) bit + 0x12 + 1 + read-only + + + CAN2_STOP_ACK_0 + CAN2 stop acknowledge is not asserted + 0 + + + CAN2_STOP_ACK_1 + CAN2 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + ENET1_STOP_ACK + ENET1 stop acknowledge. This is a status (read-only) bit + 0x13 + 1 + read-only + + + ENET1_STOP_ACK_0 + ENET1 stop acknowledge is not asserted + 0 + + + ENET1_STOP_ACK_1 + ENET1 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + ENET2_STOP_ACK + ENET2 stop acknowledge. This is a status (read-only) bit + 0x14 + 1 + read-only + + + ENET2_STOP_ACK_0 + ENET2 stop acknowledge is not asserted + 0 + + + ENET2_STOP_ACK_1 + ENET2 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + SAI1_STOP_ACK + SAI1 stop acknowledge. This is a status (read-only) bit + 0x15 + 1 + read-only + + + SAI1_STOP_ACK_0 + SAI1 stop acknowledge is not asserted + 0 + + + SAI1_STOP_ACK_1 + SAI1 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + SAI2_STOP_ACK + SAI2 stop acknowledge. This is a status (read-only) bit + 0x16 + 1 + read-only + + + SAI2_STOP_ACK_0 + SAI2 stop acknowledge is not asserted + 0 + + + SAI2_STOP_ACK_1 + SAI2 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + SAI3_STOP_ACK + SAI3 stop acknowledge. This is a status (read-only) bit + 0x17 + 1 + read-only + + + SAI3_STOP_ACK_0 + SAI3 stop acknowledge is not asserted + 0 + + + SAI3_STOP_ACK_1 + SAI3 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + ARM_WFI + ARM A7 WFI event out indicating on WFI state of the cores (these are status, read only bits) + 0x1E + 1 + read-only + + + ARM_WFI_0 + ARM Core[GPR5-index] is not in WFI mode + 0 + + + ARM_WFI_1 + ARM Core[GPR5-index] is in WFI mode + 0x1 + + + + + ARM_WFE + ARM A7 WFE event out indication on WFE state of the cores (these are status, read only bits) + 0x1F + 1 + read-only + + + ARM_WFE_0 + ARM Core[GPR5-index - 4] is not in WFE mode + 0 + + + ARM_WFE_1 + ARM Core[GPR5-index - 4] is in WFE mode + 0x1 + + + + + + + GPR5 + GPR5 General Purpose Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDOG1_MASK + WDOG1 Timeout Mask + 0x6 + 1 + read-write + + + WDOG1_MASK_0 + WDOG1 Timeout behaves normally + 0 + + + WDOG1_MASK_1 + WDOG1 Timeout is masked + 0x1 + + + + + WDOG2_MASK + WDOG2 Timeout Mask + 0x7 + 1 + read-write + + + WDOG2_MASK_0 + WDOG2 Timeout behaves normally + 0 + + + WDOG2_MASK_1 + WDOG2 Timeout is masked + 0x1 + + + + + WDOG3_MASK + WDOG3 Timeout Mask + 0x14 + 1 + read-write + + + WDOG3_MASK_0 + WDOG3 Timeout behaves normally + 0 + + + WDOG3_MASK_1 + WDOG3 Timeout is masked + 0x1 + + + + + GPT2_CAPIN1_SEL + GPT2 input capture channel 1 source select + 0x17 + 1 + read-write + + + GPT2_CAPIN1_SEL_0 + source from pad + 0 + + + GPT2_CAPIN1_SEL_1 + source from enet1.ipp_do_mac0_timer[3] + 0x1 + + + + + GPT2_CAPIN2_SEL + GPT2 input capture channel 2 source select + 0x18 + 1 + read-write + + + GPT2_CAPIN2_SEL_0 + source from pad + 0 + + + GPT2_CAPIN2_SEL_1 + source from enet2.ipp_do_mac0_timer[3] + 0x1 + + + + + ENET1_EVENT3IN_SEL + ENET1 input timer event3 source select + 0x19 + 1 + read-write + + + ENET1_EVENT3IN_SEL_0 + event3 source input from pad + 0 + + + ENET1_EVENT3IN_SEL_1 + event3 source input from gpt2.ipp_do_cmpout1 + 0x1 + + + + + ENET2_EVENT3IN_SEL + ENET2 input timer event3 source select + 0x1A + 1 + read-write + + + ENET2_EVENT3IN_SEL_0 + event3 source input from pad + 0 + + + ENET2_EVENT3IN_SEL_1 + event3 source input from gpt2.ipp_do_cmpout2 + 0x1 + + + + + VREF_1M_CLK_GPT1 + GPT1 1 MHz clock source select + 0x1C + 1 + read-write + + + VREF_1M_CLK_GPT1_0 + GPT1 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT1_1 + GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + VREF_1M_CLK_GPT2 + GPT2 1 MHz clock source select + 0x1D + 1 + read-write + + + VREF_1M_CLK_GPT2_0 + GPT2 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT2_1 + GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + REF_1M_CLK_EPIT1 + EPIT1 1 MHz clock source select + 0x1E + 1 + read-write + + + REF_1M_CLK_EPIT1_0 + EPIT1 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + REF_1M_CLK_EPIT1_1 + EPIT1 ipg_clk highfreq driven by anatop 1 MHz clock + 0x1 + + + + + REF_1M_CLK_EPIT2 + EPIT2 1 MHz clock source select + 0x1F + 1 + read-write + + + REF_1M_CLK_EPIT2_0 + EPIT2 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + REF_1M_CLK_EPIT2_1 + EPIT2 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + + + GPR9 + GPR9 General Purpose Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + TZASC1_BYP + TZASC-1 BYPASS MUX control + 0 + 1 + read-only + + + TZASC1_BYP_0 + The TZASC-1 is bypassed and the transactions to DDR are not being checked. + 0 + + + TZASC1_BYP_1 + The TZASC-1 is not bypassed and the transactions to DDR are being monitored / checked. + 0x1 + + + + + + + GPR10 + GPR10 General Purpose Register + 0x28 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + DBG_EN + ARM non secure (non-invasive) debug enable + 0 + 1 + read-write + + + DBG_EN_0 + Debug turned off. + 0 + + + DBG_EN_1 + Debug enabled (default). + 0x1 + + + + + DBG_CLK_EN + ARM Debug clock enable + 0x1 + 1 + read-write + + + DBG_CLK_EN_0 + Debug turned off. + 0 + + + DBG_CLK_EN_1 + Debug enabled (default). + 0x1 + + + + + SEC_ERR_RESP + Security error response enable for all security gaskets (on both AHB and AXI busses) + 0x2 + 1 + read-write + + + SEC_ERR_RESP_0 + OKEY response + 0 + + + SEC_ERR_RESP_1 + SLVError (default) + 0x1 + + + + + OCRAM_TZ_EN + OCRAM TrustZone (TZ) enable. + 0xA + 1 + read-write + + + OCRAM_TZ_EN_0 + The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + 0 + + + OCRAM_TZ_EN_1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + 0x1 + + + + + OCRAM_TZ_ADDR + OCRAM TrustZone (TZ) start address + 0xB + 5 + read-write + + + + + GPR14 + GPR14 General Purpose Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General purpose bits + 0x2 + 30 + read-write + + + + + + + SDMAARM + SDMA + SDMAARM + SDMAARM_ + 0x20EC000 + + 0 + 0x2C0 + registers + + + SDMA + 34 + + + + MC0PTR + ARM platform Channel 0 Pointer + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MC0PTR + Channel 0 Pointer contains the 32-bit address, in ARM platform memory, of channel 0 control block (the boot channel) + 0 + 32 + read-write + + + + + INTR + Channel Interrupts + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HI + The ARM platform Interrupts register contains the 32 HI[i] bits + 0 + 32 + read-write + oneToClear + + + + + STOP_STAT + Channel Stop/Channel Status + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HE + This 32-bit register gives access to the ARM platform Enable bits + 0 + 32 + read-write + oneToClear + + + + + HSTART + Channel Start + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + HSTART_HE + The HSTART_HE registers are 32 bits wide with one bit for every channel + 0 + 32 + read-write + oneToClear + + + + + EVTOVR + Channel Event Override + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + EO + The Channel Event Override register contains the 32 EO[i] bits + 0 + 32 + read-write + + + + + DSPOVR + Channel BP Override + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DO + This register is reserved + 0 + 32 + read-write + + + DO_0 + - Reserved + 0 + + + DO_1 + - Reset value. + 0x1 + + + + + + + HOSTOVR + Channel ARM platform Override + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + HO + The Channel ARM platform Override register contains the 32 HO[i] bits + 0 + 32 + read-write + + + + + EVTPEND + Channel Event Pending + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + EP + The Channel Event Pending register contains the 32 EP[i] bits + 0 + 32 + read-write + oneToClear + + + + + RESET + Reset Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESET + When set, this bit causes the SDMA to be held in a software reset + 0 + 1 + read-only + + + RESCHED + When set, this bit forces the SDMA to reschedule as if a script had executed a done instruction + 0x1 + 1 + read-only + + + + + EVTERR + DMA Request Error Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + CHNERR + This register is used by the SDMA to warn the ARM platform when an incoming DMA request was detected and it triggers a channel that is already pending or being serviced + 0 + 32 + read-only + + + + + INTRMASK + Channel ARM platform Interrupt Mask + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HIMASK + The Interrupt Mask Register contains 32 interrupt generation mask bits + 0 + 32 + read-write + + + + + PSW + Schedule Status + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + CCR + The Current Channel Register indicates the number of the channel that is being executed by the SDMA + 0 + 4 + read-only + + + CCP + The Current Channel Priority indicates the priority of the current active channel + 0x4 + 4 + read-only + + + CCP_0 + No running channel + 0 + + + CCP_1 + Active channel priority + 0x1 + + + + + NCR + The Next Channel Register indicates the number of the next scheduled pending channel with the highest priority + 0x8 + 5 + read-only + + + NCP + The Next Channel Priority gives the next pending channel priority + 0xD + 3 + read-only + + + NCP_0 + No running channel + 0 + + + NCP_1 + Active channel priority + 0x1 + + + + + + + EVTERRDBG + DMA Request Error Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + CHNERR + This register is the same as EVTERR, except reading it does not clear its contents + 0 + 32 + read-only + + + + + CONFIG + Configuration Register + 0x38 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + CSM + Selects the Context Switch Mode + 0 + 2 + read-write + + + CSM_0 + static + 0 + + + CSM_1 + dynamic low power + 0x1 + + + CSM_2 + dynamic with no loop + 0x2 + + + CSM_3 + dynamic + 0x3 + + + + + ACR + ARM platform DMA / SDMA Core Clock Ratio + 0x4 + 1 + read-write + + + ACR_0 + ARM platform DMA interface frequency equals twice core frequency + 0 + + + ACR_1 + ARM platform DMA interface frequency equals core frequency + 0x1 + + + + + RTDOBS + Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce power consumption + 0xB + 1 + read-write + + + RTDOBS_0 + RTD pins disabled + 0 + + + RTDOBS_1 + RTD pins enabled + 0x1 + + + + + DSPDMA + This bit's function is reserved and should be configured as zero. + 0xC + 1 + read-write + + + DSPDMA_0 + - Reset Value + 0 + + + DSPDMA_1 + - Reserved + 0x1 + + + + + + + SDMA_LOCK + SDMA LOCK + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK + The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero scripts and through the OnCE interface under ARM platform control + 0 + 1 + read-write + + + LOCK_0 + LOCK disengaged. + 0 + + + LOCK_1 + LOCK enabled. + 0x1 + + + + + SRESET_LOCK_CLR + The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by writing to the RESET register + 0x1 + 1 + read-write + + + SRESET_LOCK_CLR_0 + Software Reset does not clear the LOCK bit. + 0 + + + SRESET_LOCK_CLR_1 + Software Reset clears the LOCK bit. + 0x1 + + + + + + + ONCE_ENB + OnCE Enable + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENB + The OnCE Enable register selects the OnCE control source: When cleared (0), the OnCE registers are accessed through the JTAG interface; when set (1), the OnCE registers may be accessed by the ARM platform through the addresses described, as follows + 0 + 1 + read-write + + + + + ONCE_DATA + OnCE Data Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data register of the OnCE JTAG controller + 0 + 32 + read-write + + + + + ONCE_INSTR + OnCE Instruction Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + INSTR + Instruction register of the OnCE JTAG controller + 0 + 16 + read-write + + + + + ONCE_STAT + OnCE Status Register + 0x4C + 32 + read-only + 0xE000 + 0xFFFFFFFF + + + ECDR + Event Cell Debug Request + 0 + 3 + read-only + + + ECDR_0 + 1 matched addra_cond + 0 + + + ECDR_1 + 1 matched addrb_cond + 0x1 + + + ECDR_2 + 1 matched data_cond + 0x2 + + + + + MST + This flag is raised when the OnCE is controlled from the ARM platform peripheral interface. + 0x7 + 1 + read-only + + + MST_0 + The JTAG interface controls the OnCE. + 0 + + + MST_1 + The ARM platform peripheral interface controls the OnCE. + 0x1 + + + + + SWB + This flag is raised when the SDMA has entered debug mode after a software breakpoint. + 0x8 + 1 + read-only + + + ODR + This flag is raised when the SDMA has entered debug mode after a OnCE debug request. + 0x9 + 1 + read-only + + + EDR + This flag is raised when the SDMA has entered debug mode after an external debug request. + 0xA + 1 + read-only + + + RCV + After each write access to the real time buffer (RTB), the RCV bit is set + 0xB + 1 + read-only + + + PST + The Processor Status bits reflect the state of the SDMA RISC engine + 0xC + 4 + read-only + + + PST_0 + Program + 0 + + + PST_1 + Data + 0x1 + + + PST_2 + Change of Flow + 0x2 + + + PST_3 + Change of Flow in Loop + 0x3 + + + PST_4 + Debug + 0x4 + + + PST_5 + Functional Unit + 0x5 + + + PST_6 + Sleep + 0x6 + + + PST_7 + Save + 0x7 + + + PST_8 + Program in Sleep + 0x8 + + + PST_9 + Data in Sleep + 0x9 + + + PST_12 + Debug in Sleep + 0xC + + + PST_13 + Functional Unit in Sleep + 0xD + + + PST_14 + Sleep after Reset + 0xE + + + PST_15 + Restore + 0xF + + + + + + + ONCE_CMD + OnCE Command Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD + Writing to this register will cause the OnCE to execute the command that is written + 0 + 4 + read-write + + + CMD_0 + rstatus + 0 + + + CMD_1 + dmov + 0x1 + + + CMD_2 + exec_once + 0x2 + + + CMD_3 + run_core + 0x3 + + + CMD_4 + exec_core + 0x4 + + + CMD_5 + debug_rqst + 0x5 + + + CMD_6 + rbuffer + 0x6 + + + + + + + ILLINSTADDR + Illegal Instruction Trap Address + 0x58 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ILLINSTADDR + The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal instruction is executed + 0 + 14 + read-write + + + + + CHN0ADDR + Channel 0 Boot Address + 0x5C + 32 + read-write + 0x50 + 0xFFFFFFFF + + + CHN0ADDR + This 14-bit register is used by the boot code of the SDMA + 0 + 14 + read-write + + + SMSZ + The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel context + 0xE + 1 + read-write + + + SMSZ_0 + 24 words per context + 0 + + + SMSZ_1 + 32 words per context + 0x1 + + + + + + + EVT_MIRROR + DMA Requests + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVENTS + This register reflects the DMA requests received by the SDMA for events 31-0 + 0 + 32 + read-only + + + EVENTS_0 + DMA request event not pending + 0 + + + EVENTS_1 + DMA request event pending + 0x1 + + + + + + + EVT_MIRROR2 + DMA Requests 2 + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVENTS + This register reflects the DMA requests received by the SDMA for events 47-32 + 0 + 16 + read-only + + + EVENTS_0 + - DMA request event not pending + 0 + + + + + + + XTRIG_CONF1 + Cross-Trigger Events Configuration Register 1 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM0 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0 + 6 + read-write + + + CNF0 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x6 + 1 + read-write + + + CNF0_0 + channel + 0 + + + CNF0_1 + DMA request + 0x1 + + + + + NUM1 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x8 + 6 + read-write + + + CNF1 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0xE + 1 + read-write + + + CNF1_0 + channel + 0 + + + CNF1_1 + DMA request + 0x1 + + + + + NUM2 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x10 + 6 + read-write + + + CNF2 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x16 + 1 + read-write + + + CNF2_0 + channel + 0 + + + CNF2_1 + DMA request + 0x1 + + + + + NUM3 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x18 + 6 + read-write + + + CNF3 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x1E + 1 + read-write + + + CNF3_0 + channel + 0 + + + CNF3_1 + DMA request + 0x1 + + + + + + + XTRIG_CONF2 + Cross-Trigger Events Configuration Register 2 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM4 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0 + 6 + read-write + + + CNF4 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x6 + 1 + read-write + + + CNF4_0 + channel + 0 + + + CNF4_1 + DMA request + 0x1 + + + + + NUM5 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x8 + 6 + read-write + + + CNF5 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0xE + 1 + read-write + + + CNF5_0 + channel + 0 + + + CNF5_1 + DMA request + 0x1 + + + + + NUM6 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x10 + 6 + read-write + + + CNF6 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x16 + 1 + read-write + + + CNF6_0 + channel + 0 + + + CNF6_1 + DMA request + 0x1 + + + + + NUM7 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x18 + 6 + read-write + + + CNF7 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x1E + 1 + read-write + + + CNF7_0 + channel + 0 + + + CNF7_1 + DMA request + 0x1 + + + + + + + 32 + 0x4 + SDMA_CHNPRI%s + Channel Priority Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHNPRIn + This contains the priority of channel number n + 0 + 3 + read-write + + + + + 48 + 0x4 + CHNENBL%s + Channel Enable RAM + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENBLn + This 32-bit value selects the channels that are triggered by the DMA request number n + 0 + 32 + read-write + + + + + + + USB1 + USB + USB + USB1_ + 0x2184000 + USB + + 0 + 0x1E0 + registers + + + USB_OTG1 + 75 + + + + ID + Identification register + 0 + 32 + read-only + 0xE4A1FA05 + 0xFFFFFFFF + + + ID + Configuration number + 0 + 6 + read-only + + + NID + Complement version of ID + 0x8 + 6 + read-only + + + REVISION + Revision number of the controller core. + 0x10 + 8 + read-only + + + + + HWGENERAL + Hardware General + 0x4 + 32 + read-only + 0x35 + 0xFFFFFFFF + + + PHYW + Data width of the transciever connected to the controller core. PHYW bit reset value is + 0x4 + 2 + read-only + + + PHYW_0 + 8 bit wide data bus Software non-programmable + 0 + + + PHYW_1 + 16 bit wide data bus Software non-programmable + 0x1 + + + PHYW_2 + Reset to 8 bit wide data bus Software programmable + 0x2 + + + PHYW_3 + Reset to 16 bit wide data bus Software programmable + 0x3 + + + + + PHYM + Transciever type + 0x6 + 3 + read-only + + + PHYM_0 + UTMI/UMTI+ + 0 + + + PHYM_1 + ULPI DDR + 0x1 + + + PHYM_2 + ULPI + 0x2 + + + PHYM_3 + Serial Only + 0x3 + + + PHYM_4 + Software programmable - reset to UTMI/UTMI+ + 0x4 + + + PHYM_5 + Software programmable - reset to ULPI DDR + 0x5 + + + PHYM_6 + Software programmable - reset to ULPI + 0x6 + + + PHYM_7 + Software programmable - reset to Serial + 0x7 + + + + + SM + Serial interface mode capability + 0x9 + 2 + read-only + + + SM_0 + No Serial Engine, always use parallel signalling. + 0 + + + SM_1 + Serial Engine present, always use serial signalling for FS/LS. + 0x1 + + + SM_2 + Software programmable - Reset to use parallel signalling for FS/LS + 0x2 + + + SM_3 + Software programmable - Reset to use serial signalling for FS/LS + 0x3 + + + + + + + HWHOST + Host Hardware Parameters + 0x8 + 32 + read-only + 0x10020001 + 0xFFFFFFFF + + + HC + Host Capable. Indicating whether host operation mode is supported or not. + 0 + 1 + read-only + + + HC_0 + Not supported + 0 + + + HC_1 + Supported + 0x1 + + + + + NPORT + The Nmber of downstream ports supported by the host controller is (NPORT+1) + 0x1 + 3 + read-only + + + + + HWDEVICE + Device Hardware Parameters + 0xC + 32 + read-only + 0x11 + 0xFFFFFFFF + + + DC + Device Capable. Indicating whether device operation mode is supported or not. + 0 + 1 + read-only + + + DC_0 + Not supported + 0 + + + DC_1 + Supported + 0x1 + + + + + DEVEP + Device Endpoint Number + 0x1 + 5 + read-only + + + + + HWTXBUF + TX Buffer Hardware Parameters + 0x10 + 32 + read-only + 0x80080B08 + 0xFFFFFFFF + + + TXBURST + Default burst size for memory to TX buffer transfer + 0 + 8 + read-only + + + TXCHANADD + TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes + 0x10 + 8 + read-only + + + + + HWRXBUF + RX Buffer Hardware Parameters + 0x14 + 32 + read-only + 0x808 + 0xFFFFFFFF + + + RXBURST + Default burst size for memory to RX buffer transfer + 0 + 8 + read-only + + + RXADD + Buffer total size for all receive endpoints is (2^RXADD) + 0x8 + 8 + read-only + + + + + GPTIMER0LD + General Purpose Timer #0 Load + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again + 0x18 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 0x1E + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 0x1F + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + GPTIMER1LD + General Purpose Timer #1 Load + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software + 0x18 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 0x1E + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in USB_n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 0x1F + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + SBUSCFG + System Bus Config + 0x90 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + AHBBRST + AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority) + 0 + 3 + read-write + + + AHBBRST_0 + Incremental burst of unspecified length only + 0 + + + AHBBRST_1 + INCR4 burst, then single transfer + 0x1 + + + AHBBRST_2 + INCR8 burst, INCR4 burst, then single transfer + 0x2 + + + AHBBRST_3 + INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + 0x3 + + + AHBBRST_5 + INCR4 burst, then incremental burst of unspecified length + 0x5 + + + AHBBRST_6 + INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x6 + + + AHBBRST_7 + INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x7 + + + + + + + CAPLENGTH + Capability Registers Length + 0x100 + 8 + read-only + 0x40 + 0xFF + + + CAPLENGTH + These bits are used as an offset to add to register base to find the beginning of the Operational Register + 0 + 8 + read-only + + + + + HCIVERSION + Host Controller Interface Version + 0x102 + 16 + read-only + 0x100 + 0xFFFF + + + HCIVERSION + Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0. + 0 + 16 + read-only + + + + + HCSPARAMS + Host Controller Structural Parameters + 0x104 + 32 + read-only + 0x10011 + 0xFFFFFFFF + + + N_PORTS + Number of downstream ports + 0 + 4 + read-only + + + PPC + Port Power Control This field indicates whether the host controller implementation includes port power control + 0x4 + 1 + read-only + + + N_PCC + Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller + 0x8 + 4 + read-only + + + N_CC + Number of Companion Controller (N_CC) + 0xC + 4 + read-only + + + N_CC_0 + There is no internal Companion Controller and port-ownership hand-off is not supported. + 0 + + + N_CC_1 + There are internal companion controller(s) and port-ownership hand-offs is supported. + 0x1 + + + + + PI + Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control + 0x10 + 1 + read-only + + + N_PTT + Number of Ports per Transaction Translator (N_PTT) + 0x14 + 4 + read-only + + + N_TT + Number of Transaction Translators (N_TT) + 0x18 + 4 + read-only + + + + + HCCPARAMS + Host Controller Capability Parameters + 0x108 + 32 + read-only + 0x6 + 0xFFFFFFFF + + + ADC + 64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported + 0 + 1 + read-only + + + PFL + Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller + 0x1 + 1 + read-only + + + ASP + Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule + 0x2 + 1 + read-only + + + IST + Isochronous Scheduling Threshold + 0x4 + 4 + read-only + + + EECP + EHCI Extended Capabilities Pointer + 0x8 + 8 + read-only + + + + + DCIVERSION + Device Controller Interface Version + 0x120 + 16 + read-only + 0x1 + 0xFFFF + + + DCIVERSION + Device Controller Interface Version Number Default value is '01h', which means rev0.1. + 0 + 16 + read-only + + + + + DCCPARAMS + Device Controller Capability Parameters + 0x124 + 32 + read-only + 0x188 + 0xFFFFFFFF + + + DEN + Device Endpoint Number This field indicates the number of endpoints built into the device controller + 0 + 5 + read-only + + + DC + Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device. + 0x7 + 1 + read-only + + + HC + Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2 + 0x8 + 1 + read-only + + + + + USBCMD + USB Command Register + 0x140 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + RS + Run/Stop (RS) - Read/Write + 0 + 1 + read-write + + + RST + Controller Reset (RESET) - Read/Write + 0x1 + 1 + read-write + + + FS_1 + See description at bit 15 + 0x2 + 2 + read-write + + + PSE + Periodic Schedule Enable- Read/Write + 0x4 + 1 + read-write + + + PSE_0 + Do not process the Periodic Schedule + 0 + + + PSE_1 + Use the PERIODICLISTBASE register to access the Periodic Schedule. + 0x1 + + + + + ASE + Asynchronous Schedule Enable - Read/Write + 0x5 + 1 + read-write + + + ASE_0 + Do not process the Asynchronous Schedule. + 0 + + + ASE_1 + Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 0x1 + + + + + IAA + Interrupt on Async Advance Doorbell - Read/Write + 0x6 + 1 + read-write + + + ASP + Asynchronous Schedule Park Mode Count - Read/Write + 0x8 + 2 + read-write + + + ASPE + Asynchronous Schedule Park Mode Enable - Read/Write + 0xB + 1 + read-write + + + ATDTW + Add dTD TripWire - Read/Write + 0xC + 1 + read-write + + + SUTW + Setup TripWire - Read/Write + 0xD + 1 + read-write + + + FS_2 + See also bits 3-2 Frame List Size - (Read/Write or Read Only) + 0xF + 1 + read-write + + + FS_2_0 + 1024 elements (4096 bytes) Default value + 0 + + + FS_2_1 + 512 elements (2048 bytes) + 0x1 + + + + + ITC + Interrupt Threshold Control -Read/Write + 0x10 + 8 + read-write + + + ITC_0 + Immediate (no threshold) + 0 + + + ITC_1 + 1 micro-frame + 0x1 + + + ITC_2 + 2 micro-frames + 0x2 + + + ITC_4 + 4 micro-frames + 0x4 + + + ITC_8 + 8 micro-frames + 0x8 + + + ITC_16 + 16 micro-frames + 0x10 + + + ITC_32 + 32 micro-frames + 0x20 + + + ITC_64 + 64 micro-frames + 0x40 + + + + + + + USBSTS + USB Status Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + UI + USB Interrupt (USBINT) - R/WC + 0 + 1 + read-write + + + UEI + USB Error Interrupt (USBERRINT) - R/WC + 0x1 + 1 + read-write + + + PCI + Port Change Detect - R/WC + 0x2 + 1 + read-write + + + FRI + Frame List Rollover - R/WC + 0x3 + 1 + read-write + + + SEI + System Error- R/WC + 0x4 + 1 + read-write + + + AAI + Interrupt on Async Advance - R/WC + 0x5 + 1 + read-write + + + URI + USB Reset Received - R/WC + 0x6 + 1 + read-write + + + SRI + SOF Received - R/WC + 0x7 + 1 + read-write + + + SLI + DCSuspend - R/WC + 0x8 + 1 + read-write + + + ULPII + ULPI Interrupt - R/WC + 0xA + 1 + read-write + + + HCH + HCHaIted - Read Only + 0xC + 1 + read-write + + + RCL + Reclamation - Read Only + 0xD + 1 + read-write + + + PS + Periodic Schedule Status - Read Only + 0xE + 1 + read-write + + + AS + Asynchronous Schedule Status - Read Only + 0xF + 1 + read-write + + + NAKI + NAK Interrupt Bit--RO + 0x10 + 1 + read-only + + + TI0 + General Purpose Timer Interrupt 0(GPTINT0)--R/WC + 0x18 + 1 + read-write + + + TI1 + General Purpose Timer Interrupt 1(GPTINT1)--R/WC + 0x19 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + UE + USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt + 0 + 1 + read-write + + + UEE + USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x1 + 1 + read-write + + + PCE + Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x2 + 1 + read-write + + + FRE + Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x3 + 1 + read-write + + + SEE + System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x4 + 1 + read-write + + + AAE + Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x5 + 1 + read-write + + + URE + USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x6 + 1 + read-write + + + SRE + SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x7 + 1 + read-write + + + SLE + Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt + 0x8 + 1 + read-write + + + ULPIE + ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt + 0xA + 1 + read-write + + + NAKE + NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x10 + 1 + read-write + + + UAIE + USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 0x12 + 1 + read-write + + + UPIE + USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 0x13 + 1 + read-write + + + TIE0 + General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt + 0x18 + 1 + read-write + + + TIE1 + General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt + 0x19 + 1 + read-write + + + + + FRINDEX + USB Frame Index + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRINDEX + Frame Index + 0 + 14 + read-write + + + FRINDEX_0 + (1024) 12 + 0 + + + FRINDEX_1 + (512) 11 + 0x1 + + + FRINDEX_2 + (256) 10 + 0x2 + + + FRINDEX_3 + (128) 9 + 0x3 + + + FRINDEX_4 + (64) 8 + 0x4 + + + FRINDEX_5 + (32) 7 + 0x5 + + + FRINDEX_6 + (16) 6 + 0x6 + + + FRINDEX_7 + (8) 5 + 0x7 + + + + + + + DEVICEADDR + Device Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + USBADRA + Device Address Advance + 0x18 + 1 + read-write + + + USBADR + Device Address. These bits correspond to the USB device address + 0x19 + 7 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASEADR + Base Address (Low) + 0xC + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASYBASE + Link Pointer Low (LPL) + 0x5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPBASE + Endpoint List Pointer(Low) + 0xB + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size + 0x160 + 32 + read-write + 0x808 + 0xFFFFFFFF + + + RXPBURST + Programmable RX Burst Size + 0 + 8 + read-write + + + TXPBURST + Programmable TX Burst Size + 0x8 + 9 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning + 0x164 + 32 + read-write + 0xA0000 + 0xFFFFFFFF + + + TXSCHOH + Scheduler Overhead + 0 + 8 + read-write + + + TXSCHHEALTH + Scheduler Health Counter + 0x8 + 5 + read-write + + + TXFIFOTHRES + FIFO Burst Threshold + 0x10 + 6 + read-write + + + + + ENDPTNAK + Endpoint NAK + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRN + RX Endpoint NAK - R/WC + 0 + 8 + read-write + + + EPTN + TX Endpoint NAK - R/WC + 0x10 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRNE + RX Endpoint NAK Enable - R/W + 0 + 8 + read-write + + + EPTNE + TX Endpoint NAK Enable - R/W + 0x10 + 8 + read-write + + + + + CONFIGFLAG + Configure Flag Register + 0x180 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + CF + Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller + 0 + 1 + read-only + + + CF_0 + Port routing control logic default-routes each port to an implementation dependent classic host controller. + 0 + + + CF_1 + Port routing control logic default-routes all ports to this host controller. + 0x1 + + + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + CCS + Current Connect Status-Read Only + 0 + 1 + read-only + + + CSC + Connect Status Change-R/WC + 0x1 + 1 + read-write + + + PE + Port Enabled/Disabled-Read/Write + 0x2 + 1 + read-write + + + PEC + Port Enable/Disable Change-R/WC + 0x3 + 1 + read-write + + + OCA + Over-current Active-Read Only + 0x4 + 1 + read-only + + + OCA_0 + This port does not have an over-current condition. + 0 + + + OCA_1 + This port currently has an over-current condition + 0x1 + + + + + OCC + Over-current Change-R/WC + 0x5 + 1 + read-write + + + FPR + Force Port Resume -Read/Write + 0x6 + 1 + read-write + + + SUSP + Suspend - Read/Write or Read Only + 0x7 + 1 + read-write + + + PR + Port Reset - Read/Write or Read Only + 0x8 + 1 + read-write + + + HSP + High-Speed Port - Read Only + 0x9 + 1 + read-only + + + LS + Line Status-Read Only + 0xA + 2 + read-write + + + LS_0 + SE0 + 0 + + + LS_1 + K-state + 0x1 + + + LS_2 + J-state + 0x2 + + + LS_3 + Undefined + 0x3 + + + + + PP + Port Power (PP)-Read/Write or Read Only + 0xC + 1 + read-write + + + PO + Port Owner-Read/Write + 0xD + 1 + read-write + + + PIC + Port Indicator Control - Read/Write + 0xE + 2 + read-write + + + PIC_0 + Port indicators are off + 0 + + + PIC_1 + Amber + 0x1 + + + PIC_2 + Green + 0x2 + + + PIC_3 + Undefined + 0x3 + + + + + PTC + Port Test Control - Read/Write + 0x10 + 4 + read-write + + + PTC_0 + TEST_MODE_DISABLE + 0 + + + PTC_1 + J_STATE + 0x1 + + + PTC_2 + K_STATE + 0x2 + + + PTC_3 + SE0 (host) / NAK (device) + 0x3 + + + PTC_4 + Packet + 0x4 + + + PTC_5 + FORCE_ENABLE_HS + 0x5 + + + PTC_6 + FORCE_ENABLE_FS + 0x6 + + + PTC_7 + FORCE_ENABLE_LS + 0x7 + + + + + WKCN + Wake on Connect Enable (WKCNNT_E) - Read/Write + 0x14 + 1 + read-write + + + WKDC + Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write + 0x15 + 1 + read-write + + + WKOC + Wake on Over-current Enable (WKOC_E) - Read/Write + 0x16 + 1 + read-write + + + PHCD + PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write + 0x17 + 1 + read-write + + + PHCD_0 + Enable PHY clock + 0 + + + PHCD_1 + Disable PHY clock + 0x1 + + + + + PFSC + Port Force Full Speed Connect - Read/Write + 0x18 + 1 + read-write + + + PFSC_0 + Normal operation + 0 + + + PFSC_1 + Forced to full speed + 0x1 + + + + + PTS_2 + See description at bits 31-30 + 0x19 + 1 + read-write + + + PSPD + Port Speed - Read Only. This register field indicates the speed at which the port is operating. + 0x1A + 2 + read-write + + + PSPD_0 + Full Speed + 0 + + + PSPD_1 + Low Speed + 0x1 + + + PSPD_2 + High Speed + 0x2 + + + PSPD_3 + Undefined + 0x3 + + + + + PTW + Parallel Transceiver Width This bit has no effect if serial interface engine is used + 0x1C + 1 + read-write + + + PTW_0 + Select the 8-bit UTMI interface [60MHz] + 0 + + + PTW_1 + Select the 16-bit UTMI interface [30MHz] + 0x1 + + + + + STS + Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals + 0x1D + 1 + read-write + + + PTS_1 + All USB port interface modes are listed in this field description, but not all are supported + 0x1E + 2 + read-write + + + + + OTGSC + On-The-Go Status & control + 0x1A4 + 32 + read-write + 0x1120 + 0xFFFFFFFF + + + VD + VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + VC + VBUS Charge - Read/Write + 0x1 + 1 + read-write + + + OT + OTG Termination - Read/Write + 0x3 + 1 + read-write + + + DP + Data Pulsing - Read/Write + 0x4 + 1 + read-write + + + IDPU + ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default] + 0x5 + 1 + read-write + + + ID + USB ID - Read Only. 0 = A device, 1 = B device + 0x8 + 1 + read-only + + + AVV + A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold. + 0x9 + 1 + read-only + + + ASV + A Session Valid - Read Only. Indicates VBus is above the A session valid threshold. + 0xA + 1 + read-only + + + BSV + B Session Valid - Read Only. Indicates VBus is above the B session valid threshold. + 0xB + 1 + read-only + + + BSE + B Session End - Read Only. Indicates VBus is below the B session end threshold. + 0xC + 1 + read-only + + + TOG_1MS + 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond. + 0xD + 1 + read-only + + + DPS + Data Bus Pulsing Status - Read Only + 0xE + 1 + read-only + + + IDIS + USB ID Interrupt Status - Read/Write + 0x10 + 1 + read-write + + + AVVIS + A VBus Valid Interrupt Status - Read/Write to Clear + 0x11 + 1 + read-write + + + ASVIS + A Session Valid Interrupt Status - Read/Write to Clear + 0x12 + 1 + read-write + + + BSVIS + B Session Valid Interrupt Status - Read/Write to Clear + 0x13 + 1 + read-write + + + BSEIS + B Session End Interrupt Status - Read/Write to Clear + 0x14 + 1 + read-write + + + STATUS_1MS + 1 millisecond timer Interrupt Status - Read/Write to Clear + 0x15 + 1 + read-write + + + DPIS + Data Pulse Interrupt Status - Read/Write to Clear + 0x16 + 1 + read-write + + + IDIE + USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt. + 0x18 + 1 + read-write + + + AVVIE + A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt. + 0x19 + 1 + read-write + + + ASVIE + A Session Valid Interrupt Enable - Read/Write + 0x1A + 1 + read-write + + + BSVIE + B Session Valid Interrupt Enable - Read/Write + 0x1B + 1 + read-write + + + BSEIE + B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt. + 0x1C + 1 + read-write + + + EN_1MS + 1 millisecond timer Interrupt Enable - Read/Write + 0x1D + 1 + read-write + + + DPIE + Data Pulse Interrupt Enable + 0x1E + 1 + read-write + + + + + USBMODE + USB Device Mode + 0x1A8 + 32 + read-write + 0x5000 + 0xFFFFFFFF + + + CM + Controller Mode - R/WO + 0 + 2 + read-write + + + CM_0 + Idle [Default for combination host/device] + 0 + + + CM_2 + Device Controller [Default for device only controller] + 0x2 + + + CM_3 + Host Controller [Default for host only controller] + 0x3 + + + + + ES + Endian Select - Read/Write + 0x2 + 1 + read-write + + + ES_0 + Little Endian [Default] + 0 + + + ES_1 + Big Endian + 0x1 + + + + + SLOM + Setup Lockout Mode + 0x3 + 1 + read-write + + + SLOM_0 + Setup Lockouts On (default); + 0 + + + SLOM_1 + Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + 0x1 + + + + + SDIS + Stream Disable Mode + 0x4 + 1 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENDPTSETUPSTAT + Setup Endpoint Status + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERB + Prime Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + PETB + Prime Endpoint Transmit Buffer - R/WS + 0x10 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FERB + Flush Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + FETB + Flush Endpoint Transmit Buffer - R/WS + 0x10 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status + 0x1B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERBR + Endpoint Receive Buffer Ready -- Read Only + 0 + 8 + read-only + + + ETBR + Endpoint Transmit Buffer Ready -- Read Only + 0x10 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERCE + Endpoint Receive Complete Event - RW/C + 0 + 8 + read-write + + + ETCE + Endpoint Transmit Complete Event - R/WC + 0x10 + 8 + read-write + + + + + ENDPTCTRL0 + Endpoint Control0 + 0x1C0 + 32 + read-write + 0x800080 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point. + 0x2 + 2 + read-write + + + RXE + RX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host + 0x10 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point. + 0x12 + 2 + read-write + + + TXE + TX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 0x17 + 1 + read-write + + + + + ENDPTCTRL1 + Endpoint Control 1 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL2 + Endpoint Control 2 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL3 + Endpoint Control 3 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL4 + Endpoint Control 4 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL5 + Endpoint Control 5 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL6 + Endpoint Control 6 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL7 + Endpoint Control 7 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + + + USB2 + USB + USB + USB2_ + 0x2184200 + + 0 + 0x1E0 + registers + + + USB_OTG2 + 74 + + + + USBNC1 + USB + USBNC + USBNC1_ + 0x2184800 + USBNC + + 0 + 0x1C + registers + + + + USB_OTGn_CTRL + USB OTGn Control Register + 0 + 32 + read-write + 0x30001000 + 0xFFFFFFFF + + + OVER_CUR_DIS + Disable OTGn Overcurrent Detection + 0x7 + 1 + read-write + + + OVER_CUR_DIS_0 + Enables overcurrent detection + 0 + + + OVER_CUR_DIS_1 + Disables overcurrent detection + 0x1 + + + + + OVER_CUR_POL + OTGn Polarity of Overcurrent The polarity of OTGn port overcurrent event + 0x8 + 1 + read-write + + + OVER_CUR_POL_0 + High active (high on this signal represents an overcurrent condition) + 0 + + + OVER_CUR_POL_1 + Low active (low on this signal represents an overcurrent condition) + 0x1 + + + + + PWR_POL + OTGn Power Polarity This bit should be set according to PMIC Power Pin polarity. + 0x9 + 1 + read-write + + + PWR_POL_0 + PMIC Power Pin is Low active. + 0 + + + PWR_POL_1 + PMIC Power Pin is High active. + 0x1 + + + + + WIE + OTGn Wake-up Interrupt Enable This bit enables or disables the OTGn wake-up interrupt + 0xA + 1 + read-write + + + WIE_0 + Interrupt Disabled + 0 + + + WIE_1 + Interrupt Enabled + 0x1 + + + + + WKUP_SW_EN + OTGn Software Wake-up Enable + 0xE + 1 + read-write + + + WKUP_SW_EN_0 + Disable + 0 + + + WKUP_SW_EN_1 + Enable + 0x1 + + + + + WKUP_SW + OTGn Software Wake-up + 0xF + 1 + read-write + + + WKUP_SW_0 + Inactive + 0 + + + WKUP_SW_1 + Force wake-up + 0x1 + + + + + WKUP_ID_EN + OTGn Wake-up on ID change enable + 0x10 + 1 + read-write + + + WKUP_ID_EN_0 + Disable + 0 + + + WKUP_ID_EN_1 + Enable + 0x1 + + + + + WKUP_VBUS_EN + OTGn wake-up on VBUS change enable + 0x11 + 1 + read-write + + + WKUP_VBUS_EN_0 + Disable + 0 + + + WKUP_VBUS_EN_1 + Enable + 0x1 + + + + + WIR + OTGn Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTGn port + 0x1F + 1 + read-only + + + WIR_0 + No wake-up interrupt request received + 0 + + + WIR_1 + Wake-up Interrupt Request received + 0x1 + + + + + + + USB_OTGn_PHY_CTRL_0 + OTGn UTMI PHY Control 0 Register + 0x18 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + UTMI_CLK_VLD + Indicating whether OTGn UTMI PHY clock is valid + 0x1F + 1 + read-write + + + UTMI_CLK_VLD_0 + Invalid + 0 + + + UTMI_CLK_VLD_1 + Valid + 0x1 + + + + + + + + + USBNC2 + USB + USBNC + USBNC2_ + 0x2184804 + + 0 + 0x1C + registers + + + + ENET1 + Ethernet MAC-NET Core + ENET + ENET1_ + 0x2188000 + ENET + + 0 + 0x628 + registers + + + ENET1 + 150 + + + + EIR + Interrupt Event Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + Timestamp Timer + 0xF + 1 + read-write + oneToClear + + + TS_AVAIL + Transmit Timestamp Available + 0x10 + 1 + read-write + oneToClear + + + WAKEUP + Node Wakeup Request Indication + 0x11 + 1 + read-write + oneToClear + + + PLR + Payload Receive Error + 0x12 + 1 + read-write + oneToClear + + + UN + Transmit FIFO Underrun + 0x13 + 1 + read-write + oneToClear + + + RL + Collision Retry Limit + 0x14 + 1 + read-write + oneToClear + + + LC + Late Collision + 0x15 + 1 + read-write + oneToClear + + + EBERR + Ethernet Bus Error + 0x16 + 1 + read-write + oneToClear + + + MII + MII Interrupt. + 0x17 + 1 + read-write + oneToClear + + + RXB + Receive Buffer Interrupt + 0x18 + 1 + read-write + oneToClear + + + RXF + Receive Frame Interrupt + 0x19 + 1 + read-write + oneToClear + + + TXB + Transmit Buffer Interrupt + 0x1A + 1 + read-write + oneToClear + + + TXF + Transmit Frame Interrupt + 0x1B + 1 + read-write + oneToClear + + + GRA + Graceful Stop Complete + 0x1C + 1 + read-write + oneToClear + + + BABT + Babbling Transmit Error + 0x1D + 1 + read-write + oneToClear + + + BABR + Babbling Receive Error + 0x1E + 1 + read-write + oneToClear + + + + + EIMR + Interrupt Mask Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + TS_TIMER Interrupt Mask + 0xF + 1 + read-write + + + TS_AVAIL + TS_AVAIL Interrupt Mask + 0x10 + 1 + read-write + + + WAKEUP + WAKEUP Interrupt Mask + 0x11 + 1 + read-write + + + PLR + PLR Interrupt Mask + 0x12 + 1 + read-write + + + UN + UN Interrupt Mask + 0x13 + 1 + read-write + + + RL + RL Interrupt Mask + 0x14 + 1 + read-write + + + LC + LC Interrupt Mask + 0x15 + 1 + read-write + + + EBERR + EBERR Interrupt Mask + 0x16 + 1 + read-write + + + MII + MII Interrupt Mask + 0x17 + 1 + read-write + + + RXB + RXB Interrupt Mask + 0x18 + 1 + read-write + + + RXF + RXF Interrupt Mask + 0x19 + 1 + read-write + + + TXB + TXB Interrupt Mask + 0x1A + 1 + read-write + + + TXB_0 + The corresponding interrupt source is masked. + 0 + + + TXB_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + TXF + TXF Interrupt Mask + 0x1B + 1 + read-write + + + TXF_0 + The corresponding interrupt source is masked. + 0 + + + TXF_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + GRA + GRA Interrupt Mask + 0x1C + 1 + read-write + + + GRA_0 + The corresponding interrupt source is masked. + 0 + + + GRA_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABT + BABT Interrupt Mask + 0x1D + 1 + read-write + + + BABT_0 + The corresponding interrupt source is masked. + 0 + + + BABT_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABR + BABR Interrupt Mask + 0x1E + 1 + read-write + + + BABR_0 + The corresponding interrupt source is masked. + 0 + + + BABR_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + + + RDAR + Receive Descriptor Active Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDAR + Receive Descriptor Active + 0x18 + 1 + read-write + + + + + TDAR + Transmit Descriptor Active Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDAR + Transmit Descriptor Active + 0x18 + 1 + read-write + + + + + ECR + Ethernet Control Register + 0x24 + 32 + read-write + 0x70000000 + 0xFFFFFFFF + + + RESET + Ethernet MAC Reset + 0 + 1 + read-write + + + ETHEREN + Ethernet Enable + 0x1 + 1 + read-write + + + ETHEREN_0 + Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + 0 + + + ETHEREN_1 + MAC is enabled, and reception and transmission are possible. + 0x1 + + + + + MAGICEN + Magic Packet Detection Enable + 0x2 + 1 + read-write + + + MAGICEN_0 + Magic detection logic disabled. + 0 + + + MAGICEN_1 + The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + 0x1 + + + + + SLEEP + Sleep Mode Enable + 0x3 + 1 + read-write + + + SLEEP_0 + Normal operating mode. + 0 + + + SLEEP_1 + Sleep mode. + 0x1 + + + + + EN1588 + EN1588 Enable + 0x4 + 1 + read-write + + + EN1588_0 + Legacy FEC buffer descriptors and functions enabled. + 0 + + + EN1588_1 + Enhanced frame time-stamping functions enabled. + 0x1 + + + + + DBGEN + Debug Enable + 0x6 + 1 + read-write + + + DBGEN_0 + MAC continues operation in debug mode. + 0 + + + DBGEN_1 + MAC enters hardware freeze mode when the processor is in debug mode. + 0x1 + + + + + DBSWP + Descriptor Byte Swapping Enable + 0x8 + 1 + read-write + + + DBSWP_0 + The buffer descriptor bytes are not swapped to support big-endian devices. + 0 + + + DBSWP_1 + The buffer descriptor bytes are swapped to support little-endian devices. + 0x1 + + + + + + + MMFR + MII Management Frame Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Management Frame Data + 0 + 16 + read-write + + + TA + Turn Around + 0x10 + 2 + read-write + + + RA + Register Address + 0x12 + 5 + read-write + + + PA + PHY Address + 0x17 + 5 + read-write + + + OP + Operation Code + 0x1C + 2 + read-write + + + ST + Start Of Frame Delimiter + 0x1E + 2 + read-write + + + + + MSCR + MII Speed Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MII_SPEED + MII Speed + 0x1 + 6 + read-write + + + DIS_PRE + Disable Preamble + 0x7 + 1 + read-write + + + DIS_PRE_0 + Preamble enabled. + 0 + + + DIS_PRE_1 + Preamble (32 ones) is not prepended to the MII management frame. + 0x1 + + + + + HOLDTIME + Hold time On MDIO Output + 0x8 + 3 + read-write + + + HOLDTIME_0 + 1 internal module clock cycle + 0 + + + HOLDTIME_1 + 2 internal module clock cycles + 0x1 + + + HOLDTIME_2 + 3 internal module clock cycles + 0x2 + + + HOLDTIME_7 + 8 internal module clock cycles + 0x7 + + + + + + + MIBC + MIB Control Register + 0x64 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + MIB_CLEAR + MIB Clear + 0x1D + 1 + read-write + + + MIB_CLEAR_0 + See note above. + 0 + + + MIB_CLEAR_1 + All statistics counters are reset to 0. + 0x1 + + + + + MIB_IDLE + MIB Idle + 0x1E + 1 + read-only + + + MIB_IDLE_0 + The MIB block is updating MIB counters. + 0 + + + MIB_IDLE_1 + The MIB block is not currently updating any MIB counters. + 0x1 + + + + + MIB_DIS + Disable MIB Logic + 0x1F + 1 + read-write + + + MIB_DIS_0 + MIB logic is enabled. + 0 + + + MIB_DIS_1 + MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + 0x1 + + + + + + + RCR + Receive Control Register + 0x84 + 32 + read-write + 0x5EE0001 + 0xFFFFFFFF + + + LOOP + Internal Loopback + 0 + 1 + read-write + + + LOOP_0 + Loopback disabled. + 0 + + + LOOP_1 + Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + 0x1 + + + + + DRT + Disable Receive On Transmit + 0x1 + 1 + read-write + + + DRT_0 + Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + 0 + + + DRT_1 + Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + 0x1 + + + + + MII_MODE + Media Independent Interface Mode + 0x2 + 1 + read-write + + + MII_MODE_1 + MII or RMII mode, as indicated by the RMII_MODE field. + 0x1 + + + + + PROM + Promiscuous Mode + 0x3 + 1 + read-write + + + PROM_0 + Disabled. + 0 + + + PROM_1 + Enabled. + 0x1 + + + + + BC_REJ + Broadcast Frame Reject + 0x4 + 1 + read-write + + + FCE + Flow Control Enable + 0x5 + 1 + read-write + + + RMII_MODE + RMII Mode Enable + 0x8 + 1 + read-write + + + RMII_MODE_0 + MAC configured for MII mode. + 0 + + + RMII_MODE_1 + MAC configured for RMII operation. + 0x1 + + + + + RMII_10T + Enables 10-Mbit/s mode of the RMII . + 0x9 + 1 + read-write + + + RMII_10T_0 + 100-Mbit/s operation. + 0 + + + RMII_10T_1 + 10-Mbit/s operation. + 0x1 + + + + + PADEN + Enable Frame Padding Remove On Receive + 0xC + 1 + read-write + + + PADEN_0 + No padding is removed on receive by the MAC. + 0 + + + PADEN_1 + Padding is removed from received frames. + 0x1 + + + + + PAUFWD + Terminate/Forward Pause Frames + 0xD + 1 + read-write + + + PAUFWD_0 + Pause frames are terminated and discarded in the MAC. + 0 + + + PAUFWD_1 + Pause frames are forwarded to the user application. + 0x1 + + + + + CRCFWD + Terminate/Forward Received CRC + 0xE + 1 + read-write + + + CRCFWD_0 + The CRC field of received frames is transmitted to the user application. + 0 + + + CRCFWD_1 + The CRC field is stripped from the frame. + 0x1 + + + + + CFEN + MAC Control Frame Enable + 0xF + 1 + read-write + + + CFEN_0 + MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + 0 + + + CFEN_1 + MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + 0x1 + + + + + MAX_FL + Maximum Frame Length + 0x10 + 14 + read-write + + + NLC + Payload Length Check Disable + 0x1E + 1 + read-write + + + NLC_0 + The payload length check is disabled. + 0 + + + NLC_1 + The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field. + 0x1 + + + + + GRS + Graceful Receive Stopped + 0x1F + 1 + read-only + + + + + TCR + Transmit Control Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GTS + Graceful Transmit Stop + 0 + 1 + read-write + + + FDEN + Full-Duplex Enable + 0x2 + 1 + read-write + + + TFC_PAUSE + Transmit Frame Control Pause + 0x3 + 1 + read-write + + + TFC_PAUSE_0 + No PAUSE frame transmitted. + 0 + + + TFC_PAUSE_1 + The MAC stops transmission of data frames after the current transmission is complete. + 0x1 + + + + + RFC_PAUSE + Receive Frame Control Pause + 0x4 + 1 + read-only + + + ADDSEL + Source MAC Address Select On Transmit + 0x5 + 3 + read-write + + + ADDSEL_0 + Node MAC address programmed on PADDR1/2 registers. + 0 + + + + + ADDINS + Set MAC Address On Transmit + 0x8 + 1 + read-write + + + ADDINS_0 + The source MAC address is not modified by the MAC. + 0 + + + ADDINS_1 + The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + 0x1 + + + + + CRCFWD + Forward Frame From Application With CRC + 0x9 + 1 + read-write + + + CRCFWD_0 + TxBD[TC] controls whether the frame has a CRC from the application. + 0 + + + CRCFWD_1 + The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + 0x1 + + + + + + + PALR + Physical Address Lower Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADDR1 + Pause Address + 0 + 32 + read-write + + + + + PAUR + Physical Address Upper Register + 0xE8 + 32 + read-write + 0x8808 + 0xFFFFFFFF + + + TYPE + Type Field In PAUSE Frames + 0 + 16 + read-only + + + PADDR2 + Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames + 0x10 + 16 + read-write + + + + + OPD + Opcode/Pause Duration Register + 0xEC + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + PAUSE_DUR + Pause Duration + 0 + 16 + read-write + + + OPCODE + Opcode Field In PAUSE Frames + 0x10 + 16 + read-only + + + + + TXIC + Transmit Interrupt Coalescing Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 0x14 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 0x1E + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 0x1F + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + RXIC + Receive Interrupt Coalescing Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 0x14 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 0x1E + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 0x1F + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + IAUR + Descriptor Individual Upper Address Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + IALR + Descriptor Individual Lower Address Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + GAUR + Descriptor Group Upper Address Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + GALR + Descriptor Group Lower Address Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + TFWR + Transmit FIFO Watermark Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFWR + Transmit FIFO Write + 0 + 6 + read-write + + + TFWR_0 + 64 bytes written. + 0 + + + TFWR_1 + 64 bytes written. + 0x1 + + + TFWR_2 + 128 bytes written. + 0x2 + + + TFWR_3 + 192 bytes written. + 0x3 + + + TFWR_31 + 1984 bytes written. + 0x1F + + + + + STRFWD + Store And Forward Enable + 0x8 + 1 + read-write + + + STRFWD_0 + Reset. The transmission start threshold is programmed in TFWR[TFWR]. + 0 + + + STRFWD_1 + Enabled. + 0x1 + + + + + + + RDSR + Receive Descriptor Ring Start Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_DES_START + Pointer to the beginning of the receive buffer descriptor queue. + 0x3 + 29 + read-write + + + + + TDSR + Transmit Buffer Descriptor Ring Start Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + X_DES_START + Pointer to the beginning of the transmit buffer descriptor queue. + 0x3 + 29 + read-write + + + + + MRBR + Maximum Receive Buffer Size Register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_BUF_SIZE + Receive buffer size in bytes + 0x4 + 10 + read-write + + + + + RSFL + Receive FIFO Section Full Threshold + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_FULL + Value Of Receive FIFO Section Full Threshold + 0 + 8 + read-write + + + + + RSEM + Receive FIFO Section Empty Threshold + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_EMPTY + Value Of The Receive FIFO Section Empty Threshold + 0 + 8 + read-write + + + STAT_SECTION_EMPTY + RX Status FIFO Section Empty Threshold + 0x10 + 5 + read-write + + + + + RAEM + Receive FIFO Almost Empty Threshold + 0x198 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_EMPTY + Value Of The Receive FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + RAFL + Receive FIFO Almost Full Threshold + 0x19C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_FULL + Value Of The Receive FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TSEM + Transmit FIFO Section Empty Threshold + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SECTION_EMPTY + Value Of The Transmit FIFO Section Empty Threshold + 0 + 8 + read-write + + + + + TAEM + Transmit FIFO Almost Empty Threshold + 0x1A4 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + TX_ALMOST_EMPTY + Value of Transmit FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + TAFL + Transmit FIFO Almost Full Threshold + 0x1A8 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TX_ALMOST_FULL + Value Of The Transmit FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TIPG + Transmit Inter-Packet Gap + 0x1AC + 32 + read-write + 0xC + 0xFFFFFFFF + + + IPG + Transmit Inter-Packet Gap + 0 + 5 + read-write + + + + + FTRL + Frame Truncation Length + 0x1B0 + 32 + read-write + 0x7FF + 0xFFFFFFFF + + + TRUNC_FL + Frame Truncation Length + 0 + 14 + read-write + + + + + TACC + Transmit Accelerator Function Configuration + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFT16 + TX FIFO Shift-16 + 0 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + 0x1 + + + + + IPCHK + Enables insertion of IP header checksum. + 0x3 + 1 + read-write + + + IPCHK_0 + Checksum is not inserted. + 0 + + + IPCHK_1 + If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + 0x1 + + + + + PROCHK + Enables insertion of protocol checksum. + 0x4 + 1 + read-write + + + PROCHK_0 + Checksum not inserted. + 0 + + + PROCHK_1 + If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + 0x1 + + + + + + + RACC + Receive Accelerator Function Configuration + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADREM + Enable Padding Removal For Short IP Frames + 0 + 1 + read-write + + + PADREM_0 + Padding not removed. + 0 + + + PADREM_1 + Any bytes following the IP payload section of the frame are removed from the frame. + 0x1 + + + + + IPDIS + Enable Discard Of Frames With Wrong IPv4 Header Checksum + 0x1 + 1 + read-write + + + IPDIS_0 + Frames with wrong IPv4 header checksum are not discarded. + 0 + + + IPDIS_1 + If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + PRODIS + Enable Discard Of Frames With Wrong Protocol Checksum + 0x2 + 1 + read-write + + + PRODIS_0 + Frames with wrong checksum are not discarded. + 0 + + + PRODIS_1 + If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + LINEDIS + Enable Discard Of Frames With MAC Layer Errors + 0x6 + 1 + read-write + + + LINEDIS_0 + Frames with errors are not discarded. + 0 + + + LINEDIS_1 + Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + 0x1 + + + + + SHIFT16 + RX FIFO Shift-16 + 0x7 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + 0x1 + + + + + + + RMON_T_DROP + Reserved Statistic Register + 0x200 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_T_PACKETS + Tx Packet Count Statistic Register + 0x204 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packet count + 0 + 16 + read-only + + + + + RMON_T_BC_PKT + Tx Broadcast Packets Statistic Register + 0x208 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Broadcast packets + 0 + 16 + read-only + + + + + RMON_T_MC_PKT + Tx Multicast Packets Statistic Register + 0x20C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Multicast packets + 0 + 16 + read-only + + + + + RMON_T_CRC_ALIGN + Tx Packets with CRC/Align Error Statistic Register + 0x210 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packets with CRC/align error + 0 + 16 + read-only + + + + + RMON_T_UNDERSIZE + Tx Packets Less Than Bytes and Good CRC Statistic Register + 0x214 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets less than 64 bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_OVERSIZE + Tx Packets GT MAX_FL bytes and Good CRC Statistic Register + 0x218 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_FRAG + Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x21C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of packets less than 64 bytes with bad CRC + 0 + 16 + read-only + + + + + RMON_T_JAB + Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_T_COL + Tx Collision Count Statistic Register + 0x224 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit collisions + 0 + 16 + read-only + + + + + RMON_T_P64 + Tx 64-Byte Packets Statistic Register + 0x228 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 64-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P65TO127 + Tx 65- to 127-byte Packets Statistic Register + 0x22C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 65- to 127-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P128TO255 + Tx 128- to 255-byte Packets Statistic Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 128- to 255-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P256TO511 + Tx 256- to 511-byte Packets Statistic Register + 0x234 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 256- to 511-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P512TO1023 + Tx 512- to 1023-byte Packets Statistic Register + 0x238 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 512- to 1023-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P1024TO2047 + Tx 1024- to 2047-byte Packets Statistic Register + 0x23C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 1024- to 2047-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P_GTE2048 + Tx Packets Greater Than 2048 Bytes Statistic Register + 0x240 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than 2048 bytes + 0 + 16 + read-only + + + + + RMON_T_OCTETS + Tx Octets Statistic Register + 0x244 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXOCTS + Number of transmit octets + 0 + 32 + read-only + + + + + IEEE_T_DROP + Reserved Statistic Register + 0x248 + 32 + read-only + 0 + 0xFFFFFFFF + + + IEEE_T_FRAME_OK + Frames Transmitted OK Statistic Register + 0x24C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted OK + 0 + 16 + read-only + + + + + IEEE_T_1COL + Frames Transmitted with Single Collision Statistic Register + 0x250 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with one collision + 0 + 16 + read-only + + + + + IEEE_T_MCOL + Frames Transmitted with Multiple Collisions Statistic Register + 0x254 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with multiple collisions + 0 + 16 + read-only + + + + + IEEE_T_DEF + Frames Transmitted after Deferral Delay Statistic Register + 0x258 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with deferral delay + 0 + 16 + read-only + + + + + IEEE_T_LCOL + Frames Transmitted with Late Collision Statistic Register + 0x25C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with late collision + 0 + 16 + read-only + + + + + IEEE_T_EXCOL + Frames Transmitted with Excessive Collisions Statistic Register + 0x260 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with excessive collisions + 0 + 16 + read-only + + + + + IEEE_T_MACERR + Frames Transmitted with Tx FIFO Underrun Statistic Register + 0x264 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with transmit FIFO underrun + 0 + 16 + read-only + + + + + IEEE_T_CSERR + Frames Transmitted with Carrier Sense Error Statistic Register + 0x268 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with carrier sense error + 0 + 16 + read-only + + + + + IEEE_T_SQE + Reserved Statistic Register + 0x26C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + This read-only field is reserved and always has the value 0 + 0 + 16 + read-only + + + + + IEEE_T_FDXFC + Flow Control Pause Frames Transmitted Statistic Register + 0x270 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames transmitted + 0 + 16 + read-only + + + + + IEEE_T_OCTETS_OK + Octet Count for Frames Transmitted w/o Error Statistic Register + 0x274 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). + 0 + 32 + read-only + + + + + RMON_R_PACKETS + Rx Packet Count Statistic Register + 0x284 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of packets received + 0 + 16 + read-only + + + + + RMON_R_BC_PKT + Rx Broadcast Packets Statistic Register + 0x288 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive broadcast packets + 0 + 16 + read-only + + + + + RMON_R_MC_PKT + Rx Multicast Packets Statistic Register + 0x28C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive multicast packets + 0 + 16 + read-only + + + + + RMON_R_CRC_ALIGN + Rx Packets with CRC/Align Error Statistic Register + 0x290 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with CRC or align error + 0 + 16 + read-only + + + + + RMON_R_UNDERSIZE + Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register + 0x294 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and good CRC + 0 + 16 + read-only + + + + + RMON_R_OVERSIZE + Rx Packets Greater Than MAX_FL and Good CRC Statistic Register + 0x298 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and good CRC + 0 + 16 + read-only + + + + + RMON_R_FRAG + Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x29C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_R_JAB + Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register + 0x2A0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and bad CRC + 0 + 16 + read-only + + + + + RMON_R_RESVD_0 + Reserved Statistic Register + 0x2A4 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_R_P64 + Rx 64-Byte Packets Statistic Register + 0x2A8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 64-byte receive packets + 0 + 16 + read-only + + + + + RMON_R_P65TO127 + Rx 65- to 127-Byte Packets Statistic Register + 0x2AC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 65- to 127-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P128TO255 + Rx 128- to 255-Byte Packets Statistic Register + 0x2B0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 128- to 255-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P256TO511 + Rx 256- to 511-Byte Packets Statistic Register + 0x2B4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 256- to 511-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P512TO1023 + Rx 512- to 1023-Byte Packets Statistic Register + 0x2B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 512- to 1023-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P1024TO2047 + Rx 1024- to 2047-Byte Packets Statistic Register + 0x2BC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 1024- to 2047-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P_GTE2048 + Rx Packets Greater than 2048 Bytes Statistic Register + 0x2C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of greater-than-2048-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_OCTETS + Rx Octets Statistic Register + 0x2C4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive octets + 0 + 32 + read-only + + + + + IEEE_R_DROP + Frames not Counted Correctly Statistic Register + 0x2C8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Frame count + 0 + 16 + read-only + + + + + IEEE_R_FRAME_OK + Frames Received OK Statistic Register + 0x2CC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received OK + 0 + 16 + read-only + + + + + IEEE_R_CRC + Frames Received with CRC Error Statistic Register + 0x2D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with CRC error + 0 + 16 + read-only + + + + + IEEE_R_ALIGN + Frames Received with Alignment Error Statistic Register + 0x2D4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with alignment error + 0 + 16 + read-only + + + + + IEEE_R_MACERR + Receive FIFO Overflow Count Statistic Register + 0x2D8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Receive FIFO overflow count + 0 + 16 + read-only + + + + + IEEE_R_FDXFC + Flow Control Pause Frames Received Statistic Register + 0x2DC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames received + 0 + 16 + read-only + + + + + IEEE_R_OCTETS_OK + Octet Count for Frames Received without Error Statistic Register + 0x2E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of octets for frames received without error + 0 + 32 + read-only + + + + + ATCR + Adjustable Timer Control Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable Timer + 0 + 1 + read-write + + + EN_0 + The timer stops at the current value. + 0 + + + EN_1 + The timer starts incrementing. + 0x1 + + + + + OFFEN + Enable One-Shot Offset Event + 0x2 + 1 + read-write + + + OFFEN_0 + Disable. + 0 + + + OFFEN_1 + The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + 0x1 + + + + + OFFRST + Reset Timer On Offset Event + 0x3 + 1 + read-write + + + OFFRST_0 + The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + 0 + + + OFFRST_1 + If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + 0x1 + + + + + PEREN + Enable Periodical Event + 0x4 + 1 + read-write + + + PEREN_0 + Disable. + 0 + + + PEREN_1 + A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + 0x1 + + + + + PINPER + Enables event signal output assertion on period event + 0x7 + 1 + read-write + + + PINPER_0 + Disable. + 0 + + + PINPER_1 + Enable. + 0x1 + + + + + RESTART + Reset Timer + 0x9 + 1 + read-write + + + CAPTURE + Capture Timer Value + 0xB + 1 + read-write + + + CAPTURE_0 + No effect. + 0 + + + CAPTURE_1 + The current time is captured and can be read from the ATVR register. + 0x1 + + + + + SLAVE + Enable Timer Slave Mode + 0xD + 1 + read-write + + + SLAVE_0 + The timer is active and all configuration fields in this register are relevant. + 0 + + + SLAVE_1 + The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + 0x1 + + + + + + + ATVR + Timer Value Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATIME + A write sets the timer + 0 + 32 + read-write + + + + + ATOFF + Timer Offset Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET + Offset value for one-shot event generation + 0 + 32 + read-write + + + + + ATPER + Timer Period Register + 0x40C + 32 + read-write + 0x3B9ACA00 + 0xFFFFFFFF + + + PERIOD + Value for generating periodic events + 0 + 32 + read-write + + + + + ATCOR + Timer Correction Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + COR + Correction Counter Wrap-Around Value + 0 + 31 + read-write + + + + + ATINC + Time-Stamping Clock Period Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + 0 + 7 + read-write + + + INC_CORR + Correction Increment Value + 0x8 + 7 + read-write + + + + + ATSTMP + Timestamp of Last Transmitted Frame + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + TIMESTAMP + Timestamp of the last frame transmitted by the core that had TxBD[TS] set + 0 + 32 + read-only + + + + + TGSR + Timer Global Status Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + TF0 + Copy Of Timer Flag For Channel 0 + 0 + 1 + read-write + oneToClear + + + TF0_0 + Timer Flag for Channel 0 is clear + 0 + + + TF0_1 + Timer Flag for Channel 0 is set + 0x1 + + + + + TF1 + Copy Of Timer Flag For Channel 1 + 0x1 + 1 + read-write + oneToClear + + + TF1_0 + Timer Flag for Channel 1 is clear + 0 + + + TF1_1 + Timer Flag for Channel 1 is set + 0x1 + + + + + TF2 + Copy Of Timer Flag For Channel 2 + 0x2 + 1 + read-write + oneToClear + + + TF2_0 + Timer Flag for Channel 2 is clear + 0 + + + TF2_1 + Timer Flag for Channel 2 is set + 0x1 + + + + + TF3 + Copy Of Timer Flag For Channel 3 + 0x3 + 1 + read-write + oneToClear + + + TF3_0 + Timer Flag for Channel 3 is clear + 0 + + + TF3_1 + Timer Flag for Channel 3 is set + 0x1 + + + + + + + 4 + 0x8 + TCSR%s + Timer Control Status Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + TDRE_0 + DMA request is disabled + 0 + + + TDRE_1 + DMA request is enabled + 0x1 + + + + + TMODE + Timer Mode + 0x2 + 4 + read-write + + + TMODE_0 + Timer Channel is disabled. + 0 + + + TMODE_1 + Timer Channel is configured for Input Capture on rising edge. + 0x1 + + + TMODE_2 + Timer Channel is configured for Input Capture on falling edge. + 0x2 + + + TMODE_3 + Timer Channel is configured for Input Capture on both edges. + 0x3 + + + TMODE_4 + Timer Channel is configured for Output Compare - software only. + 0x4 + + + TMODE_5 + Timer Channel is configured for Output Compare - toggle output on compare. + 0x5 + + + TMODE_6 + Timer Channel is configured for Output Compare - clear output on compare. + 0x6 + + + TMODE_7 + Timer Channel is configured for Output Compare - set output on compare. + 0x7 + + + TMODE_10 + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + 0xA + + + TMODE_14 + Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xE + + + TMODE_15 + Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xF + + + + + TIE + Timer Interrupt Enable + 0x6 + 1 + read-write + + + TIE_0 + Interrupt is disabled + 0 + + + TIE_1 + Interrupt is enabled + 0x1 + + + + + TF + Timer Flag + 0x7 + 1 + read-write + oneToClear + + + TF_0 + Input Capture or Output Compare has not occurred. + 0 + + + TF_1 + Input Capture or Output Compare has occurred. + 0x1 + + + + + TPWC + Timer PulseWidth Control + 0xB + 5 + read-write + + + TPWC_0 + Pulse width is one 1588-clock cycle. + 0 + + + TPWC_1 + Pulse width is two 1588-clock cycles. + 0x1 + + + TPWC_2 + Pulse width is three 1588-clock cycles. + 0x2 + + + TPWC_3 + Pulse width is four 1588-clock cycles. + 0x3 + + + TPWC_31 + Pulse width is 32 1588-clock cycles. + 0x1F + + + + + + + 4 + 0x8 + TCCR%s + Timer Compare Capture Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + + + ENET2 + Ethernet MAC-NET Core + ENET + ENET2_ + 0x20B4000 + + 0 + 0x628 + registers + + + ENET2 + 152 + + + + USDHC1 + USDHC + USDHC + USDHC1_ + 0x2190000 + USDHC + + 0 + 0xD0 + registers + + + USDHC1 + 54 + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DS_ADDR + DMA System Address / Argument 2 When ACMD23_ARGU2_EN is set to 0, SDMA uses this register as system address and supports only 32-bit addressing mode + 0 + 32 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLKSIZE + Transfer Block Size: This register specifies the block size for block data transfers + 0 + 13 + read-write + + + BLKSIZE_0 + No data transfer + 0 + + + BLKSIZE_1 + 1 Byte + 0x1 + + + BLKSIZE_2 + 2 Bytes + 0x2 + + + BLKSIZE_3 + 3 Bytes + 0x3 + + + BLKSIZE_4 + 4 Bytes + 0x4 + + + BLKSIZE_8 + 4096 Bytes + 0x8 + + + BLKSIZE_200 + 512 Bytes + 0xC8 + + + BLKSIZE_800 + 2048 Bytes + 0x320 + + + + + BLKCNT + Blocks Count For Current Transfer: This register is enabled when the Block Count Enable bit in the Transfer Mode register is set to 1 and is valid only for multiple block transfers + 0x10 + 16 + read-write + + + BLKCNT_0 + Stop Count + 0 + + + BLKCNT_1 + 1 block + 0x1 + + + BLKCNT_2 + 2 blocks + 0x2 + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + Command Argument + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RSPTYP + Response Type Select + 0x10 + 2 + read-write + + + RSPTYP_0 + No Response + 0 + + + RSPTYP_1 + Response Length 136 + 0x1 + + + RSPTYP_2 + Response Length 48 + 0x2 + + + RSPTYP_3 + Response Length 48, check Busy after response + 0x3 + + + + + CCCEN + Command CRC Check Enable + 0x13 + 1 + read-write + + + CCCEN_0 + Disable + 0 + + + CCCEN_1 + Enable + 0x1 + + + + + CICEN + Command Index Check Enable + 0x14 + 1 + read-write + + + CICEN_0 + Disable + 0 + + + CICEN_1 + Enable + 0x1 + + + + + DPSEL + Data Present Select + 0x15 + 1 + read-write + + + DPSEL_0 + No Data Present + 0 + + + DPSEL_1 + Data Present + 0x1 + + + + + CMDTYP + Command Type + 0x16 + 2 + read-write + + + CMDTYP_0 + Normal Other commands + 0 + + + CMDTYP_1 + Suspend CMD52 for writing Bus Suspend in CCCR + 0x1 + + + CMDTYP_2 + Resume CMD52 for writing Function Select in CCCR + 0x2 + + + CMDTYP_3 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + 0x3 + + + + + CMDINX + Command Index + 0x18 + 6 + read-write + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + Command Response 0 + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + Command Response 1 + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + Command Response 2 + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + Command Response 3 + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + Data Content + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0x8080 + 0xFFFFFFFF + + + CIHB + Command Inhibit (CMD) + 0 + 1 + read-only + + + CIHB_0 + Can issue command using only CMD line + 0 + + + CIHB_1 + Cannot issue command + 0x1 + + + + + CDIHB + Command Inhibit (DATA) + 0x1 + 1 + read-only + + + CDIHB_0 + Can issue command which uses the DATA line + 0 + + + CDIHB_1 + Cannot issue command which uses the DATA line + 0x1 + + + + + DLA + Data Line Active + 0x2 + 1 + read-only + + + DLA_0 + DATA Line Inactive + 0 + + + DLA_1 + DATA Line Active + 0x1 + + + + + SDSTB + SD Clock Stable + 0x3 + 1 + read-only + + + SDSTB_0 + Clock is changing frequency and not stable. + 0 + + + SDSTB_1 + Clock is stable. + 0x1 + + + + + IPGOFF + IPG_CLK Gated Off Internally + 0x4 + 1 + read-only + + + IPGOFF_0 + IPG_CLK is active. + 0 + + + IPGOFF_1 + IPG_CLK is gated off. + 0x1 + + + + + HCKOFF + HCLK Gated Off Internally + 0x5 + 1 + read-only + + + HCKOFF_0 + HCLK is active. + 0 + + + HCKOFF_1 + HCLK is gated off. + 0x1 + + + + + PEROFF + IPG_PERCLK Gated Off Internally + 0x6 + 1 + read-only + + + PEROFF_0 + IPG_PERCLK is active. + 0 + + + PEROFF_1 + IPG_PERCLK is gated off. + 0x1 + + + + + SDOFF + SD Clock Gated Off Internally + 0x7 + 1 + read-only + + + SDOFF_0 + SD Clock is active. + 0 + + + SDOFF_1 + SD Clock is gated off. + 0x1 + + + + + WTA + Write Transfer Active + 0x8 + 1 + read-only + + + WTA_0 + No valid data + 0 + + + WTA_1 + Transferring data + 0x1 + + + + + RTA + Read Transfer Active + 0x9 + 1 + read-only + + + RTA_0 + No valid data + 0 + + + RTA_1 + Transferring data + 0x1 + + + + + BWEN + Buffer Write Enable + 0xA + 1 + read-only + + + BWEN_0 + Write disable + 0 + + + BWEN_1 + Write enable + 0x1 + + + + + BREN + Buffer Read Enable + 0xB + 1 + read-only + + + BREN_0 + Read disable + 0 + + + BREN_1 + Read enable + 0x1 + + + + + RTR + Re-Tuning Request (only for SD3.0 SDR104 mode) + 0xC + 1 + read-only + + + RTR_0 + Fixed or well tuned sampling clock + 0 + + + RTR_1 + Sampling clock needs re-tuning + 0x1 + + + + + TSCD + Tape Select Change Done + 0xF + 1 + read-only + + + TSCD_0 + Delay cell select change is not finished. + 0 + + + TSCD_1 + Delay cell select change is finished. + 0x1 + + + + + CINST + Card Inserted + 0x10 + 1 + read-only + + + CINST_0 + Power on Reset or No Card + 0 + + + CINST_1 + Card Inserted + 0x1 + + + + + CDPL + Card Detect Pin Level + 0x12 + 1 + read-only + + + CDPL_0 + No card present (CD_B = 1) + 0 + + + CDPL_1 + Card present (CD_B = 0) + 0x1 + + + + + WPSPL + Write Protect Switch Pin Level + 0x13 + 1 + read-only + + + WPSPL_0 + Write protected (WP = 1) + 0 + + + WPSPL_1 + Write enabled (WP = 0) + 0x1 + + + + + CLSL + CMD Line Signal Level + 0x17 + 1 + read-only + + + DLSL + DATA[7:0] Line Signal Level + 0x18 + 8 + read-only + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + LED Control + 0 + 1 + read-write + + + LCTL_0 + LED off + 0 + + + LCTL_1 + LED on + 0x1 + + + + + DTW + Data Transfer Width + 0x1 + 2 + read-write + + + DTW_0 + 1-bit mode + 0 + + + DTW_1 + 4-bit mode + 0x1 + + + DTW_2 + 8-bit mode + 0x2 + + + + + D3CD + DATA3 as Card Detection Pin + 0x3 + 1 + read-write + + + D3CD_0 + DATA3 does not monitor Card Insertion + 0 + + + D3CD_1 + DATA3 as Card Detection Pin + 0x1 + + + + + EMODE + Endian Mode + 0x4 + 2 + read-write + + + EMODE_0 + Big Endian Mode + 0 + + + EMODE_1 + Half Word Big Endian Mode + 0x1 + + + EMODE_2 + Little Endian Mode + 0x2 + + + + + CDTL + Card Detect Test Level + 0x6 + 1 + read-write + + + CDTL_0 + Card Detect Test Level is 0, no card inserted + 0 + + + CDTL_1 + Card Detect Test Level is 1, card inserted + 0x1 + + + + + CDSS + Card Detect Signal Selection + 0x7 + 1 + read-write + + + CDSS_0 + Card Detection Level is selected (for normal purpose). + 0 + + + CDSS_1 + Card Detection Test Level is selected (for test purpose). + 0x1 + + + + + DMASEL + DMA Select + 0x8 + 2 + read-write + + + DMASEL_0 + No DMA or Simple DMA is selected + 0 + + + DMASEL_1 + ADMA1 is selected + 0x1 + + + DMASEL_2 + ADMA2 is selected + 0x2 + + + + + SABGREQ + Stop At Block Gap Request + 0x10 + 1 + read-write + + + SABGREQ_0 + Transfer + 0 + + + SABGREQ_1 + Stop + 0x1 + + + + + CREQ + Continue Request + 0x11 + 1 + read-write + + + CREQ_0 + No effect + 0 + + + CREQ_1 + Restart + 0x1 + + + + + RWCTL + Read Wait Control + 0x12 + 1 + read-write + + + RWCTL_0 + Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + 0 + + + RWCTL_1 + Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + 0x1 + + + + + IABG + Interrupt At Block Gap + 0x13 + 1 + read-write + + + IABG_0 + Disabled + 0 + + + IABG_1 + Enabled + 0x1 + + + + + RD_DONE_NO_8CLK + Read done no 8 clock: According to the SD/MMC spec, for read data transaction, 8 clocks are needed after the end bit of the last data block + 0x14 + 1 + read-write + + + WECINT + Wakeup Event Enable On Card Interrupt + 0x18 + 1 + read-write + + + WECINT_0 + Disable + 0 + + + WECINT_1 + Enable + 0x1 + + + + + WECINS + Wakeup Event Enable On SD Card Insertion + 0x19 + 1 + read-write + + + WECINS_0 + Disable + 0 + + + WECINS_1 + Enable + 0x1 + + + + + WECRM + Wakeup Event Enable On SD Card Removal + 0x1A + 1 + read-write + + + WECRM_0 + Disable + 0 + + + WECRM_1 + Enable + 0x1 + + + + + BURST_LEN_EN + BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + 0x1B + 3 + read-write + + + NON_EXACT_BLK_RD + Current block read is non-exact block read. It is only used for SDIO. + 0x1E + 1 + read-write + + + NON_EXACT_BLK_RD_0 + The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + 0 + + + NON_EXACT_BLK_RD_1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + 0x1 + + + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x8080800F + 0xFFFFFFFF + + + DVS + Divisor + 0x4 + 4 + read-write + + + DVS_0 + Divide-by-1 + 0 + + + DVS_1 + Divide-by-2 + 0x1 + + + DVS_14 + Divide-by-15 + 0xE + + + DVS_15 + Divide-by-16 + 0xF + + + + + SDCLKFS + SDCLK Frequency Select + 0x8 + 8 + read-write + + + DTOCV + Data Timeout Counter Value + 0x10 + 4 + read-write + + + DTOCV_0 + SDCLK x 2 1 3 + 0 + + + DTOCV_1 + SDCLK x 2 14 + 0x1 + + + DTOCV_14 + SDCLK x 2 2 7 + 0xE + + + DTOCV_15 + SDCLK x 2 28 + 0xF + + + + + IPP_RST_N + This register's value will be output to CARD from pad directly for hardware reset of the card if the card supports this feature + 0x17 + 1 + read-write + + + RSTA + Software Reset For ALL + 0x18 + 1 + read-write + + + RSTA_0 + No Reset + 0 + + + RSTA_1 + Reset + 0x1 + + + + + RSTC + Software Reset For CMD Line + 0x19 + 1 + read-write + + + RSTC_0 + No Reset + 0 + + + RSTC_1 + Reset + 0x1 + + + + + RSTD + Software Reset For DATA Line + 0x1A + 1 + read-write + + + RSTD_0 + No Reset + 0 + + + RSTD_1 + Reset + 0x1 + + + + + INITA + Initialization Active + 0x1B + 1 + read-write + + + RSTT + Reset Tuning + 0x1C + 1 + read-write + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + Command Complete + 0 + 1 + read-write + oneToClear + + + CC_0 + Command not complete + 0 + + + CC_1 + Command complete + 0x1 + + + + + TC + Transfer Complete + 0x1 + 1 + read-write + oneToClear + + + TC_0 + Transfer not complete + 0 + + + TC_1 + Transfer complete + 0x1 + + + + + BGE + Block Gap Event + 0x2 + 1 + read-write + oneToClear + + + BGE_0 + No block gap event + 0 + + + BGE_1 + Transaction stopped at block gap + 0x1 + + + + + DINT + DMA Interrupt + 0x3 + 1 + read-write + oneToClear + + + DINT_0 + No DMA Interrupt + 0 + + + DINT_1 + DMA Interrupt is generated + 0x1 + + + + + BWR + Buffer Write Ready + 0x4 + 1 + read-write + oneToClear + + + BWR_0 + Not ready to write buffer + 0 + + + BWR_1 + Ready to write buffer: + 0x1 + + + + + BRR + Buffer Read Ready + 0x5 + 1 + read-write + oneToClear + + + BRR_0 + Not ready to read buffer + 0 + + + BRR_1 + Ready to read buffer + 0x1 + + + + + CINS + Card Insertion + 0x6 + 1 + read-write + oneToClear + + + CINS_0 + Card state unstable or removed + 0 + + + CINS_1 + Card inserted + 0x1 + + + + + CRM + Card Removal + 0x7 + 1 + read-write + oneToClear + + + CRM_0 + Card state unstable or inserted + 0 + + + CRM_1 + Card removed + 0x1 + + + + + CINT + Card Interrupt + 0x8 + 1 + read-write + oneToClear + + + CINT_0 + No Card Interrupt + 0 + + + CINT_1 + Generate Card Interrupt + 0x1 + + + + + RTE + Re-Tuning Event: (only for SD3.0 SDR104 mode) + 0xC + 1 + read-write + oneToClear + + + RTE_0 + Re-Tuning is not required + 0 + + + RTE_1 + Re-Tuning should be performed + 0x1 + + + + + TP + Tuning Pass:(only for SD3.0 SDR104 mode) + 0xE + 1 + read-write + oneToClear + + + CTOE + Command Timeout Error + 0x10 + 1 + read-write + oneToClear + + + CTOE_0 + No Error + 0 + + + CTOE_1 + Time out + 0x1 + + + + + CCE + Command CRC Error + 0x11 + 1 + read-write + oneToClear + + + CCE_0 + No Error + 0 + + + CCE_1 + CRC Error Generated. + 0x1 + + + + + CEBE + Command End Bit Error + 0x12 + 1 + read-write + oneToClear + + + CEBE_0 + No Error + 0 + + + CEBE_1 + End Bit Error Generated + 0x1 + + + + + CIE + Command Index Error + 0x13 + 1 + read-write + oneToClear + + + CIE_0 + No Error + 0 + + + CIE_1 + Error + 0x1 + + + + + DTOE + Data Timeout Error + 0x14 + 1 + read-write + oneToClear + + + DTOE_0 + No Error + 0 + + + DTOE_1 + Time out + 0x1 + + + + + DCE + Data CRC Error + 0x15 + 1 + read-write + oneToClear + + + DCE_0 + No Error + 0 + + + DCE_1 + Error + 0x1 + + + + + DEBE + Data End Bit Error + 0x16 + 1 + read-write + oneToClear + + + DEBE_0 + No Error + 0 + + + DEBE_1 + Error + 0x1 + + + + + AC12E + Auto CMD12 Error + 0x18 + 1 + read-write + oneToClear + + + AC12E_0 + No Error + 0 + + + AC12E_1 + Error + 0x1 + + + + + TNE + Tuning Error: (only for SD3.0 SDR104 mode) + 0x1A + 1 + read-write + oneToClear + + + DMAE + DMA Error + 0x1C + 1 + read-write + oneToClear + + + DMAE_0 + No Error + 0 + + + DMAE_1 + Error + 0x1 + + + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCSEN + Command Complete Status Enable + 0 + 1 + read-write + + + CCSEN_0 + Masked + 0 + + + CCSEN_1 + Enabled + 0x1 + + + + + TCSEN + Transfer Complete Status Enable + 0x1 + 1 + read-write + + + TCSEN_0 + Masked + 0 + + + TCSEN_1 + Enabled + 0x1 + + + + + BGESEN + Block Gap Event Status Enable + 0x2 + 1 + read-write + + + BGESEN_0 + Masked + 0 + + + BGESEN_1 + Enabled + 0x1 + + + + + DINTSEN + DMA Interrupt Status Enable + 0x3 + 1 + read-write + + + DINTSEN_0 + Masked + 0 + + + DINTSEN_1 + Enabled + 0x1 + + + + + BWRSEN + Buffer Write Ready Status Enable + 0x4 + 1 + read-write + + + BWRSEN_0 + Masked + 0 + + + BWRSEN_1 + Enabled + 0x1 + + + + + BRRSEN + Buffer Read Ready Status Enable + 0x5 + 1 + read-write + + + BRRSEN_0 + Masked + 0 + + + BRRSEN_1 + Enabled + 0x1 + + + + + CINSSEN + Card Insertion Status Enable + 0x6 + 1 + read-write + + + CINSSEN_0 + Masked + 0 + + + CINSSEN_1 + Enabled + 0x1 + + + + + CRMSEN + Card Removal Status Enable + 0x7 + 1 + read-write + + + CRMSEN_0 + Masked + 0 + + + CRMSEN_1 + Enabled + 0x1 + + + + + CINTSEN + Card Interrupt Status Enable + 0x8 + 1 + read-write + + + CINTSEN_0 + Masked + 0 + + + CINTSEN_1 + Enabled + 0x1 + + + + + RTESEN + Re-Tuning Event Status Enable + 0xC + 1 + read-write + + + RTESEN_0 + Masked + 0 + + + RTESEN_1 + Enabled + 0x1 + + + + + TPSEN + Tuning Pass Status Enable + 0xE + 1 + read-write + + + TPSEN_0 + Masked + 0 + + + TPSEN_1 + Enabled + 0x1 + + + + + CTOESEN + Command Timeout Error Status Enable + 0x10 + 1 + read-write + + + CTOESEN_0 + Masked + 0 + + + CTOESEN_1 + Enabled + 0x1 + + + + + CCESEN + Command CRC Error Status Enable + 0x11 + 1 + read-write + + + CCESEN_0 + Masked + 0 + + + CCESEN_1 + Enabled + 0x1 + + + + + CEBESEN + Command End Bit Error Status Enable + 0x12 + 1 + read-write + + + CEBESEN_0 + Masked + 0 + + + CEBESEN_1 + Enabled + 0x1 + + + + + CIESEN + Command Index Error Status Enable + 0x13 + 1 + read-write + + + CIESEN_0 + Masked + 0 + + + CIESEN_1 + Enabled + 0x1 + + + + + DTOESEN + Data Timeout Error Status Enable + 0x14 + 1 + read-write + + + DTOESEN_0 + Masked + 0 + + + DTOESEN_1 + Enabled + 0x1 + + + + + DCESEN + Data CRC Error Status Enable + 0x15 + 1 + read-write + + + DCESEN_0 + Masked + 0 + + + DCESEN_1 + Enabled + 0x1 + + + + + DEBESEN + Data End Bit Error Status Enable + 0x16 + 1 + read-write + + + DEBESEN_0 + Masked + 0 + + + DEBESEN_1 + Enabled + 0x1 + + + + + AC12ESEN + Auto CMD12 Error Status Enable + 0x18 + 1 + read-write + + + AC12ESEN_0 + Masked + 0 + + + AC12ESEN_1 + Enabled + 0x1 + + + + + TNESEN + Tuning Error Status Enable + 0x1A + 1 + read-write + + + TNESEN_0 + Masked + 0 + + + TNESEN_1 + Enabled + 0x1 + + + + + DMAESEN + DMA Error Status Enable + 0x1C + 1 + read-write + + + DMAESEN_0 + Masked + 0 + + + DMAESEN_1 + Enabled + 0x1 + + + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + Command Complete Interrupt Enable + 0 + 1 + read-write + + + CCIEN_0 + Masked + 0 + + + CCIEN_1 + Enabled + 0x1 + + + + + TCIEN + Transfer Complete Interrupt Enable + 0x1 + 1 + read-write + + + TCIEN_0 + Masked + 0 + + + TCIEN_1 + Enabled + 0x1 + + + + + BGEIEN + Block Gap Event Interrupt Enable + 0x2 + 1 + read-write + + + BGEIEN_0 + Masked + 0 + + + BGEIEN_1 + Enabled + 0x1 + + + + + DINTIEN + DMA Interrupt Enable + 0x3 + 1 + read-write + + + DINTIEN_0 + Masked + 0 + + + DINTIEN_1 + Enabled + 0x1 + + + + + BWRIEN + Buffer Write Ready Interrupt Enable + 0x4 + 1 + read-write + + + BWRIEN_0 + Masked + 0 + + + BWRIEN_1 + Enabled + 0x1 + + + + + BRRIEN + Buffer Read Ready Interrupt Enable + 0x5 + 1 + read-write + + + BRRIEN_0 + Masked + 0 + + + BRRIEN_1 + Enabled + 0x1 + + + + + CINSIEN + Card Insertion Interrupt Enable + 0x6 + 1 + read-write + + + CINSIEN_0 + Masked + 0 + + + CINSIEN_1 + Enabled + 0x1 + + + + + CRMIEN + Card Removal Interrupt Enable + 0x7 + 1 + read-write + + + CRMIEN_0 + Masked + 0 + + + CRMIEN_1 + Enabled + 0x1 + + + + + CINTIEN + Card Interrupt Interrupt Enable + 0x8 + 1 + read-write + + + CINTIEN_0 + Masked + 0 + + + CINTIEN_1 + Enabled + 0x1 + + + + + RTEIEN + Re-Tuning Event Interrupt Enable + 0xC + 1 + read-write + + + RTEIEN_0 + Masked + 0 + + + RTEIEN_1 + Enabled + 0x1 + + + + + TPIEN + Tuning Pass Interrupt Enable + 0xE + 1 + read-write + + + TPIEN_0 + Masked + 0 + + + TPIEN_1 + Enabled + 0x1 + + + + + CTOEIEN + Command Timeout Error Interrupt Enable + 0x10 + 1 + read-write + + + CTOEIEN_0 + Masked + 0 + + + CTOEIEN_1 + Enabled + 0x1 + + + + + CCEIEN + Command CRC Error Interrupt Enable + 0x11 + 1 + read-write + + + CCEIEN_0 + Masked + 0 + + + CCEIEN_1 + Enabled + 0x1 + + + + + CEBEIEN + Command End Bit Error Interrupt Enable + 0x12 + 1 + read-write + + + CEBEIEN_0 + Masked + 0 + + + CEBEIEN_1 + Enabled + 0x1 + + + + + CIEIEN + Command Index Error Interrupt Enable + 0x13 + 1 + read-write + + + CIEIEN_0 + Masked + 0 + + + CIEIEN_1 + Enabled + 0x1 + + + + + DTOEIEN + Data Timeout Error Interrupt Enable + 0x14 + 1 + read-write + + + DTOEIEN_0 + Masked + 0 + + + DTOEIEN_1 + Enabled + 0x1 + + + + + DCEIEN + Data CRC Error Interrupt Enable + 0x15 + 1 + read-write + + + DCEIEN_0 + Masked + 0 + + + DCEIEN_1 + Enabled + 0x1 + + + + + DEBEIEN + Data End Bit Error Interrupt Enable + 0x16 + 1 + read-write + + + DEBEIEN_0 + Masked + 0 + + + DEBEIEN_1 + Enabled + 0x1 + + + + + AC12EIEN + Auto CMD12 Error Interrupt Enable + 0x18 + 1 + read-write + + + AC12EIEN_0 + Masked + 0 + + + AC12EIEN_1 + Enabled + 0x1 + + + + + TNEIEN + Tuning Error Interrupt Enable + 0x1A + 1 + read-write + + + TNEIEN_0 + Masked + 0 + + + TNEIEN_1 + Enabled + 0x1 + + + + + DMAEIEN + DMA Error Interrupt Enable + 0x1C + 1 + read-write + + + DMAEIEN_0 + Masked + 0 + + + DMAEIEN_1 + Enable + 0x1 + + + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + AC12NE + Auto CMD12 Not Executed + 0 + 1 + read-only + + + AC12NE_0 + Executed + 0 + + + AC12NE_1 + Not executed + 0x1 + + + + + AC12TOE + Auto CMD12 / 23 Timeout Error + 0x1 + 1 + read-only + + + AC12TOE_0 + No error + 0 + + + AC12TOE_1 + Time out + 0x1 + + + + + AC12EBE + Auto CMD12 / 23 End Bit Error + 0x2 + 1 + read-only + + + AC12EBE_0 + No error + 0 + + + AC12EBE_1 + End Bit Error Generated + 0x1 + + + + + AC12CE + Auto CMD12 / 23 CRC Error + 0x3 + 1 + read-only + + + AC12CE_0 + No CRC error + 0 + + + AC12CE_1 + CRC Error Met in Auto CMD12/23 Response + 0x1 + + + + + AC12IE + Auto CMD12 / 23 Index Error + 0x4 + 1 + read-only + + + AC12IE_0 + No error + 0 + + + AC12IE_1 + Error, the CMD index in response is not CMD12/23 + 0x1 + + + + + CNIBAC12E + Command Not Issued By Auto CMD12 Error + 0x7 + 1 + read-only + + + CNIBAC12E_0 + No error + 0 + + + CNIBAC12E_1 + Not Issued + 0x1 + + + + + EXECUTE_TUNING + Execute Tuning + 0x16 + 1 + read-write + + + SMP_CLK_SEL + Sample Clock Select + 0x17 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data + 0x1 + + + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-write + 0x7F3B407 + 0xFFFFFFFF + + + SDR50_SUPPORT + SDR50 support + 0 + 1 + read-only + + + SDR104_SUPPORT + SDR104 support + 0x1 + 1 + read-only + + + DDR50_SUPPORT + DDR50 support + 0x2 + 1 + read-only + + + TIME_COUNT_RETUNING + Time Counter for Retuning + 0x8 + 4 + read-write + + + USE_TUNING_SDR50 + Use Tuning for SDR50 + 0xD + 1 + read-write + + + USE_TUNING_SDR50_0 + SDR does not require tuning + 0 + + + USE_TUNING_SDR50_1 + SDR50 requires tuning + 0x1 + + + + + RETUNING_MODE + Retuning Mode + 0xE + 2 + read-only + + + RETUNING_MODE_0 + Mode 1 + 0 + + + RETUNING_MODE_1 + Mode 2 + 0x1 + + + RETUNING_MODE_2 + Mode 3 + 0x2 + + + + + MBL + Max Block Length + 0x10 + 3 + read-only + + + MBL_0 + 512 bytes + 0 + + + MBL_1 + 1024 bytes + 0x1 + + + MBL_2 + 2048 bytes + 0x2 + + + MBL_3 + 4096 bytes + 0x3 + + + + + ADMAS + ADMA Support + 0x14 + 1 + read-only + + + ADMAS_0 + Advanced DMA Not supported + 0 + + + ADMAS_1 + Advanced DMA Supported + 0x1 + + + + + HSS + High Speed Support + 0x15 + 1 + read-only + + + HSS_0 + High Speed Not Supported + 0 + + + HSS_1 + High Speed Supported + 0x1 + + + + + DMAS + DMA Support + 0x16 + 1 + read-only + + + DMAS_0 + DMA not supported + 0 + + + DMAS_1 + DMA Supported + 0x1 + + + + + SRS + Suspend / Resume Support + 0x17 + 1 + read-only + + + SRS_0 + Not supported + 0 + + + SRS_1 + Supported + 0x1 + + + + + VS33 + Voltage Support 3.3V + 0x18 + 1 + read-only + + + VS33_0 + 3.3V not supported + 0 + + + VS33_1 + 3.3V supported + 0x1 + + + + + VS30 + Voltage Support 3.0 V + 0x19 + 1 + read-only + + + VS30_0 + 3.0V not supported + 0 + + + VS30_1 + 3.0V supported + 0x1 + + + + + VS18 + Voltage Support 1.8 V + 0x1A + 1 + read-only + + + VS18_0 + 1.8V not supported + 0 + + + VS18_1 + 1.8V supported + 0x1 + + + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + Read Watermark Level + 0 + 8 + read-write + + + RD_BRST_LEN + Read Burst Length Due to system restriction, the actual burst length may not exceed 16. + 0x8 + 5 + read-write + + + WR_WML + Write Watermark Level + 0x10 + 8 + read-write + + + WR_BRST_LEN + Write Burst Length Due to system restriction, the actual burst length may not exceed 16. + 0x18 + 5 + read-write + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + DMA Enable + 0 + 1 + read-write + + + DMAEN_0 + Disable + 0 + + + DMAEN_1 + Enable + 0x1 + + + + + BCEN + Block Count Enable + 0x1 + 1 + read-write + + + BCEN_0 + Disable + 0 + + + BCEN_1 + Enable + 0x1 + + + + + AC12EN + Auto CMD12 Enable + 0x2 + 1 + read-write + + + AC12EN_0 + Disable + 0 + + + AC12EN_1 + Enable + 0x1 + + + + + DDR_EN + Dual Data Rate mode selection + 0x3 + 1 + read-write + + + DTDSEL + Data Transfer Direction Select + 0x4 + 1 + read-write + + + DTDSEL_0 + Write (Host to Card) + 0 + + + DTDSEL_1 + Read (Card to Host) + 0x1 + + + + + MSBSEL + Multi / Single Block Select + 0x5 + 1 + read-write + + + MSBSEL_0 + Single Block + 0 + + + MSBSEL_1 + Multiple Blocks + 0x1 + + + + + NIBBLE_POS + In DDR 4-bit mode nibble position indictation + 0x6 + 1 + read-write + + + AC23EN + Auto CMD23 Enable + 0x7 + 1 + read-write + + + EXE_TUNE + Execute Tuning: (Only used for SD3.0, SDR104 mode) + 0x16 + 1 + read-write + + + EXE_TUNE_0 + Not Tuned or Tuning Completed + 0 + + + EXE_TUNE_1 + Execute Tuning + 0x1 + + + + + SMP_CLK_SEL + When STD_TUNING_EN is 0, this bit is used to select Tuned clock or Fixed clock to sample data / cmd (Only used for SD3 + 0x17 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data / cmd + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data / cmd + 0x1 + + + + + AUTO_TUNE_EN + Auto Tuning Enable (Only used for SD3.0, SDR104 mode) + 0x18 + 1 + read-write + + + AUTO_TUNE_EN_0 + Disable auto tuning + 0 + + + AUTO_TUNE_EN_1 + Enable auto tuning + 0x1 + + + + + FBCLK_SEL + Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode) + 0x19 + 1 + read-write + + + FBCLK_SEL_0 + Feedback clock comes from the loopback CLK + 0 + + + FBCLK_SEL_1 + Feedback clock comes from the ipp_card_clk_out + 0x1 + + + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + Force Event Auto Command 12 Not Executed + 0 + 1 + write-only + + + FEVTAC12TOE + Force Event Auto Command 12 Time Out Error + 0x1 + 1 + write-only + + + FEVTAC12CE + Force Event Auto Command 12 CRC Error + 0x2 + 1 + write-only + + + FEVTAC12EBE + Force Event Auto Command 12 End Bit Error + 0x3 + 1 + write-only + + + FEVTAC12IE + Force Event Auto Command 12 Index Error + 0x4 + 1 + write-only + + + FEVTCNIBAC12E + Force Event Command Not Executed By Auto Command 12 Error + 0x7 + 1 + write-only + + + FEVTCTOE + Force Event Command Time Out Error + 0x10 + 1 + write-only + + + FEVTCCE + Force Event Command CRC Error + 0x11 + 1 + write-only + + + FEVTCEBE + Force Event Command End Bit Error + 0x12 + 1 + write-only + + + FEVTCIE + Force Event Command Index Error + 0x13 + 1 + write-only + + + FEVTDTOE + Force Event Data Time Out Error + 0x14 + 1 + write-only + + + FEVTDCE + Force Event Data CRC Error + 0x15 + 1 + write-only + + + FEVTDEBE + Force Event Data End Bit Error + 0x16 + 1 + write-only + + + FEVTAC12E + Force Event Auto Command 12 Error + 0x18 + 1 + write-only + + + FEVTTNE + Force Tuning Error + 0x1A + 1 + write-only + + + FEVTDMAE + Force Event DMA Error + 0x1C + 1 + write-only + + + FEVTCINT + Force Event Card Interrupt + 0x1F + 1 + write-only + + + + + ADMA_ERR_STATUS + ADMA Error Status Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + ADMA Error State (when ADMA Error is occurred) + 0 + 2 + read-only + + + ADMALME + ADMA Length Mismatch Error + 0x2 + 1 + read-only + + + ADMALME_0 + No Error + 0 + + + ADMALME_1 + Error + 0x1 + + + + + ADMADCE + ADMA Descritor Error + 0x3 + 1 + read-only + + + ADMADCE_0 + No Error + 0 + + + ADMADCE_1 + Error + 0x1 + + + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADS_ADDR + ADMA System Address + 0x2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL + 0 + 1 + read-write + + + DLL_CTRL_RESET + Setting this bit to 1 force a reset on DLL + 0x1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately + 0x2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + The delay target for the USDHC loopback read clock can be programmed in 1/16th increments of an ref_clock half-period + 0x3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + Set this bit to 1 to prevent the DLL from updating (since when clock_in exists, glitches may appear during DLL updates) + 0x7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override + 0x8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + When SLV_OVERRIDE = 1 This field is used to select 1 of 128 physical taps manually + 0x9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + Refer to DLL_CTRL_SLV_DLY_TARGET0 below. + 0x10 + 3 + read-write + + + DLL_CTRL_SLV_UPDATE_INT + Slave delay line update interval + 0x14 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + DLL control loop update interval + 0x1C + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + Reference DLL lock status + 0x1 + 1 + read-only + + + DLL_STS_SLV_SEL + Slave delay line select status + 0x2 + 7 + read-only + + + DLL_STS_REF_SEL + Reference delay line select taps. This is encoded by 7 bits for 127 taps. + 0x9 + 7 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + Set the number of delay cells on the feedback clock between CLK_OUT and CLK_POST. + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + Set the number of delay cells on the feedback clock between CLK_PRE and CLK_OUT. + 0x4 + 4 + read-write + + + DLY_CELL_SET_PRE + Set the number of delay cells on the feedback clock between the feedback clock and CLK_PRE. + 0x8 + 7 + read-write + + + NXT_ERR + NXT error which means the number of delay cells added on the feedback clock is too large + 0xF + 1 + read-only + + + TAP_SEL_POST + Reflect the number of delay cells added on the feedback clock between CLK_OUT and CLK_POST. + 0x10 + 4 + read-only + + + TAP_SEL_OUT + Reflect the number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT. + 0x14 + 4 + read-only + + + TAP_SEL_PRE + Reflects the number of delay cells added on the feedback clock between the feedback clock and CLK_PRE + 0x18 + 7 + read-only + + + PRE_ERR + PRE error which means the number of delay cells added on the feedback clock is too small + 0x1F + 1 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + EXT_DMA_EN + External DMA Request Enable + 0 + 1 + read-write + + + EXT_DMA_EN_0 + In any scenario, USDHC does not send out external DMA request. + 0 + + + EXT_DMA_EN_1 + When internal DMA is not active, the external DMA request will be sent out. + 0x1 + + + + + VSELECT + Voltage Selection + 0x1 + 1 + read-write + + + VSELECT_0 + Change the voltage to high voltage range, around 3.0 V + 0 + + + VSELECT_1 + Change the voltage to low voltage range, around 1.8 V + 0x1 + + + + + CONFLICT_CHK_EN + Conflict check enable. + 0x2 + 1 + read-write + + + CONFLICT_CHK_EN_0 + Conflict check disable + 0 + + + CONFLICT_CHK_EN_1 + Conflict check enable + 0x1 + + + + + AC12_WR_CHKBUSY_EN + Check busy enable after auto CMD12 for write data packet + 0x3 + 1 + read-write + + + AC12_WR_CHKBUSY_EN_0 + Do not check busy after auto CMD12 for write data packet + 0 + + + AC12_WR_CHKBUSY_EN_1 + Check busy after auto CMD12 for write data packet + 0x1 + + + + + DAT3_CD_POL + Only for debug. Polarity of DATA3 pin when it is used as card detection. + 0x4 + 1 + read-write + + + DAT3_CD_POL_0 + Card detected when DATA3 is high. + 0 + + + DAT3_CD_POL_1 + Card detected when DATA3 is low. + 0x1 + + + + + CD_POL + Only for debug. Polarity of the CD_B pin: + 0x5 + 1 + read-write + + + CD_POL_0 + CD_B pin is low active. + 0 + + + CD_POL_1 + CD_B pin is high active. + 0x1 + + + + + WP_POL + Only for debug. Polarity of the WP pin: + 0x6 + 1 + read-write + + + WP_POL_0 + WP pin is high active. + 0 + + + WP_POL_1 + WP pin is low active. + 0x1 + + + + + CLKONJ_IN_ABORT + Only for debug. Force CLK output active when sending Abort command: + 0x7 + 1 + read-write + + + CLKONJ_IN_ABORT_0 + The CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full (for read) or empty (for write). + 0 + + + CLKONJ_IN_ABORT_1 + The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full (for read) or empty (for write). + 0x1 + + + + + FRC_SDCLK_ON + Force CLK output active + 0x8 + 1 + read-write + + + FRC_SDCLK_ON_0 + CLK active or inactive is fully controlled by the hardware. + 0 + + + FRC_SDCLK_ON_1 + Force CLK active. + 0x1 + + + + + IPG_CLK_SOFT_EN + IPG_CLK Software Enable + 0xB + 1 + read-write + + + IPG_CLK_SOFT_EN_0 + Gate off the IPG_CLK + 0 + + + IPG_CLK_SOFT_EN_1 + Enable the IPG_CLK + 0x1 + + + + + HCLK_SOFT_EN + AHB Clock Software Enable + 0xC + 1 + read-write + + + HCLK_SOFT_EN_0 + Gate off the AHB clock. + 0 + + + HCLK_SOFT_EN_1 + Enable the AHB clock. + 0x1 + + + + + IPG_PERCLK_SOFT_EN + IPG_PERCLK Software Enable + 0xD + 1 + read-write + + + IPG_PERCLK_SOFT_EN_0 + Gate off the IPG_PERCLK + 0 + + + IPG_PERCLK_SOFT_EN_1 + Enable the IPG_PERCLK + 0x1 + + + + + CARD_CLK_SOFT_EN + Card Clock Software Enable + 0xE + 1 + read-write + + + CARD_CLK_SOFT_EN_0 + Gate off the sd_clk + 0 + + + CARD_CLK_SOFT_EN_1 + Enable the sd_clk + 0x1 + + + + + CRC_CHK_DIS + CRC Check Disable + 0xF + 1 + read-write + + + CRC_CHK_DIS_0 + Check CRC16 for every read data packet and check CRC bits for every write data packet + 0 + + + CRC_CHK_DIS_1 + Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + 0x1 + + + + + INT_ST_VAL + Internal State Value + 0x10 + 8 + read-only + + + CMD_BYTE_EN + Byte access + 0x1F + 1 + read-write + + + CMD_BYTE_EN_0 + Disable + 0 + + + CMD_BYTE_EN_1 + Enable + 0x1 + + + + + + + MMC_BOOT + MMC Boot Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + Boot ACK time out counter value. + 0 + 4 + read-write + + + DTOCV_ACK_0 + SDCLK x 2^13 + 0 + + + DTOCV_ACK_1 + SDCLK x 2^14 + 0x1 + + + DTOCV_ACK_2 + SDCLK x 2^15 + 0x2 + + + DTOCV_ACK_3 + SDCLK x 2^16 + 0x3 + + + DTOCV_ACK_4 + SDCLK x 2^17 + 0x4 + + + DTOCV_ACK_5 + SDCLK x 2^18 + 0x5 + + + DTOCV_ACK_6 + SDCLK x 2^19 + 0x6 + + + DTOCV_ACK_7 + SDCLK x 2^20 + 0x7 + + + DTOCV_ACK_14 + SDCLK x 2^27 + 0xE + + + DTOCV_ACK_15 + SDCLK x 2^28 + 0xF + + + + + BOOT_ACK + Boot ACK mode select + 0x4 + 1 + read-write + + + BOOT_ACK_0 + No ack + 0 + + + BOOT_ACK_1 + Ack + 0x1 + + + + + BOOT_MODE + Boot mode select + 0x5 + 1 + read-write + + + BOOT_MODE_0 + Normal boot + 0 + + + BOOT_MODE_1 + Alternative boot + 0x1 + + + + + BOOT_EN + Boot mode enable + 0x6 + 1 + read-write + + + BOOT_EN_0 + Fast boot disable + 0 + + + BOOT_EN_1 + Fast boot enable + 0x1 + + + + + AUTO_SABG_EN + During boot, enable auto stop at block gap function + 0x7 + 1 + read-write + + + DISABLE_TIME_OUT + Disable Time Out + 0x8 + 1 + read-write + + + DISABLE_TIME_OUT_0 + Enable time out + 0 + + + DISABLE_TIME_OUT_1 + Disable time out + 0x1 + + + + + BOOT_BLK_CNT + The value defines the Stop At Block Gap value of automatic mode + 0x10 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x6 + 0xFFFFFFFF + + + SDR104_TIMING_DIS + Timeout counter test. This bit only uses for debugging. + 0 + 1 + read-write + + + SDR104_TIMING_DIS_0 + The timeout counter for Ncr changes to 80, Ncrc changes to 21. + 0 + + + SDR104_TIMING_DIS_1 + The timeout counter for Ncr changes to 72, Ncrc changes to 15. + 0x1 + + + + + SDR104_OE_DIS + CMD_OE / DATA_OE logic generation test. This bit only uses for debugging. + 0x1 + 1 + read-write + + + SDR104_OE_DIS_0 + Drive the CMD_OE / DATA_OE for one more clock cycle after the end bit. + 0 + + + SDR104_OE_DIS_1 + Stop to drive the CMD_OE / DATA_OE at once after driving the end bit. + 0x1 + + + + + SDR104_NSD_DIS + Interrupt window after abort command is sent. This bit only uses for debugging. + 0x2 + 1 + read-write + + + SDR104_NSD_DIS_0 + Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent. + 0 + + + SDR104_NSD_DIS_1 + Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent. + 0x1 + + + + + CARD_INT_D3_TEST + Card Interrupt Detection Test + 0x3 + 1 + read-write + + + CARD_INT_D3_TEST_0 + Check the card interrupt only when DATA3 is high. + 0 + + + CARD_INT_D3_TEST_1 + Check the card interrupt by ignoring the status of DATA3. + 0x1 + + + + + TUNING_8bit_EN + Enable the auto tuning circuit to check the DATA[7:0] + 0x4 + 1 + read-write + + + TUNING_8bit_EN_0 + Tuning circuit only checks the DATA[3:0]. + 0 + + + TUNING_8bit_EN_1 + Tuning circuit only checks the DATA0. + 0x1 + + + + + TUNING_1bit_EN + Enable the auto tuning circuit to check the DATA0 only + 0x5 + 1 + read-write + + + TUNING_CMD_EN + Enable the auto tuning circuit to check the CMD line. + 0x6 + 1 + read-write + + + TUNING_CMD_EN_0 + Auto tuning circuit does not check the CMD line. + 0 + + + TUNING_CMD_EN_1 + Auto tuning circuit checks the CMD line. + 0x1 + + + + + CARD_INT_AUTO_CLR_DIS + Disable the feature to clear the Card interrupt status bit when Card Interrupt status enable bit is cleared + 0x7 + 1 + read-write + + + CARD_INT_AUTO_CLR_DIS_0 + Card interrupt status bit (CINT) can be cleared when Card Interrupt status enable bit is 0. + 0 + + + CARD_INT_AUTO_CLR_DIS_1 + Card interrupt status bit (CINT) can only be cleared by writting a 1 to CINT bit. + 0x1 + + + + + ACMD23_ARGU2_EN + Default1 + 0x17 + 1 + read-write + + + ACMD23_ARGU2_EN_0 + Disable + 0 + + + ACMD23_ARGU2_EN_1 + Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. + 0x1 + + + + + + + TUNING_CTRL + Tuning Control Register + 0xCC + 32 + read-write + 0x212800 + 0xFFFFFFFF + + + TUNING_START_TAP + The start dealy cell point when send first CMD19 in tuning procedure. + 0 + 8 + read-write + + + TUNING_COUNTER + The MAX repeat CMD19 times in tuning procedure. + 0x8 + 8 + read-write + + + TUNING_STEP + The increasing delay cell steps in tuning procedure. + 0x10 + 3 + read-write + + + TUNING_WINDOW + Select data window value for auto tuning + 0x14 + 3 + read-write + + + STD_TUNING_EN + Standard tuning circuit and procedure enable: This bit is used to enable standard tuning circuit and procedure + 0x18 + 1 + read-write + + + + + + + USDHC2 + USDHC + USDHC + USDHC2_ + 0x2194000 + + 0 + 0xD0 + registers + + + USDHC2 + 55 + + + + ADC1 + Analog-to-Digital Converter + ADC + ADC1_ + 0x2198000 + + 0 + 0x2C + registers + + + ADC1 + 132 + + + + HC0 + Control register + 0 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 0x7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + HS + Status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COCO0 + Conversion Complete Flag + 0 + 1 + read-only + + + + + R0 + Data result register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + CFG + Configuration register + 0x14 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + ADICLK + Input Clock Select + 0 + 2 + read-write + + + ADICLK_0 + IPG clock + 0 + + + ADICLK_1 + IPG clock divided by 2 + 0x1 + + + ADICLK_3 + Asynchronous clock (ADACK) + 0x3 + + + + + MODE + Conversion Mode Selection + 0x2 + 2 + read-write + + + MODE_0 + 8-bit conversion + 0 + + + MODE_1 + 10-bit conversion + 0x1 + + + MODE_2 + 12-bit conversion + 0x2 + + + + + ADLSMP + Long Sample Time Configuration + 0x4 + 1 + read-write + + + ADLSMP_0 + Short sample mode. + 0 + + + ADLSMP_1 + Long sample mode. + 0x1 + + + + + ADIV + Clock Divide Select + 0x5 + 2 + read-write + + + ADIV_0 + Input clock + 0 + + + ADIV_1 + Input clock / 2 + 0x1 + + + ADIV_2 + Input clock / 4 + 0x2 + + + ADIV_3 + Input clock / 8 + 0x3 + + + + + ADLPC + Low-Power Configuration + 0x7 + 1 + read-write + + + ADLPC_0 + ADC hard block not in low power mode. + 0 + + + ADLPC_1 + ADC hard block in low power mode. + 0x1 + + + + + ADSTS + Defines the sample time duration + 0x8 + 2 + read-write + + + ADSTS_0 + Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + 0 + + + ADSTS_1 + Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + 0x1 + + + ADSTS_2 + Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + 0x2 + + + ADSTS_3 + Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + 0x3 + + + + + ADHSC + High Speed Configuration + 0xA + 1 + read-write + + + ADHSC_0 + Normal conversion selected. + 0 + + + ADHSC_1 + High speed conversion selected. + 0x1 + + + + + REFSEL + Voltage Reference Selection + 0xB + 2 + read-write + + + REFSEL_0 + Selects VREFH/VREFL as reference voltage. + 0 + + + + + ADTRG + Conversion Trigger Select + 0xD + 1 + read-write + + + ADTRG_0 + Software trigger selected + 0 + + + + + AVGS + Hardware Average select + 0xE + 2 + read-write + + + AVGS_0 + 4 samples averaged + 0 + + + AVGS_1 + 8 samples averaged + 0x1 + + + AVGS_2 + 16 samples averaged + 0x2 + + + AVGS_3 + 32 samples averaged + 0x3 + + + + + OVWREN + Data Overwrite Enable + 0x10 + 1 + read-write + + + OVWREN_0 + Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + 0 + + + OVWREN_1 + Enable the overwriting. + 0x1 + + + + + + + GC + General control register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACKEN + Asynchronous clock output enable + 0 + 1 + read-write + + + ADACKEN_0 + Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + 0 + + + ADACKEN_1 + Asynchronous clock and clock output enabled regardless of the state of the ADC + 0x1 + + + + + DMAEN + DMA Enable + 0x1 + 1 + read-write + + + DMAEN_0 + DMA disabled (default) + 0 + + + DMAEN_1 + DMA enabled + 0x1 + + + + + ACREN + Compare Function Range Enable + 0x2 + 1 + read-write + + + ACREN_0 + Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + 0 + + + ACREN_1 + Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + 0x1 + + + + + ACFGT + Compare Function Greater Than Enable + 0x3 + 1 + read-write + + + ACFGT_0 + Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + 0 + + + ACFGT_1 + Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + 0x1 + + + + + ACFE + Compare Function Enable + 0x4 + 1 + read-write + + + ACFE_0 + Compare function disabled + 0 + + + ACFE_1 + Compare function enabled + 0x1 + + + + + AVGE + Hardware average enable + 0x5 + 1 + read-write + + + AVGE_0 + Hardware average function disabled + 0 + + + AVGE_1 + Hardware average function enabled + 0x1 + + + + + ADCO + Continuous Conversion Enable + 0x6 + 1 + read-write + + + ADCO_0 + One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0 + + + ADCO_1 + Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0x1 + + + + + CAL + Calibration + 0x7 + 1 + read-write + + + + + GS + General status register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACT + Conversion Active + 0 + 1 + read-only + + + ADACT_0 + Conversion not in progress. + 0 + + + ADACT_1 + Conversion in progress. + 0x1 + + + + + CALF + Calibration Failed Flag + 0x1 + 1 + read-write + oneToClear + + + CALF_0 + Calibration completed normally. + 0 + + + CALF_1 + Calibration failed. ADC accuracy specifications are not guaranteed. + 0x1 + + + + + AWKST + Asynchronous wakeup interrupt status + 0x2 + 1 + read-write + oneToClear + + + AWKST_0 + No asynchronous interrupt. + 0 + + + AWKST_1 + Asynnchronous wake up interrupt occured in stop mode. + 0x1 + + + + + + + CV + Compare value register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CV1 + Compare Value 1 + 0 + 12 + read-write + + + CV2 + Compare Value 2 + 0x10 + 12 + read-write + + + + + OFS + Offset correction value register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFS + Offset value + 0 + 12 + read-write + + + SIGN + Sign bit + 0xC + 1 + read-write + + + SIGN_0 + The offset value is added with the raw result + 0 + + + SIGN_1 + The offset value is subtracted from the raw converted value + 0x1 + + + + + + + CAL + Calibration value register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_CODE + Calibration Result Value + 0 + 4 + read-write + + + + + + + ADC_5HC + Analog-to-Digital Converter + ADC_5HC + ADC_5HC_ + 0x219C000 + + 0 + 0x44 + registers + + + ADC_5HC + 133 + + + + HC0 + Control register for hardware triggers + 0 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 0x7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + 4 + 0x4 + 1,2,3,4 + HC%s + Control register for hardware triggers + 0x4 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 0x7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + HS + Status register for HW triggers + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + COCO0 + Conversion Complete Flag + 0 + 1 + read-only + + + COCO1 + See description for COCO0. + 0x1 + 1 + read-only + + + COCO2 + See description for COCO0. + 0x2 + 1 + read-only + + + COCO3 + See description for COCO0. + 0x3 + 1 + read-only + + + COCO4 + See description for COCO0. + 0x4 + 1 + read-only + + + + + R0 + Data result register for HW triggers + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + 4 + 0x4 + 1,2,3,4 + R%s + Data result register for HW triggers + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + CFG + Configuration register + 0x2C + 32 + read-write + 0x200 + 0xFFFFFFFF + + + ADICLK + Input Clock Select + 0 + 2 + read-write + + + ADICLK_0 + IPG clock + 0 + + + ADICLK_1 + IPG clock divided by 2 + 0x1 + + + ADICLK_3 + Asynchronous clock (ADACK) + 0x3 + + + + + MODE + Conversion Mode Selection + 0x2 + 2 + read-write + + + MODE_0 + 8-bit conversion + 0 + + + MODE_1 + 10-bit conversion + 0x1 + + + MODE_2 + 12-bit conversion + 0x2 + + + + + ADLSMP + Long Sample Time Configuration + 0x4 + 1 + read-write + + + ADLSMP_0 + Short sample mode. + 0 + + + ADLSMP_1 + Long sample mode. + 0x1 + + + + + ADIV + Clock Divide Select + 0x5 + 2 + read-write + + + ADIV_0 + Input clock + 0 + + + ADIV_1 + Input clock / 2 + 0x1 + + + ADIV_2 + Input clock / 4 + 0x2 + + + ADIV_3 + Input clock / 8 + 0x3 + + + + + ADLPC + Low-Power Configuration + 0x7 + 1 + read-write + + + ADLPC_0 + ADC hard block not in low power mode. + 0 + + + ADLPC_1 + ADC hard block in low power mode. + 0x1 + + + + + ADSTS + Defines the sample time duration + 0x8 + 2 + read-write + + + ADSTS_0 + Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + 0 + + + ADSTS_1 + Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + 0x1 + + + ADSTS_2 + Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + 0x2 + + + ADSTS_3 + Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + 0x3 + + + + + ADHSC + High Speed Configuration + 0xA + 1 + read-write + + + ADHSC_0 + Normal conversion selected. + 0 + + + ADHSC_1 + High speed conversion selected. + 0x1 + + + + + REFSEL + Voltage Reference Selection + 0xB + 2 + read-write + + + REFSEL_0 + Selects VREFH/VREFL as reference voltage. + 0 + + + + + ADTRG + Conversion Trigger Select + 0xD + 1 + read-write + + + ADTRG_0 + Software trigger selected + 0 + + + ADTRG_1 + Hardware trigger selected + 0x1 + + + + + AVGS + Hardware Average select + 0xE + 2 + read-write + + + AVGS_0 + 4 samples averaged + 0 + + + AVGS_1 + 8 samples averaged + 0x1 + + + AVGS_2 + 16 samples averaged + 0x2 + + + AVGS_3 + 32 samples averaged + 0x3 + + + + + OVWREN + Data Overwrite Enable + 0x10 + 1 + read-write + + + OVWREN_0 + Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + 0 + + + OVWREN_1 + Enable the overwriting. + 0x1 + + + + + + + GC + General control register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACKEN + Asynchronous clock output enable + 0 + 1 + read-write + + + ADACKEN_0 + Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + 0 + + + ADACKEN_1 + Asynchronous clock and clock output enabled regardless of the state of the ADC + 0x1 + + + + + DMAEN + DMA Enable + 0x1 + 1 + read-write + + + DMAEN_0 + DMA disabled (default) + 0 + + + DMAEN_1 + DMA enabled + 0x1 + + + + + ACREN + Compare Function Range Enable + 0x2 + 1 + read-write + + + ACREN_0 + Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + 0 + + + ACREN_1 + Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + 0x1 + + + + + ACFGT + Compare Function Greater Than Enable + 0x3 + 1 + read-write + + + ACFGT_0 + Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + 0 + + + ACFGT_1 + Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + 0x1 + + + + + ACFE + Compare Function Enable + 0x4 + 1 + read-write + + + ACFE_0 + Compare function disabled + 0 + + + ACFE_1 + Compare function enabled + 0x1 + + + + + AVGE + Hardware average enable + 0x5 + 1 + read-write + + + AVGE_0 + Hardware average function disabled + 0 + + + AVGE_1 + Hardware average function enabled + 0x1 + + + + + ADCO + Continuous Conversion Enable + 0x6 + 1 + read-write + + + ADCO_0 + One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0 + + + ADCO_1 + Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0x1 + + + + + CAL + Calibration + 0x7 + 1 + read-write + + + + + GS + General status register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACT + Conversion Active + 0 + 1 + read-only + + + ADACT_0 + Conversion not in progress. + 0 + + + ADACT_1 + Conversion in progress. + 0x1 + + + + + CALF + Calibration Failed Flag + 0x1 + 1 + read-write + oneToClear + + + CALF_0 + Calibration completed normally. + 0 + + + CALF_1 + Calibration failed. ADC accuracy specifications are not guaranteed. + 0x1 + + + + + AWKST + Asynchronous wakeup interrupt status + 0x2 + 1 + read-write + oneToClear + + + AWKST_0 + No asynchronous interrupt. + 0 + + + AWKST_1 + Asynnchronous wake up interrupt occured in stop mode. + 0x1 + + + + + + + CV + Compare value register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CV1 + Compare Value 1 + 0 + 12 + read-write + + + CV2 + Compare Value 2 + 0x10 + 12 + read-write + + + + + OFS + Offset correction value register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + OFS + Offset value + 0 + 12 + read-write + + + SIGN + Sign bit + 0xC + 1 + read-write + + + SIGN_0 + The offset value is added with the raw result + 0 + + + SIGN_1 + The offset value is subtracted from the raw converted value + 0x1 + + + + + + + CAL + Calibration value register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_CODE + Calibration Result Value + 0 + 4 + read-write + + + + + + + I2C1 + I2C + I2C + I2C1_ + 0x21A0000 + I2C + + 0 + 0x12 + registers + + + I2C1 + 68 + + + + IADR + I2C Address Register + 0 + 16 + read-write + 0 + 0xFFFF + + + ADR + Slave address + 0x1 + 7 + read-write + + + + + IFDR + I2C Frequency Divider Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + IC + I2C clock rate + 0 + 6 + read-write + + + + + I2CR + I2C Control Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + RSTA + Repeat start + 0x2 + 1 + write-only + + + RSTA_0 + No repeat start + 0 + + + RSTA_1 + Generates a Repeated Start condition + 0x1 + + + + + TXAK + Transmit acknowledge enable + 0x3 + 1 + read-write + + + TXAK_0 + An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. + 0 + + + TXAK_1 + No acknowledge signal response is sent (that is, the acknowledge bit = 1). + 0x1 + + + + + MTX + Transmit/Receive mode select bit. Selects the direction of master and slave transfers. + 0x4 + 1 + read-write + + + MTX_0 + Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]). + 0 + + + MTX_1 + Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. + 0x1 + + + + + MSTA + Master/Slave mode select bit + 0x5 + 1 + read-write + + + MSTA_0 + Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. + 0 + + + MSTA_1 + Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. + 0x1 + + + + + IIEN + I2C interrupt enable + 0x6 + 1 + read-write + + + IIEN_0 + I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs. + 0 + + + IIEN_1 + I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. + 0x1 + + + + + IEN + I2C enable + 0x7 + 1 + read-write + + + IEN_0 + The block is disabled, but registers can still be accessed. + 0 + + + IEN_1 + The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. + 0x1 + + + + + + + I2SR + I2C Status Register + 0xC + 16 + read-write + 0x81 + 0xFFFF + + + RXAK + Received acknowledge + 0 + 1 + read-only + + + RXAK_0 + An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. + 0 + + + RXAK_1 + A "No acknowledge" signal was detected at the ninth clock. + 0x1 + + + + + IIF + I2C interrupt + 0x1 + 1 + read-write + + + IIF_0 + No I2C interrupt pending. + 0 + + + IIF_1 + An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost. + 0x1 + + + + + SRW + Slave read/write + 0x2 + 1 + read-only + + + SRW_0 + Slave receive, master writing to slave + 0 + + + SRW_1 + Slave transmit, master reading from slave + 0x1 + + + + + IAL + Arbitration lost + 0x4 + 1 + read-write + + + IAL_0 + No arbitration lost. + 0 + + + IAL_1 + Arbitration is lost. + 0x1 + + + + + IBB + I2C bus busy bit + 0x5 + 1 + read-only + + + IBB_0 + Bus is idle. If a Stop signal is detected, IBB is cleared. + 0 + + + IBB_1 + Bus is busy. When Start is detected, IBB is set. + 0x1 + + + + + IAAS + I2C addressed as a slave bit + 0x6 + 1 + read-only + + + IAAS_0 + Not addressed + 0 + + + IAAS_1 + Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. + 0x1 + + + + + ICF + Data transferring bit. While one byte of data is transferred, ICF is cleared. + 0x7 + 1 + read-only + + + ICF_0 + Transfer is in progress. + 0 + + + ICF_1 + Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. + 0x1 + + + + + + + I2DR + I2C Data I/O Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + DATA + Data Byte + 0 + 8 + read-write + + + + + + + I2C2 + I2C + I2C + I2C2_ + 0x21A4000 + + 0 + 0x12 + registers + + + I2C2 + 69 + + + + I2C3 + I2C + I2C + I2C3_ + 0x21A8000 + + 0 + 0x12 + registers + + + I2C3 + 70 + + + + I2C4 + I2C + I2C + I2C4_ + 0x21F8000 + + 0 + 0x12 + registers + + + I2C4 + 67 + + + + ROMC + ROMC + ROMC + ROMC_ + 0x21AC000 + + 0 + 0x20C + registers + + + + 8 + 0x4 + 7,6,5,4,3,2,1,0 + ROMPATCH%sD + ROMC Data Registers + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAX + Data Fix Registers - Stores the data used for 1-word data fix operations + 0 + 32 + read-write + + + + + ROMPATCHCNTL + ROMC Control Register + 0xF4 + 32 + read-write + 0x8400000 + 0xFFFFFFFF + + + DATAFIX + Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine + 0 + 8 + read-write + + + DATAFIX_0 + Address comparator triggers a opcode patch + 0 + + + DATAFIX_1 + Address comparator triggers a data fix + 0x1 + + + + + DIS + ROMC Disable -- This bit, when set, disables all ROMC operations + 0x1D + 1 + read-write + + + DIS_0 + Does not affect any ROMC functions (default) + 0 + + + DIS_1 + Disable all ROMC functions: data fixing, and opcode patching + 0x1 + + + + + + + ROMPATCHENH + ROMC Enable Register High + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ROMPATCHENL + ROMC Enable Register Low + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event + 0 + 16 + read-write + + + ENABLE_0 + Address comparator disabled + 0 + + + ENABLE_1 + Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + 0x1 + + + + + + + 16 + 0x4 + ROMPATCH%sA + ROMC Address Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + THUMBX + THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an ARM opcode patch + 0 + 1 + read-write + + + THUMBX_0 + ARM patch + 0 + + + THUMBX_1 + THUMB patch (ignore if data fix) + 0x1 + + + + + ADDRX + Address Comparator Registers - Indicates the memory address to be watched + 0x1 + 22 + read-write + + + + + ROMPATCHSR + ROMC Status Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB + 0 + 6 + read-only + + + SOURCE_0 + Address Comparator 0 matched + 0 + + + SOURCE_1 + Address Comparator 1 matched + 0x1 + + + SOURCE_15 + Address Comparator 15 matched + 0xF + + + + + SW + ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred + 0x11 + 1 + read-write + oneToClear + + + SW_0 + no event or comparator collisions + 0 + + + SW_1 + a collision has occurred + 0x1 + + + + + + + + + MMDC + MMDC + MMDC + MMDC_ + 0x21B0000 + + 0 + 0x8C4 + registers + + + + MDCTL + MMDC Core Control Register + 0 + 32 + read-write + 0x3110000 + 0xFFFFFFFF + + + DSIZ + DDR data bus size. This field determines the size of the data bus of the DDR memory + 0x10 + 2 + read-write + + + DSIZ_0 + 16-bit data bus + 0 + + + + + BL + Burst Length + 0x13 + 1 + read-write + + + BL_0 + Burst Length 4 is used + 0 + + + BL_1 + Burst Length 8 is used + 0x1 + + + + + COL + Column Address Width + 0x14 + 3 + read-write + + + COL_0 + 9 bits column + 0 + + + COL_1 + 10 bits column + 0x1 + + + COL_2 + 11 bits column + 0x2 + + + COL_3 + 8 bits column + 0x3 + + + COL_4 + 12 bits column + 0x4 + + + + + ROW + Row Address Width + 0x18 + 3 + read-write + + + ROW_0 + 11 bits Row + 0 + + + ROW_1 + 12 bits Row + 0x1 + + + ROW_2 + 13 bits Row + 0x2 + + + ROW_3 + 14 bits Row + 0x3 + + + ROW_4 + 15 bits Row + 0x4 + + + ROW_5 + 16 bits Row + 0x5 + + + + + SDE_1 + MMDC Enable CS1 + 0x1E + 1 + read-write + + + SDE_1_0 + Disabled + 0 + + + SDE_1_1 + Enabled + 0x1 + + + + + SDE_0 + MMDC Enable CS0 + 0x1F + 1 + read-write + + + SDE_0_0 + Disabled + 0 + + + SDE_0_1 + Enabled + 0x1 + + + + + + + MDPDC + MMDC Core Power Down Control Register + 0x4 + 32 + read-write + 0x30012 + 0xFFFFFFFF + + + tCKSRE + Valid clock cycles after self-refresh entry + 0 + 3 + read-write + + + tCKSRE_0 + 0 cycle + 0 + + + tCKSRE_1 + 1 cycles + 0x1 + + + tCKSRE_6 + 6 cycles + 0x6 + + + tCKSRE_7 + 7 cycles + 0x7 + + + + + tCKSRX + Valid clock cycles before self-refresh exit + 0x3 + 3 + read-write + + + tCKSRX_0 + 0 cycle + 0 + + + tCKSRX_1 + 1 cycles + 0x1 + + + tCKSRX_6 + 6 cycles + 0x6 + + + tCKSRX_7 + 7 cycles + 0x7 + + + + + BOTH_CS_PD + Parallel power down entry to both chip selects + 0x6 + 1 + read-write + + + BOTH_CS_PD_0 + Each chip select can enter power down independently according to its configuration. + 0 + + + BOTH_CS_PD_1 + Chip selects can enter power down only if the amount of idle cycles of both chip selects was obtained. + 0x1 + + + + + SLOW_PD + Slow/fast power down + 0x7 + 1 + read-write + + + SLOW_PD_0 + Fast mode. + 0 + + + SLOW_PD_1 + Slow mode. + 0x1 + + + + + PWDT_0 + Power Down Timer - Chip Select 0 + 0x8 + 4 + read-write + + + PWDT_1 + Power Down Timer - Chip Select 1 + 0xC + 4 + read-write + + + tCKE + CKE minimum pulse width. This field determines the minimum pulse width of CKE. + 0x10 + 3 + read-write + + + tCKE_0 + 1 cycle + 0 + + + tCKE_1 + 2 cycles + 0x1 + + + tCKE_6 + 7 cycles + 0x6 + + + tCKE_7 + 8 cycles + 0x7 + + + + + PRCT_0 + Precharge Timer - Chip Select 0 + 0x18 + 3 + read-write + + + PRCT_1 + Precharge Timer - Chip Select 1 + 0x1C + 3 + read-write + + + + + MDOTC + MMDC Core ODT Timing Control Register + 0x8 + 32 + read-write + 0x12272000 + 0xFFFFFFFF + + + tODT_idle_off + ODT turn off latency + 0x4 + 5 + read-write + + + tODT_idle_off_0 + 0 cycle (turned off at the earliest possible time) + 0 + + + tODT_idle_off_1 + 1 cycle + 0x1 + + + tODT_idle_off_2 + 2 cycles + 0x2 + + + tODT_idle_off_30 + 30 cycles + 0x1E + + + tODT_idle_off_31 + 31 cycles + 0x1F + + + + + tODTLon + ODT turn on latency + 0xC + 3 + read-write + + + tODTLon_0 + - 0x1 Reserved + 0 + + + tODTLon_2 + 2 cycles + 0x2 + + + tODTLon_3 + 3 cycles + 0x3 + + + tODTLon_4 + 4 cycles + 0x4 + + + tODTLon_5 + 5 cycles + 0x5 + + + tODTLon_6 + 6 cycles + 0x6 + + + + + tAXPD + Asynchronous ODT to power down exit delay + 0x10 + 4 + read-write + + + tAXPD_0 + 1 clock + 0 + + + tAXPD_1 + 2 clocks + 0x1 + + + tAXPD_2 + 3 clocks + 0x2 + + + tAXPD_14 + 15 clocks + 0xE + + + tAXPD_15 + 16 clocks + 0xF + + + + + tANPD + Asynchronous ODT to power down entry delay + 0x14 + 4 + read-write + + + tANPD_0 + 1 clock + 0 + + + tANPD_1 + 2 clocks + 0x1 + + + tANPD_2 + 3 clocks + 0x2 + + + tANPD_14 + 15 clocks + 0xE + + + tANPD_15 + 16 clocks + 0xF + + + + + tAONPD + Asynchronous RTT turn-on delay (power down with DLL frozen) + 0x18 + 3 + read-write + + + tAONPD_0 + 1 cycle + 0 + + + tAONPD_1 + 2 cycles + 0x1 + + + tAONPD_6 + 7 cycles + 0x6 + + + tAONPD_7 + 8 cycles + 0x7 + + + + + tAOFPD + Asynchronous RTT turn-off delay (power down with DLL frozen) + 0x1B + 3 + read-write + + + tAOFPD_0 + 1 cycle + 0 + + + tAOFPD_1 + 2 cycles + 0x1 + + + tAOFPD_6 + 7 cycles + 0x6 + + + tAOFPD_7 + 8 cycles + 0x7 + + + + + + + MDCFG0 + MMDC Core Timing Configuration Register 0 + 0xC + 32 + read-write + 0x323622D3 + 0xFFFFFFFF + + + tCL + CAS Read Latency + 0 + 4 + read-write + + + tCL_0 + 3 cycles + 0 + + + tCL_1 + 4 cycles + 0x1 + + + tCL_2 + 5 cycles + 0x2 + + + tCL_3 + 6 cycles + 0x3 + + + tCL_4 + 7 cycles + 0x4 + + + tCL_5 + 8 cycles + 0x5 + + + tCL_6 + 9 cycles + 0x6 + + + tCL_7 + 10 cycles + 0x7 + + + tCL_8 + 11 cycles + 0x8 + + + tCL_9 + - 0xF Reserved + 0x9 + + + + + tFAW + Four Active Window (all banks) + 0x4 + 5 + read-write + + + tFAW_0 + 1 clock + 0 + + + tFAW_1 + 2 clocks + 0x1 + + + tFAW_2 + 3 clocks + 0x2 + + + tFAW_30 + 31 clocks + 0x1E + + + tFAW_31 + 32 clocks + 0x1F + + + + + tXPDLL + Exit precharge power down with DLL frozen to commands requiring DLL + 0x9 + 4 + read-write + + + tXPDLL_0 + 1 clock + 0 + + + tXPDLL_1 + 2 clocks + 0x1 + + + tXPDLL_2 + 3 clocks + 0x2 + + + tXPDLL_14 + 15 clocks + 0xE + + + tXPDLL_15 + 16 clocks + 0xF + + + + + tXP + Exit power down with DLL-on to any valid command + 0xD + 3 + read-write + + + tXP_0 + 1 cycle + 0 + + + tXP_1 + 2 cycles + 0x1 + + + tXP_6 + 7 cycles + 0x6 + + + tXP_7 + 8 cycles + 0x7 + + + + + tXS + Exit self refresh to non READ command + 0x10 + 8 + read-write + + + tXS_0 + - 0x15 reserved + 0 + + + tXS_22 + 23 clocks + 0x16 + + + tXS_23 + 24 clocks + 0x17 + + + tXS_254 + 255 clocks + 0xFE + + + tXS_255 + 256 clocks + 0xFF + + + + + tRFC + Refresh command to Active or Refresh command time + 0x18 + 8 + read-write + + + tRFC_0 + 1 clock + 0 + + + tRFC_1 + 2 clocks + 0x1 + + + tRFC_2 + 3 clocks + 0x2 + + + tRFC_254 + 255 clocks + 0xFE + + + tRFC_255 + 256 clocks + 0xFF + + + + + + + MDCFG1 + MMDC Core Timing Configuration Register 1 + 0x10 + 32 + read-write + 0xB6B18A23 + 0xFFFFFFFF + + + tCWL + CAS Write Latency + 0 + 3 + read-write + + + tCWL_0 + 2 cycles (DDR2/DDR3) , 1 cycles (LPDDR2/LPDDR3) + 0 + + + tCWL_1 + 3 cycles (DDR2/DDR3) , 2 cycles (LPDDR2/LPDDR3) + 0x1 + + + tCWL_2 + 4 cycles (DDR2/DDR3) , 3 cycles (LPDDR2/LPDDR3) + 0x2 + + + tCWL_3 + 5 cycles (DDR2/DDR3) , 4 cycles (LPDDR2/LPDDR3) + 0x3 + + + tCWL_4 + 6 cycles (DDR2/DDR3) , 5 cycles (LPDDR2/LPDDR3) + 0x4 + + + tCWL_5 + 7 cycles (DDR2/DDR3) , 6 cycles (LPDDR2/LPDDR3) + 0x5 + + + tCWL_6 + 8 cycles (DDR2/DDR3) , 7 cycles (LPDDR2/LPDDR3) + 0x6 + + + + + tMRD + Mode Register Set command cycle (all banks) + 0x5 + 4 + read-write + + + tMRD_0 + 1 clock + 0 + + + tMRD_1 + 2 clocks + 0x1 + + + tMRD_2 + 3 clocks + 0x2 + + + tMRD_14 + 15 clocks + 0xE + + + tMRD_15 + 16 clocks + 0xF + + + + + tWR + WRITE recovery time (same bank) + 0x9 + 3 + read-write + + + tWR_0 + 1cycle + 0 + + + tWR_1 + 2cycles + 0x1 + + + tWR_2 + 3cycles + 0x2 + + + tWR_3 + 4cycles + 0x3 + + + tWR_4 + 5cycles + 0x4 + + + tWR_5 + 6cycles + 0x5 + + + tWR_6 + 7cycles + 0x6 + + + tWR_7 + 8 cycles + 0x7 + + + + + tRPA + Precharge-all command period + 0xF + 1 + read-write + + + tRPA_0 + Will be equal to: tRP. + 0 + + + tRPA_1 + Will be equal to: tRP+1. + 0x1 + + + + + tRAS + Active to Precharge command period (same bank) + 0x10 + 5 + read-write + + + tRAS_0 + 1 clock + 0 + + + tRAS_1 + 2 clocks + 0x1 + + + tRAS_2 + 3 clocks + 0x2 + + + tRAS_30 + 31 clocks + 0x1E + + + + + tRC + Active to Active or Refresh command period (same bank) + 0x15 + 5 + read-write + + + tRC_0 + 1 clock + 0 + + + tRC_1 + 2 clocks + 0x1 + + + tRC_2 + 3 clocks + 0x2 + + + tRC_30 + 31 clocks + 0x1E + + + tRC_31 + 32 clocks + 0x1F + + + + + tRP + Precharge command period (same bank) + 0x1A + 3 + read-write + + + tRP_0 + 1 clock + 0 + + + tRP_1 + 2 clocks + 0x1 + + + tRP_2 + 3 clocks + 0x2 + + + tRP_3 + 4 clocks + 0x3 + + + tRP_4 + 5 clocks + 0x4 + + + tRP_5 + 6 clocks + 0x5 + + + tRP_6 + 7 clocks + 0x6 + + + tRP_7 + 8 clocks + 0x7 + + + + + tRCD + Active command to internal read or write delay time (same bank) + 0x1D + 3 + read-write + + + tRCD_0 + 1 clock + 0 + + + tRCD_1 + 2 clocks + 0x1 + + + tRCD_2 + 3 clocks + 0x2 + + + tRCD_3 + 4 clocks + 0x3 + + + tRCD_4 + 5 clocks + 0x4 + + + tRCD_5 + 6 clocks + 0x5 + + + tRCD_6 + 7 clocks + 0x6 + + + tRCD_7 + 8 clocks + 0x7 + + + + + + + MDCFG2 + MMDC Core Timing Configuration Register 2 + 0x14 + 32 + read-write + 0xC70092 + 0xFFFFFFFF + + + tRRD + Active to Active command period (all banks) + 0 + 3 + read-write + + + tRRD_0 + 1cycle + 0 + + + tRRD_1 + 2cycles + 0x1 + + + tRRD_2 + 3cycles + 0x2 + + + tRRD_3 + 4cycles + 0x3 + + + tRRD_4 + 5cycles + 0x4 + + + tRRD_5 + 6cycles + 0x5 + + + tRRD_6 + 7cycles + 0x6 + + + + + tWTR + Internal WRITE to READ command delay (same bank) + 0x3 + 3 + read-write + + + tWTR_0 + 1cycle + 0 + + + tWTR_1 + 2cycles + 0x1 + + + tWTR_2 + 3cycles + 0x2 + + + tWTR_3 + 4cycles + 0x3 + + + tWTR_4 + 5cycles + 0x4 + + + tWTR_5 + 6cycles + 0x5 + + + tWTR_6 + 7cycles + 0x6 + + + tWTR_7 + 8 cycles + 0x7 + + + + + tRTP + Internal READ command to Precharge command delay (same bank) + 0x6 + 3 + read-write + + + tRTP_0 + 1cycle + 0 + + + tRTP_1 + 2cycles + 0x1 + + + tRTP_2 + 3cycles + 0x2 + + + tRTP_3 + 4cycles + 0x3 + + + tRTP_4 + 5cycles + 0x4 + + + tRTP_5 + 6cycles + 0x5 + + + tRTP_6 + 7cycles + 0x6 + + + tRTP_7 + 8 cycles + 0x7 + + + + + tDLLK + DLL locking time + 0x10 + 9 + read-write + + + tDLLK_0 + 1 cycle. + 0 + + + tDLLK_1 + 2 cycles. + 0x1 + + + tDLLK_2 + 3 cycles. + 0x2 + + + tDLLK_199 + 200 cycles + 0xC7 + + + tDLLK_510 + 511 cycles. + 0x1FE + + + tDLLK_511 + 512 cycles (JEDEC value for DDR3). + 0x1FF + + + + + + + MDMISC + MMDC Core Miscellaneous Register + 0x18 + 32 + read-write + 0x1600 + 0xFFFFFFFF + + + RST + Software Reset + 0x1 + 1 + read-write + + + RST_0 + Do nothing. + 0 + + + RST_1 + Assert reset to the MMDC. + 0x1 + + + + + DDR_TYPE + DDR TYPE. This field determines the type of the external DDR device. + 0x3 + 2 + read-write + + + DDR_TYPE_0 + DDR3 device is used. + 0 + + + DDR_TYPE_1 + LPDDR2 device is used. + 0x1 + + + + + DDR_4_BANK + Number of banks per DDR device + 0x5 + 1 + read-write + + + DDR_4_BANK_0 + 8 banks device is being used. (Default) + 0 + + + DDR_4_BANK_1 + 4 banks device is being used + 0x1 + + + + + RALAT + Read Additional Latency + 0x6 + 3 + read-write + + + RALAT_0 + no additional latency. + 0 + + + RALAT_1 + 1 cycle additional latency. + 0x1 + + + RALAT_2 + 2 cycles additional latency. + 0x2 + + + RALAT_3 + 3 cycles additional latency. + 0x3 + + + RALAT_4 + 4 cycles additional latency. + 0x4 + + + RALAT_5 + 5 cycles additional latency. + 0x5 + + + RALAT_6 + 6 cycles additional latency. + 0x6 + + + RALAT_7 + 7 cycles additional latency. + 0x7 + + + + + MIF3_MODE + Command prediction working mode + 0x9 + 2 + read-write + + + MIF3_MODE_0 + Disable prediction. + 0 + + + MIF3_MODE_1 + Enable prediction based on : Valid access on first pipe line stage. + 0x1 + + + MIF3_MODE_2 + Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus. + 0x2 + + + MIF3_MODE_3 + Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus, Next miss access from access queue. + 0x3 + + + + + LPDDR2_S2 + LPDDR2 S2 device type indication + 0xB + 1 + read-write + + + LPDDR2_S2_0 + LPDDR2-S4 device is used. + 0 + + + LPDDR2_S2_1 + LPDDR2-S2 device is used. + 0x1 + + + + + BI_ON + Bank Interleaving On + 0xC + 1 + read-write + + + BI_ON_0 + Banks are not interleaved, and address will be decoded as bank-row-column + 0 + + + BI_ON_1 + Banks are interleaved, and address will be decoded as row-bank-column + 0x1 + + + + + WALAT + Write Additional latency + 0x10 + 2 + read-write + + + WALAT_0 + No additional latency required. + 0 + + + WALAT_1 + 1 cycle additional delay + 0x1 + + + WALAT_2 + 2 cycles additional delay + 0x2 + + + WALAT_3 + 3 cycles additional delay + 0x3 + + + + + LHD + Latency hiding disable + 0x12 + 1 + read-write + + + LHD_0 + Latency hiding on. + 0 + + + LHD_1 + Latency hiding disable. + 0x1 + + + + + ADDR_MIRROR + Address mirroring + 0x13 + 1 + read-write + + + ADDR_MIRROR_0 + Address mirroring disabled. + 0 + + + ADDR_MIRROR_1 + Address mirroring enabled. + 0x1 + + + + + CALIB_PER_CS + Number of chip-select for calibration process + 0x14 + 1 + read-write + + + CALIB_PER_CS_0 + Calibration is targetted to CS0 + 0 + + + CALIB_PER_CS_1 + Calibration is targetted to CS1 + 0x1 + + + + + CK1_GATING + Gating the secondary DDR clock + 0x15 + 1 + read-write + + + CK1_GATING_0 + MMDC drives two clocks toward the DDR memory + 0 + + + CK1_GATING_1 + MMDC drives only one clock toward the DDR memory (CK0) + 0x1 + + + + + CS1_RDY + External status device on CS1 + 0x1E + 1 + read-only + + + CS1_RDY_0 + Device in wake-up period. + 0 + + + CS1_RDY_1 + Device is ready for initialization. + 0x1 + + + + + CS0_RDY + External status device on CS0 + 0x1F + 1 + read-only + + + CS0_RDY_0 + Device in wake-up period. + 0 + + + CS0_RDY_1 + Device is ready for initialization. + 0x1 + + + + + + + MDSCR + MMDC Core Special Command Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD_BA + Bank Address + 0 + 3 + read-write + + + CMD_BA_0 + bank address 0 + 0 + + + CMD_BA_1 + bank address 1 + 0x1 + + + CMD_BA_2 + bank address 2 + 0x2 + + + CMD_BA_7 + bank address 7 + 0x7 + + + + + CMD_CS + Chip Select. This field determines which chip select the command is targeted to + 0x3 + 1 + read-write + + + CMD_CS_0 + to Chip-select 0 + 0 + + + CMD_CS_1 + to Chip-select 1 + 0x1 + + + + + CMD + Command + 0x4 + 3 + read-write + + + CMD_0 + Normal operation + 0 + + + CMD_2 + Auto-Refresh Command (set correct CMD_CS). + 0x2 + + + CMD_3 + Load Mode Register Command DDR2/DDR3, set correct CMD_CS, CMD_BA, CMD_ADDR_LSB, CMD_ADDR_MSB), MRW Command (LPDDR2/LPDDR3, set correct CMD_CS, MR_OP, MR_ADDR) + 0x3 + + + CMD_4 + ZQ calibration (DDR2/DDR3, set correct CMD_CS, {CMD_ADDR_MSB,CMD_ADDR_LSB} = 0x400 or 0x0 ) + 0x4 + + + CMD_5 + Precharge all, only if banks open (set correct CMD_CS). + 0x5 + + + CMD_6 + MRR command (LPDDR2/LPDDR3, set correct CMD_CS, MR_ADDR) + 0x6 + + + + + WL_EN + DQS pads direction + 0x9 + 1 + read-write + + + WL_EN_0 + Exit write leveling mode or stay in normal mode. + 0 + + + WL_EN_1 + Write leveling entry command was sent. + 0x1 + + + + + MRR_READ_DATA_VALID + MRR read data valid + 0xA + 1 + read-only + + + MRR_READ_DATA_VALID_0 + Cleared upon the assertion of MRR command + 0 + + + MRR_READ_DATA_VALID_1 + Set after MRR data is valid and stored at MDMRR register. + 0x1 + + + + + CON_ACK + Configuration acknowledge + 0xE + 1 + read-only + + + CON_ACK_0 + Configuration of MMDC registers is forbidden. + 0 + + + CON_ACK_1 + Configuration of MMDC registers is permitted. + 0x1 + + + + + CON_REQ + Configuration request + 0xF + 1 + read-write + + + CON_REQ_0 + No request to configure MMDC. + 0 + + + CON_REQ_1 + A request to configure MMDC is valid + 0x1 + + + + + CMD_ADDR_LSB_MR_ADDR + Command/Address LSB + 0x10 + 8 + read-write + + + CMD_ADDR_MSB_MR_OP + Command/Address MSB + 0x18 + 8 + read-write + + + + + MDREF + MMDC Core Refresh Control Register + 0x20 + 32 + read-write + 0xC000 + 0xFFFFFFFF + + + START_REF + Manual start of refresh cycle + 0 + 1 + read-write + + + START_REF_0 + Do nothing. + 0 + + + START_REF_1 + Start a refresh cycle. + 0x1 + + + + + REFR + Refresh Rate + 0xB + 3 + read-write + + + REFR_0 + 1 refresh + 0 + + + REFR_1 + 2 refreshes + 0x1 + + + REFR_2 + 3 refreshes + 0x2 + + + REFR_3 + 4 refreshes + 0x3 + + + REFR_4 + 5 refreshes + 0x4 + + + REFR_5 + 6 refreshes + 0x5 + + + REFR_6 + 7 refreshes + 0x6 + + + REFR_7 + 8 refreshes + 0x7 + + + + + REF_SEL + Refresh Selector. This bit selects the source of the clock that will trigger each refresh cycle: + 0xE + 2 + read-write + + + REF_SEL_0 + Periodic refresh cycles will be triggered in frequency of 64KHz. + 0 + + + REF_SEL_1 + Periodic refresh cycles will be triggered in frequency of 32KHz. + 0x1 + + + REF_SEL_2 + Periodic refresh cycles will be triggered every amount of cycles that are configured in REF_CNT field. + 0x2 + + + REF_SEL_3 + No refresh cycles will be triggered. + 0x3 + + + + + REF_CNT + Refresh Counter at DDR clock period If REF_SEL equals '2' a refresh cycle will begin every amount of DDR cycles configured in this field + 0x10 + 16 + read-write + + + REF_CNT_1 + 1 cycle. + 0x1 + + + REF_CNT_65534 + 65534 cycles. + 0xFFFE + + + REF_CNT_65535 + 65535 cycles. + 0xFFFF + + + + + + + MDRWD + MMDC Core Read/Write Command Delay Register + 0x2C + 32 + read-write + 0xF9F26D2 + 0xFFFFFFFF + + + RTR_DIFF + Read to read delay for different chip-select + 0 + 3 + read-write + + + RTR_DIFF_0 + 0 cycle + 0 + + + RTR_DIFF_1 + 1 cycle + 0x1 + + + RTR_DIFF_2 + 2 cycles (Default) + 0x2 + + + RTR_DIFF_3 + 3 cycles + 0x3 + + + RTR_DIFF_4 + 4 cycles + 0x4 + + + RTR_DIFF_5 + 5 cycles + 0x5 + + + RTR_DIFF_6 + 6 cycles + 0x6 + + + RTR_DIFF_7 + 7 cycles + 0x7 + + + + + RTW_DIFF + Read to write delay for different chip-select + 0x3 + 3 + read-write + + + RTW_DIFF_0 + 0 cycle + 0 + + + RTW_DIFF_1 + 1 cycle + 0x1 + + + RTW_DIFF_2 + 2 cycles (Default) + 0x2 + + + RTW_DIFF_3 + 3 cycles + 0x3 + + + RTW_DIFF_4 + 4 cycles + 0x4 + + + RTW_DIFF_5 + 5 cycles + 0x5 + + + RTW_DIFF_6 + 6 cycles + 0x6 + + + RTW_DIFF_7 + 7 cycles + 0x7 + + + + + WTW_DIFF + Write to write delay for different chip-select + 0x6 + 3 + read-write + + + WTW_DIFF_0 + 0 cycle + 0 + + + WTW_DIFF_1 + 1 cycle + 0x1 + + + WTW_DIFF_2 + 2 cycles + 0x2 + + + WTW_DIFF_3 + 3 cycles (Default) + 0x3 + + + WTW_DIFF_4 + 4 cycles + 0x4 + + + WTW_DIFF_5 + 5 cycles + 0x5 + + + WTW_DIFF_6 + 6 cycles + 0x6 + + + WTW_DIFF_7 + 7 cycles + 0x7 + + + + + WTR_DIFF + Write to read delay for different chip-select + 0x9 + 3 + read-write + + + WTR_DIFF_0 + 0 cycle + 0 + + + WTR_DIFF_1 + 1 cycle + 0x1 + + + WTR_DIFF_2 + 2 cycles + 0x2 + + + WTR_DIFF_3 + 3 cycles (Default) + 0x3 + + + WTR_DIFF_4 + 4 cycles + 0x4 + + + WTR_DIFF_5 + 5 cycles + 0x5 + + + WTR_DIFF_6 + 6 cycles + 0x6 + + + WTR_DIFF_7 + 7 cycles + 0x7 + + + + + RTW_SAME + Read to write delay for the same chip-select + 0xC + 3 + read-write + + + RTW_SAME_0 + 0 cycle + 0 + + + RTW_SAME_1 + 1 cycle + 0x1 + + + RTW_SAME_2 + 2 cycles (Default) + 0x2 + + + RTW_SAME_3 + 3 cycles + 0x3 + + + RTW_SAME_4 + 4 cycles + 0x4 + + + RTW_SAME_5 + 5 cycles + 0x5 + + + RTW_SAME_6 + 6 cycles + 0x6 + + + RTW_SAME_7 + 7 cycles + 0x7 + + + + + tDAI + Device auto initialization period.(maximum) This field is relevant only to LPDDR2 mode + 0x10 + 13 + read-write + + + tDAI_0 + 1 cycle + 0 + + + tDAI_3999 + 4000 cycles (Default, JEDEC value for LPDDR2, gives 10us at 400MHz clock). + 0xF9F + + + tDAI_8191 + 8192 cycles + 0x1FFF + + + + + + + MDOR + MMDC Core Out of Reset Delays Register + 0x30 + 32 + read-write + 0x9F0E0E + 0xFFFFFFFF + + + RST_to_CKE + DDR3: Time from SDE enable to CKE rise + 0 + 6 + read-write + + + RST_to_CKE_3 + 1 cycles + 0x3 + + + RST_to_CKE_16 + 14 cycles (JEDEC value for LPDDR2) - total of 200 us + 0x10 + + + RST_to_CKE_35 + 33 cycles (JEDEC value for DDR3) - total of 500 us + 0x23 + + + RST_to_CKE_62 + 60 cycles + 0x3E + + + RST_to_CKE_63 + 61 cycles + 0x3F + + + + + SDE_to_RST + DDR3 mode: Time from SDE enable until DDR reset# is high + 0x8 + 6 + read-write + + + SDE_to_RST_3 + 1 cycles + 0x3 + + + SDE_to_RST_4 + 2 cycles + 0x4 + + + SDE_to_RST_16 + 14 cycles (JEDEC value for DDR3) - total of 200 us + 0x10 + + + SDE_to_RST_62 + 60 cycles + 0x3E + + + SDE_to_RST_63 + 61 cycles + 0x3F + + + + + tXPR + DDR2/DDR3: CKE HIGH to a valid command + 0x10 + 8 + read-write + + + tXPR_1 + 2 cycles + 0x1 + + + tXPR_2 + 3 cycles + 0x2 + + + tXPR_254 + 255 cycles + 0xFE + + + tXPR_255 + 256 cycles + 0xFF + + + + + + + MDMRR + MMDC Core MRR Data Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + MRR_READ_DATA0 + MRR DATA that arrived on DQ[7:0] + 0 + 8 + read-only + + + MRR_READ_DATA1 + MRR DATA that arrived on DQ[15:8] + 0x8 + 8 + read-only + + + + + MDCFG3LP + MMDC Core Timing Configuration Register 3 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + tRPab_LP + Precharge (all banks) command period. This field is valid only for LPDDR2 memories + 0 + 4 + read-write + + + tRPab_LP_0 + 1 clock + 0 + + + tRPab_LP_1 + 2 clocks + 0x1 + + + tRPab_LP_2 + 3 clocks + 0x2 + + + tRPab_LP_14 + 15 clocks + 0xE + + + + + tRPpb_LP + Precharge (per bank) command period (same bank). This field is valid only for LPDDR2 memories + 0x4 + 4 + read-write + + + tRPpb_LP_0 + 1 clock + 0 + + + tRPpb_LP_1 + 2 clocks + 0x1 + + + tRPpb_LP_2 + 3 clocks + 0x2 + + + tRPpb_LP_14 + 15 clocks + 0xE + + + + + tRCD_LP + Active command to internal read or write delay time (same bank) + 0x8 + 4 + read-write + + + tRCD_LP_0 + 1 clock + 0 + + + tRCD_LP_1 + 2 clocks + 0x1 + + + tRCD_LP_2 + 3 clocks + 0x2 + + + tRCD_LP_14 + 15 clocks + 0xE + + + + + RC_LP + Active to Active or Refresh command period (same bank) + 0x10 + 6 + read-write + + + RC_LP_0 + 1 clock + 0 + + + RC_LP_1 + 2 clocks + 0x1 + + + RC_LP_2 + 3 clocks + 0x2 + + + RC_LP_62 + 63 clocks + 0x3E + + + + + + + MDMR4 + MMDC Core MR4 Derating Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + UPDATE_DE_REQ + Update Derated Values Request + 0 + 1 + read-write + + + UPDATE_DE_REQ_0 + Do nothing. + 0 + + + UPDATE_DE_REQ_1 + Request to update the following values: tRRD, tRCD, tRP, tRC, tRAS and refresh related fields(MDREF register): REF_CNT, REF_SEL, REFR + 0x1 + + + + + UPDATE_DE_ACK + Update Derated Values Acknowledge + 0x1 + 1 + read-only + + + tRCD_DE + tRCD derating value. + 0x4 + 1 + read-write + + + tRCD_DE_0 + Original tRCD is used. + 0 + + + tRCD_DE_1 + tRCD is derated in 1 cycle. + 0x1 + + + + + tRC_DE + tRC derating value. + 0x5 + 1 + read-write + + + tRC_DE_0 + Original tRC is used. + 0 + + + tRC_DE_1 + tRC is derated in 1 cycle. + 0x1 + + + + + tRAS_DE + tRAS derating value. + 0x6 + 1 + read-write + + + tRAS_DE_0 + Original tRAS is used. + 0 + + + tRAS_DE_1 + tRAS is derated in 1 cycle. + 0x1 + + + + + tRP_DE + tRP derating value. + 0x7 + 1 + read-write + + + tRP_DE_0 + Original tRP is used. + 0 + + + tRP_DE_1 + tRP is derated in 1 cycle. + 0x1 + + + + + tRRD_DE + tRRD derating value. + 0x8 + 1 + read-write + + + tRRD_DE_0 + Original tRRD is used. + 0 + + + tRRD_DE_1 + tRRD is derated in 1 cycle. + 0x1 + + + + + + + MDASP + MMDC Core Address Space Partition Register + 0x40 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + CS0_END + CS0_END + 0 + 7 + read-write + + + + + MAARCR + MMDC Core AXI Reordering Control Register + 0x400 + 32 + read-write + 0x514201F0 + 0xFFFFFFFF + + + ARCR_GUARD + ARCR Guard + 0 + 4 + read-write + + + ARCR_GUARD_0 + 15 (default) + 0 + + + ARCR_GUARD_1 + 16 + 0x1 + + + ARCR_GUARD_15 + 30 + 0xF + + + + + ARCR_DYN_MAX + ARCR Dynamic Maximum + 0x4 + 4 + read-write + + + ARCR_DYN_MAX_0 + 0 + 0 + + + ARCR_DYN_MAX_1 + 1 + 0x1 + + + ARCR_DYN_MAX_15 + 15 (default) + 0xF + + + + + ARCR_DYN_JMP + ARCR Dynamic Jump + 0x8 + 4 + read-write + + + ARCR_ACC_HIT + ARCR Access Hit Rate + 0x10 + 3 + read-write + + + ARCR_PAG_HIT + ARCR Page Hit Rate + 0x14 + 3 + read-write + + + ARCR_RCH_EN + This bit defines whether Real time channel is activated and bypassed all other pending accesses, So accesses with QoS=='F' will be granted the highest priority in the optimization/reordering mechanism Default value is 0x1 - encoding 1 (Enabled) + 0x18 + 1 + read-write + + + ARCR_RCH_EN_0 + normal prioritization, no bypassing + 0 + + + ARCR_RCH_EN_1 + accesses with QoS=='F' bypass the arbitration + 0x1 + + + + + ARCR_REO_DIS + no description available + 0x19 + 1 + read-write + + + ARCR_REO_DIS_0 + MMDC reordering controls only enabled + 0 + + + ARCR_REO_DIS_1 + MMDC reordering controls only disabled + 0x1 + + + + + ARCR_ARB_REO_DIS + no description available + 0x1A + 1 + read-write + + + ARCR_ARB_REO_DIS_0 + MMDC arbitration and reordering controls enabled + 0 + + + ARCR_ARB_REO_DIS_1 + MMDC arbitration and reordering controls disabled + 0x1 + + + + + ARCR_EXC_ERR_EN + This bit defines whether exclusive read/write access violation of AXI 6 + 0x1C + 1 + read-write + + + ARCR_EXC_ERR_EN_0 + violation of AXI exclusive rules (6.2.4) result in OKAY response (rresp/bresp=2'b00) + 0 + + + ARCR_EXC_ERR_EN_1 + violation of AXI exclusive rules (6.2.4) result in SLAVE Error response (rresp/bresp=2'b10) + 0x1 + + + + + ARCR_SEC_ERR_EN + This bit defines whether security read/write access violation result in SLV Error response or in OKAY response Default value is 0x1 - encoding 1(response is SLV Error, rresp/bresp=2'b10) + 0x1E + 1 + read-write + + + ARCR_SEC_ERR_EN_0 + security violation results in OKAY response (rresp/bresp=2'b00) + 0 + + + ARCR_SEC_ERR_EN_1 + security violation results in SLAVE Error response (rresp/bresp=2'b10) + 0x1 + + + + + ARCR_SEC_ERR_LOCK + Once set, this bit locks ARCR_SEC_ERR_EN and prevents from its updating + 0x1F + 1 + read-write + + + ARCR_SEC_ERR_LOCK_0 + ARCR_SEC_ERR_EN is unlocked, so can be updated any moment + 0 + + + ARCR_SEC_ERR_LOCK_1 + ARCR_SEC_ERR_EN is locked, so it can't be updated + 0x1 + + + + + + + MAPSR + MMDC Core Power Saving Control and Status Register + 0x404 + 32 + read-write + 0x1007 + 0xFFFFFFFF + + + PSD + Automatic Power Saving Disable + 0 + 1 + read-write + + + PSD_0 + power saving enabled + 0 + + + PSD_1 + power saving disabled (default) + 0x1 + + + + + PSS + Power Saving Status + 0x4 + 1 + read-only + + + PSS_0 + not in power saving + 0 + + + PSS_1 + power saving + 0x1 + + + + + RIS + Read Idle Status. This read only bit indicates whether read request buffer is idle (empty) or not. + 0x5 + 1 + read-only + + + RIS_0 + idle + 0 + + + RIS_1 + not idle + 0x1 + + + + + WIS + Write Idle Status + 0x6 + 1 + read-only + + + WIS_0 + idle + 0 + + + WIS_1 + not idle + 0x1 + + + + + PST + Automatic Power saving timer + 0x8 + 8 + read-write + + + PST_1 + timer is configured to 64 clock cycles. + 0x1 + + + PST_2 + timer is configured to 128 clock cycles. + 0x2 + + + PST_16 + (Default)- 1024 clock cycles. + 0x10 + + + PST_255 + timer clock is configured to 16320 clock cycles. + 0xFF + + + + + LPMD + General LPMD request + 0x14 + 1 + read-write + + + LPMD_0 + no lpmd request + 0 + + + LPMD_1 + lpmd request + 0x1 + + + + + DVFS + General DVFS request + 0x15 + 1 + read-write + + + DVFS_0 + no dvfs request + 0 + + + DVFS_1 + dvfs request + 0x1 + + + + + LPACK + General low-power acknowledge + 0x18 + 1 + read-only + + + DVACK + General DVFS acknowledge + 0x19 + 1 + read-only + + + + + MAEXIDR0 + MMDC Core Exclusive ID Monitor Register0 + 0x408 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EXC_ID_MONITOR0 + This field defines ID for Exclusive monitor#0. Default value is 0x0000 + 0 + 16 + read-write + + + EXC_ID_MONITOR1 + This field defines ID for Exclusive monitor#1. Default value is 0x0020 + 0x10 + 16 + read-write + + + + + MAEXIDR1 + MMDC Core Exclusive ID Monitor Register1 + 0x40C + 32 + read-write + 0x600040 + 0xFFFFFFFF + + + EXC_ID_MONITOR2 + This field defines ID for Exclusive monitor#2. Default value is 0x0040 + 0 + 16 + read-write + + + EXC_ID_MONITOR3 + This field defines ID for Exclusive monitor#3. Default value is 0x0060 + 0x10 + 16 + read-write + + + + + MADPCR0 + MMDC Core Debug and Profiling Control Register 0 + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DBG_EN + Debug and Profiling Enable + 0 + 1 + read-write + + + DBG_EN_0 + disable + 0 + + + DBG_EN_1 + enable + 0x1 + + + + + DBG_RST + Debug and Profiling Reset. Reset all debug and profiling counters and components. + 0x1 + 1 + read-write + + + DBG_RST_0 + no reset + 0 + + + DBG_RST_1 + reset + 0x1 + + + + + PRF_FRZ + Profiling freeze + 0x2 + 1 + read-write + + + PRF_FRZ_0 + profiling counters are not frozen + 0 + + + PRF_FRZ_1 + profiling counters are frozen + 0x1 + + + + + CYC_OVF + Total Profiling Cycles Count Overflow + 0x3 + 1 + read-write + oneToClear + + + CYC_OVF_0 + no overflow + 0 + + + CYC_OVF_1 + overflow + 0x1 + + + + + SBS_EN + Step By Step debug Enable + 0x8 + 1 + read-write + + + SBS_EN_0 + disable + 0 + + + SBS_EN_1 + enable + 0x1 + + + + + SBS + Step By Step trigger + 0x9 + 1 + read-write + + + SBS_0 + No access will be launched toward the DDR + 0 + + + SBS_1 + Launch AXI pending access toward the DDR + 0x1 + + + + + + + MADPCR1 + MMDC Core Debug and Profiling Control Register 1 + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRF_AXI_ID + Profiling AXI ID + 0 + 16 + read-write + + + PRF_AXI_IDMASK + Profiling AXI ID Mask. AXI ID bits which masked by this value are chosen for profiling. + 0x10 + 16 + read-write + + + PRF_AXI_IDMASK_0 + AXI ID specific bit is ignored (don't care) + 0 + + + PRF_AXI_IDMASK_1 + AXI ID specific bit is chosen for profiling + 0x1 + + + + + + + MADPSR0 + MMDC Core Debug and Profiling Status Register 0 + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + CYC_COUNT + Total Profiling cycle Count + 0 + 32 + read-only + + + + + MADPSR1 + MMDC Core Debug and Profiling Status Register 1 + 0x41C + 32 + read-only + 0 + 0xFFFFFFFF + + + BUSY_COUNT + Profiling Busy Cycles Count + 0 + 32 + read-only + + + + + MADPSR2 + MMDC Core Debug and Profiling Status Register 2 + 0x420 + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_ACC_COUNT + Profiling Read Access Count + 0 + 32 + read-only + + + + + MADPSR3 + MMDC Core Debug and Profiling Status Register 3 + 0x424 + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_ACC_COUNT + Profiling Write Access Count + 0 + 32 + read-only + + + + + MADPSR4 + MMDC Core Debug and Profiling Status Register 4 + 0x428 + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_BYTES_COUNT + Profiling Read Bytes Count + 0 + 32 + read-only + + + + + MADPSR5 + MMDC Core Debug and Profiling Status Register 5 + 0x42C + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_BYTES_COUNT + Profiling Write Bytes Count + 0 + 32 + read-only + + + + + MASBS0 + MMDC Core Step By Step Address Register + 0x430 + 32 + read-only + 0 + 0xFFFFFFFF + + + SBS_ADDR + Step By Step Address + 0 + 32 + read-only + + + + + MASBS1 + MMDC Core Step By Step Address Attributes Register + 0x434 + 32 + read-only + 0 + 0xFFFFFFFF + + + SBS_VLD + Step By Step Valid + 0 + 1 + read-only + + + SBS_VLD_0 + not valid + 0 + + + SBS_VLD_1 + valid + 0x1 + + + + + SBS_TYPE + Step By Step Request Type + 0x1 + 1 + read-only + + + SBS_TYPE_0 + write + 0 + + + SBS_TYPE_1 + read + 0x1 + + + + + SBS_LOCK + Step By Step Lock + 0x2 + 2 + read-only + + + SBS_PROT + Step By Step Protection + 0x4 + 3 + read-only + + + SBS_SIZE + Step By Step Size + 0x7 + 3 + read-only + + + SBS_SIZE_0 + 8 bits + 0 + + + SBS_SIZE_1 + 16 bits + 0x1 + + + SBS_SIZE_2 + 32 bits + 0x2 + + + SBS_SIZE_3 + 64 bits + 0x3 + + + SBS_SIZE_4 + 128bits + 0x4 + + + + + SBS_BURST + Step By Step Burst + 0xA + 2 + read-only + + + SBS_BURST_0 + FIXED + 0 + + + SBS_BURST_1 + INCR burst + 0x1 + + + SBS_BURST_2 + WRAP burst + 0x2 + + + + + SBS_BUFF + Step By Step Buffered + 0xC + 1 + read-only + + + SBS_LEN + Step By Step Length + 0xD + 3 + read-only + + + SBS_LEN_0 + burst of length 1 + 0 + + + SBS_LEN_1 + burst of length 2 + 0x1 + + + SBS_LEN_7 + burst of length 8 + 0x7 + + + + + SBS_AXI_ID + Step By Step AXI ID + 0x10 + 16 + read-only + + + + + MAGENP + MMDC Core General Purpose Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + GP31_GP0 + General purpose read/write bits. + 0 + 32 + read-write + + + + + MPZQHWCTRL + MMDC PHY ZQ HW control register + 0x800 + 32 + read-write + 0xA1380000 + 0xFFFFFFFF + + + ZQ_MODE + ZQ calibration mode: + 0 + 2 + read-write + + + ZQ_MODE_0 + No ZQ calibration is issued. (Default) + 0 + + + ZQ_MODE_1 + ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ long command to the external DDR device only when exiting self refresh. + 0x1 + + + ZQ_MODE_2 + ZQ calibration command long/short is issued only to the external DDR device periodically and when exiting self refresh + 0x2 + + + ZQ_MODE_3 + ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ calibration command long/short to the external DDR device periodically and when exiting self refresh + 0x3 + + + + + ZQ_HW_PER + ZQ periodic calibration time + 0x2 + 4 + read-write + + + ZQ_HW_PER_0 + ZQ calibration is performed every 1 ms. + 0 + + + ZQ_HW_PER_1 + ZQ calibration is performed every 2 ms. + 0x1 + + + ZQ_HW_PER_2 + ZQ calibration is performed every 4 ms. + 0x2 + + + ZQ_HW_PER_10 + ZQ calibration is performed every 1 sec. + 0xA + + + ZQ_HW_PER_14 + ZQ calibration is performed every 16 sec. + 0xE + + + ZQ_HW_PER_15 + ZQ calibration is performed every 32 sec. + 0xF + + + + + ZQ_HW_PU_RES + ZQ automatic calibration pull-up result + 0x6 + 5 + read-only + + + ZQ_HW_PU_RES_0 + Min. resistance. + 0 + + + ZQ_HW_PU_RES_31 + Max. resistance. + 0x1F + + + + + ZQ_HW_PD_RES + ZQ HW calibration pull-down result + 0xB + 5 + read-only + + + ZQ_HW_PD_RES_0 + Max. resistance. + 0 + + + ZQ_HW_PD_RES_31 + Min. resistance. + 0x1F + + + + + ZQ_HW_FOR + Force ZQ automatic calibration process with the i + 0x10 + 1 + read-write + + + TZQ_INIT + Device ZQ long/init time + 0x11 + 3 + read-write + + + TZQ_INIT_2 + 128 cycles + 0x2 + + + TZQ_INIT_3 + 256 cycles + 0x3 + + + TZQ_INIT_4 + 512 cycles - Default (JEDEC value for DDR3) + 0x4 + + + TZQ_INIT_5 + 1024 cycles + 0x5 + + + + + TZQ_OPER + Device ZQ long/oper time + 0x14 + 3 + read-write + + + TZQ_OPER_2 + 128 cycles + 0x2 + + + TZQ_OPER_3 + 256 cycles - Default (JEDEC value for DDR3) + 0x3 + + + TZQ_OPER_4 + 512 cycles + 0x4 + + + TZQ_OPER_5 + 1024 cycles + 0x5 + + + + + TZQ_CS + Device ZQ short time + 0x17 + 3 + read-write + + + TZQ_CS_2 + 128 cycles (Default) + 0x2 + + + TZQ_CS_3 + 256 cycles + 0x3 + + + TZQ_CS_4 + 512 cycles + 0x4 + + + TZQ_CS_5 + 1024 cycles + 0x5 + + + + + ZQ_EARLY_COMPARATOR_EN_TIMER + ZQ early comparator enable timer + 0x1B + 5 + read-write + + + ZQ_EARLY_COMPARATOR_EN_TIMER_0 + - 0x6 Reserved + 0 + + + ZQ_EARLY_COMPARATOR_EN_TIMER_7 + 8 cycles + 0x7 + + + ZQ_EARLY_COMPARATOR_EN_TIMER_20 + 21 cycles (Default) + 0x14 + + + ZQ_EARLY_COMPARATOR_EN_TIMER_30 + 31 cycles + 0x1E + + + ZQ_EARLY_COMPARATOR_EN_TIMER_31 + 32 cycles + 0x1F + + + + + + + MPZQSWCTRL + MMDC PHY ZQ SW control register + 0x804 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZQ_SW_FOR + ZQ SW calibration enable + 0 + 1 + read-write + + + ZQ_SW_RES + ZQ software calibration result. This bit reflects the ZQ calibration voltage comparator value. + 0x1 + 1 + read-only + + + ZQ_SW_RES_0 + Current ZQ calibration voltage is less than VDD/2. + 0 + + + ZQ_SW_RES_1 + Current ZQ calibration voltage is more than VDD/2 + 0x1 + + + + + ZQ_SW_PU_VAL + ZQ software pull-up resistence + 0x2 + 5 + read-write + + + ZQ_SW_PU_VAL_0 + Min. resistance. + 0 + + + ZQ_SW_PU_VAL_31 + Max. resistance. + 0x1F + + + + + ZQ_SW_PD_VAL + ZQ software pull-down resistence + 0x7 + 5 + read-write + + + ZQ_SW_PD_VAL_0 + Max. resistance. + 0 + + + ZQ_SW_PD_VAL_31 + Min. resistance. + 0x1F + + + + + ZQ_SW_PD + ZQ software PU/PD calibration. This bit determines the calibration stage (PU or PD). + 0xC + 1 + read-write + + + ZQ_SW_PD_0 + PU resistor calibration + 0 + + + ZQ_SW_PD_1 + PD resistor calibration + 0x1 + + + + + USE_ZQ_SW_VAL + Use SW ZQ configured value for I/O pads resistor controls + 0xD + 1 + read-write + + + USE_ZQ_SW_VAL_0 + Fields ZQ_HW_PD_VAL & ZQ_HW_PU_VAL will be driven to I/O pads resistor controls. + 0 + + + USE_ZQ_SW_VAL_1 + Fields ZQ_SW_PD_VAL & ZQ_SW_PU_VAL will be driven to I/O pads resistor controls. + 0x1 + + + + + ZQ_CMP_OUT_SMP + Defines the amount of cycles between driving the ZQ signals to the ZQ pad and till sampling the comparator enable output while performing ZQ calibration process with the i + 0x10 + 2 + read-write + + + ZQ_CMP_OUT_SMP_0 + 7 cycles + 0 + + + ZQ_CMP_OUT_SMP_1 + 15 cycles + 0x1 + + + ZQ_CMP_OUT_SMP_2 + 23 cycles + 0x2 + + + ZQ_CMP_OUT_SMP_3 + 31 cycles + 0x3 + + + + + + + MPWLGCR + MMDC PHY Write Leveling Configuration and Error Status Register + 0x808 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_WL_EN + Write-Leveling HW (automatic) enable + 0 + 1 + read-write + + + SW_WL_EN + Write-Leveling SW enable + 0x1 + 1 + read-write + + + SW_WL_CNT_EN + SW write-leveling count down enable + 0x2 + 1 + read-write + + + SW_WL_CNT_EN_0 + MMDC doesn't count 25+15 cycles before issuing write-leveling DQS. + 0 + + + SW_WL_CNT_EN_1 + MMDC counts 25+15 cycles before issuing write-leveling DQS. + 0x1 + + + + + WL_SW_RES0 + Byte0 write-leveling software result + 0x4 + 1 + read-only + + + WL_SW_RES0_0 + DQS0 sampled low CK during SW write-leveling. + 0 + + + WL_SW_RES0_1 + DQS0 sampled high CK during SW write-leveling. + 0x1 + + + + + WL_SW_RES1 + Byte1 write-leveling software result + 0x5 + 1 + read-only + + + WL_SW_RES1_0 + DQS1 sampled low CK during SW write-leveling. + 0 + + + WL_SW_RES1_1 + DQS1 sampled high CK during SW write-leveling. + 0x1 + + + + + WL_HW_ERR0 + Byte0 write-leveling HW calibration error + 0x8 + 1 + read-only + + + WL_HW_ERR0_0 + No error was found on byte0 during write-leveling HW calibration. + 0 + + + WL_HW_ERR0_1 + An error was found on byte0 during write-leveling HW calibration. + 0x1 + + + + + WL_HW_ERR1 + Byte1 write-leveling HW calibration error + 0x9 + 1 + read-only + + + WL_HW_ERR1_0 + No error was found on byte1 during write-leveling HW calibration. + 0 + + + WL_HW_ERR1_1 + An error was found on byte1 during write-leveling HW calibration. + 0x1 + + + + + + + MPWLDECTRL0 + MMDC PHY Write Leveling Delay Control Register 0 + 0x80C + 32 + read-write + 0 + 0xFFFFFFFF + + + WL_DL_ABS_OFFSET0 + Absolute write-leveling delay offset for Byte 0 + 0 + 7 + read-write + + + WL_HC_DEL0 + Write leveling half cycle delay for Byte 0 + 0x8 + 1 + read-write + + + WL_HC_DEL0_0 + No delay is added. + 0 + + + WL_HC_DEL0_1 + Half cycle delay is added. + 0x1 + + + + + WL_CYC_DEL0 + Write leveling cycle delay for Byte 0 + 0x9 + 2 + read-write + + + WL_CYC_DEL0_0 + No delay is added. + 0 + + + WL_CYC_DEL0_1 + 1 cycle delay is added. + 0x1 + + + WL_CYC_DEL0_2 + 2 cycles delay is added. + 0x2 + + + + + WL_DL_ABS_OFFSET1 + Absolute write-leveling delay offset for Byte 1 + 0x10 + 7 + read-write + + + WL_HC_DEL1 + Write leveling half cycle delay for Byte 1 + 0x18 + 1 + read-write + + + WL_HC_DEL1_0 + No delay is added. + 0 + + + WL_HC_DEL1_1 + Half cycle delay is added. + 0x1 + + + + + WL_CYC_DEL1 + Write leveling cycle delay for Byte 1 + 0x19 + 2 + read-write + + + WL_CYC_DEL1_0 + No delay is added. + 0 + + + WL_CYC_DEL1_1 + 1 cycle delay is added. + 0x1 + + + WL_CYC_DEL1_2 + 2 cycles delay is added. + 0x2 + + + + + + + MPWLDLST + MMDC PHY Write Leveling delay-line Status Register + 0x814 + 32 + read-only + 0 + 0xFFFFFFFF + + + WL_DL_UNIT_NUM0 + This field reflects the number of delay units that are actually used by write leveling delay-line 0 + 0 + 7 + read-only + + + WL_DL_UNIT_NUM1 + This field reflects the number of delay units that are actually used by write leveling delay-line 1 + 0x8 + 7 + read-only + + + + + MPODTCTRL + MMDC PHY ODT control register + 0x818 + 32 + read-write + 0 + 0xFFFFFFFF + + + ODT_WR_PAS_EN + Inactive write CS ODT enable + 0 + 1 + read-write + + + ODT_WR_PAS_EN_0 + Inactive CS ODT pin is disabled during write accesses to other CS. + 0 + + + ODT_WR_PAS_EN_1 + Inactive CS ODT pin is enabled during write accesses to other CS. + 0x1 + + + + + ODT_WR_ACT_EN + Active write CS ODT enable + 0x1 + 1 + read-write + + + ODT_WR_ACT_EN_0 + Active CS ODT pin is disabled during write access. + 0 + + + ODT_WR_ACT_EN_1 + Active CS ODT pin is enabled during write access. + 0x1 + + + + + ODT_RD_PAS_EN + Inactive read CS ODT enable + 0x2 + 1 + read-write + + + ODT_RD_PAS_EN_0 + Inactive CS ODT pin is disabled during read accesses to other CS. + 0 + + + ODT_RD_PAS_EN_1 + Inactive CS ODT pin is enabled during read accesses to other CS. + 0x1 + + + + + ODT_RD_ACT_EN + Active read CS ODT enable + 0x3 + 1 + read-write + + + ODT_RD_ACT_EN_0 + Active CS ODT pin is disabled during read access. + 0 + + + ODT_RD_ACT_EN_1 + Active CS ODT pin is enabled during read access. + 0x1 + + + + + ODT0_INT_RES + On chip ODT byte0 resistor - This field determines the Rtt_Nom of the on chip ODT byte0 resistor during read accesses + 0x4 + 3 + read-write + + + ODT0_INT_RES_0 + Rtt_Nom Disabled. + 0 + + + ODT0_INT_RES_1 + Rtt_Nom 120 Ohm + 0x1 + + + ODT0_INT_RES_2 + Rtt_Nom 60 Ohm + 0x2 + + + ODT0_INT_RES_3 + Rtt_Nom 40 Ohm + 0x3 + + + ODT0_INT_RES_4 + Rtt_Nom 30 Ohm + 0x4 + + + ODT0_INT_RES_5 + Rtt_Nom 24 Ohm + 0x5 + + + ODT0_INT_RES_6 + Rtt_Nom 20 Ohm + 0x6 + + + ODT0_INT_RES_7 + Rtt_Nom 17 Ohm + 0x7 + + + + + ODT1_INT_RES + On chip ODT byte1 resistor - This field determines the Rtt_Nom of the on chip ODT byte1 resistor during read accesses + 0x8 + 3 + read-write + + + ODT1_INT_RES_0 + Rtt_Nom Disabled. + 0 + + + ODT1_INT_RES_1 + Rtt_Nom 120 Ohm + 0x1 + + + ODT1_INT_RES_2 + Rtt_Nom 60 Ohm + 0x2 + + + ODT1_INT_RES_3 + Rtt_Nom 40 Ohm + 0x3 + + + ODT1_INT_RES_4 + Rtt_Nom 30 Ohm + 0x4 + + + ODT1_INT_RES_5 + Rtt_Nom 24 Ohm + 0x5 + + + ODT1_INT_RES_6 + Rtt_Nom 20 Ohm + 0x6 + + + ODT1_INT_RES_7 + Rtt_Nom 17 Ohm + 0x7 + + + + + + + MPRDDQBY0DL + MMDC PHY Read DQ Byte0 Delay Register + 0x81C + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq0_del + Read dqs0 to dq0 delay fine-tuning + 0 + 3 + read-write + + + rd_dq0_del_0 + No change in dq0 delay + 0 + + + rd_dq0_del_1 + Add dq0 delay of 1 delay unit + 0x1 + + + rd_dq0_del_2 + Add dq0 delay of 2 delay units. + 0x2 + + + rd_dq0_del_3 + Add dq0 delay of 3 delay units. + 0x3 + + + rd_dq0_del_4 + Add dq0 delay of 4 delay units. + 0x4 + + + rd_dq0_del_5 + Add dq0 delay of 5 delay units. + 0x5 + + + rd_dq0_del_6 + Add dq0 delay of 6 delay units. + 0x6 + + + rd_dq0_del_7 + Add dq0 delay of 7 delay units. + 0x7 + + + + + rd_dq1_del + Read dqs0 to dq1 delay fine-tuning + 0x4 + 3 + read-write + + + rd_dq1_del_0 + No change in dq1 delay + 0 + + + rd_dq1_del_1 + Add dq1 delay of 1 delay unit + 0x1 + + + rd_dq1_del_2 + Add dq1 delay of 2 delay units. + 0x2 + + + rd_dq1_del_3 + Add dq1 delay of 3 delay units. + 0x3 + + + rd_dq1_del_4 + Add dq1 delay of 4 delay units. + 0x4 + + + rd_dq1_del_5 + Add dq1 delay of 5 delay units. + 0x5 + + + rd_dq1_del_6 + Add dq1 delay of 6 delay units. + 0x6 + + + rd_dq1_del_7 + Add dq1 delay of 7 delay units. + 0x7 + + + + + rd_dq2_del + Read dqs0 to dq2 delay fine-tuning + 0x8 + 3 + read-write + + + rd_dq2_del_0 + No change in dq2 delay + 0 + + + rd_dq2_del_1 + Add dq2 delay of 1 delay unit + 0x1 + + + rd_dq2_del_2 + Add dq2 delay of 2 delay units. + 0x2 + + + rd_dq2_del_3 + Add dq2 delay of 3 delay units. + 0x3 + + + rd_dq2_del_4 + Add dq2 delay of 4 delay units. + 0x4 + + + rd_dq2_del_5 + Add dq2 delay of 5 delay units. + 0x5 + + + rd_dq2_del_6 + Add dq2 delay of 6 delay units. + 0x6 + + + rd_dq2_del_7 + Add dq2 delay of 7 delay units. + 0x7 + + + + + rd_dq3_del + Read dqs0 to dq3 delay fine-tuning + 0xC + 3 + read-write + + + rd_dq3_del_0 + No change in dq3 delay + 0 + + + rd_dq3_del_1 + Add dq3 delay of 1 delay unit + 0x1 + + + rd_dq3_del_2 + Add dq3 delay of 2 delay units. + 0x2 + + + rd_dq3_del_3 + Add dq3 delay of 3 delay units. + 0x3 + + + rd_dq3_del_4 + Add dq3 delay of 4 delay units. + 0x4 + + + rd_dq3_del_5 + Add dq3 delay of 5 delay units. + 0x5 + + + rd_dq3_del_6 + Add dq3 delay of 6 delay units. + 0x6 + + + rd_dq3_del_7 + Add dq3 delay of 7 delay units. + 0x7 + + + + + rd_dq4_del + Read dqs0 to dq4 delay fine-tuning + 0x10 + 3 + read-write + + + rd_dq4_del_0 + No change in dq4 delay + 0 + + + rd_dq4_del_1 + Add dq4 delay of 1 delay unit + 0x1 + + + rd_dq4_del_2 + Add dq4 delay of 2 delay units. + 0x2 + + + rd_dq4_del_3 + Add dq4 delay of 3 delay units. + 0x3 + + + rd_dq4_del_4 + Add dq4 delay of 4 delay units. + 0x4 + + + rd_dq4_del_5 + Add dq4 delay of 5 delay units. + 0x5 + + + rd_dq4_del_6 + Add dq4 delay of 6 delay units. + 0x6 + + + rd_dq4_del_7 + Add dq4 delay of 7 delay units. + 0x7 + + + + + rd_dq5_del + Read dqs0 to dq5 delay fine-tuning + 0x14 + 3 + read-write + + + rd_dq5_del_0 + No change in dq5 delay + 0 + + + rd_dq5_del_1 + Add dq5 delay of 1 delay unit + 0x1 + + + rd_dq5_del_2 + Add dq5 delay of 2 delay units. + 0x2 + + + rd_dq5_del_3 + Add dq5 delay of 3 delay units. + 0x3 + + + rd_dq5_del_4 + Add dq5 delay of 4 delay units. + 0x4 + + + rd_dq5_del_5 + Add dq5 delay of 5 delay units. + 0x5 + + + rd_dq5_del_6 + Add dq5 delay of 6 delay units. + 0x6 + + + rd_dq5_del_7 + Add dq5 delay of 7 delay units. + 0x7 + + + + + rd_dq6_del + Read dqs0 to dq6 delay fine-tuning + 0x18 + 3 + read-write + + + rd_dq6_del_0 + No change in dq6 delay + 0 + + + rd_dq6_del_1 + Add dq6 delay of 1 delay unit + 0x1 + + + rd_dq6_del_2 + Add dq6 delay of 2 delay units. + 0x2 + + + rd_dq6_del_3 + Add dq6 delay of 3 delay units. + 0x3 + + + rd_dq6_del_4 + Add dq6 delay of 4 delay units. + 0x4 + + + rd_dq6_del_5 + Add dq6 delay of 5 delay units. + 0x5 + + + rd_dq6_del_6 + Add dq6 delay of 6 delay units. + 0x6 + + + rd_dq6_del_7 + Add dq6 delay of 7 delay units. + 0x7 + + + + + rd_dq7_del + Read dqs0 to dq7 delay fine-tuning + 0x1C + 3 + read-write + + + rd_dq7_del_0 + No change in dq7 delay + 0 + + + rd_dq7_del_1 + Add dq7 delay of 1 delay unit + 0x1 + + + rd_dq7_del_2 + Add dq7 delay of 2 delay units. + 0x2 + + + rd_dq7_del_3 + Add dq7 delay of 3 delay units. + 0x3 + + + rd_dq7_del_4 + Add dq7 delay of 4 delay units. + 0x4 + + + rd_dq7_del_5 + Add dq7 delay of 5 delay units. + 0x5 + + + rd_dq7_del_6 + Add dq7 delay of 6 delay units. + 0x6 + + + rd_dq7_del_7 + Add dq7 delay of 7 delay units. + 0x7 + + + + + + + MPRDDQBY1DL + MMDC PHY Read DQ Byte1 Delay Register + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq8_del + Read dqs1 to dq8 delay fine-tuning + 0 + 3 + read-write + + + rd_dq8_del_0 + No change in dq8 delay + 0 + + + rd_dq8_del_1 + Add dq8 delay of 1 delay unit + 0x1 + + + rd_dq8_del_2 + Add dq8 delay of 2 delay units. + 0x2 + + + rd_dq8_del_3 + Add dq8 delay of 3 delay units. + 0x3 + + + rd_dq8_del_4 + Add dq8 delay of 4 delay units. + 0x4 + + + rd_dq8_del_5 + Add dq8 delay of 5 delay units. + 0x5 + + + rd_dq8_del_6 + Add dq8 delay of 6 delay units. + 0x6 + + + rd_dq8_del_7 + Add dq8 delay of 7 delay units. + 0x7 + + + + + rd_dq9_del + Read dqs1 to dq9 delay fine-tuning + 0x4 + 3 + read-write + + + rd_dq9_del_0 + No change in dq9 delay + 0 + + + rd_dq9_del_1 + Add dq9 delay of 1 delay unit + 0x1 + + + rd_dq9_del_2 + Add dq9 delay of 2 delay units. + 0x2 + + + rd_dq9_del_3 + Add dq9 delay of 3 delay units. + 0x3 + + + rd_dq9_del_4 + Add dq9 delay of 4 delay units. + 0x4 + + + rd_dq9_del_5 + Add dq9 delay of 5 delay units. + 0x5 + + + rd_dq9_del_6 + Add dq9 delay of 6 delay units. + 0x6 + + + rd_dq9_del_7 + Add dq9 delay of 7 delay units. + 0x7 + + + + + rd_dq10_del + Read dqs1 to dq10 delay fine-tuning + 0x8 + 3 + read-write + + + rd_dq10_del_0 + No change in dq10 delay + 0 + + + rd_dq10_del_1 + Add dq10 delay of 1 delay unit + 0x1 + + + rd_dq10_del_2 + Add dq10 delay of 2 delay units. + 0x2 + + + rd_dq10_del_3 + Add dq10 delay of 3 delay units. + 0x3 + + + rd_dq10_del_4 + Add dq10 delay of 4 delay units. + 0x4 + + + rd_dq10_del_5 + Add dq10 delay of 5 delay unit + 0x5 + + + rd_dq10_del_6 + Add dq10 delay of 6 delay units. + 0x6 + + + rd_dq10_del_7 + Add dq10 delay of 7 delay units. + 0x7 + + + + + rd_dq11_del + Read dqs1 to dq11 delay fine-tuning + 0xC + 3 + read-write + + + rd_dq11_del_0 + No change in dq11 delay + 0 + + + rd_dq11_del_1 + Add dq11 delay of 1 delay unit + 0x1 + + + rd_dq11_del_2 + Add dq11 delay of 2 delay units. + 0x2 + + + rd_dq11_del_3 + Add dq11 delay of 3 delay units. + 0x3 + + + rd_dq11_del_4 + Add dq11 delay of 4 delay units. + 0x4 + + + rd_dq11_del_5 + Add dq11 delay of 5 delay units. + 0x5 + + + rd_dq11_del_6 + Add dq11 delay of 6 delay units. + 0x6 + + + rd_dq11_del_7 + Add dq11 delay of 7 delay units. + 0x7 + + + + + rd_dq12_del + Read dqs1 to dq12 delay fine-tuning + 0x10 + 3 + read-write + + + rd_dq12_del_0 + No change in dq12 delay + 0 + + + rd_dq12_del_1 + Add dq12 delay of 1 delay unit + 0x1 + + + rd_dq12_del_2 + Add dq12 delay of 2 delay units. + 0x2 + + + rd_dq12_del_3 + Add dq12 delay of 3 delay units. + 0x3 + + + rd_dq12_del_4 + Add dq12 delay of 4 delay units. + 0x4 + + + rd_dq12_del_5 + Add dq12 delay of 5 delay units. + 0x5 + + + rd_dq12_del_6 + Add dq12 delay of 6 delay units. + 0x6 + + + rd_dq12_del_7 + Add dq12 delay of 7 delay units. + 0x7 + + + + + rd_dq13_del + Read dqs1 to dq13 delay fine-tuning + 0x14 + 3 + read-write + + + rd_dq13_del_0 + No change in dq13 delay + 0 + + + rd_dq13_del_1 + Add dq13 delay of 1 delay unit + 0x1 + + + rd_dq13_del_2 + Add dq13 delay of 2 delay units. + 0x2 + + + rd_dq13_del_3 + Add dq13 delay of 3 delay units. + 0x3 + + + rd_dq13_del_4 + Add dq13 delay of 4 delay units. + 0x4 + + + rd_dq13_del_5 + Add dq13 delay of 5 delay units. + 0x5 + + + rd_dq13_del_6 + Add dq13 delay of 6 delay units. + 0x6 + + + rd_dq13_del_7 + Add dq13 delay of 7 delay units. + 0x7 + + + + + rd_dq14_del + Read dqs1 to dq14 delay fine-tuning + 0x18 + 3 + read-write + + + rd_dq14_del_0 + No change in dq14 delay + 0 + + + rd_dq14_del_1 + Add dq14 delay of 1 delay unit + 0x1 + + + rd_dq14_del_2 + Add dq14 delay of 2 delay units. + 0x2 + + + rd_dq14_del_3 + Add dq14 delay of 3 delay units. + 0x3 + + + rd_dq14_del_4 + Add dq14 delay of 4 delay units. + 0x4 + + + rd_dq14_del_5 + Add dq14 delay of 5 delay units. + 0x5 + + + rd_dq14_del_6 + Add dq14 delay of 6 delay units. + 0x6 + + + rd_dq14_del_7 + Add dq14 delay of 7 delay units. + 0x7 + + + + + rd_dq15_del + Read dqs1 to dq15 delay fine-tuning + 0x1C + 3 + read-write + + + rd_dq15_del_0 + No change in dq15 delay + 0 + + + rd_dq15_del_1 + Add dq15 delay of 1 delay unit + 0x1 + + + rd_dq15_del_2 + Add dq15 delay of 2 delay units. + 0x2 + + + rd_dq15_del_3 + Add dq15 delay of 3 delay units. + 0x3 + + + rd_dq15_del_4 + Add dq15 delay of 4 delay units. + 0x4 + + + rd_dq15_del_5 + Add dq15 delay of 5 delay units. + 0x5 + + + rd_dq15_del_6 + Add dq15 delay of 6 delay units. + 0x6 + + + rd_dq15_del_7 + Add dq15 delay of 7 delay units. + 0x7 + + + + + + + MPWRDQBY0DL + MMDC PHY Write DQ Byte0 Delay Register + 0x82C + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq0_del + Write dq0 delay fine-tuning + 0 + 2 + read-write + + + wr_dq0_del_0 + No change in dq0 delay + 0 + + + wr_dq0_del_1 + Add dq0 delay of 1 delay unit. + 0x1 + + + wr_dq0_del_2 + Add dq0 delay of 2 delay units. + 0x2 + + + wr_dq0_del_3 + Add dq0 delay of 3 delay units. + 0x3 + + + + + wr_dq1_del + Write dq1 delay fine-tuning + 0x4 + 2 + read-write + + + wr_dq1_del_0 + No change in dq1 delay + 0 + + + wr_dq1_del_1 + Add dq1 delay of 1 delay unit. + 0x1 + + + wr_dq1_del_2 + Add dq1 delay of 2 delay units. + 0x2 + + + wr_dq1_del_3 + Add dq1 delay of 3 delay units. + 0x3 + + + + + wr_dq2_del + Write dq2 delay fine-tuning + 0x8 + 2 + read-write + + + wr_dq2_del_0 + No change in dq2 delay + 0 + + + wr_dq2_del_1 + Add dq2 delay of 1 delay unit. + 0x1 + + + wr_dq2_del_2 + Add dq2 delay of 2 delay units. + 0x2 + + + wr_dq2_del_3 + Add dq2 delay of 3 delay units. + 0x3 + + + + + wr_dq3_del + Write dq3 delay fine-tuning + 0xC + 2 + read-write + + + wr_dq3_del_0 + No change in dq3 delay + 0 + + + wr_dq3_del_1 + Add dq3 delay of 1 delay unit. + 0x1 + + + wr_dq3_del_2 + Add dq3 delay of 2 delay units. + 0x2 + + + wr_dq3_del_3 + Add dq3 delay of 3 delay units. + 0x3 + + + + + wr_dq4_del + Write dq4 delay fine-tuning + 0x10 + 2 + read-write + + + wr_dq4_del_0 + No change in dq4 delay + 0 + + + wr_dq4_del_1 + Add dq4 delay of 1 delay unit.. + 0x1 + + + wr_dq4_del_2 + Add dq4 delay of 2 delay units. + 0x2 + + + wr_dq4_del_3 + Add dq4 delay of 3 delay units. + 0x3 + + + + + wr_dq5_del + Write dq5 delay fine-tuning + 0x14 + 2 + read-write + + + wr_dq5_del_0 + No change in dq5 delay + 0 + + + wr_dq5_del_1 + Add dq5 delay of 1 delay unit. + 0x1 + + + wr_dq5_del_2 + Add dq5 delay of 2 delay units. + 0x2 + + + wr_dq5_del_3 + Add dq5 delay of 3 delay units. + 0x3 + + + + + wr_dq6_del + Write dq6 delay fine-tuning + 0x18 + 2 + read-write + + + wr_dq6_del_0 + No change in dq6 delay + 0 + + + wr_dq6_del_1 + Add dq6 delay of 1 delay unit. + 0x1 + + + wr_dq6_del_2 + Add dq6 delay of 2 delay units. + 0x2 + + + wr_dq6_del_3 + Add dq6 delay of 3 delay units. + 0x3 + + + + + wr_dq7_del + Write dq7 delay fine-tuning + 0x1C + 2 + read-write + + + wr_dq7_del_0 + No change in dq7 delay + 0 + + + wr_dq7_del_1 + Add dq7 delay of 1 delay unit. + 0x1 + + + wr_dq7_del_2 + Add dq7 delay of 2 delay units. + 0x2 + + + wr_dq7_del_3 + Add dq7 delay of 3 delay units. + 0x3 + + + + + wr_dm0_del + Write dm0 delay fine-tuning + 0x1E + 2 + read-write + + + wr_dm0_del_0 + No change in dm0 delay + 0 + + + wr_dm0_del_1 + Add dm0 delay of 1 delay unit. + 0x1 + + + wr_dm0_del_2 + Add dm0 delay of 2 delay units. + 0x2 + + + wr_dm0_del_3 + Add dm0 delay of 3 delay units. + 0x3 + + + + + + + MPWRDQBY1DL + MMDC PHY Write DQ Byte1 Delay Register + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq8_del + Write dq8 delay fine-tuning + 0 + 2 + read-write + + + wr_dq8_del_0 + No change in dq8 delay + 0 + + + wr_dq8_del_1 + Add dq8 delay of 1 delay unit. + 0x1 + + + wr_dq8_del_2 + Add dq8 delay of 2 delay units. + 0x2 + + + wr_dq8_del_3 + Add dq8 delay of 3 delay units. + 0x3 + + + + + wr_dq9_del + Write dq9 delay fine-tuning + 0x4 + 2 + read-write + + + wr_dq9_del_0 + No change in dq9 delay + 0 + + + wr_dq9_del_1 + Add dq9 delay of 1 delay unit. + 0x1 + + + wr_dq9_del_2 + Add dq9 delay of 2 delay units. + 0x2 + + + wr_dq9_del_3 + Add dq9 delay of 3 delay units. + 0x3 + + + + + wr_dq10_del + Write dq10 delay fine-tuning + 0x8 + 2 + read-write + + + wr_dq10_del_0 + No change in dq10 delay + 0 + + + wr_dq10_del_1 + Add dq10 delay of 1 delay unit. + 0x1 + + + wr_dq10_del_2 + Add dq10 delay of 2 delay units. + 0x2 + + + wr_dq10_del_3 + Add dq10 delay of 3 delay units. + 0x3 + + + + + wr_dq11_del + Write dq11 delay fine-tuning + 0xC + 2 + read-write + + + wr_dq11_del_0 + No change in dq11 delay + 0 + + + wr_dq11_del_1 + Add dq11 delay of 1 delay unit. + 0x1 + + + wr_dq11_del_2 + Add dq11 delay of 2 delay units. + 0x2 + + + wr_dq11_del_3 + Add dq11 delay of 3 delay units. + 0x3 + + + + + wr_dq12_del + Write dq12 delay fine-tuning + 0x10 + 2 + read-write + + + wr_dq12_del_0 + No change in dq12 delay + 0 + + + wr_dq12_del_1 + Add dq12 delay of 1 delay unit. + 0x1 + + + wr_dq12_del_2 + Add dq12 delay of 2 delay units. + 0x2 + + + wr_dq12_del_3 + Add dq12 delay of 3 delay units. + 0x3 + + + + + wr_dq13_del + Write dq13 delay fine-tuning + 0x14 + 2 + read-write + + + wr_dq13_del_0 + No change in dq13 delay + 0 + + + wr_dq13_del_1 + Add dq13 delay of 1 delay unit. + 0x1 + + + wr_dq13_del_2 + Add dq13 delay of 2 delay units. + 0x2 + + + wr_dq13_del_3 + Add dq13 delay of 3 delay units. + 0x3 + + + + + wr_dq14_del + Write dq14 delay fine-tuning + 0x18 + 2 + read-write + + + wr_dq14_del_0 + No change in dq14 delay + 0 + + + wr_dq14_del_1 + Add dq14 delay of 1 delay unit. + 0x1 + + + wr_dq14_del_2 + Add dq14 delay of 2 delay units. + 0x2 + + + wr_dq14_del_3 + Add dq14 delay of 3 delay units. + 0x3 + + + + + wr_dq15_del + Write dq15 delay fine-tuning + 0x1C + 2 + read-write + + + wr_dq15_del_0 + No change in dq15 delay + 0 + + + wr_dq15_del_1 + Add dq15 delay of 1 delay unit. + 0x1 + + + wr_dq15_del_2 + Add dq15 delay of 2 delay units. + 0x2 + + + wr_dq15_del_3 + Add dq15 delay of 3 delay units. + 0x3 + + + + + wr_dm1_del + Write dm1 delay fine-tuning + 0x1E + 2 + read-write + + + wr_dm1_del_0 + No change in dm1 delay + 0 + + + wr_dm1_del_1 + Add dm1 delay of 1 delay unit. + 0x1 + + + wr_dm1_del_2 + Add dm1 delay of 2 delay units. + 0x2 + + + wr_dm1_del_3 + Add dm1 delay of 3 delay units. + 0x3 + + + + + + + MPWRDQBY2DL + MMDC PHY Write DQ Byte2 Delay Register + 0x834 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq16_del + Write dq16 delay fine tuning + 0 + 2 + read-write + + + wr_dq16_del_0 + No change in dq16 delay + 0 + + + wr_dq16_del_1 + Add dq16 delay of 1 delay unit. + 0x1 + + + wr_dq16_del_2 + Add dq16 delay of 2 delay units. + 0x2 + + + wr_dq16_del_3 + Add dq16 delay of 3 delay units. + 0x3 + + + + + wr_dq17_del + Write dq17 delay fine tuning + 0x4 + 2 + read-write + + + wr_dq17_del_0 + No change in dq17 delay + 0 + + + wr_dq17_del_1 + Add dq17 delay of 1 delay unit. + 0x1 + + + wr_dq17_del_2 + Add dq17 delay of 2 delay units. + 0x2 + + + wr_dq17_del_3 + Add dq17 delay of 3 delay units. + 0x3 + + + + + wr_dq18_del + Write dq18 delay fine tuning + 0x8 + 2 + read-write + + + wr_dq18_del_0 + No change in dq18 delay + 0 + + + wr_dq18_del_1 + Add dq18 delay of 1 delay unit. + 0x1 + + + wr_dq18_del_2 + Add dq18 delay of 2 delay units. + 0x2 + + + wr_dq18_del_3 + Add dq18 delay of 3 delay units. + 0x3 + + + + + wr_dq19_del + Write dq19 delay fine tuning + 0xC + 2 + read-write + + + wr_dq19_del_0 + No change in dq19 delay + 0 + + + wr_dq19_del_1 + Add dq19 delay of 1 delay unit. + 0x1 + + + wr_dq19_del_2 + Add dq19 delay of 2 delay units. + 0x2 + + + wr_dq19_del_3 + Add dq19 delay of 3 delay units. + 0x3 + + + + + wr_dq20_del + Write dq20 delay fine tuning + 0x10 + 2 + read-write + + + wr_dq20_del_0 + No change in dq20 delay + 0 + + + wr_dq20_del_1 + Add dq20 delay of 1 delay unit. + 0x1 + + + wr_dq20_del_2 + Add dq20 delay of 2 delay units. + 0x2 + + + wr_dq20_del_3 + Add dq20 delay of 3 delay units. + 0x3 + + + + + wr_dq21_del + Write dq21 delay fine tuning + 0x14 + 2 + read-write + + + wr_dq21_del_0 + No change in dq21 delay + 0 + + + wr_dq21_del_1 + Add dq21 delay of 1 delay unit. + 0x1 + + + wr_dq21_del_2 + Add dq21 delay of 2 delay units. + 0x2 + + + wr_dq21_del_3 + Add dq21 delay of 3 delay units. + 0x3 + + + + + wr_dq22_del + Write dq22 delay fine tuning + 0x18 + 2 + read-write + + + wr_dq22_del_0 + No change in dq22 delay + 0 + + + wr_dq22_del_1 + Add dq22 delay of 1 delay unit. + 0x1 + + + wr_dq22_del_2 + Add dq22 delay of 2 delay units. + 0x2 + + + wr_dq22_del_3 + Add dq22 delay of 3 delay units. + 0x3 + + + + + wr_dq23_del + Write dq23 delay fine tuning + 0x1C + 2 + read-write + + + wr_dq23_del_0 + No change in dq23 delay + 0 + + + wr_dq23_del_1 + Add dq23 delay of 1 delay unit. + 0x1 + + + wr_dq23_del_2 + Add dq23 delay of 2 delay units. + 0x2 + + + wr_dq23_del_3 + Add dq23 delay of 3 delay units. + 0x3 + + + + + wr_dm2_del + Write dm2 delay fine-tuning + 0x1E + 2 + read-write + + + wr_dm2_del_0 + No change in dm2 delay + 0 + + + wr_dm2_del_1 + Add dm2 delay of 1 delay unit. + 0x1 + + + wr_dm2_del_2 + Add dm2 delay of 2 delay units. + 0x2 + + + wr_dm2_del_3 + Add dm2 delay of 3 delay units. + 0x3 + + + + + + + MPWRDQBY3DL + MMDC PHY Write DQ Byte3 Delay Register + 0x838 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq24_del + Write dq24 delay fine tuning + 0 + 2 + read-write + + + wr_dq24_del_0 + No change in dq24 delay + 0 + + + wr_dq24_del_1 + Add dq24 delay of 1 delay unit. + 0x1 + + + wr_dq24_del_2 + Add dq24 delay of 2 delay units. + 0x2 + + + wr_dq24_del_3 + Add dq24 delay of 3 delay units. + 0x3 + + + + + wr_dq25_del + Write dq25 delay fine tuning + 0x4 + 2 + read-write + + + wr_dq25_del_0 + No change in dq25 delay + 0 + + + wr_dq25_del_1 + Add dq25 delay of 1 delay unit. + 0x1 + + + wr_dq25_del_2 + Add dq25 delay of 2 delay units. + 0x2 + + + wr_dq25_del_3 + Add dq25 delay of 3 delay units. + 0x3 + + + + + wr_dq26_del + Write dq26 delay fine tuning + 0x8 + 2 + read-write + + + wr_dq26_del_0 + No change in dq26 delay + 0 + + + wr_dq26_del_1 + Add dq26 delay of 1 delay unit. + 0x1 + + + wr_dq26_del_2 + Add dq26 delay of 2 delay units. + 0x2 + + + wr_dq26_del_3 + Add dq26 delay of 3 delay units. + 0x3 + + + + + wr_dq27_del + Write dq27 delay fine tuning + 0xC + 2 + read-write + + + wr_dq27_del_0 + No change in dq27 delay + 0 + + + wr_dq27_del_1 + Add dq27 delay of 1 delay unit. + 0x1 + + + wr_dq27_del_2 + Add dq27 delay of 2 delay units. + 0x2 + + + wr_dq27_del_3 + Add dq27 delay of 3 delay units. + 0x3 + + + + + wr_dq28_del + Write dq28 delay fine tuning + 0x10 + 2 + read-write + + + wr_dq28_del_0 + No change in dq28 delay + 0 + + + wr_dq28_del_1 + Add dq28 delay of 1 delay unit. + 0x1 + + + wr_dq28_del_2 + Add dq28 delay of 2 delay units. + 0x2 + + + wr_dq28_del_3 + Add dq28 delay of 3 delay units. + 0x3 + + + + + wr_dq29_del + Write dq29 delay fine tuning + 0x14 + 2 + read-write + + + wr_dq29_del_0 + No change in dq29 delay + 0 + + + wr_dq29_del_1 + Add dq29 delay of 1 delay unit. + 0x1 + + + wr_dq29_del_2 + Add dq29 delay of 2 delay units. + 0x2 + + + wr_dq29_del_3 + Add dq29 delay of 3 delay units. + 0x3 + + + + + wr_dq30_del + Write dq30 delay fine tuning + 0x18 + 2 + read-write + + + wr_dq30_del_0 + No change in dq30 delay + 0 + + + wr_dq30_del_1 + Add dq30 delay of 1 delay unit. + 0x1 + + + wr_dq30_del_2 + Add dq30 delay of 2 delay units. + 0x2 + + + wr_dq30_del_3 + Add dq30 delay of 3 delay units. + 0x3 + + + + + wr_dq31_del + Write dq31 delay fine tuning + 0x1C + 2 + read-write + + + wr_dq31_del_0 + No change in dq31 delay + 0 + + + wr_dq31_del_1 + Add dq31 delay of 1 delay unit. + 0x1 + + + wr_dq31_del_2 + Add dq31 delay of 2 delay units. + 0x2 + + + wr_dq31_del_3 + Add dq31 delay of 3 delay units. + 0x3 + + + + + wr_dm3_del + Write dm3 delay fine tuning + 0x1E + 2 + read-write + + + wr_dm3_del_0 + No change in dm3 delay + 0 + + + wr_dm3_del_1 + Add dm3 delay of 1 delay unit. + 0x1 + + + wr_dm3_del_2 + Add dm3 delay of 2 delay units. + 0x2 + + + wr_dm3_del_3 + Add dm3 delay of 3 delay units. + 0x3 + + + + + + + MPDGCTRL0 + MMDC PHY Read DQS Gating Control Register 0 + 0x83C + 32 + read-write + 0 + 0xFFFFFFFF + + + DG_DL_ABS_OFFSET0 + Absolute read DQS gating delay offset for Byte0 + 0 + 7 + read-write + + + DG_HC_DEL0 + Read DQS gating half cycles delay for Byte0 + 0x8 + 4 + read-write + + + DG_HC_DEL0_0 + 0 cycles delay. + 0 + + + DG_HC_DEL0_1 + Half cycle delay. + 0x1 + + + DG_HC_DEL0_2 + 1 cycle delay + 0x2 + + + DG_HC_DEL0_13 + 6.5 cycles delay + 0xD + + + + + HW_DG_ERR + HW DQS gating error + 0xC + 1 + read-only + + + HW_DG_ERR_0 + No error was found during the DQS gating HW calibration process. + 0 + + + HW_DG_ERR_1 + An error was found during the DQS gating HW calibration process. + 0x1 + + + + + DG_DL_ABS_OFFSET1 + Absolute read DQS gating delay offset for Byte1 + 0x10 + 7 + read-write + + + DG_EXT_UP + DG extend upper boundary + 0x17 + 1 + read-write + + + DG_HC_DEL1 + Read DQS gating half cycles delay for Byte1 + 0x18 + 4 + read-write + + + DG_HC_DEL1_0 + 0 cycles delay. + 0 + + + DG_HC_DEL1_1 + Half cycle delay. + 0x1 + + + DG_HC_DEL1_2 + 1 cycle delay + 0x2 + + + DG_HC_DEL1_13 + 6.5 cycles delay + 0xD + + + + + HW_DG_EN + Enable automatic read DQS gating calibration + 0x1C + 1 + read-write + + + HW_DG_EN_0 + Disable automatic read DQS gating calibration + 0 + + + HW_DG_EN_1 + Start automatic read DQS gating calibration + 0x1 + + + + + DG_DIS + Read DQS gating disable + 0x1D + 1 + read-write + + + DG_DIS_0 + Read DQS gating mechanism is enabled + 0 + + + DG_DIS_1 + Read DQS gating mechanism is disabled + 0x1 + + + + + DG_CMP_CYC + Read DQS gating sample cycle + 0x1E + 1 + read-write + + + DG_CMP_CYC_0 + MMDC waits 16 DDR cycles + 0 + + + DG_CMP_CYC_1 + MMDC waits 32 DDR cycles + 0x1 + + + + + RST_RD_FIFO + Reset Read Data FIFO and associated pointers + 0x1F + 1 + read-write + + + + + MPDGDLST0 + MMDC PHY Read DQS Gating delay-line Status Register + 0x844 + 32 + read-only + 0 + 0xFFFFFFFF + + + DG_DL_UNIT_NUM0 + This field reflects the number of delay units that are actually used by read DQS gating delay-line 0 + 0 + 7 + read-only + + + DG_DL_UNIT_NUM1 + This field reflects the number of delay units that are actually used by read DQS gating delay-line 1 + 0x8 + 7 + read-only + + + + + MPRDDLCTL + MMDC PHY Read delay-lines Configuration Register + 0x848 + 32 + read-write + 0x40404040 + 0xFFFFFFFF + + + RD_DL_ABS_OFFSET0 + Absolute read delay offset for Byte0 + 0 + 7 + read-write + + + RD_DL_ABS_OFFSET1 + Absolute read delay offset for Byte1 + 0x8 + 7 + read-write + + + + + MPRDDLST + MMDC PHY Read delay-lines Status Register + 0x84C + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_DL_UNIT_NUM0 + This field reflects the number of delay units that are actually used by read delay-line 0. + 0 + 7 + read-only + + + RD_DL_UNIT_NUM1 + This field reflects the number of delay units that are actually used by read delay-line 1. + 0x8 + 7 + read-only + + + + + MPWRDLCTL + MMDC PHY Write delay-lines Configuration Register + 0x850 + 32 + read-write + 0x40404040 + 0xFFFFFFFF + + + WR_DL_ABS_OFFSET0 + Absolute write delay offset for Byte0 + 0 + 7 + read-write + + + WR_DL_ABS_OFFSET1 + Absolute write delay offset for Byte1 + 0x8 + 7 + read-write + + + + + MPWRDLST + MMDC PHY Write delay-lines Status Register + 0x854 + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_DL_UNIT_NUM0 + This field reflects the number of delay units that are actually used by write delay-line 0. + 0 + 7 + read-only + + + WR_DL_UNIT_NUM1 + This field reflects the number of delay units that are actually used by write delay-line 1. + 0x8 + 7 + read-only + + + + + MPSDCTRL + MMDC PHY CK Control Register + 0x858 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDclk0_del + DDR clock0 delay fine tuning + 0x8 + 2 + read-write + + + SDclk0_del_0 + No change in DDR clock0 delay + 0 + + + SDclk0_del_1 + Add DDR clock0 delay of 1 delay unit. + 0x1 + + + SDclk0_del_2 + Add DDR clock0 delay of 2 delay units. + 0x2 + + + SDclk0_del_3 + Add DDR clock0 delay of 3 delay units. + 0x3 + + + + + SDCLK1_del + DDR clock1 delay fine tuning + 0xA + 2 + read-write + + + SDCLK1_del_0 + No change in DDR clock delay + 0 + + + SDCLK1_del_1 + Add DDR clock delay of 1 delay unit. + 0x1 + + + SDCLK1_del_2 + Add DDR clock delay of 2 delay units. + 0x2 + + + SDCLK1_del_3 + Add DDR clock delay of 3 delay units. + 0x3 + + + + + + + MPZQLP2CTL + MMDC ZQ LPDDR2 HW Control Register + 0x85C + 32 + read-write + 0x1B5F0109 + 0xFFFFFFFF + + + ZQ_LP2_HW_ZQINIT + This register defines the period in cycles that it takes the memory device to perform a Init ZQ calibration + 0 + 9 + read-write + + + ZQ_LP2_HW_ZQINIT_55 + 112 cycles + 0x37 + + + ZQ_LP2_HW_ZQINIT_56 + 114 cycles + 0x38 + + + ZQ_LP2_HW_ZQINIT_265 + 532 cycles (Default, JEDEC value, tZQINIT, for LPDDR2, 1us @ clock frequency 533MHz) + 0x109 + + + ZQ_LP2_HW_ZQINIT_510 + 1022 cycles + 0x1FE + + + ZQ_LP2_HW_ZQINIT_511 + 1024 cycles + 0x1FF + + + + + ZQ_LP2_HW_ZQCL + This register defines the period in cycles that it takes the memory device to perform a long ZQ calibration + 0x10 + 8 + read-write + + + ZQ_LP2_HW_ZQCL_55 + 112 cycles + 0x37 + + + ZQ_LP2_HW_ZQCL_56 + 114 cycles + 0x38 + + + ZQ_LP2_HW_ZQCL_95 + 192 cycles (Default, JEDEC value, tZQCL, for LPDDR2, 360ns @ clock frequency 533MHz) + 0x5F + + + ZQ_LP2_HW_ZQCL_254 + 510 cycles + 0xFE + + + ZQ_LP2_HW_ZQCL_255 + 512 cycles + 0xFF + + + + + ZQ_LP2_HW_ZQCS + This register defines the period in cycles that it takes the memory device to perform a short ZQ calibration + 0x18 + 7 + read-write + + + ZQ_LP2_HW_ZQCS_27 + 112 cycles (default) + 0x1B + + + ZQ_LP2_HW_ZQCS_28 + 116 cycles + 0x1C + + + ZQ_LP2_HW_ZQCS_126 + 508 cycles + 0x7E + + + ZQ_LP2_HW_ZQCS_127 + 512 cycles + 0x7F + + + + + + + MPRDDLHWCTL + MMDC PHY Read Delay HW Calibration Control Register + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_RD_DL_ERR0 + Automatic (HW) read calibration error of Byte0 + 0 + 1 + read-only + + + HW_RD_DL_ERR0_0 + No error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. + 0 + + + HW_RD_DL_ERR0_1 + An error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. + 0x1 + + + + + HW_RD_DL_ERR1 + Automatic (HW) read calibration error of Byte1 + 0x1 + 1 + read-only + + + HW_RD_DL_ERR1_0 + No error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. + 0 + + + HW_RD_DL_ERR1_1 + An error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. + 0x1 + + + + + HW_RD_DL_EN + Enable automatic (HW) read calibration + 0x4 + 1 + read-write + + + HW_RD_DL_CMP_CYC + Automatic (HW) read sample cycle + 0x5 + 1 + read-write + + + + + MPWRDLHWCTL + MMDC PHY Write Delay HW Calibration Control Register + 0x864 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_WR_DL_ERR0 + Automatic (HW) write calibration error of Byte0 + 0 + 1 + read-only + + + HW_WR_DL_ERR0_0 + No error was found during the automatic (HW) write calibration process of write delay-line 0. + 0 + + + HW_WR_DL_ERR0_1 + An error was found during the automatic (HW) write calibration process of write delay-line 0. + 0x1 + + + + + HW_WR_DL_ERR1 + Automatic (HW) write calibration error of Byte1 + 0x1 + 1 + read-only + + + HW_WR_DL_ERR1_0 + No error was found during the automatic (HW) write calibration process of write delay-line 1. + 0 + + + HW_WR_DL_ERR1_1 + An error was found during the automatic (HW) write calibration process of write delay-line 1. + 0x1 + + + + + HW_WR_DL_EN + Enable automatic (HW) write calibration + 0x4 + 1 + read-write + + + HW_WR_DL_CMP_CYC + Write sample cycle + 0x5 + 1 + read-write + + + + + MPRDDLHWST0 + MMDC PHY Read Delay HW Calibration Status Register 0 + 0x868 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_RD_DL_LOW0 + Automatic (HW) read calibration result of the lower boundary of Byte0 + 0 + 7 + read-only + + + HW_RD_DL_UP0 + Automatic (HW) read calibration result of the upper boundary of Byte0 + 0x8 + 7 + read-only + + + HW_RD_DL_LOW1 + Automatic (HW) read calibration result of the lower boundary of Byte1 + 0x10 + 7 + read-only + + + HW_RD_DL_UP1 + Automatic (HW) read calibration result of the upper boundary of Byte1 + 0x18 + 7 + read-only + + + + + MPWRDLHWST0 + MMDC PHY Write Delay HW Calibration Status Register 0 + 0x870 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WR_DL_LOW0 + Automatic (HW) write calibration result of the lower boundary of Byte0 + 0 + 7 + read-only + + + HW_WR_DL_UP0 + Automatic (HW) write calibration result of the upper boundary of Byte0 + 0x8 + 7 + read-only + + + HW_WR_DL_LOW1 + Automatic (HW) write calibration result of the lower boundary of Byte1 + 0x10 + 7 + read-only + + + HW_WR_DL_UP1 + Automatic (HW) write automatic (HW) write calibration result of the upper boundary of Byte1 + 0x18 + 7 + read-only + + + + + MPWLHWERR + MMDC PHY Write Leveling HW Error Register + 0x878 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WL0_DQ + HW write-leveling calibration result of Byte0 + 0 + 8 + read-only + + + HW_WL1_DQ + HW write-leveling calibration result of Byte1 + 0x8 + 8 + read-only + + + + + MPDGHWST0 + MMDC PHY Read DQS Gating HW Status Register 0 + 0x87C + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW0 + HW DQS gating calibration result of the lower boundary of Byte0 + 0 + 11 + read-only + + + HW_DG_UP0 + HW DQS gating calibration result of the upper boundary of Byte0 + 0x10 + 11 + read-only + + + + + MPDGHWST1 + MMDC PHY Read DQS Gating HW Status Register 1 + 0x880 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW1 + HW DQS gating calibration result of the lower boundary of Byte1 + 0 + 11 + read-only + + + HW_DG_UP1 + HW DQS gating calibration result of the upper boundary of Byte1 + 0x10 + 11 + read-only + + + + + MPPDCMPR1 + MMDC PHY Pre-defined Compare Register 1 + 0x88C + 32 + read-write + 0 + 0xFFFFFFFF + + + PDV1 + MMDC Pre defined compare value2 + 0 + 16 + read-write + + + PDV2 + MMDC Pre defined compare value2 + 0x10 + 16 + read-write + + + + + MPPDCMPR2 + MMDC PHY Pre-defined Compare and CA delay-line Configuration Register + 0x890 + 32 + read-write + 0x400000 + 0xFFFFFFFF + + + MPR_CMP + MPR(DDR3)/ DQ calibration (LPDDR2/LPDDR3) compare enable + 0 + 1 + read-write + + + MPR_FULL_CMP + MPR(DDR3)/ DQ calibration (LPDDR2/LPDDR3) full compare enable + 0x1 + 1 + read-write + + + READ_LEVEL_PATTERN + MPR(DDR3)/ DQ calibration (LPDDR2/LPDDR3) read compare pattern + 0x2 + 1 + read-write + + + READ_LEVEL_PATTERN_0 + Compare with read pattern 1010 + 0 + + + READ_LEVEL_PATTERN_1 + Compare with read pattern 0011 (Used only in LPDDR2/LPDDR3 mode) + 0x1 + + + + + ZQ_OFFSET_EN + no description available + 0x3 + 1 + read-write + + + ZQ_OFFSET_EN_0 + Hardware ZQ offset disabled + 0 + + + ZQ_OFFSET_EN_1 + Hardware ZQ offset enabled + 0x1 + + + + + ZQ_PD_OFFSET + Programmable offset from -7 to 7 added to the MMDC_MPZQHWCTRL[ZQ_HW_PD_RES] field when ZQ_OFFSET_EN is enabled + 0x4 + 4 + read-write + + + ZQ_PD_OFFSET_0 + +0 + 0 + + + ZQ_PD_OFFSET_1 + +1 + 0x1 + + + ZQ_PD_OFFSET_2 + +2 + 0x2 + + + ZQ_PD_OFFSET_3 + +3 + 0x3 + + + ZQ_PD_OFFSET_4 + +4 + 0x4 + + + ZQ_PD_OFFSET_5 + +5 + 0x5 + + + ZQ_PD_OFFSET_6 + +6 + 0x6 + + + ZQ_PD_OFFSET_7 + +7 + 0x7 + + + ZQ_PD_OFFSET_8 + -0 + 0x8 + + + ZQ_PD_OFFSET_9 + -1 + 0x9 + + + ZQ_PD_OFFSET_10 + -2 + 0xA + + + ZQ_PD_OFFSET_11 + -3 + 0xB + + + ZQ_PD_OFFSET_12 + -4 + 0xC + + + ZQ_PD_OFFSET_13 + -5 + 0xD + + + ZQ_PD_OFFSET_14 + -6 + 0xE + + + ZQ_PD_OFFSET_15 + -7 + 0xF + + + + + ZQ_PU_OFFSET + Programmable offset from -7 to 7 added to the MMDC_MPZQHWCTRL[ZQ_HW_PU_RES] field when ZQ_OFFSET_EN is enabled + 0x8 + 4 + read-write + + + ZQ_PU_OFFSET_0 + +0 + 0 + + + ZQ_PU_OFFSET_1 + +1 + 0x1 + + + ZQ_PU_OFFSET_2 + +2 + 0x2 + + + ZQ_PU_OFFSET_3 + +3 + 0x3 + + + ZQ_PU_OFFSET_4 + +4 + 0x4 + + + ZQ_PU_OFFSET_5 + +5 + 0x5 + + + ZQ_PU_OFFSET_6 + +6 + 0x6 + + + ZQ_PU_OFFSET_7 + +7 + 0x7 + + + ZQ_PU_OFFSET_8 + -0 + 0x8 + + + ZQ_PU_OFFSET_9 + -1 + 0x9 + + + ZQ_PU_OFFSET_10 + -2 + 0xA + + + ZQ_PU_OFFSET_11 + -3 + 0xB + + + ZQ_PU_OFFSET_12 + -4 + 0xC + + + ZQ_PU_OFFSET_13 + -5 + 0xD + + + ZQ_PU_OFFSET_14 + -6 + 0xE + + + ZQ_PU_OFFSET_15 + -7 + 0xF + + + + + CA_DL_ABS_OFFSET + Absolute CA (Command/Address of LPDDRR2) offset + 0x10 + 7 + read-write + + + PHY_CA_DL_UNIT + This field reflects the number of delay units that are actually used by CA(Command/Address of LPDDR2) delay-line + 0x18 + 7 + read-only + + + + + MPSWDAR0 + MMDC PHY SW Dummy Access Register + 0x894 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_DUMMY_WR + SW dummy write + 0 + 1 + read-write + + + SW_DUMMY_RD + SW dummy read + 0x1 + 1 + read-write + + + SW_DUM_CMP0 + SW dummy read byte0 compare results + 0x2 + 1 + read-only + + + SW_DUM_CMP0_0 + Dummy read fail + 0 + + + SW_DUM_CMP0_1 + Dummy read pass + 0x1 + + + + + SW_DUM_CMP1 + SW dummy read byte1 compare results + 0x3 + 1 + read-only + + + SW_DUM_CMP1_0 + Dummy read fail + 0 + + + SW_DUM_CMP1_1 + Dummy read pass + 0x1 + + + + + + + MPSWDRDR0 + MMDC PHY SW Dummy Read Data Register 0 + 0x898 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD0 + Dummy read data0 + 0 + 32 + read-only + + + + + MPSWDRDR1 + MMDC PHY SW Dummy Read Data Register 1 + 0x89C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD1 + Dummy read data1 + 0 + 32 + read-only + + + + + MPSWDRDR2 + MMDC PHY SW Dummy Read Data Register 2 + 0x8A0 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD2 + Dummy read data2 + 0 + 32 + read-only + + + + + MPSWDRDR3 + MMDC PHY SW Dummy Read Data Register 3 + 0x8A4 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD3 + Dummy read data3 + 0 + 32 + read-only + + + + + MPSWDRDR4 + MMDC PHY SW Dummy Read Data Register 4 + 0x8A8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD4 + Dummy read data4 + 0 + 32 + read-only + + + + + MPSWDRDR5 + MMDC PHY SW Dummy Read Data Register 5 + 0x8AC + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD5 + Dummy read data5 + 0 + 32 + read-only + + + + + MPSWDRDR6 + MMDC PHY SW Dummy Read Data Register 6 + 0x8B0 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD6 + Dummy read data6 + 0 + 32 + read-only + + + + + MPSWDRDR7 + MMDC PHY SW Dummy Read Data Register 7 + 0x8B4 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD7 + Dummy read data7 + 0 + 32 + read-only + + + + + MPMUR0 + MMDC PHY Measure Unit Register + 0x8B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MU_BYP_VAL + Number of delay units for measurement bypass + 0 + 10 + read-write + + + MU_BYP_EN + Measure unit bypass enable + 0xA + 1 + read-write + + + MU_BYP_EN_0 + The delay-lines use delay units as indicated at MU_UNIT_DEL_NUM. + 0 + + + MU_BYP_EN_1 + The delay-lines use delay units as indicated at MU_BYPASS_VAL. + 0x1 + + + + + FRC_MSR + Force measurement on delay-lines + 0xB + 1 + read-write + + + FRC_MSR_0 + No measurement is performed + 0 + + + FRC_MSR_1 + Perform measurement process + 0x1 + + + + + MU_UNIT_DEL_NUM + Number of delay units measured per cycle + 0x10 + 10 + read-only + + + + + MPWRCADL + MMDC Write CA delay-line controller + 0x8BC + 32 + read-write + 0 + 0xFFFFFFFF + + + WR_CA0_DEL + CA(Command/Address LPDDR2 bus) bit 0 delay fine tuning + 0 + 2 + read-write + + + WR_CA0_DEL_0 + No change in CA0 delay + 0 + + + WR_CA0_DEL_1 + Add CA0 delay of 1 delay unit + 0x1 + + + WR_CA0_DEL_2 + Add CA0 delay of 2 delay units. + 0x2 + + + WR_CA0_DEL_3 + Add CA0 delay of 3 delay units. + 0x3 + + + + + WR_CA1_DEL + CA (Command/Address LPDDR2 bus) bit 1 delay fine tuning + 0x2 + 2 + read-write + + + WR_CA1_DEL_0 + No change in CA1 delay + 0 + + + WR_CA1_DEL_1 + Add CA1 delay of 1 delay unit + 0x1 + + + WR_CA1_DEL_2 + Add CA1 delay of 2 delay units. + 0x2 + + + WR_CA1_DEL_3 + Add CA1 delay of 3 delay units. + 0x3 + + + + + WR_CA2_DEL + CA (Command/Address LPDDR2 bus) bit 2 delay fine tuning + 0x4 + 2 + read-write + + + WR_CA2_DEL_0 + No change in CA2 delay + 0 + + + WR_CA2_DEL_1 + Add CA2 delay of 1 delay unit + 0x1 + + + WR_CA2_DEL_2 + Add CA2 delay of 2 delay units. + 0x2 + + + WR_CA2_DEL_3 + Add CA2 delay of 3 delay units. + 0x3 + + + + + WR_CA3_DEL + CA (Command/Address LPDDR2 bus) bit 3 delay fine tuning + 0x6 + 2 + read-write + + + WR_CA3_DEL_0 + No change in CA3 delay + 0 + + + WR_CA3_DEL_1 + Add CA3 delay of 1 delay unit + 0x1 + + + WR_CA3_DEL_2 + Add CA3 delay of 2 delay units. + 0x2 + + + WR_CA3_DEL_3 + Add CA3 delay of 3 delay units. + 0x3 + + + + + WR_CA4_DEL + CA (Command/Address LPDDR2 bus) bit 4 delay fine tuning + 0x8 + 2 + read-write + + + WR_CA4_DEL_0 + No change in CA4 delay + 0 + + + WR_CA4_DEL_1 + Add CA4 delay of 1 delay unit + 0x1 + + + WR_CA4_DEL_2 + Add CA4 delay of 2 delay units. + 0x2 + + + WR_CA4_DEL_3 + Add CA4 delay of 3 delay units. + 0x3 + + + + + WR_CA5_DEL + CA (Command/Address LPDDR2 bus) bit 5 delay fine tuning + 0xA + 2 + read-write + + + WR_CA5_DEL_0 + No change in CA5 delay + 0 + + + WR_CA5_DEL_1 + Add CA5 delay of 1 delay unit + 0x1 + + + WR_CA5_DEL_2 + Add CA5 delay of 2 delay units. + 0x2 + + + WR_CA5_DEL_3 + Add CA5 delay of 3 delay units. + 0x3 + + + + + WR_CA6_DEL + CA (Command/Address LPDDR2 bus) bit 6 delay fine tuning + 0xC + 2 + read-write + + + WR_CA6_DEL_0 + No change in CA6 delay + 0 + + + WR_CA6_DEL_1 + Add CA6 delay of 1 delay unit + 0x1 + + + WR_CA6_DEL_2 + Add CA6 delay of 2 delay units. + 0x2 + + + WR_CA6_DEL_3 + Add CA6 delay of 3 delay units. + 0x3 + + + + + WR_CA7_DEL + CA (Command/Address LPDDR2 bus) bit 7 delay fine tuning + 0xE + 2 + read-write + + + WR_CA7_DEL_0 + No change in CA7 delay + 0 + + + WR_CA7_DEL_1 + Add CA7 delay of 1 delay unit + 0x1 + + + WR_CA7_DEL_2 + Add CA7 delay of 2 delay units. + 0x2 + + + WR_CA7_DEL_3 + Add CA7 delay of 3 delay units. + 0x3 + + + + + WR_CA8_DEL + CA (Command/Address LPDDR2 bus) bit 8 delay fine tuning + 0x10 + 2 + read-write + + + WR_CA8_DEL_0 + No change in CA8 delay + 0 + + + WR_CA8_DEL_1 + Add CA8 delay of 1 delay unit + 0x1 + + + WR_CA8_DEL_2 + Add CA8 delay of 2 delay units. + 0x2 + + + WR_CA8_DEL_3 + Add CA8 delay of 3 delay units. + 0x3 + + + + + WR_CA9_DEL + CA (Command/Address LPDDR2 bus) bit 9 delay fine tuning + 0x12 + 2 + read-write + + + WR_CA9_DEL_0 + No change in CA9 delay + 0 + + + WR_CA9_DEL_1 + Add CA9 delay of 1 delay unit + 0x1 + + + WR_CA9_DEL_2 + Add CA9 delay of 2 delay units. + 0x2 + + + WR_CA9_DEL_3 + Add CA9 delay of 3 delay units. + 0x3 + + + + + + + MPDCCR + MMDC Duty Cycle Control Register + 0x8C0 + 32 + read-write + 0x24922492 + 0xFFFFFFFF + + + WR_DQS0_FT_DCC + Write DQS duty cycle fine tuning control of Byte0 + 0 + 3 + read-write + + + WR_DQS0_FT_DCC_1 + 51.5% low 48.5% high + 0x1 + + + WR_DQS0_FT_DCC_2 + 50% duty cycle (default) + 0x2 + + + WR_DQS0_FT_DCC_4 + 48.5% low 51.5% high + 0x4 + + + + + WR_DQS1_FT_DCC + Write DQS duty cycle fine tuning control of Byte1 + 0x3 + 3 + read-write + + + WR_DQS1_FT_DCC_1 + 51.5% low 48.5% high + 0x1 + + + WR_DQS1_FT_DCC_2 + 50% duty cycle (default) + 0x2 + + + WR_DQS1_FT_DCC_4 + 48.5% low 51.5% high + 0x4 + + + + + CK_FT0_DCC + Primary duty cycle fine tuning control of DDR clock + 0xC + 3 + read-write + + + CK_FT0_DCC_1 + 48.5% low 51.5% high + 0x1 + + + CK_FT0_DCC_2 + 50% duty cycle (default) + 0x2 + + + CK_FT0_DCC_4 + 51.5% low 48.5% high + 0x4 + + + + + CK_FT1_DCC + Secondary duty cycle fine tuning control of DDR clock + 0x10 + 3 + read-write + + + CK_FT1_DCC_1 + 48.5% low 51.5% high + 0x1 + + + CK_FT1_DCC_2 + 50% duty cycle (default) + 0x2 + + + CK_FT1_DCC_4 + 51.5% low 48.5% high + 0x4 + + + + + RD_DQS0_FT_DCC + Read DQS duty cycle fine tuning control of Byte0 + 0x13 + 3 + read-write + + + RD_DQS0_FT_DCC_1 + 51.5% low 48.5% high + 0x1 + + + RD_DQS0_FT_DCC_2 + 50% duty cycle (default) + 0x2 + + + RD_DQS0_FT_DCC_4 + 48.5% low 51.5% high + 0x4 + + + + + RD_DQS1_FT_DCC + Read DQS duty cycle fine tuning control of Byte1 + 0x16 + 3 + read-write + + + RD_DQS1_FT_DCC_1 + 51.5% low 48.5% high + 0x1 + + + RD_DQS1_FT_DCC_2 + 50% duty cycle (default) + 0x2 + + + RD_DQS1_FT_DCC_4 + 48.5% low 51.5% high + 0x4 + + + + + + + + + EIM + EIM + EIM + EIM_ + 0x21B8000 + + 0 + 0x94 + registers + + + WEIM + 46 + + + + 6 + 0x18 + CS%sGCR1 + Chip Select n General Configuration Register 1 + 0 + 32 + read-write + 0x10080 + 0xFFFFFFFF + + + CSEN + CS Enable + 0 + 1 + read-write + + + CSEN_0 + Chip select function is disabled; attempts to access an address mapped by this chip select results in an error respond and no assertion of the chip select output + 0 + + + CSEN_1 + Chip select is enabled, and is asserted when presented with a valid access. + 0x1 + + + + + SWR + Synchronous Write Data + 0x1 + 1 + read-write + + + SWR_0 + write accesses are in Asynchronous mode + 0 + + + SWR_1 + write accesses are in Synchronous mode + 0x1 + + + + + SRD + Synchronous Read Data + 0x2 + 1 + read-write + + + SRD_0 + read accesses are in Asynchronous mode + 0 + + + SRD_1 + read accesses are in Synchronous mode + 0x1 + + + + + MUM + Multiplexed Mode + 0x3 + 1 + read-write + + + MUM_0 + Multiplexed Mode disable + 0 + + + MUM_1 + Multiplexed Mode enable + 0x1 + + + + + WFL + Write Fix Latency + 0x4 + 1 + read-write + + + WFL_0 + the External device WAIT signal is being monitored, and it reflect the external data bus state + 0 + + + WFL_1 + the state of the External devices is determined internally (Fix latency mode only) + 0x1 + + + + + RFL + Read Fix Latency + 0x5 + 1 + read-write + + + RFL_0 + the External device WAIT signal is being monitored, and it reflect the external data bus state + 0 + + + RFL_1 + the state of the External devices is determined internally (Fix latency mode only) + 0x1 + + + + + CRE + Configuration Register Enable + 0x6 + 1 + read-write + + + CRE_0 + CRE signal use is disable + 0 + + + CRE_1 + CRE signal use is enable + 0x1 + + + + + CREP + Configuration Register Enable Polarity + 0x7 + 1 + read-write + + + CREP_0 + CRE signal is active low + 0 + + + CREP_1 + CRE signal is active high + 0x1 + + + + + BL + Burst Length + 0x8 + 3 + read-write + + + BL_0 + 4 words Memory wrap burst length (read page burst size when APR = 1) + 0 + + + BL_1 + 8 words Memory wrap burst length (read page burst size when APR = 1) + 0x1 + + + BL_2 + 16 words Memory wrap burst length (read page burst size when APR = 1) + 0x2 + + + BL_3 + 32 words Memory wrap burst length (read page burst size when APR = 1) + 0x3 + + + BL_4 + Continuous burst length (2 words read page burst size when APR = 1) + 0x4 + + + + + WC + Write Continuous + 0xB + 1 + read-write + + + WC_0 + Write access burst length occurs according to BL value. + 0 + + + WC_1 + Write access burst length is continuous. + 0x1 + + + + + BCD + Burst Clock Divisor + 0xC + 2 + read-write + + + BCD_0 + Divide EIM clock by 1 + 0 + + + BCD_1 + Divide EIM clock by 2 + 0x1 + + + BCD_2 + Divide EIM clock by 3 + 0x2 + + + BCD_3 + Divide EIM clock by 4 + 0x3 + + + + + BCS + Burst Clock Start + 0xE + 2 + read-write + + + BCS_0 + 0 EIM clock cycle additional delay + 0 + + + BCS_1 + 1 EIM clock cycle additional delay + 0x1 + + + BCS_2 + 2 EIM clock cycle additional delay + 0x2 + + + BCS_3 + 3 EIM clock cycle additional delay + 0x3 + + + + + DSZ + Data Port Size + 0x10 + 3 + read-write + + + DSZ_1 + 16 bit port resides on DATA[15:0] + 0x1 + + + DSZ_2 + 16 bit port resides on DATA[31:16] + 0x2 + + + DSZ_3 + 32 bit port resides on DATA[31:0] + 0x3 + + + DSZ_4 + 8 bit port resides on DATA[7:0] + 0x4 + + + DSZ_5 + 8 bit port resides on DATA[15:8] + 0x5 + + + DSZ_6 + 8 bit port resides on DATA[23:16] + 0x6 + + + DSZ_7 + 8 bit port resides on DATA[31:24] + 0x7 + + + + + SP + Supervisor Protect + 0x13 + 1 + read-write + + + SP_0 + User mode accesses are allowed in the memory range defined by chip select. + 0 + + + SP_1 + User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in an error response and no assertion of the chip select output. + 0x1 + + + + + CSREC + CS Recovery + 0x14 + 3 + read-write + + + CSREC_0 + 0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only) + 0 + + + CSREC_1 + 1 EIM clock cycles minimum width of CS, OE and WE signals + 0x1 + + + CSREC_2 + 2 EIM clock cycles minimum width of CS, OE and WE signals + 0x2 + + + CSREC_7 + 7 EIM clock cycles minimum width of CS, OE and WE signals + 0x7 + + + + + AUS + Address UnShifted + 0x17 + 1 + read-write + + + AUS_0 + Address shifted according to port size (DSZ config) (128 Mbyte maximum supported memory density). + 0 + + + AUS_1 + Address unshifted (32 Mbyte maximum supported memory density). + 0x1 + + + + + GBC + Gap Between Chip Selects + 0x18 + 3 + read-write + + + GBC_0 + minimum of 0 EIM clock cycles before next access from different chip select (async. mode only) + 0 + + + GBC_1 + minimum of 1 EIM clock cycles before next access from different chip select + 0x1 + + + GBC_2 + minimum of 2 EIM clock cycles before next access from different chip select + 0x2 + + + GBC_7 + minimum of 7 EIM clock cycles before next access from different chip select + 0x7 + + + + + WP + Write Protect + 0x1B + 1 + read-write + + + WP_0 + Writes are allowed in the memory range defined by chip. + 0 + + + WP_1 + Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response and no assertion of the chip select output. + 0x1 + + + + + PSZ + Page Size + 0x1C + 4 + read-write + + + PSZ_0 + 8 words page size + 0 + + + PSZ_1 + 16 words page size + 0x1 + + + PSZ_2 + 32 words page size + 0x2 + + + PSZ_3 + 64 words page size + 0x3 + + + PSZ_4 + 128 words page size + 0x4 + + + PSZ_5 + 256 words page size + 0x5 + + + PSZ_6 + 512 words page size + 0x6 + + + PSZ_7 + 1024 (1k) words page size + 0x7 + + + PSZ_8 + 2048 (2k) words page size + 0x8 + + + PSZ_9 + - 1111 Reserved + 0x9 + + + + + + + 6 + 0x18 + CS%sGCR2 + Chip Select n General Configuration Register 2 + 0x4 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ADH + Address hold time - This bit field determine the address hold time after ADV negation when mum = 1 (muxed mode) + 0 + 2 + read-write + + + ADH_0 + 0 cycle after ADV negation + 0 + + + ADH_1 + 1 cycle after ADV negation + 0x1 + + + ADH_2 + 2 cycle after ADV negation + 0x2 + + + + + DAPS + Data Acknowledge Poling Start + 0x4 + 4 + read-write + + + DAPS_0 + 3 EIM clk cycle between start of access and first DTACK check + 0 + + + DAPS_1 + 4 EIM clk cycles between start of access and first DTACK check + 0x1 + + + DAPS_2 + 5 EIM clk cycles between start of access and first DTACK check + 0x2 + + + DAPS_7 + 10 EIM clk cycles between start of access and first DTACK check + 0x7 + + + DAPS_11 + 14 EIM clk cycles between start of access and first DTACK check + 0xB + + + DAPS_15 + 18 EIM clk cycles between start of access and first DTACK check + 0xF + + + + + DAE + Data Acknowledge Enable + 0x8 + 1 + read-write + + + DAE_0 + DTACK signal use is disable + 0 + + + DAE_1 + DTACK signal use is enable + 0x1 + + + + + DAP + Data Acknowledge Polarity + 0x9 + 1 + read-write + + + DAP_0 + DTACK signal is active high + 0 + + + DAP_1 + DTACK signal is active low + 0x1 + + + + + MUX16_BYP_GRANT + Muxed 16 bypass grant + 0xC + 1 + read-write + + + MUX16_BYP_GRANT_0 + EIM waits for grant before driving a 16 bit muxed mode access to the memory. + 0 + + + MUX16_BYP_GRANT_1 + EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory. + 0x1 + + + + + + + 6 + 0x18 + CS%sRCR1 + Chip Select n Read Configuration Register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RCSN + Read CS Negation + 0 + 3 + read-write + + + RCSN_0 + 0 EIM clock cycles between end of read access and CS negation + 0 + + + RCSN_1 + 1 EIM clock cycles between end of read access and CS negation + 0x1 + + + RCSN_2 + 2 EIM clock cycles between end of read access and CS negation + 0x2 + + + RCSN_7 + 7 EIM clock cycles between end of read access and CS negation + 0x7 + + + + + RCSA + Read CS Assertion + 0x4 + 3 + read-write + + + RCSA_0 + 0 EIM clock cycles between beginning of read access and CS assertion + 0 + + + RCSA_1 + 1 EIM clock cycles between beginning of read access and CS assertion + 0x1 + + + RCSA_2 + 2 EIM clock cycles between beginning of read access and CS assertion + 0x2 + + + RCSA_7 + 7 EIM clock cycles between beginning of read access and CS assertion + 0x7 + + + + + OEN + OE Negation + 0x8 + 3 + read-write + + + OEN_0 + 0 EIM clock cycles between end of access and OE negation + 0 + + + OEN_1 + 1 EIM clock cycles between end of access and OE negation + 0x1 + + + OEN_2 + 2 EIM clock cycles between end of access and OE negation + 0x2 + + + OEN_7 + 7 EIM clock cycles between end of access and OE negation + 0x7 + + + + + OEA + OE Assertion + 0xC + 3 + read-write + + + OEA_0 + 0 EIM clock cycles between beginning of access and OE assertion + 0 + + + OEA_1 + 1 EIM clock cycles between beginning of access and OE assertion + 0x1 + + + OEA_2 + 2 EIM clock cycles between beginning of access and OE assertion + 0x2 + + + OEA_7 + 7 EIM clock cycles between beginning of access and OE assertion + 0x7 + + + + + RADVN + ADV Negation + 0x10 + 3 + read-write + + + RAL + Read ADV Low + 0x13 + 1 + read-write + + + RADVA + ADV Assertion + 0x14 + 3 + read-write + + + RADVA_0 + 0 EIM clock cycles between beginning of access and ADV assertion + 0 + + + RADVA_1 + 1 EIM clock cycles between beginning of access and ADV assertion + 0x1 + + + RADVA_2 + 2 EIM clock cycles between beginning of access and ADV assertion + 0x2 + + + RADVA_7 + 7 EIM clock cycles between beginning of access and ADV assertion + 0x7 + + + + + RWSC + Read Wait State Control + 0x18 + 6 + read-write + + + RWSC_1 + RWSC value is 1 + 0x1 + + + RWSC_2 + RWSC value is 2 + 0x2 + + + RWSC_61 + RWSC value is 61 + 0x3D + + + RWSC_62 + RWSC value is 62 + 0x3E + + + RWSC_63 + RWSC value is 63 + 0x3F + + + + + + + 6 + 0x18 + CS%sRCR2 + Chip Select n Read Configuration Register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RBEN + Read BE Negation + 0 + 3 + read-write + + + RBEN_0 + 0 EIM clock cycles between end of read access and BE negation + 0 + + + RBEN_1 + 1 EIM clock cycles between end of read access and BE negation + 0x1 + + + RBEN_2 + 2 EIM clock cycles between end of read access and BE negation + 0x2 + + + RBEN_7 + 7 EIM clock cycles between end of read access and BE negation + 0x7 + + + + + RBE + Read BE enable. This bit field determines if BE will be asserted during read access. + 0x3 + 1 + read-write + + + RBE_0 + - BE are disabled during read access. + 0 + + + + + RBEA + Read BE Assertion + 0x4 + 3 + read-write + + + RBEA_0 + 0 EIM clock cycles between beginning of read access and BE assertion + 0 + + + RBEA_1 + 1 EIM clock cycles between beginning of read access and BE assertion + 0x1 + + + RBEA_2 + 2 EIM clock cycles between beginning of read access and BE assertion + 0x2 + + + RBEA_7 + 7 EIM clock cycles between beginning of read access and BE assertion + 0x7 + + + + + RL + Read Latency + 0x8 + 2 + read-write + + + RL_0 + Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0 + 0 + + + RL_1 + Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0 + 0x1 + + + RL_2 + Feedback clock loop delay is up to 3 cycles for BCD = 0 or 3.5 cycles for BCD != 0 + 0x2 + + + RL_3 + Feedback clock loop delay is up to 4 cycles for BCD = 0 or 4.5 cycles for BCD != 0 + 0x3 + + + + + PAT + Page Access Time + 0xC + 3 + read-write + + + PAT_0 + Address width is 2 EIM clock cycles + 0 + + + PAT_1 + Address width is 3 EIM clock cycles + 0x1 + + + PAT_2 + Address width is 4 EIM clock cycles + 0x2 + + + PAT_3 + Address width is 5 EIM clock cycles + 0x3 + + + PAT_4 + Address width is 6 EIM clock cycles + 0x4 + + + PAT_5 + Address width is 7 EIM clock cycles + 0x5 + + + PAT_6 + Address width is 8 EIM clock cycles + 0x6 + + + PAT_7 + Address width is 9 EIM clock cycles + 0x7 + + + + + APR + Asynchronous Page Read + 0xF + 1 + read-write + + + + + 6 + 0x18 + CS%sWCR1 + Chip Select n Write Configuration Register 1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + WCSN + Write CS Negation + 0 + 3 + read-write + + + WCSN_0 + 0 EIM clock cycles between end of read access and CS negation + 0 + + + WCSN_1 + 1 EIM clock cycles between end of read access and CS negation + 0x1 + + + WCSN_2 + 2 EIM clock cycles between end of read access and CS negation + 0x2 + + + WCSN_7 + 7 EIM clock cycles between end of read access and CS negation + 0x7 + + + + + WCSA + Write CS Assertion + 0x3 + 3 + read-write + + + WCSA_0 + 0 EIM clock cycles between beginning of write access and CS assertion + 0 + + + WCSA_1 + 1 EIM clock cycles between beginning of write access and CS assertion + 0x1 + + + WCSA_2 + 2 EIM clock cycles between beginning of write access and CS assertion + 0x2 + + + WCSA_7 + 7 EIMclock cycles between beginning of write access and CS assertion + 0x7 + + + + + WEN + WE Negation + 0x6 + 3 + read-write + + + WEN_0 + 0 EIM clock cycles between beginning of access and WE assertion + 0 + + + WEN_1 + 1 EIM clock cycles between beginning of access and WE assertion + 0x1 + + + WEN_2 + 2 EIM clock cycles between beginning of access and WE assertion + 0x2 + + + WEN_7 + 7 EIM clock cycles between beginning of access and WE assertion + 0x7 + + + + + WEA + WE Assertion + 0x9 + 3 + read-write + + + WEA_0 + 0 EIM clock cycles between beginning of access and WE assertion + 0 + + + WEA_1 + 1 EIM clock cycles between beginning of access and WE assertion + 0x1 + + + WEA_2 + 2 EIM clock cycles between beginning of access and WE assertion + 0x2 + + + WEA_7 + 7 EIMclock cycles between beginning of access and WE assertion + 0x7 + + + + + WBEN + BE[3:0] Negation + 0xC + 3 + read-write + + + WBEA + BE Assertion + 0xF + 3 + read-write + + + WBEA_0 + 0 EIM clock cycles between beginning of access and BE assertion + 0 + + + WBEA_1 + 1 EIM clock cycles between beginning of access and BE assertion + 0x1 + + + WBEA_2 + 2 EIM clock cycles between beginning of access and BE assertion + 0x2 + + + WBEA_7 + 7 EIM clock cycles between beginning of access and BE assertion + 0x7 + + + + + WADVN + ADV Negation + 0x12 + 3 + read-write + + + WADVA + ADV Assertion + 0x15 + 3 + read-write + + + WADVA_0 + 0 EIM clock cycles between beginning of access and ADV assertion + 0 + + + WADVA_1 + 1 EIM clock cycles between beginning of access and ADV assertion + 0x1 + + + WADVA_2 + 2 EIM clock cycles between beginning of access and ADV assertion + 0x2 + + + WADVA_7 + 7 EIM clock cycles between beginning of access and ADV assertion + 0x7 + + + + + WWSC + Write Wait State Control + 0x18 + 6 + read-write + + + WWSC_1 + WWSC value is 1 + 0x1 + + + WWSC_2 + WWSC value is 2 + 0x2 + + + WWSC_3 + WWSC value is 3 + 0x3 + + + WWSC_63 + WWSC value is 63 + 0x3F + + + + + WBED + Write Byte Enable Disable + 0x1E + 1 + read-write + + + WAL + Write ADV Low + 0x1F + 1 + read-write + + + + + 6 + 0x18 + CS%sWCR2 + Chip Select n Write Configuration Register 2 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WBCDD + Write Burst Clock Divisor Decrement + 0 + 1 + read-write + + + + + WCR + EIM Configuration Register + 0x90 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + BCM + Burst Clock Mode + 0 + 1 + read-write + + + BCM_0 + The burst clock runs only when accessing a chip select range with the SWR/SRD bits set. When the burst clock is not running it remains in a logic 0 state. When the burst clock is running it is configured by the BCD and BCS bit fields in the chip select Configuration Register. + 0 + + + BCM_1 + The burst clock runs whenever ACLK is active (independent of chip select configuration) + 0x1 + + + + + GBCD + General Burst Clock Divisor + 0x1 + 2 + read-write + + + GBCD_0 + Divide EIM clock by 1 + 0 + + + GBCD_1 + Divide EIM clock by 2 + 0x1 + + + GBCD_2 + Divide EIM clock by 3 + 0x2 + + + GBCD_3 + Divide EIM clock by 4 + 0x3 + + + + + CONT_BCLK_SEL + Continuous BCLK select + 0x3 + 1 + read-write + + + CONT_BCLK_SEL_0 + BCLK When nesserary + 0 + + + CONT_BCLK_SEL_1 + BCLK Continuous + 0x1 + + + + + INTEN + Interrupt Enable + 0x4 + 1 + read-write + + + INTEN_0 + External interrupt Disable + 0 + + + INTEN_1 + External interrupt Enable + 0x1 + + + + + INTPOL + Interrupt Polarity. This bit field determines the polarity of the external device interrupt. + 0x5 + 1 + read-write + + + INTPOL_0 + External interrupt polarity is active low + 0 + + + INTPOL_1 + External interrupt polarity is active high + 0x1 + + + + + WDOG_EN + Memory WDOG enable + 0x8 + 1 + read-write + + + WDOG_EN_0 + Memory WDOG is Disabled + 0 + + + WDOG_EN_1 + Memory WDOG is Enabled + 0x1 + + + + + WDOG_LIMIT + Memory Watchdog (WDOG) cycle limit + 0x9 + 2 + read-write + + + WDOG_LIMIT_0 + 128 BCLK cycles + 0 + + + WDOG_LIMIT_1 + 256 BCLK cycles + 0x1 + + + WDOG_LIMIT_2 + 512 BCLK cycles + 0x2 + + + WDOG_LIMIT_3 + 1024 BCLK cycles + 0x3 + + + + + FRUN_ACLK_EN + Free run ACLK enable + 0xB + 1 + read-write + + + + + + + OCOTP + OCOTP Register Reference Index + OCOTP + OCOTP_ + 0x21BC000 + + 0 + 0x8F4 + registers + + + + CTRL + OTP Controller Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + RSVD0 + Reserved + 0x6 + 2 + read-only + + + BUSY + OTP controller status bit + 0x8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 0x9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 0xA + 1 + read-write + + + CRC_TEST + Set to calculate CRC according to start address and end address in CRC_ADDR register + 0xB + 1 + read-write + + + CRC_FAIL + Set by controller when calculated CRC value is not equal to appointed CRC fuse word + 0xC + 1 + read-write + + + RSVD1 + Reserved + 0xD + 3 + read-only + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 0x10 + 16 + read-write + + + KEY + Key needed to unlock HW_OCOTP_DATA register. + 0x3E77 + + + + + + + CTRL_SET + OTP Controller Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + RSVD0 + Reserved + 0x6 + 2 + read-only + + + BUSY + OTP controller status bit + 0x8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 0x9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 0xA + 1 + read-write + + + CRC_TEST + Set to calculate CRC according to start address and end address in CRC_ADDR register + 0xB + 1 + read-write + + + CRC_FAIL + Set by controller when calculated CRC value is not equal to appointed CRC fuse word + 0xC + 1 + read-write + + + RSVD1 + Reserved + 0xD + 3 + read-only + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 0x10 + 16 + read-write + + + KEY + Key needed to unlock HW_OCOTP_DATA register. + 0x3E77 + + + + + + + CTRL_CLR + OTP Controller Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + RSVD0 + Reserved + 0x6 + 2 + read-only + + + BUSY + OTP controller status bit + 0x8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 0x9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 0xA + 1 + read-write + + + CRC_TEST + Set to calculate CRC according to start address and end address in CRC_ADDR register + 0xB + 1 + read-write + + + CRC_FAIL + Set by controller when calculated CRC value is not equal to appointed CRC fuse word + 0xC + 1 + read-write + + + RSVD1 + Reserved + 0xD + 3 + read-only + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 0x10 + 16 + read-write + + + KEY + Key needed to unlock HW_OCOTP_DATA register. + 0x3E77 + + + + + + + CTRL_TOG + OTP Controller Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + RSVD0 + Reserved + 0x6 + 2 + read-only + + + BUSY + OTP controller status bit + 0x8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 0x9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 0xA + 1 + read-write + + + CRC_TEST + Set to calculate CRC according to start address and end address in CRC_ADDR register + 0xB + 1 + read-write + + + CRC_FAIL + Set by controller when calculated CRC value is not equal to appointed CRC fuse word + 0xC + 1 + read-write + + + RSVD1 + Reserved + 0xD + 3 + read-only + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 0x10 + 16 + read-write + + + KEY + Key needed to unlock HW_OCOTP_DATA register. + 0x3E77 + + + + + + + TIMING + OTP Controller Timing Register + 0x10 + 32 + read-write + 0x2C64116 + 0xFFFFFFFF + + + STROBE_PROG + This count value specifies the strobe period in one time write OTP + 0 + 12 + read-write + + + RELAX + This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd + 0xC + 4 + read-write + + + STROBE_READ + This count value specifies the strobe period in one time read OTP + 0x10 + 6 + read-write + + + WAIT + This count value specifies time interval between auto read and write access in one time program + 0x16 + 6 + read-write + + + RSRVD0 + These bits always read back zero. + 0x1C + 4 + read-only + + + + + DATA + OTP Controller Write Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Used to initiate a write to OTP + 0 + 32 + read-write + + + + + READ_CTRL + OTP Controller Write Data Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + READ_FUSE + Used to initiate a read to OTP + 0 + 1 + read-write + + + RSVD0 + Reserved + 0x1 + 31 + read-only + + + + + READ_FUSE_DATA + OTP Controller Read Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + The data read from OTP + 0 + 32 + read-write + + + + + SW_STICKY + Sticky bit Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRK_REVOKE_LOCK + Shadow register write and OTP write lock for SRK_REVOKE region + 0x1 + 1 + read-write + + + FIELD_RETURN_LOCK + Shadow register write and OTP write lock for FIELD_RETURN region + 0x2 + 1 + read-write + + + RSVD0 + Reserved + 0x5 + 27 + read-only + + + + + SCS + Software Controllable Signals Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 0x1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 0x1F + 1 + read-write + + + + + SCS_SET + Software Controllable Signals Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 0x1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 0x1F + 1 + read-write + + + + + SCS_CLR + Software Controllable Signals Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 0x1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 0x1F + 1 + read-write + + + + + SCS_TOG + Software Controllable Signals Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 0x1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 0x1F + 1 + read-write + + + + + CRC_ADDR + OTP Controller CRC test address + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_START_ADDR + End address of fuse location for CRC calculation + 0 + 8 + read-write + + + DATA_END_ADDR + Start address of fuse location for CRC calculation + 0x8 + 8 + read-write + + + CRC_ADDR + Address of 32-bit CRC result for comparing + 0x10 + 3 + read-write + + + OTPMK_CRC + Enable bit for CRC32 calculation address When OTPMK_CRC_ADDR_OTPMK_CRC bit sets to 1, calculation address sets to OTPMK_CRC (recommend) + 0x13 + 1 + read-write + + + RSVD0 + Reserved + 0x14 + 12 + read-only + + + + + CRC_VALUE + OTP Controller CRC Value Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + The crc32 value based on CRC_ADDR + 0 + 32 + read-write + + + + + VERSION + OTP Controller Version Register + 0x90 + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + TIMING2 + OTP Controller Timing Register 2 + 0x100 + 32 + read-write + 0x1C10042 + 0xFFFFFFFF + + + RELAX_PROG + This count value specifies the time to add to write OTP for complement address enable time. + 0 + 12 + read-write + + + RELAX_READ + This count value specifies the time to add to read OTP for complement address enable cycle time. + 0x10 + 6 + read-write + + + RELAX1 + Not used, preserved + 0x16 + 7 + read-write + + + + + LOCK + Value of OTP Bank0 Word0 (Lock controls) + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TESTER + Status of shadow register and OTP write lock for tester region + 0 + 2 + read-only + + + BOOT_CFG + Status of shadow register and OTP write lock for boot_cfg region + 0x2 + 2 + read-only + + + MEM_TRIM + Status of shadow register and OTP write lock for mem_trim region + 0x4 + 2 + read-only + + + SJC_RESP + Status of shadow register read and write, OTP read and write lock for sjc_resp region + 0x6 + 1 + read-only + + + RSVD0 + Reserved + 0x7 + 1 + read-only + + + MAC_ADDR + Status of shadow register and OTP write lock for mac_addr region + 0x8 + 2 + read-only + + + GP1 + Status of shadow register and OTP write lock for gp2 region + 0xA + 2 + read-only + + + GP2 + Status of shadow register and OTP write lock for gp2 region + 0xC + 2 + read-only + + + SRK + Status of shadow register and OTP write lock for srk region + 0xE + 1 + read-only + + + GP3 + Status of shadow register and OTP write lock for GP3 region + 0xF + 1 + read-only + + + SW_GP + Status of shadow register and OTP write lock for SW_GP region + 0x10 + 1 + read-only + + + OTPMK + Status of shadow register and OTP write lock for OTPMK region + 0x11 + 1 + read-only + + + ANALOG + Status of shadow register and OTP write lock for analog region + 0x12 + 2 + read-only + + + OTPMK_CRC + Status of shadow register and OTP write lock for otpmk crc region + 0x14 + 1 + read-only + + + ROM_PATCH + Status of shadow register and OTP write lock for rom_patch region + 0x15 + 1 + read-only + + + MISC_CONF + Status of shadow register and OTP write lock for misc_conf region + 0x16 + 1 + read-only + + + GP4 + Status of shadow register and OTP write lock for GP4 region + 0x17 + 1 + read-only + + + PIN + Status of Pin access lock bit. When set, pin access is disabled. + 0x19 + 1 + read-only + + + GP4_RLOCK + Status of shadow register and OTP read lock for GP4 region + 0x1E + 1 + read-write + + + GP3_RLOCK + Status of shadow register and OTP read lock for GP3 region + 0x1F + 1 + read-only + + + + + CFG0 + Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + This register contains 32 bits of the Unique ID and SJC_CHALLENGE field + 0 + 32 + read-write + + + + + CFG1 + Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + This register contains 32 bits of the Unique ID and SJC_CHALLENGE field + 0 + 32 + read-write + + + + + CFG2 + Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 3 (ADDR = 0x03) + 0 + 32 + read-write + + + + + CFG3 + Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 4 (ADDR = 0x04) + 0 + 32 + read-write + + + + + CFG4 + Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 5 (ADDR = 0x05) + 0 + 32 + read-write + + + + + CFG5 + Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 6 (ADDR = 0x06) + 0 + 32 + read-write + + + + + CFG6 + Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 7 (ADDR = 0x07) + 0 + 32 + read-write + + + + + MEM0 + Value of OTP Bank1 Word0 (Memory Related Info.) + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 0 (ADDR = 0x08) + 0 + 32 + read-write + + + + + MEM1 + Value of OTP Bank1 Word1 (Memory Related Info.) + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 1 (ADDR = 0x09) + 0 + 32 + read-write + + + + + MEM2 + Value of OTP Bank1 Word2 (Memory Related Info.) + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 2 (ADDR = 0x0A) + 0 + 32 + read-write + + + + + MEM3 + Value of OTP Bank1 Word3 (Memory Related Info.) + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 3 (ADDR = 0x0B) + 0 + 32 + read-write + + + + + MEM4 + Value of OTP Bank1 Word4 (Memory Related Info.) + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 4 (ADDR = 0x0C) + 0 + 32 + read-write + + + + + ANA0 + Value of OTP Bank1 Word5 (Memory Related Info.) + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 5 (ADDR = 0x0D) + 0 + 32 + read-write + + + + + ANA1 + Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 6 (ADDR = 0x0E) + 0 + 32 + read-write + + + + + ANA2 + Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 7 (ADDR = 0x0F) + 0 + 32 + read-write + + + + + OTPMK0 + Value of OTP Bank2 Word0 (OTPMK Key) + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 0 (ADDR = 0x10)) + 0 + 32 + read-write + + + + + OTPMK1 + Value of OTP Bank2 Word1 (OTPMK Key) + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 1 (ADDR = 0x11)) + 0 + 32 + read-write + + + + + OTPMK2 + Value of OTP Bank2 Word2 (OTPMK Key) + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 2 (ADDR = 0x12)) + 0 + 32 + read-write + + + + + OTPMK3 + Value of OTP Bank2 Word3 (OTPMK Key) + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 3 (ADDR = 0x13)) + 0 + 32 + read-write + + + + + OTPMK4 + Value of OTP Bank2 Word4 (OTPMK Key) + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 4 (ADDR = 0x14)) + 0 + 32 + read-write + + + + + OTPMK5 + Value of OTP Bank2 Word5 (OTPMK Key) + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 4 (ADDR = 0x14)) + 0 + 32 + read-write + + + + + OTPMK6 + Value of OTP Bank2 Word6 (OTPMK Key) + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 6 (ADDR = 0x16)) + 0 + 32 + read-write + + + + + OTPMK7 + Value of OTP Bank2 Word7 (OTPMK Key) + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 7 (ADDR = 0x17)) + 0 + 32 + read-write + + + + + SRK0 + Shadow Register for OTP Bank3 Word0 (SRK Hash) + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = 0x18)) + 0 + 32 + read-write + + + + + SRK1 + Shadow Register for OTP Bank3 Word1 (SRK Hash) + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = 0x19)) + 0 + 32 + read-write + + + + + SRK2 + Shadow Register for OTP Bank3 Word2 (SRK Hash) + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = 0x1A)) + 0 + 32 + read-write + + + + + SRK3 + Shadow Register for OTP Bank3 Word3 (SRK Hash) + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = 0x1B)) + 0 + 32 + read-write + + + + + SRK4 + Shadow Register for OTP Bank3 Word4 (SRK Hash) + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x1C)) + 0 + 32 + read-write + + + + + SRK5 + Shadow Register for OTP Bank3 Word5 (SRK Hash) + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x1D)) + 0 + 32 + read-write + + + + + SRK6 + Shadow Register for OTP Bank3 Word6 (SRK Hash) + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x1E)) + 0 + 32 + read-write + + + + + SRK7 + Shadow Register for OTP Bank3 Word7 (SRK Hash) + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = 0x1F)) + 0 + 32 + read-write + + + + + SJC_RESP0 + Value of OTP Bank4 Word0 (Secure JTAG Response Field) + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20)) + 0 + 32 + read-write + + + + + SJC_RESP1 + Value of OTP Bank4 Word1 (Secure JTAG Response Field) + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21)) + 0 + 32 + read-write + + + + + MAC0 + Value of OTP Bank4 Word2 (MAC Address) + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 2 (ADDR = 0x22). + 0 + 32 + read-write + + + + + MAC1 + Value of OTP Bank4 Word3 (MAC Address) + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 3 (ADDR = 0x23). + 0 + 32 + read-write + + + + + MAC + Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED) + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 4 (ADDR = 0x24). + 0 + 32 + read-write + + + + + CRC + Value of OTP Bank4 Word5 (CRC Key) + 0x650 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 5 (ADDR = 0x25). + 0 + 32 + read-write + + + + + GP1 + Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 6 (ADDR = 0x26). + 0 + 32 + read-write + + + + + GP2 + Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 7 (ADDR = 0x27). + 0 + 32 + read-write + + + + + SW_GP0 + Value of OTP Bank5 Word0 (SW GP) + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 0 (ADDR = 0x28). + 0 + 32 + read-write + + + + + SW_GP1 + Value of OTP Bank5 Word1 (SW GP) + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 1 (ADDR = 0x29). + 0 + 32 + read-write + + + + + SW_GP2 + Value of OTP Bank5 Word2 (SW GP) + 0x6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a). + 0 + 32 + read-write + + + + + SW_GP3 + Value of OTP Bank5 Word3 (SW GP) + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b). + 0 + 32 + read-write + + + + + SW_GP4 + Value of OTP Bank5 Word4 (SW GP) + 0x6C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c). + 0 + 32 + read-write + + + + + MISC_CONF + Value of OTP Bank5 Word5 (Misc Conf) + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d). + 0 + 32 + read-write + + + + + FIELD_RETURN + Value of OTP Bank5 Word6 (Field Return) + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e). + 0 + 32 + read-write + + + + + SRK_REVOKE + Value of OTP Bank5 Word7 (SRK Revoke) + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f). + 0 + 32 + read-write + + + + + ROM_PATCH0 + Value of OTP Bank6 Word0 (ROM Patch) + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 0 (ADDR = 0x30). + 0 + 32 + read-write + + + + + ROM_PATCH1 + Value of OTP Bank6 Word1 (ROM Patch) + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 1 (ADDR = 0x31). + 0 + 32 + read-write + + + + + ROM_PATCH2 + Value of OTP Bank6 Word2 (ROM Patch) + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 2 (ADDR = 0x32). + 0 + 32 + read-write + + + + + ROM_PATCH3 + Value of OTP Bank6 Word3 (ROM Patch) + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 3 (ADDR = 0x33). + 0 + 32 + read-write + + + + + ROM_PATCH4 + Value of OTP Bank6 Word4 (ROM Patch) + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 4 (ADDR = 0x34). + 0 + 32 + read-write + + + + + ROM_PATCH5 + Value of OTP Bank6 Word5 (ROM Patch) + 0x850 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 5 (ADDR = 0x35). + 0 + 32 + read-write + + + + + ROM_PATCH6 + Value of OTP Bank6 Word6 (ROM Patch) + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 6 (ADDR = 0x36). + 0 + 32 + read-write + + + + + ROM_PATCH7 + Value of OTP Bank6 Word7 (ROM Patch) + 0x870 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 7 (ADDR = 0x37). + 0 + 32 + read-write + + + + + GP3_0 + Value of OTP Bank7 Word0 (General Purpose Customer Defined Info) + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 0 (ADDR = 0x40). + 0 + 32 + read-write + + + + + GP3_1 + Value of OTP Bank7 Word1 (General Purpose Customer Defined Info) + 0x890 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 1 (ADDR = 0x41). + 0 + 32 + read-write + + + + + GP3_2 + Value of OTP Bank7 Word2 (General Purpose Customer Defined Info) + 0x8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 2 (ADDR = 0x42). + 0 + 32 + read-write + + + + + GP3_3 + Value of OTP Bank7 Word3 (General Purpose Customer Defined Info) + 0x8B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 3 (ADDR = 0x43). + 0 + 32 + read-write + + + + + GP3_4 + Value of OTP Bank8 Word4 (General Purpose Customer Defined Info) + 0x8C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 4 (ADDR = 0x44). + 0 + 32 + read-write + + + + + GP4_0 + Value of OTP Bank7 Word5 (General Purpose Customer Defined Info) + 0x8D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 5 (ADDR = 0x45). + 0 + 32 + read-write + + + + + GP4_1 + Value of OTP Bank7 Word6 (General Purpose Customer Defined Info) + 0x8E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 6 (ADDR = 0x46). + 0 + 32 + read-write + + + + + GP4_2 + Value of OTP Bank7 Word7 (General Purpose Customer Defined Info) + 0x8F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 7 (ADDR = 0x47). + 0 + 32 + read-write + + + + + + + CSI + CSI + CSI + CSI_ + 0x21C4000 + + 0 + 0x50 + registers + + + CSI + 39 + + + + CSICR1 + CSI Control Register 1 + 0 + 32 + read-write + 0x40000800 + 0xFFFFFFFF + + + PIXEL_BIT + Pixel Bit + 0 + 1 + read-write + + + PIXEL_BIT_0 + 8-bit data for each pixel + 0 + + + PIXEL_BIT_1 + 10-bit data for each pixel + 0x1 + + + + + REDGE + Valid Pixel Clock Edge Select + 0x1 + 1 + read-write + + + REDGE_0 + Pixel data is latched at the falling edge of CSI_PIXCLK + 0 + + + REDGE_1 + Pixel data is latched at the rising edge of CSI_PIXCLK + 0x1 + + + + + INV_PCLK + Invert Pixel Clock Input + 0x2 + 1 + read-write + + + INV_PCLK_0 + CSI_PIXCLK is directly applied to internal circuitry + 0 + + + INV_PCLK_1 + CSI_PIXCLK is inverted before applied to internal circuitry + 0x1 + + + + + INV_DATA + Invert Data Input. This bit enables or disables internal inverters on the data lines. + 0x3 + 1 + read-write + + + INV_DATA_0 + CSI_D[7:0] data lines are directly applied to internal circuitry + 0 + + + INV_DATA_1 + CSI_D[7:0] data lines are inverted before applied to internal circuitry + 0x1 + + + + + GCLK_MODE + Gated Clock Mode Enable + 0x4 + 1 + read-write + + + GCLK_MODE_0 + Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. + 0 + + + GCLK_MODE_1 + Gated clock mode. Pixel clock signal is valid only when HSYNC is active. + 0x1 + + + + + CLR_RXFIFO + Asynchronous RXFIFO Clear + 0x5 + 1 + read-write + + + CLR_STATFIFO + Asynchronous STATFIFO Clear + 0x6 + 1 + read-write + + + PACK_DIR + Data Packing Direction + 0x7 + 1 + read-write + + + PACK_DIR_0 + Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. + 0 + + + PACK_DIR_1 + Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. + 0x1 + + + + + FCC + FIFO Clear Control + 0x8 + 1 + read-write + + + FCC_0 + Asynchronous FIFO clear is selected. + 0 + + + FCC_1 + Synchronous FIFO clear is selected. + 0x1 + + + + + CCIR_EN + CCIR656 Interface Enable + 0xA + 1 + read-write + + + CCIR_EN_0 + Traditional interface is selected. Timing interface logic is used to latch data. + 0 + + + CCIR_EN_1 + CCIR656 interface is selected. + 0x1 + + + + + HSYNC_POL + HSYNC Polarity Select + 0xB + 1 + read-write + + + HSYNC_POL_0 + HSYNC is active low + 0 + + + HSYNC_POL_1 + HSYNC is active high + 0x1 + + + + + SOF_INTEN + Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. + 0x10 + 1 + read-write + + + SOF_INTEN_0 + SOF interrupt disable + 0 + + + SOF_INTEN_1 + SOF interrupt enable + 0x1 + + + + + SOF_POL + SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. + 0x11 + 1 + read-write + + + SOF_POL_0 + SOF interrupt is generated on SOF falling edge + 0 + + + SOF_POL_1 + SOF interrupt is generated on SOF rising edge + 0x1 + + + + + RXFF_INTEN + RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt. + 0x12 + 1 + read-write + + + RXFF_INTEN_0 + RxFIFO full interrupt disable + 0 + + + RXFF_INTEN_1 + RxFIFO full interrupt enable + 0x1 + + + + + FB1_DMA_DONE_INTEN + Frame Buffer1 DMA Transfer Done Interrupt Enable + 0x13 + 1 + read-write + + + FB1_DMA_DONE_INTEN_0 + Frame Buffer1 DMA Transfer Done interrupt disable + 0 + + + FB1_DMA_DONE_INTEN_1 + Frame Buffer1 DMA Transfer Done interrupt enable + 0x1 + + + + + FB2_DMA_DONE_INTEN + Frame Buffer2 DMA Transfer Done Interrupt Enable + 0x14 + 1 + read-write + + + FB2_DMA_DONE_INTEN_0 + Frame Buffer2 DMA Transfer Done interrupt disable + 0 + + + FB2_DMA_DONE_INTEN_1 + Frame Buffer2 DMA Transfer Done interrupt enable + 0x1 + + + + + STATFF_INTEN + STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt. + 0x15 + 1 + read-write + + + STATFF_INTEN_0 + STATFIFO full interrupt disable + 0 + + + STATFF_INTEN_1 + STATFIFO full interrupt enable + 0x1 + + + + + SFF_DMA_DONE_INTEN + STATFIFO DMA Transfer Done Interrupt Enable + 0x16 + 1 + read-write + + + SFF_DMA_DONE_INTEN_0 + STATFIFO DMA Transfer Done interrupt disable + 0 + + + SFF_DMA_DONE_INTEN_1 + STATFIFO DMA Transfer Done interrupt enable + 0x1 + + + + + RF_OR_INTEN + RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. + 0x18 + 1 + read-write + + + RF_OR_INTEN_0 + RxFIFO overrun interrupt is disabled + 0 + + + RF_OR_INTEN_1 + RxFIFO overrun interrupt is enabled + 0x1 + + + + + SF_OR_INTEN + STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt. + 0x19 + 1 + read-write + + + SF_OR_INTEN_0 + STATFIFO overrun interrupt is disabled + 0 + + + SF_OR_INTEN_1 + STATFIFO overrun interrupt is enabled + 0x1 + + + + + COF_INT_EN + Change Of Image Field (COF) Interrupt Enable + 0x1A + 1 + read-write + + + COF_INT_EN_0 + COF interrupt is disabled + 0 + + + COF_INT_EN_1 + COF interrupt is enabled + 0x1 + + + + + VIDEO_MODE + Video mode select. This bit controls the video mode in CCIR mode and TV decoder input. + 0x1B + 1 + read-write + + + VIDEO_MODE_0 + Progressive mode is selected + 0 + + + VIDEO_MODE_1 + Interlace mode is selected + 0x1 + + + + + PrP_IF_EN + CSI-PrP Interface Enable + 0x1C + 1 + read-write + + + PrP_IF_EN_0 + CSI to PrP bus is disabled + 0 + + + PrP_IF_EN_1 + CSI to PrP bus is enabled + 0x1 + + + + + EOF_INT_EN + End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. + 0x1D + 1 + read-write + + + EOF_INT_EN_0 + EOF interrupt is disabled. + 0 + + + EOF_INT_EN_1 + EOF interrupt is generated when RX count value is reached. + 0x1 + + + + + EXT_VSYNC + External VSYNC Enable + 0x1E + 1 + read-write + + + EXT_VSYNC_0 + Internal VSYNC mode + 0 + + + EXT_VSYNC_1 + External VSYNC mode + 0x1 + + + + + SWAP16_EN + SWAP 16-Bit Enable + 0x1F + 1 + read-write + + + SWAP16_EN_0 + Disable swapping + 0 + + + SWAP16_EN_1 + Enable swapping + 0x1 + + + + + + + CSICR2 + CSI Control Register 2 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HSC + Horizontal Skip Count + 0 + 8 + read-write + + + VSC + Vertical Skip Count. Contains the number of rows to skip. SCE must be 1, otherwise VSC is ignored. + 0x8 + 8 + read-write + + + LVRM + Live View Resolution Mode. Selects the grid size used for live view resolution. + 0x10 + 3 + read-write + + + LVRM_0 + 512 x 384 + 0 + + + LVRM_1 + 448 x 336 + 0x1 + + + LVRM_2 + 384 x 288 + 0x2 + + + LVRM_3 + 384 x 256 + 0x3 + + + LVRM_4 + 320 x 240 + 0x4 + + + LVRM_5 + 288 x 216 + 0x5 + + + LVRM_6 + 400 x 300 + 0x6 + + + + + BTS + Bayer Tile Start. Controls the Bayer pattern starting point. + 0x13 + 2 + read-write + + + BTS_0 + GR + 0 + + + BTS_1 + RG + 0x1 + + + BTS_2 + BG + 0x2 + + + BTS_3 + GB + 0x3 + + + + + SCE + Skip Count Enable. Enables or disables the skip count feature. + 0x17 + 1 + read-write + + + SCE_0 + Skip count disable + 0 + + + SCE_1 + Skip count enable + 0x1 + + + + + AFS + Auto Focus Spread. Selects which green pixels are used for auto-focus. + 0x18 + 2 + read-write + + + AFS_0 + Abs Diff on consecutive green pixels + 0 + + + AFS_1 + Abs Diff on every third green pixels + 0x1 + + + + + DRM + Double Resolution Mode. Controls size of statistics grid. + 0x1A + 1 + read-write + + + DRM_0 + Stats grid of 8 x 6 + 0 + + + DRM_1 + Stats grid of 8 x 12 + 0x1 + + + + + DMA_BURST_TYPE_SFF + Burst Type of DMA Transfer from STATFIFO. Selects the burst type of DMA transfer from STATFIFO. + 0x1C + 2 + read-write + + + DMA_BURST_TYPE_SFF_1 + INCR4 + 0x1 + + + DMA_BURST_TYPE_SFF_3 + INCR16 + 0x3 + + + + + DMA_BURST_TYPE_RFF + Burst Type of DMA Transfer from RxFIFO. Selects the burst type of DMA transfer from RxFIFO. + 0x1E + 2 + read-write + + + DMA_BURST_TYPE_RFF_1 + INCR4 + 0x1 + + + DMA_BURST_TYPE_RFF_3 + INCR16 + 0x3 + + + + + + + CSICR3 + CSI Control Register 3 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ECC_AUTO_EN + Automatic Error Correction Enable + 0 + 1 + read-write + + + ECC_AUTO_EN_0 + Auto Error correction is disabled. + 0 + + + ECC_AUTO_EN_1 + Auto Error correction is enabled. + 0x1 + + + + + ECC_INT_EN + Error Detection Interrupt Enable + 0x1 + 1 + read-write + + + ECC_INT_EN_0 + No interrupt is generated when error is detected. Only the status bit ECC_INT is set. + 0 + + + ECC_INT_EN_1 + Interrupt is generated when error is detected. + 0x1 + + + + + ZERO_PACK_EN + Dummy Zero Packing Enable + 0x2 + 1 + read-write + + + ZERO_PACK_EN_0 + Zero packing disabled + 0 + + + ZERO_PACK_EN_1 + Zero packing enabled + 0x1 + + + + + TWO_8BIT_SENSOR + Two 8-bit Sensor Mode + 0x3 + 1 + read-write + + + TWO_8BIT_SENSOR_0 + Only one sensor is connected. + 0 + + + TWO_8BIT_SENSOR_1 + Two 8-bit sensors are connected or one 16-bit sensor is connected. + 0x1 + + + + + RxFF_LEVEL + RxFIFO Full Level + 0x4 + 3 + read-write + + + RxFF_LEVEL_0 + 4 Words + 0 + + + RxFF_LEVEL_1 + 8 Words + 0x1 + + + RxFF_LEVEL_2 + 16 Words + 0x2 + + + RxFF_LEVEL_3 + 24 Words + 0x3 + + + RxFF_LEVEL_4 + 32 Words + 0x4 + + + RxFF_LEVEL_5 + 48 Words + 0x5 + + + RxFF_LEVEL_6 + 64 Words + 0x6 + + + RxFF_LEVEL_7 + 96 Words + 0x7 + + + + + HRESP_ERR_EN + Hresponse Error Enable. This bit enables the hresponse error interrupt. + 0x7 + 1 + read-write + + + HRESP_ERR_EN_0 + Disable hresponse error interrupt + 0 + + + HRESP_ERR_EN_1 + Enable hresponse error interrupt + 0x1 + + + + + STATFF_LEVEL + STATFIFO Full Level + 0x8 + 3 + read-write + + + STATFF_LEVEL_0 + 4 Words + 0 + + + STATFF_LEVEL_1 + 8 Words + 0x1 + + + STATFF_LEVEL_2 + 12 Words + 0x2 + + + STATFF_LEVEL_3 + 16 Words + 0x3 + + + STATFF_LEVEL_4 + 24 Words + 0x4 + + + STATFF_LEVEL_5 + 32 Words + 0x5 + + + STATFF_LEVEL_6 + 48 Words + 0x6 + + + STATFF_LEVEL_7 + 64 Words + 0x7 + + + + + DMA_REQ_EN_SFF + DMA Request Enable for STATFIFO + 0xB + 1 + read-write + + + DMA_REQ_EN_SFF_0 + Disable the dma request + 0 + + + DMA_REQ_EN_SFF_1 + Enable the dma request + 0x1 + + + + + DMA_REQ_EN_RFF + DMA Request Enable for RxFIFO + 0xC + 1 + read-write + + + DMA_REQ_EN_RFF_0 + Disable the dma request + 0 + + + DMA_REQ_EN_RFF_1 + Enable the dma request + 0x1 + + + + + DMA_REFLASH_SFF + Reflash DMA Controller for STATFIFO + 0xD + 1 + read-write + + + DMA_REFLASH_SFF_0 + No reflashing + 0 + + + DMA_REFLASH_SFF_1 + Reflash the embedded DMA controller + 0x1 + + + + + DMA_REFLASH_RFF + Reflash DMA Controller for RxFIFO + 0xE + 1 + read-write + + + DMA_REFLASH_RFF_0 + No reflashing + 0 + + + DMA_REFLASH_RFF_1 + Reflash the embedded DMA controller + 0x1 + + + + + FRMCNT_RST + Frame Count Reset. Resets the Frame Counter. (Cleared automatically after reset is done) + 0xF + 1 + read-write + + + FRMCNT_RST_0 + Do not reset + 0 + + + FRMCNT_RST_1 + Reset frame counter immediately + 0x1 + + + + + FRMCNT + Frame Counter + 0x10 + 16 + read-write + + + + + CSISTATFIFO + CSI Statistic FIFO Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT + Static data from sensor + 0 + 32 + read-only + + + + + CSIRFIFO + CSI RX FIFO Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMAGE + Received image data + 0 + 32 + read-only + + + + + CSIRXCNT + CSI RX Count Register + 0x14 + 32 + read-write + 0x9600 + 0xFFFFFFFF + + + RXCNT + RxFIFO Count + 0 + 22 + read-write + + + + + CSISR + CSI Status Register + 0x18 + 32 + read-write + 0x4000 + 0xFFFFFFFF + + + DRDY + RXFIFO Data Ready + 0 + 1 + read-write + + + DRDY_0 + No data (word) is ready + 0 + + + DRDY_1 + At least 1 datum (word) is ready in RXFIFO. + 0x1 + + + + + ECC_INT + CCIR Error Interrupt + 0x1 + 1 + read-write + + + ECC_INT_0 + No error detected + 0 + + + ECC_INT_1 + Error is detected in CCIR coding + 0x1 + + + + + HRESP_ERR_INT + Hresponse Error Interrupt Status + 0x7 + 1 + read-write + + + HRESP_ERR_INT_0 + No hresponse error. + 0 + + + HRESP_ERR_INT_1 + Hresponse error is detected. + 0x1 + + + + + COF_INT + Change Of Field Interrupt Status + 0xD + 1 + read-write + + + COF_INT_0 + Video field has no change. + 0 + + + COF_INT_1 + Change of video field is detected. + 0x1 + + + + + F1_INT + CCIR Field 1 Interrupt Status + 0xE + 1 + read-write + + + F1_INT_0 + Field 1 of video is not detected. + 0 + + + F1_INT_1 + Field 1 of video is about to start. + 0x1 + + + + + F2_INT + CCIR Field 2 Interrupt Status + 0xF + 1 + read-write + + + F2_INT_0 + Field 2 of video is not detected + 0 + + + F2_INT_1 + Field 2 of video is about to start + 0x1 + + + + + SOF_INT + Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) + 0x10 + 1 + read-write + + + SOF_INT_0 + SOF is not detected. + 0 + + + SOF_INT_1 + SOF is detected. + 0x1 + + + + + EOF_INT + End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) + 0x11 + 1 + read-write + + + EOF_INT_0 + EOF is not detected. + 0 + + + EOF_INT_1 + EOF is detected. + 0x1 + + + + + RxFF_INT + RXFIFO Full Interrupt Status + 0x12 + 1 + read-write + + + RxFF_INT_0 + RxFIFO is not full. + 0 + + + RxFF_INT_1 + RxFIFO is full. + 0x1 + + + + + DMA_TSF_DONE_FB1 + DMA Transfer Done in Frame Buffer1 + 0x13 + 1 + read-write + + + DMA_TSF_DONE_FB1_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_FB1_1 + DMA transfer is completed. + 0x1 + + + + + DMA_TSF_DONE_FB2 + DMA Transfer Done in Frame Buffer2 + 0x14 + 1 + read-write + + + DMA_TSF_DONE_FB2_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_FB2_1 + DMA transfer is completed. + 0x1 + + + + + STATFF_INT + STATFIFO Full Interrupt Status + 0x15 + 1 + read-write + + + STATFF_INT_0 + STATFIFO is not full. + 0 + + + STATFF_INT_1 + STATFIFO is full. + 0x1 + + + + + DMA_TSF_DONE_SFF + DMA Transfer Done from StatFIFO + 0x16 + 1 + read-write + + + DMA_TSF_DONE_SFF_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_SFF_1 + DMA transfer is completed. + 0x1 + + + + + RF_OR_INT + RxFIFO Overrun Interrupt Status + 0x18 + 1 + read-write + + + RF_OR_INT_0 + RXFIFO has not overflowed. + 0 + + + RF_OR_INT_1 + RXFIFO has overflowed. + 0x1 + + + + + SF_OR_INT + STATFIFO Overrun Interrupt Status + 0x19 + 1 + read-write + + + SF_OR_INT_0 + STATFIFO has not overflowed. + 0 + + + SF_OR_INT_1 + STATFIFO has overflowed. + 0x1 + + + + + DMA_FIELD1_DONE + When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). + 0x1A + 1 + read-write + + + DMA_FIELD0_DONE + When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). + 0x1B + 1 + read-write + + + BASEADDR_CHHANGE_ERROR + When using base address switching enable, this bit will be 1 when switching occur before DMA complete + 0x1C + 1 + read-write + + + + + CSIDMASA_STATFIFO + CSI DMA Start Address Register - for STATFIFO + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_SFF + DMA Start Address for STATFIFO + 0x2 + 30 + read-write + + + + + CSIDMATS_STATFIFO + CSI DMA Transfer Size Register - for STATFIFO + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_TSF_SIZE_SFF + DMA Transfer Size for STATFIFO + 0 + 32 + read-write + + + + + CSIDMASA_FB1 + CSI DMA Start Address Register - for Frame Buffer1 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_FB1 + DMA Start Address in Frame Buffer1 + 0x2 + 30 + read-write + + + + + CSIDMASA_FB2 + CSI DMA Transfer Size Register - for Frame Buffer2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_FB2 + DMA Start Address in Frame Buffer2 + 0x2 + 30 + read-write + + + + + CSIFBUF_PARA + CSI Frame Buffer Parameter Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FBUF_STRIDE + Frame Buffer Parameter + 0 + 16 + read-write + + + DEINTERLACE_STRIDE + DEINTERLACE_STRIDE is only used in the deinterlace mode + 0x10 + 16 + read-write + + + + + CSIIMAG_PARA + CSI Image Parameter Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMAGE_HEIGHT + Image Height. Indicates how many pixels in a column of the image from the sensor. + 0 + 16 + read-write + + + IMAGE_WIDTH + Image Width + 0x10 + 16 + read-write + + + + + CSICR18 + CSI Control Register 18 + 0x48 + 32 + read-write + 0x2D000 + 0xFFFFFFFF + + + DEINTERLACE_EN + This bit is used to select the output method When input is standard CCIR656 video. + 0x2 + 1 + read-write + + + DEINTERLACE_EN_0 + Deinterlace disabled + 0 + + + DEINTERLACE_EN_1 + Deinterlace enabled + 0x1 + + + + + PARALLEL24_EN + When input is parallel rgb888/yuv444 24bit, this bit can be enabled. + 0x3 + 1 + read-write + + + BASEADDR_SWITCH_EN + When this bit is enabled, CSI DMA will switch the base address according to BASEADDR_SWITCH_SEL rather than atomically by DMA completed + 0x4 + 1 + read-write + + + BASEADDR_SWITCH_SEL + CSI 2 base addresses switching method. When using this bit, BASEADDR_SWITCH_EN is 1. + 0x5 + 1 + read-write + + + BASEADDR_SWITCH_SEL_0 + Switching base address at the edge of the vsync + 0 + + + BASEADDR_SWITCH_SEL_1 + Switching base address at the edge of the first data of each frame + 0x1 + + + + + FIELD0_DONE_IE + In interlace mode, fileld 0 means interrupt enabled. + 0x6 + 1 + read-write + + + FIELD0_DONE_IE_0 + Interrupt disabled + 0 + + + FIELD0_DONE_IE_1 + Interrupt enabled + 0x1 + + + + + DMA_FIELD1_DONE_IE + When in interlace mode, field 1 done interrupt enable. + 0x7 + 1 + read-write + + + DMA_FIELD1_DONE_IE_0 + Interrupt disabled + 0 + + + DMA_FIELD1_DONE_IE_1 + Interrupt enabled + 0x1 + + + + + LAST_DMA_REQ_SEL + Choosing the last DMA request condition. + 0x8 + 1 + read-write + + + LAST_DMA_REQ_SEL_0 + fifo_full_level + 0 + + + LAST_DMA_REQ_SEL_1 + hburst_length + 0x1 + + + + + BASEADDR_CHANGE_ERROR_IE + Base address change error interrupt enable signal. + 0x9 + 1 + read-write + + + RGB888A_FORMAT_SEL + Output is 32-bit format. + 0xA + 1 + read-write + + + RGB888A_FORMAT_SEL_0 + {8'h0, data[23:0]} + 0 + + + RGB888A_FORMAT_SEL_1 + {data[23:0], 8'h0} + 0x1 + + + + + AHB_HPROT + Hprot value in AHB bus protocol. + 0xC + 4 + read-write + + + CSI_LCDIF_BUFFER_LINES + The number of lines are used in handshake mode with LCDIF. + 0x10 + 2 + read-write + + + CSI_LCDIF_BUFFER_LINES_0 + 4 lines + 0 + + + CSI_LCDIF_BUFFER_LINES_1 + 8 lines + 0x1 + + + CSI_LCDIF_BUFFER_LINES_2 + 16 lines + 0x2 + + + CSI_LCDIF_BUFFER_LINES_3 + 16 lines + 0x3 + + + + + MASK_OPTION + These bits used to choose the method to mask the CSI input. + 0x12 + 2 + read-write + + + MASK_OPTION_0 + Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1. + 0 + + + MASK_OPTION_1 + Writing to memory when CSI_ENABLE is 1. + 0x1 + + + MASK_OPTION_2 + Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. + 0x2 + + + MASK_OPTION_3 + Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. + 0x3 + + + + + CSI_ENABLE + CSI global enable signal + 0x1F + 1 + read-write + + + + + CSICR19 + CSI Control Register 19 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_RFIFO_HIGHEST_FIFO_LEVEL + This byte stores the highest FIFO level achieved by CSI FIFO timely and will be clear by writing 8'ff to it + 0 + 8 + read-write + + + + + + + LCDIF + eLCDIF Register Reference Index + LCDIF + LCDIF_ + 0x21C8000 + + 0 + 0x264 + registers + + + LCDIF + 37 + + + + CTRL + eLCDIF General Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 0x1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 0x2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 0x3 + 1 + read-write + + + MASTER + Set this bit to make the eLCDIF act as a bus master. + 0x5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + 0x6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 0x7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 0x8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 0xA + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 0xC + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 0xE + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 0x10 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 0x11 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the eLCDIF hardware go into VSYNC mode + 0x12 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 0x13 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 0x14 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 0x15 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 0x1A + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 0x1B + 1 + read-write + + + READ_WRITEB + By default, eLCDIF is in the write mode + 0x1C + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the eLCDIF + 0x1F + 1 + read-write + + + + + CTRL_SET + eLCDIF General Control Register + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 0x1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 0x2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 0x3 + 1 + read-write + + + MASTER + Set this bit to make the eLCDIF act as a bus master. + 0x5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + 0x6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 0x7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 0x8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 0xA + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 0xC + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 0xE + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 0x10 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 0x11 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the eLCDIF hardware go into VSYNC mode + 0x12 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 0x13 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 0x14 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 0x15 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 0x1A + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 0x1B + 1 + read-write + + + READ_WRITEB + By default, eLCDIF is in the write mode + 0x1C + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the eLCDIF + 0x1F + 1 + read-write + + + + + CTRL_CLR + eLCDIF General Control Register + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 0x1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 0x2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 0x3 + 1 + read-write + + + MASTER + Set this bit to make the eLCDIF act as a bus master. + 0x5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + 0x6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 0x7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 0x8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 0xA + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 0xC + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 0xE + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 0x10 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 0x11 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the eLCDIF hardware go into VSYNC mode + 0x12 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 0x13 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 0x14 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 0x15 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 0x1A + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 0x1B + 1 + read-write + + + READ_WRITEB + By default, eLCDIF is in the write mode + 0x1C + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the eLCDIF + 0x1F + 1 + read-write + + + + + CTRL_TOG + eLCDIF General Control Register + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 0x1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 0x2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 0x3 + 1 + read-write + + + MASTER + Set this bit to make the eLCDIF act as a bus master. + 0x5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + 0x6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 0x7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 0x8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 0xA + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 0xC + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 0xE + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 0x10 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 0x11 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the eLCDIF hardware go into VSYNC mode + 0x12 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 0x13 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 0x14 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 0x15 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 0x1A + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 0x1B + 1 + read-write + + + READ_WRITEB + By default, eLCDIF is in the write mode + 0x1C + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the eLCDIF + 0x1F + 1 + read-write + + + + + CTRL1 + eLCDIF General Control1 Register + 0x10 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 0x1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 0x2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xA + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xB + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 0xC + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 0xD + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 0xE + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 0xF + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 0x10 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 0x14 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 0x15 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 0x16 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + 0x17 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 0x18 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x19 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the eLCDIF master mode. + 0x1A + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 0x1B + 1 + read-write + + + + + CTRL1_SET + eLCDIF General Control1 Register + 0x14 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 0x1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 0x2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xA + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xB + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 0xC + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 0xD + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 0xE + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 0xF + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 0x10 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 0x14 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 0x15 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 0x16 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + 0x17 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 0x18 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x19 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the eLCDIF master mode. + 0x1A + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 0x1B + 1 + read-write + + + + + CTRL1_CLR + eLCDIF General Control1 Register + 0x18 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 0x1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 0x2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xA + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xB + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 0xC + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 0xD + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 0xE + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 0xF + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 0x10 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 0x14 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 0x15 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 0x16 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + 0x17 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 0x18 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x19 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the eLCDIF master mode. + 0x1A + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 0x1B + 1 + read-write + + + + + CTRL1_TOG + eLCDIF General Control1 Register + 0x1C + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 0x1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 0x2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xA + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xB + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 0xC + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 0xD + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 0xE + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 0xF + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 0x10 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 0x14 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 0x15 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 0x16 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + 0x17 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 0x18 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x19 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the eLCDIF master mode. + 0x1A + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 0x1B + 1 + read-write + + + + + CTRL2 + eLCDIF General Control2 Register + 0x20 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 0x1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 0x4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to eLCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 0x8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 0x9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 0xA + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 0xC + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 0x10 + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + BURST_LEN_8 + By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 0x14 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + 0x15 + 3 + read-write + + + REQ_1 + no description available + 0 + + + REQ_2 + no description available + 0x1 + + + REQ_4 + no description available + 0x2 + + + REQ_8 + no description available + 0x3 + + + REQ_16 + no description available + 0x4 + + + + + + + CTRL2_SET + eLCDIF General Control2 Register + 0x24 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 0x1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 0x4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to eLCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 0x8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 0x9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 0xA + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 0xC + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 0x10 + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + BURST_LEN_8 + By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 0x14 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + 0x15 + 3 + read-write + + + REQ_1 + no description available + 0 + + + REQ_2 + no description available + 0x1 + + + REQ_4 + no description available + 0x2 + + + REQ_8 + no description available + 0x3 + + + REQ_16 + no description available + 0x4 + + + + + + + CTRL2_CLR + eLCDIF General Control2 Register + 0x28 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 0x1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 0x4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to eLCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 0x8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 0x9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 0xA + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 0xC + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 0x10 + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + BURST_LEN_8 + By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 0x14 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + 0x15 + 3 + read-write + + + REQ_1 + no description available + 0 + + + REQ_2 + no description available + 0x1 + + + REQ_4 + no description available + 0x2 + + + REQ_8 + no description available + 0x3 + + + REQ_16 + no description available + 0x4 + + + + + + + CTRL2_TOG + eLCDIF General Control2 Register + 0x2C + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 0x1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 0x4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to eLCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 0x8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 0x9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 0xA + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 0xC + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 0x10 + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + BURST_LEN_8 + By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 0x14 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + 0x15 + 3 + read-write + + + REQ_1 + no description available + 0 + + + REQ_2 + no description available + 0x1 + + + REQ_4 + no description available + 0x2 + + + REQ_8 + no description available + 0x3 + + + REQ_16 + no description available + 0x4 + + + + + + + TRANSFER_COUNT + eLCDIF Horizontal and Vertical Valid Data Count Register + 0x30 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + H_COUNT + Total valid data (pixels) in each horizontal line + 0 + 16 + read-write + + + V_COUNT + Number of horizontal lines per frame which contain valid data + 0x10 + 16 + read-write + + + + + CUR_BUF + LCD Interface Current Buffer Address Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the current frame being transmitted by eLCDIF. + 0 + 32 + read-write + + + + + NEXT_BUF + LCD Interface Next Buffer Address Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the next frame that will be transmitted by eLCDIF. + 0 + 32 + read-write + + + + + TIMING + LCD Interface Timing Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_SETUP + Data bus setup time in DISPLAY CLOCK (pix_clk) cycles + 0 + 8 + read-write + + + DATA_HOLD + Data bus hold time in DISPLAY CLOCK (pix_clk) cycles + 0x8 + 8 + read-write + + + CMD_SETUP + Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active before LCD_CS is asserted + 0x10 + 8 + read-write + + + CMD_HOLD + Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active after LCD_CS is deasserted + 0x18 + 8 + read-write + + + + + VDCTRL0 + eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 0x12 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 0x13 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 0x14 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 0x15 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 0x18 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 0x19 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 0x1A + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1B + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 0x1C + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 0x1D + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the eLCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL0_SET + eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 0x12 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 0x13 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 0x14 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 0x15 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 0x18 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 0x19 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 0x1A + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1B + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 0x1C + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 0x1D + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the eLCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL0_CLR + eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 0x12 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 0x13 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 0x14 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 0x15 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 0x18 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 0x19 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 0x1A + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1B + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 0x1C + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 0x1D + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the eLCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL0_TOG + eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 0x12 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 0x13 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 0x14 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 0x15 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 0x18 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 0x19 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 0x1A + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1B + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 0x1C + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 0x1D + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the eLCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL1 + eLCDIF VSYNC Mode and Dotclk Mode Control Register1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PERIOD + Total number of units between two positive or two negative edges of the VSYNC signal + 0 + 32 + read-write + + + + + VDCTRL2 + LCDIF VSYNC Mode and Dotclk Mode Control Register2 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + HSYNC_PERIOD + Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal + 0 + 18 + read-write + + + HSYNC_PULSE_WIDTH + Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active. + 0x12 + 14 + read-write + + + + + VDCTRL3 + eLCDIF VSYNC Mode and Dotclk Mode Control Register3 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + VERTICAL_WAIT_CNT + In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set + 0 + 16 + read-write + + + HORIZONTAL_WAIT_CNT + In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins + 0x10 + 12 + read-write + + + VSYNC_ONLY + This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation. + 0x1C + 1 + read-write + + + MUX_SYNC_SIGNALS + When this bit is set, the eLCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins + 0x1D + 1 + read-write + + + + + VDCTRL4 + eLCDIF VSYNC Mode and Dotclk Mode Control Register4 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOTCLK_H_VALID_DATA_CNT + Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode + 0 + 18 + read-write + + + SYNC_SIGNALS_ON + Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end + 0x12 + 1 + read-write + + + DOTCLK_DLY_SEL + This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin + 0x1D + 3 + read-write + + + + + DVICTRL0 + Digital Video Interface Control0 Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_BLANKING_CNT + Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval. + 0 + 12 + read-write + + + H_ACTIVE_CNT + Number of active video samples to be transmitted + 0x10 + 12 + read-write + + + + + DVICTRL1 + Digital Video Interface Control1 Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + F2_START_LINE + Vertical line number from which Field 2 begins. + 0 + 10 + read-write + + + F1_END_LINE + Vertical line number at which Field1 ends. + 0xA + 10 + read-write + + + F1_START_LINE + Vertical line number from which Field 1 begins. + 0x14 + 10 + read-write + + + + + DVICTRL2 + Digital Video Interface Control2 Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + V1_BLANK_END_LINE + Vertical line number in the beginning part of Field2 where first Vertical Blanking interval ends. + 0 + 10 + read-write + + + V1_BLANK_START_LINE + Vertical line number towards the end of Field1 where first Vertical Blanking interval starts. + 0xA + 10 + read-write + + + F2_END_LINE + Vertical line number at which Field 2 ends. + 0x14 + 10 + read-write + + + + + DVICTRL3 + Digital Video Interface Control3 Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + V_LINES_CNT + Total number of vertical lines per frame (generally 525 or 625) + 0 + 10 + read-write + + + V2_BLANK_END_LINE + Vertical line number in the beginning part of Field1 where second Vertical Blanking interval ends. + 0xA + 10 + read-write + + + V2_BLANK_START_LINE + Vertical line number towards the end of Field2 where second Vertical Blanking interval starts. + 0x14 + 10 + read-write + + + + + DVICTRL4 + Digital Video Interface Control4 Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_FILL_CNT + Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval + 0 + 8 + read-write + + + CR_FILL_VALUE + Value of CR component of filler data. + 0x8 + 8 + read-write + + + CB_FILL_VALUE + Value of CB component of filler data + 0x10 + 8 + read-write + + + Y_FILL_VALUE + Value of Y component of filler data + 0x18 + 8 + read-write + + + + + CSC_COEFF0 + RGB to YCbCr 4:2:2 CSC Coefficient0 Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSC_SUBSAMPLE_FILTER + This register describes the filtering and subsampling scheme to be performed on the chroma components in order to convert from YCbCr 4:4:4 to YCbCr 4:2:2 space + 0 + 2 + read-write + + + SAMPLE_AND_HOLD + No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1. + 0 + + + INTERSTITIAL + Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples. + 0x2 + + + COSITED + Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4) and that chroma value exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded. + 0x3 + + + + + C0 + Two's complement red multiplier coefficient for Y + 0x10 + 10 + read-write + + + + + CSC_COEFF1 + RGB to YCbCr 4:2:2 CSC Coefficient1 Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + C1 + Two's complement green multiplier coefficient for Y + 0 + 10 + read-write + + + C2 + Two's complement blue multiplier coefficient for Y + 0x10 + 10 + read-write + + + + + CSC_COEFF2 + RGB to YCbCr 4:2:2 CSC Coefficent2 Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + C3 + Two's complement red multiplier coefficient for Cb + 0 + 10 + read-write + + + C4 + Two's complement green multiplier coefficient for Cb + 0x10 + 10 + read-write + + + + + CSC_COEFF3 + RGB to YCbCr 4:2:2 CSC Coefficient3 Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + C5 + Two's complement blue multiplier coefficient for Cb + 0 + 10 + read-write + + + C6 + Two's complement red multiplier coefficient for Cr + 0x10 + 10 + read-write + + + + + CSC_COEFF4 + RGB to YCbCr 4:2:2 CSC Coefficient4 Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + C7 + Two's complement green multiplier coefficient for Cr + 0 + 10 + read-write + + + C8 + Two's complement blue multiplier coefficient for Cr + 0x10 + 10 + read-write + + + + + CSC_OFFSET + RGB to YCbCr 4:2:2 CSC Offset Register + 0x160 + 32 + read-write + 0x800010 + 0xFFFFFFFF + + + Y_OFFSET + Two's complement offset for the Y component + 0 + 9 + read-write + + + CBCR_OFFSET + Two's complement offset for the Cb and Cr components + 0x10 + 9 + read-write + + + + + CSC_LIMIT + RGB to YCbCr 4:2:2 CSC Limit Register + 0x170 + 32 + read-write + 0xFF00FF + 0xFFFFFFFF + + + Y_MAX + Upper limit of Y after RGB to 4:2:2 YCbCr conversion + 0 + 8 + read-write + + + Y_MIN + Lower limit of Y after RGB to 4:2:2 YCbCr conversion + 0x8 + 8 + read-write + + + CBCR_MAX + Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion + 0x10 + 8 + read-write + + + CBCR_MIN + Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion + 0x18 + 8 + read-write + + + + + DATA + LCD Interface Data Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_ZERO + Byte 0 (least significant byte) of data written to eLCDIF. + 0 + 8 + read-write + + + DATA_ONE + Byte 1 of data written to eLCDIF. + 0x8 + 8 + read-write + + + DATA_TWO + Byte 2 of data written to eLCDIF. + 0x10 + 8 + read-write + + + DATA_THREE + Byte 3 (most significant byte) of data written to LCDIF. + 0x18 + 8 + read-write + + + + + BM_ERROR_STAT + Bus Master Error Status Register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Virtual address at which bus master error occurred. + 0 + 32 + read-write + + + + + CRC_STAT + CRC Status Register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_VALUE + Calculated CRC value. + 0 + 32 + read-write + + + + + STAT + LCD Interface Status Register + 0x1B0 + 32 + read-only + 0x95000000 + 0xFFFFFFFF + + + LFIFO_COUNT + Read only view of the current count in Latency buffer (LFIFO). + 0 + 9 + read-only + + + DVI_CURRENT_FIELD + Read only view of the current field being transmitted + 0x18 + 1 + read-only + + + BUSY + Read only view of the input busy signal from the external LCD controller. + 0x19 + 1 + read-only + + + TXFIFO_EMPTY + Read only view of the signal that indicates that LCD write dapatath FIFO is empty, will be generally used in the read mode of the LCD interface + 0x1A + 1 + read-only + + + TXFIFO_FULL + Read only view of the signal that indicates that LCD write datapath FIFO is full, will be generally used in the write mode of the LCD interface + 0x1B + 1 + read-only + + + LFIFO_EMPTY + Read only view of the signal that indicates that LCD read dapatath FIFO is empty, will be generally used in the read mode of the LCD interface + 0x1C + 1 + read-only + + + LFIFO_FULL + Read only view of the signal that indicates that LCD read datapath FIFO is full, will be generally used in the write mode of the LCD interface + 0x1D + 1 + read-only + + + PRESENT + 0: eLCDIF not present on this product 1: eLCDIF is present. + 0x1F + 1 + read-only + + + + + THRES + eLCDIF Threshold Register + 0x200 + 32 + read-write + 0x100000F + 0xFFFFFFFF + + + PANIC + This value should be set to a value of pixels from 0 to 511 + 0 + 9 + read-write + + + FASTCLOCK + This value should be set to a value of pixels, from 0 to 511 + 0x10 + 9 + read-write + + + + + AS_CTRL + eLCDIF AS Buffer Control Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + AS_ENABLE + When this bit is set by software, the LCDIF will start fetching AS buffer data in bus master mode and combine it with another buffer + 0 + 1 + read-write + + + ALPHA_CTRL + Determines how the alpha value is constructed for this alpha surface + 0x1 + 2 + read-write + + + ENABLE_COLORKEY + Indicates that colorkey functionality is enabled for this alpha surface + 0x3 + 1 + read-write + + + FORMAT + Indicates the input buffer format for AS + 0x4 + 4 + read-write + + + ALPHA + Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL] + 0x8 + 8 + read-write + + + ROP + Indicates a raster operation to perform when enabled + 0x10 + 4 + read-write + + + ALPHA_INVERT + Setting this bit to logic 0 will not alter the alpha value + 0x14 + 1 + read-write + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF + 0x15 + 2 + read-write + + + PS_DISABLE + When this bit is set by software, the LCDIF will disable PS buffer data. + 0x17 + 1 + read-write + + + RVDS1 + Reserved, always set to zero. + 0x18 + 3 + read-only + + + CSI_SYNC_ON_IRQ + this bit is set by software to decide which vsync generate mode + 0x1B + 1 + read-write + + + CSI_SYNC_ON_IRQ_EN + This bit is set to enable an interrupt when LCDIF lock with CSI vsync input. + 0x1C + 1 + read-write + + + CSI_VSYNC_MODE + this bit is set by software to decide which vsync generate mode + 0x1D + 1 + read-write + + + CSI_VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1E + 1 + read-write + + + CSI_VSYNC_ENABLE + When this bit is set by software, the LCDIF work as sync mode with CSI input. + 0x1F + 1 + read-write + + + + + AS_BUF + Alpha Surface Buffer Pointer + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the alpha surface 0 buffer. + 0 + 32 + read-write + + + + + AS_NEXT_BUF + no description available + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the next frame that will be transmitted by eLCDIF. + 0 + 32 + read-write + + + + + AS_CLRKEYLOW + eLCDIF Overlay Color Key Low + 0x240 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of RGB color key applied to AS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-write + + + + + AS_CLRKEYHIGH + eLCDIF Overlay Color Key High + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of RGB color key applied to AS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-write + + + + + SYNC_DELAY + LCD working insync mode with CSI for VSYNC delay + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_COUNT_DELAY + LCDIF VSYNC delayed counter for CSI_VSYNC. + 0 + 16 + read-write + + + V_COUNT_DELAY + LCDIF VSYNC delayed counter for CSI_VSYNC. + 0x10 + 16 + read-write + + + + + + + PXP + PXP v3.0 Register Reference Index + PXP + PXP_ + 0x21CC000 + + 0 + 0x2D44 + registers + + + PXP_IRQ0 + 40 + + + PXP_IRQ1 + 50 + + + + HW_CTRL + Control Register 0 + 0 + 32 + read-write + 0xC7008000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + IRQ_ENABLE + Interrupt enable + 0x1 + 1 + read-write + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 0x2 + 1 + read-write + + + LUT_DMA_IRQ_ENABLE + LUT DMA interrupt enable + 0x3 + 1 + read-write + + + ENABLE_LCD0_HANDSHAKE + Enable handshake with LCD0 controller + 0x4 + 1 + read-write + + + HANDSHAKE_ABORT_SKIP + When skip is enable, even the abort asserted, pxp will not assert the ready directly but wait for whole block line complete + 0x5 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + ROTATE0 + Indicates the clockwise rotation to be applied at the output buffer + 0x8 + 2 + read-write + + + ROT_0 + no description available + 0 + + + ROT_90 + no description available + 0x1 + + + ROT_180 + no description available + 0x2 + + + ROT_270 + no description available + 0x3 + + + + + HFLIP0 + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 0xA + 1 + read-write + + + VFLIP0 + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 0xB + 1 + read-write + + + ROTATE1 + Indicates the clockwise rotation to be applied at the input buffer + 0xC + 2 + read-write + + + ROT_0 + no description available + 0 + + + ROT_90 + no description available + 0x1 + + + ROT_180 + no description available + 0x2 + + + ROT_270 + no description available + 0x3 + + + + + HFLIP1 + Indicates that the input should be flipped horizontally (effect applied before rotation). + 0xE + 1 + read-write + + + VFLIP1 + Indicates that the input should be flipped vertically (effect applied before rotation). + 0xF + 1 + read-write + + + ENABLE_PS_AS_OUT + Enable the PS engine, AS engine, OUTBUF in the PXP primary processing flow. + 0x10 + 1 + read-write + + + ENABLE_DITHER + Enable the Dithering engine in the PXP primary processing flow. + 0x11 + 1 + read-write + + + ENABLE_WFE_A + Enable the WFE-A engine in the PXP primary processing flow. + 0x12 + 1 + read-write + + + ENABLE_WFE_B + Enable the WFE-B engine in the PXP primary processing flow. + 0x13 + 1 + read-write + + + ENABLE_INPUT_FETCH_STORE + Enable the Input Fetch and Store engine in the PXP primary processing flow. + 0x14 + 1 + read-write + + + ENABLE_ALPHA_B + Enable the Alpha-B engine in the PXP primary processing flow. + 0x15 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + BLOCK_SIZE + Select the block size to process through the Rotate block. + 0x17 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + ENABLE_CSC2 + Enable the CSC2 engine in the PXP primary processing flow. + 0x18 + 1 + read-write + + + ENABLE_LUT + Enable the LUT engine in the PXP primary processing flow. + 0x19 + 1 + read-write + + + ENABLE_ROTATE0 + Enable the ROTATE0 engine in the PXP primary processing flow. + 0x1A + 1 + read-write + + + ENABLE_ROTATE1 + Enable the ROTATE1 engine in the PXP primary processing flow. + 0x1B + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x1C + 1 + read-only + + + RSVD4 + Reserved, always set to zero. + 0x1D + 1 + read-only + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal PXP operation + 0x1F + 1 + read-write + + + + + HW_STAT + Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ0 + Indicates current PXP interrupt status + 0 + 1 + read-write + + + AXI_WRITE_ERROR_0 + Indicates PXP encountered an AXI write error and processing has been terminated. + 0x1 + 1 + read-write + + + AXI_READ_ERROR_0 + Indicates PXP encountered an AXI read error and processing has been terminated. + 0x2 + 1 + read-write + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 0x3 + 1 + read-write + + + AXI_ERROR_ID_0 + Indicates the AXI0 ID of the failing bus operation. + 0x4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 0x8 + 1 + read-write + + + AXI_WRITE_ERROR_1 + Indicates PXP encountered an AXI write error and processing has been terminated. + 0x9 + 1 + read-write + + + AXI_READ_ERROR_1 + Indicates PXP encountered an AXI read error and processing has been terminated. + 0xA + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xB + 1 + read-only + + + AXI_ERROR_ID_1 + Indicates the AXI1 ID of the failing bus operation. + 0xC + 4 + read-only + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 0x10 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 0x18 + 8 + read-only + + + + + HW_OUT_CTRL + Output Buffer Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + RSVD0 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 0x8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0xA + 13 + read-only + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by REG_OUT_CTRL[ALPHA] register + 0x17 + 1 + read-write + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 0x18 + 8 + read-write + + + + + HW_OUT_BUF + Output Frame Buffer Pointer + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer + 0 + 32 + read-write + + + + + HW_OUT_BUF2 + Output Frame Buffer Pointer #2 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer + 0 + 32 + read-write + + + + + HW_OUT_PITCH + Output Buffer Pitch + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + RSVD + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_OUT_LRC + Output Surface Lower Right Coordinate + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + Indicates the number of vertical PIXELS in the output surface (non-rotated) + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + Indicates number of horizontal PIXELS in the output surface (non-rotated) + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_OUT_PS_ULC + Processed Surface Upper Left Coordinate + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + This field indicates the upper left X-coordinate (in pixels) of the processed surface (PS) in the output buffer + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_OUT_PS_LRC + Processed Surface Lower Right Coordinate + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + This field indicates the lower right X-coordinate (in pixels) of the processed surface (PS) in the output frame buffer + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_OUT_AS_ULC + Alpha Surface Upper Left Coordinate + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the alpha surface in the output frame buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + This field indicates the upper left X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_OUT_AS_LRC + Alpha Surface Lower Right Coordinate + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the alpha surface in the output frame buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + This field indicates the lower right X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_PS_CTRL + Processed Surface (PS) Control Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 6 + read-write + + + RGB888 + 32-bit pixels (unpacked 24-bit format) + 0x4 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 0x6 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + DECY + Verticle pre decimation filter control. + 0x8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 0xA + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0xC + 20 + read-only + + + + + HW_PS_BUF + PS Input Buffer Address + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS RGB or Y (luma) input buffer. + 0 + 32 + read-write + + + + + HW_PS_UBUF + PS U/Cb or 2 Plane UV Input Buffer Address + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS U/Cb or 2 plane UV Chroma input buffer. + 0 + 32 + read-write + + + + + HW_PS_VBUF + PS V/Cr Input Buffer Address + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS V/Cr Chroma input buffer. + 0 + 32 + read-write + + + + + HW_PS_PITCH + Processed Surface Pitch + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + RSVD + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_PS_BACKGROUND_0 + PS Background Color + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + COLOR + Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC + 0 + 24 + read-write + + + RSVD + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_PS_SCALE + PS Scale Factor Register + 0x110 + 32 + read-write + 0x10001000 + 0xFFFFFFFF + + + XSCALE + This is a two bit integer and 12 bit fractional representation (## + 0 + 15 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xF + 1 + read-only + + + YSCALE + This is a two bit integer and 12 bit fractional representation (## + 0x10 + 15 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_PS_OFFSET + PS Scale Offset Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + XOFFSET + This is a 12 bit fractional representation (0 + 0 + 12 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xC + 4 + read-only + + + YOFFSET + This is a 12 bit fractional representation (0 + 0x10 + 12 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x1C + 4 + read-only + + + + + HW_PS_CLRKEYLOW_0 + PS Color Key Low + 0x130 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_PS_CLRKEYHIGH_0 + PS Color Key High + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_AS_CTRL + Alpha Surface Control + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved, always set to zero. + 0 + 1 + read-only + + + ALPHA_CTRL + Determines how the alpha value is constructed for this alpha surface + 0x1 + 2 + read-write + + + Embedded + Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. + 0 + + + Override + Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. + 0x1 + + + Multiply + Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. + 0x2 + + + ROPs + Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels. + 0x3 + + + + + ENABLE_COLORKEY + Indicates that colorkey functionality is enabled for this alpha surface + 0x3 + 1 + read-write + + + FORMAT + Indicates the input buffer format for AS. + 0x4 + 4 + read-write + + + ARGB8888 + 32-bit pixels with alpha + 0 + + + RGBA8888 + 32-bit pixels with alpha + 0x1 + + + RGB888 + 32-bit pixels without alpha (unpacked 24-bit format) + 0x4 + + + ARGB1555 + 16-bit pixels with alpha + 0x8 + + + ARGB4444 + 16-bit pixels with alpha + 0x9 + + + RGB555 + 16-bit pixels without alpha + 0xC + + + RGB444 + 16-bit pixels without alpha + 0xD + + + RGB565 + 16-bit pixels without alpha + 0xE + + + + + ALPHA + Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL] + 0x8 + 8 + read-write + + + ROP + Indicates a raster operation to perform when enabled + 0x10 + 4 + read-write + + + MASKAS + AS AND PS + 0 + + + MASKNOTAS + nAS AND PS + 0x1 + + + MASKASNOT + AS AND nPS + 0x2 + + + MERGEAS + AS OR PS + 0x3 + + + MERGENOTAS + nAS OR PS + 0x4 + + + MERGEASNOT + AS OR nPS + 0x5 + + + NOTCOPYAS + nAS + 0x6 + + + NOT + nPS + 0x7 + + + NOTMASKAS + AS NAND PS + 0x8 + + + NOTMERGEAS + AS NOR PS + 0x9 + + + XORAS + AS XOR PS + 0xA + + + NOTXORAS + AS XNOR PS + 0xB + + + + + ALPHA0_INVERT + Setting this bit to logic 0 will not alter the alpha0 value + 0x14 + 1 + read-write + + + ALPHA1_INVERT + Setting this bit to logic 0 will not alter the alpha1 value + 0x15 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 10 + read-only + + + + + HW_AS_BUF + Alpha Surface Buffer Pointer + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the alpha surface 0 buffer. + 0 + 32 + read-write + + + + + HW_AS_PITCH + Alpha Surface Pitch + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + RSVD + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_AS_CLRKEYLOW_0 + Overlay Color Key Low + 0x180 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_AS_CLRKEYHIGH_0 + Overlay Color Key High + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_CSC1_COEF0 + Color Space Conversion Coefficient Register 0 + 0x1A0 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data + 0 + 9 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data + 0x9 + 9 + read-write + + + C0 + Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 0x12 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1D + 1 + read-only + + + BYPASS + Bypass the CSC unit in the scaling engine + 0x1E + 1 + read-write + + + YCBCR_MODE + Set to 1 when performing YCbCr conversion to RGB + 0x1F + 1 + read-write + + + + + HW_CSC1_COEF1 + Color Space Conversion Coefficient Register 1 + 0x1B0 + 32 + read-write + 0x1230208 + 0xFFFFFFFF + + + C4 + Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + C1 + Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC1_COEF2 + Color Space Conversion Coefficient Register 2 + 0x1C0 + 32 + read-write + 0x79B076C + 0xFFFFFFFF + + + C3 + Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + C2 + Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_CTRL + Color Space Conversion Control Register. + 0x1D0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + BYPASS + This bit controls whether the pixels entering the CSC2 unit get converted or not + 0 + 1 + read-write + + + CSC_MODE + This field controls how the CSC unit operates on pixels when the CSC is not bypassed. + 0x1 + 2 + read-write + + + YUV2RGB + Convert from YUV to RGB. + 0 + + + YCbCr2RGB + Convert from YCbCr to RGB. + 0x1 + + + RGB2YUV + Convert from RGB to YUV. + 0x2 + + + RGB2YCbCr + Convert from RGB to YCbCr. + 0x3 + + + + + RSVD + Reserved, always set to zero. + 0x3 + 29 + read-only + + + + + HW_CSC2_COEF0 + Color Space Conversion Coefficient Register 0 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + A1 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + A2 + Two's compliment coefficient offset + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_COEF1 + Color Space Conversion Coefficient Register 1 + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + A3 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + B1 + Two's compliment coefficient offset + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_COEF2 + Color Space Conversion Coefficient Register 2 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + B2 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + B3 + Two's compliment coefficient offset + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_COEF3 + Color Space Conversion Coefficient Register 3 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + C1 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + C2 + Two's compliment coefficient offset + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_COEF4 + Color Space Conversion Coefficient Register 4 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + C3 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + D1 + Two's compliment coefficient integer offset to be added. + 0x10 + 9 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x19 + 7 + read-only + + + + + HW_CSC2_COEF5 + Color Space Conversion Coefficient Register 5 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + D2 + Two's compliment D1 coefficient integer offset to be added. + 0 + 9 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x9 + 7 + read-only + + + D3 + Two's compliment coefficient integer offset to be added. + 0x10 + 9 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x19 + 7 + read-only + + + + + HW_LUT_CTRL + Lookup Table Control Register. + 0x240 + 32 + read-write + 0x80010000 + 0xFFFFFFFF + + + DMA_START + Setting this bit will result in the DMA operation to load the PXP LUT memory based on REG_LUT_ADDR_NUM_BYTES, REG_LUT_ADDR_ADDR, and REG_LUT_MEM_ADDR + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 7 + read-only + + + INVALID + Invalidate the cache LRU and valid bits. This bit will automatically reset when set to a logic 1. + 0x8 + 1 + read-write + + + LRU_UPD + Least Recently Used Policy Update Control: 1=> block LRU update for hit after miss + 0x9 + 1 + read-write + + + SEL_8KB + Selects which 8KB bank of memory to use for direct 12bpp lookup modes + 0xA + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xB + 5 + read-only + + + OUT_MODE + Select the output mode of operation for the LUT resource + 0x10 + 2 + read-write + + + Y8 + R/Y byte lane 2 lookup, bytes 1,0 bypassed. + 0x1 + + + RGBW4444CFA + Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444. + 0x2 + + + RGB888 + RGB565->RGB888 conversion for Gamma correction. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + LOOKUP_MODE + Configure the input address for the 16KB LUT memory + 0x18 + 2 + read-write + + + CACHE_RGB565 + LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT for indirect cached 128KB lookup. + 0 + + + DIRECT_Y8 + LUT ADDR = 16'b0,Y[7:0]. Use only the first 256 bytes of LUT. Only the Y, or third data path byte, is tranformed. + 0x1 + + + DIRECT_RGB444 + LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT selected by SEL_8KB. + 0x2 + + + DIRECT_RGB454 + LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT. + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x1A + 5 + read-only + + + BYPASS + Setting this bit will bypass the LUT memory resource completely + 0x1F + 1 + read-write + + + + + HW_LUT_ADDR + Lookup Table Control Register. + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + LUT indexed address pointer + 0 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + NUM_BYTES + Indicates the number of bytes to load via a DMA operation + 0x10 + 15 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_LUT_DATA + Lookup Table Data Register. + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register + 0 + 32 + read-write + + + + + HW_LUT_EXTMEM + Lookup Table External Memory Address Register. + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + This register contains the external memory address used for LUT memory operation. + 0 + 32 + read-write + + + + + HW_CFA + Color Filter Array Register. + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + This register contains the Color Filter Array pattern for decimation of RGBW4444 16 bit pixels to individual R, G, B, W values + 0 + 32 + read-write + + + + + HW_ALPHA_A_CTRL + PXP Alpha Engine A Control Register. + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + POTER_DUFF_ENABLE + poter_duff enable + 0 + 1 + read-write + + + 0 + porter duff disable. + 0 + + + 1 + porter duff enable. + 0x1 + + + + + S0_S1_FACTOR_MODE + s0 to s1 factor mode + 0x1 + 2 + read-write + + + 0 + using 1. + 0 + + + 1 + using 0. + 0x1 + + + 2 + using straight alpha. + 0x2 + + + 3 + using inverse alpha. + 0x3 + + + + + S0_GLOBAL_ALPHA_MODE + s0 global alpha mode + 0x3 + 2 + read-write + + + 0 + using global alpha. + 0 + + + 1 + using local alpha. + 0x1 + + + 2 + using scaled alpha. + 0x2 + + + 3 + using scaled alpha. + 0x3 + + + + + S0_ALPHA_MODE + s0 alpha mode + 0x5 + 1 + read-write + + + 0 + straight mode for s0 alpha + 0 + + + 1 + inversed mode for s0 alpha + 0x1 + + + + + S0_COLOR_MODE + s0 color mode + 0x6 + 1 + read-write + + + 0 + straight mode for s0 color + 0 + + + 1 + multiply mode for s0 color + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + S1_S0_FACTOR_MODE + s1 to s0 factor mode + 0x8 + 2 + read-write + + + 0 + using 1. + 0 + + + 1 + using 0. + 0x1 + + + 2 + using straight alpha. + 0x2 + + + 3 + using inverse alpha. + 0x3 + + + + + S1_GLOBAL_ALPHA_MODE + s1 global alpha mode + 0xA + 2 + read-write + + + 0 + using global alpha. + 0 + + + + + S1_ALPHA_MODE + s1 alpha mode + 0xC + 1 + read-write + + + 0 + straight mode for s1 alpha + 0 + + + 1 + inversed mode for s1 alpha + 0x1 + + + + + S1_COLOR_MODE + s1 color mode + 0xD + 1 + read-write + + + 0 + straight mode for s1 color + 0 + + + 1 + multiply mode for s1 color + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + S0_GLOBAL_ALPHA + s0 global alpha + 0x10 + 8 + read-write + + + S1_GLOBAL_ALPHA + s1 global alpha + 0x18 + 8 + read-write + + + + + HW_ALPHA_B_CTRL + PXP Alpha Engine B Control Register. + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POTER_DUFF_ENABLE + poter_duff enable + 0 + 1 + read-write + + + 0 + porter duff disable. + 0 + + + 1 + porter duff enable. + 0x1 + + + + + S0_S1_FACTOR_MODE + s0 to s1 factor mode + 0x1 + 2 + read-write + + + 0 + using 1. + 0 + + + 1 + using 0. + 0x1 + + + 2 + using straight alpha. + 0x2 + + + 3 + using inverse alpha. + 0x3 + + + + + S0_GLOBAL_ALPHA_MODE + s0 global alpha mode + 0x3 + 2 + read-write + + + 0 + using global alpha. + 0 + + + 1 + using local alpha. + 0x1 + + + 2 + using scaled alpha. + 0x2 + + + 3 + using scaled alpha. + 0x3 + + + + + S0_ALPHA_MODE + s0 alpha mode + 0x5 + 1 + read-write + + + 0 + straight mode for s0 alpha + 0 + + + 1 + inversed mode for s0 alpha + 0x1 + + + + + S0_COLOR_MODE + s0 color mode + 0x6 + 1 + read-write + + + 0 + straight mode for s0 color + 0 + + + 1 + multiply mode for s0 color + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + S1_S0_FACTOR_MODE + s1 to s0 factor mode + 0x8 + 2 + read-write + + + 0 + using 1. + 0 + + + 1 + using 0. + 0x1 + + + 2 + using straight alpha. + 0x2 + + + 3 + using inverse alpha. + 0x3 + + + + + S1_GLOBAL_ALPHA_MODE + s1 global alpha mode + 0xA + 2 + read-write + + + 0 + using global alpha. + 0 + + + 1 + using local alpha. + 0x1 + + + 2 + using scaled alpha. + 0x2 + + + 3 + using scaled alpha. + 0x3 + + + + + S1_ALPHA_MODE + s1 alpha mode + 0xC + 1 + read-write + + + 0 + straight mode for s1 alpha + 0 + + + 1 + inversed mode for s1 alpha + 0x1 + + + + + S1_COLOR_MODE + s1 color mode + 0xD + 1 + read-write + + + 0 + straight mode for s1 color + 0 + + + 1 + multiply mode for s1 color + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + S0_GLOBAL_ALPHA + s0 global alpha + 0x10 + 8 + read-write + + + S1_GLOBAL_ALPHA + s1 global alpha + 0x18 + 8 + read-write + + + + + HW_ALPHA_B_CTRL_1 + no description available + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROP_ENABLE + ROP ENABLE + 0 + 1 + read-write + + + OL_CLRKEY_ENABLE + Indicates that colorkey functionality is enabled for this alpha surface + 0x1 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x2 + 2 + read-only + + + ROP + Indicates a raster operation to perform when enabled. + 0x4 + 4 + read-write + + + MASKAS + AS AND PS + 0 + + + MASKNOTAS + nAS AND PS + 0x1 + + + MASKASNOT + AS AND nPS + 0x2 + + + MERGEAS + AS OR PS + 0x3 + + + MERGENOTAS + nAS OR PS + 0x4 + + + MERGEASNOT + AS OR nPS + 0x5 + + + NOTCOPYAS + nAS + 0x6 + + + NOT + nPS + 0x7 + + + NOTMASKAS + AS NAND PS + 0x8 + + + NOTMERGEAS + AS NOR PS + 0x9 + + + XORAS + AS XOR PS + 0xA + + + NOTXORAS + AS XNOR PS + 0xB + + + + + RSVD0 + Reserved, always set to zero. + 0x8 + 24 + read-only + + + + + HW_PS_BACKGROUND_1 + PS Background Color 1 + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + COLOR + Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC + 0 + 24 + read-write + + + RSVD + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_PS_CLRKEYLOW_1 + PS Color Key Low 1 + 0x2D0 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_PS_CLRKEYHIGH_1 + PS Color Key High 1 + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_AS_CLRKEYLOW_1 + Overlay Color Key Low + 0x2F0 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_AS_CLRKEYHIGH_1 + Overlay Color Key High + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_CTRL2 + Control Register 2 + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enables PXP secondary data processing flow with specified parameters + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 7 + read-only + + + ROTATE0 + Indicates the clockwise rotation to be applied at the output buffer + 0x8 + 2 + read-write + + + ROT_0 + no description available + 0 + + + ROT_90 + no description available + 0x1 + + + ROT_180 + no description available + 0x2 + + + ROT_270 + no description available + 0x3 + + + + + HFLIP0 + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 0xA + 1 + read-write + + + VFLIP0 + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 0xB + 1 + read-write + + + ROTATE1 + Indicates the clockwise rotation to be applied at the input buffer + 0xC + 2 + read-write + + + ROT_0 + no description available + 0 + + + ROT_90 + no description available + 0x1 + + + ROT_180 + no description available + 0x2 + + + ROT_270 + no description available + 0x3 + + + + + HFLIP1 + Indicates that the input should be flipped horizontally (effect applied before rotation). + 0xE + 1 + read-write + + + VFLIP1 + Indicates that the input should be flipped vertically (effect applied before rotation). + 0xF + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x10 + 1 + read-only + + + ENABLE_DITHER + Enable the Dithering engine in the PXP secondary processing flow. + 0x11 + 1 + read-write + + + ENABLE_WFE_A + Enable the WFE-A engine in the PXP secondary processing flow. + 0x12 + 1 + read-write + + + ENABLE_WFE_B + Enable the WFE-B engine in the PXP secondary processing flow. + 0x13 + 1 + read-write + + + ENABLE_INPUT_FETCH_STORE + Enable the Input Fetch and Store engine in the PXP secondary processing flow. + 0x14 + 1 + read-write + + + ENABLE_ALPHA_B + Enable the Alpha-B engine in the PXP secondary processing flow. + 0x15 + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + BLOCK_SIZE + Select the block size to process through the Rotate block. + 0x17 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + ENABLE_CSC2 + Enable the CSC2 engine in the PXP secondary processing flow. + 0x18 + 1 + read-write + + + ENABLE_LUT + Enable the LUT engine in the PXP secondary processing flow. + 0x19 + 1 + read-write + + + ENABLE_ROTATE0 + Enable the ROTATE0 engine in the PXP secondary processing flow. + 0x1A + 1 + read-write + + + ENABLE_ROTATE1 + Enable the ROTATE1 engine in the PXP secondary processing flow. + 0x1B + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1C + 4 + read-only + + + + + HW_POWER_REG0 + PXP Power Control Register. + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUT_LP_STATE_WAY0_BANK0 + Select the low power state of the LUT's WAY0-BANK0 memory. + 0 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + LUT_LP_STATE_WAY0_BANKN + Select the low power state of the LUT's WAY0-BANK1,2,3 memory. + 0x3 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + LUT_LP_STATE_WAY1_BANKN + Select the low power state of the LUT's WAY0-BANK0,1,2,3 memory. + 0x6 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + ROT0_MEM_LP_STATE + Select the low power state of the ROT 0 memory. + 0x9 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + CTRL + This register contains power control for the PXP. + 0xC + 20 + read-write + + + + + HW_POWER_REG1 + PXP Power Control Register 1. + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROT1_MEM_LP_STATE + Select the low power state of the ROT 1 memory. + 0 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH0_LUT_MEM_LP_STATE + Select the low power state of the dither0 LUT memory. + 0x3 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH0_ERR0_MEM_LP_STATE + Select the low power state of the dither0 ERR0 memory. + 0x6 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH0_ERR1_MEM_LP_STATE + Select the low power state of the dither0 ERR1 memory. + 0x9 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH1_LUT_MEM_LP_STATE + Select the low power state of the dither1 LUT memory. + 0xC + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH2_LUT_MEM_LP_STATE + Select the low power state of the dither2 LUT memory. + 0xF + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + ALU_A_MEM_LP_STATE + Select the low power state of the ALU A memory. + 0x12 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + ALU_B_MEM_LP_STATE + Select the low power state of the ALU B memory. + 0x15 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + RSVD0 + This register contains power control for the PXP. + 0x18 + 8 + read-only + + + + + HW_DATA_PATH_CTRL1 + no description available + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX16_SEL + This mux chooses the data path through MUX 16. + 0 + 2 + read-write + + + 0 + Output of ALU A Engine + 0 + + + 1 + histogram_pixel output from output + 0x1 + + + 2 + Output of ALU B Engine + 0x2 + + + 3 + No output + 0x3 + + + + + MUX17_SEL + This field chooses the data path through MUX 17. + 0x2 + 2 + read-write + + + 0 + Output of ALU A + 0 + + + 1 + Output of ALU B + 0x1 + + + 2 + No output + 0x2 + + + 3 + No Output + 0x3 + + + + + RSVD0 + Reserved. This field always reads 0. + 0x4 + 28 + read-only + + + + + HW_INIT_MEM_CTRL + Initialize memory buffer control Register + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Base address to start writing + 0 + 16 + read-write + + + RSVD0 + Reserved. + 0x10 + 11 + read-only + + + SELECT + Select which memory to write. + 0x1B + 4 + read-write + + + DITHER0_LUT + Select the LUT memory for access + 0 + + + DITHER0_ERR0 + Select the ERR0 memory for access + 0x1 + + + DITHER0_ERR1 + Select the ERR1 memory for access + 0x2 + + + DITHER1_LUT + Select the LUT memory for access + 0x3 + + + DITHER2_LUT + Select the LUT memory for access + 0x4 + + + ALU_A + Select the ALU instr memory for access + 0x5 + + + ALU_B + Select the ALU instr memory for access + 0x6 + + + WFE_A_FETCH + Select the WFE-A fetch memory for access + 0x7 + + + WFE_B_FETCH + Select the WFE-B fetch memory for access + 0x8 + + + + + START + Enable writing to the memory. + 0x1F + 1 + read-write + + + + + HW_INIT_MEM_DATA + Write data Register + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data value to be written to the memory + 0 + 32 + read-write + + + + + HW_INIT_MEM_DATA_HIGH + Write data Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data value to be written to the most significant 32 bits of the fetch memories + 0 + 32 + read-write + + + + + HW_IRQ_MASK + PXP IRQ Mask Register + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIRST_CH0_PREFETCH_IRQ_EN + Enable First ch0 prefetch engine interrupt detection + 0 + 1 + read-write + + + FIRST_CH1_PREFETCH_IRQ_EN + Enable First ch1 prefetch engine interrupt detection + 0x1 + 1 + read-write + + + FIRST_CH0_STORE_IRQ_EN + Enable First ch0 store engine interrupt detection + 0x2 + 1 + read-write + + + FIRST_CH1_STORE_IRQ_EN + Enable First ch1 store engine interrupt detection + 0x3 + 1 + read-write + + + DITHER_CH0_PREFETCH_IRQ_EN + Enable Dither ch0 prefetch engine interrupt detection + 0x4 + 1 + read-write + + + DITHER_CH1_PREFETCH_IRQ_EN + Enable Dither ch1 prefetch engine interrupt detection + 0x5 + 1 + read-write + + + DITHER_CH0_STORE_IRQ_EN + Enable dither ch0 store engine interrupt detection. + 0x6 + 1 + read-write + + + DITHER_CH1_STORE_IRQ_EN + Enable dither ch1 store engine interrupt detection. + 0x7 + 1 + read-write + + + WFE_A_CH0_STORE_IRQ_EN + Enable WFE A ch0 store engine interrupt detection. + 0x8 + 1 + read-write + + + WFE_A_CH1_STORE_IRQ_EN + Enable WFE A ch1 store engine interrupt detection. + 0x9 + 1 + read-write + + + WFE_B_CH0_STORE_IRQ_EN + Enable WFE B ch0 store engine interrupt detection. + 0xA + 1 + read-write + + + WFE_B_CH1_STORE_IRQ_EN + Enable WFE B ch1 store engine interrupt detection. + 0xB + 1 + read-write + + + FIRST_STORE_IRQ_EN + Enable First store engine interrupt detection + 0xC + 1 + read-write + + + DITHER_STORE_IRQ_EN + Enable dither store engine interrupt detection. + 0xD + 1 + read-write + + + WFE_A_STORE_IRQ_EN + Enable WFE A store engine interrupt detection. + 0xE + 1 + read-write + + + WFE_B_STORE_IRQ_EN + Enable WFE B store engine interrupt detection. + 0xF + 1 + read-write + + + RSVD1 + Reserved. + 0x10 + 15 + read-only + + + COMPRESS_DONE_IRQ_EN + Enable compression done interrupt detection. + 0x1F + 1 + read-write + + + + + HW_IRQ + PXP Interrupt Register + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIRST_CH0_PREFETCH_IRQ + Initial ch0 prefetch engine interrupt + 0 + 1 + read-write + + + FIRST_CH1_PREFETCH_IRQ + Initial ch1 prefetch engine interrupt + 0x1 + 1 + read-write + + + FIRST_CH0_STORE_IRQ + Initial ch0 store engine interrupt + 0x2 + 1 + read-write + + + FIRST_CH1_STORE_IRQ + Initial ch1 store engine interrupt + 0x3 + 1 + read-write + + + DITHER_CH0_PREFETCH_IRQ + Dither ch0 prefetch engine interrupt + 0x4 + 1 + read-write + + + DITHER_CH1_PREFETCH_IRQ + Dither ch1 prefetch engine interrupt + 0x5 + 1 + read-write + + + DITHER_CH0_STORE_IRQ + Dither ch0 store engine Interrupt + 0x6 + 1 + read-write + + + DITHER_CH1_STORE_IRQ + Dither ch1 store engine Interrupt + 0x7 + 1 + read-write + + + WFE_A_CH0_STORE_IRQ + WFE A ch0 store engine Interrupt. + 0x8 + 1 + read-write + + + WFE_A_CH1_STORE_IRQ + WFE A ch1 store engine Interrupt. + 0x9 + 1 + read-write + + + WFE_B_CH0_STORE_IRQ + WFE B ch0 store engine Interrupt + 0xA + 1 + read-write + + + WFE_B_CH1_STORE_IRQ + WFE B ch1 store engine Interrupt + 0xB + 1 + read-write + + + FIRST_STORE_IRQ + Initial store engine interrupt + 0xC + 1 + read-write + + + DITHER_STORE_IRQ + Dither store engine Interrupt + 0xD + 1 + read-write + + + WFE_A_STORE_IRQ + WFE A store engine Interrupt. + 0xE + 1 + read-write + + + WFE_B_STORE_IRQ + WFE B store engine Interrupt + 0xF + 1 + read-write + + + RSVD1 + Reserved. + 0x10 + 15 + read-only + + + COMPRESS_DONE_IRQ + compression done Interrupt + 0x1F + 1 + read-write + + + + + HW_NEXT + Next Frame Pointer + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLED + Indicates that the "next frame" functionality has been enabled + 0 + 1 + read-only + + + RSVD + Reserved, always set to zero. + 0x1 + 1 + read-only + + + POINTER + A pointer to a data structure containing register values to be used when processing the next frame + 0x2 + 30 + read-write + + + + + HW_INPUT_FETCH_CTRL_CH0 + Pre-fetch engine Control Channel 0 Register + 0x450 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Prefetch function is disable + 0 + + + 1 + Prefetch function is enable + 0x1 + + + + + BLOCK_EN + Choses the prefetch mode. + 0x1 + 1 + read-write + + + 0 + Prefetch in scan mode + 0 + + + 1 + Prefetch in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the store engine is disabled + 0 + + + 1 + Handshake with the store engine is enabled + 0x1 + + + + + BYPASS_PIXEL_EN + Selects Channel 0 pixel source + 0x4 + 1 + read-write + + + 0 + Channel 0 is from memory + 0 + + + 1 + Channel 0 is from previous process engine + 0x1 + + + + + HIGH_BYTE + channel 0 high byte selection + 0x5 + 1 + read-write + + + 0 + In 64 bit mode, the output high byte will use channel1. + 0 + + + 1 + In 64 bit mode, the output high byte will use channel0 + 0x1 + + + + + RSVD4 + Reserved, always set to zero. + 0x6 + 3 + read-only + + + HFLIP + Enables HFLIP. + 0x9 + 1 + read-write + + + 0 + HFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + VFLIP + Enables VFLIP + 0xA + 1 + read-write + + + 0 + VFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 0xB + 1 + read-only + + + ROTATION_ANGLE + no description available + 0xC + 2 + read-write + + + ROT_0 + Rotate image by 0 degrees. + 0 + + + ROT_90 + Rotate image by 90 degrees. + 0x1 + + + ROT_180 + Rotate image by 180 degrees. + 0x2 + + + ROT_270 + Rotate image by 270 degrees. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RD_NUM_BYTES + Bytes in a read burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes. + 0 + + + 16_bytes + 16 bytes. + 0x1 + + + 32_bytes + 32 bytes. + 0x2 + + + 64_bytes + 64 bytes. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + HANDSHAKE_SCAN_LINE_NUM + scan handshake line number + 0x18 + 2 + read-write + + + 0 + 1 line. + 0 + + + 1 + 8 lines + 0x1 + + + 2 + 16 lines + 0x2 + + + 3 + 16 lines + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x1A + 5 + read-only + + + ARBIT_EN + Enables Arbitration + 0x1F + 1 + read-write + + + 0 + Arbitration disable. If using 2 channels, will output 2 axi bus sets. + 0 + + + 1 + Arbitration enable. If using 2 channel, will only output 1 axi bus sets + 0x1 + + + + + + + HW_INPUT_FETCH_CTRL_CH1 + Pre-fetch engine Control Channel 1 Register + 0x460 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + prefetch function is disable + 0 + + + 1 + prefetch function is enable + 0x1 + + + + + BLOCK_EN + Choses the prefetch mode. + 0x1 + 1 + read-write + + + 0 + Prefetch in scan mode + 0 + + + 1 + Prefetch in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the store engine is disabled + 0 + + + 1 + Handshake with the store engine is enabled + 0x1 + + + + + BYPASS_PIXEL_EN + Selects Channel 1 pixel source + 0x4 + 1 + read-write + + + 0 + Channel 1 is from memory + 0 + + + 1 + Channel 1 is from previous process engine + 0x1 + + + + + RSVD4 + Reserved, always set to zero. + 0x5 + 4 + read-only + + + HFLIP + Enables HFLIP. + 0x9 + 1 + read-write + + + 0 + HFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + VFLIP + Enables VFLIP + 0xA + 1 + read-write + + + 0 + VFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 0xB + 1 + read-only + + + ROTATION_ANGLE + no description available + 0xC + 2 + read-write + + + ROT_0 + Rotate image by 0 degrees. + 0 + + + ROT_90 + Rotate image by 90 degrees. + 0x1 + + + ROT_180 + Rotate image by 180 degrees. + 0x2 + + + ROT_270 + Rotate image by 270 degrees. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RD_NUM_BYTES + Bytes in a read burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes. + 0 + + + 16_bytes + 16 bytes. + 0x1 + + + 32_bytes + 32 bytes. + 0x2 + + + 64_bytes + 64 bytes. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + HANDSHAKE_SCAN_LINE_NUM + scan handshake line number + 0x18 + 2 + read-write + + + 0 + 1 line. + 0 + + + 1 + 8 lines + 0x1 + + + 2 + 16 lines + 0x2 + + + 3 + 16 lines + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x1A + 6 + read-only + + + + + HW_INPUT_FETCH_STATUS_CH0 + Pre-fetch engine status Channel 0 Register + 0x470 + 32 + read-only + 0 + 0xFFFFFFFF + + + PREFETCH_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + PREFETCH_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_INPUT_FETCH_STATUS_CH1 + Store engine status Channel 1 Register + 0x480 + 32 + read-only + 0 + 0xFFFFFFFF + + + PREFETCH_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + PREFETCH_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 + no description available + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_ULC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_ULC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 + no description available + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_LRC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_LRC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 + no description available + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_ULC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_ULC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 + no description available + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_LRC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_LRC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_SIZE_CH0 + no description available + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_TOTAL_WIDTH + actual total width -1 + 0 + 16 + read-write + + + INPUT_TOTAL_HEIGHT + actual total height - 1 + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_SIZE_CH1 + no description available + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_TOTAL_WIDTH + actual total width -1 + 0 + 16 + read-write + + + INPUT_TOTAL_HEIGHT + actual total height -1 + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_BACKGROUND_COLOR_CH0 + no description available + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BACKGROUND_COLOR + background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_BACKGROUND_COLOR_CH1 + no description available + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + BACKGROUND_COLOR + background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_PITCH + no description available + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_INPUT_PITCH + This field indicates the channel 0 input pitch + 0 + 16 + read-write + + + CH1_INPUT_PITCH + This field indicates the channel 1 input pitch + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_SHIFT_CTRL_CH0 + no description available + 0x520 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + INPUT_ACTIVE_BPP + no description available + 0 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x2 + 6 + read-only + + + EXPAND_FORMAT + Select Pixel format + 0x8 + 3 + read-write + + + 0 + RGB 565 + 0 + + + 1 + RGB 555 + 0x1 + + + 2 + ARGB 1555 + 0x2 + + + 3 + RGB 444 + 0x3 + + + 4 + ARGB 4444 + 0x4 + + + 5 + YUYV/YVYU + 0x5 + + + 6 + UYVY/VYUY + 0x6 + + + 7 + YUV422_2P + 0x7 + + + + + EXPAND_EN + no description available + 0xB + 1 + read-write + + + 0 + channel0 format expanding disable + 0 + + + 1 + channel0 format expanding enable + 0x1 + + + + + SHIFT_BYPASS + no description available + 0xC + 1 + read-write + + + 0 + channel0 data will do shift function + 0 + + + 1 + channel0 will bypass shift function + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xD + 19 + read-only + + + + + HW_INPUT_FETCH_SHIFT_CTRL_CH1 + no description available + 0x530 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + INPUT_ACTIVE_BPP + no description available + 0 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x2 + 6 + read-only + + + EXPAND_FORMAT + Select Pixel format + 0x8 + 3 + read-write + + + 0 + RGB 565 + 0 + + + 1 + RGB 555 + 0x1 + + + 2 + ARGB 1555 + 0x2 + + + 3 + RGB 444 + 0x3 + + + 4 + ARGB 4444 + 0x4 + + + 5 + YUYV/YVYU + 0x5 + + + 6 + UYVY/VYUY + 0x6 + + + 7 + YUV422_2P + 0x7 + + + + + EXPAND_EN + no description available + 0xB + 1 + read-write + + + 0 + channel1 format expanding disable + 0 + + + 1 + channel1 format expanding enable + 0x1 + + + + + SHIFT_BYPASS + no description available + 0xC + 1 + read-write + + + 0 + channel1 data will do shift function + 0 + + + 1 + channel1 will bypass shift function + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xD + 19 + read-only + + + + + HW_INPUT_FETCH_SHIFT_OFFSET_CH0 + no description available + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET0 + Shift Offset for channel 0 componnent 0. + 0 + 5 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + OFFSET1 + Shift Offset for channel 0 componnent 1. + 0x8 + 5 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + OFFSET2 + Shift Offset for channel 0 componnent 2. + 0x10 + 5 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x15 + 3 + read-only + + + OFFSET3 + Shift Offset for channel 0 componnent 3. + 0x18 + 5 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1D + 3 + read-only + + + + + HW_INPUT_FETCH_SHIFT_OFFSET_CH1 + no description available + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET0 + Shift Offset for channel 1 componnent 0. + 0 + 5 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + OFFSET1 + Shift Offset for channel 1 componnent 1. + 0x8 + 5 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + OFFSET2 + Shift Offset for channel 1 componnent 2. + 0x10 + 5 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x15 + 3 + read-only + + + OFFSET3 + Shift Offset for channel 1 componnent 3. + 0x18 + 5 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1D + 3 + read-only + + + + + HW_INPUT_FETCH_SHIFT_WIDTH_CH0 + no description available + 0x560 + 32 + read-write + 0x8888 + 0xFFFFFFFF + + + WIDTH0 + Shift Width for channel 0 componnent 0. + 0 + 4 + read-write + + + WIDTH1 + Shift Width for channel 0 componnent 1. + 0x4 + 4 + read-write + + + WIDTH2 + Shift Width for channel 0 componnent 2. + 0x8 + 4 + read-write + + + WIDTH3 + Shift Width for channel 0 componnent 3. + 0xC + 4 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_INPUT_FETCH_SHIFT_WIDTH_CH1 + no description available + 0x570 + 32 + read-write + 0x8888 + 0xFFFFFFFF + + + WIDTH0 + Shift Width for channel 1 componnent 0. + 0 + 4 + read-write + + + WIDTH1 + Shift Width for channel 1 componnent 1. + 0x4 + 4 + read-write + + + WIDTH2 + Shift Width for channel 1 componnent 2. + 0x8 + 4 + read-write + + + WIDTH3 + Shift Width for channel 1 componnent 3. + 0xC + 4 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_INPUT_FETCH_ADDR_0_CH0 + no description available + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_ADDR_1_CH0 + no description available + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_ADDR_0_CH1 + no description available + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_ADDR_1_CH1 + no description available + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_CTRL_CH0 + Store engine Control Channel 0 Register + 0x5C0 + 32 + read-write + 0x20200 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Store function is disable + 0 + + + 1 + Store function is enable + 0x1 + + + + + BLOCK_EN + Choses the store mode. + 0x1 + 1 + read-write + + + 0 + Store in scan mode + 0 + + + 1 + Store in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the prefetch engine is disabled + 0 + + + 1 + Handshake with the prefetch engine is enabled + 0x1 + + + + + ARRAY_EN + no description available + 0x4 + 1 + read-write + + + 0 + Array Handshake Disabled + 0 + + + 1 + Array Handshake Enabled + 0x1 + + + + + ARRAY_LINE_NUM + Selects Array Size + 0x5 + 2 + read-write + + + 0 + Using 1x1 Array + 0 + + + 1 + Using 3x3 Array + 0x1 + + + 2 + Using 5x5 Array + 0x2 + + + 3 + Using 5x5 Array + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + STORE_BYPASS_EN + store bypass enable + 0x8 + 1 + read-write + + + 0 + store bypass mode disable. + 0 + + + 1 + store bypass mode enable. Data will bypass to store output. + 0x1 + + + + + STORE_MEMORY_EN + store memory enable + 0x9 + 1 + read-write + + + 0 + store memory mode disable. + 0 + + + 1 + store memory mode enable. Data will store to memory + 0x1 + + + + + PACK_IN_SEL + pack_in_sel + 0xA + 1 + read-write + + + 0 + select 64 shift out data to pack + 0 + + + 1 + select low 32 bit shift out data to pack + 0x1 + + + + + FILL_DATA_EN + fill data enable + 0xB + 1 + read-write + + + 0 + Fill data mode disable. + 0 + + + 1 + Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register + 0x1 + + + + + RSVD2 + Reserved, always set to zero. + 0xC + 4 + read-only + + + WR_NUM_BYTES + Bytes in a write burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes + 0 + + + 16_bytes + 16 bytes + 0x1 + + + 32_bytes + 32 bytes + 0x2 + + + 64_bytes + 64 bytes + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + COMBINE_2CHANNEL + Combine 2 channel Enable + 0x18 + 1 + read-write + + + 0 + combine 2 channel disable + 0 + + + 1 + combine 2 channel enable + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x19 + 6 + read-only + + + ARBIT_EN + Arbitration Enable + 0x1F + 1 + read-write + + + 0 + Arbitration disable. If using 2 channels, will output 2 axi bus sets + 0 + + + 1 + Arbitration enable. If using 2 channel, will only output 1 axi bus sets + 0x1 + + + + + + + HW_INPUT_STORE_CTRL_CH1 + Store engine Control Channel 1 Register + 0x5D0 + 32 + read-write + 0x20200 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Store function is disable + 0 + + + 1 + Store function is enable + 0x1 + + + + + BLOCK_EN + Choses the store mode. + 0x1 + 1 + read-write + + + 0 + Store in scan mode + 0 + + + 1 + Store in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the fetch engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the fetch engine is disabled + 0 + + + 1 + Handshake with the fetch engine is enabled + 0x1 + + + + + ARRAY_EN + no description available + 0x4 + 1 + read-write + + + 0 + Array Handshake Disabled + 0 + + + 1 + Array Handshake Enabled + 0x1 + + + + + ARRAY_LINE_NUM + Selects Array Size + 0x5 + 2 + read-write + + + 0 + Using 1x1 Array + 0 + + + 1 + Using 3x3 Array + 0x1 + + + 2 + Using 5x5 Array + 0x2 + + + 3 + Using 5x5 Array + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + STORE_BYPASS_EN + enable bit for store bypass + 0x8 + 1 + read-write + + + 0 + store bypass mode disable. + 0 + + + 1 + store bypass mode enable. Data will bypass to store output. + 0x1 + + + + + STORE_MEMORY_EN + store memory enable + 0x9 + 1 + read-write + + + 0 + store memory mode disable. + 0 + + + 1 + store memory mode enable. Data will store to memory. + 0x1 + + + + + PACK_IN_SEL + pack_in_sel + 0xA + 1 + read-write + + + 0 + select 64 shift out data to pack + 0 + + + 1 + select channel 0 high 32 bit shift out data to pack + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0xB + 5 + read-only + + + WR_NUM_BYTES + Bytes in a write burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes + 0 + + + 16_bytes + 16 bytes + 0x1 + + + 32_bytes + 32 bytes + 0x2 + + + 64_bytes + 64 bytes + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x12 + 14 + read-only + + + + + HW_INPUT_STORE_STATUS_CH0 + Store engine status Channel 0 Register + 0x5E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STORE_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + STORE_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_INPUT_STORE_STATUS_CH1 + Store engine status Channel 1 Register + 0x5F0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STORE_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + STORE_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_INPUT_STORE_SIZE_CH0 + no description available + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_WIDTH + actual output width -1 + 0 + 16 + read-write + + + OUT_HEIGHT + actual output height -1 + 0x10 + 16 + read-write + + + + + HW_INPUT_STORE_SIZE_CH1 + no description available + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_WIDTH + actual output width -1 + 0 + 16 + read-write + + + OUT_HEIGHT + actual output height -1 + 0x10 + 16 + read-write + + + + + HW_INPUT_STORE_PITCH + no description available + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_OUT_PITCH + This field indicates the channel 0 input pitch + 0 + 16 + read-write + + + CH1_OUT_PITCH + This field indicates the channel 1 input pitch + 0x10 + 16 + read-write + + + + + HW_INPUT_STORE_SHIFT_CTRL_CH0 + no description available + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD2 + Reserved, always set to zero. + 0 + 2 + read-only + + + OUTPUT_ACTIVE_BPP + no description available + 0x2 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + OUT_YUV422_1P_EN + Enable for YUV422 1 plane + 0x4 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + OUT_YUV422_2P_EN + Enable for YUV422 2 plane + 0x5 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + SHIFT_BYPASS + CH0 shift bypass + 0x7 + 1 + read-write + + + 0 + data will do shift processing. + 0 + + + 1 + data will bypass shift module. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x8 + 24 + read-only + + + + + HW_INPUT_STORE_SHIFT_CTRL_CH1 + no description available + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD2 + Reserved, always set to zero. + 0 + 2 + read-only + + + OUTPUT_ACTIVE_BPP + no description available + 0x2 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + OUT_YUV422_1P_EN + Enable for YUV422 1 plane + 0x4 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + OUT_YUV422_2P_EN + Enable for YUV422 2 plane + 0x5 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x6 + 26 + read-only + + + + + HW_INPUT_STORE_ADDR_0_CH0 + no description available + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_ADDR_1_CH0 + no description available + 0x6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_FILL_DATA_CH0 + no description available + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FILL_DATA_CH0 + when using fill_data mode,store engine channel0 will store the fill_data value defined here. + 0 + 32 + read-write + + + + + HW_INPUT_STORE_ADDR_0_CH1 + no description available + 0x6C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_ADDR_1_CH1 + no description available + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK0_H_CH0 + no description available + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK0_H_CH0 + data mask0 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK0_L_CH0 + no description available + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK0_L_CH0 + data mask0 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK1_H_CH0 + no description available + 0x700 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK1_H_CH0 + data mask1 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK1_L_CH0 + no description available + 0x710 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK1_L_CH0 + data mask1 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK2_H_CH0 + no description available + 0x720 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK2_H_CH0 + data mask2 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK2_L_CH0 + no description available + 0x730 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK2_L_CH0 + data mask2 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK3_H_CH0 + no description available + 0x740 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK3_H_CH0 + data mask3 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK3_L_CH0 + no description available + 0x750 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK3_L_CH0 + data mask3 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK4_H_CH0 + no description available + 0x760 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK4_H_CH0 + data mask4 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK4_L_CH0 + no description available + 0x770 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK4_L_CH0 + data mask4 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK5_H_CH0 + no description available + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK5_H_CH0 + data mask5 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK5_L_CH0 + no description available + 0x790 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK5_L_CH0 + data mask5 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK6_H_CH0 + no description available + 0x7A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK6_H_CH0 + data mask6 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK6_L_CH0 + no description available + 0x7B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK6_L_CH0 + data mask6 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK7_H_CH0 + no description available + 0x7C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK7_H_CH0 + data mask7 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK7_L_CH0 + no description available + 0x7E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK7_L_CH0 + data mask7 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_SHIFT_L_CH0 + no description available + 0x7F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SHIFT_WIDTH0 + data shift width 0 + 0 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + D_SHIFT_FLAG0 + data shift flag 0 + 0x7 + 1 + read-write + + + D_SHIFT_WIDTH1 + data shift width 1 + 0x8 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xE + 1 + read-only + + + D_SHIFT_FLAG1 + data shift flag 1 + 0xF + 1 + read-write + + + D_SHIFT_WIDTH2 + data shift width 2 + 0x10 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + D_SHIFT_FLAG2 + data shift flag 2 + 0x17 + 1 + read-write + + + D_SHIFT_WIDTH3 + data shift width 3 + 0x18 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1E + 1 + read-only + + + D_SHIFT_FLAG3 + data shift flag 3 + 0x1F + 1 + read-write + + + + + HW_INPUT_STORE_D_SHIFT_H_CH0 + no description available + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SHIFT_WIDTH4 + data shift width 4 + 0 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + D_SHIFT_FLAG4 + data shift flag 4 + 0x7 + 1 + read-write + + + D_SHIFT_WIDTH5 + data shift width 5 + 0x8 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xE + 1 + read-only + + + D_SHIFT_FLAG5 + data shift flag 5 + 0xF + 1 + read-write + + + D_SHIFT_WIDTH6 + data shift width 6 + 0x10 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + D_SHIFT_FLAG6 + data shift flag 6 + 0x17 + 1 + read-write + + + D_SHIFT_WIDTH7 + data shift width 3 + 0x18 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1E + 1 + read-only + + + D_SHIFT_FLAG7 + data shift flag 7 + 0x1F + 1 + read-write + + + + + HW_INPUT_STORE_F_SHIFT_L_CH0 + no description available + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_SHIFT_WIDTH0 + flag shift width 0 + 0 + 6 + read-write + + + F_SHIFT_FLAG0 + flag shift flag0 + 0x6 + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + F_SHIFT_WIDTH1 + flag shift width 1 + 0x8 + 6 + read-write + + + F_SHIFT_FLAG1 + flag shift flag1 + 0xE + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xF + 1 + read-only + + + F_SHIFT_WIDTH2 + flag shift width 2 + 0x10 + 6 + read-write + + + F_SHIFT_FLAG2 + flag shift flag2 + 0x16 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + F_SHIFT_WIDTH3 + flag shift width 3 + 0x18 + 6 + read-write + + + F_SHIFT_FLAG3 + flag shift flag3 + 0x1E + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_INPUT_STORE_F_SHIFT_H_CH0 + no description available + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_SHIFT_WIDTH4 + flag shift width 4 + 0 + 6 + read-write + + + F_SHIFT_FLAG4 + flag shift flag4 + 0x6 + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + F_SHIFT_WIDTH5 + flag shift width 5 + 0x8 + 6 + read-write + + + F_SHIFT_FLAG5 + flag shift flag5 + 0xE + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xF + 1 + read-only + + + F_SHIFT_WIDTH6 + flag shift width 5 + 0x10 + 6 + read-write + + + F_SHIFT_FLAG6 + flag shift flag6 + 0x16 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + F_SHIFT_WIDTH7 + flag shift width 7 + 0x18 + 6 + read-write + + + F_SHIFT_FLAG7 + flag shift flag7 + 0x1E + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_INPUT_STORE_F_MASK_L_CH0 + no description available + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_MASK0 + flag mask0 + 0 + 8 + read-write + + + F_MASK1 + flag mask1 + 0x8 + 8 + read-write + + + F_MASK2 + flag mask2 + 0x10 + 8 + read-write + + + F_MASK3 + flag mask3 + 0x18 + 8 + read-write + + + + + HW_INPUT_STORE_F_MASK_H_CH0 + no description available + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_MASK4 + flag mask4 + 0 + 8 + read-write + + + F_MASK5 + flag mask5 + 0x8 + 8 + read-write + + + F_MASK6 + flag mask6 + 0x10 + 8 + read-write + + + F_MASK7 + flag mask7 + 0x18 + 8 + read-write + + + + + HW_DITHER_FETCH_CTRL_CH0 + Pre-fetch engine Control Channel 0 Register + 0x850 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Prefetch function is disable + 0 + + + 1 + Prefetch function is enable + 0x1 + + + + + BLOCK_EN + Choses the prefetch mode. + 0x1 + 1 + read-write + + + 0 + Prefetch in scan mode + 0 + + + 1 + Prefetch in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the store engine is disabled + 0 + + + 1 + Handshake with the store engine is enabled + 0x1 + + + + + BYPASS_PIXEL_EN + Selects Channel 0 pixel source + 0x4 + 1 + read-write + + + 0 + Channel 0 is from memory + 0 + + + 1 + Channel 0 is from previous process engine + 0x1 + + + + + HIGH_BYTE + channel 0 high byte selection + 0x5 + 1 + read-write + + + 0 + In 64 bit mode, the output high byte will use channel1. + 0 + + + 1 + In 64 bit mode, the output high byte will use channel0 + 0x1 + + + + + RSVD4 + Reserved, always set to zero. + 0x6 + 3 + read-only + + + HFLIP + Enables HFLIP. + 0x9 + 1 + read-write + + + 0 + HFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + VFLIP + Enables VFLIP + 0xA + 1 + read-write + + + 0 + VFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 0xB + 1 + read-only + + + ROTATION_ANGLE + no description available + 0xC + 2 + read-write + + + ROT_0 + Rotate image by 0 degrees. + 0 + + + ROT_90 + Rotate image by 90 degrees. + 0x1 + + + ROT_180 + Rotate image by 180 degrees. + 0x2 + + + ROT_270 + Rotate image by 270 degrees. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RD_NUM_BYTES + Bytes in a read burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes. + 0 + + + 16_bytes + 16 bytes. + 0x1 + + + 32_bytes + 32 bytes. + 0x2 + + + 64_bytes + 64 bytes. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + HANDSHAKE_SCAN_LINE_NUM + scan handshake line number + 0x18 + 2 + read-write + + + 0 + 1 line. + 0 + + + 1 + 8 lines + 0x1 + + + 2 + 16 lines + 0x2 + + + 3 + 16 lines + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x1A + 5 + read-only + + + ARBIT_EN + Enables Arbitration + 0x1F + 1 + read-write + + + 0 + Arbitration disable. If using 2 channels, will output 2 axi bus sets. + 0 + + + 1 + Arbitration enable. If using 2 channel, will only output 1 axi bus sets + 0x1 + + + + + + + HW_DITHER_FETCH_CTRL_CH1 + Pre-fetch engine Control Channel 1 Register + 0x860 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Prefetch function is disable + 0 + + + 1 + Prefetch function is enable + 0x1 + + + + + BLOCK_EN + Choses the prefetch mode. + 0x1 + 1 + read-write + + + 0 + Prefetch in scan mode + 0 + + + 1 + Prefetch in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the store engine is disabled + 0 + + + 1 + Handshake with the store engine is enabled + 0x1 + + + + + BYPASS_PIXEL_EN + Selects Channel 1 pixel source + 0x4 + 1 + read-write + + + 0 + Channel 1 is from memory + 0 + + + 1 + Channel 1 is from previous process engine + 0x1 + + + + + RSVD4 + Reserved, always set to zero. + 0x5 + 4 + read-only + + + HFLIP + Enables HFLIP. + 0x9 + 1 + read-write + + + 0 + HFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + VFLIP + Enables VFLIP + 0xA + 1 + read-write + + + 0 + VFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 0xB + 1 + read-only + + + ROTATION_ANGLE + no description available + 0xC + 2 + read-write + + + ROT_0 + Rotate image by 0 degrees. + 0 + + + ROT_90 + Rotate image by 90 degrees. + 0x1 + + + ROT_180 + Rotate image by 180 degrees. + 0x2 + + + ROT_270 + Rotate image by 270 degrees. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RD_NUM_BYTES + Bytes in a read burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes. + 0 + + + 16_bytes + 16 bytes. + 0x1 + + + 32_bytes + 32 bytes. + 0x2 + + + 64_bytes + 64 bytes. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + HANDSHAKE_SCAN_LINE_NUM + scan handshake line number + 0x18 + 2 + read-write + + + 0 + 1 line. + 0 + + + 1 + 8 lines + 0x1 + + + 2 + 16 lines + 0x2 + + + 3 + 16 lines + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x1A + 6 + read-only + + + + + HW_DITHER_FETCH_STATUS_CH0 + Pre-fetch engine status Channel 0 Register + 0x870 + 32 + read-only + 0 + 0xFFFFFFFF + + + PREFETCH_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + PREFETCH_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_DITHER_FETCH_STATUS_CH1 + Store engine status Channel 1 Register + 0x880 + 32 + read-only + 0 + 0xFFFFFFFF + + + PREFETCH_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + PREFETCH_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 + no description available + 0x890 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_ULC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_ULC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 + no description available + 0x8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_LRC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_LRC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 + no description available + 0x8B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_ULC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_ULC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 + no description available + 0x8C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_LRC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_LRC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_SIZE_CH0 + no description available + 0x8D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_TOTAL_WIDTH + actual total widht -1 + 0 + 16 + read-write + + + INPUT_TOTAL_HEIGHT + actual total height -1 + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_SIZE_CH1 + no description available + 0x8E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_TOTAL_WIDTH + actual_total_width -1 + 0 + 16 + read-write + + + INPUT_TOTAL_HEIGHT + acutal total height -1 + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_BACKGROUND_COLOR_CH0 + no description available + 0x8F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BACKGROUND_COLOR + background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_BACKGROUND_COLOR_CH1 + no description available + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + BACKGROUND_COLOR + background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_PITCH + no description available + 0x910 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_INPUT_PITCH + This field indicates the channel 0 input pitch + 0 + 16 + read-write + + + CH1_INPUT_PITCH + This field indicates the channel 1 input pitch + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_SHIFT_CTRL_CH0 + no description available + 0x920 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + INPUT_ACTIVE_BPP + no description available + 0 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x2 + 6 + read-only + + + EXPAND_FORMAT + Select Pixel format + 0x8 + 3 + read-write + + + 0 + RGB 565 + 0 + + + 1 + RGB 555 + 0x1 + + + 2 + ARGB 1555 + 0x2 + + + 3 + RGB 444 + 0x3 + + + 4 + ARGB 4444 + 0x4 + + + 5 + YUYV/YVYU + 0x5 + + + 6 + UYVY/VYUY + 0x6 + + + 7 + YUV422_2P + 0x7 + + + + + EXPAND_EN + no description available + 0xB + 1 + read-write + + + 0 + channel0 format expanding disable + 0 + + + 1 + channel0 format expanding enable + 0x1 + + + + + SHIFT_BYPASS + no description available + 0xC + 1 + read-write + + + 0 + channel0 data will do shift function + 0 + + + 1 + channel0 will bypass shift function + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xD + 19 + read-only + + + + + HW_DITHER_FETCH_SHIFT_CTRL_CH1 + no description available + 0x930 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + INPUT_ACTIVE_BPP + no description available + 0 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x2 + 6 + read-only + + + EXPAND_FORMAT + Select Pixel format + 0x8 + 3 + read-write + + + 0 + RGB 565 + 0 + + + 1 + RGB 555 + 0x1 + + + 2 + ARGB 1555 + 0x2 + + + 3 + RGB 444 + 0x3 + + + 4 + ARGB 4444 + 0x4 + + + 5 + YUYV/YVYU + 0x5 + + + 6 + UYVY/VYUY + 0x6 + + + 7 + YUV422_2P + 0x7 + + + + + EXPAND_EN + no description available + 0xB + 1 + read-write + + + 0 + channel1 format expanding disable + 0 + + + 1 + channel1 format expanding enable + 0x1 + + + + + SHIFT_BYPASS + no description available + 0xC + 1 + read-write + + + 0 + channel1 data will do shift function + 0 + + + 1 + channel1 will bypass shift function + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xD + 19 + read-only + + + + + HW_DITHER_FETCH_SHIFT_OFFSET_CH0 + no description available + 0x940 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET0 + Shift Offset for channel 0 componnent 0. + 0 + 5 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + OFFSET1 + Shift Offset for channel 0 componnent 1. + 0x8 + 5 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + OFFSET2 + Shift Offset for channel 0 componnent 2. + 0x10 + 5 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x15 + 3 + read-only + + + OFFSET3 + Shift Offset for channel 0 componnent 3. + 0x18 + 5 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1D + 3 + read-only + + + + + HW_DITHER_FETCH_SHIFT_OFFSET_CH1 + no description available + 0x950 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET0 + Shift Offset for channel 1 componnent 0. + 0 + 5 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + OFFSET1 + Shift Offset for channel 1 componnent 1. + 0x8 + 5 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + OFFSET2 + Shift Offset for channel 1 componnent 2. + 0x10 + 5 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x15 + 3 + read-only + + + OFFSET3 + Shift Offset for channel 1 componnent 3. + 0x18 + 5 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1D + 3 + read-only + + + + + HW_DITHER_FETCH_SHIFT_WIDTH_CH0 + no description available + 0x960 + 32 + read-write + 0x8888 + 0xFFFFFFFF + + + WIDTH0 + Shift Width for channel 0 componnent 0. + 0 + 4 + read-write + + + WIDTH1 + Shift Width for channel 0 componnent 1. + 0x4 + 4 + read-write + + + WIDTH2 + Shift Width for channel 0 componnent 2. + 0x8 + 4 + read-write + + + WIDTH3 + Shift Width for channel 0 componnent 3. + 0xC + 4 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_DITHER_FETCH_SHIFT_WIDTH_CH1 + no description available + 0x970 + 32 + read-write + 0x8888 + 0xFFFFFFFF + + + WIDTH0 + Shift Width for channel 1 componnent 0. + 0 + 4 + read-write + + + WIDTH1 + Shift Width for channel 1 componnent 1. + 0x4 + 4 + read-write + + + WIDTH2 + Shift Width for channel 1 componnent 2. + 0x8 + 4 + read-write + + + WIDTH3 + Shift Width for channel 1 componnent 3. + 0xC + 4 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_DITHER_FETCH_ADDR_0_CH0 + no description available + 0x980 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_ADDR_1_CH0 + no description available + 0x990 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_ADDR_0_CH1 + no description available + 0x9A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_ADDR_1_CH1 + no description available + 0x9B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_CTRL_CH0 + Store engine Control Channel 0 Register + 0x9C0 + 32 + read-write + 0x20200 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Store function is disable + 0 + + + 1 + Store function is enable + 0x1 + + + + + BLOCK_EN + Choses the store mode. + 0x1 + 1 + read-write + + + 0 + Store in scan mode + 0 + + + 1 + Store in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the prefetch engine is disabled + 0 + + + 1 + Handshake with the prefetch engine is enabled + 0x1 + + + + + ARRAY_EN + no description available + 0x4 + 1 + read-write + + + 0 + Array Handshake Disabled + 0 + + + 1 + Array Handshake Enabled + 0x1 + + + + + ARRAY_LINE_NUM + Selects Array Size + 0x5 + 2 + read-write + + + 0 + Using 1x1 Array + 0 + + + 1 + Using 3x3 Array + 0x1 + + + 2 + Using 5x5 Array + 0x2 + + + 3 + Using 5x5 Array + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + STORE_BYPASS_EN + enable bit for store bypass + 0x8 + 1 + read-write + + + 0 + store bypass mode disable. + 0 + + + 1 + store bypass mode enable. Data will bypass to store output. + 0x1 + + + + + STORE_MEMORY_EN + store memory enable + 0x9 + 1 + read-write + + + 0 + store memory mode disable. + 0 + + + 1 + store memory mode enable. Data will store to memory + 0x1 + + + + + PACK_IN_SEL + pack_in_sel + 0xA + 1 + read-write + + + 0 + select 64 shift out data to pack + 0 + + + 1 + select low 32 bit shift out data to pack + 0x1 + + + + + FILL_DATA_EN + enable bit for fill data + 0xB + 1 + read-write + + + 0 + Fill data mode disable. + 0 + + + 1 + Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register + 0x1 + + + + + RSVD2 + Reserved, always set to zero. + 0xC + 4 + read-only + + + WR_NUM_BYTES + Bytes in a write burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes + 0 + + + 16_bytes + 16 bytes + 0x1 + + + 32_bytes + 32 bytes + 0x2 + + + 64_bytes + 64 bytes + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + COMBINE_2CHANNEL + Combine 2 channel Enable + 0x18 + 1 + read-write + + + 0 + combine 2 channel disable + 0 + + + 1 + combine 2 channel enable + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x19 + 6 + read-only + + + ARBIT_EN + Arbitration Enable + 0x1F + 1 + read-write + + + 0 + Arbitration disable. If using 2 channels, will output 2 axi bus sets + 0 + + + 1 + Arbitration enable. If using 2 channel, will only output 1 axi bus sets + 0x1 + + + + + + + HW_DITHER_STORE_CTRL_CH1 + Store engine Control Channel 1 Register + 0x9D0 + 32 + read-write + 0x20200 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Store function is disable + 0 + + + 1 + Store function is enable + 0x1 + + + + + BLOCK_EN + Choses the store mode. + 0x1 + 1 + read-write + + + 0 + Store in scan mode + 0 + + + 1 + Store in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the fetch engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the fetch engine is disabled + 0 + + + 1 + Handshake with the fetch engine is enabled + 0x1 + + + + + ARRAY_EN + no description available + 0x4 + 1 + read-write + + + 0 + Array Handshake Disabled + 0 + + + 1 + Array Handshake Enabled + 0x1 + + + + + ARRAY_LINE_NUM + Selects Array Size + 0x5 + 2 + read-write + + + 0 + Using 1x1 Array + 0 + + + 1 + Using 3x3 Array + 0x1 + + + 2 + Using 5x5 Array + 0x2 + + + 3 + Using 5x5 Array + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + STORE_BYPASS_EN + enable bit for store bypass + 0x8 + 1 + read-write + + + 0 + store bypass mode disable. + 0 + + + 1 + store bypass mode enable. Data will bypass to store output. + 0x1 + + + + + STORE_MEMORY_EN + store memory enable + 0x9 + 1 + read-write + + + 0 + store memory mode disable. + 0 + + + 1 + store memory mode enable. Data will store to memory + 0x1 + + + + + PACK_IN_SEL + pack_in_sel + 0xA + 1 + read-write + + + 0 + select 64 shift out data to pack + 0 + + + 1 + select channel 0 high 32 bit shift out data to pack + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0xB + 5 + read-only + + + WR_NUM_BYTES + Bytes in a write burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes + 0 + + + 16_bytes + 16 bytes + 0x1 + + + 32_bytes + 32 bytes + 0x2 + + + 64_bytes + 64 bytes + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x12 + 14 + read-only + + + + + HW_DITHER_STORE_STATUS_CH0 + Store engine status Channel 0 Register + 0x9E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STORE_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + STORE_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_DITHER_STORE_STATUS_CH1 + Store engine status Channel 1 Register + 0x9F0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STORE_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + STORE_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_DITHER_STORE_SIZE_CH0 + no description available + 0xA00 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_WIDTH + actual output width -1 + 0 + 16 + read-write + + + OUT_HEIGHT + actual output height -1 + 0x10 + 16 + read-write + + + + + HW_DITHER_STORE_SIZE_CH1 + no description available + 0xA10 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_WIDTH + actual output width -1 + 0 + 16 + read-write + + + OUT_HEIGHT + actual output height -1 + 0x10 + 16 + read-write + + + + + HW_DITHER_STORE_PITCH + no description available + 0xA20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_OUT_PITCH + This field indicates the channel 0 input pitch + 0 + 16 + read-write + + + CH1_OUT_PITCH + This field indicates the channel 1 input pitch + 0x10 + 16 + read-write + + + + + HW_DITHER_STORE_SHIFT_CTRL_CH0 + no description available + 0xA30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD2 + Reserved, always set to zero. + 0 + 2 + read-only + + + OUTPUT_ACTIVE_BPP + no description available + 0x2 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + OUT_YUV422_1P_EN + Enable for YUV422 1 plane + 0x4 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + OUT_YUV422_2P_EN + Enable for YUV422 2 plane + 0x5 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + SHIFT_BYPASS + CH0 shift bypass + 0x7 + 1 + read-write + + + 0 + data will do shift processing. + 0 + + + 1 + data will bypass shift module. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x8 + 24 + read-only + + + + + HW_DITHER_STORE_SHIFT_CTRL_CH1 + no description available + 0xA40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD2 + Reserved, always set to zero. + 0 + 2 + read-only + + + OUTPUT_ACTIVE_BPP + no description available + 0x2 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + OUT_YUV422_1P_EN + Enable for YUV422 1 plane + 0x4 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + OUT_YUV422_2P_EN + Enable for YUV422 2 plane + 0x5 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x6 + 26 + read-only + + + + + HW_DITHER_STORE_ADDR_0_CH0 + no description available + 0xA90 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_ADDR_1_CH0 + no description available + 0xAA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_FILL_DATA_CH0 + no description available + 0xAB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FILL_DATA_CH0 + when using fill_data mode,store engine channel0 will store the fill_data value defined here. + 0 + 32 + read-write + + + + + HW_DITHER_STORE_ADDR_0_CH1 + no description available + 0xAC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_ADDR_1_CH1 + no description available + 0xAD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK0_H_CH0 + no description available + 0xAE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK0_H_CH0 + data mask0 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK0_L_CH0 + no description available + 0xAF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK0_L_CH0 + data mask0 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK1_H_CH0 + no description available + 0xB00 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK1_H_CH0 + data mask1 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK1_L_CH0 + no description available + 0xB10 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK1_L_CH0 + data mask1 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK2_H_CH0 + no description available + 0xB20 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK2_H_CH0 + data mask2 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK2_L_CH0 + no description available + 0xB30 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK2_L_CH0 + data mask2 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK3_H_CH0 + no description available + 0xB40 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK3_H_CH0 + data mask3 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK3_L_CH0 + no description available + 0xB50 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK3_L_CH0 + data mask3 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK4_H_CH0 + no description available + 0xB60 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK4_H_CH0 + data mask4 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK4_L_CH0 + no description available + 0xB70 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK4_L_CH0 + data mask4 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK5_H_CH0 + no description available + 0xB80 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK5_H_CH0 + data mask5 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK5_L_CH0 + no description available + 0xB90 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK5_L_CH0 + data mask5 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK6_H_CH0 + no description available + 0xBA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK6_H_CH0 + data mask6 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK6_L_CH0 + no description available + 0xBB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK6_L_CH0 + data mask6 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK7_H_CH0 + no description available + 0xBC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK7_H_CH0 + data mask7 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK7_L_CH0 + no description available + 0xBD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK7_L_CH0 + data mask7 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_SHIFT_L_CH0 + no description available + 0xBE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SHIFT_WIDTH0 + data shift width 0 + 0 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + D_SHIFT_FLAG0 + data shift flag 0 + 0x7 + 1 + read-write + + + D_SHIFT_WIDTH1 + data shift width 1 + 0x8 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xE + 1 + read-only + + + D_SHIFT_FLAG1 + data shift flag 1 + 0xF + 1 + read-write + + + D_SHIFT_WIDTH2 + data shift width 2 + 0x10 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + D_SHIFT_FLAG2 + data shift flag 2 + 0x17 + 1 + read-write + + + D_SHIFT_WIDTH3 + data shift width 3 + 0x18 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1E + 1 + read-only + + + D_SHIFT_FLAG3 + data shift flag 3 + 0x1F + 1 + read-write + + + + + HW_DITHER_STORE_D_SHIFT_H_CH0 + no description available + 0xBF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SHIFT_WIDTH4 + data shift width 4 + 0 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + D_SHIFT_FLAG4 + data shift flag 4 + 0x7 + 1 + read-write + + + D_SHIFT_WIDTH5 + data shift width 5 + 0x8 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xE + 1 + read-only + + + D_SHIFT_FLAG5 + data shift flag 5 + 0xF + 1 + read-write + + + D_SHIFT_WIDTH6 + data shift width 6 + 0x10 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + D_SHIFT_FLAG6 + data shift flag 6 + 0x17 + 1 + read-write + + + D_SHIFT_WIDTH7 + data shift width 3 + 0x18 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1E + 1 + read-only + + + D_SHIFT_FLAG7 + data shift flag 7 + 0x1F + 1 + read-write + + + + + HW_DITHER_STORE_F_SHIFT_L_CH0 + no description available + 0xC00 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_SHIFT_WIDTH0 + flag shift width 0 + 0 + 6 + read-write + + + F_SHIFT_FLAG0 + flag shift flag0 + 0x6 + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + F_SHIFT_WIDTH1 + flag shift width 1 + 0x8 + 6 + read-write + + + F_SHIFT_FLAG1 + flag shift flag1 + 0xE + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xF + 1 + read-only + + + F_SHIFT_WIDTH2 + flag shift width 2 + 0x10 + 6 + read-write + + + F_SHIFT_FLAG2 + flag shift flag2 + 0x16 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + F_SHIFT_WIDTH3 + flag shift width 3 + 0x18 + 6 + read-write + + + F_SHIFT_FLAG3 + flag shift flag3 + 0x1E + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_DITHER_STORE_F_SHIFT_H_CH0 + no description available + 0xC10 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_SHIFT_WIDTH4 + flag shift width 4 + 0 + 6 + read-write + + + F_SHIFT_FLAG4 + flag shift flag4 + 0x6 + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + F_SHIFT_WIDTH5 + flag shift width 5 + 0x8 + 6 + read-write + + + F_SHIFT_FLAG5 + flag shift flag5 + 0xE + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xF + 1 + read-only + + + F_SHIFT_WIDTH6 + flag shift width 5 + 0x10 + 6 + read-write + + + F_SHIFT_FLAG6 + flag shift flag6 + 0x16 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + F_SHIFT_WIDTH7 + flag shift width 7 + 0x18 + 6 + read-write + + + F_SHIFT_FLAG7 + flag shift flag7 + 0x1E + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_DITHER_STORE_F_MASK_L_CH0 + no description available + 0xC20 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_MASK0 + flag mask0 + 0 + 8 + read-write + + + F_MASK1 + flag mask1 + 0x8 + 8 + read-write + + + F_MASK2 + flag mask2 + 0x10 + 8 + read-write + + + F_MASK3 + flag mask3 + 0x18 + 8 + read-write + + + + + HW_DITHER_STORE_F_MASK_H_CH0 + no description available + 0xC30 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_MASK4 + flag mask4 + 0 + 8 + read-write + + + F_MASK5 + flag mask5 + 0x8 + 8 + read-write + + + F_MASK6 + flag mask6 + 0x10 + 8 + read-write + + + F_MASK7 + flag mask7 + 0x18 + 8 + read-write + + + + + HW_DITHER_CTRL + Dither Control Register 0 + 0x1670 + 32 + read-write + 0x544000 + 0xFFFFFFFF + + + ENABLE0 + Enables the dither engine 0 + 0 + 1 + read-write + + + Disabled + The dither engine 0 will not process any frames. + 0 + + + Enabled + The dither engine 0 is on and ready for processing + 0x1 + + + + + ENABLE1 + Enables the dither engine 1 + 0x1 + 1 + read-write + + + Disabled + The dither engine 1 will not process any frames. + 0 + + + Enabled + The dither engine 1 is on and ready for processing + 0x1 + + + + + ENABLE2 + Enables the dither engine 2 + 0x2 + 1 + read-write + + + Disabled + The dither engine 2 will not process any frames. + 0 + + + Enabled + The dither engine 2 is on and ready for processing + 0x1 + + + + + DITHER_MODE0 + Dither mode. + 0x3 + 3 + read-write + + + 0 + Pass through. + 0 + + + 1 + Floyd-Steinberg. + 0x1 + + + 2 + Atkinson. + 0x2 + + + 3 + Ordered. + 0x3 + + + 4 + No Dithering, quantization only. + 0x4 + + + + + DITHER_MODE1 + Dither mode. + 0x6 + 3 + read-write + + + 0 + Pass through. + 0 + + + 3 + Ordered. + 0x3 + + + 4 + No Dithering, quantization only. + 0x4 + + + + + DITHER_MODE2 + Dither mode. + 0x9 + 3 + read-write + + + 0 + Pass through. + 0 + + + 3 + Ordered. + 0x3 + + + 4 + No Dithering, quantization only. + 0x4 + + + + + NUM_QUANT_BIT + Number of bits to quantize down to. From 8 to (0-7). + 0xC + 3 + read-write + + + 1 + Quantize down to 1 bit. + 0x1 + + + 2 + Quantize down to 2 bits. + 0x2 + + + 3 + Quantize down to 3 bits. + 0x3 + + + 4 + Quantize down to 4 bits. + 0x4 + + + 5 + Quantize down to 5 bits. + 0x5 + + + 6 + Quantize down to 6 bits. + 0x6 + + + 7 + Quantize down to 7 bits. + 0x7 + + + + + LUT_MODE + Specify to use memory lut to transform pixel + 0xF + 2 + read-write + + + 0 + LUT mode off. + 0 + + + 1 + Use LUT at pre-diter stage. + 0x1 + + + 2 + Use LUT at post-dither stage. + 0x2 + + + + + IDX_MATRIX0_SIZE + For Dither Engine 0 + 0x11 + 2 + read-write + + + 0 + 4x4 + 0 + + + 1 + 8x8 + 0x1 + + + 2 + 16x16 + 0x2 + + + 3 + Input value of index + 0x3 + + + + + IDX_MATRIX1_SIZE + For Dither Engine 1 + 0x13 + 2 + read-write + + + 0 + 4x4 + 0 + + + 1 + 8x8 + 0x1 + + + 2 + 16x16 + 0x2 + + + 3 + Input value of index + 0x3 + + + + + IDX_MATRIX2_SIZE + For Dither Engine 2 + 0x15 + 2 + read-write + + + 0 + 4x4 + 0 + + + 1 + 8x8 + 0x1 + + + 2 + 16x16 + 0x2 + + + 3 + Input value of index + 0x3 + + + + + FINAL_LUT_ENABLE + Enables a final stage register based LUT at the last stage before output + 0x17 + 1 + read-write + + + Disabled + The dither engine 2 will not process any frames. + 0 + + + Enabled + The dither engine 2 is on and ready for processing + 0x1 + + + + + ORDERED_ROUND_MODE + For test purposes + 0x18 + 1 + read-write + + + 0 + Use truncation method. + 0 + + + 1 + Use rounding method. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x19 + 4 + read-only + + + BUSY2 + When set indicates if the dither engine 2 is busy -- started but not finished processing all of the pixels in the current frame + 0x1D + 1 + read-only + + + BUSY1 + When set indicates if the dither engine 1 is busy -- started but not finished processing all of the pixels in the current frame + 0x1E + 1 + read-only + + + BUSY0 + When set indicates if the dither engine 0 is busy -- started but not finished processing all of the pixels in the current frame + 0x1F + 1 + read-only + + + + + HW_DITHER_FINAL_LUT_DATA0 + Final stage lookup value Register + 0x1680 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA0 + Final stage LUT data value. + 0 + 8 + read-write + + + DATA1 + Final stage LUT data value. + 0x8 + 8 + read-write + + + DATA2 + Final stage LUT data value. + 0x10 + 8 + read-write + + + DATA3 + Final stage LUT data value. + 0x18 + 8 + read-write + + + + + HW_DITHER_FINAL_LUT_DATA1 + Final stage lookup value Register + 0x1690 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA4 + Final stage LUT data value. + 0 + 8 + read-write + + + DATA5 + Final stage LUT data value. + 0x8 + 8 + read-write + + + DATA6 + Final stage LUT data value. + 0x10 + 8 + read-write + + + DATA7 + Final stage LUT data value. + 0x18 + 8 + read-write + + + + + HW_DITHER_FINAL_LUT_DATA2 + Final stage lookup value Register + 0x16A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA8 + Final stage LUT data value. + 0 + 8 + read-write + + + DATA9 + Final stage LUT data value. + 0x8 + 8 + read-write + + + DATA10 + Final stage LUT data value. + 0x10 + 8 + read-write + + + DATA11 + Final stage LUT data value. + 0x18 + 8 + read-write + + + + + HW_DITHER_FINAL_LUT_DATA3 + Final stage lookup value Register + 0x16B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA12 + Final stage LUT data value. + 0 + 8 + read-write + + + DATA13 + Final stage LUT data value. + 0x8 + 8 + read-write + + + DATA14 + Final stage LUT data value. + 0x10 + 8 + read-write + + + DATA15 + Final stage LUT data value. + 0x18 + 8 + read-write + + + + + HW_HIST_A_CTRL + Histogram Control Register. + 0x2A00 + 32 + read-write + 0x5001F00 + 0xFFFFFFFF + + + ENABLE + Enable the Histogram Engine + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 3 + read-only + + + CLEAR + Write 1 to clear the histogram result and will be self-clear after clear function finished + 0x4 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + STATUS + Indicates which histogram matched the processed bitmap + 0x8 + 5 + read-only + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + PIXEL_OFFSET + The offset of the pixel to be used for histogram calculation + 0x10 + 7 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + PIXEL_WIDTH + The width of the pixel to be used for histogram calculation + 0x18 + 3 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_HIST_A_MASK + Histogram Pixel Mask Register. + 0x2A10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK_EN + Enable the Pixel Mask Function in Histogram + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 3 + read-only + + + MASK_MODE + Operation mode of pixel mask function + 0x4 + 2 + read-write + + + EQUAL + Run histogram for pixels equal to value0 + 0 + + + NOT_EQUAL + Run histogram for pixels not equal to value0 + 0x1 + + + INSIDE + Run histogram for pixels within the range of value0 to value1 + 0x2 + + + OUTSIDE + Run histogram for pixels outside of the rang of value0 to value1 + 0x3 + + + + + MASK_OFFSET + The offset of the field to be checked against mask condition + 0x6 + 7 + read-write + + + MASK_WIDTH + The width of the field to be checked against mask condition + 0xD + 3 + read-write + + + MASK_VALUE0 + The value0 for mask condition checking + 0x10 + 8 + read-write + + + MASK_VALUE1 + The value1 for mask condition checking + 0x18 + 8 + read-write + + + + + HW_HIST_A_BUF_SIZE + Histogram Pixel Buffer Size Register. + 0x2A20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WIDTH + This indicate the buffer width in pixels + 0 + 12 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + HEIGHT + This indicate the buffer height in pixels + 0x10 + 12 + read-write + + + RSVD0 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_A_TOTAL_PIXEL + Total Number of Pixels Used by Histogram Engine. + 0x2A30 + 32 + read-only + 0 + 0xFFFFFFFF + + + TOTAL_PIXEL + Total number of pixels used by histogram engine, the pixels got masked will be skipped + 0 + 24 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0x18 + 8 + read-only + + + + + HW_HIST_A_ACTIVE_AREA_X + The X Coordinate Offset for Active Area. + 0x2A40 + 32 + read-only + 0 + 0xFFFFFFFF + + + MIN_X_OFFSET + Minimul X coordinate offset for the active area in histogram processing + 0 + 12 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + MAX_X_OFFSET + Maximum X coordinate offset for the active area in histogram processing + 0x10 + 12 + read-only + + + RSVD1 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_A_ACTIVE_AREA_Y + The Y Coordinate Offset for Active Area. + 0x2A50 + 32 + read-only + 0 + 0xFFFFFFFF + + + MIN_Y_OFFSET + Minimul Y coordinate offset for the active area in histogram processing + 0 + 12 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + MAX_Y_OFFSET + Maximum Y coordinate offset for the active area in histogram processing + 0x10 + 12 + read-only + + + RSVD1 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_A_RAW_STAT0 + Histogram Result Based on RAW Pixel Value. + 0x2A60 + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT0 + Lower 32-bit result fo the histogram calculation + 0 + 32 + read-only + + + + + HW_HIST_A_RAW_STAT1 + Histogram Result Based on RAW Pixel Value. + 0x2A70 + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT1 + Higher 32-bit result fo the histogram calculation + 0 + 32 + read-only + + + + + HW_HIST_B_CTRL + Histogram Control Register. + 0x2A80 + 32 + read-write + 0x5001F00 + 0xFFFFFFFF + + + ENABLE + Enable the Histogram Engine + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 3 + read-only + + + CLEAR + Write 1 to clear the histogram result and will be self-clear after clear function finished + 0x4 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + STATUS + Indicates which histogram matched the processed bitmap + 0x8 + 5 + read-only + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + PIXEL_OFFSET + The offset of the pixel to be used for histogram calculation + 0x10 + 7 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + PIXEL_WIDTH + The width of the pixel to be used for histogram calculation + 0x18 + 3 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_HIST_B_MASK + Histogram Pixel Mask Register. + 0x2A90 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK_EN + Enable the Pixel Mask Function in Histogram + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 3 + read-only + + + MASK_MODE + Operation mode of pixel mask function + 0x4 + 2 + read-write + + + EQUAL + Run histogram for pixels equal to value0 + 0 + + + NOT_EQUAL + Run histogram for pixels not equal to value0 + 0x1 + + + INSIDE + Run histogram for pixels within the range of value0 to value1 + 0x2 + + + OUTSIDE + Run histogram for pixels outside of the rang of value0 to value1 + 0x3 + + + + + MASK_OFFSET + The offset of the field to be checked against mask condition + 0x6 + 7 + read-write + + + MASK_WIDTH + The width of the field to be checked against mask condition + 0xD + 3 + read-write + + + MASK_VALUE0 + The value0 for mask condition checking + 0x10 + 8 + read-write + + + MASK_VALUE1 + The value1 for mask condition checking + 0x18 + 8 + read-write + + + + + HW_HIST_B_BUF_SIZE + Histogram Pixel Buffer Size Register. + 0x2AA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + WIDTH + This indicate the buffer width in pixels + 0 + 12 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + HEIGHT + This indicate the buffer height in pixels + 0x10 + 12 + read-write + + + RSVD0 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_B_TOTAL_PIXEL + Total Number of Pixels Used by Histogram Engine. + 0x2AB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + TOTAL_PIXEL + Total number of pixels used by histogram engine, the pixels got masked will be skipped + 0 + 24 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0x18 + 8 + read-only + + + + + HW_HIST_B_ACTIVE_AREA_X + The X Coordinate Offset for Active Area. + 0x2AC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + MIN_X_OFFSET + Minimul X coordinate offset for the active area in histogram processing + 0 + 12 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + MAX_X_OFFSET + Maximum X coordinate offset for the active area in histogram processing + 0x10 + 12 + read-only + + + RSVD1 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_B_ACTIVE_AREA_Y + The Y Coordinate Offset for Active Area. + 0x2AD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + MIN_Y_OFFSET + Minimul Y coordinate offset for the active area in histogram processing + 0 + 12 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + MAX_Y_OFFSET + Maximum Y coordinate offset for the active area in histogram processing + 0x10 + 12 + read-only + + + RSVD1 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_B_RAW_STAT0 + Histogram Result Based on RAW Pixel Value. + 0x2AE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT0 + Lower 32-bit result fo the histogram calculation + 0 + 32 + read-only + + + + + HW_HIST_B_RAW_STAT1 + Histogram Result Based on RAW Pixel Value. + 0x2AF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT1 + Higher 32-bit result fo the histogram calculation + 0 + 32 + read-only + + + + + HW_HIST2_PARAM + 2-level Histogram Parameter Register. + 0x2B00 + 32 + read-write + 0xF00 + 0xFFFFFFFF + + + VALUE0 + Black value for 2-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + White value for 2-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RSVD + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_HIST4_PARAM + 4-level Histogram Parameter Register. + 0x2B10 + 32 + read-write + 0xF0A0500 + 0xFFFFFFFF + + + VALUE0 + GRAY0 (Black) value for 4-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + GRAY1 value for 4-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE2 + GRAY2 value for 4-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE3 + GRAY3 (White) value for 4-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST8_PARAM0 + 8-level Histogram Parameter 0 Register. + 0x2B20 + 32 + read-write + 0x6040200 + 0xFFFFFFFF + + + VALUE0 + GRAY0 (Black) value for 8-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + GRAY1 value for 8-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE2 + GRAY2 value for 8-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE3 + GRAY3 value for 8-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST8_PARAM1 + 8-level Histogram Parameter 1 Register. + 0x2B30 + 32 + read-write + 0xF0D0B09 + 0xFFFFFFFF + + + VALUE4 + GRAY4 value for 8-level histogram + 0 + 6 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE5 + GRAY5 value for 8-level histogram + 0x8 + 6 + read-write + + + RSVD5 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE6 + GRAY6 value for 8-level histogram + 0x10 + 6 + read-write + + + RSVD6 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE7 + GRAY7 (White) value for 8-level histogram + 0x18 + 6 + read-write + + + RSVD7 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST16_PARAM0 + 16-level Histogram Parameter 0 Register. + 0x2B40 + 32 + read-write + 0x3020100 + 0xFFFFFFFF + + + VALUE0 + GRAY0 (Black) value for 16-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + GRAY1 value for 16-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE2 + GRAY2 value for 16-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE3 + GRAY3 value for 16-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST16_PARAM1 + 16-level Histogram Parameter 1 Register. + 0x2B50 + 32 + read-write + 0x7060504 + 0xFFFFFFFF + + + VALUE4 + GRAY4 value for 16-level histogram + 0 + 6 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE5 + GRAY5 value for 16-level histogram + 0x8 + 6 + read-write + + + RSVD5 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE6 + GRAY6 value for 16-level histogram + 0x10 + 6 + read-write + + + RSVD6 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE7 + GRAY7 value for 16-level histogram + 0x18 + 6 + read-write + + + RSVD7 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST16_PARAM2 + 16-level Histogram Parameter 2 Register. + 0x2B60 + 32 + read-write + 0xB0A0908 + 0xFFFFFFFF + + + VALUE8 + GRAY8 value for 16-level histogram + 0 + 6 + read-write + + + RSVD8 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE9 + GRAY9 value for 16-level histogram + 0x8 + 6 + read-write + + + RSVD9 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE10 + GRAY10 value for 16-level histogram + 0x10 + 6 + read-write + + + RSVD10 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE11 + GRAY11 value for 16-level histogram + 0x18 + 6 + read-write + + + RSVD11 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST16_PARAM3 + 16-level Histogram Parameter 3 Register. + 0x2B70 + 32 + read-write + 0xF0E0D0C + 0xFFFFFFFF + + + VALUE12 + GRAY12 value for 16-level histogram + 0 + 6 + read-write + + + RSVD12 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE13 + GRAY13 value for 16-level histogram + 0x8 + 6 + read-write + + + RSVD13 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE14 + GRAY14 value for 16-level histogram + 0x10 + 6 + read-write + + + RSVD14 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE15 + GRAY15 (White) value for 16-level histogram + 0x18 + 6 + read-write + + + RSVD15 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM0 + 32-level Histogram Parameter 0 Register. + 0x2B80 + 32 + read-write + 0x3020100 + 0xFFFFFFFF + + + VALUE0 + GRAY0 (Black) value for 32-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + GRAY1 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE2 + GRAY2 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE3 + GRAY3 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM1 + 32-level Histogram Parameter 1 Register. + 0x2B90 + 32 + read-write + 0x7060504 + 0xFFFFFFFF + + + VALUE4 + GRAY4 value for 32-level histogram + 0 + 6 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE5 + GRAY5 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD5 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE6 + GRAY6 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD6 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE7 + GRAY7 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD7 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM2 + 32-level Histogram Parameter 2 Register. + 0x2BA0 + 32 + read-write + 0xB0A0908 + 0xFFFFFFFF + + + VALUE8 + GRAY8 value for 32-level histogram + 0 + 6 + read-write + + + RSVD8 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE9 + GRAY9 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD9 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE10 + GRAY10 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD10 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE11 + GRAY11 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD11 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM3 + 32-level Histogram Parameter 3 Register. + 0x2BB0 + 32 + read-write + 0xF0E0D0C + 0xFFFFFFFF + + + VALUE12 + GRAY12 value for 32-level histogram + 0 + 6 + read-write + + + RSVD12 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE13 + GRAY13 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD13 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE14 + GRAY14 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD14 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE15 + GRAY15 (White) value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD15 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM4 + 32-level Histogram Parameter 0 Register. + 0x2BC0 + 32 + read-write + 0x3020100 + 0xFFFFFFFF + + + VALUE16 + GRAY16 (Black) value for 32-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE17 + GRAY17 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE18 + GRAY18 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE19 + GRAY19 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM5 + 32-level Histogram Parameter 1 Register. + 0x2BD0 + 32 + read-write + 0x7060504 + 0xFFFFFFFF + + + VALUE20 + GRAY20 value for 32-level histogram + 0 + 6 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE21 + GRAY21 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD5 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE22 + GRAY22 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD6 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE23 + GRAY23 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD7 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM6 + 32-level Histogram Parameter 2 Register. + 0x2BE0 + 32 + read-write + 0xB0A0908 + 0xFFFFFFFF + + + VALUE24 + GRAY24 value for 32-level histogram + 0 + 6 + read-write + + + RSVD8 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE25 + GRAY25 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD9 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE26 + GRAY26 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD10 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE27 + GRAY27 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD11 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM7 + 32-level Histogram Parameter 3 Register. + 0x2BF0 + 32 + read-write + 0xF0E0D0C + 0xFFFFFFFF + + + VALUE28 + GRAY28 value for 32-level histogram + 0 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE29 + GRAY29 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD13 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE30 + GRAY30 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD14 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE31 + GRAY31 (White) value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD15 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_COMP_CTRL + no description available + 0x2C00 + 32 + read-write + 0 + 0xFFFFFFFF + + + START + Write to 1 to start operation, self-clear + 0 + 1 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0x1 + 7 + read-only + + + SW_RESET + Write to 1 to do a software reset to the engine, self-clear. + 0x8 + 1 + read-write + + + RSVD0 + Reserved. This field always reads 0. + 0x9 + 23 + read-only + + + + + HW_COMP_FORMAT0 + no description available + 0x2C10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLAG_32B + 1 indicate 32-bit for one pixel, 0 for 16-bit + 0 + 1 + read-write + + + RSVD3 + Reserved. This field always reads 0. + 0x1 + 3 + read-only + + + FIELD_NUM + indicate how many fields in one pixel,0 for only A;3 for ABCD + 0x4 + 2 + read-write + + + RSVD2 + Reserved. This field always reads 0. + 0x6 + 2 + read-only + + + MASK_INDEX + which field is the mask,0 for A, 3 for D + 0x8 + 2 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0xA + 6 + read-only + + + PIXEL_PITCH_64B + extend each line to be 64-bit aligned + 0x10 + 10 + read-write + + + ERR_PRONE + step1 write fifo full. If detected, this bit is 1, there is data error in current frame. + 0x1A + 1 + read-only + + + FIFOFULL + step1 write fifo full + 0x1B + 1 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_COMP_FORMAT1 + no description available + 0x2C20 + 32 + read-write + 0 + 0xFFFFFFFF + + + A_OFFSET + offset for field A, 0 means A start from bit0 + 0 + 5 + read-write + + + A_LEN + length of field A, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit + 0x5 + 3 + read-write + + + B_OFFSET + offset for field B, 0 means B start from bit0 + 0x8 + 5 + read-write + + + B_LEN + length of field B, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit + 0xD + 3 + read-write + + + C_OFFSET + offset for field C, 0 means C start from bit0 + 0x10 + 5 + read-write + + + C_LEN + length of field C, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit + 0x15 + 3 + read-write + + + D_OFFSET + offset for field D, 0 means D start from bit0 + 0x18 + 5 + read-write + + + D_LEN + length of field D, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit + 0x1D + 3 + read-write + + + + + HW_COMP_FORMAT2 + no description available + 0x2C30 + 32 + read-write + 0 + 0xFFFFFFFF + + + A_RUNLEN + length of the RLE for field A, 12-bit(4095) max + 0 + 4 + read-write + + + B_RUNLEN + length of the RLE for field B, 12-bit(4095) max + 0x4 + 4 + read-write + + + C_RUNLEN + length of the RLE for field C, 12-bit(4095) max + 0x8 + 4 + read-write + + + D_RUNLEN + length of the RLE for field D, 12-bit(4095) max + 0xC + 4 + read-write + + + RSVD + Reserved. This field always reads 0. + 0x10 + 16 + read-only + + + + + HW_COMP_MASK0 + no description available + 0x2C40 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD_MASK_LOW + low 32bit of the valid mask, one of ABCD will be vld_flag,1 left shifted by vld_flag anded with vld_mask will be used to check whether this pixel is valid + 0 + 32 + read-write + + + + + HW_COMP_MASK1 + no description available + 0x2C50 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD_MASK_HIGH + high 32bit of the valid mask + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_SIZE + no description available + 0x2C60 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL_LENGTH + pixel length of the input frame, 4096 max + 0 + 13 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0xD + 3 + read-only + + + PIXEL_WIDTH + pixel width of the input frame, 4096 max + 0x10 + 13 + read-write + + + RSVD0 + Reserved. This field always reads 0. + 0x1D + 3 + read-only + + + + + HW_COMP_SOURCE + no description available + 0x2C70 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE_ADDR + source address of the input frame that located in the memory, should be 32-byte aligned + 0 + 32 + read-write + + + + + HW_COMP_TARGET + no description available + 0x2C80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TARGET_ADDR + taget address of the output frmae that the pxp compress engine should write to the memory, should be 32-byte aligned + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_A + no description available + 0x2C90 + 32 + read-write + 0 + 0xFFFFFFFF + + + A_SRAM_ADDR + sram address used for inter-data saving of A filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_B + no description available + 0x2CA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + B_SRAM_ADDR + sram address used for inter-data saving of B filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_C + no description available + 0x2CB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + C_SRAM_ADDR + sram address used for inter-data saving of C filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_D + no description available + 0x2CC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SRAM_ADDR + sram address used for inter-data saving of D filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap + 0 + 32 + read-write + + + + + HW_COMP_DEBUG + no description available + 0x2CD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_SEL + debug selection + 0 + 8 + read-write + + + DEBUG_VALUE + value of selected debug signal + 0x8 + 24 + read-only + + + + + HW_BUS_MUX + no description available + 0x2CE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RD_SEL + Subblock BUS to AXI MUX, setting 0 to axi0 and setting 1 to axi1 + 0 + 8 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x8 + 8 + read-only + + + WR_SEL + Subblock BUS to AXI MUX, setting 0 to axi0 and setting 1 to axi1 + 0x10 + 8 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_HANDSHAKE_READY_MUX0 + no description available + 0x2CF0 + 32 + read-write + 0x76543210 + 0xFFFFFFFF + + + HSK0 + Subblock double buffer handshake signals MUX 0: Ready signal source is from pxp_control; 1: Ready signal source is from pxp_store_wfe_B CH0; 2: Ready signal source is from pxp_store_wfe_B CH1; 3: Ready signal source is from pxp_store_pre_ditering CH0; 4: Ready signal source is from pxp_store_pre_ditering CH1; 5: Ready signal source is from pxp_store_dithering CH0; 6: Ready signal source is from pxp_store_dithering CH1; 7: Ready signal source is from pxp_store_wfe_a CH0; 8: Ready signal source is from pxp_store_wfe_a CH1; 9: Ready signal source is from cpu_fetch_sw0_ready; A: Ready signal source is from cpu_fetch_sw1_ready; B: Ready signal source is from cpu_store_sw0_ready; C: Ready signal source is from cpu_store_sw1_ready; + 0 + 4 + read-write + + + HSK1 + Subblock double buffer handshake signals MUX + 0x4 + 4 + read-write + + + HSK2 + Subblock double buffer handshake signals MUX + 0x8 + 4 + read-write + + + HSK3 + Subblock double buffer handshake signals MUX + 0xC + 4 + read-write + + + HSK4 + Subblock double buffer handshake signals MUX + 0x10 + 4 + read-write + + + HSK5 + Subblock double buffer handshake signals MUX + 0x14 + 4 + read-write + + + HSK6 + Subblock double buffer handshake signals MUX + 0x18 + 4 + read-write + + + HSK7 + Subblock double buffer handshake signals MUX + 0x1C + 4 + read-write + + + + + HW_HANDSHAKE_READY_MUX1 + no description available + 0x2D00 + 32 + read-write + 0xFEDCBA98 + 0xFFFFFFFF + + + HSK8 + Subblock double buffer handshake signals MUX + 0 + 4 + read-write + + + HSK9 + Subblock double buffer handshake signals MUX + 0x4 + 4 + read-write + + + HSK10 + Subblock double buffer handshake signals MUX + 0x8 + 4 + read-write + + + HSK11 + Subblock double buffer handshake signals MUX + 0xC + 4 + read-write + + + HSK12 + Subblock double buffer handshake signals MUX + 0x10 + 4 + read-write + + + HSK13 + Subblock double buffer handshake signals MUX + 0x14 + 4 + read-write + + + HSK14 + Subblock double buffer handshake signals MUX + 0x18 + 4 + read-write + + + HSK15 + Subblock double buffer handshake signals MUX + 0x1C + 4 + read-write + + + + + HW_HANDSHAKE_DONE_MUX0 + no description available + 0x2D10 + 32 + read-write + 0x76543210 + 0xFFFFFFFF + + + HSK0 + Subblock double buffer handshake signals MUX 0: Done signal source is from LCDIF; 1: Done signal source is from pxp_fetch_input CH0; 2: Done signal source is from pxp_fetch_input CH1; 3: Done signal source is from pxp_fetch_dithering CH0; 4: Done signal source is from pxp_fetch_dithering CH1; 5: Done signal source is from pxp_fetch_wfe_a CH0; 6: Done signal source is from pxp_fetch_wfe_a CH1; 7: Done signal source is from pxp_fetch_wfe_b CH0; 8: Done signal source is from pxp_fetch_wfe_b CH1; 9: Done signal source is from cpu_fetch_sw0_done; A: Done signal source is from cpu_fetch_sw1_done; B: Done signal source is from cpu_store_sw0_done; C: Done signal source is from cpu_store_sw1_done; + 0 + 4 + read-write + + + HSK1 + Subblock double buffer handshake signals MUX + 0x4 + 4 + read-write + + + HSK2 + Subblock double buffer handshake signals MUX + 0x8 + 4 + read-write + + + HSK3 + Subblock double buffer handshake signals MUX + 0xC + 4 + read-write + + + HSK4 + Subblock double buffer handshake signals MUX + 0x10 + 4 + read-write + + + HSK5 + Subblock double buffer handshake signals MUX + 0x14 + 4 + read-write + + + HSK6 + Subblock double buffer handshake signals MUX + 0x18 + 4 + read-write + + + HSK7 + Subblock double buffer handshake signals MUX + 0x1C + 4 + read-write + + + + + HW_HANDSHAKE_DONE_MUX1 + no description available + 0x2D20 + 32 + read-write + 0xFEDCBA98 + 0xFFFFFFFF + + + HSK8 + Subblock double buffer handshake signals MUX + 0 + 4 + read-write + + + HSK9 + Subblock double buffer handshake signals MUX + 0x4 + 4 + read-write + + + HSK10 + Subblock double buffer handshake signals MUX + 0x8 + 4 + read-write + + + HSK11 + Subblock double buffer handshake signals MUX + 0xC + 4 + read-write + + + HSK12 + Subblock double buffer handshake signals MUX + 0x10 + 4 + read-write + + + HSK13 + Subblock double buffer handshake signals MUX + 0x14 + 4 + read-write + + + HSK14 + Subblock double buffer handshake signals MUX + 0x18 + 4 + read-write + + + HSK15 + Subblock double buffer handshake signals MUX + 0x1C + 4 + read-write + + + + + HW_HANDSHAKE_CPU_FETCH + no description available + 0x2D30 + 32 + read-write + 0x100010 + 0xFFFFFFFF + + + SW0_B0_READY + PXP b0 buffer ready to CPU + 0 + 1 + read-only + + + SW0_B1_READY + PXP b1 buffer ready to CPU + 0x1 + 1 + read-only + + + SW0_B0_DONE + CPU b0 buffer done to PXP + 0x2 + 1 + read-write + + + SW0_B1_DONE + CPU b1 buffer done to PXP + 0x3 + 1 + read-write + + + SW0_BUF_LINES + Buffer lines for software handshake + 0x4 + 2 + read-only + + + LINE_4 + Buffer lines is 4 lines. + 0 + + + LINE_8 + Buffer lines is 8 lines. + 0x1 + + + LINE_16 + Buffer lines is 16 lines. + 0x2 + + + + + RSVD0 + Reserved, always set to zero. + 0x6 + 9 + read-only + + + SW0_HSK_EN + Enable software handshake 0 with CPU + 0xF + 1 + read-write + + + SW1_B0_READY + PXP b0 buffer ready to CPU + 0x10 + 1 + read-only + + + SW1_B1_READY + PXP b1 buffer ready to CPU + 0x11 + 1 + read-only + + + SW1_B0_DONE + CPU b0 buffer done to PXP + 0x12 + 1 + read-write + + + SW1_B1_DONE + CPU b1 buffer done to PXP + 0x13 + 1 + read-write + + + SW1_BUF_LINES + Buffer lines for software handshake + 0x14 + 2 + read-only + + + LINE_4 + Buffer lines is 4 lines. + 0 + + + LINE_8 + Buffer lines is 8 lines. + 0x1 + + + LINE_16 + Buffer lines is 16 lines. + 0x2 + + + + + RSVD1 + Reserved, always set to zero. + 0x16 + 9 + read-only + + + SW1_HSK_EN + Enable software handshake 1 with CPU + 0x1F + 1 + read-write + + + + + HW_HANDSHAKE_CPU_STORE + no description available + 0x2D40 + 32 + read-write + 0x100010 + 0xFFFFFFFF + + + SW0_B0_READY + PXP b0 buffer ready to CPU + 0 + 1 + read-write + + + SW0_B1_READY + PXP b1 buffer ready to CPU + 0x1 + 1 + read-write + + + SW0_B0_DONE + CPU b0 buffer done to PXP + 0x2 + 1 + read-only + + + SW0_B1_DONE + CPU b1 buffer done to PXP + 0x3 + 1 + read-only + + + SW0_BUF_LINES + Buffer lines for software handshake + 0x4 + 2 + read-only + + + LINE_4 + Buffer lines is 4 lines. + 0 + + + LINE_8 + Buffer lines is 8 lines. + 0x1 + + + LINE_16 + Buffer lines is 16 lines. + 0x2 + + + + + RSVD0 + Reserved, always set to zero. + 0x6 + 9 + read-only + + + SW0_HSK_EN + Enable software handshake 0 with CPU + 0xF + 1 + read-write + + + SW1_B0_READY + PXP b0 buffer ready to CPU + 0x10 + 1 + read-write + + + SW1_B1_READY + PXP b1 buffer ready to CPU + 0x11 + 1 + read-write + + + SW1_B0_DONE + CPU b0 buffer done to PXP + 0x12 + 1 + read-only + + + SW1_B1_DONE + CPU b1 buffer done to PXP + 0x13 + 1 + read-only + + + SW1_BUF_LINES + Buffer lines for software handshake + 0x14 + 2 + read-only + + + LINE_4 + Buffer lines is 4 lines. + 0 + + + LINE_8 + Buffer lines is 8 lines. + 0x1 + + + LINE_16 + Buffer lines is 16 lines. + 0x2 + + + + + RSVD1 + Reserved, always set to zero. + 0x16 + 9 + read-only + + + SW1_HSK_EN + Enable software handshake 1 with CPU + 0x1F + 1 + read-write + + + + + + + QuadSPI + QuadSPI + QUADSPI + QuadSPI_ + 0x21E0000 + + 0 + 0x410 + registers + + + QSPI + 139 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0xF4000 + 0xFFFFFFFF + + + SWRSTSD + Software reset for Serial Flash domainPlease keep other fields value when write to SWRSTHD and SWRSTSD These software reset don't reset register setting but only reset internal flip-flops in quadspi controller To remove the reset, need to write 0 to SWRSTHD and SWRSTSD + 0 + 1 + read-write + + + SWRSTSD_0 + No action + 0 + + + SWRSTSD_1 + Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. + 0x1 + + + + + SWRSTHD + Software reset for AHB domainPlease keep other fields value when write to SWRSTHD and SWRSTSD These software reset don't reset register setting but only reset internal flip-flops in quadspi controller To remove the reset, need to write 0 to SWRSTHD and SWRSTSD + 0x1 + 1 + read-write + + + SWRSTHD_0 + No action + 0 + + + SWRSTHD_1 + AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. + 0x1 + + + + + END_CFG + Defines the endianness of the QSPI module.For more details refer to Byte Ordering Endianess + 0x2 + 2 + read-write + + + DQS_EN + DQS enable: This field is valid for both SDR and DDR mode + 0x6 + 1 + read-write + + + DQS_EN_0 + DQS disabled. + 0 + + + DQS_EN_1 + DQS enabled- When enabled, the incoming data is sampled on both the edges of DQS input when QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored. + 0x1 + + + + + DDR_EN + DDR mode enable: + 0x7 + 1 + read-write + + + DDR_EN_0 + 2x and 4x clocks are disabled for SDR instructions only + 0 + + + DDR_EN_1 + 2x and 4x clocks are enabled supports both SDR and DDR instruction. + 0x1 + + + + + CLR_RXF + Clear RX FIFO. Invalidate the RX Buffer. + 0xA + 1 + read-write + + + CLR_RXF_0 + No action. + 0 + + + CLR_RXF_1 + Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0. + 0x1 + + + + + CLR_TXF + Clear TX FIFO/Buffer. Invalidate the TX Buffer content. + 0xB + 1 + read-write + + + CLR_TXF_0 + No action. + 0 + + + CLR_TXF_1 + Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0. + 0x1 + + + + + MDIS + Module Disable + 0xE + 1 + read-write + + + MDIS_0 + Enable QuadSPI clocks. + 0 + + + MDIS_1 + Allow external logic to disable QuadSPI clocks. + 0x1 + + + + + DQS_LOOPBACK_EN + Quadspi will output serial data strobe signal which will be loopback from pad to sample input flash serial data + 0x18 + 1 + read-write + + + DQS_PHASE_EN + This bit controls internal DQS output phase + 0x1E + 1 + read-write + + + + + IPCR + IP Configuration Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDATSZ + IP data transfer size: Defines the data transfer size in bytes of the IP command. + 0 + 16 + read-write + + + PAR_EN + When set, a transaction to two serial flash devices is triggered in parallel mode + 0x10 + 1 + read-write + + + SEQID + Points to a sequence in the Look-up-table + 0x18 + 4 + read-write + + + + + FLSHCR + Flash Configuration Register + 0xC + 32 + read-write + 0x303 + 0xFFFFFFFF + + + TCSS + Serial flash CS setup time in terms of serial flash clock cycles + 0 + 4 + read-write + + + TCSH + Serial flash CS hold time in terms of serial flash clock cycles + 0x8 + 4 + read-write + + + + + BUF0CR + Buffer0 Configuration Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER0 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash + 0x8 + 8 + read-write + + + HP_EN + High Priority Enable: When set, the master associated with this buffer is assigned a priority higher than the rest of the masters + 0x1F + 1 + read-write + + + + + BUF1CR + Buffer1 Configuration Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER1 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash + 0x8 + 8 + read-write + + + + + BUF2CR + Buffer2 Configuration Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER2 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 Bytes of an AHB triggered access to serial flash + 0x8 + 8 + read-write + + + + + BUF3CR + Buffer3 Configuration Register + 0x1C + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER3 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 Bytes of an AHB triggered access to serial flash + 0x8 + 8 + read-write + + + ALLMST + All master enable: When set, buffer3 acts as an all-master buffer + 0x1F + 1 + read-write + + + + + BFGENCR + Buffer Generic Configuration Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEQID + Points to a sequence in the Look-up-table + 0xC + 4 + read-write + + + PAR_EN + When set, a transaction to two serial flash devices is triggered in parallel mode + 0x10 + 1 + read-write + + + + + BUF0IND + Buffer0 Top Index Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPINDX0 + Top index of buffer 0. + 0x3 + 29 + read-write + + + + + BUF1IND + Buffer1 Top Index Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPINDX1 + Top index of buffer 1. + 0x3 + 29 + read-write + + + + + BUF2IND + Buffer2 Top Index Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPINDX2 + Top index of buffer 2. + 0x3 + 29 + read-write + + + + + SFAR + Serial Flash Address Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SFADR + Serial Flash Address. The register content is used as byte address for all following IP Commands. + 0 + 32 + read-write + + + + + SMPR + Sampling Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDRSMP + SDR sampling point. + 0x5 + 2 + read-write + + + DDRSMP + DDR Sampling point + 0x10 + 3 + read-write + + + + + RBSR + RX Buffer Status Register + 0x10C + 32 + read-only + 0 + 0xFFFFFFFF + + + RDBFL + RX Buffer Fill Level, indicates how many entries of 4 bytes are still available in the RX Buffer + 0x8 + 6 + read-only + + + RDCTR + Read Counter, indicates how many entries of 4 bytes have been removed from the RX Buffer + 0x10 + 16 + read-only + + + + + RBCT + RX Buffer Control Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + WMRK + RX Buffer Watermark: This field determines when the readout action of the RX Buffer is triggered + 0 + 5 + read-write + + + RXBRD + RX Buffer Readout: This bit specifies the access scheme for the RX Buffer readout. + 0x8 + 1 + read-write + + + RXBRD_0 + RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB31. For details, refer to Exclusive Access to Serial Flash for AHB Commands. + 0 + + + RXBRD_1 + RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR31. + 0x1 + + + + + + + TBSR + TX Buffer Status Register + 0x150 + 32 + read-only + 0 + 0xFFFFFFFF + + + TRBFL + TX Buffer Fill Level + 0x8 + 5 + read-only + + + TRCTR + Transmit Counter + 0x10 + 16 + read-only + + + + + TBDR + TX Buffer Data Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXDATA + TX Data On write access the data is written into the next available entry of the TX Buffer and the QPSI_TBSR[TRBFL] field is updated accordingly + 0 + 32 + read-write + + + + + SR + Status Register + 0x15C + 32 + read-only + 0x3800 + 0xFFFFFFFF + + + BUSY + Module Busy: Asserted when module is currently busy handling a transaction to an external flash device + 0 + 1 + read-only + + + IP_ACC + IP Access: Asserted when transaction currently executed was initiated by IP bus. + 0x1 + 1 + read-only + + + AHB_ACC + AHB Access: Asserted when the transaction currently executed was initiated by AHB bus. + 0x2 + 1 + read-only + + + AHBGNT + AHB Command priority Granted: Asserted when another module has been granted priority of AHB Commands against IP Commands + 0x5 + 1 + read-only + + + AHBTRN + AHB Access Transaction pending: Asserted when there is a pending request on the AHB interface + 0x6 + 1 + read-only + + + AHB0NE + AHB 0 Buffer Not Empty: Asserted when AHB 0 buffer contains data. + 0x7 + 1 + read-only + + + AHB1NE + AHB 1 Buffer Not Empty: Asserted when AHB 1 buffer contains data. + 0x8 + 1 + read-only + + + AHB2NE + AHB 2 Buffer Not Empty: Asserted when AHB 2 buffer contains data. + 0x9 + 1 + read-only + + + AHB3NE + AHB 3 Buffer Not Empty: Asserted when AHB 3 buffer contains data. + 0xA + 1 + read-only + + + AHB0FUL + AHB 0 Buffer Full: Asserted when AHB 0 buffer is full. + 0xB + 1 + read-only + + + AHB1FUL + AHB 1 Buffer Full: Asserted when AHB 1 buffer is full. + 0xC + 1 + read-only + + + AHB2FUL + AHB 2 Buffer Full: Asserted when AHB 2 buffer is full. + 0xD + 1 + read-only + + + AHB3FUL + AHB 3 Buffer Full: Asserted when AHB 3 buffer is full. + 0xE + 1 + read-only + + + RXWE + RX Buffer Watermark Exceeded: Asserted when the number of valid entries in the RX Buffer exceeds the number given in the QSPI_RBCT[WMRK] field + 0x10 + 1 + read-only + + + RXFULL + RX Buffer Full: Asserted when the RX Buffer is full, i + 0x13 + 1 + read-only + + + RXDMA + RX Buffer DMA: Asserted when RX Buffer read out via DMA is active i.e DMA is requested or running. + 0x17 + 1 + read-only + + + TXEDA + Tx Buffer Enough Data Available + 0x18 + 1 + read-only + + + TXFULL + TX Buffer Full: Asserted when no more data can be stored. + 0x1B + 1 + read-only + + + DLPSMP + Data learning is not implemented on this chip + 0x1D + 3 + read-only + + + + + FR + Flag Register + 0x160 + 32 + read-write + 0x8000000 + 0xFFFFFFFF + + + TFF + IP Command Transaction Finished Flag: Set when the QuadSPI module has finished a running IP Command + 0 + 1 + read-write + oneToClear + + + IPGEF + IP Command Trigger during AHB Grant Error Flag: Set when the following condition occurs: A write access occurs to the QSPI_IPCR[SEQID] field and the QSPI_SR[AHBGNT] bit is set + 0x4 + 1 + read-write + oneToClear + + + IPIEF + IP Command Trigger could not be executed Error Flag + 0x6 + 1 + read-write + oneToClear + + + IPAEF + IP Command Trigger during AHB Access Error Flag + 0x7 + 1 + read-write + oneToClear + + + IUEF + IP Command Usage Error Flag: Set when in parallel flash mode the execution of an IP Command is started and the sequence pointed to by the sequence ID contains a WRITE or a WRITE_DDR command + 0xB + 1 + read-write + oneToClear + + + ABOF + AHB Buffer Overflow Flag: Set when the size of the AHB access exceeds the size of the AHB buffer + 0xC + 1 + read-write + oneToClear + + + ABSEF + AHB Sequence Error Flag: Set when the execution of an AHB Command is started with an WRITE or WRITE_DDR Command in the sequence pointed to by the QSPI_BUFxCR QSPI_BUFxCR implies anyone of QSPI_BUF0CR/QSPI_BUF1CR/QSPI_BUF2CR/QSPI_BUF3CR register Communication with the serial flash device is terminated before the execution of WRITE/WRITE_DDR command by the QuadSPI module + 0xF + 1 + read-write + oneToClear + + + RBDF + RX Buffer Drain Flag: Will be set if the QuadSPI_SR[RXWE] status bit is asserted + 0x10 + 1 + read-write + oneToClear + + + RBOF + RX Buffer Overflow Flag: Set when not all the data read from the serial flash device could be pushed into the RX Buffer + 0x11 + 1 + read-write + oneToClear + + + ILLINE + Illegal Instruction Error Flag: Set when an illegal instruction is encountered by the controller in any of the sequences + 0x17 + 1 + read-write + oneToClear + + + TBUF + TX Buffer Underrun Flag: Set when the module tried to pull data although TX Buffer was emptyor the buffer contains less than 128bits of data + 0x1A + 1 + read-write + oneToClear + + + TBFF + TX Buffer Fill Flag: Before writing to the TX buffer, this bit should be cleared + 0x1B + 1 + read-write + oneToClear + + + DLPFF + Data learning is not implemented on this chip + 0x1F + 1 + read-write + oneToClear + + + + + RSER + Interrupt and DMA Request Select and Enable Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFIE + Transaction Finished Interrupt Enable + 0 + 1 + read-write + + + TFIE_0 + No TFF interrupt will be generated + 0 + + + TFIE_1 + TFF interrupt will be generated + 0x1 + + + + + IPGEIE + IP Command Trigger during AHB Grant Error Interrupt Enable + 0x4 + 1 + read-write + + + IPGEIE_0 + No IPGEF interrupt will be generated + 0 + + + IPGEIE_1 + IPGEF interrupt will be generated + 0x1 + + + + + IPIEIE + IP Command Trigger during IP Access Error Interrupt Enable + 0x6 + 1 + read-write + + + IPIEIE_0 + No IPIEF interrupt will be generated + 0 + + + + + IPAEIE + IP Command Trigger during AHB Access Error Interrupt Enable + 0x7 + 1 + read-write + + + IPAEIE_0 + No IPAEF interrupt will be generated + 0 + + + IPAEIE_1 + IPAEF interrupt will be generated + 0x1 + + + + + IUEIE + IP Command Usage Error Interrupt Enable + 0xB + 1 + read-write + + + IUEIE_0 + No IUEF interrupt will be generated + 0 + + + IUEIE_1 + IUEF interrupt will be generated + 0x1 + + + + + ABOIE + AHB Buffer Overflow Interrupt Enable + 0xC + 1 + read-write + + + ABOIE_0 + No ABOF interrupt will be generated + 0 + + + ABOIE_1 + ABOF interrupt will be generated + 0x1 + + + + + ABSEIE + AHB Sequence Error Interrupt Enable: Triggered by ABSEF flags of QSPI_FR + 0xF + 1 + read-write + + + ABSEIE_0 + No ABSEF interrupt will be generated + 0 + + + ABSEIE_1 + ABSEF interrupt will be generated + 0x1 + + + + + RBDIE + RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain + 0x10 + 1 + read-write + + + RBDIE_0 + No RBDF interrupt will be generated + 0 + + + RBDIE_1 + RBDF Interrupt will be generated + 0x1 + + + + + RBOIE + RX Buffer Overflow Interrupt Enable + 0x11 + 1 + read-write + + + RBOIE_0 + No RBOF interrupt will be generated + 0 + + + RBOIE_1 + RBOF interrupt will be generated + 0x1 + + + + + RBDDE + RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain + 0x15 + 1 + read-write + + + RBDDE_0 + No DMA request will be generated + 0 + + + RBDDE_1 + DMA request will be generated + 0x1 + + + + + ILLINIE + Illegal Instruction Error Interrupt Enable. Triggered by ILLINE flag in QSPI_FR + 0x17 + 1 + read-write + + + ILLINIE_0 + No ILLINE interrupt will be generated + 0 + + + ILLINIE_1 + ILLINE interrupt will be generated + 0x1 + + + + + TBUIE + TX Buffer Underrun Interrupt Enable + 0x1A + 1 + read-write + + + TBUIE_0 + No TBUF interrupt will be generated + 0 + + + TBUIE_1 + TBUF interrupt will be generated + 0x1 + + + + + TBFIE + TX Buffer Fill Interrupt Enable + 0x1B + 1 + read-write + + + TBFIE_0 + No TBFF interrupt will be generated + 0 + + + TBFIE_1 + TBFF interrupt will be generated + 0x1 + + + + + DLPFIE + Data learning is not implemented on this chip + 0x1F + 1 + read-write + + + DLPFIE_0 + No DLPFF interrupt will be generated + 0 + + + DLPFIE_1 + DLPFF interrupt will be generated + 0x1 + + + + + + + SPNDST + Sequence Suspend Status Register + 0x168 + 32 + read-only + 0 + 0xFFFFFFFF + + + SUSPND + When set, it signifies that a sequence is in suspended state + 0 + 1 + read-only + + + SPDBUF + Suspended Buffer: Provides the suspended buffer number. Valid only when SUSPND is set to 1'b1 + 0x6 + 2 + read-only + + + DATLFT + Data left: Provides information about the amount of data left to be read in the suspended sequence + 0x9 + 7 + read-only + + + + + SPTRCLR + Sequence Pointer Clear Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + BFPTRC + Buffer Pointer Clear: 1: Clears the sequence pointer for AHB accesses as defined in QuadSPI_BFGENCR + 0 + 1 + read-write + + + IPPTRC + IP Pointer Clear: 1: Clears the sequence pointer for IP accesses as defined in QuadSPI_IPCR + 0x8 + 1 + read-write + + + + + SFA1AD + Serial Flash A1 Top Address + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADA1 + Top address for Serial Flash A1. In effect, TPADxx is the first location of the next memory. + 0xA + 22 + read-write + + + + + SFA2AD + Serial Flash A2 Top Address + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADA2 + Top address for Serial Flash A2. In effect, TPxxAD is the first location of the next memory. + 0xA + 22 + read-write + + + + + SFB1AD + Serial Flash B1Top Address + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADB1 + Top address for Serial Flash B1.In effect, TPxxAD is the first location of the next memory. + 0xA + 22 + read-write + + + + + SFB2AD + Serial Flash B2Top Address + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADB2 + Top address for Serial Flash B2. In effect, TPxxAD is the first location of the next memory. + 0xA + 22 + read-write + + + + + 32 + 0x4 + RBDR%s + RX Buffer Data Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXDATA + RX Data + 0 + 32 + read-write + + + + + LUTKEY + LUT Key Register + 0x300 + 32 + read-write + 0x5AF05AF0 + 0xFFFFFFFF + + + KEY + The key to lock or unlock the LUT. The KEY is 0x5AF05AF0. The read value is always 0x5AF05AF0 + 0 + 32 + read-write + + + + + LCKCR + LUT Lock Configuration Register + 0x304 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOCK + Locks the LUT when the following condition is met: This register is written just after the LUTKEYLUT Key Register The LUT key register was written with 0x5AF05AF0 key + 0 + 1 + read-write + + + UNLOCK + Unlocks the LUT when the following two conditions are met: 1 + 0x1 + 1 + read-write + + + + + LUT0 + Look-up Table register + 0x310 + 32 + read-write + 0x8180403 + 0xFFFFFFFF + + + OPRND0 + Operand for INSTR0. + 0 + 8 + read-write + + + PAD0 + Pad information for INSTR0. + 0x8 + 2 + read-write + + + PAD0_0 + 1 Pad + 0 + + + PAD0_1 + 2 Pads + 0x1 + + + PAD0_2 + 4 Pads + 0x2 + + + PAD0_3 + NA + 0x3 + + + + + INSTR0 + Instruction 0 + 0xA + 6 + read-write + + + OPRND1 + Operand for INSTR1. + 0x10 + 8 + read-write + + + PAD1 + Pad information for INSTR1. + 0x18 + 2 + read-write + + + PAD1_0 + 1 Pad + 0 + + + PAD1_1 + 2 Pads + 0x1 + + + PAD1_2 + 4 Pads + 0x2 + + + PAD1_3 + NA + 0x3 + + + + + INSTR1 + Instruction 1 + 0x1A + 6 + read-write + + + + + LUT1 + Look-up Table register + 0x314 + 32 + read-write + 0x24001C08 + 0xFFFFFFFF + + + OPRND0 + Operand for INSTR0. + 0 + 8 + read-write + + + PAD0 + Pad information for INSTR0. + 0x8 + 2 + read-write + + + PAD0_0 + 1 Pad + 0 + + + PAD0_1 + 2 Pads + 0x1 + + + PAD0_2 + 4 Pads + 0x2 + + + PAD0_3 + NA + 0x3 + + + + + INSTR0 + Instruction 0 + 0xA + 6 + read-write + + + OPRND1 + Operand for INSTR1. + 0x10 + 8 + read-write + + + PAD1 + Pad information for INSTR1. + 0x18 + 2 + read-write + + + PAD1_0 + 1 Pad + 0 + + + PAD1_1 + 2 Pads + 0x1 + + + PAD1_2 + 4 Pads + 0x2 + + + PAD1_3 + NA + 0x3 + + + + + INSTR1 + Instruction 1 + 0x1A + 6 + read-write + + + + + 62 + 0x4 + 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 + LUT%s + Look-up Table register + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPRND0 + Operand for INSTR0. + 0 + 8 + read-write + + + PAD0 + Pad information for INSTR0. + 0x8 + 2 + read-write + + + PAD0_0 + 1 Pad + 0 + + + PAD0_1 + 2 Pads + 0x1 + + + PAD0_2 + 4 Pads + 0x2 + + + PAD0_3 + NA + 0x3 + + + + + INSTR0 + Instruction 0 + 0xA + 6 + read-write + + + OPRND1 + Operand for INSTR1. + 0x10 + 8 + read-write + + + PAD1 + Pad information for INSTR1. + 0x18 + 2 + read-write + + + PAD1_0 + 1 Pad + 0 + + + PAD1_1 + 2 Pads + 0x1 + + + PAD1_2 + 4 Pads + 0x2 + + + PAD1_3 + NA + 0x3 + + + + + INSTR1 + Instruction 1 + 0x1A + 6 + read-write + + + + + + + DCP + DCP register reference index + DCP + DCP_ + 0x2280000 + + 0 + 0x434 + registers + + + DCP_IRQ + 78 + + + DCP_VMI_IRQ + 79 + + + DCP_SEC_IRQ + 80 + + + + CTRL + DCP control register 0 + 0 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x4 + + + CH3 + no description available + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 0x15 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 0x16 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 0x17 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 0x1C + 1 + read-only + + + Absent + no description available + 0 + + + Present + no description available + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 0x1D + 1 + read-only + + + Absent + no description available + 0 + + + Present + no description available + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 0x1F + 1 + read-write + + + + + STAT + DCP status register + 0x10 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 0x10 + 8 + read-only + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x4 + + + CH3 + no description available + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 0x18 + 4 + read-only + + + None + no description available + 0 + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x3 + + + CH3 + no description available + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 0x1C + 1 + read-only + + + + + CHANNELCTRL + DCP channel control register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x4 + + + CH3 + no description available + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 0x8 + 8 + read-write + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x4 + + + CH3 + no description available + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 0x10 + 1 + read-write + + + + + CAPABILITY0 + DCP capability 0 register + 0x30 + 32 + read-write + 0x404 + 0xFFFFFFFF + + + NUM_KEYS + Encoded value indicating the number of key-storage locations implemented in the design + 0 + 8 + read-only + + + NUM_CHANNELS + Encoded value indicating the number of channels implemented in the design + 0x8 + 4 + read-only + + + DISABLE_UNIQUE_KEY + Write to a 1 to disable the per-device unique key + 0x1D + 1 + read-write + + + DISABLE_DECRYPT + Write to 1 to disable the decryption + 0x1F + 1 + read-write + + + + + CAPABILITY1 + DCP capability 1 register + 0x40 + 32 + read-only + 0x70001 + 0xFFFFFFFF + + + CIPHER_ALGORITHMS + One-hot field indicating which cipher algorithms are available + 0 + 16 + read-only + + + AES128 + no description available + 0x1 + + + + + HASH_ALGORITHMS + One-hot field indicating which hashing features are implemented in the hardware + 0x10 + 16 + read-only + + + SHA1 + no description available + 0x1 + + + CRC32 + no description available + 0x2 + + + SHA256 + no description available + 0x4 + + + + + + + CONTEXT + DCP context buffer pointer + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Context pointer address + 0 + 32 + read-write + + + + + KEY + DCP key index + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SUBWORD + Key subword pointer + 0 + 2 + read-write + + + INDEX + Key index pointer. The valid indices are 0-[number_keys]. + 0x4 + 2 + read-write + + + + + KEYDATA + DCP key data + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Word 0 data for the key. This is the least-significant word. + 0 + 32 + read-write + + + + + PACKET0 + DCP work packet 0 status register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Next pointer register + 0 + 32 + read-only + + + + + PACKET1 + DCP work packet 1 status register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + INTERRUPT + Reflects whether the channel must issue an interrupt upon the completion of the packet. + 0 + 1 + read-only + + + DECR_SEMAPHORE + Reflects whether the channel's semaphore must be decremented at the end of the current operation + 0x1 + 1 + read-only + + + CHAIN + Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer + 0x2 + 1 + read-only + + + CHAIN_CONTIGUOUS + Reflects whether the next packet's address is located following this packet's payload. + 0x3 + 1 + read-only + + + ENABLE_MEMCOPY + Reflects whether the selected hashing function should be enabled for this operation. + 0x4 + 1 + read-only + + + ENABLE_CIPHER + Reflects whether the selected cipher function must be enabled for this operation. + 0x5 + 1 + read-only + + + ENABLE_HASH + Reflects whether the selected hashing function must be enabled for this operation. + 0x6 + 1 + read-only + + + ENABLE_BLIT + Reflects whether the DCP must perform a blit operation + 0x7 + 1 + read-only + + + CIPHER_ENCRYPT + When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption + 0x8 + 1 + read-only + + + DECRYPT + no description available + 0 + + + ENCRYPT + no description available + 0x1 + + + + + CIPHER_INIT + Reflects whether the cipher block must load the initialization vector from the payload for this operation + 0x9 + 1 + read-only + + + OTP_KEY + Reflects whether a hardware-based key must be used + 0xA + 1 + read-only + + + PAYLOAD_KEY + When set, it indicates the payload contains the key + 0xB + 1 + read-only + + + HASH_INIT + Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation + 0xC + 1 + read-only + + + HASH_TERM + Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware + 0xD + 1 + read-only + + + CHECK_HASH + Reflects whether the calculated hash value must be compared to the hash provided in the payload. + 0xE + 1 + read-only + + + HASH_OUTPUT + When the hashing is enabled, this bit controls whether the input or output data is hashed. + 0xF + 1 + read-only + + + INPUT + no description available + 0 + + + OUTPUT + no description available + 0x1 + + + + + CONSTANT_FILL + When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field + 0x10 + 1 + read-only + + + TEST_SEMA_IRQ + This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY! + 0x11 + 1 + read-only + + + KEY_BYTESWAP + Reflects whether the DCP engine swaps the key bytes (big-endian key). + 0x12 + 1 + read-only + + + KEY_WORDSWAP + Reflects whether the DCP engine swaps the key words (big-endian key). + 0x13 + 1 + read-only + + + INPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the input data (big-endian data). + 0x14 + 1 + read-only + + + INPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the input data (big-endian data). + 0x15 + 1 + read-only + + + OUTPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the output data (big-endian data). + 0x16 + 1 + read-only + + + OUTPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the output data (big-endian data). + 0x17 + 1 + read-only + + + TAG + Packet Tag + 0x18 + 8 + read-only + + + + + PACKET2 + DCP work packet 2 status register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIPHER_SELECT + Cipher selection field + 0 + 4 + read-only + + + AES128 + no description available + 0 + + + + + CIPHER_MODE + Cipher mode selection field. Reflects the mode of operation for the cipher operations. + 0x4 + 4 + read-only + + + ECB + no description available + 0 + + + CBC + no description available + 0x1 + + + + + KEY_SELECT + Key selection field + 0x8 + 8 + read-only + + + KEY0 + no description available + 0 + + + KEY1 + no description available + 0x1 + + + KEY2 + no description available + 0x2 + + + KEY3 + no description available + 0x3 + + + UNIQUE_KEY + no description available + 0xFE + + + OTP_KEY + no description available + 0xFF + + + + + HASH_SELECT + Hash Selection Field + 0x10 + 4 + read-only + + + SHA1 + no description available + 0 + + + CRC32 + no description available + 0x1 + + + SHA256 + no description available + 0x2 + + + + + CIPHER_CFG + Cipher configuration bits. Optional configuration bits are required for the ciphers. + 0x18 + 8 + read-only + + + + + PACKET3 + DCP work packet 3 status register + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Source buffer address pointer + 0 + 32 + read-only + + + + + PACKET4 + DCP work packet 4 status register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Destination buffer address pointer + 0 + 32 + read-only + + + + + PACKET5 + DCP work packet 5 status register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Byte count register. This value is the working value and updates as the operation proceeds. + 0 + 32 + read-only + + + + + PACKET6 + DCP work packet 6 status register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + This regiser reflects the payload pointer for the current control packet. + 0 + 32 + read-only + + + + + CH0CMDPTR + DCP channel 0 command pointer address register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 0. + 0 + 32 + read-write + + + + + CH0SEMA + DCP channel 0 semaphore register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + CH0STAT + DCP channel 0 status register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 0x1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 0x2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 0x3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 0x4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 0x5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 0x6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 0x10 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 0x18 + 8 + read-only + + + + + CH0OPTS + DCP channel 0 options register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1CMDPTR + DCP channel 1 command pointer address register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 1. + 0 + 32 + read-write + + + + + CH1SEMA + DCP channel 1 semaphore register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + CH1STAT + DCP channel 1 status register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 0x1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 0x2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 0x3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 0x4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 0x5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 0x6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 0x10 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 0x18 + 8 + read-only + + + + + CH1OPTS + DCP channel 1 options register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2CMDPTR + DCP channel 2 command pointer address register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 2. + 0 + 32 + read-write + + + + + CH2SEMA + DCP channel 2 semaphore register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + CH2STAT + DCP channel 2 status register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 0x1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 0x2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 0x3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 0x4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 0x5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 0x6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 0x10 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 0x18 + 8 + read-only + + + + + CH2OPTS + DCP channel 2 options register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3CMDPTR + DCP channel 3 command pointer address register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 3. + 0 + 32 + read-write + + + + + CH3SEMA + DCP channel 3 semaphore register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + CH3STAT + DCP channel 3 status register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 0x1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 0x2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 0x3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 0x4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 0x5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 0x6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 0x10 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 0x18 + 8 + read-only + + + + + CH3OPTS + DCP channel 3 options register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + DBGSELECT + DCP debug select register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + INDEX + Selects a value to read via the debug data register. + 0 + 8 + read-write + + + CONTROL + no description available + 0x1 + + + OTPKEY0 + no description available + 0x10 + + + OTPKEY1 + no description available + 0x11 + + + OTPKEY2 + no description available + 0x12 + + + OTPKEY3 + no description available + 0x13 + + + + + + + DBGDATA + DCP debug data register + 0x410 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Debug data + 0 + 32 + read-only + + + + + PAGETABLE + DCP page table register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Page table enable control + 0 + 1 + read-write + + + FLUSH + Page table flush control. To flush the TLB, write this bit to 1 and then back to 0. + 0x1 + 1 + read-write + + + BASE + Page table base address + 0x2 + 30 + read-write + + + + + VERSION + DCP version register + 0x430 + 32 + read-only + 0x2010000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the version of the design implementation. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR version of the design implementation. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR version of the design implementation. + 0x18 + 8 + read-only + + + + + + + RNG + Random number generator + RNG + RNG_ + 0x2284000 + + 0 + 0x18 + registers + + + RNGB + 38 + + + + VER + RNGB version ID register + 0 + 32 + read-only + 0x10000280 + 0xFFFFFFFF + + + MINOR + Minor version number + 0 + 8 + read-only + + + MAJOR + Major version number + 0x8 + 8 + read-only + + + TYPE + Random number generator type + 0x1C + 4 + read-only + + + TYPE_0 + RNGA + 0 + + + TYPE_1 + RNGB (This is the type used in this module.) + 0x1 + + + TYPE_2 + RNGC + 0x2 + + + + + + + CMD + RNGB command register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ST + Self test + 0 + 1 + read-write + + + ST_0 + Not in the self-test mode + 0 + + + ST_1 + Self-test mode + 0x1 + + + + + GS + Generate the seed. + 0x1 + 1 + read-write + + + GS_0 + Not in the seed generation mode + 0 + + + GS_1 + Generate the seed mode. + 0x1 + + + + + CI + Clear the interrupt. + 0x4 + 1 + write-only + + + CI_0 + Do not clear the interrupt. + 0 + + + CI_1 + Clear the interrupt. + 0x1 + + + + + CE + Clear the error. + 0x5 + 1 + write-only + + + CE_0 + Do not clear the errors and the interrupt. + 0 + + + CE_1 + Clear the errors and the interrupt. + 0x1 + + + + + SR + Software reset + 0x6 + 1 + write-only + + + SR_0 + Do not perform a software reset. + 0 + + + SR_1 + Software reset + 0x1 + + + + + + + CR + RNGB control register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FUFMOD + FIFO underflow response mode + 0 + 2 + read-write + + + FUFMOD_0 + Return all zeros and set the RNG_ESR[FUFE]. + 0 + + + FUFMOD_1 + Return all zeros and set the RNG_ESR[FUFE]. + 0x1 + + + FUFMOD_2 + Generate the bus transfer error + 0x2 + + + FUFMOD_3 + Generate the interrupt and return all zeros (overrides the RNG_CR[MASKERR]). + 0x3 + + + + + AR + Auto-reseed + 0x4 + 1 + read-write + + + AR_0 + Do not enable the automatic reseeding. + 0 + + + AR_1 + Enable the automatic reseeding. + 0x1 + + + + + MASKDONE + Mask the interrupt done. + 0x5 + 1 + read-write + + + MASKDONE_0 + No mask is applied. + 0 + + + MASKDONE_1 + The mask is applied. + 0x1 + + + + + MASKERR + Mask the error interrupt. + 0x6 + 1 + read-write + + + MASKERR_0 + No mask is applied. + 0 + + + MASKERR_1 + The mask applied to the error interrupt + 0x1 + + + + + + + SR + RNGB status register + 0xC + 32 + read-only + 0x500D + 0xFFFFFFFF + + + BUSY + Busy. + 0x1 + 1 + read-only + + + BUSY_0 + Not busy + 0 + + + BUSY_1 + Busy + 0x1 + + + + + SLP + Sleep + 0x2 + 1 + read-only + + + SLP_0 + The RNGB is not in the sleep mode. + 0 + + + SLP_1 + The RNGB is in the sleep mode. + 0x1 + + + + + RS + Reseed needed + 0x3 + 1 + read-only + + + RS_0 + The RNGB does not need to be reseeded. + 0 + + + RS_1 + The RNGB needs to be reseeded. + 0x1 + + + + + STDN + Self test done + 0x4 + 1 + read-only + + + STDN_0 + Self test not completed + 0 + + + STDN_1 + Completed a self test since the last reset + 0x1 + + + + + SDN + Seed done + 0x5 + 1 + read-only + + + SDN_0 + The seed-generation process is not complete. + 0 + + + SDN_1 + Completed the seed generation since the last reset + 0x1 + + + + + NSDN + New seed done + 0x6 + 1 + read-only + + + FIFO_LVL + FIFO level + 0x8 + 4 + read-only + + + FIFO_SIZE + FIFO size + 0xC + 4 + read-only + + + ERR + Error + 0x10 + 1 + read-only + + + ERR_0 + No error + 0 + + + ERR_1 + Error detected + 0x1 + + + + + ST_PF + Self-test pass fail + 0x15 + 3 + read-only + + + ST_PF_0 + Pass + 0 + + + ST_PF_1 + Fail + 0x1 + + + + + STATPF + Statistics test pass failed. + 0x18 + 8 + read-only + + + STATPF_0 + Pass + 0 + + + STATPF_1 + Fail + 0x1 + + + + + + + ESR + RNGB error status register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + LFE + Linear feedback shift register (LFSR) error + 0 + 1 + read-only + + + LFE_0 + The LFSRs are working properly. + 0 + + + LFE_1 + The LFSR failure occurred. + 0x1 + + + + + OSCE + Oscillator error + 0x1 + 1 + read-only + + + OSCE_0 + The RNG oscillator is working properly. + 0 + + + OSCE_1 + A problem with the RNG oscillator was detected. + 0x1 + + + + + STE + Self-test error + 0x2 + 1 + read-only + + + STE_0 + The RNGB did not fail the self test. + 0 + + + STE_1 + The RNGB failed the self test. + 0x1 + + + + + SATE + Statistical test error + 0x3 + 1 + read-only + + + SATE_0 + The RNGB did not fail the statistical tests. + 0 + + + SATE_1 + The RNGB failed the statistical tests during the initialization. + 0x1 + + + + + FUFE + FIFO underflow error + 0x4 + 1 + read-only + + + FUFE_0 + FIFO underflow did not occur. + 0 + + + FUFE_1 + FIFO underflow occurred. + 0x1 + + + + + + + OUT + RNGB Output FIFO + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RANDOUT + Random output + 0 + 32 + read-only + + + + + + + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS_ + 0x2290000 + + 0 + 0x74 + registers + + + + SW_MUX_CTL_PAD_BOOT_MODE0 + SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO10 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad BOOT_MODE0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_BOOT_MODE1 + SW_MUX_CTL_PAD_BOOT_MODE1 SW MUX Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO11 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad BOOT_MODE1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER0 + SW_MUX_CTL_PAD_SNVS_TAMPER0 SW MUX Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER1 + SW_MUX_CTL_PAD_SNVS_TAMPER1 SW MUX Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER2 + SW_MUX_CTL_PAD_SNVS_TAMPER2 SW MUX Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER3 + SW_MUX_CTL_PAD_SNVS_TAMPER3 SW MUX Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + Mux Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO03 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER4 + SW_MUX_CTL_PAD_SNVS_TAMPER4 SW MUX Control Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO04 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER4 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER5 + SW_MUX_CTL_PAD_SNVS_TAMPER5 SW MUX Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO05 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER5 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER6 + SW_MUX_CTL_PAD_SNVS_TAMPER6 SW MUX Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO06 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER6 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER7 + SW_MUX_CTL_PAD_SNVS_TAMPER7 SW MUX Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO07 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER7 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER8 + SW_MUX_CTL_PAD_SNVS_TAMPER8 SW MUX Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO08 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER8 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER9 + SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO09 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER9 + 0x1 + + + + + + + SW_PAD_CTL_PAD_TEST_MODE + SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register + 0x30 + 32 + read-write + 0x30A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_POR_B + SW_PAD_CTL_PAD_POR_B SW PAD Control Register + 0x34 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ONOFF + SW_PAD_CTL_PAD_ONOFF SW PAD Control Register + 0x38 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ + SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ SW PAD Control Register + 0x3C + 32 + read-write + 0xB8A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ + SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ SW PAD Control Register + 0x40 + 32 + read-write + 0x20A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_BOOT_MODE0 + SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register + 0x44 + 32 + read-write + 0x130A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_BOOT_MODE1 + SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control Register + 0x48 + 32 + read-write + 0x130A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER0 + SW_PAD_CTL_PAD_SNVS_TAMPER0 SW PAD Control Register + 0x4C + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER1 + SW_PAD_CTL_PAD_SNVS_TAMPER1 SW PAD Control Register + 0x50 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER2 + SW_PAD_CTL_PAD_SNVS_TAMPER2 SW PAD Control Register + 0x54 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER3 + SW_PAD_CTL_PAD_SNVS_TAMPER3 SW PAD Control Register + 0x58 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER4 + SW_PAD_CTL_PAD_SNVS_TAMPER4 SW PAD Control Register + 0x5C + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER5 + SW_PAD_CTL_PAD_SNVS_TAMPER5 SW PAD Control Register + 0x60 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER6 + SW_PAD_CTL_PAD_SNVS_TAMPER6 SW PAD Control Register + 0x64 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER7 + SW_PAD_CTL_PAD_SNVS_TAMPER7 SW PAD Control Register + 0x68 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER8 + SW_PAD_CTL_PAD_SNVS_TAMPER8 SW PAD Control Register + 0x6C + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER9 + SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register + 0x70 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2_features.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2_features.h new file mode 100644 index 0000000000000000000000000000000000000000..15180c2bddd00714ee31070b9ceab615b9d4bb7b --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2_features.h @@ -0,0 +1,801 @@ +/* +** ################################################################### +** Version: rev. 3.0, 2017-02-28 +** Build: b170422 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-12-18) +** Initial version. +** - rev. 2.0 (2016-08-02) +** Rev.B Header GA +** - rev. 3.0 (2017-02-28) +** Rev.1 Header GA +** +** ################################################################### +*/ + +#ifndef _MCIMX6Y2_FEATURES_H_ +#define _MCIMX6Y2_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (0) +/* @brief ADC_5HC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_5HC_COUNT (1) +/* @brief AES availability on the SoC. */ +#define FSL_FEATURE_SOC_AES_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AGC availability on the SoC. */ +#define FSL_FEATURE_SOC_AGC_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (3) +/* @brief ANATOP availability on the SoC. */ +#define FSL_FEATURE_SOC_ANATOP_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief APBH availability on the SoC. */ +#define FSL_FEATURE_SOC_APBH_COUNT (1) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief ASRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASRC_COUNT (1) +/* @brief ASYNC_SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0) +/* @brief ATX availability on the SoC. */ +#define FSL_FEATURE_SOC_ATX_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief BCH availability on the SoC. */ +#define FSL_FEATURE_SOC_BCH_COUNT (1) +/* @brief BLEDP availability on the SoC. */ +#define FSL_FEATURE_SOC_BLEDP_COUNT (0) +/* @brief BOD availability on the SoC. */ +#define FSL_FEATURE_SOC_BOD_COUNT (0) +/* @brief CAAM availability on the SoC. */ +#define FSL_FEATURE_SOC_CAAM_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief CALIB availability on the SoC. */ +#define FSL_FEATURE_SOC_CALIB_COUNT (0) +/* @brief CAN availability on the SoC. */ +#define FSL_FEATURE_SOC_CAN_COUNT (0) +/* @brief CAU availability on the SoC. */ +#define FSL_FEATURE_SOC_CAU_COUNT (0) +/* @brief CAU3 availability on the SoC. */ +#define FSL_FEATURE_SOC_CAU3_COUNT (0) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief CHRG availability on the SoC. */ +#define FSL_FEATURE_SOC_CHRG_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (0) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief COP availability on the SoC. */ +#define FSL_FEATURE_SOC_COP_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0) +/* @brief CS availability on the SoC. */ +#define FSL_FEATURE_SOC_CS_COUNT (0) +/* @brief CSI availability on the SoC. */ +#define FSL_FEATURE_SOC_CSI_COUNT (1) +/* @brief CT32B availability on the SoC. */ +#define FSL_FEATURE_SOC_CT32B_COUNT (0) +/* @brief CTI availability on the SoC. */ +#define FSL_FEATURE_SOC_CTI_COUNT (0) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (0) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (0) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0) +/* @brief DCP availability on the SoC. */ +#define FSL_FEATURE_SOC_DCP_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DDRC availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_COUNT (0) +/* @brief DDRC_MP availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0) +/* @brief DDR_PHY availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (0) +/* @brief DMIC availability on the SoC. */ +#define FSL_FEATURE_SOC_DMIC_COUNT (0) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (0) +/* @brief ECSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_ECSPI_COUNT (4) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (0) +/* @brief EEPROM availability on the SoC. */ +#define FSL_FEATURE_SOC_EEPROM_COUNT (0) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EMC availability on the SoC. */ +#define FSL_FEATURE_SOC_EMC_COUNT (0) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (2) +/* @brief EPDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EPDC_COUNT (0) +/* @brief EPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_EPIT_COUNT (2) +/* @brief ESAI availability on the SoC. */ +#define FSL_FEATURE_SOC_ESAI_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (0) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FLEXRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXRAM_COUNT (0) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FSP availability on the SoC. */ +#define FSL_FEATURE_SOC_FSP_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (0) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (0) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (1) +/* @brief GPC_PGC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (0) +/* @brief GPMI availability on the SoC. */ +#define FSL_FEATURE_SOC_GPMI_COUNT (1) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (2) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (0) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (3) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief IEE availability on the SoC. */ +#define FSL_FEATURE_SOC_IEE_COUNT (0) +/* @brief IEER availability on the SoC. */ +#define FSL_FEATURE_SOC_IEER_COUNT (0) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (5) +/* @brief II2C availability on the SoC. */ +#define FSL_FEATURE_SOC_II2C_COUNT (4) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (0) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (1) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief IOMUXC_LPSR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0) +/* @brief IOMUXC_LPSR_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0) +/* @brief IOMUXC_SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) +/* @brief IPWM availability on the SoC. */ +#define FSL_FEATURE_SOC_IPWM_COUNT (8) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief IUART availability on the SoC. */ +#define FSL_FEATURE_SOC_IUART_COUNT (8) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief KPP availability on the SoC. */ +#define FSL_FEATURE_SOC_KPP_COUNT (1) +/* @brief L2CACHEC availability on the SoC. */ +#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0) +/* @brief LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (1) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (0) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (0) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (0) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (0) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (0) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (0) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (0) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (0) +/* @brief MIPI_CSI2 availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0) +/* @brief MIPI_DSI availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0) +/* @brief MIPI_DSI_HOST availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief MMDC availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDC_COUNT (1) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (0) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PCIE_PHY_CMN availability on the SoC. */ +#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0) +/* @brief PCIE_PHY_TRSV availability on the SoC. */ +#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (0) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (0) +/* @brief PMU availability on the SoC. */ +#define FSL_FEATURE_SOC_PMU_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (0) +/* @brief PROP availability on the SoC. */ +#define FSL_FEATURE_SOC_PROP_COUNT (0) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief PXP availability on the SoC. */ +#define FSL_FEATURE_SOC_PXP_COUNT (1) +/* @brief QDEC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDEC_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (1) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (0) +/* @brief RDC availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_COUNT (0) +/* @brief RDC_SEMAPHORE availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (0) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RIT availability on the SoC. */ +#define FSL_FEATURE_SOC_RIT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (1) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (0) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (0) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (0) +/* @brief SDIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIO_COUNT (0) +/* @brief SDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMA_COUNT (1) +/* @brief SDMAARM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMAARM_COUNT (0) +/* @brief SDMABP availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMABP_COUNT (0) +/* @brief SDMACORE availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMACORE_COUNT (0) +/* @brief SDMCORE availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMCORE_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA4 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA4_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SHA availability on the SoC. */ +#define FSL_FEATURE_SOC_SHA_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (0) +/* @brief SIMDGO availability on the SoC. */ +#define FSL_FEATURE_SOC_SIMDGO_COUNT (0) +/* @brief SJC availability on the SoC. */ +#define FSL_FEATURE_SOC_SJC_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief SMARTCARD availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (0) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1) +/* @brief SPBA availability on the SoC. */ +#define FSL_FEATURE_SOC_SPBA_COUNT (1) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0) +/* @brief SPIFI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPIFI_COUNT (0) +/* @brief SPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SPM_COUNT (0) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (0) +/* @brief TEMPMON availability on the SoC. */ +#define FSL_FEATURE_SOC_TEMPMON_COUNT (1) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (0) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0) +/* @brief TSC availability on the SoC. */ +#define FSL_FEATURE_SOC_TSC_COUNT (1) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (0) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (0) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (2) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (0) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (0) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (2) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (2) +/* @brief USB_HSIC availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0) +/* @brief USB_OTG availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_OTG_COUNT (0) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (2) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (0) +/* @brief VIU availability on the SoC. */ +#define FSL_FEATURE_SOC_VIU_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (0) +/* @brief VFIFO availability on the SoC. */ +#define FSL_FEATURE_SOC_VFIFO_COUNT (0) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (3) +/* @brief WKPU availability on the SoC. */ +#define FSL_FEATURE_SOC_WKPU_COUNT (0) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief XTALOSC availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC_COUNT (0) +/* @brief XTALOSC24M availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0) + +/* ADC module features */ + +/* @brief Remove Hardware Trigger feature. */ +#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (1) +/* @brief Remove ALT Clock selection feature. */ +#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) + +/* CACHEC module features */ + +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (64) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) +/* @brief Has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0) +/* @brief Has extra MB interrupt or common one. */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (0) + +/* ECSPI module features */ + +/* @brief ECSPI Tx FIFO Size. */ +#define FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(x) (64) + +/* ENET module features */ + +/* @brief Support Interrupt Coalesce */ +#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) +/* @brief Queue Size. */ +#define FSL_FEATURE_ENET_QUEUE (1) +/* @brief Has AVB Support. */ +#define FSL_FEATURE_ENET_HAS_AVB (0) +/* @brief Has Timer Pulse Width control. */ +#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1) +/* @brief Has Extend MDIO Support. */ +#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) +/* @brief Has Additional 1588 Timer Channel Interrupt. */ +#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1) + +/* ESAI module features */ + +/* @brief ESAI FIFO Size. */ +#define FSL_FEATURE_ESAI_FIFO_SIZEn(x) (128) + +/* GPC module features */ + +/* @brief Has No DVFS0 Change Request. */ +#define FSL_FEATURE_GPC_HAS_NO_CNTR_DVFS0CR (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (32) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (1) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) + +/* MMDC module features */ + +/* @brief MMDC module has CLK32 clock source gate. */ +#define FSL_FEATURE_MMDC_HAS_CLK32_GATE (1) +/* @brief MMDC module has arbitration and reordering control. */ +#define FSL_FEATURE_MMDC_HAS_ARB_REO_CONTROL (0) + +/* PXP module features */ + +/* @brief PXP module has dither engine. */ +#define FSL_FEATURE_PXP_HAS_DITHER (1) +/* @brief PXP module supports repeat run */ +#define FSL_FEATURE_PXP_HAS_EN_REPEAT (0) + +/* QSPI module features */ + +/* @brief QSPI lookup table depth. */ +#define FSL_FEATURE_QSPI_LUT_DEPTH (64) +/* @brief QSPI Tx FIFO depth. */ +#define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16) +/* @brief QSPI Rx FIFO depth. */ +#define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16) +/* @brief QSPI AHB buffer count. */ +#define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4) +/* @brief QSPI has command usage error flag. */ +#define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (1) +/* @brief QSPI support parallel mode. */ +#define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (1) +/* @brief QSPI support dual die. */ +#define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (1) +/* @brief there is no SCLKCFG bit in MCR register. */ +#define FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL (1) +/* @brief there is no AITEF bit in FR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_AITEF (1) +/* @brief there is no AIBSEF bit in FR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_AIBSEF (1) +/* @brief there is no TXDMA and TXWA bit in SR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_TXDMA (1) +/* @brief there is no SFACR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_SFACR (1) +/* @brief there is no TDH bit in FLSHCR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_TDH (1) +/* @brief QSPI AMBA base address. */ +#define FSL_FEATURE_QSPI_AMBA_BASE (0x60000000U) +/* @brief QSPI AHB buffer ARDB base address. */ +#define FSL_FEATURE_QSPI_ARDB_BASE (0x0C000000U) + +/* SDMA module features */ + +/* @brief SDMA module channel number. */ +#define FSL_FEATURE_SDMA_MODULE_CHANNEL (32) +/* @brief SDMA module event number. */ +#define FSL_FEATURE_SDMA_EVENT_NUM (48) +/* @brief SDMA ROM memory to memory script start address. */ +#define FSL_FEATURE_SDMA_M2M_ADDR (642) +/* @brief SDMA ROM peripheral to memory script start address. */ +#define FSL_FEATURE_SDMA_P2M_ADDR (683) +/* @brief SDMA ROM memory to peripheral script start address. */ +#define FSL_FEATURE_SDMA_M2P_ADDR (747) +/* @brief SDMA ROM uart to memory script start address. */ +#define FSL_FEATURE_SDMA_UART2M_ADDR (817) +/* @brief SDMA ROM peripheral on SPBA to memory script start address. */ +#define FSL_FEATURE_SDMA_SHP2M_ADDR (891) +/* @brief SDMA ROM memory to peripheral on SPBA script start address. */ +#define FSL_FEATURE_SDMA_M2SHP_ADDR (960) +/* @brief SDMA ROM UART on SPBA to memory script start address. */ +#define FSL_FEATURE_SDMA_UARTSH2M_ADDR (1032) +/* @brief SDMA ROM SPDIF to memory script start address. */ +#define FSL_FEATURE_SDMA_SPDIF2M_ADDR (1100) +/* @brief SDMA ROM memory to SPDIF script start address. */ +#define FSL_FEATURE_SDMA_M2SPDIF_ADDR (1134) + +/* SNVS module features */ + +/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ +#define FSL_FEATURE_SNVS_HAS_SRTC (0) + +/* SPBA module features */ + +/* @brief SPBA module start address. */ +#define FSL_FEATURE_SPBA_START (0x02000000U) +/* @brief SPBA module end address. */ +#define FSL_FEATURE_SPBA_END (0x0203FFFFU) + +/* SRC module features */ + +/* @brief There is MASK_WDOG3_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) +/* @brief There is MIX_RST_STRCH bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (1) +/* @brief There is DBG_RST_MSK_PG bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) +/* @brief There is WDOG3_RST_OPTN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (1) +/* @brief There is CORES_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (1) +/* @brief There is MTSR bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) +/* @brief There is CORE0_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) +/* @brief There is CORE0_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) +/* @brief There is SWRC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) +/* @brief There is EIM_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (1) +/* @brief There is LUEN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) +/* @brief There is SISR register. */ +#define FSL_FEATURE_SRC_HAS_SISR (1) +/* @brief There is RESET_OUT bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) +/* @brief There is WDOG3_RST_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) +/* @brief There is SW bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SW (0) +/* @brief There is IPP_USER_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) +/* @brief There is SNVS bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) +/* @brief There is CSU_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) +/* @brief There is LOCKUP bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0) +/* @brief There is POR bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_POR (0) +/* @brief There is IPP_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) + +/* IUART module features */ + +/* @brief UART Transmit/Receive FIFO Size */ +#define FSL_FEATURE_IUART_FIFO_SIZEn(x) (32) +/* @brief UART RX MUXed input selected option */ +#define FSL_FEATURE_IUART_RXDMUXSEL (1) + +/* USBHS module features */ + +/* @brief EHCI module instance count */ +#define FSL_FEATURE_USBHS_EHCI_COUNT (2) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (1) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) + +#endif /* _MCIMX6Y2_FEATURES_H_ */ + diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..97865d743aa433ea222b34a7c8620d08b87dba9a --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/SConscript @@ -0,0 +1,13 @@ +from building import * + +cwd = GetCurrentDir() +src = ['system_MCIMX6Y2.c'] + Glob('drivers/*.c') +CPPDEFINES = ['CHIP_MX6UL', 'CPU_MCIMX6Y2DVM09'] +path = [cwd, cwd + '/drivers'] + +src += Glob('drivers/usdhc/*.c') +path.append(cwd + '/drivers/usdhc') + +group = DefineGroup('libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_adc.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..265e196936a093113e4d5a9364152aac6a57ebc0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_adc.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_adc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ADC module. + * + * @param base ADC peripheral base address + */ +static uint32_t ADC_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC bases for each instance. */ +static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ADC clocks for each instance. */ +static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++) + { + if (s_adcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_adcBases)); + + return instance; +} + +void ADC_Init(ADC_Type *base, const adc_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* ADCx_CFG */ + tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */ + tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) | + ADC_CFG_ADICLK(config->clockSource) | ADC_CFG_ADIV(config->clockDriver) | ADC_CFG_MODE(config->resolution); + if (config->enableOverWrite) + { + tmp32 |= ADC_CFG_OVWREN_MASK; + } + if (config->enableLongSample) + { + tmp32 |= ADC_CFG_ADLSMP_MASK; + } + if (config->enableLowPower) + { + tmp32 |= ADC_CFG_ADLPC_MASK; + } + if (config->enableHighSpeed) + { + tmp32 |= ADC_CFG_ADHSC_MASK; + } + base->CFG = tmp32; + + /* ADCx_GC */ + tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK); + if (config->enableContinuousConversion) + { + tmp32 |= ADC_GC_ADCO_MASK; + } + if (config->enableAsynchronousClockOutput) + { + tmp32 |= ADC_GC_ADACKEN_MASK; + } + base->GC = tmp32; +} + +void ADC_Deinit(ADC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ADC_GetDefaultConfig(adc_config_t *config) +{ + assert(NULL != config); + + config->enableAsynchronousClockOutput = true; + config->enableOverWrite = false; + config->enableContinuousConversion = false; + config->enableHighSpeed = false; + config->enableLowPower = false; + config->enableLongSample = false; + config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; + config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; + config->clockSource = kADC_ClockSourceAD; + config->clockDriver = kADC_ClockDriver1; + config->resolution = kADC_Resolution12Bit; +} + +void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config) +{ + assert(NULL != config); + assert(channelGroup < ADC_HC_COUNT); + + uint32_t tmp32; + + tmp32 = ADC_HC_ADCH(config->channelNumber); + if (config->enableInterruptOnConversionCompleted) + { + tmp32 |= ADC_HC_AIEN_MASK; + } + base->HC[channelGroup] = tmp32; +} + +/* + *To complete calibration, the user must follow the below procedure: + * 1. Configure ADC_CFG with actual operating values for maximum accuracy. + * 2. Configure the ADC_GC values along with CAL bit. + * 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. + * 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. + */ +status_t ADC_DoAutoCalibration(ADC_Type *base) +{ + status_t status = kStatus_Success; +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) + bool bHWTrigger = false; + + /* The calibration would be failed when in hardwar mode. + * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ + if (0U != (ADC_CFG_ADTRG_MASK & base->CFG)) + { + bHWTrigger = true; + ADC_EnableHardwareTrigger(base, false); + } +#endif + + /* Clear the CALF and launch the calibration. */ + base->GS = ADC_GS_CALF_MASK; /* Clear the CALF. */ + base->GC |= ADC_GC_CAL_MASK; /* Launch the calibration. */ + + /* Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. */ + while (0U != (base->GC & ADC_GC_CAL_MASK)) + { + /* Check the CALF when the calibration is active. */ + if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) + { + status = kStatus_Fail; + break; + } + } + + /* When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. */ + if (0U == ADC_GetChannelStatusFlags(base, 0U)) /* Check the COCO[0] bit status. */ + { + status = kStatus_Fail; + } + if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) /* Check the CALF status. */ + { + status = kStatus_Fail; + } + + /* Clear conversion done flag. */ + ADC_GetChannelConversionValue(base, 0U); + +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) + /* Restore original trigger mode. */ + if (true == bHWTrigger) + { + ADC_EnableHardwareTrigger(base, true); + } +#endif + + return status; +} + +void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + tmp32 = ADC_OFS_OFS(config->offsetValue); + if (config->enableSigned) + { + tmp32 |= ADC_OFS_SIGN_MASK; + } + base->OFS = tmp32; +} + +void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config) +{ + uint32_t tmp32; + + tmp32 = base->GC & ~(ADC_GC_ACFE_MASK | ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK); + if (NULL == config) /* Pass "NULL" to disable the feature. */ + { + base->GC = tmp32; + return; + } + /* Enable the feature. */ + tmp32 |= ADC_GC_ACFE_MASK; + + /* Select the hardware compare working mode. */ + switch (config->hardwareCompareMode) + { + case kADC_HardwareCompareMode0: + break; + case kADC_HardwareCompareMode1: + tmp32 |= ADC_GC_ACFGT_MASK; + break; + case kADC_HardwareCompareMode2: + tmp32 |= ADC_GC_ACREN_MASK; + break; + case kADC_HardwareCompareMode3: + tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK; + break; + default: + break; + } + base->GC = tmp32; + + /* Load the compare values. */ + tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2); + base->CV = tmp32; +} + +void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode) +{ + uint32_t tmp32; + + if (mode == kADC_HardwareAverageDiasable) + { + base->GC &= ~ADC_GC_AVGE_MASK; + } + else + { + tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK; + tmp32 |= ADC_CFG_AVGS(mode); + base->CFG = tmp32; + base->GC |= ADC_GC_AVGE_MASK; /* Enable the hardware compare. */ + } +} + +void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + uint32_t tmp32 = 0; + + if (0U != (mask & kADC_CalibrationFailedFlag)) + { + tmp32 |= ADC_GS_CALF_MASK; + } + if (0U != (mask & kADC_ConversionActiveFlag)) + { + tmp32 |= ADC_GS_ADACT_MASK; + } + base->GS = tmp32; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_adc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..99429e60981ff4bc0302af61c3b4d0cd61e07539 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_adc.h @@ -0,0 +1,420 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ADC_H_ +#define _FSL_ADC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup adc_12b1msps_sar + * @{ + */ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! @brief ADC driver version */ +#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ + +/*! + * @brief Converter's status flags. + */ +typedef enum _adc_status_flags +{ + kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */ + kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */ + kADC_AsynchronousWakeupInterruptFlag = + ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */ +} adc_status_flags_t; + +/*! + * @brief Reference voltage source. + */ +typedef enum _adc_reference_voltage_source +{ + kADC_ReferenceVoltageSourceAlt0 = 0U, /*!< For external pins pair of VrefH and VrefL. */ +} adc_reference_voltage_source_t; + +/*! + * @brief Sample time duration. + */ +typedef enum _adc_sample_period_mode +{ + /* This group of enumeration is for internal use which is related to register setting. */ + kADC_SamplePeriod2or12Clocks = 0U, /*!< Long sample 12 clocks or short sample 2 clocks. */ + kADC_SamplePeriod4or16Clocks = 1U, /*!< Long sample 16 clocks or short sample 4 clocks. */ + kADC_SamplePeriod6or20Clocks = 2U, /*!< Long sample 20 clocks or short sample 6 clocks. */ + kADC_SamplePeriod8or24Clocks = 3U, /*!< Long sample 24 clocks or short sample 8 clocks. */ + /* This group of enumeration is for a public user. */ + /* For long sample mode. */ + kADC_SamplePeriodLong12Clcoks = kADC_SamplePeriod2or12Clocks, /*!< Long sample 12 clocks. */ + kADC_SamplePeriodLong16Clcoks = kADC_SamplePeriod4or16Clocks, /*!< Long sample 16 clocks. */ + kADC_SamplePeriodLong20Clcoks = kADC_SamplePeriod6or20Clocks, /*!< Long sample 20 clocks. */ + kADC_SamplePeriodLong24Clcoks = kADC_SamplePeriod8or24Clocks, /*!< Long sample 24 clocks. */ + /* For short sample mode. */ + kADC_SamplePeriodShort2Clocks = kADC_SamplePeriod2or12Clocks, /*!< Short sample 2 clocks. */ + kADC_SamplePeriodShort4Clocks = kADC_SamplePeriod4or16Clocks, /*!< Short sample 4 clocks. */ + kADC_SamplePeriodShort6Clocks = kADC_SamplePeriod6or20Clocks, /*!< Short sample 6 clocks. */ + kADC_SamplePeriodShort8Clocks = kADC_SamplePeriod8or24Clocks, /*!< Short sample 8 clocks. */ +} adc_sample_period_mode_t; + +/*! + * @brief Clock source. + */ +typedef enum _adc_clock_source +{ + kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */ + kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */ +#if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) + kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */ +#endif + kADC_ClockSourceAD = 3U, /*!< Select Asynchronous clock to generate ADCK. */ +} adc_clock_source_t; + +/*! + * @brief Clock divider for the converter. + */ +typedef enum _adc_clock_drvier +{ + kADC_ClockDriver1 = 0U, /*!< For divider 1 from the input clock to the module. */ + kADC_ClockDriver2 = 1U, /*!< For divider 2 from the input clock to the module. */ + kADC_ClockDriver4 = 2U, /*!< For divider 4 from the input clock to the module. */ + kADC_ClockDriver8 = 3U, /*!< For divider 8 from the input clock to the module. */ +} adc_clock_driver_t; + +/*! + * @brief Converter's resolution. + */ +typedef enum _adc_resolution +{ + kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */ + kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */ + kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */ +} adc_resolution_t; + +/*! + * @brief Converter hardware compare mode. + */ +typedef enum _adc_hardware_compare_mode +{ + kADC_HardwareCompareMode0 = 0U, /*!< Compare true if the result is less than the value1. */ + kADC_HardwareCompareMode1 = 1U, /*!< Compare true if the result is greater than or equal to value1. */ + kADC_HardwareCompareMode2 = 2U, /*!< Value1 <= Value2, compare true if the result is less than value1 Or + the result is Greater than value2. + Value1 > Value2, compare true if the result is less than value1 And the + result is greater than value2*/ + kADC_HardwareCompareMode3 = 3U, /*!< Value1 <= Value2, compare true if the result is greater than or equal + to value1 And the result is less than or equal to value2. + Value1 > Value2, compare true if the result is greater than or equal to + value1 Or the result is less than or equal to value2. */ +} adc_hardware_compare_mode_t; + +/*! + * @brief Converter hardware average mode. + */ +typedef enum _adc_hardware_average_mode +{ + kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ + kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ + kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ + kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ + kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */ +} adc_hardware_average_mode_t; + +/*! + * @brief Converter configuration. + */ +typedef struct _adc_config +{ + bool enableOverWrite; /*!< Enable the overwriting. */ + bool enableContinuousConversion; /*!< Enable the continuous conversion mode. */ + bool enableHighSpeed; /*!< Enable the high-speed mode. */ + bool enableLowPower; /*!< Enable the low power mode. */ + bool enableLongSample; /*!< Enable the long sample mode. */ + bool enableAsynchronousClockOutput; /*!< Enable the asynchronous clock output. */ + adc_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ + adc_sample_period_mode_t samplePeriodMode; /*!< Select the sample period in long sample mode or short mode. */ + adc_clock_source_t clockSource; /*!< Select the input clock source to generate the internal clock ADCK. */ + adc_clock_driver_t clockDriver; /*!< Select the divide ratio used by the ADC to generate the internal clock ADCK. */ + adc_resolution_t resolution; /*!< Select the ADC resolution mode. */ +} adc_config_t; + +/*! + * @brief Converter Offset configuration. + */ +typedef struct _adc_offest_config +{ + bool enableSigned; /*!< if false,The offset value is added with the raw result. + if true,The offset value is subtracted from the raw converted value. */ + uint32_t offsetValue; /*!< User configurable offset value(0-4095). */ +} adc_offest_config_t; + +/*! + * @brief ADC hardware compare configuration. + * + * In kADC_HardwareCompareMode0, compare true if the result is less than the value1. + * In kADC_HardwareCompareMode1, compare true if the result is greater than or equal to value1. + * In kADC_HardwareCompareMode2, Value1 <= Value2, compare true if the result is less than value1 Or the result is + * Greater than value2. + * Value1 > Value2, compare true if the result is less than value1 And the result is + * Greater than value2. + * In kADC_HardwareCompareMode3, Value1 <= Value2, compare true if the result is greater than or equal to value1 And the + * result is less than or equal to value2. + * Value1 > Value2, compare true if the result is greater than or equal to value1 Or the + * result is less than or equal to value2. + */ +typedef struct _adc_hardware_compare_config +{ + adc_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. + See "adc_hardware_compare_mode_t". */ + uint16_t value1; /*!< Setting value1(0-4095) for hardware compare mode. */ + uint16_t value2; /*!< Setting value2(0-4095) for hardware compare mode. */ +} adc_hardware_compare_config_t; + +/*! + * @brief ADC channel conversion configuration. + */ +typedef struct _adc_channel_config +{ + uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. + See channel connection information for each chip in Reference + Manual document. */ + bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */ +} adc_channel_config_t; +/******************************************************************************* +* API +******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initialize the ADC module. + * + * @param base ADC peripheral base address. + * @param config Pointer to "adc_config_t" structure. + */ +void ADC_Init(ADC_Type *base, const adc_config_t *config); + +/*! + * @brief De-initializes the ADC module. + * + * @param base ADC peripheral base address. + */ +void ADC_Deinit(ADC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the converter's configuration. + * + * This function initializes the converter configuration structure with available settings. The default values are: + * @code + * config->enableAsynchronousClockOutput = true; + * config->enableOverWrite = false; + * config->enableContinuousConversion = false; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableLongSample = false; + * config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; + * config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; + * config->clockSource = kADC_ClockSourceAD; + * config->clockDriver = kADC_ClockDriver1; + * config->resolution = kADC_Resolution12Bit; + * @endcode + * @param base ADC peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ADC_GetDefaultConfig(adc_config_t *config); + +/*! + * @brief Configures the conversion channel. + * + * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one + * group of status and control registers, one for each conversion. The channel group parameter indicates which group of + * registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B + * registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and + * hardware + * trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual + * about the + * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used + * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. + * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * @param base ADC peripheral base address. + * @param channelGroup Channel group index. + * @param config Pointer to the "adc_channel_config_t" structure for the conversion channel. + */ +void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config); + +/*! + * @brief Gets the conversion value. + * + * @param base ADC peripheral base address. + * @param channelGroup Channel group index. + * + * @return Conversion value. + */ +static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_R_COUNT); + + return base->R[channelGroup]; +} + +/*! + * @brief Gets the status flags of channel. + * + * A conversion is completed when the result of the conversion is transferred into the data + * result registers. (provided the compare function & hardware averaging is disabled), this is + * indicated by the setting of COCOn. If hardware averaging is enabled, COCOn sets only, + * if the last of the selected number of conversions is complete. If the compare function is + * enabled, COCOn sets and conversion result data is transferred only if the compare + * condition is true. If both hardware averaging and compare functions are enabled, then + * COCOn sets only if the last of the selected number of conversions is complete and the + * compare condition is true. + * + * @param base ADC peripheral base address. + * @param channelGroup Channel group index. + * + * @return Status flags of channel.return 0 means COCO flag is 0,return 1 means COCOflag is 1. + */ +static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_HC_COUNT); + + /* If flag is set,return 1,otherwise, return 0. */ + return (((base->HS) & (1U << channelGroup)) >> channelGroup); +} + +/*! + * @brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically. + * Execute the calibration before using the converter. Note that the software trigger should be used + * during calibration. + * + * @param base ADC peripheral base address. + * + * @return Execution status. + * @retval kStatus_Success Calibration is done successfully. + * @retval kStatus_Fail Calibration has failed. + */ +status_t ADC_DoAutoCalibration(ADC_Type *base); + +/*! + * @brief Set user defined offset. + * + * @param base ADC peripheral base address. + * @param config Pointer to "adc_offest_config_t" structure. + */ +void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config); + +/*! + * @brief Enables generating the DMA trigger when the conversion is complete. + * + * @param base ADC peripheral base address. + * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled. + */ +static inline void ADC_EnableDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->GC |= ADC_GC_DMAEN_MASK; + } + else + { + base->GC &= ~ADC_GC_DMAEN_MASK; + } +} + +/*! + * @brief Enables the hardware trigger mode. + * + * @param base ADC peripheral base address. + * @param enable Switcher of the trigger mode. "true" means hardware tirgger mode,"false" means software mode. + */ +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) +static inline void ADC_EnableHardwareTrigger(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= ADC_CFG_ADTRG_MASK; + } + else + { + base->CFG &= ~ADC_CFG_ADTRG_MASK; + } +} +#endif + +/*! + * @brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the + * result + * in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate + * reference + * manual for more information. + * + * @param base ADC peripheral base address. + * @param Pointer to "adc_hardware_compare_config_t" structure. + * + */ +void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config); + +/*! + * @brief Configures the hardware average mode. + * + * The hardware average mode provides a way to process the conversion result automatically by using hardware. The + * multiple + * conversion results are accumulated and averaged internally making them easier to read. + * + * @param base ADC peripheral base address. + * @param mode Setting the hardware average mode. See "adc_hardware_average_mode_t". + */ +void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode); + +/*! + * @brief Gets the converter's status flags. + * + * @param base ADC peripheral base address. + * + * @return Flags' mask if indicated flags are asserted. See "adc_status_flags_t". + */ +static inline uint32_t ADC_GetStatusFlags(ADC_Type *base) +{ + return base->GS; +} + +/*! + * @brief Clears the converter's status falgs. + * + * @param base ADC peripheral base address. + * @param mask Mask value for the cleared flags. See "adc_status_flags_t". + */ +void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_ADC_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.c new file mode 100644 index 0000000000000000000000000000000000000000..8df9a16f9e51b5ecc9eb573dcfa35487231081ad --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateICacheByRange(address, size_byte); +} + +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateDCacheByRange(address, size_byte); +} + +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanDCacheByRange(address, size_byte); +} + +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.h new file mode 100644 index 0000000000000000000000000000000000000000..7eedede9e31c7ddbd474e18e83a331d007413881 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version 2.0.0. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Cache Control for Cortex-a L1 cache + *@{ + */ + +/*! + * @brief Enables L1 instruction cache. + * + */ +static inline void L1CACHE_EnableICache(void) +{ + L1C_EnableInstructionCache(); +} +/*! + * @brief Disables L1 instruction cache. + * + */ +static inline void L1CACHE_DisableICache(void) +{ + L1C_DisableInstructionCache(); +} +/*! + * @brief Invalidates L1 instruction cache all. + * + */ +static inline void L1CACHE_InvalidateICache(void) +{ + L1C_InvalidateInstructionCacheAll(); +} +/*! + * @brief Invalidates L1 instruction cache by range. + * + * @param startAddr The start startAddr of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start startAddr and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned due to the + * cache operation unit is one L1 I-cache line. The startAddr here will be forced + * to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_InvalidateICacheByRange(uint32_t startAddr, uint32_t size_byte) +{ + L1C_InvalidateInstructionCacheRange((void *)startAddr, size_byte); +} +/*! + * @brief Enables L1 data cache. + * + */ +static inline void L1CACHE_EnableDCache(void) +{ + L1C_EnableDataCache(); +} +/*! + * @brief Disables L1 data cache. + * + */ +static inline void L1CACHE_DisableDCache(void) +{ + L1C_DisableDataCache(); +} +/*! + * @brief Invalidates L1 data cache all. + * + */ +static inline void L1CACHE_InvalidateDCache(void) +{ + L1C_InvalidateDataCacheAll(); +} +/*! + * @brief Invalidates L1 data cache by range. + * + * @param startAddr The start startAddr of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start startAddr and size_byte should be 64-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned due to the + * cache operation unit is one L1 D-cache line. The startAddr here will be forced + * to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_InvalidateDCacheByRange(uint32_t startAddr, uint32_t size_byte) +{ + L1C_InvalidateDataCacheRange((void *)startAddr, size_byte); +} +/*! + * @brief Clean L1 data cache all. + * + */ +static inline void L1CACHE_CleanDCache(void) +{ + L1C_CleanDataCacheAll(); +} +/*! + * @brief Cleans L1 data cache by range. + * + * @param startAddr The start startAddr of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start startAddr and size_byte should be 64-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned due to the + * cache operation unit is one L1 D-cache line. The startAddr here will be forced + * to align to L1 D-cache line size if startAddr is not aligned. For size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanDCacheByRange(uint32_t startAddr, uint32_t size_byte) +{ + L1C_CleanDataCacheRange((void *)startAddr, size_byte); +} +/*! + * @brief Cleans and invalidates L1 data cache all. + * + */ +static inline void L1CACHE_CleanInvalidateDCache(void) +{ + L1C_CleanInvalidateDataCacheAll(); +} +/*! + * @brief Cleans and invalidates L1 data cache by range. + * + * @param startAddr The start startAddr of the memory to be clean and invalidated. + * @param size_byte The memory size. + * @note The start startAddr and size_byte should be 64-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned due to the + * cache operation unit is one L1 D-cache line. The startAddr here will be forced + * to align to L1 D-cache line size if startAddr is not aligned. For size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t startAddr, uint32_t size_byte) +{ + L1C_CleanInvalidateDataCacheRange((void *)startAddr, size_byte); +} +/*@}*/ + +/*! + * @name Unified Cache Control for all caches which is mainly used for + * SDK Driver easy use cache driver + *@{ + */ + +/*! + * @brief Invalidates instruction cache by range. + * + * Cortex-a L1 instruction cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Invalidates data cache by range. + * + * Cortex-a L1 data cache line length is 64-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to cache line size + * 64-byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans data cache by range. + * + * Cortex-a L1 data cache line length is 64-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to cache line size + * 64-byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and Invalidates data cache by range. + * + * Cortex-a L1 data cache line length is 64-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned and invalidated. + * @note Address and size should be aligned to cache line size + * 64-byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); +/*@}*/ +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.c new file mode 100644 index 0000000000000000000000000000000000000000..347d92e10573c37a6e38287cb0a0e8616eb35766 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.c @@ -0,0 +1,915 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* External XTAL (OSC) clock frequency. */ +uint32_t g_xtalFreq; +/* External RTC XTAL clock frequency. */ +uint32_t g_rtcXtalFreq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CLOCK_GetPeriphClkFreq(void) +{ + uint32_t freq; + + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CLOCK_GetOscFreq(); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pll2_main_clk ---> Periph_clk */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL2 PFD2 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 PFD0 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + + /* PLL2 PFD2 divided(/2) ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) >> 1U); + break; + + default: + freq = 0U; + break; + } + } + + return freq; +} + +void CLOCK_InitExternalClk(bool bypassXtalOsc) +{ + /* This device does not support bypass XTAL OSC. */ + assert(!bypassXtalOsc); + + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */ + while ((PMU->LOWPWR_CTRL & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0) + { + } + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */ + while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0) + { + } + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; +} + +void CLOCK_DeinitExternalClk(void) +{ + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ +} + +void CLOCK_SwitchOsc(clock_osc_t osc) +{ + if (osc == kCLOCK_RcOsc) + PMU->LOWPWR_CTRL_SET = PMU_LOWPWR_CTRL_OSC_SEL_MASK; + else + PMU->LOWPWR_CTRL_CLR = PMU_LOWPWR_CTRL_OSC_SEL_MASK; +} + +void CLOCK_InitRcOsc24M(void) +{ + PMU->LOWPWR_CTRL |= PMU_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +void CLOCK_DeinitRcOsc24M(void) +{ + PMU->LOWPWR_CTRL &= ~PMU_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +uint32_t CLOCK_GetFreq(clock_name_t name) +{ + uint32_t freq; + + switch (name) + { + case kCLOCK_CpuClk: + switch (CCM->CCSR & (CCM_CCSR_STEP_SEL_MASK | CCM_CCSR_SECONDARY_CLK_SEL_MASK | CCM_CCSR_PLL1_SW_CLK_SEL_MASK)) + { + /* ARM PLL ---> CPU Clock */ + case 0U: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + + /* Osc_clk (24M) ---> Step Clock ---> CPU Clock */ + case (CCM_CCSR_PLL1_SW_CLK_SEL_MASK): + freq = CLOCK_GetOscFreq(); + break; + + /* PLL2 PFD2 ---> Secondary_clk ---> Step Clock ---> CPU Clock */ + case (CCM_CCSR_PLL1_SW_CLK_SEL_MASK | CCM_CCSR_STEP_SEL_MASK): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 ---> Secondary_clk ---> Step Clock ---> CPU Clock */ + case (CCM_CCSR_STEP_SEL_MASK | CCM_CCSR_SECONDARY_CLK_SEL_MASK | CCM_CCSR_PLL1_SW_CLK_SEL_MASK): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + default: + freq = 0U; + break; + } + freq /= (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + case kCLOCK_AxiClk: + /* AXI alternative clock ---> AXI Clock */ + if (CCM->CBCDR & CCM_CBCDR_AXI_SEL_MASK) + { + /* PLL3 PFD1 ---> AXI alternative clock ---> AXI Clock */ + if (CCM->CBCDR & CCM_CBCDR_AXI_ALT_SEL_MASK) + { + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + } + /* PLL2 PFD2 ---> AXI alternative clock ---> AXI Clock */ + else + { + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + } + } + /* Periph_clk ---> AXI Clock */ + else + { + freq = CLOCK_GetPeriphClkFreq(); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_AXI_PODF_MASK) >> CCM_CBCDR_AXI_PODF_SHIFT) + 1U); + break; + + case kCLOCK_AhbClk: + /* Periph_clk ---> AHB Clock */ + freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + break; + + case kCLOCK_IpgClk: + /* Periph_clk ---> AHB Clock ---> IPG Clock */ + freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); + break; + + case kCLOCK_MmdcClk: + /* periph2_clk2 ---> MMDC Clock */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH2_CLK_SEL_MASK) + { + /* OSC ---> periph2_clk2 ---> MMDC Clock */ + if (CCM->CBCMR & CCM_CBCMR_PERIPH2_CLK2_SEL_MASK) + { + freq = CLOCK_GetOscFreq(); + } + /* pll3_sw_clk ---> periph2_clk2 ---> MMDC Clock */ + else + { + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT) + 1U); + } + /* pll2_main_clk ---> MMDC Clock */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) + { + /* PLL2 ---> pll2_main_clk ---> MMDC Clock */ + case CCM_CBCMR_PRE_PERIPH2_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL2 PFD2 ---> pll2_main_clk ---> MMDC Clock */ + case CCM_CBCMR_PRE_PERIPH2_CLK_SEL(1U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 PFD0 ---> pll2_main_clk ---> MMDC Clock */ + case CCM_CBCMR_PRE_PERIPH2_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + + /* PLL4 ---> pll2_main_clk ---> MMDC Clock */ + case CCM_CBCMR_PRE_PERIPH2_CLK_SEL(3U): + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + + default: + freq = 0U; + break; + } + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_FABRIC_MMDC_PODF_MASK) >> CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT) + 1U); + break; + + case kCLOCK_OscClk: + freq = CLOCK_GetOscFreq(); + break; + case kCLOCK_RtcClk: + freq = CLOCK_GetRtcFreq(); + break; + case kCLOCK_ArmPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + case kCLOCK_Usb1PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + case kCLOCK_Usb1PllPfd0Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_Usb1PllPfd1Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_Usb1PllPfd2Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_Usb1PllPfd3Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_Usb2PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb2); + break; + case kCLOCK_SysPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case kCLOCK_SysPllPfd0Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_SysPllPfd1Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_SysPllPfd2Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_SysPllPfd3Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_EnetPll0Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet0); + break; + case kCLOCK_EnetPll1Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet1); + break; + case kCLOCK_EnetPll2Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet2); + break; + case kCLOCK_AudioPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + case kCLOCK_VideoPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) +{ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_MASK | + CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitArmPll(void) +{ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; +} + +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_ENABLE_MASK | + CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitSysPll(void) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; +} + +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) +{ + CCM_ANALOG->PLL_USB1 = CCM_ANALOG_PLL_USB1_ENABLE_MASK | + CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | + CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitUsb1Pll(void) +{ + CCM_ANALOG->PLL_USB1 = 0U; +} + +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) +{ + CCM_ANALOG->PLL_USB2 = CCM_ANALOG_PLL_USB2_ENABLE_MASK | + CCM_ANALOG_PLL_USB2_POWER_MASK | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | + CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitUsb2Pll(void) +{ + CCM_ANALOG->PLL_USB2 = 0U; +} + +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) +{ + uint32_t pllAudio; + uint32_t misc2 = 0; + + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); + CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllAudio = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 8: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 4: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 2: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + break; + + default: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) + | misc2; + + CCM_ANALOG->PLL_AUDIO = pllAudio; + + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitAudioPll(void) +{ + CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; +} + +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) +{ + uint32_t pllVideo; + uint32_t misc2 = 0; + + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllVideo = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 8: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 4: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 2: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + break; + + default: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK) | misc2; + + CCM_ANALOG->PLL_VIDEO = pllVideo; + + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitVideoPll(void) +{ + CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; +} + +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) +{ + uint32_t enet_pll = CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(config->loopDivider1) | + CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(config->loopDivider0); + + if (config->enableClkOutput0) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK; + } + + if (config->enableClkOutput1) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK; + } + + if (config->enableClkOutput2) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + } + + CCM_ANALOG->PLL_ENET = enet_pll; + + /* Wait for stable */ + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitEnetPll(void) +{ + CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; +} + +uint32_t CLOCK_GetPllFreq(clock_pll_t pll) +{ + uint32_t freq; + uint32_t divSelect; + uint64_t freqTmp; + + const uint32_t enetRefClkFreq[] = { + 25000000U, /* 25M */ + 50000000U, /* 50M */ + 100000000U, /* 100M */ + 125000000U /* 125M */ + }; + + switch (pll) + { + case kCLOCK_PllArm: + freq = ((CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + break; + + case kCLOCK_PllSys: + freq = CLOCK_GetOscFreq(); + + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + freq *= 22U; + } + else + { + freq *= 20U; + } + + freq += (uint32_t)freqTmp; + break; + + case kCLOCK_PllUsb1: + freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + case kCLOCK_PllAudio: + freq = CLOCK_GetOscFreq(); + + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + + freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* AUDIO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_AUDIO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[AUDO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)) + { + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 1U; + break; + + default: + break; + } + break; + + case kCLOCK_PllVideo: + freq = CLOCK_GetOscFreq(); + + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; + + freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* VIDEO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_VIDEO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[VIDEO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + { + case CCM_ANALOG_MISC2_VIDEO_DIV(3): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_VIDEO_DIV(1): + freq >>= 1U; + break; + + default: + break; + } + break; + + case kCLOCK_PllEnet0: + divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) + >> CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet1: + divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) + >> CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet2: + /* ref_enetpll2 if fixed at 25MHz. */ + freq = 25000000UL; + break; + + case kCLOCK_PllUsb2: + freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd528; + + pfd528 = CCM_ANALOG->PFD_528 & ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +void CLOCK_DeinitSysPfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd); +} + +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd480; + + pfd480 = CCM_ANALOG->PFD_480 & ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd); +} + +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + + +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + + +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY1->PWD = 0; + USBPHY1->CTRL |= + USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | + USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | + USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); + USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY2->PWD = 0; + USBPHY2->CTRL |= + USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | + USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | + USBPHY_CTRL_ENUTMILEVEL3_MASK; + + return true; +} +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CLOCK_DeinitUsb1Pll(); + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ + +} +void CLOCK_DisableUsbhs1PhyPllClock(void) +{ + CLOCK_DeinitUsb2Pll(); + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.h new file mode 100644 index 0000000000000000000000000000000000000000..b2916922b68a86dfbcd55c6d94326b6c9b74eae3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.h @@ -0,0 +1,1177 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name ofcopyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_device_registers.h" +#include +#include +#include + +/*! + * @addtogroup clock + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_TUPLE(reg, shift, mask, busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.1.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + + +/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. + * + * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, + * if XTAL is 24MHz, + * @code + * CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC + * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver. + * @endcode + */ +extern uint32_t g_xtalFreq; + +/*! @brief External RTC XTAL (32K OSC) clock frequency. + * + * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. + */ +extern uint32_t g_rtcXtalFreq; + +/* For compatible with other platforms */ +#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq +#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq + + /*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1 \ + } + +/*! @brief Clock ip name array for ADC_5HC. */ +#define ADC_5HC_CLOCKS \ + { \ + kCLOCK_Adc_5hc \ + } + +/*! @brief Clock ip name array for ECSPI. */ +#define ECSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, \ + kCLOCK_Ecspi3, kCLOCK_Ecspi4 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enet, kCLOCK_Enet \ + } + +/*! @brief Clock ip name array for EPIT. */ +#define EPIT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Epit1, kCLOCK_Epit2 \ + } + +/*! @brief Clock ip name array for ESAI. */ +#define ESAI_CLOCKS \ + { \ + kCLOCK_Esai \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ + } + +/*! @brief Serial Clock ip name array for FLEXCAN. */ +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, \ + kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ + } + +/*! @brief Serial Clock ip name array for GPT. */ +#define GPT_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1S, kCLOCK_Gpt2S \ + } + +/*! @brief Clock ip name array for I2C. */ +#define I2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_I2c1S, kCLOCK_I2c2S, \ + kCLOCK_I2c3S, kCLOCK_I2c4S \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + kCLOCK_IpInvalid, \ + kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \ + kCLOCK_Pwm5, kCLOCK_Pwm6, kCLOCK_Pwm7, kCLOCK_Pwm8, \ + } + +/*! @brief Clock ip name array for QSPI. */ +#define QSPI_CLOCKS \ + { \ + kCLOCK_Qspi1 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, \ + } + +/*! @brief Clock ip name array for SDMA. */ +#define SDMA_CLOCKS \ + { \ + kCLOCK_Sdma \ + } + +/*! @brief Clock ip name array for TSC. */ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ + } + +/*! @brief Clock ip name array for UART. */ +#define UART_CLOCKS \ + { \ + kCLOCK_IpInvalid, \ + kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \ + kCLOCK_Uart5, kCLOCK_Uart6, kCLOCK_Uart7, kCLOCK_Uart8 \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \ + } + +/*! @brief eLCDIF apb_clk. */ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ + } + +/*! @brief eLCDIF pix_clk. */ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_Lcdif1 \ + } + +/*! @brief PXP clock. */ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ + } + +/*! @brief Clock ip name array for SNVS HP. */ +#define SNVS_HP_CLOCKS \ + { \ + kCLOCK_SnvsHp \ + } + +/*! @brief Clock ip name array for SNVS LP. */ +#define SNVS_LP_CLOCKS \ + { \ + kCLOCK_SnvsLp \ + } + +/*! @brief CSI clock. */ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ + } + +/*! @brief CSI MCLK. */ +#define CSI_MCLK_CLOCKS \ + { \ + kCLOCK_CsiMclk \ + } + +/*! @brief MMDC IPG clock. */ +#define FSL_CLOCK_MMDC_IPG_GATE_COUNT 2U +#define MMDC_CLOCKS \ + { \ + {kCLOCK_MmdcIpgP0, kCLOCK_MmdcIpgP1} \ + } + +/*! @brief MMDC ACLK. */ +#define MMDC_ACLK_CLOCKS \ + { \ + kCLOCK_MmdcAClk \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AxiClk = 0x1U, /*!< AXI clock */ + kCLOCK_AhbClk = 0x2U, /*!< AHB clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_MmdcClk = 0x4U, /*!< MMDC clock */ + + kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */ + + kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */ + + kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */ + + kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */ + + kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */ + + kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */ + kCLOCK_EnetPll2Clk = 0x15U, /*!< Enet PLLCLK ref_enetpll2. */ + + kCLOCK_AudioPllClk = 0x16U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x17U, /*!< Video PLLCLK. */ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/*! @brief Clock name used to enable/disable gate */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + /* CCM CCGR0 */ + kCLOCK_AipsTz1 = (0U << 8) | 0x0U, /*!< CCGR0, CG0 */ + kCLOCK_AipsTz2 = (0U << 8) | 0x1U, /*!< CCGR0, CG1 */ + kCLOCK_Apbhdma = (0U << 8) | 0x2U, /*!< CCGR0, CG2 */ + kCLOCK_Asrc = (0U << 8) | 0x3U, /*!< CCGR0, CG3 */ + /*!< CCGR(0U << 8), CG4 reserved */ + kCLOCK_Dcp = (0U << 8) | 0x5U, /*!< CCGR0, CG5 */ + kCLOCK_Enet = (0U << 8) | 0x6U, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8) | 0x7U, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8) | 0x8U, /*!< CCGR0, CG8 , Serial Clock */ + kCLOCK_Can2 = (0U << 8) | 0x9U, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8) | 0xAU, /*!< CCGR0, CG10, Serial Clock */ + kCLOCK_CpuDbg = (0U << 8) | 0xBU, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8) | 0xCU, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8) | 0xDU, /*!< CCGR0, CG13, Serial Clock */ + kCLOCK_Uart2 = (0U << 8) | 0xEU, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8) | 0xFU, /*!< CCGR0, CG15 */ + + /*!< CCM CCGR1 */ + kCLOCK_Ecspi1 = (1U << 8) | 0x0U, /*!< CCGR1, CG0 */ + kCLOCK_Ecspi2 = (1U << 8) | 0x1U, /*!< CCGR1, CG1 */ + kCLOCK_Ecspi3 = (1U << 8) | 0x2U, /*!< CCGR1, CG2 */ + kCLOCK_Ecspi4 = (1U << 8) | 0x3U, /*!< CCGR1, CG3 */ + kCLOCK_Adc_5hc = (1U << 8) | 0x4U, /*!< CCGR1, CG4 */ + kCLOCK_Uart3 = (1U << 8) | 0x5U, /*!< CCGR1, CG5 */ + kCLOCK_Epit1 = (1U << 8) | 0x6U, /*!< CCGR1, CG6 */ + kCLOCK_Epit2 = (1U << 8) | 0x7U, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8) | 0x8U, /*!< CCGR1, CG8 */ + kCLOCK_SimS = (1U << 8) | 0x9U, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8) | 0xAU, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8) | 0xBU, /*!< CCGR1, CG11, Serial Clock */ + kCLOCK_Uart4 = (1U << 8) | 0xCU, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8) | 0xDU, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8) | 0xEU, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8) | 0xFU, /*!< CCGR1, CG15 */ + + /*!< CCM CCGR2 */ + kCLOCK_Esai = (2U << 8) | 0x0U, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8) | 0x1U, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8) | 0x2U, /*!< CCGR2, CG2 */ + kCLOCK_I2c1S = (2U << 8) | 0x3U, /*!< CCGR2, CG3, Serial Clock */ + kCLOCK_I2c2S = (2U << 8) | 0x4U, /*!< CCGR2, CG4, Serial Clock */ + kCLOCK_I2c3S = (2U << 8) | 0x5U, /*!< CCGR2, CG5, Serial Clock */ + kCLOCK_Ocotp = (2U << 8) | 0x6U, /*!< CCGR2, CG6 */ + kCLOCK_IomuxcIpt = (2U << 8) | 0x7U, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8) | 0x8U, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8) | 0x9U, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8) | 0xAU, /*!< CCGR2, CG10 */ + kCLOCK_Ipsync = (2U << 8) | 0xBU, /*!< CCGR2, CG11 */ + /*!< CCGR2, CG12 reserved */ + kCLOCK_Gpio3 = (2U << 8) | 0xDU, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8) | 0xEU, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8) | 0xFU, /*!< CCGR2, CG15 */ + + /*!< CCM CCGR3 */ + kCLOCK_CsiMclk = (3U << 8) | 0x0U, /*!< CCGR3, CG0 */ + kCLOCK_Uart5 = (3U << 8) | 0x1U, /*!< CCGR3, CG1 */ + kCLOCK_Epdc = (3U << 8) | 0x2U, /*!< CCGR3, CG2 */ + kCLOCK_Uart6 = (3U << 8) | 0x3U, /*!< CCGR3, CG3 */ + kCLOCK_Dap = (3U << 8) | 0x4U, /*!< CCGR3, CG4 */ + kCLOCK_Lcdif1 = (3U << 8) | 0x5U, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8) | 0x6U, /*!< CCGR3, CG6 */ + kCLOCK_Qspi1 = (3U << 8) | 0x7U, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8) | 0x8U, /*!< CCGR3, CG8 */ + kCLOCK_Patch = (3U << 8) | 0x9U, /*!< CCGR3, CG9 */ + kCLOCK_MmdcAClk = (3U << 8) | 0xAU, /*!< CCGR3, CG10 */ + /*!< CCGR3, CG11 reserved */ + kCLOCK_MmdcIpgP0 = (3U << 8) | 0xCU, /*!< CCGR3, CG12 */ + kCLOCK_MmdcIpgP1 = (3U << 8) | 0xDU, /*!< CCGR3, CG13 */ + kCLOCK_Axi = (3U << 8) | 0xEU, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8) | 0xFU, /*!< CCGR3, CG15 */ + + /*!< CCM CCGR4 */ + /*!< CCGR4, CG0 reserved */ + kCLOCK_Iomuxc = (4U << 8) | 0x1U, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8) | 0x2U, /*!< CCGR4, CG2 */ + kCLOCK_SimCpu = (4U << 8) | 0x3U, /*!< CCGR4, CG3 */ + kCLOCK_ApbSlave = (4U << 8) | 0x4U, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8) | 0x5U, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8) | 0x6U, /*!< CCGR4, CG6 */ + kCLOCK_Axi2Apb = (4U << 8) | 0x7U, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8) | 0x8U, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8) | 0x9U, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8) | 0xAU, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8) | 0xBU, /*!< CCGR4, CG11 */ + kCLOCK_RawNandBchApb = (4U << 8) | 0xCU, /*!< CCGR4, CG12 */ + kCLOCK_RawNandBch = (4U << 8) | 0xDU, /*!< CCGR4, CG13 */ + kCLOCK_RawNandGpmi = (4U << 8) | 0xEU, /*!< CCGR4, CG14 */ + kCLOCK_RawNandGpmiApb = (4U << 8) | 0xFU, /*!< CCGR4, CG15 */ + + /*!< CCM CCGR5 */ + kCLOCK_Rom = (5U << 8) | 0x0U, /*!< CCGR5, CG0 */ + kCLOCK_Stcr = (5U << 8) | 0x1U, /*!< CCGR5, CG1 */ + kCLOCK_SnvsDryice = (5U << 8) | 0x2U, /*!< CCGR5, CG2 */ + kCLOCK_Sdma = (5U << 8) | 0x3U, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8) | 0x4U, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8) | 0x5U, /*!< CCGR5, CG5 */ + kCLOCK_Spba = (5U << 8) | 0x6U, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8) | 0x7U, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8) | 0x8U, /*!< CCGR5, CG8 */ + kCLOCK_SnvsHp = (5U << 8) | 0x9U, /*!< CCGR5, CG9 */ + kCLOCK_SnvsLp = (5U << 8) | 0xAU, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8) | 0xBU, /*!< CCGR5, CG11 */ + kCLOCK_Uart1 = (5U << 8) | 0xCU, /*!< CCGR5, CG12 */ + kCLOCK_Uart7 = (5U << 8) | 0xDU, /*!< CCGR5, CG13 */ + kCLOCK_Sai1 = (5U << 8) | 0xEU, /*!< CCGR5, CG14 */ + kCLOCK_Sai2 = (5U << 8) | 0xFU, /*!< CCGR5, CG15 */ + + /*!< CCM CCGR6 */ + kCLOCK_UsbOh3 = (6U << 8) | 0x0U, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8) | 0x1U, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8) | 0x2U, /*!< CCGR6, CG2 */ + /*!< CCGR6, CG3 reserved */ + kCLOCK_Ipmux4 = (6U << 8) | 0x4U, /*!< CCGR6, CG4 */ + kCLOCK_EimSlow = (6U << 8) | 0x5U, /*!< CCGR6, CG5 */ + /*!< CCGR6, CG6 reserved */ + kCLOCK_Uart8 = (6U << 8) | 0x7U, /*!< CCGR6, CG7 */ + kCLOCK_Pwm8 = (6U << 8) | 0x8U, /*!< CCGR6, CG8 */ + kCLOCK_AipsTz3 = (6U << 8) | 0x9U, /*!< CCGR6, CG9 */ + kCLOCK_Wdog3 = (6U << 8) | 0xAU, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8) | 0xBU, /*!< CCGR6, CG11 */ + kCLOCK_I2c4S = (6U << 8) | 0xCU, /*!< CCGR6, CG12, Serial Clock */ + kCLOCK_Pwm5 = (6U << 8) | 0xDU, /*!< CCGR6, CG13 */ + kCLOCK_Pwm6 = (6U << 8) | 0xEU, /*!< CCGR6, CG14 */ + kCLOCK_Pwm7 = (6U << 8) | 0xFU, /*!< CCGR6, CG15 */ +} clock_ip_name_t; + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! + * @brief MUX control names for clock mux setting. + * + * These constants define the mux control names for clock mux setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_mux +{ + kCLOCK_StepMux = CCM_TUPLE(CCSR, CCM_CCSR_STEP_SEL_SHIFT, CCM_CCSR_STEP_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< atep clock mux name */ + kCLOCK_SecMux = CCM_TUPLE(CCSR, CCM_CCSR_SECONDARY_CLK_SEL_SHIFT, CCM_CCSR_SECONDARY_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< secondary clock mux name */ + kCLOCK_Pll1SwMux = CCM_TUPLE(CCSR, CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT, CCM_CCSR_PLL1_SW_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pll1_sw_clk mux name */ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR, CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, CCM_CCSR_PLL3_SW_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< Pll3_sw_clk mux name */ + + kCLOCK_Periph2Mux = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT, CCM_CBCDR_PERIPH2_CLK_SEL_MASK, CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT), /*!< periph2 mux name */ + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, CCM_CBCDR_PERIPH_CLK_SEL_MASK, CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_AxiAltMux = CCM_TUPLE(CBCDR, CCM_CBCDR_AXI_ALT_SEL_SHIFT, CCM_CBCDR_AXI_ALT_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< axi alt mux name */ + kCLOCK_AxiMux = CCM_TUPLE(CBCDR, CCM_CBCDR_AXI_SEL_SHIFT, CCM_CBCDR_AXI_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< axi mux name */ + + kCLOCK_PrePeriph2Mux = CCM_TUPLE(CBCMR, CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT, CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pre-periph2 mux name */ + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR, CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_Periph2Clk2Mux = CCM_TUPLE(CBCMR, CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT, CCM_CBCMR_PERIPH2_CLK2_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< periph2 clock2 mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR, CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, CCM_CBCMR_PERIPH_CLK2_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + + kCLOCK_EimSlowMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT, CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< aclk eim slow mux name */ + kCLOCK_GpmiMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_GPMI_CLK_SEL_SHIFT, CCM_CSCMR1_GPMI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< gpmi mux name */ + kCLOCK_BchMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_BCH_CLK_SEL_SHIFT, CCM_CSCMR1_BCH_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< bch mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_Qspi1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT, CCM_CSCMR1_QSPI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< qspi1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, CCM_CSCMR1_PERCLK_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + + kCLOCK_VidMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_VID_CLK_SEL_SHIFT, CCM_CSCMR2_VID_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< vid mux name */ + kCLOCK_EsaiMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ESAI_CLK_SEL_SHIFT, CCM_CSCMR2_ESAI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< esai mux name */ + kCLOCK_CanMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */ + + kCLOCK_UartMux = CCM_TUPLE(CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */ + + kCLOCK_EnfcMux = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ENFC_CLK_SEL_SHIFT, CCM_CS2CDR_ENFC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< enfc mux name */ + kCLOCK_LdbDi0Mux = CCM_TUPLE(CS2CDR, CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT, CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< ldb di0 mux name */ + + kCLOCK_SpdifMux = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + + kCLOCK_EpdcPreMux = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT, CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< epdc pre mux name */ + kCLOCK_EpdcMux = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT, CCM_CHSCCDR_EPDC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< epdc mux name */ + + kCLOCK_EcspiMux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT, CCM_CSCDR2_ECSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< ecspi mux name */ + kCLOCK_Lcdif1PreMux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT, CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 pre mux name */ + kCLOCK_Lcdif1Mux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT, CCM_CSCDR2_LCDIF1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 mux name */ + + kCLOCK_CsiMux = CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */ +} clock_mux_t; + +/*! + * @brief DIV control names for clock div setting. + * + * These constants define div control names for clock div setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_div +{ + kCLOCK_ArmDiv = CCM_TUPLE(CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, CCM_CBCDR_PERIPH_CLK2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_Periph2Clk2Div = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT, CCM_CBCDR_PERIPH2_CLK2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< periph2 clock2 div name */ + kCLOCK_AxiDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_AXI_PODF_SHIFT, CCM_CBCDR_AXI_PODF_MASK, CCM_CDHIPR_AXI_PODF_BUSY_SHIFT), /*!< axi div name */ + kCLOCK_AhbDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + kCLOCK_FabricMmdcDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT, CCM_CBCDR_FABRIC_MMDC_PODF_MASK, CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT), /*!< mmdc/fabric div name */ + + kCLOCK_Lcdif1Div = CCM_TUPLE(CBCMR, CCM_CBCMR_LCDIF1_PODF_SHIFT, CCM_CBCMR_LCDIF1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 div name */ + + kCLOCK_Qspi1Div = CCM_TUPLE(CSCMR1, CCM_CSCMR1_QSPI1_PODF_SHIFT, CCM_CSCMR1_QSPI1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< qspi1 div name */ + kCLOCK_EimSlowDiv = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT, CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< eim slow div name */ + kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */ + + kCLOCK_VidDiv = CCM_TUPLE(CSCMR2, CCM_CSCMR2_VID_CLK_PODF_SHIFT, CCM_CSCMR2_VID_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< vid div name */ + kCLOCK_VidPreDiv = CCM_TUPLE(CSCMR2, CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT, CCM_CSCMR2_VID_CLK_PRE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< vid pre div name */ + kCLOCK_LdbDi0Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_LDB_DI0_DIV_SHIFT, CCM_CSCMR2_LDB_DI0_DIV_MASK, CCM_NO_BUSY_WAIT), /*!< ldb di0 div name */ + kCLOCK_LdbDi1Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_LDB_DI1_DIV_SHIFT, CCM_CSCMR2_LDB_DI1_DIV_MASK, CCM_NO_BUSY_WAIT), /*!< ldb di1 div name */ + kCLOCK_CanDiv = CCM_TUPLE(CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */ + + kCLOCK_GpmiDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_GPMI_PODF_SHIFT, CCM_CSCDR1_GPMI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< gpmi div name */ + kCLOCK_BchDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_BCH_PODF_SHIFT, CCM_CSCDR1_BCH_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< bch div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */ + + kCLOCK_EsaiPreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ESAI_CLK_PRED_SHIFT, CCM_CS1CDR_ESAI_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_EsaiDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ESAI_CLK_PODF_SHIFT, CCM_CS1CDR_ESAI_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< esai div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, CCM_CS1CDR_SAI3_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, CCM_CS1CDR_SAI1_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + + kCLOCK_EnfcPreDiv = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ENFC_CLK_PRED_SHIFT, CCM_CS2CDR_ENFC_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< enfc pre div name */ + kCLOCK_EnfcDiv = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ENFC_CLK_PODF_SHIFT, CCM_CS2CDR_ENFC_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< enfc div name */ + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR, CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, CCM_CS2CDR_SAI2_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, CCM_CDCDR_SPDIF0_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, CCM_CDCDR_SPDIF0_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< spdif div name */ + + kCLOCK_EpdcDiv = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_EPDC_PODF_SHIFT, CCM_CHSCCDR_EPDC_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< epdc div name */ + + kCLOCK_EcspiDiv = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT, CCM_CSCDR2_ECSPI_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ecspi div name */ + kCLOCK_Lcdif1PreDiv = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF1_PRED_SHIFT, CCM_CSCDR2_LCDIF1_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 pre div name */ + + kCLOCK_CsiDiv = CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ +} clock_div_t; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ +} clock_usb_pll_config_t; + + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput0; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + bool enableClkOutput2; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */ + uint8_t loopDivider0; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = 0U, /*!< PLL ARM */ + kCLOCK_PllSys = 1U, /*!< PLL SYS */ + kCLOCK_PllUsb1 = 2U, /*!< PLL USB1 */ + kCLOCK_PllAudio = 3U, /*!< PLL Audio */ + kCLOCK_PllVideo = 4U, /*!< PLL Video */ + kCLOCK_PllEnet0 = 5U, /*!< PLL Enet0 */ + kCLOCK_PllEnet1 = 6U, /*!< PLL Enet1 */ + kCLOCK_PllEnet2 = 7U, /*!< PLL Enet2 */ + kCLOCK_PllUsb2 = 8U, /*!< PLL USB2 */ +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM MUX value. + * + * @param mux Which mux node to get, see \ref clock_mux_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetMux(clock_mux_t mux) +{ + return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux); +} + +/*! + * @brief Set CCM DIV node to certain value. + * + * @param divider Which div node to set, see \ref clock_div_t. + * @param value Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM DIV node value. + * + * @param divider Which div node to get, see \ref clock_div_t. + */ +static inline uint32_t CLOCK_GetDiv(clock_div_t divider) +{ + uint32_t value; + + value = (CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider); + return value; +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + uint32_t index = ((uint32_t)name) >> 8; + uint32_t shift = (((uint32_t)name) & 0xF) << 1; + volatile uint32_t *reg; + + assert (index <= 6); + + reg = ((volatile uint32_t *)&CCM->CCGR0) + index; + *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); +} + +/*! + * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * @param mode Which mode to enter, see \ref clock_mode_t. + */ +static inline void CLOCK_SetMode(clock_mode_t mode) +{ + CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * @note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc); + +/*! + * @brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void); + +/*! + * @brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * @param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc); + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @param osc OSC type to get frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return (PMU->LOWPWR_CTRL & PMU_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the XTAL (24M OSC) frequency based on board setting. + * + * @param freq The XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetXtalFreq(uint32_t freq) +{ + g_xtalFreq = freq; +} + +/*! + * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. + * + * @param freq The RTC XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) +{ + g_rtcXtalFreq = freq; +} + + +/*! + * @brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void); + +/*! + * @brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void); +/* @} */ + +/*! + * @name PLL/PFD operations + * @{ + */ + +/*! + * @brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void); + +/*! + * @brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void); + +/*! + * @brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void); + +/*! + * @brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); + +/*! + * @brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void); + +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd); + +/*! + * @brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); + +/*! + * @brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); + +/*! + * @brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.c new file mode 100644 index 0000000000000000000000000000000000000000..90862b0ef7719c8e9ceb5ab4b7ca05ff7bd9a905 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.c @@ -0,0 +1,207 @@ +/* +* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_common.h" +#include +#define PRINTF rt_kprintf + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned adress to real address */ +} mem_align_cb_t; + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __BKPT(0); + } +} +#elif(defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __BKPT(0); + } +} +#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ +#endif /* NDEBUG */ + +#ifndef __GIC_PRIO_BITS +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif + +#ifndef CPU_QN908X +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + SYSCON->STARTERCLR[index] = 1u << intNumber; +} +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ +#else +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + /* SYSCON->STARTERSET[index] = 1u << intNumber; */ + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + /* SYSCON->STARTERCLR[index] = 1u << intNumber; */ +} +#endif /*CPU_QN908X */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + void *p_align_addr, *p_addr = malloc(alignedsize); + + if (!p_addr) + { + return NULL; + } + + p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + + return (void *)p_align_addr; +} + +void SDK_Free(void *ptr) +{ + mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + free((void *)((uint32_t)ptr - p_cb->offset)); +} + + diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.h new file mode 100644 index 0000000000000000000000000000000000000000..8245d7750ec04c61e39f664f61bdbaf8b8861ff5 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.h @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! Function to allocate/free L1 cache aligned memory using the malloc/free. */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +void SDK_Free(void *ptr); + +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#endif +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + extern void rt_hw_interrupt_umask(int vector); + rt_hw_interrupt_umask(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + extern void rt_hw_interrupt_mask(int vector); + rt_hw_interrupt_mask(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif + } + + /*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif + } + + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.c new file mode 100644 index 0000000000000000000000000000000000000000..d16a40a06cf33b945ff0f6fd4bcd459d7e1d50b0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.c @@ -0,0 +1,778 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ecspi.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +/*! @brief ECSPI transfer state, which is used for ECSPI transactiaonl APIs' internal state. */ +enum _ecspi_transfer_states_t +{ + kECSPI_Idle = 0x0, /*!< ECSPI is idle state */ + kECSPI_Busy /*!< ECSPI is busy tranferring data. */ +}; + +/*! @brief Typedef for ecspi master interrupt handler. ecspi master and slave handle is the same. */ +typedef void (*ecspi_isr_t)(ECSPI_Type *base, ecspi_master_handle_t *ecspiHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance for ECSPI module. + * + * @param base ECSPI base address + */ +uint32_t ECSPI_GetInstance(ECSPI_Type *base); + +/*! + * @brief Sends a buffer of data bytes in non-blocking way. + * + * @param base ECSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +static void ECSPI_WriteNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Receive a buffer of data bytes in non-blocking way. + * + * @param base ECSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +static void ECSPI_ReadNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Send a piece of data for ECSPI. + * + * This function computes the number of data to be written into D register or Tx FIFO, + * and write the data into it. At the same time, this function updates the values in + * master handle structure. + * + * @param base ECSPI base pointer + * @param handle Pointer to ECSPI master handle structure. + */ +static void ECSPI_SendTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Receive a piece of data for ECSPI master. + * + * This function computes the number of data to receive from D register or Rx FIFO, + * and write the data to destination address. At the same time, this function updates + * the values in master handle structure. + * + * @param base ECSPI base pointer + * @param handle Pointer to ECSPI master handle structure. + */ +static void ECSPI_ReceiveTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! +* @brief Sets the ECSPI channel configuration structure to default values. +* +* This function is to get the channel configuration structure initialized for use in ECSPI_SetChannelConfig(). +* User may use the initialized structure unchanged in ECSPI_SetChannelConfig(), or modify +* some fields of the structure before calling ECSPI_SetChannelConfig(). +* +* @param config pointer to config structure +*/ +static void ECSPI_GetDefaultChannelConfig(ecspi_channel_config_t *config); + +/*! + * @brief Common IRQ handler for SPI. + * + * @param base SPI base pointer. + * @param instance SPI instance number. + */ +static void ECSPI_CommonIRQHandler(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Base pointer array */ +static ECSPI_Type *const s_ecspiBases[] = ECSPI_BASE_PTRS; +/*! @brief ECSPI internal handle pointer array */ +static ecspi_master_handle_t *s_ecspiHandle[ARRAY_SIZE(s_ecspiBases)]; +/*! @brief IRQ name array */ +static const IRQn_Type s_ecspiIRQ[] = ECSPI_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Clock array name */ +static const clock_ip_name_t s_ecspiClock[] = ECSPI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance. */ +static ecspi_isr_t s_ecspiMasterIsr; +/*! @brief Pointer to slave IRQ handler for each instance. */ +static ecspi_isr_t s_ecspiSlaveIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t ECSPI_GetInstance(ECSPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ecspiBases); instance++) + { + if (s_ecspiBases[instance] == base) + { + break; + } + } + assert(instance <= ARRAY_SIZE(s_ecspiBases)); + return instance; +} + +static void ECSPI_WriteNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + size_t i = 0U; + + for (i = 0U; i < size; i++) + { + if (buffer != NULL) + { + base->TXDATA = *buffer++; + } + else + { + ECSPI_WriteData(base, ECSPI_DUMMYDATA); + } + } +} + +static void ECSPI_ReadNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + if (NULL != buffer) + { + while (size--) + { + *buffer++ = ECSPI_ReadData(base); + } + } + else + { + while (size--) + { + (void)ECSPI_ReadData(base); + } + } +} + +static void ECSPI_SendTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(base); + assert(handle); + + uint32_t dataCounts = 0U; + /* Caculate the data size to send */ + dataCounts = (FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(base) - ECSPI_GetTxFifoCount(base)) < (handle->txRemainingBytes) ? + (FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(base) - ECSPI_GetTxFifoCount(base)) : + (handle->txRemainingBytes); + while (dataCounts--) + { + ECSPI_WriteNonBlocking(base, handle->txData, 1); + if (NULL != handle->txData) + { + handle->txData += 1U; + } + handle->txRemainingBytes -= 1U; + } +} + +static void ECSPI_ReceiveTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(base); + + uint32_t dataCounts = 0U; + /* Caculate the data size need to receive */ + dataCounts = + (ECSPI_GetRxFifoCount(base) < handle->rxRemainingBytes) ? ECSPI_GetRxFifoCount(base) : handle->rxRemainingBytes; + + ECSPI_ReadNonBlocking(base, handle->rxData, dataCounts); + if (NULL != handle->rxData) + { + handle->rxData += dataCounts; + } + handle->rxRemainingBytes -= dataCounts; +} +static void ECSPI_GetDefaultChannelConfig(ecspi_channel_config_t *config) +{ + config->channelMode = kECSPI_Slave; /*!< ECSPI peripheral operates in slave mode.*/ + config->clockInactiveState = kECSPI_ClockInactiveStateLow; /*!< Clock line (SCLK) inactive state */ + config->dataLineInactiveState = kECSPI_DataLineInactiveStateLow; /*!< Data line (MOSI&MISO) inactive state */ + config->chipSlectActiveState = kECSPI_ChipSelectActiveStateLow; /*!< Chip select(SS) line active state */ + config->waveForm = kECSPI_WaveFormSingle; /*!< ECSPI SS wave form */ + config->polarity = kECSPI_PolarityActiveHigh; /*!< Clock polarity */ + config->phase = kECSPI_ClockPhaseFirstEdge; /*!< clock phase */ +} + +void ECSPI_MasterGetDefaultConfig(ecspi_master_config_t *config) +{ + config->channel = kECSPI_Channel0; + config->burstLength = 8; + config->samplePeriodClock = kECSPI_spiClock; + config->baudRate_Bps = 500000; + config->chipSelectDelay = 0; + config->samplePeriod = 0; + config->txFifoThreshold = 1; + config->rxFifoThreshold = 0; + /* Default configuration of channel */ + ECSPI_GetDefaultChannelConfig(&config->channelConfig); + /*!< ECSPI peripheral operates in slave mode.*/ + config->channelConfig.channelMode = kECSPI_Master; +} + +void ECSPI_MasterInit(ECSPI_Type *base, const ecspi_master_config_t *config, uint32_t srcClock_Hz) +{ + assert(config && srcClock_Hz); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Open clock gate for SPI and open interrupt */ + CLOCK_EnableClock(s_ecspiClock[ECSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Reset control register to default value */ + ECSPI_SoftwareReset(base); + /* Config CONREG register */ + base->CONREG = ECSPI_CONREG_BURST_LENGTH(config->burstLength - 1) | ECSPI_CONREG_SMC(1) | ECSPI_CONREG_EN(1); + /* Config CONFIGREG register */ + ECSPI_SetChannelConfig(base, config->channel, &config->channelConfig); + /* Config DMAREG register */ + base->DMAREG |= + ECSPI_DMAREG_TX_THRESHOLD(config->txFifoThreshold) | ECSPI_DMAREG_RX_THRESHOLD(config->rxFifoThreshold); + /* Config PERIODREG register */ + base->PERIODREG |= ECSPI_PERIODREG_CSRC(config->samplePeriodClock) | + ECSPI_PERIODREG_SAMPLE_PERIOD(config->samplePeriod) | + ECSPI_PERIODREG_CSD_CTL(config->chipSelectDelay); + /* Set baud rate */ + ECSPI_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); +} + +void ECSPI_SlaveGetDefaultConfig(ecspi_slave_config_t *config) +{ + /* Default configuration of channel nember */ + config->channel = kECSPI_Channel0; + config->burstLength = 8; + config->txFifoThreshold = 1; + config->rxFifoThreshold = 0; + /* Set default channel configuration */ + ECSPI_GetDefaultChannelConfig(&config->channelConfig); + /* ECSPI peripheral operates in slave mode.*/ + config->channelConfig.channelMode = kECSPI_Slave; +} + +void ECSPI_SlaveInit(ECSPI_Type *base, const ecspi_slave_config_t *config) +{ + assert(base && config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Open clock gate for SPI and open interrupt */ + CLOCK_EnableClock(s_ecspiClock[ECSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset control register to default value */ + ECSPI_SoftwareReset(base); + /* Config CONREG register */ + base->CONREG = ECSPI_CONREG_BURST_LENGTH(config->burstLength - 1) | ECSPI_CONREG_EN(1); + /* Config DMAREG register */ + base->DMAREG |= + ECSPI_DMAREG_TX_THRESHOLD(config->txFifoThreshold) | ECSPI_DMAREG_RX_THRESHOLD(config->rxFifoThreshold); + /* Setup channel configuration */ + ECSPI_SetChannelConfig(base, config->channel, &config->channelConfig); +} + +void ECSPI_Deinit(ECSPI_Type *base) +{ + /* Disable ECSPI module before shutting down */ + base->CONREG &= ~ECSPI_CONREG_EN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock */ + CLOCK_DisableClock(s_ecspiClock[ECSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ECSPI_SetBaudRate(ECSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(base); + + uint8_t bestPreDividerValue = 0U, preDividerValue = 0U; + uint8_t bestPostDividerValue = 0U, postDividerValue = 0U; + uint32_t realBaudrate = 0U; + uint32_t diff = 0xFFFFFFFFU; + uint32_t min_diff = 0xFFFFFFFFU; + + for (preDividerValue = 0; (preDividerValue < 16) && diff; preDividerValue++) + { + for (postDividerValue = 0; (postDividerValue < 16) && diff; postDividerValue++) + { + realBaudrate = (srcClock_Hz / (preDividerValue + 1)) >> postDividerValue; + if (realBaudrate > baudRate_Bps) + { + diff = realBaudrate - baudRate_Bps; + if (diff < min_diff) + { + min_diff = diff; + bestPreDividerValue = preDividerValue; + bestPostDividerValue = postDividerValue; + } + } + else + { + diff = baudRate_Bps - realBaudrate; + if (diff < min_diff) + { + min_diff = diff; + bestPreDividerValue = preDividerValue; + bestPostDividerValue = postDividerValue; + } + } + } + } + + base->CONREG |= ECSPI_CONREG_PRE_DIVIDER(bestPreDividerValue) | ECSPI_CONREG_POST_DIVIDER(bestPostDividerValue); +} + +void ECSPI_SetChannelConfig(ECSPI_Type *base, ecspi_channel_source_t channel, const ecspi_channel_config_t *config) +{ + switch (channel) + { + case kECSPI_Channel0: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode); + base->CONFIGREG |= + (ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) | + ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) | + ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) | ECSPI_CONFIGREG_SS_CTL(config->waveForm) | + ECSPI_CONFIGREG_SCLK_POL(config->polarity) | ECSPI_CONFIGREG_SCLK_PHA(config->phase)); + break; + + case kECSPI_Channel1: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode) << 1; + base->CONFIGREG |= + ((ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) << 1) | + (ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) << 1) | + (ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) << 1) | + (ECSPI_CONFIGREG_SS_CTL(config->waveForm) << 1) | (ECSPI_CONFIGREG_SCLK_POL(config->polarity) << 1) | + (ECSPI_CONFIGREG_SCLK_PHA(config->phase) << 1)); + break; + + case kECSPI_Channel2: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode) << 2; + base->CONFIGREG |= + ((ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) << 2) | + (ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) << 2) | + (ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) << 2) | + (ECSPI_CONFIGREG_SS_CTL(config->waveForm) << 2) | (ECSPI_CONFIGREG_SCLK_POL(config->polarity) << 2) | + (ECSPI_CONFIGREG_SCLK_PHA(config->phase) << 2)); + break; + + case kECSPI_Channel3: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode) << 3; + base->CONFIGREG |= + ((ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) << 3) | + (ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) << 3) | + (ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) << 3) | + (ECSPI_CONFIGREG_SS_CTL(config->waveForm) << 3) | (ECSPI_CONFIGREG_SCLK_POL(config->polarity) << 3) | + (ECSPI_CONFIGREG_SCLK_PHA(config->phase) << 3)); + break; + + default: + break; + } +} + +void ECSPI_WriteBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + size_t i = 0U; + + while (i < size) + { + /* Wait for TX fifo buffer empty */ + while (!(base->STATREG & ECSPI_STATREG_TE_MASK)) + { + } + /* Write data to tx register */ + if (NULL != buffer) + { + ECSPI_WriteData(base, *buffer++); + } + else + { + ECSPI_WriteData(base, ECSPI_DUMMYDATA); + } + i++; + } +} + +static status_t ECSPI_ReadBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + assert(base); + + uint32_t state = 0U; + size_t i = 0U; + + while (i < size) + { + /* Wait for RX FIFO buffer ready */ + while (!(base->STATREG & ECSPI_STATREG_RR_MASK)) + { + /* Get status flags of ECSPI */ + state = ECSPI_GetStatusFlags(base); + /* If hardware overflow happen */ + if (ECSPI_STATREG_RO_MASK & state) + { + /* Clear overflow flag for next transfer */ + ECSPI_ClearStatusFlags(base, kECSPI_RxFifoOverFlowFlag); + return kStatus_ECSPI_HardwareOverFlow; + } + } + /* Read data from rx register */ + if (NULL != buffer) + { + *buffer++ = ECSPI_ReadData(base); + } + else + { + (void)ECSPI_ReadData(base); + } + i++; + } + return kStatus_Success; +} + +void ECSPI_MasterTransferCreateHandle(ECSPI_Type *base, + ecspi_master_handle_t *handle, + ecspi_master_callback_t callback, + void *userData) +{ + assert(base); + assert(handle); + + uint8_t instance = ECSPI_GetInstance(base); + + /* Initialize the handle */ + s_ecspiHandle[instance] = handle; + handle->callback = callback; + handle->userData = userData; + s_ecspiMasterIsr = ECSPI_MasterTransferHandleIRQ; + + /* Enable ECSPI NVIC */ + EnableIRQ(s_ecspiIRQ[instance]); +} + +status_t ECSPI_MasterTransferBlocking(ECSPI_Type *base, ecspi_transfer_t *xfer) +{ + assert(base && xfer); + + status_t state; + uint32_t burstLength = 0U; + uint32_t dataCounts = 0U; + /* Check if the argument is legal */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + /* Select ECSPI channel to current channel + * Note: + * xfer.channel must be configured before transfer, because every channel has + * it's own configuration,if don't configure this parameter, transfer channel + * will use the default channel0. + */ + ECSPI_SetChannelSelect(base, xfer->channel); + /* Caculate the data size need to be send for one burst */ + burstLength = ((base->CONREG & ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT) + 1; + dataCounts = (burstLength % 32) ? (burstLength / 32 + 1) : (burstLength / 32); + + while (xfer->dataSize > 0) + { + /* ECSPI will transmit and receive at the same time, if txData is NULL, + * instance will transmit dummy data, the dummy data can be set by user. + * if rxData is NULL, data will be read from RX FIFO buffer, but the + * data will be ignored by driver. + * Note that, txData and rxData can not be both NULL. + */ + ECSPI_WriteBlocking(base, xfer->txData, dataCounts); + if (NULL != xfer->txData) + { + xfer->txData += dataCounts; + } + state = ECSPI_ReadBlocking(base, xfer->rxData, dataCounts); + if ((kStatus_Success == state) && (NULL != xfer->rxData)) + { + xfer->rxData += dataCounts; + } + if (kStatus_ECSPI_HardwareOverFlow == state) + { + return kStatus_ECSPI_HardwareOverFlow; + } + + xfer->dataSize -= dataCounts; + } + + return kStatus_Success; +} + +status_t ECSPI_MasterTransferNonBlocking(ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_transfer_t *xfer) +{ + assert(base && handle && xfer); + + /* Check if ECSPI is busy */ + if (handle->state == kECSPI_Busy) + { + return kStatus_ECSPI_Busy; + } + + /* Check if the input arguments valid */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* Set the handle information */ + handle->channel = xfer->channel; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->transferSize = xfer->dataSize; + handle->txRemainingBytes = xfer->dataSize; + handle->rxRemainingBytes = xfer->dataSize; + + /* Set the ECSPI state to busy */ + handle->state = kECSPI_Busy; + + /* Select ECSPI channel to current channel + * Note: + * xfer.channel must be configured before transferfer, because every channel has + * it's own configuration, if don't configure this parameter, transfer channel + * will use the default channel0. + */ + ECSPI_SetChannelSelect(base, xfer->channel); + + /* First send data to Tx FIFO to start a ECSPI transfer */ + ECSPI_SendTransfer(base, handle); + + if (NULL != xfer->rxData) + { + /* Enable Rx data request interrupt and receive overflow interrupt, when data in RX FIFO buffer is greater + * than the RX_THRESHOLD, then a interrupt occurred. Only enable Rx interrupt, + * use rx interrupt to driver ECSPI transfer. + */ + ECSPI_EnableInterrupts(base, kECSPI_RxFifoReadyInterruptEnable | kECSPI_RxFifoOverFlowInterruptEnable); + } + else + { + /* Enable Tx data request interrupt, when data in TX FIFO buffer is greater + * than the TX_THRESHOLD, then a interrupt occurred. + */ + ECSPI_EnableInterrupts(base, kECSPI_TxFifoDataRequstInterruptEnable); + } + + return kStatus_Success; +} + +status_t ECSPI_MasterTransferGetCount(ECSPI_Type *base, ecspi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kStatus_ECSPI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + /* Return remaing bytes in different cases */ + if (handle->rxData) + { + *count = handle->transferSize - handle->rxRemainingBytes; + } + else + { + *count = handle->transferSize - handle->txRemainingBytes; + } + } + + return status; +} + +void ECSPI_MasterTransferAbort(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(handle); + + /* Stop interrupts */ + if (NULL != handle->rxData) + { + ECSPI_DisableInterrupts(base, kECSPI_RxFifoReadyInterruptEnable | kECSPI_RxFifoOverFlowInterruptEnable); + } + else + { + ECSPI_DisableInterrupts(base, kECSPI_TxFifoDataRequstInterruptEnable); + } + /* Transfer finished, set the state to Done*/ + handle->state = kECSPI_Idle; + + /* Clear the internal state */ + handle->rxRemainingBytes = 0; + handle->txRemainingBytes = 0; +} + +void ECSPI_MasterTransferHandleIRQ(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(handle); + + /* If hardware overflow happens */ + if (base->STATREG & ECSPI_STATREG_RO_MASK) + { + /* Clear overflow flag for next transfer */ + ECSPI_ClearStatusFlags(base, kECSPI_RxFifoOverFlowFlag); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_ECSPI_HardwareOverFlow, handle->userData); + } + } + /* If need to receive data, do a receive */ + if (handle->rxRemainingBytes) + { + ECSPI_ReceiveTransfer(base, handle); + } + + /* We always need to send a data to make the ECSPI run */ + if (handle->txRemainingBytes) + { + ECSPI_SendTransfer(base, handle); + } + + /* All the transfer finished */ + if ((handle->txRemainingBytes == 0) && (handle->rxRemainingBytes == 0)) + { + /* Complete the transfer */ + ECSPI_MasterTransferAbort(base, handle); + + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } +} + +void ECSPI_SlaveTransferCreateHandle(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + ecspi_slave_callback_t callback, + void *userData) +{ + assert(handle); + + /* Slave create handle share same logic with master create handle, the only difference + is the Isr pointer. */ + ECSPI_MasterTransferCreateHandle(base, handle, callback, userData); + s_ecspiSlaveIsr = ECSPI_SlaveTransferHandleIRQ; +} + +void ECSPI_SlaveTransferHandleIRQ(ECSPI_Type *base, ecspi_slave_handle_t *handle) +{ + assert(handle); + /* If hardware overflow happens */ + if (base->STATREG & ECSPI_STATREG_RO_MASK) + { + /* Clear overflow flag for next transfer */ + ECSPI_ClearStatusFlags(base, kECSPI_RxFifoOverFlowFlag); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_ECSPI_HardwareOverFlow, handle->userData); + } + } + /* If needs to receive data, do a receive */ + if (handle->rxRemainingBytes) + { + ECSPI_ReceiveTransfer(base, handle); + } + + /* We always need to send a data to make the ECSPI run */ + if (handle->txRemainingBytes) + { + ECSPI_SendTransfer(base, handle); + } + + /* All the transfer finished */ + if ((handle->txRemainingBytes == 0) && (handle->rxRemainingBytes == 0)) + { + /* Complete the transfer */ + ECSPI_SlaveTransferAbort(base, handle); + + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } +} + +static void ECSPI_CommonIRQHandler(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + if (ECSPI_IsMaster(base, handle->channel)) + { + s_ecspiMasterIsr(base, handle); + } + else + { + s_ecspiSlaveIsr(base, handle); + } +} + +#if defined(ECSPI1) +void ECSPI1_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[1]); + ECSPI_CommonIRQHandler(ECSPI1, s_ecspiHandle[1]); +} +#endif /* ECSPI1 */ + +#if defined(ECSPI2) +void ECSPI2_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[2]); + ECSPI_CommonIRQHandler(ECSPI2, s_ecspiHandle[2]); +} +#endif /* ECSPI2 */ + +#if defined(ECSPI3) +void ECSPI3_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[3]); + ECSPI_CommonIRQHandler(ECSPI3, s_ecspiHandle[3]); +} +#endif /* ECSPI3 */ + +#if defined(ECSPI4) +void ECSPI4_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[4]); + ECSPI_CommonIRQHandler(ECSPI4, s_ecspiHandle[4]); +} +#endif /* ECSPI4 */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.h new file mode 100644 index 0000000000000000000000000000000000000000..b5885572dab51b05fc1294fdec7191071c9c5905 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.h @@ -0,0 +1,749 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_ECSPI_H_ +#define _FSL_ECSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ecspi_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ECSPI driver version 2.0.0. */ +#define FSL_ECSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#ifndef ECSPI_DUMMYDATA +/*! @brief ECSPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define ECSPI_DUMMYDATA (0xFFFFFFFFU) +#endif + +/*! @brief Return status for the ECSPI driver. */ +enum _ecspi_status +{ + kStatus_ECSPI_Busy = MAKE_STATUS(kStatusGroup_ECSPI, 0), /*!< ECSPI bus is busy */ + kStatus_ECSPI_Idle = MAKE_STATUS(kStatusGroup_ECSPI, 1), /*!< ECSPI is idle */ + kStatus_ECSPI_Error = MAKE_STATUS(kStatusGroup_ECSPI, 2), /*!< ECSPI error */ + kStatus_ECSPI_HardwareOverFlow = MAKE_STATUS(kStatusGroup_ECSPI, 3), /*!< ECSPI hardware overflow */ +}; + +/*! @brief ECSPI clock polarity configuration. */ +typedef enum _ecspi_clock_polarity +{ + kECSPI_PolarityActiveHigh = 0x0U, /*!< Active-high ECSPI polarity high (idles low). */ + kECSPI_PolarityActiveLow, /*!< Active-low ECSPI polarity low (idles high). */ +} ecspi_clock_polarity_t; + +/*! @brief ECSPI clock phase configuration. */ +typedef enum _ecspi_clock_phase +{ + kECSPI_ClockPhaseFirstEdge = + 0x0U, /*!< First edge on SPSCK occurs at the middle of the first cycle of a data transfer. */ + kECSPI_ClockPhaseSecondEdge, /*!< First edge on SPSCK occurs at the start of the first cycle of a data transfer. */ +} ecspi_clock_phase_t; + +/*! @brief ECSPI interrupt sources. */ +enum _ecspi_interrupt_enable +{ + kECSPI_TxfifoEmptyInterruptEnable = ECSPI_INTREG_TEEN_MASK, /*!< Transmit FIFO buffer empty interrupt */ + kECSPI_TxFifoDataRequstInterruptEnable = ECSPI_INTREG_TDREN_MASK, /*!< Transmit FIFO data requst interrupt */ + kECSPI_TxFifoFullInterruptEnable = ECSPI_INTREG_TFEN_MASK, /*!< Transmit FIFO full interrupt */ + kECSPI_RxFifoReadyInterruptEnable = ECSPI_INTREG_RREN_MASK, /*!< Receiver FIFO ready interrupt */ + kECSPI_RxFifoDataRequstInterruptEnable = ECSPI_INTREG_RDREN_MASK, /*!< Receiver FIFO data requst interrupt */ + kECSPI_RxFifoFullInterruptEnable = ECSPI_INTREG_RFEN_MASK, /*!< Receiver FIFO full interrupt */ + kECSPI_RxFifoOverFlowInterruptEnable = ECSPI_INTREG_ROEN_MASK, /*!< Receiver FIFO buffer overflow interrupt */ + kECSPI_TransferCompleteInterruptEnable = ECSPI_INTREG_TCEN_MASK, /*!< Transfer complete interrupt */ + kECSPI_AllInterruptEnable = (ECSPI_INTREG_TEEN_MASK | ECSPI_INTREG_TDREN_MASK | ECSPI_INTREG_TFEN_MASK | + ECSPI_INTREG_RREN_MASK | ECSPI_INTREG_RDREN_MASK | ECSPI_INTREG_RFEN_MASK | + ECSPI_INTREG_ROEN_MASK | ECSPI_INTREG_TCEN_MASK), /*!< All interrupt */ +}; + +/*! @brief ECSPI status flags. */ +enum _ecspi_flags +{ + kECSPI_TxfifoEmptyFlag = ECSPI_STATREG_TE_MASK, /*!< Transmit FIFO buffer empty flag */ + kECSPI_TxFifoDataRequstFlag = ECSPI_STATREG_TDR_MASK, /*!< Transmit FIFO data requst flag */ + kECSPI_TxFifoFullFlag = ECSPI_STATREG_TF_MASK, /*!< Transmit FIFO full flag */ + kECSPI_RxFifoReadyFlag = ECSPI_STATREG_RR_MASK, /*!< Receiver FIFO ready flag */ + kECSPI_RxFifoDataRequstFlag = ECSPI_STATREG_RDR_MASK, /*!< Receiver FIFO data requst flag */ + kECSPI_RxFifoFullFlag = ECSPI_STATREG_RF_MASK, /*!< Receiver FIFO full flag */ + kECSPI_RxFifoOverFlowFlag = ECSPI_STATREG_RO_MASK, /*!< Receiver FIFO buffer overflow flag */ + kECSPI_TransferCompleteFlag = ECSPI_STATREG_TC_MASK, /*!< Transfer complete flag */ +}; +/*! @brief ECSPI DMA enable.*/ +enum _ecspi_dma_enable_t +{ + kECSPI_TxDmaEnable = ECSPI_DMAREG_TEDEN_MASK, /*!< Tx DMA request source */ + kECSPI_RxDmaEnable = ECSPI_DMAREG_RXDEN_MASK, /*!< Rx DMA request source */ + kECSPI_DmaAllEnable = (ECSPI_DMAREG_TEDEN_MASK | ECSPI_DMAREG_RXDEN_MASK) /*!< All DMA request source*/ +}; + +/*! @brief ECSPI SPI_RDY signal configuration. */ +typedef enum _ecspi_data_ready +{ + kECSPI_DataReadyIgnore = 0x0U, /*!< SPI_RDY signal is ignored */ + kECSPI_DataReadyFallingEdge, /*!< SPI_RDY signal will be triggerd by the falling edge */ + kECSPI_DataReadyLowLevel, /*!< SPI_RDY signal will be triggerd by a low level */ +} ecspi_Data_ready_t; + +/*! @brief ECSPI channel select source. */ +typedef enum _ecspi_channel_source +{ + kECSPI_Channel0 = 0x0U, /*!< Channel 0 is selectd */ + kECSPI_Channel1, /*!< Channel 1 is selectd */ + kECSPI_Channel2, /*!< Channel 2 is selectd */ + kECSPI_Channel3, /*!< Channel 3 is selectd */ +} ecspi_channel_source_t; + +/*! @brief ECSPI master or slave mode configuration. */ +typedef enum _ecspi_master_slave_mode +{ + kECSPI_Slave = 0U, /*!< ECSPI peripheral operates in slave mode.*/ + kECSPI_Master, /*!< ECSPI peripheral operates in master mode.*/ +} ecspi_master_slave_mode_t; + +/*! @brief ECSPI data line inactive state configuration. */ +typedef enum _ecspi_data_line_inactive_state_t +{ + kECSPI_DataLineInactiveStateHigh = 0x0U, /*!< The data line inactive state stays high. */ + kECSPI_DataLineInactiveStateLow, /*!< The data line inactive state stays low. */ +} ecspi_data_line_inactive_state_t; + +/*! @brief ECSPI clock inactive state configuration. */ +typedef enum _ecspi_clock_inactive_state_t +{ + kECSPI_ClockInactiveStateLow = 0x0U, /*!< The SCLK inactive state stays low. */ + kECSPI_ClockInactiveStateHigh, /*!< The SCLK inactive state stays high. */ +} ecspi_clock_inactive_state_t; + +/*! @brief ECSPI active state configuration.*/ +typedef enum _ecspi_chip_select_active_state_t +{ + kECSPI_ChipSelectActiveStateLow = 0x0U, /*!< The SS signal line active stays low. */ + kECSPI_ChipSelectActiveStateHigh, /*!< The SS signal line active stays high. */ +} ecspi_chip_select_active_state_t; + +/*! @brief ECSPI wave form configuration.*/ +typedef enum _ecspi_wave_form_t +{ + kECSPI_WaveFormSingle = 0x0U, /*!< The wave form for signal burst */ + kECSPI_WaveFormMultiple, /*!< The wave form for multiple burst */ +} ecspi_wave_form_t; + +/*! @brief ECSPI sample period clock configuration.*/ +typedef enum _ecspi_sample_period_clock_source +{ + kECSPI_spiClock = 0x0U, /*!< The sample period clock source is SCLK. */ + kECSPI_lowFreqClock, /*!< The sample seriod clock source is low_frequency reference clock(32.768 kHz). */ +} ecspi_sample_period_clock_source_t; + +/*! @brief ECSPI user channel configure structure.*/ +typedef struct _ecspi_channel_config +{ + ecspi_master_slave_mode_t channelMode; /*!< Channel mode */ + ecspi_clock_inactive_state_t clockInactiveState; /*!< Clock line (SCLK) inactive state */ + ecspi_data_line_inactive_state_t dataLineInactiveState; /*!< Data line (MOSI&MISO) inactive state */ + ecspi_chip_select_active_state_t chipSlectActiveState; /*!< Chip select(SS) line active state */ + ecspi_wave_form_t waveForm; /*!< Wave form */ + ecspi_clock_polarity_t polarity; /*!< Clock polarity */ + ecspi_clock_phase_t phase; /*!< Clock phase */ +} ecspi_channel_config_t; + +/*! @brief ECSPI master configure structure.*/ +typedef struct _ecspi_master_config +{ + ecspi_channel_source_t channel; /*!< Channel number */ + ecspi_channel_config_t channelConfig; /*!< Channel configuration */ + ecspi_sample_period_clock_source_t samplePeriodClock; /*!< Sample period clock source */ + + uint8_t burstLength; /*!< Burst length */ + uint8_t chipSelectDelay; /*!< SS delay time */ + uint16_t samplePeriod; /*!< Sample period */ + uint8_t txFifoThreshold; /*!< TX Threshold */ + uint8_t rxFifoThreshold; /*!< RX Threshold */ + uint32_t baudRate_Bps; /*!< ECSPI baud rate for master mode */ +} ecspi_master_config_t; + +/*! @brief ECSPI slave configure structure.*/ +typedef struct _ecspi_slave_config +{ + ecspi_channel_source_t channel; /*Channel number */ + uint8_t burstLength; /*!< Burst length */ + uint8_t txFifoThreshold; /*!< TX Threshold */ + uint8_t rxFifoThreshold; /*!< RX Threshold */ + ecspi_channel_config_t channelConfig; /*!< Channel configuration */ +} ecspi_slave_config_t; + +/*! @brief ECSPI transfer structure */ +typedef struct _ecspi_transfer +{ + uint32_t *txData; /*!< Send buffer */ + uint32_t *rxData; /*!< Receive buffer */ + size_t dataSize; /*!< Transfer bytes */ + ecspi_channel_source_t channel; /*!< ECSPI channel select */ +} ecspi_transfer_t; + +typedef struct _ecspi_master_handle ecspi_master_handle_t; +/*! @brief Slave handle is the same with master handle */ +typedef ecspi_master_handle_t ecspi_slave_handle_t; + +/*! @brief ECSPI master callback for finished transmit */ +typedef void (*ecspi_master_callback_t)(ECSPI_Type *base, + ecspi_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief ECSPI slave callback for finished transmit */ +typedef void (*ecspi_slave_callback_t)(ECSPI_Type *base, ecspi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief ECSPI master handle structure */ +struct _ecspi_master_handle +{ + ecspi_channel_source_t channel; /*!< Channel number */ + uint32_t *volatile txData; /*!< Transfer buffer */ + uint32_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Send data remaining in bytes */ + volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes */ + volatile uint32_t state; /*!< ECSPI internal state */ + size_t transferSize; /*!< Bytes to be transferred */ + ecspi_master_callback_t callback; /*!< ECSPI callback */ + void *userData; /*!< Callback parameter */ +}; + +#if defined(__cplusplus) +extern "C" { +#endif +/******************************************************************************* + * APIs + ******************************************************************************/ +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the ECSPI configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in ECSPI_MasterInit(). + * User may use the initialized structure unchanged in ECSPI_MasterInit, or modify + * some fields of the structure before calling ECSPI_MasterInit. After calling this API, + * the master is ready to transfer. + * Example: + @code + ecspi_master_config_t config; + ECSPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to config structure + */ +void ECSPI_MasterGetDefaultConfig(ecspi_master_config_t *config); + +/*! + * @brief Initializes the ECSPI with configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by ECSPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + ecspi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + ECSPI_MasterInit(ECSPI0, &config); + @endcode + * + * @param base ECSPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +void ECSPI_MasterInit(ECSPI_Type *base, const ecspi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the ECSPI configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in ECSPI_SlaveInit(). + * User may use the initialized structure unchanged in ECSPI_SlaveInit(), or modify + * some fields of the structure before calling ECSPI_SlaveInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + ecspi_Slaveconfig_t config; + ECSPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to config structure + */ +void ECSPI_SlaveGetDefaultConfig(ecspi_slave_config_t *config); + +/*! + * @brief Initializes the ECSPI with configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by ECSPI_SlaveGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + ecspi_Salveconfig_t config = { + .baudRate_Bps = 400000, + ... + }; + ECSPI_SlaveInit(ECSPI1, &config); + @endcode + * + * @param base ECSPI base pointer + * @param config pointer to master configuration structure + */ +void ECSPI_SlaveInit(ECSPI_Type *base, const ecspi_slave_config_t *config); + +/*! + * @brief De-initializes the ECSPI. + * + * Calling this API resets the ECSPI module, gates the ECSPI clock. + * The ECSPI module can't work unless calling the ECSPI_MasterInit/ECSPI_SlaveInit to initialize module. + * + * @param base ECSPI base pointer + */ +void ECSPI_Deinit(ECSPI_Type *base); + +/*! + * @brief Enables or disables the ECSPI. + * + * @param base ECSPI base pointer + * @param enable pass true to enable module, false to disable module + */ +static inline void ECSPI_Enable(ECSPI_Type *base, bool enable) +{ + if (enable) + { + base->CONREG |= ECSPI_CONREG_EN_MASK; + } + else + { + base->CONREG &= ~ECSPI_CONREG_EN_MASK; + } +} +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base ECSPI base pointer + * @return ECSPI Status, use status flag to AND #_ecspi_flags could get the related status. + */ +static inline uint32_t ECSPI_GetStatusFlags(ECSPI_Type *base) +{ + return (base->STATREG); +} + +/*! + * @brief Clear the status flag. + * + * @param base ECSPI base pointer + * @param mask ECSPI Status, use status flag to AND #_ecspi_flags could get the related status. + */ +static inline void ECSPI_ClearStatusFlags(ECSPI_Type *base, uint32_t mask) +{ + base->STATREG |= mask; +} +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the ECSPI. + * + * @param base ECSPI base pointer + * @param mask ECSPI interrupt source. The parameter can be any combination of the following values: + * @arg kECSPI_TxfifoEmptyInterruptEnable + * @arg kECSPI_TxFifoDataRequstInterruptEnable + * @arg kECSPI_TxFifoFullInterruptEnable + * @arg kECSPI_RxFifoReadyInterruptEnable + * @arg kECSPI_RxFifoDataRequstInterruptEnable + * @arg kECSPI_RxFifoFullInterruptEnable + * @arg kECSPI_RxFifoOverFlowInterruptEnable + * @arg kECSPI_TransferCompleteInterruptEnable + * @arg kECSPI_AllInterruptEnable + */ +static inline void ECSPI_EnableInterrupts(ECSPI_Type *base, uint32_t mask) +{ + base->INTREG |= mask; +} + +/*! + * @brief Disables the interrupt for the ECSPI. + * + * @param base ECSPI base pointer + * @param mask ECSPI interrupt source. The parameter can be any combination of the following values: + * @arg kECSPI_TxfifoEmptyInterruptEnable + * @arg kECSPI_TxFifoDataRequstInterruptEnable + * @arg kECSPI_TxFifoFullInterruptEnable + * @arg kECSPI_RxFifoReadyInterruptEnable + * @arg kECSPI_RxFifoDataRequstInterruptEnable + * @arg kECSPI_RxFifoFullInterruptEnable + * @arg kECSPI_RxFifoOverFlowInterruptEnable + * @arg kECSPI_TransferCompleteInterruptEnable + * @arg kECSPI_AllInterruptEnable + */ +static inline void ECSPI_DisableInterrupts(ECSPI_Type *base, uint32_t mask) +{ + base->INTREG &= ~(mask); +} +/*! @} */ + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Software reset. + * + * @param base ECSPI base pointer + */ +static inline void ECSPI_SoftwareReset(ECSPI_Type *base) +{ + /* Disables the block and resets the internal logic with the exception of the ECSPI control register */ + base->CONREG &= ~ECSPI_CONREG_EN_MASK; + /* Software reset can not reset the control register, so clear the control register manually */ + base->CONREG = 0x0U; +} +/*! @} */ + +/*! + * @name Channel mode check + * @{ + */ + +/*! + * @brief Mode check + * + * @param base ECSPI base pointer + * @param channel ECSPI channel source + * @return mode of channel + */ +static inline bool ECSPI_IsMaster(ECSPI_Type *base, ecspi_channel_source_t channel) +{ + return (bool)(((base->CONREG & ECSPI_CONREG_CHANNEL_MODE_MASK) >> (ECSPI_CONREG_CHANNEL_MODE_SHIFT + channel)) & + 0x1U); +} +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DMA source for ECSPI. + * + * @param base ECSPI base pointer + * @param source ECSPI DMA source. + * @param enable True means enable DMA, false means disable DMA + */ +static inline void ECSPI_EnableDMA(ECSPI_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->DMAREG |= mask; + } + else + { + base->DMAREG &= ~mask; + } +} +/*! @} */ + +/*! + * @name FIFO Operation + * @{ + */ + +/*! + * @brief Get the Tx FIFO data count. + * + * @param base ECSPI base pointer. + * @return the number of words in Tx FIFO buffer. + */ +static inline uint8_t ECSPI_GetTxFifoCount(ECSPI_Type *base) +{ + return (uint8_t)((base->TESTREG & ECSPI_TESTREG_TXCNT_MASK) >> ECSPI_TESTREG_TXCNT_SHIFT); +} + +/*! + * @brief Get the Rx FIFO data count. + * + * @param base ECSPI base pointer. + * @return the number of words in Rx FIFO buffer. + */ +static inline uint8_t ECSPI_GetRxFifoCount(ECSPI_Type *base) +{ + return (uint8_t)((base->TESTREG & ECSPI_TESTREG_RXCNT_MASK) >> ECSPI_TESTREG_RXCNT_SHIFT); +} +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Set channel select for transfer. + * + * @param base ECSPI base pointer + * @param channel Channel source. + */ +static inline void ECSPI_SetChannelSelect(ECSPI_Type *base, ecspi_channel_source_t channel) +{ + /* Clear Channel select bits in CONREG register */ + uint32_t temp = base->CONREG & (~(ECSPI_CONREG_CHANNEL_SELECT_MASK)); + /* Set channel select bits */ + base->CONREG = (temp | ECSPI_CONREG_CHANNEL_SELECT(channel)); +} +/*! + * @brief Set channel select configuration for transfer. + * + * The purpose of this API is to set the channel will be use to transfer. + * User may use this API after instance has been initialized or before transfer start. + * The configuration structure #_ecspi_channel_config_ can be filled by user from scratch. + * After calling this API, user can select this channel as transfer channel. + * + * @param base ECSPI base pointer + * @param channel Channel source. + * @param config Configuration struct of channel + */ +void ECSPI_SetChannelConfig(ECSPI_Type *base, ecspi_channel_source_t channel, const ecspi_channel_config_t *config); + +/*! + * @brief Sets the baud rate for ECSPI transfer. This is only used in master. + * + * @param base ECSPI base pointer + * @param baudRate_Bps baud rate needed in Hz. + * @param srcClock_Hz ECSPI source clock frequency in Hz. + */ +void ECSPI_SetBaudRate(ECSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a buffer of data bytes using a blocking method. + * + * @note This function blocks via polling until all bytes have been sent. + * + * @param base ECSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +void ECSPI_WriteBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Writes a data into the ECSPI data register. + * + * @param base ECSPI base pointer + * @param data Data needs to be write. + */ +static inline void ECSPI_WriteData(ECSPI_Type *base, uint32_t data) +{ + base->TXDATA = data; +} + +/*! + * @brief Gets a data from the ECSPI data register. + * + * @param base ECSPI base pointer + * @return Data in the register. + */ +static inline uint32_t ECSPI_ReadData(ECSPI_Type *base) +{ + return (uint32_t)(base->RXDATA); +} +/*! @} */ + +/*! + * @name Transactional + * @{ + */ +/*! + * @brief Initializes the ECSPI master handle. + * + * This function initializes the ECSPI master handle which can be used for other ECSPI master transactional APIs. + * Usually, + * for a specified ECSPI instance, call this API once to get the initialized handle. + * + * @param base ECSPI peripheral base address. + * @param handle ECSPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void ECSPI_MasterTransferCreateHandle(ECSPI_Type *base, + ecspi_master_handle_t *handle, + ecspi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t ECSPI_MasterTransferBlocking(ECSPI_Type *base, ecspi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking ECSPI interrupt transfer. + * + * @note The API immediately returns after transfer initialization is finished. + * @note If ECSPI transfer data frame size is 16 bits, the transfer size cannot be an odd number. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_master_handle_t structure which stores the transfer state + * @param xfer pointer to ecspi_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_ECSPI_Busy ECSPI is not idle, is running another transfer. + */ +status_t ECSPI_MasterTransferNonBlocking(ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_transfer_t *xfer); + +/*! + * @brief Gets the bytes of the ECSPI interrupt transferred. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + * @param count Transferred bytes of ECSPI master. + * @retval kStatus_ECSPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t ECSPI_MasterTransferGetCount(ECSPI_Type *base, ecspi_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an ECSPI transfer using interrupt. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + */ +void ECSPI_MasterTransferAbort(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the ECSPI. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_master_handle_t structure which stores the transfer state. + */ +void ECSPI_MasterTransferHandleIRQ(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Initializes the ECSPI slave handle. + * + * This function initializes the ECSPI slave handle which can be used for other ECSPI slave transactional APIs. Usually, + * for a specified ECSPI instance, call this API once to get the initialized handle. + * + * @param base ECSPI peripheral base address. + * @param handle ECSPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void ECSPI_SlaveTransferCreateHandle(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + ecspi_slave_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking ECSPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_master_handle_t structure which stores the transfer state + * @param xfer pointer to ecspi_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_ECSPI_Busy ECSPI is not idle, is running another transfer. + */ +static inline status_t ECSPI_SlaveTransferNonBlocking(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + ecspi_transfer_t *xfer) +{ + return ECSPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the bytes of the ECSPI interrupt transferred. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + * @param count Transferred bytes of ECSPI slave. + * @retval kStatus_ECSPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +static inline status_t ECSPI_SlaveTransferGetCount(ECSPI_Type *base, ecspi_slave_handle_t *handle, size_t *count) +{ + return ECSPI_MasterTransferGetCount(base, handle, count); +} + +/*! + * @brief Aborts an ECSPI slave transfer using interrupt. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + */ +static inline void ECSPI_SlaveTransferAbort(ECSPI_Type *base, ecspi_slave_handle_t *handle) +{ + ECSPI_MasterTransferAbort(base, handle); +} + +/*! + * @brief Interrupts a handler for the ECSPI slave. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_slave_handle_t structure which stores the transfer state + */ +void ECSPI_SlaveTransferHandleIRQ(ECSPI_Type *base, ecspi_slave_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_ECSPI_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.c new file mode 100644 index 0000000000000000000000000000000000000000..f0a6f0aaa8d88b70c136f292f4b1f9fb175b517f --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_elcdif.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for ELCDIF module. + * + * @param base ELCDIF peripheral base address + */ +static uint32_t ELCDIF_GetInstance(LCDIF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to ELCDIF bases for each instance. */ +static LCDIF_Type *const s_elcdifBases[] = LCDIF_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to eLCDIF apb_clk for each instance. */ +static const clock_ip_name_t s_elcdifApbClocks[] = LCDIF_CLOCKS; +#if defined(LCDIF_PERIPH_CLOCKS) +/*! @brief Pointers to eLCDIF pix_clk for each instance. */ +static const clock_ip_name_t s_elcdifPixClocks[] = LCDIF_PERIPH_CLOCKS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief The control register value to select different pixel format. */ +elcdif_pixel_format_reg_t s_pixelFormatReg[] = { + /* kELCDIF_PixelFormatRAW8 */ + {/* Register CTRL. */ + LCDIF_CTRL_WORD_LENGTH(1U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, + /* kELCDIF_PixelFormatRGB565 */ + {/* Register CTRL. */ + LCDIF_CTRL_WORD_LENGTH(0U) | LCDIF_CTRL_DATA_FORMAT_16_BIT(1U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, + /* kELCDIF_PixelFormatRGB666 */ + {/* Register CTRL. */ + LCDIF_CTRL_WORD_LENGTH(3U) | LCDIF_CTRL_DATA_FORMAT_24_BIT(1U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)}, + /* kELCDIF_PixelFormatRGB888 */ + {/* Register CTRL. 24-bit. */ + LCDIF_CTRL_WORD_LENGTH(3U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)}, +}; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t ELCDIF_GetInstance(LCDIF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_elcdifBases); instance++) + { + if (s_elcdifBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_elcdifBases)); + + return instance; +} + +void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config) +{ + assert(config); + assert(config->pixelFormat < ARRAY_SIZE(s_pixelFormatReg)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = ELCDIF_GetInstance(base); + /* Enable the clock. */ + CLOCK_EnableClock(s_elcdifApbClocks[instance]); +#if defined(LCDIF_PERIPH_CLOCKS) + CLOCK_EnableClock(s_elcdifPixClocks[instance]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset. */ + ELCDIF_Reset(base); + + base->CTRL = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl | (uint32_t)(config->dataBus) | + LCDIF_CTRL_DOTCLK_MODE_MASK | /* RGB mode. */ + LCDIF_CTRL_BYPASS_COUNT_MASK | /* Keep RUN bit set. */ + LCDIF_CTRL_MASTER_MASK; + + base->CTRL1 = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl1; + + base->TRANSFER_COUNT = ((uint32_t)config->panelHeight << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) | + ((uint32_t)config->panelWidth << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT); + + base->VDCTRL0 = LCDIF_VDCTRL0_ENABLE_PRESENT_MASK | /* Data enable signal. */ + LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK | /* VSYNC period in the unit of display clock. */ + LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK | /* VSYNC pulse width in the unit of display clock. */ + (uint32_t)config->polarityFlags | (uint32_t)config->vsw; + + base->VDCTRL1 = config->vsw + config->panelHeight + config->vfp + config->vbp; + base->VDCTRL2 = ((uint32_t)config->hsw << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) | + ((uint32_t)(config->hfp + config->hbp + config->panelWidth + config->hsw)) + << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT; + + base->VDCTRL3 = (((uint32_t)config->hbp + config->hsw) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) | + (((uint32_t)config->vbp + config->vsw) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT); + + base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK | + ((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT); + + base->CUR_BUF = config->bufferAddr; + base->NEXT_BUF = config->bufferAddr; +} + +void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config) +{ + assert(config); + + config->panelWidth = 480U; + config->panelHeight = 272U; + config->hsw = 41; + config->hfp = 4; + config->hbp = 8; + config->vsw = 10; + config->vfp = 4; + config->vbp = 2; + config->polarityFlags = kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow | + kELCDIF_DriveDataOnFallingClkEdge; + config->bufferAddr = 0U; + config->pixelFormat = kELCDIF_PixelFormatRGB888; + config->dataBus = kELCDIF_DataBus24Bit; +} + +void ELCDIF_Deinit(LCDIF_Type *base) +{ + ELCDIF_Reset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = ELCDIF_GetInstance(base); +/* Disable the clock. */ +#if defined(LCDIF_PERIPH_CLOCKS) + CLOCK_DisableClock(s_elcdifPixClocks[instance]); +#endif + CLOCK_DisableClock(s_elcdifApbClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ELCDIF_RgbModeStop(LCDIF_Type *base) +{ + base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK; + + /* Wait for data transfer finished. */ + while (base->CTRL & LCDIF_CTRL_DOTCLK_MODE_MASK) + { + } +} + +void ELCDIF_Reset(LCDIF_Type *base) +{ + volatile uint32_t i = 0x100; + + /* Disable the clock gate. */ + base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK; + /* Confirm the clock gate is disabled. */ + while (base->CTRL & LCDIF_CTRL_CLKGATE_MASK) + { + } + + /* Reset the block. */ + base->CTRL_SET = LCDIF_CTRL_SFTRST_MASK; + /* Confirm the reset bit is set. */ + while (!(base->CTRL & LCDIF_CTRL_SFTRST_MASK)) + { + } + + /* Delay for the reset. */ + while (i--) + { + } + + /* Bring the module out of reset. */ + base->CTRL_CLR = LCDIF_CTRL_SFTRST_MASK; + /* Disable the clock gate. */ + base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK; +} + +void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config) +{ + assert(config); + + base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat); + base->AS_BUF = config->bufferAddr; + base->AS_NEXT_BUF = config->bufferAddr; +} + +void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config) +{ + assert(config); + uint32_t reg; + + reg = base->AS_CTRL; + reg &= ~(LCDIF_AS_CTRL_ALPHA_INVERT_MASK | LCDIF_AS_CTRL_ROP_MASK | LCDIF_AS_CTRL_ALPHA_MASK | + LCDIF_AS_CTRL_ALPHA_CTRL_MASK); + reg |= (LCDIF_AS_CTRL_ROP(config->ropMode) | LCDIF_AS_CTRL_ALPHA(config->alpha) | + LCDIF_AS_CTRL_ALPHA_CTRL(config->alphaMode)); + + if (config->invertAlpha) + { + reg |= LCDIF_AS_CTRL_ALPHA_INVERT_MASK; + } + + base->AS_CTRL = reg; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.h new file mode 100644 index 0000000000000000000000000000000000000000..84d6b2aa9cd8a1b8829c1a88140dfe5b8534666c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.h @@ -0,0 +1,659 @@ +/* + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ELCDIF_H_ +#define _FSL_ELCDIF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup elcdif + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eLCDIF driver version */ +#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/* All IRQ flags in CTRL1 register. */ +#define ELCDIF_CTRL1_IRQ_MASK \ + (LCDIF_CTRL1_BM_ERROR_IRQ_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_MASK | \ + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) + +/* All IRQ enable control bits in CTRL1 register. */ +#define ELCDIF_CTRL1_IRQ_EN_MASK \ + (LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK | \ + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) + +/* All IRQ flags in AS_CTRL register. */ +#define ELCDIF_AS_CTRL_IRQ_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) + +/* All IRQ enable control bits in AS_CTRL register. */ +#define ELCDIF_AS_CTRL_IRQ_EN_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) + +#if ((ELCDIF_CTRL1_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_MASK) || (ELCDIF_AS_CTRL_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_EN_MASK)) +#error Interrupt bits overlap, need to update the interrupt functions. +#endif + +/*! + * @brief eLCDIF signal polarity flags + */ +enum _elcdif_polarity_flags +{ + kELCDIF_VsyncActiveLow = 0U, /*!< VSYNC active low. */ + kELCDIF_VsyncActiveHigh = LCDIF_VDCTRL0_VSYNC_POL_MASK, /*!< VSYNC active high. */ + kELCDIF_HsyncActiveLow = 0U, /*!< HSYNC active low. */ + kELCDIF_HsyncActiveHigh = LCDIF_VDCTRL0_HSYNC_POL_MASK, /*!< HSYNC active high. */ + kELCDIF_DataEnableActiveLow = 0U, /*!< Data enable line active low. */ + kELCDIF_DataEnableActiveHigh = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */ + kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data + on rising clock edge. */ + kELCDIF_DriveDataOnRisingClkEdge = LCDIF_VDCTRL0_DOTCLK_POL_MASK, /*!< Drive data on falling + clock edge, capture data + on rising clock edge. */ +}; + +/*! + * @brief The eLCDIF interrupts to enable. + */ +enum _elcdif_interrupt_enable +{ + kELCDIF_BusMasterErrorInterruptEnable = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK, /*!< Bus master error interrupt. */ + kELCDIF_TxFifoOverflowInterruptEnable = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK, /*!< TXFIFO overflow interrupt. */ + kELCDIF_TxFifoUnderflowInterruptEnable = LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK, /*!< TXFIFO underflow interrupt. */ + kELCDIF_CurFrameDoneInterruptEnable = + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK, /*!< Interrupt when hardware enters vertical blanking state. */ + kELCDIF_VsyncEdgeInterruptEnable = + LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */ + kELCDIF_SciSyncOnInterruptEnable = + LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */ +}; + +/*! + * @brief The eLCDIF interrupt status flags. + */ +enum _elcdif_interrupt_flags +{ + kELCDIF_BusMasterError = LCDIF_CTRL1_BM_ERROR_IRQ_MASK, /*!< Bus master error interrupt. */ + kELCDIF_TxFifoOverflow = LCDIF_CTRL1_OVERFLOW_IRQ_MASK, /*!< TXFIFO overflow interrupt. */ + kELCDIF_TxFifoUnderflow = LCDIF_CTRL1_UNDERFLOW_IRQ_MASK, /*!< TXFIFO underflow interrupt. */ + kELCDIF_CurFrameDone = + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK, /*!< Interrupt when hardware enters vertical blanking state. */ + kELCDIF_VsyncEdge = LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */ + kELCDIF_SciSyncOn = LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */ +}; + +/*! + * @brief eLCDIF status flags + */ +enum _elcdif_status_flags +{ + kELCDIF_LFifoFull = LCDIF_STAT_LFIFO_FULL_MASK, /*!< LFIFO full. */ + kELCDIF_LFifoEmpty = LCDIF_STAT_LFIFO_EMPTY_MASK, /*!< LFIFO empty. */ + kELCDIF_TxFifoFull = LCDIF_STAT_TXFIFO_FULL_MASK, /*!< TXFIFO full. */ + kELCDIF_TxFifoEmpty = LCDIF_STAT_TXFIFO_EMPTY_MASK, /*!< TXFIFO empty. */ + kELCDIF_LcdControllerBusy = LCDIF_STAT_BUSY_MASK, /*!< The external LCD controller busy signal. */ + kELCDIF_CurDviField2 = LCDIF_STAT_DVI_CURRENT_FIELD_MASK, /*!< Current DVI filed, if set, then current filed is 2, + otherwise current filed is 1. */ +}; + +/*! + * @brief The pixel format. + * + * This enumerator should be defined together with the array s_pixelFormatReg. + * To support new pixel format, enhance this enumerator and s_pixelFormatReg. + */ +typedef enum _elcdif_pixel_format +{ + kELCDIF_PixelFormatRAW8 = 0, /*!< RAW 8 bit, four data use 32 bits. */ + kELCDIF_PixelFormatRGB565 = 1, /*!< RGB565, two pixel use 32 bits. */ + kELCDIF_PixelFormatRGB666 = 2, /*!< RGB666 unpacked, one pixel uses 32 bits, high byte unused, + upper 2 bits of other bytes unused. */ + kELCDIF_PixelFormatRGB888 = 3, /*!< RGB888 unpacked, one pixel uses 32 bits, high byte unused. */ +} elcdif_pixel_format_t; + +/*! @brief The LCD data bus type. */ +typedef enum _elcdif_lcd_data_bus +{ + kELCDIF_DataBus8Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */ + kELCDIF_DataBus16Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(0), /*!< 16-bit data bus, support RGB565. */ + kELCDIF_DataBus18Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(2), /*!< 18-bit data bus, support RGB666. */ + kELCDIF_DataBus24Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /*!< 24-bit data bus, support RGB888. */ +} elcdif_lcd_data_bus_t; + +/*! + * @brief The register value when using different pixel format. + * + * These register bits control the pixel format: + * - CTRL[DATA_FORMAT_24_BIT] + * - CTRL[DATA_FORMAT_18_BIT] + * - CTRL[DATA_FORMAT_16_BIT] + * - CTRL[WORD_LENGTH] + * - CTRL1[BYTE_PACKING_FORMAT] + */ +typedef struct _elcdif_pixel_format_reg +{ + uint32_t regCtrl; /*!< Value of register CTRL. */ + uint32_t regCtrl1; /*!< Value of register CTRL1. */ +} elcdif_pixel_format_reg_t; + +/*! + * @brief eLCDIF configure structure for RGB mode (DOTCLK mode). + */ +typedef struct _elcdif_rgb_mode_config +{ + uint16_t panelWidth; /*!< Display panel width, pixels per line. */ + uint16_t panelHeight; /*!< Display panel height, how many lines per panel. */ + uint8_t hsw; /*!< HSYNC pulse width. */ + uint8_t hfp; /*!< Horizontal front porch. */ + uint8_t hbp; /*!< Horizontal back porch. */ + uint8_t vsw; /*!< VSYNC pulse width. */ + uint8_t vfp; /*!< Vrtical front porch. */ + uint8_t vbp; /*!< Vertical back porch. */ + uint32_t polarityFlags; /*!< OR'ed value of @ref _elcdif_polarity_flags, used to contol the signal polarity. */ + uint32_t bufferAddr; /*!< Frame buffer address. */ + elcdif_pixel_format_t pixelFormat; /*!< Pixel format. */ + elcdif_lcd_data_bus_t dataBus; /*!< LCD data bus. */ +} elcdif_rgb_mode_config_t; + +/*! + * @brief eLCDIF alpha surface pixel format. + */ +typedef enum _elcdif_as_pixel_format +{ + kELCDIF_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ + kELCDIF_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ + kELCDIF_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ + kELCDIF_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ + kELCDIF_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ + kELCDIF_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ + kELCDIF_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ +} elcdif_as_pixel_format_t; + +/*! + * @brief eLCDIF alpha surface buffer configuration. + */ +typedef struct _elcdif_as_buffer_config +{ + uint32_t bufferAddr; /*!< Buffer address. */ + elcdif_as_pixel_format_t pixelFormat; /*!< Pixel format. */ +} elcdif_as_buffer_config_t; + +/*! + * @brief eLCDIF alpha mode during blending. + */ +typedef enum _elcdif_alpha_mode +{ + kELCDIF_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */ + kELCDIF_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */ + kELCDIF_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined + alpha value will be used for blend, for example, pixel alpha set + set to 200, user defined alpha set to 100, then the reault alpha + is 200 * 100 / 255. */ + kELCDIF_AlphaRop /*!< Raster operation. */ +} elcdif_alpha_mode_t; + +/*! + * @brief eLCDIF ROP mode during blending. + * + * Explanation: + * - AS: Alpha surface + * - PS: Process surface + * - nAS: Alpha surface NOT value + * - nPS: Process surface NOT value + */ +typedef enum _elcdif_rop_mode +{ + kELCDIF_RopMaskAs = 0x0, /*!< AS AND PS. */ + kELCDIF_RopMaskNotAs = 0x1, /*!< nAS AND PS. */ + kELCDIF_RopMaskAsNot = 0x2, /*!< AS AND nPS. */ + kELCDIF_RopMergeAs = 0x3, /*!< AS OR PS. */ + kELCDIF_RopMergeNotAs = 0x4, /*!< nAS OR PS. */ + kELCDIF_RopMergeAsNot = 0x5, /*!< AS OR nPS. */ + kELCDIF_RopNotCopyAs = 0x6, /*!< nAS. */ + kELCDIF_RopNot = 0x7, /*!< nPS. */ + kELCDIF_RopNotMaskAs = 0x8, /*!< AS NAND PS. */ + kELCDIF_RopNotMergeAs = 0x9, /*!< AS NOR PS. */ + kELCDIF_RopXorAs = 0xA, /*!< AS XOR PS. */ + kELCDIF_RopNotXorAs = 0xB /*!< AS XNOR PS. */ +} elcdif_rop_mode_t; + +/*! + * @brief eLCDIF alpha surface blending configuration. + */ +typedef struct _elcdif_as_blend_config +{ + uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kELCDIF_AlphaOverride or @ref + kELCDIF_AlphaRop. */ + bool invertAlpha; /*!< Set true to invert the alpha. */ + elcdif_alpha_mode_t alphaMode; /*!< Alpha mode. */ + elcdif_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kELCDIF_AlphaRop. */ +} elcdif_as_blend_config_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eLCDIF initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode). + * + * This function ungates the eLCDIF clock and configures the eLCDIF peripheral according + * to the configuration structure. + * + * @param base eLCDIF peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config); + +/*! + * @brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * @code + config->panelWidth = 480U; + config->panelHeight = 272U; + config->hsw = 41; + config->hfp = 4; + config->hbp = 8; + config->vsw = 10; + config->vfp = 4; + config->vbp = 2; + config->polarityFlags = kELCDIF_VsyncActiveLow | + kELCDIF_HsyncActiveLow | + kELCDIF_DataEnableActiveLow | + kELCDIF_DriveDataOnFallingClkEdge; + config->bufferAddr = 0U; + config->pixelFormat = kELCDIF_PixelFormatRGB888; + config->dataBus = kELCDIF_DataBus24Bit; + @code + * + * @param config Pointer to the eLCDIF configuration structure. + */ +void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config); + +/*! + * @brief Deinitializes the eLCDIF peripheral. + * + * @param base eLCDIF peripheral base address. + */ +void ELCDIF_Deinit(LCDIF_Type *base); + +/* @} */ + +/*! + * @name Module operation + * @{ + */ + +/*! + * @brief Start to display in RGB (DOTCLK) mode. + * + * @param base eLCDIF peripheral base address. + */ +static inline void ELCDIF_RgbModeStart(LCDIF_Type *base) +{ + base->CTRL_SET = LCDIF_CTRL_RUN_MASK | LCDIF_CTRL_DOTCLK_MODE_MASK; +} + +/*! + * @brief Stop display in RGB (DOTCLK) mode and wait until finished. + * + * @param base eLCDIF peripheral base address. + */ +void ELCDIF_RgbModeStop(LCDIF_Type *base); + +/*! + * @brief Set the next frame buffer address to display. + * + * @param base eLCDIF peripheral base address. + * @param bufferAddr The frame buffer address to set. + */ +static inline void ELCDIF_SetNextBufferAddr(LCDIF_Type *base, uint32_t bufferAddr) +{ + base->NEXT_BUF = bufferAddr; +} + +/*! + * @brief Reset the eLCDIF peripheral. + * + * @param base eLCDIF peripheral base address. + */ +void ELCDIF_Reset(LCDIF_Type *base); + +/*! + * @brief Pull up or down the reset pin for the externel LCD controller. + * + * @param base eLCDIF peripheral base address. + * @param pullUp True to pull up reset pin, false to pull down. + */ +static inline void ELCDIF_PullUpResetPin(LCDIF_Type *base, bool pullUp) +{ + if (pullUp) + { + base->CTRL1_SET = LCDIF_CTRL1_RESET_MASK; + } + else + { + base->CTRL1_CLR = LCDIF_CTRL1_RESET_MASK; + } +} + +/*! + * @brief Enable or disable the hand shake with PXP. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnablePxpHandShake(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_SET = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK; + } + else + { + base->CTRL_CLR = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get the CRC value of the frame sent out. + * + * When a frame is sent complete (the interrupt @ref kELCDIF_CurFrameDone assert), this function + * can be used to get the CRC value of the frame sent. + * + * @param base eLCDIF peripheral base address. + * @return The CRC value. + * + * @note The CRC value is dependent on the LCD_DATABUS_WIDTH. + */ +static inline uint32_t ELCDIF_GetCrcValue(LCDIF_Type *base) +{ + return base->CRC_STAT; +} + +/*! + * @brief Get the bus master error virtual address. + * + * When bus master error occurs (the interrupt kELCDIF_BusMasterError assert), this function + * can get the virtual address at which the AXI master received an error + * response from the slave. + * + * @param base eLCDIF peripheral base address. + * @return The error virtual address. + */ +static inline uint32_t ELCDIF_GetBusMasterErrorAddr(LCDIF_Type *base) +{ + return base->BM_ERROR_STAT; +} + +/*! + * @brief Get the eLCDIF status. + * + * The status flags are returned as a mask value, application could check the + * corresponding bit. Example: + * + * @code + uint32_t statusFlags; + statusFlags = ELCDIF_GetStatus(LCDIF); + + // If LFIFO is full. + if (kELCDIF_LFifoFull & statusFlags) + { + // ...; + } + // If TXFIFO is empty. + if (kELCDIF_TxFifoEmpty & statusFlags) + { + // ...; + } + @endcode + * + * @param base eLCDIF peripheral base address. + * @return The mask value of status flags, it is OR'ed value of @ref _elcdif_status_flags. + */ +static inline uint32_t ELCDIF_GetStatus(LCDIF_Type *base) +{ + return base->STAT & (LCDIF_STAT_LFIFO_FULL_MASK | LCDIF_STAT_LFIFO_EMPTY_MASK | LCDIF_STAT_TXFIFO_FULL_MASK | + LCDIF_STAT_TXFIFO_EMPTY_MASK | LCDIF_STAT_BUSY_MASK | LCDIF_STAT_DVI_CURRENT_FIELD_MASK); +} + +/*! + * @brief Get current count in Latency buffer (LFIFO). + * + * @param base eLCDIF peripheral base address. + * @return The LFIFO current count + */ +static inline uint32_t ELCDIF_GetLFifoCount(LCDIF_Type *base) +{ + return (base->STAT & LCDIF_STAT_LFIFO_COUNT_MASK) >> LCDIF_STAT_LFIFO_COUNT_SHIFT; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables eLCDIF interrupt requests. + * + * @param base eLCDIF peripheral base address. + * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable. + */ +static inline void ELCDIF_EnableInterrupts(LCDIF_Type *base, uint32_t mask) +{ + base->CTRL1_SET = (mask & ELCDIF_CTRL1_IRQ_EN_MASK); + base->AS_CTRL |= (mask & ELCDIF_AS_CTRL_IRQ_EN_MASK); +} + +/*! + * @brief Disables eLCDIF interrupt requests. + * + * @param base eLCDIF peripheral base address. + * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable. + */ +static inline void ELCDIF_DisableInterrupts(LCDIF_Type *base, uint32_t mask) +{ + base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_EN_MASK); + base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_EN_MASK); +} + +/*! + * @brief Get eLCDIF interrupt peding status. + * + * @param base eLCDIF peripheral base address. + * @return Interrupt pending status, OR'ed value of _elcdif_interrupt_flags. + */ +static inline uint32_t ELCDIF_GetInterruptStatus(LCDIF_Type *base) +{ + uint32_t flags; + + flags = (base->CTRL1 & ELCDIF_CTRL1_IRQ_MASK); + flags |= (base->AS_CTRL & ELCDIF_AS_CTRL_IRQ_MASK); + + return flags; +} + +/*! + * @brief Clear eLCDIF interrupt peding status. + * + * @param base eLCDIF peripheral base address. + * @param mask of the flags to clear, OR'ed value of _elcdif_interrupt_flags. + */ +static inline void ELCDIF_ClearInterruptStatus(LCDIF_Type *base, uint32_t mask) +{ + base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_MASK); + base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_MASK); +} + +/* @} */ + +/*! + * @name Alpha surface + * @{ + */ + +/*! + * @brief Set the configuration for alpha surface buffer. + * + * @param base eLCDIF peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config); + +/*! + * @brief Set the alpha surface blending configuration. + * + * @param base eLCDIF peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config); + +/*! + * @brief Set the next alpha surface buffer address. + * + * @param base eLCDIF peripheral base address. + * @param bufferAddr Alpha surface buffer address. + */ +static inline void ELCDIF_SetNextAlphaSurfaceBufferAddr(LCDIF_Type *base, uint32_t bufferAddr) +{ + base->AS_NEXT_BUF = bufferAddr; +} + +/*! + * @brief Set the overlay color key. + * + * If a pixel in the current overlay image with a color that falls in the range + * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface + * pixel value for that location. + * + * @param base eLCDIF peripheral base address. + * @param colorKeyLow Color key low range. + * @param colorKeyHigh Color key high range. + * + * @note Colorkey operations are higher priority than alpha or ROP operations + */ +static inline void ELCDIF_SetOverlayColorKey(LCDIF_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) +{ + base->AS_CLRKEYLOW = colorKeyLow; + base->AS_CLRKEYHIGH = colorKeyHigh; +} + +/*! + * @brief Enable or disable the color key. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableOverlayColorKey(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL |= LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK; + } + else + { + base->AS_CTRL &= ~LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK; + } +} + +/*! + * @brief Enable or disable the alpha surface. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableAlphaSurface(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL |= LCDIF_AS_CTRL_AS_ENABLE_MASK; + } + else + { + base->AS_CTRL &= ~LCDIF_AS_CTRL_AS_ENABLE_MASK; + } +} + +/*! + * @brief Enable or disable the process surface. + * + * Process surface is the normal frame buffer. The process surface content + * is controlled by @ref ELCDIF_SetNextBufferAddr. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableProcessSurface(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL &= ~LCDIF_AS_CTRL_PS_DISABLE_MASK; + } + else + { + base->AS_CTRL |= LCDIF_AS_CTRL_PS_DISABLE_MASK; + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_ELCDIF_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.c new file mode 100644 index 0000000000000000000000000000000000000000..bcfc1466797784ce19698295a841554534c92074 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.c @@ -0,0 +1,1032 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-16 songchao support emac driver + */ + +#include +#include "fsl_enet.h" +#include "fsl_iomuxc.h" +#include "ioremap.h" +#define DBG_TAG "drv.enet" +#define DBG_LVL DBG_LOG +#include +#include "drv_eth.h" + +#define ETH_ENABLE (1U) +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief IPv4 PTP message IP version offset. */ +#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU +/*! @brief IPv4 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U +/*! @brief IPv4 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U +/*! @brief IPv4 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU +/*! @brief IPv4 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU +/*! @brief IPv4 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU +/*! @brief IPv4 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U +/*! @brief IPv4 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU +/*! @brief IPv6 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U +/*! @brief IPv6 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U +/*! @brief IPv6 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU +/*! @brief IPv6 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU +/*! @brief IPv6 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U +/*! @brief IPv6 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU +/*! @brief IPv6 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU +/*! @brief PTPv2 message Ethernet packet type offset. */ +#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU +/*! @brief PTPv2 message Ethernet message type offset. */ +#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU +/*! @brief PTPv2 message Ethernet version type offset. */ +#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU +/*! @brief PTPv2 message Ethernet clock id offset. */ +#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 +/*! @brief PTPv2 message Ethernet sequence id offset. */ +#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c +/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ +#define ENET_ETHERNETL2 0x88F7U +/*! @brief Packet type IPv4. */ +#define ENET_IPV4 0x0800U +/*! @brief Packet type IPv6. */ +#define ENET_IPV6 0x86ddU +/*! @brief Packet type VLAN. */ +#define ENET_8021QVLAN 0x8100U +/*! @brief UDP protocol type. */ +#define ENET_UDPVERSION 0x0011U +/*! @brief Packet IP version IPv4. */ +#define ENET_IPV4VERSION 0x0004U +/*! @brief Packet IP version IPv6. */ +#define ENET_IPV6VERSION 0x0006U +/*! @brief Ethernet mac address length. */ +#define ENET_FRAME_MACLEN 6U +/*! @brief Ethernet VLAN header length. */ +#define ENET_FRAME_VLAN_TAGLEN 4U +/*! @brief MDC frequency. */ +#define ENET_MDC_FREQUENCY 2500000U +/*! @brief NanoSecond in one second. */ +#define ENET_NANOSECOND_ONE_SECOND 1000000000U +/*! @brief Define a common clock cycle delays used for time stamp capture. */ +#define ENET_1588TIME_DELAY_COUNT 10U +/*! @brief Defines the macro for converting constants from host byte order to network byte order. */ +#define ENET_HTONS(n) __REV16(n) +#define ENET_HTONL(n) __REV(n) +#define ENET_NTOHS(n) __REV16(n) +#define ENET_NTOHL(n) __REV(n) + +/* Typedef for interrupt handler. */ +typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +uint32_t ENET_GetInstance(ENET_Type *base); + +/*! + * @brief Set ENET MAC controller with the configuration. + * + * @param base ENET peripheral base address. + * @param config ENET Mac configuration. + * @param bufferConfig ENET buffer configuration. + * @param macAddr ENET six-byte mac address. + * @param srcClock_Hz ENET module clock source, normally it's system clock. + */ +static void ENET_SetMacController(ENET_Type *base, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Set ENET handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param config ENET configuration stucture pointer. + * @param bufferConfig ENET buffer configuration. + */ +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); +/*! + * @brief Set ENET MAC transmit buffer descriptors. + * + * @param txBdStartAlign The aligned start address of ENET transmit buffer descriptors. + * is recommended to evenly divisible by 16. + * @param txBuffStartAlign The aligned start address of ENET transmit buffers, must be evenly divisible by 16. + * @param txBuffSizeAlign The aligned ENET transmit buffer size, must be evenly divisible by 16. + * @param txBdNumber The number of ENET transmit buffers. + */ +static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartAlign, + uint8_t *txBuffStartAlign, + uint32_t txBuffSizeAlign, + uint32_t txBdNumber); + +/*! + * @brief Set ENET MAC receive buffer descriptors. + * + * @param rxBdStartAlign The aligned start address of ENET receive buffer descriptors. + * is recommended to evenly divisible by 16. + * @param rxBuffStartAlign The aligned start address of ENET receive buffers, must be evenly divisible by 16. + * @param rxBuffSizeAlign The aligned ENET receive buffer size, must be evenly divisible by 16. + * @param rxBdNumber The number of ENET receive buffers. + * @param enableInterrupt Enable/disables to generate the receive byte and frame interrupt. + * It's used for ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enabled case. + */ +static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign, + uint8_t *rxBuffStartAlign, + uint32_t rxBuffSizeAlign, + uint32_t rxBdNumber, + bool enableInterrupt); + +/*! + * @brief Updates the ENET read buffer descriptors. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + */ +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle); + +void rt_hw_cpu_dcache_clean(void *addr, int size); +void rt_hw_cpu_dcache_invalidate(void *addr, int size); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to enet handles for each instance. */ +static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL,NULL}; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +const clock_ip_name_t s_enetClock[] = ENET_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to enet bases for each instance. */ +static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; + +/* ENET ISR for transactional APIs. */ +static enet_isr_t s_enetTxIsr = NULL; +static enet_isr_t s_enetRxIsr = NULL; +static enet_isr_t s_enetErrIsr = NULL; +static enet_isr_t s_enetTsIsr = NULL; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t ENET_GetInstance(ENET_Type *base) +{ + uint32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_enetBases); instance++) + { + if (s_enetBases[instance] == base) + { + break; + } + } + RT_ASSERT(instance < ARRAY_SIZE(s_enetBases)); + + return instance; +} + +void ENET_GetDefaultConfig(enet_config_t *config) +{ + /* Checks input parameter. */ + RT_ASSERT(config); + + /* Initializes the MAC configure structure to zero. */ + memset(config, 0, sizeof(enet_config_t)); + + /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ + config->miiMode = kENET_RmiiMode; + config->miiSpeed = kENET_MiiSpeed100M; + config->miiDuplex = kENET_MiiFullDuplex; + + /* Sets the maximum receive frame length. */ + config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; +} + +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ + /* Checks input parameters. */ + RT_ASSERT(handle); + RT_ASSERT(config); + RT_ASSERT(bufferConfig); + RT_ASSERT(bufferConfig->rxBdStartAddrAlign); + RT_ASSERT(bufferConfig->txBdStartAddrAlign); + RT_ASSERT(bufferConfig->rxBufferAlign); + RT_ASSERT(bufferConfig->txBufferAlign); + RT_ASSERT(macAddr); + RT_ASSERT(bufferConfig->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); + /* Make sure the buffers should be have the capability of process at least one maximum frame. */ + if (config->macSpecialConfig & kENET_ControlVLANTagEnable) + { + RT_ASSERT(bufferConfig->txBuffSizeAlign * bufferConfig->txBdNumber > (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN)); + } + else + { + RT_ASSERT(bufferConfig->txBuffSizeAlign * bufferConfig->txBdNumber > ENET_FRAME_MAX_FRAMELEN); + RT_ASSERT(bufferConfig->rxBuffSizeAlign * bufferConfig->rxBdNumber > config->rxMaxFrameLen); + } + + /* Reset ENET module. */ + ENET_Reset(base); + /* Initializes the ENET transmit buffer descriptors. */ + ENET_SetTxBufferDescriptors(bufferConfig->txBdStartAddrAlign, bufferConfig->txPhyBufferAlign, + bufferConfig->txBuffSizeAlign, bufferConfig->txBdNumber); + /* Initializes the ENET receive buffer descriptors. */ + + + ENET_SetRxBufferDescriptors(bufferConfig->rxBdStartAddrAlign, bufferConfig->rxPhyBufferAlign, + bufferConfig->rxBuffSizeAlign, bufferConfig->rxBdNumber, + !!(config->interrupt & (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt))); + /* Initializes the ENET MAC controller. */ + ENET_SetMacController(base, config, bufferConfig, macAddr, srcClock_Hz); + /* Set all buffers or data in handler for data transmit/receive process. */ + ENET_SetHandler(base, handle, config, bufferConfig); +} + +void ENET_Deinit(ENET_Type *base) +{ + /* Disable interrupt. */ + base->EIMR = 0; + + /* Disable ENET. */ + base->ECR &= ~ENET_ECR_ETHEREN_MASK; + +} + +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData) +{ + RT_ASSERT(handle); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; +} + +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) +{ + struct rt_imx6ul_ethps *imx6ul_device = rt_container_of(config,struct rt_imx6ul_ethps,config); + uint32_t instance = get_instance_by_base(base); + memset(handle, 0, sizeof(enet_handle_t)); + handle->rxBdBase = bufferConfig->rxBdStartAddrAlign; + handle->rxBdCurrent = bufferConfig->rxBdStartAddrAlign; + handle->txBdBase = bufferConfig->txBdStartAddrAlign; + handle->txBdCurrent = bufferConfig->txBdStartAddrAlign; + handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign; + handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign; + + /* Save the handle pointer in the global variables. */ + s_ENETHandle[instance] = handle; + + /* Set the IRQ handler when the interrupt is enabled. */ + if (config->interrupt & ENET_TX_INTERRUPT) + { + s_enetTxIsr = ENET_TransmitIRQHandler; + EnableIRQ(imx6ul_device->irq_num); + } + if (config->interrupt & ENET_RX_INTERRUPT) + { + s_enetRxIsr = ENET_ReceiveIRQHandler; + EnableIRQ(imx6ul_device->irq_num); + } + if (config->interrupt & ENET_ERR_INTERRUPT) + { + s_enetErrIsr = ENET_ErrorIRQHandler; + EnableIRQ(imx6ul_device->irq_num); + } +} + +static void ENET_SetMacController(ENET_Type *base, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ + uint32_t rcr = 0; + uint32_t tcr = 0; + uint32_t ecr = 0; + uint32_t macSpecialConfig = config->macSpecialConfig; + uint32_t maxFrameLen = config->rxMaxFrameLen; + + /* Maximum frame length check. */ + if ((macSpecialConfig & kENET_ControlVLANTagEnable) && (maxFrameLen <= ENET_FRAME_MAX_FRAMELEN)) + { + maxFrameLen = (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN); + } + + /* Configures MAC receive controller with user configure structure. */ + rcr = ENET_RCR_NLC(!!(macSpecialConfig & kENET_ControlRxPayloadCheckEnable)) | + ENET_RCR_CFEN(!!(macSpecialConfig & kENET_ControlFlowControlEnable)) | + ENET_RCR_FCE(!!(macSpecialConfig & kENET_ControlFlowControlEnable)) | + ENET_RCR_PADEN(!!(macSpecialConfig & kENET_ControlRxPadRemoveEnable)) | + ENET_RCR_BC_REJ(!!(macSpecialConfig & kENET_ControlRxBroadCastRejectEnable)) | + ENET_RCR_PROM(!!(macSpecialConfig & kENET_ControlPromiscuousEnable)) | ENET_RCR_MII_MODE(1) | + ENET_RCR_RMII_MODE(config->miiMode) | ENET_RCR_RMII_10T(!config->miiSpeed) | + ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD(1); + /* Receive setting for half duplex. */ + if (config->miiDuplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + } + /* Sets internal loop only for MII mode. */ + if ((config->macSpecialConfig & kENET_ControlMIILoopEnable) && (config->miiMode == kENET_MiiMode)) + { + rcr |= ENET_RCR_LOOP_MASK; + rcr &= ~ENET_RCR_DRT_MASK; + } + base->RCR = rcr; + + /* Configures MAC transmit controller: duplex mode, mac address insertion. */ + tcr = base->TCR & ~(ENET_TCR_FDEN_MASK | ENET_TCR_ADDINS_MASK); + tcr |= ENET_TCR_FDEN(config->miiDuplex) | ENET_TCR_ADDINS(!!(macSpecialConfig & kENET_ControlMacAddrInsert)); + base->TCR = tcr; + + /* Configures receive and transmit accelerator. */ + base->TACC = config->txAccelerConfig; + base->RACC = config->rxAccelerConfig; + + /* Sets the pause duration and FIFO threshold for the flow control enabled case. */ + if (macSpecialConfig & kENET_ControlFlowControlEnable) + { + uint32_t reemReg; + base->OPD = config->pauseDuration; + reemReg = ENET_RSEM_RX_SECTION_EMPTY(config->rxFifoEmptyThreshold); +#if defined (FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + reemReg |= ENET_RSEM_STAT_SECTION_EMPTY(config->rxFifoStatEmptyThreshold); +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + base->RSEM = reemReg; + } + + /* FIFO threshold setting for store and forward enable/disable case. */ + if (macSpecialConfig & kENET_ControlStoreAndFwdDisable) + { + /* Transmit fifo watermark settings. */ + base->TFWR = config->txFifoWatermark & ENET_TFWR_TFWR_MASK; + /* Receive fifo full threshold settings. */ + base->RSFL = config->rxFifoFullThreshold & ENET_RSFL_RX_SECTION_FULL_MASK; + } + else + { + /* Transmit fifo watermark settings. */ + base->TFWR = ENET_TFWR_STRFWD_MASK; + base->RSFL = 0; + } + + /* Enable store and forward when accelerator is enabled */ + if (config->txAccelerConfig & (kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled)) + { + base->TFWR = ENET_TFWR_STRFWD_MASK; + } + if (config->rxAccelerConfig & (kENET_RxAccelIpCheckEnabled | kENET_RxAccelProtoCheckEnabled)) + { + base->RSFL = 0; + } + + /* Initializes transmit buffer descriptor rings start address, two start address should be aligned. */ + base->TDSR = (uint32_t)bufferConfig->txPhyBdStartAddrAlign; + base->RDSR = (uint32_t)bufferConfig->rxPhyBdStartAddrAlign; + + /* Initializes the maximum buffer size, the buffer size should be aligned. */ + + base->MRBR = ENET_MRBR_R_BUF_SIZE(bufferConfig->rxBuffSizeAlign); + + /* Configures the Mac address. */ + ENET_SetMacAddr(base, macAddr); + + /* Initialize the SMI if uninitialized. */ + if (!ENET_GetSMI(base)) + { + ENET_SetSMI(base, srcClock_Hz, !!(config->macSpecialConfig & kENET_ControlSMIPreambleDisable)); + } + +/* Enables Ethernet interrupt and NVIC. */ +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + if (config->intCoalesceCfg) + { + uint32_t intMask = (ENET_EIMR_TXB_MASK | ENET_EIMR_RXB_MASK); + + /* Clear all buffer interrupts. */ + base->EIMR &= ~intMask; + + /* Set the interrupt coalescence. */ + base->TXIC = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[0]) | + config->intCoalesceCfg->txCoalesceTimeCount[0] | ENET_TXIC_ICCS_MASK | ENET_TXIC_ICEN_MASK; + base->RXIC = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[0]) | + config->intCoalesceCfg->rxCoalesceTimeCount[0] | ENET_RXIC_ICCS_MASK | ENET_RXIC_ICEN_MASK; + } +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + ENET_EnableInterrupts(base, config->interrupt); + + /* ENET control register setting. */ + ecr = base->ECR; + + /* Enables Ethernet module after all configuration except the buffer descriptor active. */ + ecr |= ENET_ECR_ETHEREN_MASK | ENET_ECR_DBSWP_MASK; + base->ECR = ecr; +} + +static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartAlign, + uint8_t *txBuffStartAlign, + uint32_t txBuffSizeAlign, + uint32_t txBdNumber) +{ + RT_ASSERT(txBdStartAlign); + RT_ASSERT(txBuffStartAlign); + uint32_t count; + volatile enet_tx_bd_struct_t *curBuffDescrip = txBdStartAlign; + for (count = 0; count < txBdNumber; count++) + { + + /* Set data buffer address. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]); + /* Initializes data length. */ + curBuffDescrip->length = 0; + /* Sets the crc. */ + curBuffDescrip->control = (ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK); + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == txBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_WRAP_MASK; + } + + /* Add cache clean operation. */ + rt_hw_cpu_dcache_clean((void *)curBuffDescrip, sizeof(enet_tx_bd_struct_t)); + /* Increase the index. */ + curBuffDescrip++; + } +} + +static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign, + uint8_t *rxBuffStartAlign, + uint32_t rxBuffSizeAlign, + uint32_t rxBdNumber, + bool enableInterrupt) +{ + RT_ASSERT(rxBdStartAlign); + RT_ASSERT(rxBuffStartAlign); + + volatile enet_rx_bd_struct_t *curBuffDescrip = rxBdStartAlign; + uint32_t count = 0; + + /* Initializes receive buffer descriptors. */ + for (count = 0; count < rxBdNumber; count++) + { + /* Set data buffer and the length. */ + curBuffDescrip->buffer = (uint8_t *)((void *)&rxBuffStartAlign[count * rxBuffSizeAlign]); + curBuffDescrip->length = 0; + /* Initializes the buffer descriptors with empty bit. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == rxBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + } + /* Add cache clean operation. */ + rt_hw_cpu_dcache_clean((void *)curBuffDescrip, sizeof(enet_rx_bd_struct_t)); + /* Increase the index. */ + curBuffDescrip++; + } +} + +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) +{ + uint32_t rcr = base->RCR; + uint32_t tcr = base->TCR; + /* Sets speed mode. */ + if (kENET_MiiSpeed10M == speed) + { + rcr |= ENET_RCR_RMII_10T_MASK; + } + else + { + rcr &= ~ENET_RCR_RMII_10T_MASK; + } + /* Set duplex mode. */ + if (duplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + tcr &= ~ENET_TCR_FDEN_MASK; + } + else + { + rcr &= ~ENET_RCR_DRT_MASK; + tcr |= ENET_TCR_FDEN_MASK; + } + + base->RCR = rcr; + base->TCR = tcr; +} + +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + uint32_t address; + + /* Set physical address lower register. */ + address = (uint32_t)(((uint32_t)macAddr[0] << 24U) | ((uint32_t)macAddr[1] << 16U) | ((uint32_t)macAddr[2] << 8U) | + (uint32_t)macAddr[3]); + base->PALR = address; + /* Set physical address high register. */ + address = (uint32_t)(((uint32_t)macAddr[4] << 8U) | ((uint32_t)macAddr[5])); + base->PAUR = address << ENET_PAUR_PADDR2_SHIFT; +} + +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + RT_ASSERT(macAddr); + + uint32_t address; + + /* Get from physical address lower register. */ + address = base->PALR; + macAddr[0] = 0xFFU & (address >> 24U); + macAddr[1] = 0xFFU & (address >> 16U); + macAddr[2] = 0xFFU & (address >> 8U); + macAddr[3] = 0xFFU & address; + + /* Get from physical address high register. */ + address = (base->PAUR & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT; + macAddr[4] = 0xFFU & (address >> 8U); + macAddr[5] = 0xFFU & address; +} + +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) +{ + RT_ASSERT(srcClock_Hz); + + uint32_t clkCycle = 0; + uint32_t speed = 0; + uint32_t mscr = 0; + + /* Calculate the MII speed which controls the frequency of the MDC. */ + speed = srcClock_Hz / (2 * ENET_MDC_FREQUENCY); + /* Calculate the hold time on the MDIO output. */ + clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1; + /* Build the configuration for MDC/MDIO control. */ + mscr = ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_DIS_PRE(isPreambleDisabled) | ENET_MSCR_HOLDTIME(clkCycle); + base->MSCR = mscr; +} + +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2) | + (data & 0xFFFF); + base->MMFR = mmfr; +} + +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation) +{ + uint32_t mmfr = 0; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2); + base->MMFR = mmfr; +} + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(data); + base->MMFR = mmfr; +} + +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2); + base->MMFR = mmfr; +} +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + RT_ASSERT(handle); + RT_ASSERT(handle->rxBdCurrent); + RT_ASSERT(eErrorStatic); + + uint16_t control = 0; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent; + + do + { + /* Add the cache invalidate maintain. */ + rt_hw_cpu_dcache_invalidate((void *)curBuffDescrip, sizeof(enet_rx_bd_struct_t)); + + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + control = curBuffDescrip->control; + if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) + { + /* The receive truncate error. */ + eErrorStatic->statsRxTruncateErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) + { + /* The receive over run error. */ + eErrorStatic->statsRxOverRunErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) + { + /* The receive length violation error. */ + eErrorStatic->statsRxLenGreaterErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) + { + /* The receive alignment error. */ + eErrorStatic->statsRxAlignErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) + { + /* The receive CRC error. */ + eErrorStatic->statsRxFcsErr++; + } + break; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent); +} + +status_t ENET_ReadFrame(ENET_Type *base,enet_handle_t *handle,const enet_config_t *config,uint8_t *data,uint16_t *length) +{ + RT_ASSERT(handle); + RT_ASSERT(handle->rxBdCurrent); + RT_ASSERT(length); + + /* Reset the length to zero. */ + *length = 0; + + uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent; + rt_hw_cpu_dcache_invalidate((void *)physical_to_virtual(curBuffDescrip->buffer), handle->rxBuffSizeAlign); + + /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) + { + return kStatus_ENET_RxFrameEmpty; + } + else + { + if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + if(curBuffDescrip->length <= config->rxMaxFrameLen) + { + *length = curBuffDescrip->length; + + rt_memcpy(data, physical_to_virtual(curBuffDescrip->buffer),curBuffDescrip->length); + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle); + return kStatus_Success; + } + else + { + LOG_E("frame error0 curBuffDescrip->control 0x%04x length %d\n",curBuffDescrip->control,curBuffDescrip->length); + *length = curBuffDescrip->length; + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle); + return kStatus_ENET_RxFrameError; + } + } + else + { + LOG_E("frame error1 curBuffDescrip->control 0x%04x length %d\n",curBuffDescrip->control,curBuffDescrip->length); + *length = curBuffDescrip->length; + ENET_UpdateReadBuffers(base, handle); + return kStatus_ENET_RxFrameError; + } + } + /* The frame is on processing - set to empty status to make application to receive it next time. */ + return kStatus_ENET_RxFrameEmpty; +} + +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle) +{ + RT_ASSERT(handle); + + /* Clears status. */ + handle->rxBdCurrent->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + /* Sets the receive buffer descriptor with the empty flag. */ + handle->rxBdCurrent->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + /* Increase current buffer descriptor to the next one. */ + if (handle->rxBdCurrent->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + handle->rxBdCurrent = handle->rxBdBase; + } + else + { + handle->rxBdCurrent++; + } + /* Actives the receive buffer descriptor. */ + base->RDAR = ENET_RDAR_RDAR_MASK; +} + +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint16_t length,uint32_t last_flag) +{ + RT_ASSERT(handle); + RT_ASSERT(handle->txBdCurrent); + RT_ASSERT(data); + RT_ASSERT(length <= ENET_FRAME_MAX_FRAMELEN); + + volatile enet_tx_bd_struct_t *curBuffDescrip = handle->txBdCurrent; + /* Check if the transmit buffer is ready. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign >= length) + { + /* Copy data to the buffer for uDMA transfer. */ + rt_memcpy(physical_to_virtual(curBuffDescrip->buffer), data, length); + /* Set data length. */ + curBuffDescrip->length = length; + if(last_flag) + { + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + } + else + { + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + } + + rt_hw_cpu_dcache_clean((void *)physical_to_virtual(curBuffDescrip->buffer),length); + /* Active the transmit buffer descriptor. */ + + base->TDAR = ENET_TDAR_TDAR_MASK; + /* Increase the buffer descriptor address. */ + while((base->TDAR != 0)) + { + } + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent = handle->txBdBase; + } + else + { + handle->txBdCurrent++; + } + return kStatus_Success; + } + else + { + return kStatus_ENET_RxFrameError; + } +} + +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) +{ + RT_ASSERT(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Enable a multicast group address. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } + else + { + base->GAUR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } +} + +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) +{ + RT_ASSERT(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Set the hash table. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } + else + { + base->GAUR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } +} +void tx_enet_callback(void *base); +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + RT_ASSERT(handle); + /* Check if the transmit interrupt happen. */ + if((kENET_TxBufferInterrupt | kENET_TxFrameInterrupt) & base->EIR) + { + /* Clear the transmit interrupt event. */ + base->EIR = kENET_TxFrameInterrupt | kENET_TxBufferInterrupt; + } + tx_enet_callback((void *)base); +} +void rx_enet_callback(void *base); +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + RT_ASSERT(handle); + + /* Check if the receive interrupt happen. */ + if((kENET_RxBufferInterrupt | kENET_RxFrameInterrupt) & base->EIR) + { + /* Clear the transmit interrupt event. */ + base->EIR = kENET_RxFrameInterrupt | kENET_RxBufferInterrupt; + rx_enet_callback((void *)base); + } +} +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + RT_ASSERT(handle); + + uint32_t errMask = kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_PayloadRxInterrupt | + kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt; + /* Check if the error interrupt happen. */ + if (kENET_WakeupInterrupt & base->EIR) + { + /* Clear the wakeup interrupt. */ + base->EIR = kENET_WakeupInterrupt; + /* wake up and enter the normal mode. */ + ENET_EnableSleepMode(base, false); + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_WakeUpEvent, handle->userData); + } + } + else + { + /* Clear the error interrupt event status. */ + errMask &= base->EIR; + base->EIR = errMask; + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_ErrEvent, handle->userData); + } + } +} + +void ENET_CommonFrame0IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = get_instance_by_base(base); + + if(base->EIMR & ENET_TX_INTERRUPT) + { + if (event & ENET_TX_INTERRUPT) + { + if(s_enetTxIsr) + { + s_enetTxIsr(base, s_ENETHandle[instance]); + } + } + } + if (base->EIMR & ENET_RX_INTERRUPT) + { + if (event & ENET_RX_INTERRUPT) + { + if(s_enetRxIsr) + { + s_enetRxIsr(base, s_ENETHandle[instance]); + } + } + } + if(base->EIMR & ENET_TS_INTERRUPT) + { + if (event & ENET_TS_INTERRUPT) + { + if(s_enetTsIsr) + { + s_enetTsIsr(base, s_ENETHandle[instance]); + } + } + } + if(base->EIMR & ENET_ERR_INTERRUPT) + { + if (event & ENET_ERR_INTERRUPT) + { + if(s_enetErrIsr) + { + s_enetErrIsr(base, s_ENETHandle[instance]); + } + } + } +} +void ENET_DriverIRQHandler(int irq, void *base) +{ + ENET_CommonFrame0IRQHandler((ENET_Type *)base); +} \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.h new file mode 100644 index 0000000000000000000000000000000000000000..5a4f4e16d477614e2c1c666adb8b83fbcbd043ce --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.h @@ -0,0 +1,1337 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_ENET_H_ +#define _FSL_ENET_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup enet + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define ENET_PHY2 0x01U +#define ENET_PHY1 0x0U + +#define DETECT_DELAY_ONE_SECOND 1000 +#define ENET_RXBD_NUM (128) +#define ENET_TXBD_NUM (128) + +#define ENET_RXBUFF_ALIGN_SIZE (1536) +#define ENET_TXBUFF_ALIGN_SIZE (1536) + +#define ENET_RXBUFF_TOTAL_SIZE (ENET_RXBD_NUM*ENET_RXBUFF_ALIGN_SIZE) +#define ENET_TXBUFF_TOTAL_SIZE (ENET_TXBD_NUM*ENET_TXBUFF_ALIGN_SIZE) + +#define ENET_RX_MAX_BUFFER_SIZE (65536U) +#define SYS_PAGE_SIZE (4096U) + +#define TX_BUFFER_INDEX_NUM (6) +#define RX_BUFFER_INDEX_NUM (6) + +#define TX_BD_INDEX_NUM (0) +#define RX_BD_INDEX_NUM (0) + +#define SYS_CLOCK_HZ (66000000) + +#define virtual_to_physical(v) ((void *)((size_t)v + PV_OFFSET)) +#define physical_to_virtual(p) ((void *)((size_t)p - PV_OFFSET)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines the driver version. */ +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */ +/*@}*/ + +/*! @name Control and status region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ +#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ +#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ +#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ +/*@}*/ + +/*! @name Control and status bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ +/*@}*/ + +/* Extended control regions for enhanced buffer descriptors. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @name First extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ +/*@}*/ + +/*! @name First extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ +/*@}*/ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive error status flag mask. */ +#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ + ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) +#endif +#define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt) +#define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt) +#define ENET_TS_INTERRUPT (kENET_TsTimerInterrupt | kENET_TsAvailInterrupt) +#define ENET_ERR_INTERRUPT (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | \ + kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) + + +/*! @name Defines the maximum Ethernet frame size. */ +/*@{*/ +#define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Default maximum Ethernet frame size. */ +/*@}*/ + +#define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ +#define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ + +/*! @brief Defines the PHY address scope for the ENET. */ +#define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) + +/*! @brief Defines the status return codes for transaction. */ +enum _enet_status +{ + kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ + kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ + kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ + kStatus_ENET_TxFrameBusy = + MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Transmit buffer descriptors are under process. */ + kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 4U) /*!< Transmit frame fail. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + , + kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 5U), /*!< Timestamp ring full. */ + kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 6U) /*!< Timestamp ring empty. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY. */ +typedef enum _enet_mii_mode +{ + kENET_MiiMode = 0U, /*!< MII mode for data interface. */ + kENET_RmiiMode /*!< RMII mode for data interface. */ +} enet_mii_mode_t; + +/*! @brief Defines the 10 Mbps or 100 Mbps speed for the MII data interface. */ +typedef enum _enet_mii_speed +{ + kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ + kENET_MiiSpeed100M /*!< Speed 100 Mbps. */ +} enet_mii_speed_t; + +/*! @brief Defines the half or full duplex for the MII data interface. */ +typedef enum _enet_mii_duplex +{ + kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ + kENET_MiiFullDuplex /*!< Full duplex mode. */ +} enet_mii_duplex_t; + +/*! @brief Defines the write operation for the MII management frame. */ +typedef enum _enet_mii_write +{ + kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ + kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ +} enet_mii_write_t; + +/*! @brief Defines the read operation for the MII management frame. */ +typedef enum _enet_mii_read +{ + kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ + kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ +} enet_mii_read_t; + +#if defined (FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ +typedef enum _enet_mii_extend_opcode { + kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ + kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ + kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ +} enet_mii_extend_opcode; +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +/*! @brief Defines a special configuration for ENET MAC controller. + * + * These control flags are provided for special user requirements. + * Normally, these control flags are unused for ENET initialization. + * For special requirements, set the flags to + * macSpecialConfig in the enet_config_t. + * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store + * and forward. FIFO store and forward means that the FIFO read/send is started + * when a complete frame is stored in TX/RX FIFO. If this flag is set, + * configure rxFifoFullThreshold and txFifoWatermark + * in the enet_config_t. + */ +typedef enum _enet_special_control_flag +{ + kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ + kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ + kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ + kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ + kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ + kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ + kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ + kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ + kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ + kENET_ControlVLANTagEnable = 0x0200U /*!< Enable VLAN tag frame. */ +} enet_special_control_flag_t; + +/*! @brief List of interrupts supported by the peripheral. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. Members usually map to interrupt enable bits in one or more + * peripheral registers. + */ +typedef enum _enet_interrupt_enable +{ + kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ + kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ + kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ + kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ + kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */ + kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ + kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */ + kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ + kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ + kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ + kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ + kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ + kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive interrupt source */ + kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK, /*!< WAKEUP interrupt source */ + kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ + kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ +} enet_interrupt_enable_t; + +/*! @brief Defines the common interrupt event for callback use. */ +typedef enum _enet_event +{ + kENET_RxEvent, /*!< Receive event. */ + kENET_TxEvent, /*!< Transmit event. */ + kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ + kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ + kENET_TimeStampEvent, /*!< Time stamp event. */ + kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ +} enet_event_t; + +/*! @brief Defines the transmit accelerator configuration. */ +typedef enum _enet_tx_accelerator +{ + kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ + kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ + kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ +} enet_tx_accelerator_t; + +/*! @brief Defines the receive accelerator configuration. */ +typedef enum _enet_rx_accelerator +{ + kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ + kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ + kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ + kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ + kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ +} enet_rx_accelerator_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP message related constant. */ +typedef enum _enet_ptp_event_type +{ + kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ + kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ + kENET_PtpEventPort = 319U, /*!< PTP event port number. */ + kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ +} enet_ptp_event_type_t; + +/*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ +typedef enum _enet_ptp_timer_channel +{ + kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ + kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ + kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ + kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ +} enet_ptp_timer_channel_t; + +/*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ +typedef enum _enet_ptp_timer_channel_mode +{ + kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ + kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ + kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ + kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ + kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ + kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ + kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ + kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ + kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ + kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ + kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ + kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ +} enet_ptp_timer_channel_mode_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ +typedef struct _enet_rx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ + uint16_t payloadCheckSum; /*!< Internal payload checksum. */ + uint8_t headerLength; /*!< Header length. */ + uint8_t protocolTyte; /*!< Protocol type. */ + uint16_t reserved0; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved1; + uint16_t reserved2; + uint16_t reserved3; + uint16_t reserved4; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_rx_bd_struct_t; + +/*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ +typedef struct _enet_tx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ + uint16_t reserved0; + uint16_t reserved1; + uint16_t reserved2; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved3; + uint16_t reserved4; + uint16_t reserved5; + uint16_t reserved6; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_tx_bd_struct_t; + +/*! @brief Defines the ENET data error statistic structure. */ +typedef struct _enet_data_error_stats +{ + uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ + uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ + uint32_t statsRxFcsErr; /*!< Receive CRC error. */ + uint32_t statsRxOverRunErr; /*!< Receive over run. */ + uint32_t statsRxTruncateErr; /*!< Receive truncate. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ + uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ + uint32_t statsRxMacErr; /*!< Receive Mac error. */ + uint32_t statsRxPhyErr; /*!< Receive PHY error. */ + uint32_t statsRxCollisionErr; /*!< Receive collision. */ + uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ + uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ + uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ + uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ + uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ + uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ + uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_data_error_stats_t; + +/*! @brief Defines the receive buffer descriptor configuration structure. + * + * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements. + * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + * 2. The aligned transmit and receive buffer descriptor start address must be at + * least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. + * buffer descriptors should be put in non-cacheable region when cache is enabled. + * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. + * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". + * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + */ +typedef struct _enet_buffer_config +{ + uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ + uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ + uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ + uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ + volatile enet_rx_bd_struct_t *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address. */ + volatile enet_tx_bd_struct_t *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address. */ + uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ + uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ + void *rxPhyBdStartAddrAlign; /*!< Aligned receive buffer descriptor physical start address. */ + void *txPhyBdStartAddrAlign; /*!< Aligned transmit buffer descriptor physical start address. */ + uint8_t *rxPhyBufferAlign; /*!< Receive data buffer physical start address. */ + uint8_t *txPhyBufferAlign; /*!< Transmit data buffer physical start address. */ + uint32_t rxBufferTotalSize; /*!< Receive data buffer max size. */ + uint32_t txBufferTotalSize; /*!< Transmit data buffer max size. */ +} enet_buffer_config_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP time stamp structure. */ +typedef struct _enet_ptp_time +{ + uint64_t second; /*!< Second. */ + uint32_t nanosecond; /*!< Nanosecond. */ +} enet_ptp_time_t; + +/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ +typedef struct _enet_ptp_time_data +{ + uint8_t version; /*!< PTP version. */ + uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ + uint16_t sequenceId; /*!< PTP sequence ID. */ + uint8_t messageType; /*!< PTP message type. */ + enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ +} enet_ptp_time_data_t; + +/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ +typedef struct _enet_ptp_time_data_ring +{ + uint32_t front; /*!< The first index of the ring. */ + uint32_t end; /*!< The end index of the ring. */ + uint32_t size; /*!< The size of the ring. */ + enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ +} enet_ptp_time_data_ring_t; + +/*! @brief Defines the ENET PTP configuration structure. */ +typedef struct _enet_ptp_config +{ + uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ + uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ + enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ + enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ + enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ + uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ +} enet_ptp_config_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +#if defined (FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE +/*! @brief Defines the interrupt coalescing configure structure. */ +typedef struct _enet_intcoalesce_config +{ + uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */ + uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */ + uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */ + uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */ +} enet_intcoalesce_config_t; +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + +/*! @brief Defines the basic configuration structure for the ENET device. + * + * Note: + * 1. macSpecialConfig is used for a special control configuration, a logical OR of + * "enet_special_control_flag_t". For a special configuration for MAC, + * set this parameter to 0. + * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes. + * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. + * 2 - 128 bytes written to TX FIFO .... + * 3 - 192 bytes written to TX FIFO .... + * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO. + * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 + * or for larger bus access latency 3 or larger due to contention for the system bus. + * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. + * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. + * If the end of the frame is stored in FIFO and the frame size if smaller than the + * txWatermark, the frame is still transmitted. The rule is the + * same for rxFifoFullThreshold in the receive direction. + * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure + * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold + * are set for flow control enabled case. + * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure + * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. + * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator + * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are + * recommended to be used to enable the transmit and receive accelerator. + * After the accelerators are enabled, the store and forward feature should be enabled. + * As a result, kENET_ControlStoreAndFwdDisabled should not be set. + */ +typedef struct _enet_config +{ + uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ + uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ + uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ + enet_mii_mode_t miiMode; /*!< MII mode. */ + enet_mii_speed_t miiSpeed; /*!< MII Speed. */ + enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ + uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ + uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, + it makes MAC generate XOFF pause frame. */ +#if defined (FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, + independent of size, that can be accept. If the limit is reached, reception + continues and a pause frame is triggered. */ +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify + the MAC receive ready status. */ + uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO + before a frame transmit start. */ +#if defined (FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + enet_intcoalesce_config_t *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), please set + to NULL. */ +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ +} enet_config_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _enet_handle enet_handle_t; + +/*! @brief ENET callback function. */ +typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData); + +/*! @brief Defines the ENET handler structure. */ +struct _enet_handle +{ + volatile enet_rx_bd_struct_t *rxBdBase; /*!< Receive buffer descriptor base address pointer. */ + volatile enet_rx_bd_struct_t *rxBdCurrent; /*!< The current available receive buffer descriptor pointer. */ + volatile enet_tx_bd_struct_t *txBdBase; /*!< Transmit buffer descriptor base address pointer. */ + volatile enet_tx_bd_struct_t *txBdCurrent; /*!< The current available transmit buffer descriptor pointer. */ + uint32_t rxBuffSizeAlign; /*!< Receive buffer size alignment. */ + uint32_t txBuffSizeAlign; /*!< Transmit buffer size alignment. */ + enet_callback_t callback; /*!< Callback function. */ + void *userData; /*!< Callback function parameter.*/ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + volatile enet_tx_bd_struct_t *txBdDirtyStatic; /*!< The dirty transmit buffer descriptor for error static update. */ + volatile enet_tx_bd_struct_t *txBdDirtyTime; /*!< The dirty transmit buffer descriptor for time stamp update. */ + uint64_t msTimerSecond; /*!< The second for Master PTP timer .*/ + enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ + enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and de-initialization + * @{ + */ + +/*! + * @brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configuration structure for ENET_Init(). Users may use the initialized + * structure unchanged in ENET_Init() or modify fields of the + * structure before calling ENET_Init(). + * This is an example. + @code + enet_config_t config; + ENET_GetDefaultConfig(&config); + @endcode + * @param config The ENET mac controller configuration structure pointer. + */ +void ENET_GetDefaultConfig(enet_config_t *config); + +/*! + * @brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param config ENET Mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * @param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * @param macAddr ENET mac address of the Ethernet device. This Mac address should be + * provided. + * @param srcClock_Hz The internal module clock source for MII clock. + * + * @note ENET has two buffer descriptors legacy buffer descriptors and + * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To + * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * @param base ENET peripheral base address. + */ +void ENET_Deinit(ENET_Type *base); + +/*! + * @brief Resets the ENET module. + * + * This function restores the ENET module to the reset state. + * Note that this function sets all registers to the + * reset state. As a result, the ENET module can't work after calling this function. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Reset(ENET_Type *base) +{ + base->ECR |= ENET_ECR_RESET_MASK; +} + +/* @} */ + +/*! + * @name MII interface operation + * @{ + */ + +/*! + * @brief Sets the ENET MII speed and duplex. + * + * @param base ENET peripheral base address. + * @param speed The speed of the RMII mode. + * @param duplex The duplex of the RMII mode. + */ +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); + +/*! + * @brief Sets the ENET SMI (serial management interface) - MII management interface. + * + * @param base ENET peripheral base address. + * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * @param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); + +/*! + * @brief Gets the ENET SMI- MII management interface configuration. + * + * This API is used to get the SMI configuration to check whether the MII management + * interface has been set. + * + * @param base ENET peripheral base address. + * @return The SMI setup status true or false. + */ +static inline bool ENET_GetSMI(ENET_Type *base) +{ + return (0 != (base->MSCR & 0x7E)); +} + +/*! + * @brief Reads data from the PHY register through an SMI interface. + * + * @param base ENET peripheral base address. + * @return The data read from PHY + */ +static inline uint32_t ENET_ReadSMIData(ENET_Type *base) +{ + return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); +} + +/*! + * @brief Starts an SMI (Serial Management Interface) read command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param operation The read operation. + */ +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation); + +/*! + * @brief Starts an SMI write command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param operation The write operation. + * @param data The data written to PHY. + */ +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data); + +#if defined (FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + */ +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg); + +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + * @param data The data written to PHY. + */ +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +/* @} */ + +/*! + * @name MAC Address Filter + * @{ + */ + +/*! + * @brief Sets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Gets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Adds the ENET device to a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); + +/*! + * @brief Moves the ENET device from a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); + +/* @} */ + +/*! + * @name Other basic operations + * @{ + */ + +/*! + * @brief Activates ENET read or receive. + * + * @param base ENET peripheral base address. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * ENET_Ptp1588Configure(). This should be called when the ENET receive required. + */ +static inline void ENET_ActiveRead(ENET_Type *base) +{ + base->RDAR = ENET_RDAR_RDAR_MASK; +} + +/*! + * @brief Enables/disables the MAC to enter sleep mode. + * This function is used to set the MAC enter sleep mode. + * When entering sleep mode, the magic frame wakeup interrupt should be enabled + * to wake up MAC from the sleep mode and reset it to normal mode. + * + * @param base ENET peripheral base address. + * @param enable True enable sleep mode, false disable sleep mode. + */ +static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) +{ + if (enable) + { + /* When this field is set, MAC enters sleep mode. */ + base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; + } + else + { /* MAC exits sleep mode. */ + base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); + } +} + +/*! + * @brief Gets ENET transmit and receive accelerator functions from the MAC controller. + * + * @param base ENET peripheral base address. + * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is + * recommended as the mask to get the exact the accelerator option. + * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is + * recommended as the mask to get the exact the accelerator option. + */ +static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) +{ + assert(txAccelOption); + assert(txAccelOption); + + *txAccelOption = base->TACC; + *rxAccelOption = base->RACC; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the ENET interrupt. + * + * This function enables the ENET interrupt according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to enable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to enable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR |= mask; +} + +/*! + * @brief Disables the ENET interrupt. + * + * This function disables the ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to disable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to disable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR &= ~mask; +} + +/*! + * @brief Gets the ENET interrupt status flag. + * + * @param base ENET peripheral base address. + * @return The event status of the interrupt source. This is the logical OR of members + * of the enumeration :: enet_interrupt_enable_t. + */ +static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) +{ + return base->EIR; +} + +/*! + * @brief Clears the ENET interrupt events status flag. + * + * This function clears enabled ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t. + * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupt source to be cleared. + * This is the logical OR of members of the enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) +{ + base->EIR = mask; +} + +/* @} */ + +/*! + * @name Transactional operation + * @{ + */ + +/*! + * @brief Sets the callback function. + * This API is provided for the application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * @param handle ENET handler pointer. Should be provided by application. + * @param callback The ENET callback function. + * @param userData The callback function parameter. + */ +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData); + +/*! + * @brief Gets the ENET the error statistics of a received frame. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * This is an example. + * @code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + */ +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Gets the ENET transmit frame statistics after the data send. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/*! +* @brief Gets the size of the read frame. +* This function gets a received frame size from the ENET buffer descriptors. +* @note The FCS of the frame is automatically removed by Mac and the size is the length without the FCS. +* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the +* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". +* +* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. +* @param length The length of the valid frame received. +* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. +* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data +* and NULL length to update the receive buffers. +* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame +* should be called with the right data buffer and the captured data length input. +*/ +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length); + +/*! + * @brief Reads a frame from the ENET device. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * This is an example. + * @code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrame(ENET_Type *base,enet_handle_t *handle,const enet_config_t *config, uint8_t *data,uint16_t *length); + +/*! + * @brief Transmits an ENET frame. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint16_t length,uint32_t last_flag); + +/*! + * @brief The transmit IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The receive IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The error IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single ring (ring 0). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame0IRQHandler(ENET_Type *base); +/* @} */ + +/*! + * @brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single ring (ring 0). + * @param irq gic interrupt number. + * @param base ENET peripheral base address. + */ +void ENET_DriverIRQHandler(int irq, void *base); + +/*! + * config pin for enet function + */ +void ENET_InitPins(void); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @name ENET PTP 1588 function operation + * @{ + */ + +/*! + * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param ptpConfig The ENET PTP1588 configuration. + */ +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); + +/*! + * @brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * @param base ENET peripheral base address. + * @param ptpClkSrc The clock source of the PTP timer. + */ +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); + +/*! + * @brief Stops the ENET PTP 1588 Timer. + * This function is used to stops the ENET PTP timer. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Ptp1588StopTimer(ENET_Type *base) +{ + /* Disable PTP timer and reset the timer. */ + base->ATCR &= ~ENET_ATCR_EN_MASK; + base->ATCR |= ENET_ATCR_RESTART_MASK; +} + +/*! + * @brief Adjusts the ENET PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); + +/*! + * @brief Sets the ENET PTP 1588 timer channel mode. + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, + enet_ptp_timer_channel_t channel, + enet_ptp_timer_channel_mode_t mode, + bool intEnable) +{ + uint32_t tcrReg = 0; + + tcrReg = ENET_TCSR_TMODE(mode) | ENET_TCSR_TIE(intEnable); + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} + +#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL +/*! + * @brief Sets ENET PTP 1588 timer channel mode pulse width. + * + * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare + * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock. + * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. + * so call this function if you need to set the timer channel mode for + * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare + * with pulse width more than one 1588 clock, + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param isOutputLow True --- timer channel is configured for output compare + * pulse output low. + * false --- timer channel is configured for output compare + * pulse output high. + * @param pulseWidth The pulse width control value, range from 0 ~ 31. + * 0 --- pulse width is one 1588 clock cycle. + * 31 --- pulse width is thirty two 1588 clock cycles. + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelOutputPulseWidth(ENET_Type *base, + enet_ptp_timer_channel_t channel, + bool isOutputLow, + uint8_t pulseWidth, + bool intEnable) +{ + uint32_t tcrReg; + + tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth); + + if (isOutputLow) + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare); + } + else + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare); + } + + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} +#endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */ + +/*! + * @brief Sets the ENET PTP 1588 timer channel comparison value. + * + * @param base ENET peripheral base address. + * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". + * @param cmpValue The compare value for the compare setting. + */ +static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) +{ + base->CHANNEL[channel].TCCR = cmpValue; +} + +/*! + * @brief Gets the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + * @return True or false, Compare or capture operation status + */ +static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + return (0 != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); +} + +/*! + * @brief Clears the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + */ +static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; + base->TGSR = (1U << channel); +} + +/*! + * @brief Gets the current ENET time from the PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The PTP timer structure. + */ +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief Sets the ENET PTP 1588 timer to the assigned time. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The timer to be set to the PTP timer. + */ +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief The IEEE 1588 PTP time stamp interrupt handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_ENET_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.c new file mode 100644 index 0000000000000000000000000000000000000000..2213758248e37aac83ea96c69a2a3a073ed4b169 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_epit.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base EPIT peripheral base address + * + * @return The EPIT instance + */ +static uint32_t EPIT_GetInstance(EPIT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to EPIT bases for each instance. */ +static EPIT_Type *const s_epitBases[] = EPIT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to EPIT clocks for each instance. */ +static const clock_ip_name_t s_epitClocks[] = EPIT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t EPIT_GetInstance(EPIT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_epitBases); instance++) + { + if (s_epitBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_epitBases)); + + return instance; +} + +void EPIT_Init(EPIT_Type *base, const epit_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the EPIT clock*/ + CLOCK_EnableClock(s_epitClocks[EPIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->CR = 0U; + + EPIT_SoftwareReset(base); + + base->CR = + (config->enableRunInStop ? EPIT_CR_STOPEN_MASK : 0U) | (config->enableRunInWait ? EPIT_CR_WAITEN_MASK : 0U) | + (config->enableRunInDbg ? EPIT_CR_DBGEN_MASK : 0U) | (config->enableCounterOverwrite ? EPIT_CR_IOVW_MASK : 0U) | + (config->enableFreeRun ? 0U : EPIT_CR_RLD_MASK) | (config->enableResetMode ? EPIT_CR_ENMOD_MASK : 0U); + + EPIT_SetClockSource(base, config->clockSource); + EPIT_SetClockDivider(base, config->divider); +} + +void EPIT_Deinit(EPIT_Type *base) +{ + /* Disable EPIT timers */ + base->CR = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the EPIT clock*/ + CLOCK_DisableClock(s_epitClocks[EPIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void EPIT_GetDefaultConfig(epit_config_t *config) +{ + assert(config); + + config->clockSource = kEPIT_ClockSource_Periph; + config->divider = 1U; + config->enableRunInStop = true; + config->enableRunInWait = true; + config->enableRunInDbg = false; + config->enableCounterOverwrite = false; + config->enableFreeRun = false; + config->enableResetMode = true; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.h new file mode 100644 index 0000000000000000000000000000000000000000..14dd31240b740d6356cc27aeb2d7172f5af91588 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.h @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_EPIT_H_ +#define _FSL_EPIT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup epit + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_EPIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ + /*@}*/ + +/*! + * @brief List of clock sources + * @note Actual number of clock sources is SoC dependent + */ +typedef enum _epit_clock_source +{ + kEPIT_ClockSource_Off = 0U, /*!< EPIT Clock Source Off.*/ + kEPIT_ClockSource_Periph = 1U, /*!< EPIT Clock Source from Peripheral Clock.*/ + kEPIT_ClockSource_HighFreq = 2U, /*!< EPIT Clock Source from High Frequency Reference Clock.*/ + kEPIT_ClockSource_LowFreq = 3U, /*!< EPIT Clock Source from Low Frequency Reference Clock.*/ +} epit_clock_source_t; + +/*! + * @brief List of output compare operation mode + */ +typedef enum _epit_output_operation_mode +{ + kEPIT_OutputOperation_Disconnected = 0U, /*!< EPIT Output Operation: Disconnected from pad.*/ + kEPIT_OutputOperation_Toggle = 1U, /*!< EPIT Output Operation: Toggle output pin.*/ + kEPIT_OutputOperation_Clear = 2U, /*!< EPIT Output Operation: Clear output pin.*/ + kEPIT_OutputOperation_Set = 3U, /*!< EPIT Output Operation: Set putput pin.*/ +} epit_output_operation_mode_t; + +/*! @brief List of EPIT interrupts */ +typedef enum _epit_interrupt_enable +{ + kEPIT_OutputCompareInterruptEnable = EPIT_CR_OCIEN_MASK, /*!< Output Compare interrupt enable*/ +} epit_interrupt_enable_t; + +/*! @brief List of EPIT status flags */ +typedef enum _epit_status_flags +{ + kEPIT_OutputCompareFlag = EPIT_SR_OCIF_MASK, /*!< Output Compare flag */ +} epit_status_flags_t; + +/*! @brief Structure to configure the running mode. */ +typedef struct _epit_config +{ + epit_clock_source_t clockSource; /*!< clock source for EPIT module. */ + uint32_t divider; /*!< clock divider (prescaler+1) from clock source to counter. */ + bool enableRunInStop; /*!< EPIT enabled in stop mode. */ + bool enableRunInWait; /*!< EPIT enabled in wait mode. */ + bool enableRunInDbg; /*!< EPIT enabled in debug mode. */ + bool enableCounterOverwrite; /*!< set timer period results in counter value being overwritten. */ + bool enableFreeRun; /*!< true: free-running mode, counter will be reset to 0xFFFFFFFF when timer expires; + false: set-and-forget mode, counter will be reloaded from set timer periods. */ + bool enableResetMode; /*!< true: counter is reset to timer periods in set-and-forget mode or 0xFFFFFFFF in + free-running mode when enabled; + false: counter restores the value that it was disabled when enabled. */ +} epit_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Software reset of EPIT module. + * + * @param base EPIT peripheral base address. + */ +static inline void EPIT_SoftwareReset(EPIT_Type *base) +{ + base->CR |= EPIT_CR_SWR_MASK; + /* Wait reset finished. */ + while ((base->CR & EPIT_CR_SWR_MASK) == EPIT_CR_SWR_MASK) + { + } +} + +/* @} */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the EPIT clock and configures the peripheral for a basic operation. + * + * This function issues a software reset to reset all the registers to their reset values, + * except for the EN, ENMOD, STOPEN, WAITEN and DBGEN bits in Control register. + * + * @note This API should be called at the beginning of the application using the EPIT driver. + * + * @param base EPIT peripheral base address. + * @param config Pointer to the user configuration structure. + */ +void EPIT_Init(EPIT_Type *base, const epit_config_t *config); + +/*! + * @brief Disables the module and gates the EPIT clock. + * + * @param base EPIT peripheral base address. + */ +void EPIT_Deinit(EPIT_Type *base); + +/*! + * @brief Fills in the EPIT configuration structure with default settings. + * + * The default values are: + * @code + * config->clockSource = kEPIT_ClockSource_Periph; + * config->divider = 1U; + * config->enableRunInStop = true; + * config->enableRunInWait = true; + * config->enableRunInDbg = false; + * config->enableCounterOverwrite = false; + * config->enableFreeRun = false; + * config->enableResetMode = true; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void EPIT_GetDefaultConfig(epit_config_t *config); + +/*! @}*/ + +/*! + * @name Clock source and frequency control + * @{ + */ + +/*! + * @brief Set clock source of EPIT. + * + * @param base EPIT peripheral base address. + * @param source clock source to switch to. + */ +static inline void EPIT_SetClockSource(EPIT_Type *base, epit_clock_source_t source) +{ + base->CR = (base->CR & ~EPIT_CR_CLKSRC_MASK) | EPIT_CR_CLKSRC(source); +} + +/*! + * @brief Set clock divider inside EPIT module. + * + * @param base EPIT peripheral base address. + * @param divider Clock divider in EPIT module (1-4096, divider = prescaler + 1). + */ +static inline void EPIT_SetClockDivider(EPIT_Type *base, uint32_t divider) +{ + assert((divider > 0) && (divider <= (EPIT_CR_PRESCALAR_MASK >> EPIT_CR_PRESCALAR_SHIFT) + 1)); + base->CR = (base->CR & ~EPIT_CR_PRESCALAR_MASK) | EPIT_CR_PRESCALAR(divider - 1); +} + +/*! + * @brief Get clock divider inside EPIT module. + * + * @param base EPIT base pointer. + * @return clock divider in EPIT module (1-4096). + */ +static inline uint32_t EPIT_GetClockDivider(EPIT_Type *base) +{ + return ((base->CR & EPIT_CR_PRESCALAR_MASK) >> EPIT_CR_PRESCALAR_SHIFT) + 1; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Start EPIT timer. + * + * @param base EPIT peripheral base address. + */ +static inline void EPIT_StartTimer(EPIT_Type *base) +{ + base->CR |= EPIT_CR_EN_MASK; +} + +/*! + * @brief Stop EPIT timer. + * + * @param base EPIT peripheral base address. + */ +static inline void EPIT_StopTimer(EPIT_Type *base) +{ + base->CR &= ~EPIT_CR_EN_MASK; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting down from the value set by this function until it reaches 0, at which point + * it generates an interrupt and loads this register value again. + * When enableCounterOverwrite is false, writing a new value to this register does not restart the timer, + * and the value is loaded after the timer expires. When enableCounterOverwrite is true, the counter + * will be set immediately and starting counting down from that value. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks. + * + * @param base EPIT peripheral base address. + * @param ticks Timer period in units of ticks. + */ +static inline void EPIT_SetTimerPeriod(EPIT_Type *base, uint32_t ticks) +{ + base->LR = ticks; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to microseconds or milliseconds. + * + * @param base EPIT peripheral base address. + * + * @return Current timer counting value in ticks. + */ +static inline uint32_t EPIT_GetCurrentTimerCount(EPIT_Type *base) +{ + return base->CNR; +} + +/*@}*/ + +/*! + * @name Output Signal Control + * @{ + */ + +/*! + * @brief Set EPIT output compare operation mode. + * + * @param base EPIT peripheral base address. + * @param mode EPIT output compare operation mode. + */ +static inline void EPIT_SetOutputOperationMode(EPIT_Type *base, epit_output_operation_mode_t mode) +{ + base->CR = (base->CR & ~EPIT_CR_OM_MASK) | EPIT_CR_OM(mode); +} + +/*! + * @brief Set EPIT output compare value. + * + * @param base EPIT peripheral base address. + * @param value EPIT output compare value. + */ +static inline void EPIT_SetOutputCompareValue(EPIT_Type *base, uint32_t value) +{ + base->CMPR = value; +} + +/*@}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected EPIT interrupts. + * + * @param base EPIT peripheral base address. + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::epit_interrupt_enable_t + */ +static inline void EPIT_EnableInterrupts(EPIT_Type *base, uint32_t mask) +{ + base->CR |= mask; +} + +/*! + * @brief Disables the selected EPIT interrupts. + * + * @param base EPIT peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::epit_interrupt_enable_t + */ +static inline void EPIT_DisableInterrupts(EPIT_Type *base, uint32_t mask) +{ + base->CR &= ~mask; +} + +/*! + * @brief Gets the enabled EPIT interrupts. + * + * @param base EPIT peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::epit_interrupt_enable_t + */ +static inline uint32_t EPIT_GetEnabledInterrupts(EPIT_Type *base) +{ + return (base->CR & EPIT_CR_OCIEN_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the EPIT status flags. + * + * @param base EPIT peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::epit_status_flags_t + */ +static inline uint32_t EPIT_GetStatusFlags(EPIT_Type *base) +{ + return (base->SR & EPIT_SR_OCIF_MASK); +} + +/*! + * @brief Clears the EPIT status flags. + * + * @param base EPIT peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::epit_status_flags_t + */ +static inline void EPIT_ClearStatusFlags(EPIT_Type *base, uint32_t mask) +{ + base->SR = mask; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /*_FSL_EPIT_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..be1665ffddf432be31d858aeb56e38e553f407d4 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of GPIO peripheral base address. */ +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of GPIO clock name. */ +static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/*! +* @brief Gets the GPIO instance according to the GPIO base +* +* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval GPIO instance +*/ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} + +void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable GPIO clock. */ + CLOCK_EnableClock(s_gpioClock[GPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Register reset to default value */ + base->IMR &= ~(1U << pin); + + /* Configure GPIO pin direction */ + if (Config->direction == kGPIO_DigitalInput) + { + base->GDIR &= ~(1U << pin); + } + else + { + GPIO_WritePinOutput(base, pin, Config->outputLogic); + base->GDIR |= (1U << pin); + } + + /* Configure GPIO pin interrupt mode */ + GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); +} + +void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, uint8_t output) +{ + assert(pin < 32); + if (output == 0U) + { + base->DR &= ~(1U << pin); /* Set pin output to low level.*/ + } + else + { + base->DR |= (1U << pin); /* Set pin output to high level.*/ + } +} + +void GPIO_SetPinInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + volatile uint32_t *icr; + uint32_t icrShift; + + icrShift = pin; + + /* Register reset to default value */ + base->EDGE_SEL &= ~(1U << pin); + + if(pin < 16) + { + icr = &(base->ICR1); + } + else + { + icr = &(base->ICR2); + icrShift -= 16; + } + switch(pinInterruptMode) + { + case(kGPIO_IntLowLevel): + *icr &= ~(3U << (2 * icrShift)); + break; + case(kGPIO_IntHighLevel): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift)); + break; + case(kGPIO_IntRisingEdge): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift)); + break; + case(kGPIO_IntFallingEdge): + *icr |= (3U << (2 * icrShift)); + break; + case(kGPIO_IntRisingOrFallingEdge): + base->EDGE_SEL |= (1U << pin); + break; + default: + break; + } +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..53d6ba5737310199bbda23f584490ced5405b715 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.h @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.0.0. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ +} gpio_interrupt_mode_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + gpio_interrupt_mode_t interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param pin Specifies the pin number + * @param initConfig pointer to a @ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config); +/*@}*/ + +/*! + * @name GPIO Reads and Write Functions + * @{ + */ + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. */ +void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, uint8_t output); + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_SetPinsOutput(GPIO_Type* base, uint32_t mask) +{ + base->DR |= mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type* base, uint32_t mask) +{ + base->DR &= ~mask; +} + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO port input value. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (((base->DR) >> pin) & 0x1U); +} +/*@}*/ + +/*! + * @name GPIO Reads Pad Status Functions + * @{ + */ + + /*! + * @brief Reads the current GPIO pin pad status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO pin pad status value. + */ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)(((base->PSR) >> pin) & 0x1U); +} +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Sets the current pin interrupt mode. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pininterruptMode pointer to a @ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_EnableInterrupts(GPIO_Type* base, uint32_t mask) +{ + base->IMR |= mask; +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_DisableInterrupts(GPIO_Type* base, uint32_t mask) +{ + base->IMR &= ~mask; +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type* base) +{ + return base->ISR; +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type* base, uint32_t mask) +{ + base->ISR = mask; +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..c17020e1004e61a4d3857a1d67e7184023bfa79d --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.c @@ -0,0 +1,1382 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief i2c transfer state. */ +enum _i2c_transfer_states +{ + kIdleState = 0x0U, /*!< I2C bus idle. */ + kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ + kSendCommandState = 0x2U, /*!< Send command byte phase. */ + kSendDataState = 0x3U, /*!< Send data transfer phase. */ + kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ + kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, + kIrqFlags = kI2C_GlobalInterruptEnable, +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for I2C module. + * + * @param base I2C peripheral base address. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Check and clear status operation. + * + * @param base I2C peripheral base address. + * @param status current i2c hardware status. + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + */ +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @param isDone input param to get whether the thing is done, true is done + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief I2C common interrupt handler. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief SCL clock divider used to calculate baudrate. */ +static const uint16_t s_i2cDividerTable[] = { + 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 160, 192, 240, + 288, 320, 384, 480, 576, 640, 768, 960, 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840, + 22, 24, 26, 28, 32, 36, 40, 44, 48, 56, 64, 72, 80, 96, 112, 128, + 160, 192, 224, 256, 320, 384, 448, 512, 640, 768, 896, 1024, 1280, 1536, 1792, 2048}; + +/*! @brief Pointers to i2c bases for each instance. */ +static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; + +/*! @brief Pointers to i2c IRQ number for each instance. */ +static const IRQn_Type s_i2cIrqs[] = I2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to i2c clocks for each instance. */ +static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to i2c handles for each instance. */ +static void *s_i2cHandle[ARRAY_SIZE(s_i2cBases)] = {NULL}; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static i2c_isr_t s_i2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static i2c_isr_t s_i2cSlaveIsr; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++) + { + if (s_i2cBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_i2cBases)); + + return instance; +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + i2c_direction_t direction = xfer->direction; + + /* Initialize the handle transfer information. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Initial transfer state. */ + if (handle->transfer.subaddressSize > 0) + { + if (xfer->direction == kI2C_Read) + { + direction = kI2C_Write; + } + } + + handle->state = kCheckAddressState; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + return result; +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->I2SR &= (uint8_t)(~kI2C_ArbitrationLostFlag); + + /* Reset I2C controller*/ + base->I2CR &= ~I2C_I2CR_IEN_MASK; + base->I2CR |= I2C_I2CR_IEN_MASK; + + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = base->I2SR; + *isDone = false; + volatile uint8_t dummy = 0; + bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) || + ((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U)); + + /* Add this to avoid build warning. */ + dummy++; + + /* Check & clear error flags. */ + result = I2C_CheckAndClearError(base, statusFlags); + + /* Ignore Nak when it's appeared for last byte. */ + if ((result == kStatus_I2C_Nak) && ignoreNak) + { + result = kStatus_Success; + } + /* Handle Check address state to check the slave address is Acked in slave + probe application. */ + if (handle->state == kCheckAddressState) + { + if (statusFlags & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Addr_Nak; + } + else + { + if (handle->transfer.subaddressSize > 0) + { + handle->state = kSendCommandState; + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + } + else + { + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + } + } + + if (result) + { + return result; + } + + /* Run state machine. */ + switch (handle->state) + { + /* Send I2C command. */ + case kSendCommandState: + if (handle->transfer.subaddressSize) + { + handle->transfer.subaddressSize--; + base->I2DR = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->I2DR = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + } + else + { + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + break; + + /* Send I2C data. */ + case kSendDataState: + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->I2DR = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + break; + + /* Start I2C data receive. */ + case kReceiveDataBeginState: + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Read dummy to release the bus. */ + dummy = base->I2DR; + + /* Next state, receive data. */ + handle->state = kReceiveDataState; + break; + + /* Receive I2C data. */ + case kReceiveDataState: + /* Receive one byte of data. */ + if (handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0) + { + *isDone = true; + + /* Send stop if kI2C_TransferNoStop is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + else + { + base->I2CR |= I2C_I2CR_MTX_MASK; + } + } + + /* Send NAK at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + /* Read the data byte into the transfer buffer. */ + *handle->transfer.data = base->I2DR; + handle->transfer.data++; + } + break; + + default: + break; + } + + return result; +} + +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) +{ + /* Check if master interrupt. */ + if ((base->I2SR & kI2C_ArbitrationLostFlag) || (base->I2CR & I2C_I2CR_MSTA_MASK)) + { + s_i2cMasterIsr(base, handle); + } + else + { + s_i2cSlaveIsr(base, handle); + } + __DSB(); +} + +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig && srcClock_Hz); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable I2C prior to configuring it. */ + base->I2CR &= ~(I2C_I2CR_IEN_MASK); + + /* Clear all flags. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Configure baud rate. */ + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + + /* Enable the I2C peripheral based on the configuration. */ + base->I2CR = I2C_I2CR_IEN(masterConfig->enableMaster); +} + +void I2C_MasterDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + assert(masterConfig); + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; + + /* Enable the I2C peripheral. */ + masterConfig->enableMaster = true; +} + +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->I2CR |= I2C_I2CR_IIEN_MASK; + } +} + +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->I2CR &= ~I2C_I2CR_IIEN_MASK; + } +} + +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t computedRate; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestIcr = 0u; + uint8_t i; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i) + { + computedRate = srcClock_Hz / s_i2cDividerTable[i]; + absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); + + if (absError < bestError) + { + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0) + { + break; + } + } + } + + /* Set frequency register based on best settings. */ + base->IFDR = I2C_IFDR_IC(bestIcr); +} + +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use. */ + if (statusFlags & kI2C_BusBusyFlag) + { + result = kStatus_I2C_Busy; + } + else + { + /* Send the START signal. */ + base->I2CR |= I2C_I2CR_MSTA_MASK | I2C_I2CR_MTX_MASK; + + base->I2DR = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use, but not by us. */ + if ((statusFlags & kI2C_BusBusyFlag) && ((base->I2CR & I2C_I2CR_MSTA_MASK) == 0)) + { + result = kStatus_I2C_Busy; + } + else + { + /* We are already in a transfer, so send a repeated start. */ + base->I2CR |= I2C_I2CR_RSTA_MASK | I2C_I2CR_MTX_MASK; + + base->I2DR = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = kStatus_Success; + uint16_t timeout = UINT16_MAX; + + /* Issue the STOP command on the bus. */ + base->I2CR &= ~(I2C_I2CR_MSTA_MASK | I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Wait until data transfer complete. */ + while ((base->I2SR & kI2C_BusBusyFlag) && (--timeout)) + { + } + + if (timeout == 0) + { + result = kStatus_I2C_Timeout; + } + + return result; +} + +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags) +{ + status_t result = kStatus_Success; + uint8_t statusFlags = 0; + + /* Wait until the data register is ready for transmit. */ + while (!(base->I2SR & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to transmit data. */ + base->I2CR |= I2C_I2CR_MTX_MASK; + + while (txSize--) + { + /* Send a byte of data. */ + base->I2DR = *txBuff++; + + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + statusFlags = base->I2SR; + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ + if (statusFlags & kI2C_ArbitrationLostFlag) + { + base->I2SR = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + + if ((statusFlags & kI2C_ReceiveNakFlag) && txSize) + { + base->I2SR = kI2C_ReceiveNakFlag; + result = kStatus_I2C_Nak; + } + + if (result != kStatus_Success) + { + /* Breaking out of the send loop. */ + break; + } + } + + if (((result == kStatus_Success) && (!(flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak)) + { + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Send stop. */ + result = I2C_MasterStop(base); + } + + return result; +} + +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait until the data register is ready for transmit. */ + while (!(base->I2SR & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* If rxSize equals 1, configure to send NAK. */ + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Do dummy read. */ + dummy = base->I2DR; + + while ((rxSize--)) + { + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Single byte use case. */ + if (rxSize == 0) + { + if (!(flags & kI2C_TransferNoStopFlag)) + { + /* Issue STOP command before reading last byte. */ + result = I2C_MasterStop(base); + } + else + { + /* Change direction to Tx to avoid extra clocks. */ + base->I2CR |= I2C_I2CR_MTX_MASK; + } + } + + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Read from the data register. */ + *rxBuff++ = base->I2DR; + } + + return result; +} + +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + assert(xfer); + + i2c_direction_t direction = xfer->direction; + status_t result = kStatus_Success; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Wait until ready to complete. */ + while (!(base->I2SR & kI2C_TransferCompleteFlag)) + { + } + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (xfer->flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + } + + /* Return if error. */ + if (result) + { + return result; + } + + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->I2SR); + + /* Return if error. */ + if (result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + I2C_MasterStop(base); + } + + return result; + } + + /* Send subaddress. */ + if (xfer->subaddressSize) + { + do + { + /* Clear interrupt pending flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + xfer->subaddressSize--; + base->I2DR = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); + + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->I2SR); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + } while ((xfer->subaddressSize > 0) && (result == kStatus_Success)); + + if (xfer->direction == kI2C_Read) + { + /* Clear pending flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); + + /* Return if error. */ + if (result) + { + return result; + } + + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->I2SR); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + I2C_MasterStop(base); + } + + return result; + } + } + } + + /* Transmit data. */ + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + { + /* Send Data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + + /* Receive Data. */ + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + { + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + + return result; +} + +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save master interrupt handler. */ + s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result = kStatus_Success; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kIdleState) + { + result = kStatus_I2C_Busy; + } + else + { + /* Start up the master transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + if (result == kStatus_Success) + { + /* Enable the I2C interrupts. */ + I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable); + } + } + + return result; +} + +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + assert(handle); + + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Reset the state to idle. */ + handle->state = kIdleState; + + /* Send STOP signal. */ + if (handle->transfer.direction == kI2C_Read) + { + base->I2CR |= I2C_I2CR_TXAK_MASK; + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + base->I2CR &= ~(I2C_I2CR_MSTA_MASK | I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + dummy = base->I2DR; + } + else + { + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + base->I2CR &= ~(I2C_I2CR_MSTA_MASK | I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + } +} + +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; + status_t result = kStatus_Success; + bool isDone; + + /* Clear the interrupt flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Check transfer complete flag. */ + result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); + + if (isDone || result) + { + /* Send stop command if transfer done or received Nak. */ + if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) || + (result == kStatus_I2C_Addr_Nak)) + { + /* Ensure stop command is a need. */ + if ((base->I2CR & I2C_I2CR_MSTA_MASK)) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + } + + /* Restore handle to idle state. */ + handle->state = kIdleState; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Call the callback function after the function has completed. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->IADR = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + base->I2CR = I2C_I2CR_IEN(slaveConfig->enableSlave); +} + +void I2C_SlaveDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + /* Enable the I2C peripheral. */ + slaveConfig->enableSlave = true; +} + +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait for address match flag. */ + while (!(base->I2SR & kI2C_AddressMatchFlag)) + { + } + + /* Read dummy to release bus. */ + dummy = base->I2DR; + + result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferDefaultFlag); + + /* Switch to receive mode. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->I2DR; + + return result; +} + +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait for address match and int pending flag. */ + while (!(base->I2SR & kI2C_AddressMatchFlag)) + { + } + + /* Read dummy to release bus. */ + dummy = base->I2DR; + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK); + + while (rxSize--) + { + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Read from the data register. */ + *rxBuff++ = base->I2DR; + } +} + +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save slave interrupt handler. */ + s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(handle); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + else + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Clear transfer in handle. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->state = kCheckAddressState; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; + + /* Clear all flags. */ + I2C_SlaveClearStatusFlags(base, kClearFlags); + + /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I2C_EnableInterrupts(base, kIrqFlags); + } + + return kStatus_Success; +} + +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + assert(handle); + + if (handle->state != kIdleState) + { + /* Disable interrupts. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Reset transfer info. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Reset the state to idle. */ + handle->state = kIdleState; + } +} + +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + uint16_t status; + bool doTransmit = false; + i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; + i2c_slave_transfer_t *xfer; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + status = I2C_SlaveGetStatusFlags(base); + xfer = &(handle->transfer); + + /* Clear the interrupt flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Check NAK */ + if (status & kI2C_ReceiveNakFlag) + { + /* Set receive mode. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Read dummy. */ + dummy = base->I2DR; + + if (handle->transfer.dataSize != 0) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_I2C_Nak; + handle->state = kIdleState; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->state = kIdleState; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + } + /* Check address match. */ + else if (status & kI2C_AddressMatchFlag) + { + xfer->event = kI2C_SlaveAddressMatchEvent; + + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + handle->state = kSendDataState; + /* Change direction to send data. */ + base->I2CR |= I2C_I2CR_MTX_MASK; + + doTransmit = true; + } + else + { + handle->state = kReceiveDataState; + /* Slave receive, master writing to slave. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Read dummy to release the bus. */ + dummy = base->I2DR; + } + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + /* Check transfer complete flag. */ + else if (status & kI2C_TransferCompleteFlag) + { + /* Slave transmit, master reading from slave. */ + if (handle->state == kSendDataState) + { + doTransmit = true; + } + else + { + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveReceiveEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + /* Slave receive, master writing to slave. */ + uint8_t data = base->I2DR; + + if (handle->transfer.dataSize) + { + /* Receive data. */ + *handle->transfer.data++ = data; + handle->transfer.dataSize--; + xfer->transferredCount++; + + if (!handle->transfer.dataSize) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->state = kIdleState; + + /* Proceed receive complete event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + } + } + } + else + { + /* Read dummy to release bus. */ + dummy = base->I2DR; + } + + /* Send data if there is the need. */ + if (doTransmit) + { + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveTransmitEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + if (handle->transfer.dataSize) + { + /* Send data. */ + base->I2DR = *handle->transfer.data++; + handle->transfer.dataSize--; + xfer->transferredCount++; + } + else + { + /* Switch to receive mode. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->I2DR; + + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->state = kIdleState; + + /* Proceed txdone event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + } +} + +#if defined(I2C1) +void I2C1_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); +} +#endif + +#if defined(I2C2) +void I2C2_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); +} +#endif + +#if defined(I2C3) +void I2C3_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); +} +#endif + +#if defined(I2C4) +void I2C4_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C4, s_i2cHandle[4]); +} +#endif + +extern void *imx6ull_get_periph_paddr(uint32_t vaddr); +void I2C_DriverIRQHandler(int irq, void *base) +{ + uint32_t i2c_instance = 0; + i2c_instance = I2C_GetInstance(imx6ull_get_periph_paddr((uint32_t)base)); + I2C_TransferCommonIRQHandler(base, s_i2cHandle[i2c_instance]); +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..9656b65eae8705e3172d3aa1fda2ae1d6d32aed4 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.h @@ -0,0 +1,671 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version 2.0.0. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief I2C status return codes. */ +enum _i2c_status +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ + kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NAK received during the address probe. */ +}; + +/*! + * @brief I2C peripheral flags + * + * The following status register flags can be cleared: + * - #kI2C_ArbitrationLostFlag + * - #kI2C_IntPendingFlag + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + * + */ +enum _i2c_flags +{ + kI2C_ReceiveNakFlag = I2C_I2SR_RXAK_MASK, /*!< I2C receive NAK flag. */ + kI2C_IntPendingFlag = I2C_I2SR_IIF_MASK, /*!< I2C interrupt pending flag. */ + kI2C_TransferDirectionFlag = I2C_I2SR_SRW_MASK, /*!< I2C transfer direction flag. */ + kI2C_ArbitrationLostFlag = I2C_I2SR_IAL_MASK, /*!< I2C arbitration lost flag. */ + kI2C_BusBusyFlag = I2C_I2SR_IBB_MASK, /*!< I2C bus busy flag. */ + kI2C_AddressMatchFlag = I2C_I2SR_IAAS_MASK, /*!< I2C address match flag. */ + kI2C_TransferCompleteFlag = I2C_I2SR_ICF_MASK, + /*!< I2C transfer complete flag. */ +}; + +/*! @brief I2C feature interrupt source. */ +enum _i2c_interrupt_enable +{ + kI2C_GlobalInterruptEnable = I2C_I2CR_IIEN_MASK, /*!< I2C global interrupt. */ +}; + +/*! @brief The direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0x0U, /*!< Master transmits to the slave. */ + kI2C_Read = 0x1U, /*!< Master receives from the slave. */ +} i2c_direction_t; + +/*! @brief I2C transfer control flag. */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x0U, /*!< A transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x1U, /*!< A transfer starts without a start signal. */ + kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */ + kI2C_TransferNoStopFlag = 0x4U, /*!< A transfer ends without a stop signal. */ +}; + +/*! @brief I2C master user configuration. */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ + uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ +} i2c_master_config_t; + +/*! @brief I2C master handle typedef. */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! @brief I2C master transfer callback typedef. */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C master transfer structure. */ +typedef struct _i2c_master_transfer +{ + uint32_t flags; /*!< A transfer flag which controls the transfer. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + i2c_direction_t direction; /*!< A transfer direction, read or write. */ + uint32_t subaddress; /*!< A sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< A size of the command buffer. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ +} i2c_master_transfer_t; + +/*! @brief I2C master handle structure. */ +struct _i2c_master_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< A transfer state maintained during transfer. */ + i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */ + void *userData; /*!< A callback parameter passed to the callback function. */ +}; + +/*! + * @brief Set of events sent to the callback for nonblocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< A callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< A callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveTransmitAckEvent = 0x08U, /*!< A callback needs to either transmit an ACK or NACK. */ + kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ + /*! A bit mask of all available events. */ + kI2C_SlaveAllEvents = + kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | kI2C_SlaveCompletionEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C slave user configuration. */ +typedef struct _i2c_slave_config +{ + bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ + uint16_t slaveAddress; /*!< A slave address configuration. */ +} i2c_slave_config_t; + +/*! @brief I2C slave transfer structure. */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated + start. */ +} i2c_slave_transfer_t; + +/*! @brief I2C slave transfer callback typedef. */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); + +/*! @brief I2C slave handle structure. */ +struct _i2c_slave_handle +{ + volatile uint8_t state; /*!< A transfer state maintained during transfer. */ + i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ + uint32_t eventMask; /*!< A mask of enabled events. */ + i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */ + void *userData; /*!< A callback parameter passed to the callback. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can be custom filled + * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * This is an example. + * @code + * i2c_master_config_t config = { + * .enableMaster = true, + * .baudRate_Bps = 100000 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param masterConfig A pointer to the master configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * @param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterInit(). + * Use the initialized structure unchanged in the I2C_MasterInit() or modify + * the structure before calling the I2C_MasterInit(). + * This is an example. + * @code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * @endcode + * @param masterConfig A pointer to the master configuration structure. +*/ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initialize the I2C with the slave configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. + * This is an example. + * @code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .slaveAddress = 0x1DU, + * }; + * I2C_SlaveInit(I2C0, &config); + * @endcode + * + * @param base I2C base pointer + * @param slaveConfig A pointer to the slave configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * @param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveInit(). + * Modify fields of the structure before calling the I2C_SlaveInit(). + * This is an example. + * @code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * @endcode + * @param slaveConfig A pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Enables or disabless the I2C peripheral operation. + * + * @param base I2C base pointer + * @param enable Pass true to enable and false to disable the module. + */ +static inline void I2C_Enable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->I2CR |= I2C_I2CR_IEN_MASK; + } + else + { + base->I2CR &= ~I2C_I2CR_IEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +static inline uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) +{ + return base->I2SR; +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag. + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + base->I2SR = (uint8_t)statusMask; +} + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) +{ + return I2C_MasterGetStatusFlags(base); +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + I2C_MasterClearStatusFlags(base, statusMask); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); + +/* @} */ +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the I2C master transfer baud rate. + * + * @param base I2C base pointer + * @param baudRate_Bps the baud rate value in bps + * @param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag +* to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag +* to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + */ +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note Calling the API returns immediately after transfer initiates. The user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Aborts the slave transfer. + * + * @note This API can be called at any time to stop slave for handling the bus events. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Slave interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* _FSL_I2C_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_iomuxc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_iomuxc.h new file mode 100644 index 0000000000000000000000000000000000000000..8f314567f7d56e5faa773af4de9a39c2b1a8b7ec --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_iomuxc.h @@ -0,0 +1,1151 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.0. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Pin function ID */ +/*@{*/ +/*! @brief The pin function ID is a tuple of */ +#define IOMUXC_SNVS_BOOT_MODE0_GPIO5_IO10 0x02290000U, 0x5U, 0x00000000U, 0x0U, 0x02290044U +#define IOMUXC_SNVS_BOOT_MODE1_GPIO5_IO11 0x02290004U, 0x5U, 0x00000000U, 0x0U, 0x02290048U +#define IOMUXC_SNVS_SNVS_TAMPER0_GPIO5_IO00 0x02290008U, 0x5U, 0x00000000U, 0x0U, 0x0229004CU +#define IOMUXC_SNVS_SNVS_TAMPER1_GPIO5_IO01 0x0229000CU, 0x5U, 0x00000000U, 0x0U, 0x02290050U +#define IOMUXC_SNVS_SNVS_TAMPER2_GPIO5_IO02 0x02290010U, 0x5U, 0x00000000U, 0x0U, 0x02290054U +#define IOMUXC_SNVS_SNVS_TAMPER3_GPIO5_IO03 0x02290014U, 0x5U, 0x00000000U, 0x0U, 0x02290058U +#define IOMUXC_SNVS_SNVS_TAMPER4_GPIO5_IO04 0x02290018U, 0x5U, 0x00000000U, 0x0U, 0x0229005CU +#define IOMUXC_SNVS_SNVS_TAMPER5_GPIO5_IO05 0x0229001CU, 0x5U, 0x00000000U, 0x0U, 0x02290060U +#define IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06 0x02290020U, 0x5U, 0x00000000U, 0x0U, 0x02290064U +#define IOMUXC_SNVS_SNVS_TAMPER7_GPIO5_IO07 0x02290024U, 0x5U, 0x00000000U, 0x0U, 0x02290068U +#define IOMUXC_SNVS_SNVS_TAMPER8_GPIO5_IO08 0x02290028U, 0x5U, 0x00000000U, 0x0U, 0x0229006CU +#define IOMUXC_SNVS_SNVS_TAMPER9_GPIO5_IO09 0x0229002CU, 0x5U, 0x00000000U, 0x0U, 0x02290070U +#define IOMUXC_SNVS_TEST_MODE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290030U +#define IOMUXC_SNVS_POR_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290034U +#define IOMUXC_SNVS_ONOFF 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290038U +#define IOMUXC_SNVS_SNVS_PMIC_ON_REQ 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x0229003CU +#define IOMUXC_SNVS_CCM_PMIC_STBY_REQ 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290040U +#define IOMUXC_JTAG_MOD_SJC_MOD 0x020E0044U, 0x0U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_GPT2_CLK 0x020E0044U, 0x1U, 0x020E05A0U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_SPDIF_OUT 0x020E0044U, 0x2U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_ENET1_REF_CLK_25M 0x020E0044U, 0x3U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_CCM_PMIC_RDY 0x020E0044U, 0x4U, 0x020E04C0U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_GPIO1_IO10 0x020E0044U, 0x5U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_SDMA_EXT_EVENT00 0x020E0044U, 0x6U, 0x020E0610U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_TMS_SJC_TMS 0x020E0048U, 0x0U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_GPT2_CAPTURE1 0x020E0048U, 0x1U, 0x020E0598U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_SAI2_MCLK 0x020E0048U, 0x2U, 0x020E05F0U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_CCM_CLKO1 0x020E0048U, 0x3U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_CCM_WAIT 0x020E0048U, 0x4U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_GPIO1_IO11 0x020E0048U, 0x5U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_SDMA_EXT_EVENT01 0x020E0048U, 0x6U, 0x020E0614U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_EPIT1_OUT 0x020E0048U, 0x8U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TDO_SJC_TDO 0x020E004CU, 0x0U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_GPT2_CAPTURE2 0x020E004CU, 0x1U, 0x020E059CU, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_SAI2_TX_SYNC 0x020E004CU, 0x2U, 0x020E05FCU, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_CCM_CLKO2 0x020E004CU, 0x3U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_CCM_STOP 0x020E004CU, 0x4U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_GPIO1_IO12 0x020E004CU, 0x5U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_MQS_RIGHT 0x020E004CU, 0x6U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_EPIT2_OUT 0x020E004CU, 0x8U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDI_SJC_TDI 0x020E0050U, 0x0U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_GPT2_COMPARE1 0x020E0050U, 0x1U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_SAI2_TX_BCLK 0x020E0050U, 0x2U, 0x020E05F8U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_PWM6_OUT 0x020E0050U, 0x4U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_GPIO1_IO13 0x020E0050U, 0x5U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_MQS_LEFT 0x020E0050U, 0x6U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TCK_SJC_TCK 0x020E0054U, 0x0U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_GPT2_COMPARE2 0x020E0054U, 0x1U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_SAI2_RX_DATA 0x020E0054U, 0x2U, 0x020E05F4U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_PWM7_OUT 0x020E0054U, 0x4U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_GPIO1_IO14 0x020E0054U, 0x5U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TRST_B_SJC_TRSTB 0x020E0058U, 0x0U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_GPT2_COMPARE3 0x020E0058U, 0x1U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_SAI2_TX_DATA 0x020E0058U, 0x2U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_PWM8_OUT 0x020E0058U, 0x4U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_GPIO1_IO15 0x020E0058U, 0x5U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_GPIO1_IO00_I2C2_SCL 0x020E005CU, 0x0U, 0x020E05ACU, 0x1U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_GPT1_CAPTURE1 0x020E005CU, 0x1U, 0x020E058CU, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_ANATOP_OTG1_ID 0x020E005CU, 0x2U, 0x020E04B8U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_ENET1_REF_CLK1 0x020E005CU, 0x3U, 0x020E0574U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_MQS_RIGHT 0x020E005CU, 0x4U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x020E005CU, 0x5U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_ENET1_1588_EVENT0_IN 0x020E005CU, 0x6U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_SRC_SYSTEM_RESET 0x020E005CU, 0x7U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_WDOG3_WDOG_B 0x020E005CU, 0x8U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO01_I2C2_SDA 0x020E0060U, 0x0U, 0x020E05B0U, 0x1U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_GPT1_COMPARE1 0x020E0060U, 0x1U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_USB_OTG1_OC 0x020E0060U, 0x2U, 0x020E0664U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_ENET2_REF_CLK2 0x020E0060U, 0x3U, 0x020E057CU, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_MQS_LEFT 0x020E0060U, 0x4U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x020E0060U, 0x5U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_ENET1_1588_EVENT0_OUT 0x020E0060U, 0x6U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_SRC_EARLY_RESET 0x020E0060U, 0x7U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_WDOG1_WDOG_B 0x020E0060U, 0x8U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO02_I2C1_SCL 0x020E0064U, 0x0U, 0x020E05A4U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_GPT1_COMPARE2 0x020E0064U, 0x1U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_USB_OTG2_PWR 0x020E0064U, 0x2U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_ENET1_REF_CLK_25M 0x020E0064U, 0x3U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_USDHC1_WP 0x020E0064U, 0x4U, 0x020E066CU, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x020E0064U, 0x5U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_SDMA_EXT_EVENT00 0x020E0064U, 0x6U, 0x020E0610U, 0x1U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_SRC_ANY_PU_RESET 0x020E0064U, 0x7U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_UART1_TX 0x020E0064U, 0x8U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_UART1_RX 0x020E0064U, 0x8U, 0x020E0624U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO03_I2C1_SDA 0x020E0068U, 0x0U, 0x020E05A8U, 0x1U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_GPT1_COMPARE3 0x020E0068U, 0x1U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_USB_OTG2_OC 0x020E0068U, 0x2U, 0x020E0660U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_USDHC1_CD_B 0x020E0068U, 0x4U, 0x020E0668U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x020E0068U, 0x5U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_CCM_DI0_EXT_CLK 0x020E0068U, 0x6U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_SRC_TESTER_ACK 0x020E0068U, 0x7U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_UART1_RX 0x020E0068U, 0x8U, 0x020E0624U, 0x1U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_UART1_TX 0x020E0068U, 0x8U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO04_ENET1_REF_CLK1 0x020E006CU, 0x0U, 0x020E0574U, 0x1U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_PWM3_OUT 0x020E006CU, 0x1U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_USB_OTG1_PWR 0x020E006CU, 0x2U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_USDHC1_RESET_B 0x020E006CU, 0x4U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x020E006CU, 0x5U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_ENET2_1588_EVENT0_IN 0x020E006CU, 0x6U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_UART5_TX 0x020E006CU, 0x8U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_UART5_RX 0x020E006CU, 0x8U, 0x020E0644U, 0x2U, 0x020E02F8U +#define IOMUXC_GPIO1_IO05_ENET2_REF_CLK2 0x020E0070U, 0x0U, 0x020E057CU, 0x1U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_PWM4_OUT 0x020E0070U, 0x1U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_ANATOP_OTG2_ID 0x020E0070U, 0x2U, 0x020E04BCU, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_CSI_FIELD 0x020E0070U, 0x3U, 0x020E0530U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_USDHC1_VSELECT 0x020E0070U, 0x4U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x020E0070U, 0x5U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_ENET2_1588_EVENT0_OUT 0x020E0070U, 0x6U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_UART5_RX 0x020E0070U, 0x8U, 0x020E0644U, 0x3U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_UART5_TX 0x020E0070U, 0x8U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO06_ENET1_MDIO 0x020E0074U, 0x0U, 0x020E0578U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_ENET2_MDIO 0x020E0074U, 0x1U, 0x020E0580U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_USB_OTG_PWR_WAKE 0x020E0074U, 0x2U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_CSI_MCLK 0x020E0074U, 0x3U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_USDHC2_WP 0x020E0074U, 0x4U, 0x020E069CU, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x020E0074U, 0x5U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_CCM_WAIT 0x020E0074U, 0x6U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_CCM_REF_EN_B 0x020E0074U, 0x7U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_UART1_CTS_B 0x020E0074U, 0x8U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_UART1_RTS_B 0x020E0074U, 0x8U, 0x020E0620U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO07_ENET1_MDC 0x020E0078U, 0x0U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_ENET2_MDC 0x020E0078U, 0x1U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_USB_OTG_HOST_MODE 0x020E0078U, 0x2U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_CSI_PIXCLK 0x020E0078U, 0x3U, 0x020E0528U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_USDHC2_CD_B 0x020E0078U, 0x4U, 0x020E0674U, 0x1U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x020E0078U, 0x5U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_CCM_STOP 0x020E0078U, 0x6U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_UART1_RTS_B 0x020E0078U, 0x8U, 0x020E0620U, 0x1U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_UART1_CTS_B 0x020E0078U, 0x8U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO08_PWM1_OUT 0x020E007CU, 0x0U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_WDOG1_WDOG_B 0x020E007CU, 0x1U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_SPDIF_OUT 0x020E007CU, 0x2U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_CSI_VSYNC 0x020E007CU, 0x3U, 0x020E052CU, 0x1U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_USDHC2_VSELECT 0x020E007CU, 0x4U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x020E007CU, 0x5U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_CCM_PMIC_RDY 0x020E007CU, 0x6U, 0x020E04C0U, 0x1U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_UART5_RTS_B 0x020E007CU, 0x8U, 0x020E0640U, 0x1U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_UART5_CTS_B 0x020E007CU, 0x8U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO09_PWM2_OUT 0x020E0080U, 0x0U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_WDOG1_WDOG_ANY 0x020E0080U, 0x1U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_SPDIF_IN 0x020E0080U, 0x2U, 0x020E0618U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_CSI_HSYNC 0x020E0080U, 0x3U, 0x020E0524U, 0x1U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_USDHC2_RESET_B 0x020E0080U, 0x4U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x020E0080U, 0x5U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_USDHC1_RESET_B 0x020E0080U, 0x6U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_UART5_CTS_B 0x020E0080U, 0x8U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_UART5_RTS_B 0x020E0080U, 0x8U, 0x020E0640U, 0x2U, 0x020E030CU +#define IOMUXC_UART1_TX_DATA_UART1_TX 0x020E0084U, 0x0U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_UART1_RX 0x020E0084U, 0x0U, 0x020E0624U, 0x2U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_ENET1_RDATA02 0x020E0084U, 0x1U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_I2C3_SCL 0x020E0084U, 0x2U, 0x020E05B4U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_CSI_DATA02 0x020E0084U, 0x3U, 0x020E04C4U, 0x1U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_GPT1_COMPARE1 0x020E0084U, 0x4U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_GPIO1_IO16 0x020E0084U, 0x5U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_SPDIF_OUT 0x020E0084U, 0x8U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_UART5_TX 0x020E0084U, 0x9U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_UART5_RX 0x020E0084U, 0x9U, 0x020E0644U, 0x4U, 0x020E0310U +#define IOMUXC_UART1_RX_DATA_UART1_RX 0x020E0088U, 0x0U, 0x020E0624U, 0x3U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_UART1_TX 0x020E0088U, 0x0U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_ENET1_RDATA03 0x020E0088U, 0x1U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_I2C3_SDA 0x020E0088U, 0x2U, 0x020E05B8U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_CSI_DATA03 0x020E0088U, 0x3U, 0x020E04C8U, 0x1U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_GPT1_CLK 0x020E0088U, 0x4U, 0x020E0594U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_GPIO1_IO17 0x020E0088U, 0x5U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_SPDIF_IN 0x020E0088U, 0x8U, 0x020E0618U, 0x1U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_UART5_RX 0x020E0088U, 0x9U, 0x020E0644U, 0x5U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_UART5_TX 0x020E0088U, 0x9U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_CTS_B_UART1_CTS_B 0x020E008CU, 0x0U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_UART1_RTS_B 0x020E008CU, 0x0U, 0x020E0620U, 0x2U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_ENET1_RX_CLK 0x020E008CU, 0x1U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_USDHC1_WP 0x020E008CU, 0x2U, 0x020E066CU, 0x1U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_CSI_DATA04 0x020E008CU, 0x3U, 0x020E04D8U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_ENET2_1588_EVENT1_IN 0x020E008CU, 0x4U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_GPIO1_IO18 0x020E008CU, 0x5U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_USDHC2_WP 0x020E008CU, 0x8U, 0x020E069CU, 0x1U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_UART5_CTS_B 0x020E008CU, 0x9U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_UART5_RTS_B 0x020E008CU, 0x9U, 0x020E0640U, 0x3U, 0x020E0318U +#define IOMUXC_UART1_RTS_B_UART1_RTS_B 0x020E0090U, 0x0U, 0x020E0620U, 0x3U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_UART1_CTS_B 0x020E0090U, 0x0U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_ENET1_TX_ER 0x020E0090U, 0x1U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_USDHC1_CD_B 0x020E0090U, 0x2U, 0x020E0668U, 0x1U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_CSI_DATA05 0x020E0090U, 0x3U, 0x020E04CCU, 0x1U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_ENET2_1588_EVENT1_OUT 0x020E0090U, 0x4U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_GPIO1_IO19 0x020E0090U, 0x5U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_USDHC2_CD_B 0x020E0090U, 0x8U, 0x020E0674U, 0x2U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_UART5_RTS_B 0x020E0090U, 0x9U, 0x020E0640U, 0x4U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_UART5_CTS_B 0x020E0090U, 0x9U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART2_TX_DATA_UART2_TX 0x020E0094U, 0x0U, 0x00000000U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_UART2_RX 0x020E0094U, 0x0U, 0x020E062CU, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_ENET1_TDATA02 0x020E0094U, 0x1U, 0x00000000U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_I2C4_SCL 0x020E0094U, 0x2U, 0x020E05BCU, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_CSI_DATA06 0x020E0094U, 0x3U, 0x020E04DCU, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_GPT1_CAPTURE1 0x020E0094U, 0x4U, 0x020E058CU, 0x1U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_GPIO1_IO20 0x020E0094U, 0x5U, 0x00000000U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_ECSPI3_SS0 0x020E0094U, 0x8U, 0x020E0560U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_RX_DATA_UART2_RX 0x020E0098U, 0x0U, 0x020E062CU, 0x1U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_UART2_TX 0x020E0098U, 0x0U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_ENET1_TDATA03 0x020E0098U, 0x1U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_I2C4_SDA 0x020E0098U, 0x2U, 0x020E05C0U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_CSI_DATA07 0x020E0098U, 0x3U, 0x020E04E0U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_GPT1_CAPTURE2 0x020E0098U, 0x4U, 0x020E0590U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_GPIO1_IO21 0x020E0098U, 0x5U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_SJC_DONE 0x020E0098U, 0x7U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_ECSPI3_SCLK 0x020E0098U, 0x8U, 0x020E0554U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_CTS_B_UART2_CTS_B 0x020E009CU, 0x0U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_UART2_RTS_B 0x020E009CU, 0x0U, 0x020E0628U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_ENET1_CRS 0x020E009CU, 0x1U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_FLEXCAN2_TX 0x020E009CU, 0x2U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_CSI_DATA08 0x020E009CU, 0x3U, 0x020E04E4U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_GPT1_COMPARE2 0x020E009CU, 0x4U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_GPIO1_IO22 0x020E009CU, 0x5U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_SJC_DE_B 0x020E009CU, 0x7U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_ECSPI3_MOSI 0x020E009CU, 0x8U, 0x020E055CU, 0x0U, 0x020E0328U +#define IOMUXC_UART2_RTS_B_UART2_RTS_B 0x020E00A0U, 0x0U, 0x020E0628U, 0x1U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_UART2_CTS_B 0x020E00A0U, 0x0U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_ENET1_COL 0x020E00A0U, 0x1U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_FLEXCAN2_RX 0x020E00A0U, 0x2U, 0x020E0588U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_CSI_DATA09 0x020E00A0U, 0x3U, 0x020E04E8U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_GPT1_COMPARE3 0x020E00A0U, 0x4U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_GPIO1_IO23 0x020E00A0U, 0x5U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_SJC_FAIL 0x020E00A0U, 0x7U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_ECSPI3_MISO 0x020E00A0U, 0x8U, 0x020E0558U, 0x0U, 0x020E032CU +#define IOMUXC_UART3_TX_DATA_UART3_TX 0x020E00A4U, 0x0U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_UART3_RX 0x020E00A4U, 0x0U, 0x020E0634U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_ENET2_RDATA02 0x020E00A4U, 0x1U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_CSI_DATA01 0x020E00A4U, 0x3U, 0x020E04D4U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_UART2_CTS_B 0x020E00A4U, 0x4U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_UART2_RTS_B 0x020E00A4U, 0x4U, 0x020E0628U, 0x2U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_GPIO1_IO24 0x020E00A4U, 0x5U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_SJC_JTAG_ACT 0x020E00A4U, 0x7U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_ANATOP_OTG1_ID 0x020E00A4U, 0x8U, 0x020E04B8U, 0x1U, 0x020E0330U +#define IOMUXC_UART3_RX_DATA_UART3_RX 0x020E00A8U, 0x0U, 0x020E0634U, 0x1U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_UART3_TX 0x020E00A8U, 0x0U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_ENET2_RDATA03 0x020E00A8U, 0x1U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_CSI_DATA00 0x020E00A8U, 0x3U, 0x020E04D0U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_UART2_RTS_B 0x020E00A8U, 0x4U, 0x020E0628U, 0x3U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_UART2_CTS_B 0x020E00A8U, 0x4U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_GPIO1_IO25 0x020E00A8U, 0x5U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_EPIT1_OUT 0x020E00A8U, 0x8U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_CTS_B_UART3_CTS_B 0x020E00ACU, 0x0U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_UART3_RTS_B 0x020E00ACU, 0x0U, 0x020E0630U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_ENET2_RX_CLK 0x020E00ACU, 0x1U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_FLEXCAN1_TX 0x020E00ACU, 0x2U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_CSI_DATA10 0x020E00ACU, 0x3U, 0x020E04ECU, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_ENET1_1588_EVENT1_IN 0x020E00ACU, 0x4U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_GPIO1_IO26 0x020E00ACU, 0x5U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_EPIT2_OUT 0x020E00ACU, 0x8U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_RTS_B_UART3_RTS_B 0x020E00B0U, 0x0U, 0x020E0630U, 0x1U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_UART3_CTS_B 0x020E00B0U, 0x0U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_ENET2_TX_ER 0x020E00B0U, 0x1U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_FLEXCAN1_RX 0x020E00B0U, 0x2U, 0x020E0584U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_CSI_DATA11 0x020E00B0U, 0x3U, 0x020E04F0U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_ENET1_1588_EVENT1_OUT 0x020E00B0U, 0x4U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_GPIO1_IO27 0x020E00B0U, 0x5U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_WDOG1_WDOG_B 0x020E00B0U, 0x8U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART4_TX_DATA_UART4_TX 0x020E00B4U, 0x0U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_UART4_RX 0x020E00B4U, 0x0U, 0x020E063CU, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_ENET2_TDATA02 0x020E00B4U, 0x1U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_I2C1_SCL 0x020E00B4U, 0x2U, 0x020E05A4U, 0x1U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_CSI_DATA12 0x020E00B4U, 0x3U, 0x020E04F4U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_CSU_CSU_ALARM_AUT02 0x020E00B4U, 0x4U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_GPIO1_IO28 0x020E00B4U, 0x5U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_ECSPI2_SCLK 0x020E00B4U, 0x8U, 0x020E0544U, 0x1U, 0x020E0340U +#define IOMUXC_UART4_RX_DATA_UART4_RX 0x020E00B8U, 0x0U, 0x020E063CU, 0x1U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_UART4_TX 0x020E00B8U, 0x0U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_ENET2_TDATA03 0x020E00B8U, 0x1U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_I2C1_SDA 0x020E00B8U, 0x2U, 0x020E05A8U, 0x2U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_CSI_DATA13 0x020E00B8U, 0x3U, 0x020E04F8U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_CSU_CSU_ALARM_AUT01 0x020E00B8U, 0x4U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_GPIO1_IO29 0x020E00B8U, 0x5U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_ECSPI2_SS0 0x020E00B8U, 0x8U, 0x020E0550U, 0x1U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_EPDC_PWRCTRL01 0x020E00B8U, 0x9U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART5_TX_DATA_GPIO1_IO30 0x020E00BCU, 0x5U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_ECSPI2_MOSI 0x020E00BCU, 0x8U, 0x020E054CU, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_EPDC_PWRCTRL02 0x020E00BCU, 0x9U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_UART5_TX 0x020E00BCU, 0x0U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_UART5_RX 0x020E00BCU, 0x0U, 0x020E0644U, 0x6U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_ENET2_CRS 0x020E00BCU, 0x1U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_I2C2_SCL 0x020E00BCU, 0x2U, 0x020E05ACU, 0x2U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_CSI_DATA14 0x020E00BCU, 0x3U, 0x020E04FCU, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_CSU_CSU_ALARM_AUT00 0x020E00BCU, 0x4U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_RX_DATA_UART5_RX 0x020E00C0U, 0x0U, 0x020E0644U, 0x7U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_UART5_TX 0x020E00C0U, 0x0U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_ENET2_COL 0x020E00C0U, 0x1U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_I2C2_SDA 0x020E00C0U, 0x2U, 0x020E05B0U, 0x2U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_CSI_DATA15 0x020E00C0U, 0x3U, 0x020E0500U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_CSU_CSU_INT_DEB 0x020E00C0U, 0x4U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_GPIO1_IO31 0x020E00C0U, 0x5U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_ECSPI2_MISO 0x020E00C0U, 0x8U, 0x020E0548U, 0x1U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_EPDC_PWRCTRL03 0x020E00C0U, 0x9U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_ENET1_RX_DATA0_ENET1_RDATA00 0x020E00C4U, 0x0U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_UART4_RTS_B 0x020E00C4U, 0x1U, 0x020E0638U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_UART4_CTS_B 0x020E00C4U, 0x1U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_PWM1_OUT 0x020E00C4U, 0x2U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_CSI_DATA16 0x020E00C4U, 0x3U, 0x020E0504U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_FLEXCAN1_TX 0x020E00C4U, 0x4U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_GPIO2_IO00 0x020E00C4U, 0x5U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_KPP_ROW00 0x020E00C4U, 0x6U, 0x020E05D0U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_USDHC1_LCTL 0x020E00C4U, 0x8U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_EPDC_SDCE04 0x020E00C4U, 0x9U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA1_ENET1_RDATA01 0x020E00C8U, 0x0U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_UART4_CTS_B 0x020E00C8U, 0x1U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_UART4_RTS_B 0x020E00C8U, 0x1U, 0x020E0638U, 0x1U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_PWM2_OUT 0x020E00C8U, 0x2U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_CSI_DATA17 0x020E00C8U, 0x3U, 0x020E0508U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_FLEXCAN1_RX 0x020E00C8U, 0x4U, 0x020E0584U, 0x1U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_GPIO2_IO01 0x020E00C8U, 0x5U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_KPP_COL00 0x020E00C8U, 0x6U, 0x020E05C4U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_USDHC2_LCTL 0x020E00C8U, 0x8U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_EPDC_SDCE05 0x020E00C8U, 0x9U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_EN_ENET1_RX_EN 0x020E00CCU, 0x0U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_UART5_RTS_B 0x020E00CCU, 0x1U, 0x020E0640U, 0x5U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_UART5_CTS_B 0x020E00CCU, 0x1U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_CSI_DATA18 0x020E00CCU, 0x3U, 0x020E050CU, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_FLEXCAN2_TX 0x020E00CCU, 0x4U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_GPIO2_IO02 0x020E00CCU, 0x5U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_KPP_ROW01 0x020E00CCU, 0x6U, 0x020E05D4U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_USDHC1_VSELECT 0x020E00CCU, 0x8U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_EPDC_SDCE06 0x020E00CCU, 0x9U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_TX_DATA0_ENET1_TDATA00 0x020E00D0U, 0x0U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_UART5_CTS_B 0x020E00D0U, 0x1U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_UART5_RTS_B 0x020E00D0U, 0x1U, 0x020E0640U, 0x6U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_CSI_DATA19 0x020E00D0U, 0x3U, 0x020E0510U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_FLEXCAN2_RX 0x020E00D0U, 0x4U, 0x020E0588U, 0x1U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_GPIO2_IO03 0x020E00D0U, 0x5U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_KPP_COL01 0x020E00D0U, 0x6U, 0x020E05C8U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_USDHC2_VSELECT 0x020E00D0U, 0x8U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_EPDC_SDCE07 0x020E00D0U, 0x9U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA1_ENET1_TDATA01 0x020E00D4U, 0x0U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_UART6_CTS_B 0x020E00D4U, 0x1U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_UART6_RTS_B 0x020E00D4U, 0x1U, 0x020E0648U, 0x2U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_PWM5_OUT 0x020E00D4U, 0x2U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_CSI_DATA20 0x020E00D4U, 0x3U, 0x020E0514U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_ENET2_MDIO 0x020E00D4U, 0x4U, 0x020E0580U, 0x1U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_GPIO2_IO04 0x020E00D4U, 0x5U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_KPP_ROW02 0x020E00D4U, 0x6U, 0x020E05D8U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_WDOG1_WDOG_RST_B_DEB 0x020E00D4U, 0x8U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_EPDC_SDCE08 0x020E00D4U, 0x9U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_EN_ENET1_TX_EN 0x020E00D8U, 0x0U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_UART6_RTS_B 0x020E00D8U, 0x1U, 0x020E0648U, 0x3U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_UART6_CTS_B 0x020E00D8U, 0x1U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_PWM6_OUT 0x020E00D8U, 0x2U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_CSI_DATA21 0x020E00D8U, 0x3U, 0x020E0518U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_ENET2_MDC 0x020E00D8U, 0x4U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_GPIO2_IO05 0x020E00D8U, 0x5U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_KPP_COL02 0x020E00D8U, 0x6U, 0x020E05CCU, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_WDOG2_WDOG_RST_B_DEB 0x020E00D8U, 0x8U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_EPDC_SDCE09 0x020E00D8U, 0x9U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_CLK_ENET1_TX_CLK 0x020E00DCU, 0x0U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_UART7_CTS_B 0x020E00DCU, 0x1U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_UART7_RTS_B 0x020E00DCU, 0x1U, 0x020E0650U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_PWM7_OUT 0x020E00DCU, 0x2U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_CSI_DATA22 0x020E00DCU, 0x3U, 0x020E051CU, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_ENET1_REF_CLK1 0x020E00DCU, 0x4U, 0x020E0574U, 0x2U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_GPIO2_IO06 0x020E00DCU, 0x5U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_KPP_ROW03 0x020E00DCU, 0x6U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_GPT1_CLK 0x020E00DCU, 0x8U, 0x020E0594U, 0x1U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_EPDC_SDOED 0x020E00DCU, 0x9U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_RX_ER_ENET1_RX_ER 0x020E00E0U, 0x0U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_UART7_RTS_B 0x020E00E0U, 0x1U, 0x020E0650U, 0x1U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_UART7_CTS_B 0x020E00E0U, 0x1U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_PWM8_OUT 0x020E00E0U, 0x2U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_CSI_DATA23 0x020E00E0U, 0x3U, 0x020E0520U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_EIM_CRE 0x020E00E0U, 0x4U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_GPIO2_IO07 0x020E00E0U, 0x5U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_KPP_COL03 0x020E00E0U, 0x6U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_GPT1_CAPTURE2 0x020E00E0U, 0x8U, 0x020E0590U, 0x1U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_EPDC_SDOEZ 0x020E00E0U, 0x9U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00 0x020E00E4U, 0x0U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_UART6_TX 0x020E00E4U, 0x1U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_UART6_RX 0x020E00E4U, 0x1U, 0x020E064CU, 0x1U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_I2C3_SCL 0x020E00E4U, 0x3U, 0x020E05B4U, 0x1U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_ENET1_MDIO 0x020E00E4U, 0x4U, 0x020E0578U, 0x1U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_GPIO2_IO08 0x020E00E4U, 0x5U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_KPP_ROW04 0x020E00E4U, 0x6U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_USB_OTG1_PWR 0x020E00E4U, 0x8U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_EPDC_SDDO08 0x020E00E4U, 0x9U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01 0x020E00E8U, 0x0U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_UART6_RX 0x020E00E8U, 0x1U, 0x020E064CU, 0x2U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_UART6_TX 0x020E00E8U, 0x1U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_I2C3_SDA 0x020E00E8U, 0x3U, 0x020E05B8U, 0x1U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_ENET1_MDC 0x020E00E8U, 0x4U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_GPIO2_IO09 0x020E00E8U, 0x5U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_KPP_COL04 0x020E00E8U, 0x6U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_USB_OTG1_OC 0x020E00E8U, 0x8U, 0x020E0664U, 0x1U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_EPDC_SDDO09 0x020E00E8U, 0x9U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_EN_ENET2_RX_EN 0x020E00ECU, 0x0U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_UART7_TX 0x020E00ECU, 0x1U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_UART7_RX 0x020E00ECU, 0x1U, 0x020E0654U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_I2C4_SCL 0x020E00ECU, 0x3U, 0x020E05BCU, 0x1U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_EIM_ADDR26 0x020E00ECU, 0x4U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_GPIO2_IO10 0x020E00ECU, 0x5U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_KPP_ROW05 0x020E00ECU, 0x6U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_ENET1_REF_CLK_25M 0x020E00ECU, 0x8U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_EPDC_SDDO10 0x020E00ECU, 0x9U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00 0x020E00F0U, 0x0U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_UART7_RX 0x020E00F0U, 0x1U, 0x020E0654U, 0x1U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_UART7_TX 0x020E00F0U, 0x1U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_I2C4_SDA 0x020E00F0U, 0x3U, 0x020E05C0U, 0x1U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_EIM_EB_B02 0x020E00F0U, 0x4U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_GPIO2_IO11 0x020E00F0U, 0x5U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_KPP_COL05 0x020E00F0U, 0x6U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_EPDC_SDDO11 0x020E00F0U, 0x9U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01 0x020E00F4U, 0x0U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_UART8_TX 0x020E00F4U, 0x1U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_UART8_RX 0x020E00F4U, 0x1U, 0x020E065CU, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_ECSPI4_SCLK 0x020E00F4U, 0x3U, 0x020E0564U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_EIM_EB_B03 0x020E00F4U, 0x4U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_GPIO2_IO12 0x020E00F4U, 0x5U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_KPP_ROW06 0x020E00F4U, 0x6U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_USB_OTG2_PWR 0x020E00F4U, 0x8U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_EPDC_SDDO12 0x020E00F4U, 0x9U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_EN_ENET2_TX_EN 0x020E00F8U, 0x0U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_UART8_RX 0x020E00F8U, 0x1U, 0x020E065CU, 0x1U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_UART8_TX 0x020E00F8U, 0x1U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_ECSPI4_MOSI 0x020E00F8U, 0x3U, 0x020E056CU, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_EIM_ACLK_FREERUN 0x020E00F8U, 0x4U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_GPIO2_IO13 0x020E00F8U, 0x5U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_KPP_COL06 0x020E00F8U, 0x6U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_USB_OTG2_OC 0x020E00F8U, 0x8U, 0x020E0660U, 0x1U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_EPDC_SDDO13 0x020E00F8U, 0x9U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_CLK_ENET2_TX_CLK 0x020E00FCU, 0x0U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_UART8_CTS_B 0x020E00FCU, 0x1U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_UART8_RTS_B 0x020E00FCU, 0x1U, 0x020E0658U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_ECSPI4_MISO 0x020E00FCU, 0x3U, 0x020E0568U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2 0x020E00FCU, 0x4U, 0x020E057CU, 0x2U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_GPIO2_IO14 0x020E00FCU, 0x5U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_KPP_ROW07 0x020E00FCU, 0x6U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_ANATOP_OTG2_ID 0x020E00FCU, 0x8U, 0x020E04BCU, 0x1U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_EPDC_SDDO14 0x020E00FCU, 0x9U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_RX_ER_ENET2_RX_ER 0x020E0100U, 0x0U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_UART8_RTS_B 0x020E0100U, 0x1U, 0x020E0658U, 0x1U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_UART8_CTS_B 0x020E0100U, 0x1U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_ECSPI4_SS0 0x020E0100U, 0x3U, 0x020E0570U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_EIM_ADDR25 0x020E0100U, 0x4U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_GPIO2_IO15 0x020E0100U, 0x5U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_KPP_COL07 0x020E0100U, 0x6U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_WDOG1_WDOG_ANY 0x020E0100U, 0x8U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_EPDC_SDDO15 0x020E0100U, 0x9U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_LCD_CLK_LCDIF_CLK 0x020E0104U, 0x0U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_LCDIF_WR_RWN 0x020E0104U, 0x1U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_UART4_TX 0x020E0104U, 0x2U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_UART4_RX 0x020E0104U, 0x2U, 0x020E063CU, 0x2U, 0x020E0390U +#define IOMUXC_LCD_CLK_SAI3_MCLK 0x020E0104U, 0x3U, 0x020E0600U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_EIM_CS2_B 0x020E0104U, 0x4U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_GPIO3_IO00 0x020E0104U, 0x5U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_WDOG1_WDOG_RST_B_DEB 0x020E0104U, 0x8U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_EPDC_SDCLK 0x020E0104U, 0x9U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_ENABLE_LCDIF_ENABLE 0x020E0108U, 0x0U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_LCDIF_RD_E 0x020E0108U, 0x1U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_UART4_RX 0x020E0108U, 0x2U, 0x020E063CU, 0x3U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_UART4_TX 0x020E0108U, 0x2U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_SAI3_TX_SYNC 0x020E0108U, 0x3U, 0x020E060CU, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_EIM_CS3_B 0x020E0108U, 0x4U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_GPIO3_IO01 0x020E0108U, 0x5U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_ECSPI2_RDY 0x020E0108U, 0x8U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_EPDC_SDLE 0x020E0108U, 0x9U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_HSYNC_LCDIF_HSYNC 0x020E010CU, 0x0U, 0x020E05DCU, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_LCDIF_RS 0x020E010CU, 0x1U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_UART4_CTS_B 0x020E010CU, 0x2U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_UART4_RTS_B 0x020E010CU, 0x2U, 0x020E0638U, 0x2U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_SAI3_TX_BCLK 0x020E010CU, 0x3U, 0x020E0608U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_WDOG3_WDOG_RST_B_DEB 0x020E010CU, 0x4U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_GPIO3_IO02 0x020E010CU, 0x5U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_ECSPI2_SS1 0x020E010CU, 0x8U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_EPDC_SDOE 0x020E010CU, 0x9U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_VSYNC_LCDIF_VSYNC 0x020E0110U, 0x0U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_LCDIF_BUSY 0x020E0110U, 0x1U, 0x020E05DCU, 0x1U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_UART4_RTS_B 0x020E0110U, 0x2U, 0x020E0638U, 0x3U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_UART4_CTS_B 0x020E0110U, 0x2U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_SAI3_RX_DATA 0x020E0110U, 0x3U, 0x020E0604U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_WDOG2_WDOG_B 0x020E0110U, 0x4U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_GPIO3_IO03 0x020E0110U, 0x5U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_ECSPI2_SS2 0x020E0110U, 0x8U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_EPDC_SDCE00 0x020E0110U, 0x9U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_RESET_LCDIF_RESET 0x020E0114U, 0x0U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_LCDIF_CS 0x020E0114U, 0x1U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_CA7_MX6ULL_EVENTI 0x020E0114U, 0x2U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_SAI3_TX_DATA 0x020E0114U, 0x3U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_WDOG1_WDOG_ANY 0x020E0114U, 0x4U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_GPIO3_IO04 0x020E0114U, 0x5U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_ECSPI2_SS3 0x020E0114U, 0x8U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_EPDC_GDOE 0x020E0114U, 0x9U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_DATA00_LCDIF_DATA00 0x020E0118U, 0x0U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_PWM1_OUT 0x020E0118U, 0x1U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_ENET1_1588_EVENT2_IN 0x020E0118U, 0x3U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_I2C3_SDA 0x020E0118U, 0x4U, 0x020E05B8U, 0x2U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_GPIO3_IO05 0x020E0118U, 0x5U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_SRC_BT_CFG00 0x020E0118U, 0x6U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_SAI1_MCLK 0x020E0118U, 0x8U, 0x020E05E0U, 0x1U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_EPDC_SDDO00 0x020E0118U, 0x9U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA01_LCDIF_DATA01 0x020E011CU, 0x0U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_PWM2_OUT 0x020E011CU, 0x1U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_ENET1_1588_EVENT2_OUT 0x020E011CU, 0x3U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_I2C3_SCL 0x020E011CU, 0x4U, 0x020E05B4U, 0x2U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_GPIO3_IO06 0x020E011CU, 0x5U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_SRC_BT_CFG01 0x020E011CU, 0x6U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_SAI1_TX_SYNC 0x020E011CU, 0x8U, 0x020E05ECU, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_EPDC_SDDO01 0x020E011CU, 0x9U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA02_LCDIF_DATA02 0x020E0120U, 0x0U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_PWM3_OUT 0x020E0120U, 0x1U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_ENET1_1588_EVENT3_IN 0x020E0120U, 0x3U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_I2C4_SDA 0x020E0120U, 0x4U, 0x020E05C0U, 0x2U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_GPIO3_IO07 0x020E0120U, 0x5U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_SRC_BT_CFG02 0x020E0120U, 0x6U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_SAI1_TX_BCLK 0x020E0120U, 0x8U, 0x020E05E8U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_EPDC_SDDO02 0x020E0120U, 0x9U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA03_LCDIF_DATA03 0x020E0124U, 0x0U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_PWM4_OUT 0x020E0124U, 0x1U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_ENET1_1588_EVENT3_OUT 0x020E0124U, 0x3U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_I2C4_SCL 0x020E0124U, 0x4U, 0x020E05BCU, 0x2U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_GPIO3_IO08 0x020E0124U, 0x5U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_SRC_BT_CFG03 0x020E0124U, 0x6U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_SAI1_RX_DATA 0x020E0124U, 0x8U, 0x020E05E4U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_EPDC_SDDO03 0x020E0124U, 0x9U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA04_LCDIF_DATA04 0x020E0128U, 0x0U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_UART8_CTS_B 0x020E0128U, 0x1U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_UART8_RTS_B 0x020E0128U, 0x1U, 0x020E0658U, 0x2U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_ENET2_1588_EVENT2_IN 0x020E0128U, 0x3U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_SPDIF_SR_CLK 0x020E0128U, 0x4U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_GPIO3_IO09 0x020E0128U, 0x5U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_SRC_BT_CFG04 0x020E0128U, 0x6U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_SAI1_TX_DATA 0x020E0128U, 0x8U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_EPDC_SDDO04 0x020E0128U, 0x9U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA05_LCDIF_DATA05 0x020E012CU, 0x0U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_UART8_RTS_B 0x020E012CU, 0x1U, 0x020E0658U, 0x3U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_UART8_CTS_B 0x020E012CU, 0x1U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_ENET2_1588_EVENT2_OUT 0x020E012CU, 0x3U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_SPDIF_OUT 0x020E012CU, 0x4U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_GPIO3_IO10 0x020E012CU, 0x5U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_SRC_BT_CFG05 0x020E012CU, 0x6U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_ECSPI1_SS1 0x020E012CU, 0x8U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_EPDC_SDDO05 0x020E012CU, 0x9U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA06_LCDIF_DATA06 0x020E0130U, 0x0U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_UART7_CTS_B 0x020E0130U, 0x1U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_UART7_RTS_B 0x020E0130U, 0x1U, 0x020E0650U, 0x2U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_ENET2_1588_EVENT3_IN 0x020E0130U, 0x3U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_SPDIF_LOCK 0x020E0130U, 0x4U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_GPIO3_IO11 0x020E0130U, 0x5U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_SRC_BT_CFG06 0x020E0130U, 0x6U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_ECSPI1_SS2 0x020E0130U, 0x8U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_EPDC_SDDO06 0x020E0130U, 0x9U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA07_LCDIF_DATA07 0x020E0134U, 0x0U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_UART7_RTS_B 0x020E0134U, 0x1U, 0x020E0650U, 0x3U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_UART7_CTS_B 0x020E0134U, 0x1U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_ENET2_1588_EVENT3_OUT 0x020E0134U, 0x3U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_SPDIF_EXT_CLK 0x020E0134U, 0x4U, 0x020E061CU, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_GPIO3_IO12 0x020E0134U, 0x5U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_SRC_BT_CFG07 0x020E0134U, 0x6U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_ECSPI1_SS3 0x020E0134U, 0x8U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_EPDC_SDDO07 0x020E0134U, 0x9U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA08_LCDIF_DATA08 0x020E0138U, 0x0U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_SPDIF_IN 0x020E0138U, 0x1U, 0x020E0618U, 0x2U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_CSI_DATA16 0x020E0138U, 0x3U, 0x020E0504U, 0x1U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_EIM_DATA00 0x020E0138U, 0x4U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_GPIO3_IO13 0x020E0138U, 0x5U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_SRC_BT_CFG08 0x020E0138U, 0x6U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_FLEXCAN1_TX 0x020E0138U, 0x8U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_EPDC_PWRIRQ 0x020E0138U, 0x9U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA09_LCDIF_DATA09 0x020E013CU, 0x0U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_SAI3_MCLK 0x020E013CU, 0x1U, 0x020E0600U, 0x1U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_CSI_DATA17 0x020E013CU, 0x3U, 0x020E0508U, 0x1U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_EIM_DATA01 0x020E013CU, 0x4U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_GPIO3_IO14 0x020E013CU, 0x5U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_SRC_BT_CFG09 0x020E013CU, 0x6U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_FLEXCAN1_RX 0x020E013CU, 0x8U, 0x020E0584U, 0x2U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_EPDC_PWRWAKE 0x020E013CU, 0x9U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA10_LCDIF_DATA10 0x020E0140U, 0x0U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_SAI3_RX_SYNC 0x020E0140U, 0x1U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_CSI_DATA18 0x020E0140U, 0x3U, 0x020E050CU, 0x1U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_EIM_DATA02 0x020E0140U, 0x4U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_GPIO3_IO15 0x020E0140U, 0x5U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_SRC_BT_CFG10 0x020E0140U, 0x6U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_FLEXCAN2_TX 0x020E0140U, 0x8U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_EPDC_PWRCOM 0x020E0140U, 0x9U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA11_LCDIF_DATA11 0x020E0144U, 0x0U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_SAI3_RX_BCLK 0x020E0144U, 0x1U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_CSI_DATA19 0x020E0144U, 0x3U, 0x020E0510U, 0x1U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_EIM_DATA03 0x020E0144U, 0x4U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_GPIO3_IO16 0x020E0144U, 0x5U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_SRC_BT_CFG11 0x020E0144U, 0x6U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_FLEXCAN2_RX 0x020E0144U, 0x8U, 0x020E0588U, 0x2U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_EPDC_PWRSTAT 0x020E0144U, 0x9U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA12_LCDIF_DATA12 0x020E0148U, 0x0U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_SAI3_TX_SYNC 0x020E0148U, 0x1U, 0x020E060CU, 0x1U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_CSI_DATA20 0x020E0148U, 0x3U, 0x020E0514U, 0x1U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_EIM_DATA04 0x020E0148U, 0x4U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_GPIO3_IO17 0x020E0148U, 0x5U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_SRC_BT_CFG12 0x020E0148U, 0x6U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_ECSPI1_RDY 0x020E0148U, 0x8U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_EPDC_PWRCTRL00 0x020E0148U, 0x9U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA13_LCDIF_DATA13 0x020E014CU, 0x0U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_SAI3_TX_BCLK 0x020E014CU, 0x1U, 0x020E0608U, 0x1U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_CSI_DATA21 0x020E014CU, 0x3U, 0x020E0518U, 0x1U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_EIM_DATA05 0x020E014CU, 0x4U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_GPIO3_IO18 0x020E014CU, 0x5U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_SRC_BT_CFG13 0x020E014CU, 0x6U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_USDHC2_RESET_B 0x020E014CU, 0x8U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_EPDC_BDR00 0x020E014CU, 0x9U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA14_LCDIF_DATA14 0x020E0150U, 0x0U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_SAI3_RX_DATA 0x020E0150U, 0x1U, 0x020E0604U, 0x1U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_CSI_DATA22 0x020E0150U, 0x3U, 0x020E051CU, 0x1U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_EIM_DATA06 0x020E0150U, 0x4U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_GPIO3_IO19 0x020E0150U, 0x5U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_SRC_BT_CFG14 0x020E0150U, 0x6U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_USDHC2_DATA4 0x020E0150U, 0x8U, 0x020E068CU, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_EPDC_SDSHR 0x020E0150U, 0x9U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA15_LCDIF_DATA15 0x020E0154U, 0x0U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_SAI3_TX_DATA 0x020E0154U, 0x1U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_CSI_DATA23 0x020E0154U, 0x3U, 0x020E0520U, 0x1U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_EIM_DATA07 0x020E0154U, 0x4U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_GPIO3_IO20 0x020E0154U, 0x5U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_SRC_BT_CFG15 0x020E0154U, 0x6U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_USDHC2_DATA5 0x020E0154U, 0x8U, 0x020E0690U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_EPDC_GDRL 0x020E0154U, 0x9U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA16_LCDIF_DATA16 0x020E0158U, 0x0U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_UART7_TX 0x020E0158U, 0x1U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_UART7_RX 0x020E0158U, 0x1U, 0x020E0654U, 0x2U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_CSI_DATA01 0x020E0158U, 0x3U, 0x020E04D4U, 0x1U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_EIM_DATA08 0x020E0158U, 0x4U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_GPIO3_IO21 0x020E0158U, 0x5U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_SRC_BT_CFG24 0x020E0158U, 0x6U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_USDHC2_DATA6 0x020E0158U, 0x8U, 0x020E0694U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_EPDC_GDCLK 0x020E0158U, 0x9U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA17_LCDIF_DATA17 0x020E015CU, 0x0U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_UART7_RX 0x020E015CU, 0x1U, 0x020E0654U, 0x3U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_UART7_TX 0x020E015CU, 0x1U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_CSI_DATA00 0x020E015CU, 0x3U, 0x020E04D0U, 0x1U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_EIM_DATA09 0x020E015CU, 0x4U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_GPIO3_IO22 0x020E015CU, 0x5U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_SRC_BT_CFG25 0x020E015CU, 0x6U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_USDHC2_DATA7 0x020E015CU, 0x8U, 0x020E0698U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_EPDC_GDSP 0x020E015CU, 0x9U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA18_LCDIF_DATA18 0x020E0160U, 0x0U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_PWM5_OUT 0x020E0160U, 0x1U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_CA7_MX6ULL_EVENTO 0x020E0160U, 0x2U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_CSI_DATA10 0x020E0160U, 0x3U, 0x020E04ECU, 0x1U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_EIM_DATA10 0x020E0160U, 0x4U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_GPIO3_IO23 0x020E0160U, 0x5U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_SRC_BT_CFG26 0x020E0160U, 0x6U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_USDHC2_CMD 0x020E0160U, 0x8U, 0x020E0678U, 0x1U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_EPDC_BDR01 0x020E0160U, 0x9U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA19_EIM_DATA11 0x020E0164U, 0x4U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_GPIO3_IO24 0x020E0164U, 0x5U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_SRC_BT_CFG27 0x020E0164U, 0x6U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_USDHC2_CLK 0x020E0164U, 0x8U, 0x020E0670U, 0x1U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_EPDC_VCOM00 0x020E0164U, 0x9U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_LCDIF_DATA19 0x020E0164U, 0x0U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_PWM6_OUT 0x020E0164U, 0x1U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_WDOG1_WDOG_ANY 0x020E0164U, 0x2U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_CSI_DATA11 0x020E0164U, 0x3U, 0x020E04F0U, 0x1U, 0x020E03F0U +#define IOMUXC_LCD_DATA20_EIM_DATA12 0x020E0168U, 0x4U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_GPIO3_IO25 0x020E0168U, 0x5U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_SRC_BT_CFG28 0x020E0168U, 0x6U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_USDHC2_DATA0 0x020E0168U, 0x8U, 0x020E067CU, 0x1U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_EPDC_VCOM01 0x020E0168U, 0x9U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_LCDIF_DATA20 0x020E0168U, 0x0U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_UART8_TX 0x020E0168U, 0x1U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_UART8_RX 0x020E0168U, 0x1U, 0x020E065CU, 0x2U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_ECSPI1_SCLK 0x020E0168U, 0x2U, 0x020E0534U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_CSI_DATA12 0x020E0168U, 0x3U, 0x020E04F4U, 0x1U, 0x020E03F4U +#define IOMUXC_LCD_DATA21_LCDIF_DATA21 0x020E016CU, 0x0U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_UART8_RX 0x020E016CU, 0x1U, 0x020E065CU, 0x3U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_UART8_TX 0x020E016CU, 0x1U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_ECSPI1_SS0 0x020E016CU, 0x2U, 0x020E0540U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_CSI_DATA13 0x020E016CU, 0x3U, 0x020E04F8U, 0x1U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_EIM_DATA13 0x020E016CU, 0x4U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_GPIO3_IO26 0x020E016CU, 0x5U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_SRC_BT_CFG29 0x020E016CU, 0x6U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_USDHC2_DATA1 0x020E016CU, 0x8U, 0x020E0680U, 0x1U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_EPDC_SDCE01 0x020E016CU, 0x9U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA22_LCDIF_DATA22 0x020E0170U, 0x0U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_MQS_RIGHT 0x020E0170U, 0x1U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_ECSPI1_MOSI 0x020E0170U, 0x2U, 0x020E053CU, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_CSI_DATA14 0x020E0170U, 0x3U, 0x020E04FCU, 0x1U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_EIM_DATA14 0x020E0170U, 0x4U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_GPIO3_IO27 0x020E0170U, 0x5U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_SRC_BT_CFG30 0x020E0170U, 0x6U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_USDHC2_DATA2 0x020E0170U, 0x8U, 0x020E0684U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_EPDC_SDCE02 0x020E0170U, 0x9U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA23_EPDC_SDCE03 0x020E0174U, 0x9U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_LCDIF_DATA23 0x020E0174U, 0x0U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_MQS_LEFT 0x020E0174U, 0x1U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_ECSPI1_MISO 0x020E0174U, 0x2U, 0x020E0538U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_CSI_DATA15 0x020E0174U, 0x3U, 0x020E0500U, 0x1U, 0x020E0400U +#define IOMUXC_LCD_DATA23_EIM_DATA15 0x020E0174U, 0x4U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_GPIO3_IO28 0x020E0174U, 0x5U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_SRC_BT_CFG31 0x020E0174U, 0x6U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_USDHC2_DATA3 0x020E0174U, 0x8U, 0x020E0688U, 0x1U, 0x020E0400U +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x020E0178U, 0x0U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_USDHC2_CLK 0x020E0178U, 0x1U, 0x020E0670U, 0x2U, 0x020E0404U +#define IOMUXC_NAND_RE_B_QSPI_B_SCLK 0x020E0178U, 0x2U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_KPP_ROW00 0x020E0178U, 0x3U, 0x020E05D0U, 0x1U, 0x020E0404U +#define IOMUXC_NAND_RE_B_EIM_EB_B00 0x020E0178U, 0x4U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_GPIO4_IO00 0x020E0178U, 0x5U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_ECSPI3_SS2 0x020E0178U, 0x8U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x020E017CU, 0x0U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_USDHC2_CMD 0x020E017CU, 0x1U, 0x020E0678U, 0x2U, 0x020E0408U +#define IOMUXC_NAND_WE_B_QSPI_B_SS0_B 0x020E017CU, 0x2U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_KPP_COL00 0x020E017CU, 0x3U, 0x020E05C4U, 0x1U, 0x020E0408U +#define IOMUXC_NAND_WE_B_EIM_EB_B01 0x020E017CU, 0x4U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_GPIO4_IO01 0x020E017CU, 0x5U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_ECSPI3_SS3 0x020E017CU, 0x8U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x020E0180U, 0x0U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_USDHC2_DATA0 0x020E0180U, 0x1U, 0x020E067CU, 0x2U, 0x020E040CU +#define IOMUXC_NAND_DATA00_QSPI_B_SS1_B 0x020E0180U, 0x2U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_KPP_ROW01 0x020E0180U, 0x3U, 0x020E05D4U, 0x1U, 0x020E040CU +#define IOMUXC_NAND_DATA00_EIM_AD08 0x020E0180U, 0x4U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_GPIO4_IO02 0x020E0180U, 0x5U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_ECSPI4_RDY 0x020E0180U, 0x8U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x020E0184U, 0x0U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_USDHC2_DATA1 0x020E0184U, 0x1U, 0x020E0680U, 0x2U, 0x020E0410U +#define IOMUXC_NAND_DATA01_QSPI_B_DQS 0x020E0184U, 0x2U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_KPP_COL01 0x020E0184U, 0x3U, 0x020E05C8U, 0x1U, 0x020E0410U +#define IOMUXC_NAND_DATA01_EIM_AD09 0x020E0184U, 0x4U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_GPIO4_IO03 0x020E0184U, 0x5U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_ECSPI4_SS1 0x020E0184U, 0x8U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x020E0188U, 0x0U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_USDHC2_DATA2 0x020E0188U, 0x1U, 0x020E0684U, 0x1U, 0x020E0414U +#define IOMUXC_NAND_DATA02_QSPI_B_DATA00 0x020E0188U, 0x2U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_KPP_ROW02 0x020E0188U, 0x3U, 0x020E05D8U, 0x1U, 0x020E0414U +#define IOMUXC_NAND_DATA02_EIM_AD10 0x020E0188U, 0x4U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_GPIO4_IO04 0x020E0188U, 0x5U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_ECSPI4_SS2 0x020E0188U, 0x8U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x020E018CU, 0x0U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_USDHC2_DATA3 0x020E018CU, 0x1U, 0x020E0688U, 0x2U, 0x020E0418U +#define IOMUXC_NAND_DATA03_QSPI_B_DATA01 0x020E018CU, 0x2U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_KPP_COL02 0x020E018CU, 0x3U, 0x020E05CCU, 0x1U, 0x020E0418U +#define IOMUXC_NAND_DATA03_EIM_AD11 0x020E018CU, 0x4U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_GPIO4_IO05 0x020E018CU, 0x5U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_ECSPI4_SS3 0x020E018CU, 0x8U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x020E0190U, 0x0U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_USDHC2_DATA4 0x020E0190U, 0x1U, 0x020E068CU, 0x1U, 0x020E041CU +#define IOMUXC_NAND_DATA04_QSPI_B_DATA02 0x020E0190U, 0x2U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_ECSPI4_SCLK 0x020E0190U, 0x3U, 0x020E0564U, 0x1U, 0x020E041CU +#define IOMUXC_NAND_DATA04_EIM_AD12 0x020E0190U, 0x4U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_GPIO4_IO06 0x020E0190U, 0x5U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_UART2_TX 0x020E0190U, 0x8U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_UART2_RX 0x020E0190U, 0x8U, 0x020E062CU, 0x2U, 0x020E041CU +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x020E0194U, 0x0U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_USDHC2_DATA5 0x020E0194U, 0x1U, 0x020E0690U, 0x1U, 0x020E0420U +#define IOMUXC_NAND_DATA05_QSPI_B_DATA03 0x020E0194U, 0x2U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_ECSPI4_MOSI 0x020E0194U, 0x3U, 0x020E056CU, 0x1U, 0x020E0420U +#define IOMUXC_NAND_DATA05_EIM_AD13 0x020E0194U, 0x4U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_GPIO4_IO07 0x020E0194U, 0x5U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_UART2_RX 0x020E0194U, 0x8U, 0x020E062CU, 0x3U, 0x020E0420U +#define IOMUXC_NAND_DATA05_UART2_TX 0x020E0194U, 0x8U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x020E0198U, 0x0U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_USDHC2_DATA6 0x020E0198U, 0x1U, 0x020E0694U, 0x1U, 0x020E0424U +#define IOMUXC_NAND_DATA06_SAI2_RX_BCLK 0x020E0198U, 0x2U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_ECSPI4_MISO 0x020E0198U, 0x3U, 0x020E0568U, 0x1U, 0x020E0424U +#define IOMUXC_NAND_DATA06_EIM_AD14 0x020E0198U, 0x4U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_GPIO4_IO08 0x020E0198U, 0x5U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_UART2_CTS_B 0x020E0198U, 0x8U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_UART2_RTS_B 0x020E0198U, 0x8U, 0x020E0628U, 0x4U, 0x020E0424U +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x020E019CU, 0x0U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_USDHC2_DATA7 0x020E019CU, 0x1U, 0x020E0698U, 0x1U, 0x020E0428U +#define IOMUXC_NAND_DATA07_QSPI_A_SS1_B 0x020E019CU, 0x2U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_ECSPI4_SS0 0x020E019CU, 0x3U, 0x020E0570U, 0x1U, 0x020E0428U +#define IOMUXC_NAND_DATA07_EIM_AD15 0x020E019CU, 0x4U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_GPIO4_IO09 0x020E019CU, 0x5U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_UART2_RTS_B 0x020E019CU, 0x8U, 0x020E0628U, 0x5U, 0x020E0428U +#define IOMUXC_NAND_DATA07_UART2_CTS_B 0x020E019CU, 0x8U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x020E01A0U, 0x0U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_USDHC2_RESET_B 0x020E01A0U, 0x1U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_QSPI_A_DQS 0x020E01A0U, 0x2U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_PWM3_OUT 0x020E01A0U, 0x3U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_EIM_ADDR17 0x020E01A0U, 0x4U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_GPIO4_IO10 0x020E01A0U, 0x5U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_ECSPI3_SS1 0x020E01A0U, 0x8U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x020E01A4U, 0x0U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_USDHC1_RESET_B 0x020E01A4U, 0x1U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_QSPI_A_SCLK 0x020E01A4U, 0x2U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_PWM4_OUT 0x020E01A4U, 0x3U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_EIM_BCLK 0x020E01A4U, 0x4U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_GPIO4_IO11 0x020E01A4U, 0x5U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_ECSPI3_RDY 0x020E01A4U, 0x8U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x020E01A8U, 0x0U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_USDHC1_DATA4 0x020E01A8U, 0x1U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_QSPI_A_DATA00 0x020E01A8U, 0x2U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_ECSPI3_SS0 0x020E01A8U, 0x3U, 0x020E0560U, 0x1U, 0x020E0434U +#define IOMUXC_NAND_READY_B_EIM_CS1_B 0x020E01A8U, 0x4U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_GPIO4_IO12 0x020E01A8U, 0x5U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_UART3_TX 0x020E01A8U, 0x8U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_UART3_RX 0x020E01A8U, 0x8U, 0x020E0634U, 0x2U, 0x020E0434U +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x020E01ACU, 0x0U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_USDHC1_DATA5 0x020E01ACU, 0x1U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_QSPI_A_DATA01 0x020E01ACU, 0x2U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_ECSPI3_SCLK 0x020E01ACU, 0x3U, 0x020E0554U, 0x1U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_EIM_DTACK_B 0x020E01ACU, 0x4U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_GPIO4_IO13 0x020E01ACU, 0x5U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_UART3_RX 0x020E01ACU, 0x8U, 0x020E0634U, 0x3U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_UART3_TX 0x020E01ACU, 0x8U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x020E01B0U, 0x0U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_USDHC1_DATA6 0x020E01B0U, 0x1U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_QSPI_A_DATA02 0x020E01B0U, 0x2U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_ECSPI3_MOSI 0x020E01B0U, 0x3U, 0x020E055CU, 0x1U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_EIM_ADDR18 0x020E01B0U, 0x4U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_GPIO4_IO14 0x020E01B0U, 0x5U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_UART3_CTS_B 0x020E01B0U, 0x8U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_UART3_RTS_B 0x020E01B0U, 0x8U, 0x020E0630U, 0x2U, 0x020E043CU +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x020E01B4U, 0x0U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_USDHC1_DATA7 0x020E01B4U, 0x1U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_QSPI_A_DATA03 0x020E01B4U, 0x2U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_ECSPI3_MISO 0x020E01B4U, 0x3U, 0x020E0558U, 0x1U, 0x020E0440U +#define IOMUXC_NAND_CLE_EIM_ADDR16 0x020E01B4U, 0x4U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_GPIO4_IO15 0x020E01B4U, 0x5U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_UART3_RTS_B 0x020E01B4U, 0x8U, 0x020E0630U, 0x3U, 0x020E0440U +#define IOMUXC_NAND_CLE_UART3_CTS_B 0x020E01B4U, 0x8U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x020E01B8U, 0x0U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_CSI_FIELD 0x020E01B8U, 0x1U, 0x020E0530U, 0x1U, 0x020E0444U +#define IOMUXC_NAND_DQS_QSPI_A_SS0_B 0x020E01B8U, 0x2U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_PWM5_OUT 0x020E01B8U, 0x3U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_EIM_WAIT 0x020E01B8U, 0x4U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_GPIO4_IO16 0x020E01B8U, 0x5U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_SDMA_EXT_EVENT01 0x020E01B8U, 0x6U, 0x020E0614U, 0x1U, 0x020E0444U +#define IOMUXC_NAND_DQS_SPDIF_EXT_CLK 0x020E01B8U, 0x8U, 0x020E061CU, 0x1U, 0x020E0444U +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x020E01BCU, 0x0U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_GPT2_COMPARE1 0x020E01BCU, 0x1U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_SAI2_RX_SYNC 0x020E01BCU, 0x2U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_SPDIF_OUT 0x020E01BCU, 0x3U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_EIM_ADDR19 0x020E01BCU, 0x4U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_GPIO2_IO16 0x020E01BCU, 0x5U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_SDMA_EXT_EVENT00 0x020E01BCU, 0x6U, 0x020E0610U, 0x2U, 0x020E0448U +#define IOMUXC_SD1_CMD_USB_OTG1_PWR 0x020E01BCU, 0x8U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x020E01C0U, 0x0U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_GPT2_COMPARE2 0x020E01C0U, 0x1U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_SAI2_MCLK 0x020E01C0U, 0x2U, 0x020E05F0U, 0x1U, 0x020E044CU +#define IOMUXC_SD1_CLK_SPDIF_IN 0x020E01C0U, 0x3U, 0x020E0618U, 0x3U, 0x020E044CU +#define IOMUXC_SD1_CLK_EIM_ADDR20 0x020E01C0U, 0x4U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_GPIO2_IO17 0x020E01C0U, 0x5U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_USB_OTG1_OC 0x020E01C0U, 0x8U, 0x020E0664U, 0x2U, 0x020E044CU +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x020E01C4U, 0x0U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_GPT2_COMPARE3 0x020E01C4U, 0x1U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_SAI2_TX_SYNC 0x020E01C4U, 0x2U, 0x020E05FCU, 0x1U, 0x020E0450U +#define IOMUXC_SD1_DATA0_FLEXCAN1_TX 0x020E01C4U, 0x3U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_EIM_ADDR21 0x020E01C4U, 0x4U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_GPIO2_IO18 0x020E01C4U, 0x5U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_ANATOP_OTG1_ID 0x020E01C4U, 0x8U, 0x020E04B8U, 0x2U, 0x020E0450U +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x020E01C8U, 0x0U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA1_GPT2_CLK 0x020E01C8U, 0x1U, 0x020E05A0U, 0x1U, 0x020E0454U +#define IOMUXC_SD1_DATA1_SAI2_TX_BCLK 0x020E01C8U, 0x2U, 0x020E05F8U, 0x1U, 0x020E0454U +#define IOMUXC_SD1_DATA1_FLEXCAN1_RX 0x020E01C8U, 0x3U, 0x020E0584U, 0x3U, 0x020E0454U +#define IOMUXC_SD1_DATA1_EIM_ADDR22 0x020E01C8U, 0x4U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA1_GPIO2_IO19 0x020E01C8U, 0x5U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA1_USB_OTG2_PWR 0x020E01C8U, 0x8U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x020E01CCU, 0x0U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_GPT2_CAPTURE1 0x020E01CCU, 0x1U, 0x020E0598U, 0x1U, 0x020E0458U +#define IOMUXC_SD1_DATA2_SAI2_RX_DATA 0x020E01CCU, 0x2U, 0x020E05F4U, 0x1U, 0x020E0458U +#define IOMUXC_SD1_DATA2_FLEXCAN2_TX 0x020E01CCU, 0x3U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_EIM_ADDR23 0x020E01CCU, 0x4U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_GPIO2_IO20 0x020E01CCU, 0x5U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_CCM_CLKO1 0x020E01CCU, 0x6U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_USB_OTG2_OC 0x020E01CCU, 0x8U, 0x020E0660U, 0x2U, 0x020E0458U +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x020E01D0U, 0x0U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_GPT2_CAPTURE2 0x020E01D0U, 0x1U, 0x020E059CU, 0x1U, 0x020E045CU +#define IOMUXC_SD1_DATA3_SAI2_TX_DATA 0x020E01D0U, 0x2U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_FLEXCAN2_RX 0x020E01D0U, 0x3U, 0x020E0588U, 0x3U, 0x020E045CU +#define IOMUXC_SD1_DATA3_EIM_ADDR24 0x020E01D0U, 0x4U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_GPIO2_IO21 0x020E01D0U, 0x5U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_CCM_CLKO2 0x020E01D0U, 0x6U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_ANATOP_OTG2_ID 0x020E01D0U, 0x8U, 0x020E04BCU, 0x2U, 0x020E045CU +#define IOMUXC_CSI_MCLK_CSI_MCLK 0x020E01D4U, 0x0U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_USDHC2_CD_B 0x020E01D4U, 0x1U, 0x020E0674U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_RAWNAND_CE2_B 0x020E01D4U, 0x2U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_I2C1_SDA 0x020E01D4U, 0x3U, 0x020E05A8U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_EIM_CS0_B 0x020E01D4U, 0x4U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_GPIO4_IO17 0x020E01D4U, 0x5U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_SNVS_HP_VIO_5_CTL 0x020E01D4U, 0x6U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_UART6_TX 0x020E01D4U, 0x8U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_UART6_RX 0x020E01D4U, 0x8U, 0x020E064CU, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_ESAI_TX3_RX2 0x020E01D4U, 0x9U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_PIXCLK_CSI_PIXCLK 0x020E01D8U, 0x0U, 0x020E0528U, 0x1U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_USDHC2_WP 0x020E01D8U, 0x1U, 0x020E069CU, 0x2U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_RAWNAND_CE3_B 0x020E01D8U, 0x2U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_I2C1_SCL 0x020E01D8U, 0x3U, 0x020E05A4U, 0x2U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_EIM_OE 0x020E01D8U, 0x4U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_GPIO4_IO18 0x020E01D8U, 0x5U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_SNVS_HP_VIO_5 0x020E01D8U, 0x6U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_UART6_RX 0x020E01D8U, 0x8U, 0x020E064CU, 0x3U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_UART6_TX 0x020E01D8U, 0x8U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_ESAI_TX2_RX3 0x020E01D8U, 0x9U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_VSYNC_CSI_VSYNC 0x020E01DCU, 0x0U, 0x020E052CU, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_USDHC2_CLK 0x020E01DCU, 0x1U, 0x020E0670U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_I2C2_SDA 0x020E01DCU, 0x3U, 0x020E05B0U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_EIM_RW 0x020E01DCU, 0x4U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_GPIO4_IO19 0x020E01DCU, 0x5U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_PWM7_OUT 0x020E01DCU, 0x6U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_UART6_RTS_B 0x020E01DCU, 0x8U, 0x020E0648U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_UART6_CTS_B 0x020E01DCU, 0x8U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_ESAI_TX4_RX1 0x020E01DCU, 0x9U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_HSYNC_CSI_HSYNC 0x020E01E0U, 0x0U, 0x020E0524U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_USDHC2_CMD 0x020E01E0U, 0x1U, 0x020E0678U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_I2C2_SCL 0x020E01E0U, 0x3U, 0x020E05ACU, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_EIM_LBA_B 0x020E01E0U, 0x4U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_GPIO4_IO20 0x020E01E0U, 0x5U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_PWM8_OUT 0x020E01E0U, 0x6U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_UART6_CTS_B 0x020E01E0U, 0x8U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_UART6_RTS_B 0x020E01E0U, 0x8U, 0x020E0648U, 0x1U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_ESAI_TX1 0x020E01E0U, 0x9U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_DATA00_CSI_DATA02 0x020E01E4U, 0x0U, 0x020E04C4U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_USDHC2_DATA0 0x020E01E4U, 0x1U, 0x020E067CU, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_ECSPI2_SCLK 0x020E01E4U, 0x3U, 0x020E0544U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_EIM_AD00 0x020E01E4U, 0x4U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_GPIO4_IO21 0x020E01E4U, 0x5U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_SRC_INT_BOOT 0x020E01E4U, 0x6U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_UART5_TX 0x020E01E4U, 0x8U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_UART5_RX 0x020E01E4U, 0x8U, 0x020E0644U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_ESAI_TX_HF_CLK 0x020E01E4U, 0x9U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA01_CSI_DATA03 0x020E01E8U, 0x0U, 0x020E04C8U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_USDHC2_DATA1 0x020E01E8U, 0x1U, 0x020E0680U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_ECSPI2_SS0 0x020E01E8U, 0x3U, 0x020E0550U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_EIM_AD01 0x020E01E8U, 0x4U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_GPIO4_IO22 0x020E01E8U, 0x5U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_SAI1_MCLK 0x020E01E8U, 0x6U, 0x020E05E0U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_UART5_RX 0x020E01E8U, 0x8U, 0x020E0644U, 0x1U, 0x020E0474U +#define IOMUXC_CSI_DATA01_UART5_TX 0x020E01E8U, 0x8U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_ESAI_RX_HF_CLK 0x020E01E8U, 0x9U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA02_CSI_DATA04 0x020E01ECU, 0x0U, 0x020E04D8U, 0x1U, 0x020E0478U +#define IOMUXC_CSI_DATA02_USDHC2_DATA2 0x020E01ECU, 0x1U, 0x020E0684U, 0x2U, 0x020E0478U +#define IOMUXC_CSI_DATA02_ECSPI2_MOSI 0x020E01ECU, 0x3U, 0x020E054CU, 0x1U, 0x020E0478U +#define IOMUXC_CSI_DATA02_EIM_AD02 0x020E01ECU, 0x4U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_GPIO4_IO23 0x020E01ECU, 0x5U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_SAI1_RX_SYNC 0x020E01ECU, 0x6U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_UART5_RTS_B 0x020E01ECU, 0x8U, 0x020E0640U, 0x7U, 0x020E0478U +#define IOMUXC_CSI_DATA02_UART5_CTS_B 0x020E01ECU, 0x8U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_ESAI_RX_FS 0x020E01ECU, 0x9U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA03_CSI_DATA05 0x020E01F0U, 0x0U, 0x020E04CCU, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_USDHC2_DATA3 0x020E01F0U, 0x1U, 0x020E0688U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_ECSPI2_MISO 0x020E01F0U, 0x3U, 0x020E0548U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_EIM_AD03 0x020E01F0U, 0x4U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_GPIO4_IO24 0x020E01F0U, 0x5U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_SAI1_RX_BCLK 0x020E01F0U, 0x6U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_UART5_CTS_B 0x020E01F0U, 0x8U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_UART5_RTS_B 0x020E01F0U, 0x8U, 0x020E0640U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_ESAI_RX_CLK 0x020E01F0U, 0x9U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA04_CSI_DATA06 0x020E01F4U, 0x0U, 0x020E04DCU, 0x1U, 0x020E0480U +#define IOMUXC_CSI_DATA04_USDHC2_DATA4 0x020E01F4U, 0x1U, 0x020E068CU, 0x2U, 0x020E0480U +#define IOMUXC_CSI_DATA04_ECSPI1_SCLK 0x020E01F4U, 0x3U, 0x020E0534U, 0x1U, 0x020E0480U +#define IOMUXC_CSI_DATA04_EIM_AD04 0x020E01F4U, 0x4U, 0x00000000U, 0x0U, 0x020E0480U +#define IOMUXC_CSI_DATA04_GPIO4_IO25 0x020E01F4U, 0x5U, 0x00000000U, 0x0U, 0x020E0480U +#define IOMUXC_CSI_DATA04_SAI1_TX_SYNC 0x020E01F4U, 0x6U, 0x020E05ECU, 0x1U, 0x020E0480U +#define IOMUXC_CSI_DATA04_USDHC1_WP 0x020E01F4U, 0x8U, 0x020E066CU, 0x2U, 0x020E0480U +#define IOMUXC_CSI_DATA04_ESAI_TX_FS 0x020E01F4U, 0x9U, 0x00000000U, 0x0U, 0x020E0480U +#define IOMUXC_CSI_DATA05_CSI_DATA07 0x020E01F8U, 0x0U, 0x020E04E0U, 0x1U, 0x020E0484U +#define IOMUXC_CSI_DATA05_USDHC2_DATA5 0x020E01F8U, 0x1U, 0x020E0690U, 0x2U, 0x020E0484U +#define IOMUXC_CSI_DATA05_ECSPI1_SS0 0x020E01F8U, 0x3U, 0x020E0540U, 0x1U, 0x020E0484U +#define IOMUXC_CSI_DATA05_EIM_AD05 0x020E01F8U, 0x4U, 0x00000000U, 0x0U, 0x020E0484U +#define IOMUXC_CSI_DATA05_GPIO4_IO26 0x020E01F8U, 0x5U, 0x00000000U, 0x0U, 0x020E0484U +#define IOMUXC_CSI_DATA05_SAI1_TX_BCLK 0x020E01F8U, 0x6U, 0x020E05E8U, 0x1U, 0x020E0484U +#define IOMUXC_CSI_DATA05_USDHC1_CD_B 0x020E01F8U, 0x8U, 0x020E0668U, 0x2U, 0x020E0484U +#define IOMUXC_CSI_DATA05_ESAI_TX_CLK 0x020E01F8U, 0x9U, 0x00000000U, 0x0U, 0x020E0484U +#define IOMUXC_CSI_DATA06_CSI_DATA08 0x020E01FCU, 0x0U, 0x020E04E4U, 0x1U, 0x020E0488U +#define IOMUXC_CSI_DATA06_USDHC2_DATA6 0x020E01FCU, 0x1U, 0x020E0694U, 0x2U, 0x020E0488U +#define IOMUXC_CSI_DATA06_ECSPI1_MOSI 0x020E01FCU, 0x3U, 0x020E053CU, 0x1U, 0x020E0488U +#define IOMUXC_CSI_DATA06_EIM_AD06 0x020E01FCU, 0x4U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA06_GPIO4_IO27 0x020E01FCU, 0x5U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA06_SAI1_RX_DATA 0x020E01FCU, 0x6U, 0x020E05E4U, 0x1U, 0x020E0488U +#define IOMUXC_CSI_DATA06_USDHC1_RESET_B 0x020E01FCU, 0x8U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA06_ESAI_TX5_RX0 0x020E01FCU, 0x9U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA07_CSI_DATA09 0x020E0200U, 0x0U, 0x020E04E8U, 0x1U, 0x020E048CU +#define IOMUXC_CSI_DATA07_USDHC2_DATA7 0x020E0200U, 0x1U, 0x020E0698U, 0x2U, 0x020E048CU +#define IOMUXC_CSI_DATA07_ECSPI1_MISO 0x020E0200U, 0x3U, 0x020E0538U, 0x1U, 0x020E048CU +#define IOMUXC_CSI_DATA07_EIM_AD07 0x020E0200U, 0x4U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_GPIO4_IO28 0x020E0200U, 0x5U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_SAI1_TX_DATA 0x020E0200U, 0x6U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_USDHC1_VSELECT 0x020E0200U, 0x8U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_ESAI_TX0 0x020E0200U, 0x9U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_DRAM_ADDR00 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0204U +#define IOMUXC_DRAM_ADDR01 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0208U +#define IOMUXC_DRAM_ADDR02 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E020CU +#define IOMUXC_DRAM_ADDR03 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0210U +#define IOMUXC_DRAM_ADDR04 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0214U +#define IOMUXC_DRAM_ADDR05 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0218U +#define IOMUXC_DRAM_ADDR06 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E021CU +#define IOMUXC_DRAM_ADDR07 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0220U +#define IOMUXC_DRAM_ADDR08 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0224U +#define IOMUXC_DRAM_ADDR09 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0228U +#define IOMUXC_DRAM_ADDR10 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E022CU +#define IOMUXC_DRAM_ADDR11 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0230U +#define IOMUXC_DRAM_ADDR12 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0234U +#define IOMUXC_DRAM_ADDR13 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0238U +#define IOMUXC_DRAM_ADDR14 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E023CU +#define IOMUXC_DRAM_ADDR15 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0240U +#define IOMUXC_DRAM_DQM0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0244U +#define IOMUXC_DRAM_DQM1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0248U +#define IOMUXC_DRAM_RAS_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E024CU +#define IOMUXC_DRAM_CAS_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0250U +#define IOMUXC_DRAM_CS0_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0254U +#define IOMUXC_DRAM_CS1_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0258U +#define IOMUXC_DRAM_SDWE_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E025CU +#define IOMUXC_DRAM_ODT0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0260U +#define IOMUXC_DRAM_ODT1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0264U +#define IOMUXC_DRAM_SDBA0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0268U +#define IOMUXC_DRAM_SDBA1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E026CU +#define IOMUXC_DRAM_SDBA2 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0270U +#define IOMUXC_DRAM_SDCKE0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0274U +#define IOMUXC_DRAM_SDCKE1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0278U +#define IOMUXC_DRAM_SDCLK0_P 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E027CU +#define IOMUXC_DRAM_SDQS0_P 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0280U +#define IOMUXC_DRAM_SDQS1_P 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0284U +#define IOMUXC_DRAM_RESET 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0288U +#define IOMUXC_GRP_ADDDS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0490U +#define IOMUXC_GRP_DDRMODE_CTL 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0494U +#define IOMUXC_GRP_B0DS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0498U +#define IOMUXC_GRP_DDRPK 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E049CU +#define IOMUXC_GRP_CTLDS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04A0U +#define IOMUXC_GRP_B1DS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04A4U +#define IOMUXC_GRP_DDRHYS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04A8U +#define IOMUXC_GRP_DDRPKE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04ACU +#define IOMUXC_GRP_DDRMODE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04B0U +#define IOMUXC_GRP_DDR_TYPE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04B4U + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the ENET1_RX_DATA0 Pad as FLEXCAN1_TX: + * @code + * IOMUXC_SetPinMux(IOMUXC_ENET1_RX_DATA0_FLEXCAN1_TX, 0); + * @endcode + * + * This is an example to set the GPIO1_IO02 Pad as I2C1_SCL: + * @code + * IOMUXC_SetPinMux(IOMUXC_GPIO1_IO02_I2C1_SCL, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_GPIO1_IO02_I2C1_SCL: + * @code + * IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO02_I2C1_SCL, IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.c new file mode 100644 index 0000000000000000000000000000000000000000..c1bfd98186e119c65426040cfc434627f8df863c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.c @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_phy.h" +#include "fsl_gpio.h" +#include "ioremap.h" +#include +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0x4FFFFFFU +#define PHY_NEGOTIATION_DELAY 100 +#define PHY_ID 0X7 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +extern uint32_t ENET_GetInstance(ENET_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +status_t phy_reset(GPIO_Type *base,uint32_t pin) +{ + GPIO_Type *gpio_base = NULL; + gpio_pin_config_t sw_config = + { + kGPIO_DigitalOutput, + 0, + kGPIO_NoIntmode, + }; + + gpio_base = (GPIO_Type *)rt_ioremap((void *)base,0x1000); + GPIO_PinInit(gpio_base, pin, &sw_config); + GPIO_WritePinOutput(gpio_base,pin,0); + rt_thread_delay(50); + GPIO_WritePinOutput(gpio_base,pin,1); + + return kStatus_Success; + +} + +status_t PHY_StartNegotiation(ENET_Type *base, uint32_t phyAddr) +{ + uint32_t counter = PHY_TIMEOUT_COUNT; + status_t result = kStatus_Success; + uint32_t bssReg; + uint32_t timeDelay; + + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (result == kStatus_Success) + { + +#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) + uint32_t data = 0; + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if ( result != kStatus_Success) + { + return result; + } + result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); + if (result != kStatus_Success) + { + return result; + } +#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ + /* Set the negotiation. */ + result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); + if (result == kStatus_Success) + { + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, + (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + if (result == kStatus_Success) + { + /* Check auto negotiation complete. */ + while (counter --) + { + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); + if ( result == kStatus_Success) + { + if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) + { + /* Wait a moment for Phy status stable. */ + for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++) + { + __ASM("nop"); + } + break; + } + } + rt_thread_delay(PHY_NEGOTIATION_DELAY); + if (!counter) + { + return kStatus_PHY_AutoNegotiateFail; + } + } + } + } + } + return kStatus_Success; +} + +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz,uint32_t phy_id) +{ + uint32_t counter = PHY_TIMEOUT_COUNT; + uint32_t idReg = 0; + status_t result = kStatus_Success; + + ENET_SetSMI(base, srcClock_Hz, false); + PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); + while ((idReg != phy_id) && (counter != 0)) + { + PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); + counter --; + } + if (!counter) + { + return kStatus_Fail; + } + /* Reset PHY. */ + counter = PHY_TIMEOUT_COUNT; + return result; +} + +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t counter; + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); + + /* Wait for SMI complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) +{ + RT_ASSERT(dataPtr); + + uint32_t counter; + + /* Clear the MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); + + /* Wait for MII complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Get data from MII register. */ + *dataPtr = ENET_ReadSMIData(base); + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable) +{ + status_t result; + uint32_t data = 0; + + /* Set the loop mode. */ + if (enable) + { + if (mode == kPHY_LocalLoop) + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_LOOP_MASK)); + } + } + else + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (mode == kPHY_LocalLoop) + { + /* First read the current status in the basic control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data & ~PHY_BCTL_LOOP_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + return result; +} + +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) +{ + RT_ASSERT(status); + + status_t result = kStatus_Success; + uint32_t data; + + /* Read the basic status register. */ + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); + if (result == kStatus_Success) + { + if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) + { + /* link down. */ + *status = false; + } + else + { + /* link up. */ + *status = true; + } + } + return result; +} + +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) +{ + RT_ASSERT(duplex); + + status_t result = kStatus_Success; + uint32_t data, ctlReg; + + /* Read the control two register. */ + + result = PHY_Read(base, phyAddr, 31, &ctlReg); + + data = ((ctlReg>>2) & 0x7); + switch (data) + { + case 1: + *speed = kPHY_Speed10M; + *duplex = kPHY_HalfDuplex; + break; + case 5: + *speed = kPHY_Speed10M; + *duplex = kPHY_FullDuplex; + break; + case 2: + *speed = kPHY_Speed100M; + *duplex = kPHY_HalfDuplex; + break; + case 6: + *speed = kPHY_Speed100M; + *duplex = kPHY_FullDuplex; + break; + default: + *speed = kPHY_Speed100M; + *duplex = kPHY_FullDuplex; + } + + return result; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.h new file mode 100644 index 0000000000000000000000000000000000000000..417202ea44023472d8fa1bbe4a3125a678c08248 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PHY_H_ +#define _FSL_PHY_H_ + +#include "fsl_enet.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! @brief Defines the PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ +#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ + +#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ + +/*! @brief Defines the mask flag in basic control register. */ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ + +/*!@brief Defines the mask flag of operation mode in control two register*/ +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ + +/*! @brief Defines the mask flag in basic status register. */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ + +/*! @brief Defines the PHY status. */ +enum _phy_status +{ + kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ + kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ +}; + +/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ +typedef enum _phy_speed +{ + kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ + kPHY_Speed100M /*!< ENET PHY 100M speed. */ +} phy_speed_t; + +/*! @brief Defines the PHY link duplex. */ +typedef enum _phy_duplex +{ + kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ + kPHY_FullDuplex /*!< ENET PHY full duplex. */ +} phy_duplex_t; + +/*! @brief Defines the PHY loopback mode. */ +typedef enum _phy_loop +{ + kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ + kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ +} phy_loop_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize the SMI interface and initialize PHY. + * The SMI is the MII management interface between PHY and MAC, which should be + * firstly initialized before any other operation for PHY. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. + * @retval kStatus_Success PHY initialize success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz,uint32_t phy_id); + +/*! + * @brief PHY Negotiation function. + * + * This function initialize the SMI interface and initialize PHY. + * The SMI is the MII management interface between PHY and MAC, which should be + * firstly initialized before any other operation for PHY. + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @retval kStatus_Success PHY negotiate success + * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail + */ +status_t PHY_StartNegotiation(ENET_Type *base, uint32_t phyAddr); + +/*! + * @brief PHY Write function. This function write data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); + +/*! + * @brief PHY Read function. This interface read data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); + +/*! + * @brief Enables/disables PHY loopback. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * the two loopback mode should not be both set. when one loopback mode is set + * the other one should be disabled. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY loopback success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable); + +/*! + * @brief Gets the PHY link status. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY get link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); + +/*! + * @brief hardware reset phy device. + */ +status_t phy_reset(GPIO_Type *base,uint32_t pin); +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHY_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_pwm.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..947876c20409849cef24d0b9d74ddef244d25810 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_pwm.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pwm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance from the base address + * + * @param base PWM peripheral base address + * + * @return The PWM module instance + */ +static uint32_t pwm_get_instance(PWM_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PWM bases for each instance. */ +static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of PWM clock name. */ +static const clock_ip_name_t s_pwmClock[] = PWM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t pwm_get_instance(PWM_Type *base) +{ + uint32_t instance; + uint32_t pwmArrayCount = (sizeof(s_pwmBases) / sizeof(s_pwmBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < pwmArrayCount; instance++) + { + if (s_pwmBases[instance] == base) + { + break; + } + } + + assert(instance < pwmArrayCount); + + return instance; +} + +status_t pwm_init(PWM_Type *base, const pwm_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate PWM clock */ + CLOCK_EnableClock(s_pwmClock[pwm_get_instance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Setup the PWM operation */ + base->PWMCR = (PWM_PWMCR_REPEAT(config->sampleRepeat) | PWM_PWMCR_PRESCALER(config->prescale) | + PWM_PWMCR_CLKSRC(config->clockSource) | PWM_PWMCR_POUTC(config->outputConfig) | + PWM_PWMCR_HCTR(config->halfWordSwap) | PWM_PWMCR_BCTR(config->byteSwap) | + PWM_PWMCR_STOPEN(config->enableStopMode) | PWM_PWMCR_DBGEN(config->enableDebugMode) | + PWM_PWMCR_WAITEN(config->enableWaitMode) | PWM_PWMCR_DOZEN(config->enableDozeMode) | + PWM_PWMCR_FWM(config->fifoWater)); + + return kStatus_Success; +} + +void pwm_deinit(PWM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->PWMCR &= ~(PWM_PWMCR_CLKSRC_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PWM clock */ + CLOCK_DisableClock(s_pwmClock[pwm_get_instance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void pwm_get_default_config(pwm_config_t *config) +{ + assert(config); + + /* Stop mode disabled */ + config->enableStopMode = false; + /* Doze mode disabled */ + config->enableDozeMode = false; + /* Wait mode disabled */ + config->enableWaitMode = false; + /* Debug mode disabled */ + config->enableDebugMode = false; + /* Choose low frequency clock to control counter operation */ + config->clockSource = KPWM_LOW_FREQUENCY_CLOCK; + /* PWM clock devide by (config->prescale + 1) */ + config->prescale = 0U; + /* Output pin is set at rollover and cleared at comparison */ + config->outputConfig = KPWM_SET_AT_ROLLOVER_AND_CLEAR_AT_COMPARISON; + /* FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO */ + config->fifoWater = KPWM_FIFO_WATERMARK_2; + /* Use each sample once */ + config->sampleRepeat = KPMW_EACH_SAMPLE_ONCE; + /* byte ordering remains the same */ + config->byteSwap = KPWM_BYTE_NO_SWAP; + /* Half word swapping does not take place */ + config->halfWordSwap = KPWM_HALF_WORD_NO_SWAP; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_pwm.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..c89c5514cb6606350ee2d5328f52674eb74c23ca --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_pwm.h @@ -0,0 +1,427 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PWM_H_ +#define _FSL_PWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pwm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief PWM clock source select. */ +typedef enum _pwm_clock_source +{ + KPWM_PERIPHERAL_CLOCK = 0U, /*!< The Peripheral clock is used as the clock */ + KPWM_HIGH_FREQUENCY_CLOCK, /*!< High-frequency reference clock is used as the clock */ + KPWM_LOW_FREQUENCY_CLOCK /*!< Low-frequency reference clock(32KHz) is used as the clock */ +} pwm_clock_source_t; + +/*! + * @brief PWM FIFO water mark select. + * Sets the data level at which the FIFO empty flag will be set + */ +typedef enum _pwm_fifo_water_mark +{ + KPWM_FIFO_WATERMARK_1 = 0U, /*!< FIFO empty flag is set when there are more than or equal to 1 empty slots */ + KPWM_FIFO_WATERMARK_2, /*!< FIFO empty flag is set when there are more than or equal to 2 empty slots */ + KPWM_FIFO_WATERMARK_3, /*!< FIFO empty flag is set when there are more than or equal to 3 empty slots */ + KPWM_FIFO_WATERMARK_4 /*!< FIFO empty flag is set when there are more than or equal to 4 empty slots */ +} pwm_fifo_water_mark_t; + +/*! + * @brief PWM byte data swap select. + * It determines the byte ordering of the 16-bit data when it goes into the FIFO from the sample register. + */ +typedef enum _pwm_byte_data_swap +{ + KPWM_BYTE_NO_SWAP = 0U, /*!< byte ordering remains the same */ + KPWM_BYTE_SWAP /*!< byte ordering is reversed */ +} pwm_byte_data_swap_t; + +/*! @brief PWM half-word data swap select. */ +typedef enum _pwm_half_word_data_swap +{ + KPWM_HALF_WORD_NO_SWAP = 0U, /*!< Half word swapping does not take place */ + KPWM_HALF_WORD_SWAP /*!< Half word from write data bus are swapped */ +} pwm_half_word_data_swap_t; + +/*! @brief PWM Output Configuration */ +typedef enum _pwm_output_configuration +{ + KPWM_SET_AT_ROLLOVER_AND_CLEAR_AT_COMPARISON = 0U, /*!< Output pin is set at + rollover and cleared at comparison */ + KPWM_CLEAR_AT_ROLLOVER_AND_SET_AT_COMPARISON, /*!< Output pin is + cleared at rollover and set at comparison */ + KPWM_NO_CONFIGURE /*!< PWM output is disconnected */ +} pwm_output_configuration_t; + +/*! + * @brief PWM FIFO sample repeat + * It determines the number of times each sample from the FIFO is to be used. + */ +typedef enum _pwm_sample_repeat +{ + KPMW_EACH_SAMPLE_ONCE = 0u, /*!< Use each sample once */ + KPWM_EACH_SAMPLE_TWICE, /*!< Use each sample twice */ + KPWM_EACH_SAMPLE_FOUR_TIMES, /*!< Use each sample four times */ + KPWM_EACH_SAMPLE_EIGHT_TIMES /*!< Use each sample eight times */ +} pwm_sample_repeat_t; + +/*! @brief List of PWM interrupt options */ +typedef enum _pwm_interrupt_enable +{ + KPWM_FIFO_EMPTY_INTERRUPT_ENABLE = (1U << 0), /*!< This bit controls the generation of the FIFO Empty interrupt. */ + KPWM_ROLLOVER_INTERRUPT_ENABLE = (1U << 1), /*!< This bit controls the generation of the Rollover interrupt. */ + KPWM_CMPARE_INTERRUPT_ENABLE = (1U << 2) /*!< This bit controls the generation of the Compare interrupt */ +} pwm_interrupt_enable_t; + +/*! @brief List of PWM status flags */ +typedef enum _pwm_status_flags +{ + KPWM_FIFO_EMPTY_FLAG = (1U << 3), /*!< This bit indicates the FIFO data level in comparison to the water + level set by FWM field in the control register. */ + KPWM_ROLLOVER_FLAG = (1U << 4), /*!< This bit shows that a roll-over event has occurred. */ + KPWM_COMPARE_FLAG = (1U << 5), /*!< This bit shows that a compare event has occurred. */ + KPWM_FIFO_WRITE_ERROR_FLAG = (1U << 6) /*!< This bit shows that an attempt + has been made to write FIFO when it is full. */ +} pwm_status_flags_t; + +/*! @brief List of PWM FIFO available */ +typedef enum _pwm_fifo_available +{ + KPWM_NO_DATA_IN_FIFO_FLAG = 0U, /*!< No data available */ + KPWM_ONE_WORD_IN_FIFO_FLAG, /*!< 1 word of data in FIFO */ + KPWM_TWO_WWRDS_IN_FIFO_FLAG, /*!< 2 word of data in FIFO */ + KPWM_THREE_WORDS_IN_FIFO_FLAG, /*!< 3 word of data in FIFO */ + KPWM_FOUR_WORDS_IN_FIFO_FLAG /*!< 4 word of data in FIFO */ +} pwm_fifo_available_t; + +typedef struct _pwm_config +{ + bool enableStopMode; /*!< True: PWM continues to run in stop mode; + False: PWM is paused in stop mode. */ + bool enableDozeMode; /*!< True: PWM continues to run in doze mode; + False: PWM is paused in doze mode. */ + bool enableWaitMode; /*!< True: PWM continues to run in wait mode; + False: PWM is paused in wait mode. */ + bool enableDebugMode; /*!< True: PWM continues to run in debug mode; + False: PWM is paused in debug mode. */ + uint16_t prescale; /*!< Pre-scaler to divide down the clock + The prescaler value is not more than 0xFFF. Divide by (value + 1)*/ + pwm_clock_source_t clockSource; /*!< Clock source for the counter */ + pwm_output_configuration_t outputConfig; /*!< Set the mode of the PWM output on the output pin. */ + pwm_fifo_water_mark_t fifoWater; /*!< Set the data level for FIFO. */ + pwm_sample_repeat_t sampleRepeat; /*!< The number of times each sample from the FIFO is to be used. */ + pwm_byte_data_swap_t byteSwap; /*!< It determines the byte ordering of the 16-bit data when it + goes into the FIFO from the sample register. */ + pwm_half_word_data_swap_t halfWordSwap; /*!< It determines which half word data from the 32-bit + IP Bus interface is written into the lower 16 bits of the sample register. */ +} pwm_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PWM clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PWM driver. + * + * @param base PWM peripheral base address + * @param config Pointer to user's PWM config structure. + * + * @return kStatus_Success means success; else failed. + */ +status_t pwm_init(PWM_Type *base, const pwm_config_t *config); + +/*! + * @brief Gate the PWM submodule clock + * + * @param base PWM peripheral base address + */ +void pwm_deinit(PWM_Type *base); + +/*! + * @brief Fill in the PWM config struct with the default settings + * + * The default values are: + * @code + * config->enableStopMode = false; + * config->enableDozeMode = false; + * config->enableWaitMode = false; + * config->enableDozeMode = false; + * config->clockSource = kPWM_LowFrequencyClock; + * config->prescale = 0U; + * config->outputConfig = kPWM_SetAtRolloverAndClearAtcomparison; + * config->fifoWater = kPWM_FIFOWaterMark_2; + * config->sampleRepeat = kPWM_EachSampleOnce; + * config->byteSwap = kPWM_ByteNoSwap; + * config->halfWordSwap = kPWM_HalfWordNoSwap; + * @endcode + * @param config Pointer to user's PWM config structure. + */ +void pwm_get_default_config(pwm_config_t *config); + +/*! @}*/ + +/*! + * @name PWM start and stop. + * @{ + */ + +/*! + * @brief Starts the PWM counter when the PWM is enabled. + * + * When the PWM is enabled, it begins a new period, the output pin is set to start a new period while + * the prescaler and counter are released and counting begins. + * + * @param base PWM peripheral base address + */ +static inline void pwm_start_timer(PWM_Type *base) +{ + base->PWMCR |= PWM_PWMCR_EN_MASK; +} + +/*! + * @brief Stops the PWM counter when the pwm is disabled. + * + * @param base PWM peripheral base address + */ +static inline void pwm_stop_timer(PWM_Type *base) +{ + base->PWMCR &= ~(PWM_PWMCR_EN_MASK); +} + +/*! @}*/ + +/*! + * @brief Sofrware reset. + * + * PWM is reset when this bit is set to 1. It is a self clearing bit. + * Setting this bit resets all the registers to their reset values except for the STOPEN, + * DOZEN, WAITEN, and DBGEN bits in this control register. + * + * @param base PWM peripheral base address + */ +static inline void pwm_software_reset(PWM_Type *base) +{ + base->PWMCR |= PWM_PWMCR_SWR_MASK; +} + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected PWM interrupts. + * + * @param base PWM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +static inline void pwm_enable_interrupts(PWM_Type *base, uint32_t mask) +{ + base->PWMIR |= (mask & (PWM_PWMIR_FIE_MASK | PWM_PWMIR_RIE_MASK | PWM_PWMIR_CIE_MASK)); +} + +/*! + * @brief Disables the selected PWM interrupts. + * + * @param base PWM peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +static inline void pwm_disable_interrupts(PWM_Type *base, uint32_t mask) +{ + base->PWMIR &= ~(mask & (PWM_PWMIR_FIE_MASK | PWM_PWMIR_RIE_MASK | PWM_PWMIR_CIE_MASK)); +} + +/*! + * @brief Gets the enabled PWM interrupts. + * + * @param base PWM peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +static inline uint32_t pwm_get_enabled_interrupts(PWM_Type *base) +{ + return base->PWMIR; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PWM status flags. + * + * @param base PWM peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +static inline uint32_t pwm_get_status_flags(PWM_Type *base) +{ + uint32_t statusFlags = base->PWMSR; + + statusFlags &= (PWM_PWMSR_FE_MASK | PWM_PWMSR_ROV_MASK | PWM_PWMSR_CMP_MASK | PWM_PWMSR_FWE_MASK); + return statusFlags; +} + +/*! + * @brief Clears the PWM status flags. + * + * @param base PWM peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +static inline void pwm_clear_status_flags(PWM_Type *base, uint32_t mask) +{ + base->PWMSR = (mask & (PWM_PWMSR_FE_MASK | PWM_PWMSR_ROV_MASK | + PWM_PWMSR_CMP_MASK | PWM_PWMSR_FWE_MASK)); +} + +/*! + * @brief Gets the PWM FIFO available. + * + * @param base PWM peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pwm_fifo_available_t + */ +static inline uint32_t pwm_get_fifo_available(PWM_Type *base) +{ + return (base->PWMSR & PWM_PWMSR_FIFOAV_MASK); +} + +/*! @}*/ + +/*! + * @name Sample Interface + * @{ + */ + +/*! + * @brief Sets the PWM sample value. + * + * @param base PWM peripheral base address + * @param mask The sample value. This is the input to the 4x16 FIFO. The value in this register denotes + * the value of the sample being currently used. + */ +static inline void pwm_set_sample_value(PWM_Type *base, uint32_t value) +{ + base->PWMSAR = (value & PWM_PWMSAR_SAMPLE_MASK); +} + +/*! + * @brief Gets the PWM sample value. + * + * @param base PWM peripheral base address + * + * @return The sample value. It can be read only when the PWM is enable. + */ +static inline uint32_t pwm_get_sample_value(PWM_Type *base) +{ + return base->PWMSAR; +} + +/*! @}*/ + +/*! + * @brief Sets the PWM period value. + * + * @param base PWM peripheral base address + * @param mask The period value. The PWM period register (PWM_PWMPR) determines the period of + * the PWM output signal. + * Writing 0xFFFF to this register will achieve the same result as writing 0xFFFE. + * PWMO (Hz) = PCLK(Hz) / (period +2) + */ +static inline void pwm_set_period_value(PWM_Type *base, uint32_t value) +{ + base->PWMPR = (value & PWM_PWMPR_PERIOD_MASK); +} + +/*! + * @brief Gets the PWM period value. + * + * @param base PWM peripheral base address + * + * @return The period value. The PWM period register (PWM_PWMPR) determines the period of + * the PWM output signal. + */ +static inline uint32_t pwm_get_period_value(PWM_Type *base) +{ + return (base->PWMPR & PWM_PWMPR_PERIOD_MASK); +} + +/*! + * @brief Gets the PWM counter value. + * + * @param base PWM peripheral base address + * + * @return The counter value. The current count value. + */ +static inline uint32_t pwm_get_counter_value(PWM_Type *base) +{ + return (base->PWMCNR & PWM_PWMCNR_COUNT_MASK); +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PWM_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.c new file mode 100644 index 0000000000000000000000000000000000000000..1f98dec45cc983a76020e47826ba39937a3c2ff5 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.c @@ -0,0 +1,532 @@ +/* + * Copyright (c) 2017, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_snvs_hp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +#if !(defined(SNVS_HPCOMR_SW_SV_MASK)) +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#endif +#if !(defined(SNVS_HPSR_PI_MASK)) +#define SNVS_HPSR_PI_MASK (0x2U) +#endif +#if !(defined(SNVS_HPSR_HPTA_MASK)) +#define SNVS_HPSR_HPTA_MASK (0x1U) +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Returns RTC time in seconds. + * + * This function is used internally to get actual RTC time in seconds. + * + * @param base SNVS peripheral base address + * + * @return RTC time in seconds + */ +static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +/*! + * @brief Get the SNVS instance from peripheral base address. + * + * @param base SNVS peripheral base address. + * + * @return SNVS instance. + */ +static uint32_t SNVS_HP_GetInstance(SNVS_Type *base); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +/*! @brief Pointer to snvs_hp clock. */ +const clock_ip_name_t s_snvsHpClock[] = SNVS_HP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +static uint32_t SNVS_HP_GetInstance(SNVS_Type *base) +{ + return 0U; +} +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config) +{ + assert(config); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_EnableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK | SNVS_HPCOMR_SW_SV_MASK; + + base->HPCR = SNVS_HPCR_PI_FREQ(config->periodicInterruptFreq); + + if (config->rtcCalEnable) + { + base->HPCR = SNVS_HPCR_HPCALB_VAL_MASK & (config->rtcCalValue << SNVS_HPCR_HPCALB_VAL_SHIFT); + base->HPCR |= SNVS_HPCR_HPCALB_EN_MASK; + } +} + +void SNVS_HP_RTC_Deinit(SNVS_Type *base) +{ + base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_DisableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config) +{ + assert(config); + + config->rtcCalEnable = false; + config->rtcCalValue = 0U; + config->periodicInterruptFreq = 0U; +} + +static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base) +{ + uint32_t seconds = 0; + uint32_t tmp = 0; + + /* Do consecutive reads until value is correct */ + do + { + seconds = tmp; + tmp = (base->HPRTCMR << 17U) | (base->HPRTCLR >> 15U); + } while (tmp != seconds); + + return seconds; +} + +status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0U; + uint32_t tmp = base->HPCR; + + /* disable RTC */ + SNVS_HP_RTC_StopTimer(base); + + /* Return error if the time provided is not valid */ + if (!(SNVS_HP_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + seconds = SNVS_HP_ConvertDatetimeToSeconds(datetime); + + base->HPRTCMR = (uint32_t)(seconds >> 17U); + base->HPRTCLR = (uint32_t)(seconds << 15U); + + /* reenable RTC in case that it was enabled before */ + if (tmp & SNVS_HPCR_RTC_EN_MASK) + { + SNVS_HP_RTC_StartTimer(base); + } + + return kStatus_Success; +} + +void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + SNVS_HP_ConvertSecondsToDatetime(SNVS_HP_RTC_GetSeconds(base), datetime); +} + +status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0U; + uint32_t currSeconds = 0U; + uint32_t tmp = base->HPCR; + + /* Return error if the alarm time provided is not valid */ + if (!(SNVS_HP_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = SNVS_HP_ConvertDatetimeToSeconds(alarmTime); + currSeconds = SNVS_HP_RTC_GetSeconds(base); + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* disable RTC alarm interrupt */ + base->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK; + while (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) + { + } + + /* Set alarm in seconds*/ + base->HPTAMR = (uint32_t)(alarmSeconds >> 17U); + base->HPTALR = (uint32_t)(alarmSeconds << 15U); + + /* reenable RTC alarm interrupt in case that it was enabled before */ + base->HPCR = tmp; + + return kStatus_Success; +} + +void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0U; + + /* Get alarm in seconds */ + alarmSeconds = (base->HPTAMR << 17U) | (base->HPTALR >> 15U); + + SNVS_HP_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) +void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base) +{ + uint32_t tmp = base->HPCR; + + /* disable RTC */ + SNVS_HP_RTC_StopTimer(base); + + base->HPCR |= SNVS_HPCR_HP_TS_MASK; + + /* reenable RTC in case that it was enabled before */ + if (tmp & SNVS_HPCR_RTC_EN_MASK) + { + SNVS_HP_RTC_StartTimer(base); + } +} +#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ + +uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base) +{ + uint32_t flags = 0U; + + if (base->HPSR & SNVS_HPSR_PI_MASK) + { + flags |= kSNVS_RTC_PeriodicInterruptFlag; + } + + if (base->HPSR & SNVS_HPSR_HPTA_MASK) + { + flags |= kSNVS_RTC_AlarmInterruptFlag; + } + + return flags; +} + +void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) +{ + uint32_t wrMask = 0U; + + if (mask & kSNVS_RTC_PeriodicInterruptFlag) + { + wrMask |= SNVS_HPSR_PI_MASK; + } + + if (mask & kSNVS_RTC_AlarmInterruptFlag) + { + wrMask |= SNVS_HPSR_HPTA_MASK; + } + + base->HPSR |= wrMask; +} + +void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) +{ + uint32_t wrMask = 0U; + + if (mask & kSNVS_RTC_PeriodicInterruptEnable) + { + wrMask |= SNVS_HPCR_PI_EN_MASK; + } + + if (mask & kSNVS_RTC_AlarmInterruptEnable) + { + wrMask |= SNVS_HPCR_HPTA_EN_MASK; + } + + base->HPCR |= wrMask; +} + +void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) +{ + uint32_t wrMask = 0U; + + if (mask & kSNVS_RTC_PeriodicInterruptEnable) + { + wrMask |= SNVS_HPCR_PI_EN_MASK; + } + + if (mask & kSNVS_RTC_AlarmInterruptEnable) + { + wrMask |= SNVS_HPCR_HPTA_EN_MASK; + } + + base->HPCR &= ~wrMask; +} + +uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base) +{ + uint32_t val = 0U; + + if (base->HPCR & SNVS_HPCR_PI_EN_MASK) + { + val |= kSNVS_RTC_PeriodicInterruptFlag; + } + + if (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) + { + val |= kSNVS_RTC_AlarmInterruptFlag; + } + + return val; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.h new file mode 100644 index 0000000000000000000000000000000000000000..d06b0233ec9663837d17156ada3819e60297f3e9 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2017, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SNVS_HP_H_ +#define _FSL_SNVS_HP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup snvs_hp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of SNVS interrupts */ +typedef enum _snvs_hp_interrupt_enable +{ + kSNVS_RTC_PeriodicInterruptEnable = 1U, /*!< RTC periodic interrupt.*/ + kSNVS_RTC_AlarmInterruptEnable = 2U, /*!< RTC time alarm.*/ +} snvs_hp_interrupt_enable_t; + +/*! @brief List of SNVS flags */ +typedef enum _snvs_hp_status_flags +{ + kSNVS_RTC_PeriodicInterruptFlag = 1U, /*!< RTC periodic interrupt flag */ + kSNVS_RTC_AlarmInterruptFlag = 2U, /*!< RTC time alarm flag */ +} snvs_hp_status_flags_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _snvs_hp_rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} snvs_hp_rtc_datetime_t; + +/*! + * @brief SNVS config structure + * + * This structure holds the configuration settings for the SNVS peripheral. To initialize this + * structure to reasonable defaults, call the SNVS_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _snvs_hp_rtc_config +{ + bool rtcCalEnable; /*!< true: RTC calibration mechanism is enabled; + false:No calibration is used */ + uint32_t rtcCalValue; /*!< Defines signed calibration value for nonsecure RTC; + This is a 5-bit 2's complement value, range from -16 to +15 */ + uint32_t periodicInterruptFreq; /*!< Defines frequency of the periodic interrupt; + Range from 0 to 15 */ +} snvs_hp_rtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SNVS driver. + * + * @param base SNVS peripheral base address + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config); + +/*! + * @brief Stops the RTC and SRTC timers. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_RTC_Deinit(SNVS_Type *base); + +/*! + * @brief Fills in the SNVS config struct with the default settings. + * + * The default values are as follows. + * @code + * config->rtccalenable = false; + * config->rtccalvalue = 0U; + * config->PIFreq = 0U; + * @endcode + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config); + +/*! @}*/ + +/*! + * @name Non secure RTC current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the SNVS RTC date and time according to the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + * + * @return kStatus_Success: Success in setting the time and starting the SNVS RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Gets the SNVS RTC time and stores it in the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + */ +void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Sets the SNVS RTC alarm time. + * + * The function sets the RTC alarm. It also checks whether the specified alarm time + * is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * + * @param base SNVS peripheral base address + * @param alarmTime Pointer to the structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the SNVS RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the SNVS RTC alarm time. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the alarm date and time details are stored. + */ +void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); + +#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) +/*! + * @brief The function synchronizes RTC counter value with SRTC. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base); +#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask); + +/*! + * @brief Disables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled SNVS interrupts. + * + * @param base SNVS peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SNVS status flags. + * + * @param base SNVS peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base); + +/*! + * @brief Clears the SNVS status flags. + * + * @param base SNVS peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the SNVS RTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_RTC_StartTimer(SNVS_Type *base) +{ + base->HPCR |= SNVS_HPCR_RTC_EN_MASK; + while (!(base->HPCR & SNVS_HPCR_RTC_EN_MASK)) + { + } +} + +/*! + * @brief Stops the SNVS RTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_RTC_StopTimer(SNVS_Type *base) +{ + base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; + while (base->HPCR & SNVS_HPCR_RTC_EN_MASK) + { + } +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SNVS_HP_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..dc41551bb3cb5db233adb8476fa6e5a7521f289b --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.c @@ -0,0 +1,1275 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* UART transfer state. */ +enum _uart_tansfer_states +{ + kUART_TxIdle, /* TX idle. */ + kUART_TxBusy, /* TX busy. */ + kUART_RxIdle, /* RX idle. */ + kUART_RxBusy, /* RX busy. */ + kUART_RxFramingError, /* Rx framing error */ + kUART_RxParityError /* Rx parity error */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the UART instance from peripheral base address. + * + * @param base UART peripheral base address. + * @return UART instance. + */ +uint32_t UART_GetInstance(UART_Type *base); + +/*! + * @brief Check whether the RX ring buffer is full. + * + * @param handle UART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @param data Start addresss of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start addresss of the data to write. + * @param length Size of the buffer to be sent. + */ +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* ARRAY of UART handle */ +#if (defined(UART8)) +#define UART_HANDLE_ARRAY_SIZE 8 +#else /* UART8 */ +#if (defined(UART7)) +#define UART_HANDLE_ARRAY_SIZE 7 +#else /* UART7 */ +#if (defined(UART6)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART6 */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART1 */ +#error No UART instance. +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ +#endif /* UART 6 */ +#endif /* UART 7 */ +#endif /* UART 8 */ +static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE]; + +/* Array of UART peripheral base address. */ +static UART_Type *const s_uartBases[] = UART_BASE_PTRS; + +/* Array of UART IRQ number. */ +static const IRQn_Type s_uartIRQ[] = UART_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UART clock name. */ +static const clock_ip_name_t s_uartClock[] = UART_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* UART ISR for transactional APIs. */ +static uart_isr_t s_uartIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t UART_GetInstance(UART_Type *base) +{ + uint32_t instance; + uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < uartArrayCount; instance++) + { + if (s_uartBases[instance] == base) + { + break; + } + } + assert(instance < uartArrayCount); + + return instance; +} + +size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) +{ + assert(handle); + + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) +{ + assert(handle); + + bool full; + + if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) +{ + /* Check argument */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable uart clock */ + CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable UART Module. */ + UART_Disable(base); + /* Reset the transmit and receive state machines, all FIFOs and register + * USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD and UTS[6-3]. */ + UART_SoftwareReset(base); + + /* Set UART Module Register content to default value */ + base->UCR1 = 0x0; + base->UCR2 = UART_UCR2_SRST_MASK; + base->UCR3 = UART_UCR3_DSR_MASK | UART_UCR3_DCD_MASK | UART_UCR3_RI_MASK; + base->UCR4 = UART_UCR4_CTSTL(32); + base->UFCR = UART_UFCR_TXTL(2) | UART_UFCR_RXTL(1); + base->UESC = UART_UESC_ESC_CHAR(0x2B); + base->UTIM = 0x0; + base->ONEMS = 0x0; + base->UTS = UART_UTS_TXEMPTY_MASK | UART_UTS_RXEMPTY_MASK; + base->UMCR = 0x0; + + /* Set UART data word length, stop bit count, parity mode and communication + * direction according to uart init struct, disable RTS hardware flow control. + */ + base->UCR2 |= + ((uint32_t)UART_UCR2_WS(config->dataBitsCount) | (uint32_t)UART_UCR2_STPB(config->stopBitCount) | + (uint32_t)(((config->parityMode) << UART_UCR2_PROE_SHIFT) & (UART_UCR2_PREN_MASK | UART_UCR2_PROE_MASK)) | + (uint32_t)UART_UCR2_TXEN(config->enableTx) | (uint32_t)UART_UCR2_RXEN(config->enableRx) | UART_UCR2_IRTS_MASK); + + /* For imx family device, UARTs are used in MUXED mode, so that this bit should always be set.*/ + if (FSL_FEATURE_IUART_RXDMUXSEL) + { + base->UCR3 |= UART_UCR3_RXDMUXSEL_MASK; + } + /* Set TX/RX fifo water mark */ + UART_SetTxFifoWatermark(base, config->txFifoWatermark); + UART_SetRxFifoWatermark(base, config->rxFifoWatermark); + + if (config->enableAutoBaudRate) + { + /* Start automatic baud rate detection */ + UART_EnableAutoBaudRate(base, true); + } + else if (config->baudRate_Bps) + { + /* Stop automatic baud rate detection */ + UART_EnableAutoBaudRate(base, false); + /* Set BaudRate according to uart initialize struct. Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)) */ + if (kStatus_Success != UART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz)) + { + return kStatus_UART_BaudrateNotSupport; + } + } + else + { + /* Stop automatic baud rate detection */ + UART_EnableAutoBaudRate(base, false); + } + + /* Enable UART module */ + UART_Enable(base); + + return kStatus_Success; +} + +void UART_Deinit(UART_Type *base) +{ + /* Wait transmit FIFO buffer and shift register empty */ + while (UART_USR2_TXDC_MASK != (base->USR2 & UART_USR2_TXDC_MASK)) + { + } + /* Disable UART Module */ + UART_Disable(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable uart clock */ + CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void UART_GetDefaultConfig(uart_config_t *config) +{ + assert(config); + + config->baudRate_Bps = 115200U; + config->parityMode = kUART_ParityDisabled; + config->dataBitsCount = kUART_EightDataBits; + config->stopBitCount = kUART_OneStopBit; + config->txFifoWatermark = 2; + config->rxFifoWatermark = 1; + config->enableAutoBaudRate = false; + config->enableTx = false; + config->enableRx = false; +} + +/* This UART instantiation uses a slightly different baud rate calculation. + * Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)). + * To get a baud rate, three register need to be writen, UFCR,UBMR and UBIR + * At first, find the approximately maximum divisor of src_Clock and baudRate_Bps. + * If the numerator and denominator are larger then register maximum value(0xFFFF), + * both of numerator and denominator will be divided by the same value, which + * will ensure numerator and denominator range from 0~maximum value(0xFFFF). + * Then calculate UFCR and UBIR value from numerator, and get UBMR value from denominator. + */ +status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t numerator = 0u; + uint32_t denominator = 0U; + uint32_t divisor = 0U; + uint32_t refFreqDiv = 0U; + uint32_t divider = 1U; + uint64_t baudDiff = 0U; + uint64_t tempNumerator = 0U; + uint32_t tempDenominator = 0u; + + /* get the approximately maximum divisor */ + numerator = srcClock_Hz; + denominator = baudRate_Bps << 4; + divisor = 1; + + while (denominator != 0) + { + divisor = denominator; + denominator = numerator % denominator; + numerator = divisor; + } + + numerator = srcClock_Hz / divisor; + denominator = (baudRate_Bps << 4) / divisor; + + /* numerator ranges from 1 ~ 7 * 64k */ + /* denominator ranges from 1 ~ 64k */ + if ((numerator > (UART_UBIR_INC_MASK * 7)) || (denominator > UART_UBIR_INC_MASK)) + { + uint32_t m = (numerator - 1) / (UART_UBIR_INC_MASK * 7) + 1; + uint32_t n = (denominator - 1) / UART_UBIR_INC_MASK + 1; + uint32_t max = m > n ? m : n; + numerator /= max; + denominator /= max; + if (0 == numerator) + { + numerator = 1; + } + if (0 == denominator) + { + denominator = 1; + } + } + divider = (numerator - 1) / UART_UBIR_INC_MASK + 1; + + switch (divider) + { + case 1: + refFreqDiv = 0x05; + break; + case 2: + refFreqDiv = 0x04; + break; + case 3: + refFreqDiv = 0x03; + break; + case 4: + refFreqDiv = 0x02; + break; + case 5: + refFreqDiv = 0x01; + break; + case 6: + refFreqDiv = 0x00; + break; + case 7: + refFreqDiv = 0x06; + break; + default: + refFreqDiv = 0x05; + break; + } + /* Compare the difference between baudRate_Bps and calculated baud rate. + * Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)). + * baudDiff = (srcClock_Hz/divider)/( 16 * ((numerator / divider)/ denominator). + */ + tempNumerator = srcClock_Hz; + tempDenominator = (numerator << 4); + divisor = 1; + /* get the approximately maximum divisor */ + while (tempDenominator != 0) + { + divisor = tempDenominator; + tempDenominator = tempNumerator % tempDenominator; + tempNumerator = divisor; + } + tempNumerator = srcClock_Hz / divisor; + tempDenominator = (numerator << 4) / divisor; + baudDiff = (tempNumerator * denominator) / tempDenominator; + baudDiff = (baudDiff >= baudRate_Bps) ? (baudDiff - baudRate_Bps) : (baudRate_Bps - baudDiff); + + if (baudDiff < (baudRate_Bps / 100) * 3) + { + base->UFCR &= ~UART_UFCR_RFDIV_MASK; + base->UFCR |= UART_UFCR_RFDIV(refFreqDiv); + base->UBIR = UART_UBIR_INC(denominator - 1); + base->UBMR = UART_UBMR_MOD(numerator / divider - 1); + base->ONEMS = UART_ONEMS_ONEMS(srcClock_Hz / (1000 * divider)); + + return kStatus_Success; + } + else + { + return kStatus_UART_BaudrateNotSupport; + } +} + +void UART_EnableInterrupts(UART_Type *base, uint32_t mask) +{ + assert(0x3F3FF73FU & mask); + + if (0X3F & mask) + { + base->UCR1 |= ((mask << UART_UCR1_ADEN_SHIFT) & UART_UCR1_ADEN_MASK) | + (((mask >> 1) << UART_UCR1_TRDYEN_SHIFT) & UART_UCR1_TRDYEN_MASK) | + (((mask >> 2) << UART_UCR1_IDEN_SHIFT) & UART_UCR1_IDEN_MASK) | + (((mask >> 3) << UART_UCR1_RRDYEN_SHIFT) & UART_UCR1_RRDYEN_MASK) | + (((mask >> 4) << UART_UCR1_TXMPTYEN_SHIFT) & UART_UCR1_TXMPTYEN_MASK) | + (((mask >> 5) << UART_UCR1_RTSDEN_SHIFT) & UART_UCR1_RTSDEN_MASK); + } + if (0X700U & mask) + { + base->UCR2 |= (((mask >> 8) << UART_UCR2_ESCI_SHIFT) & UART_UCR2_ESCI_MASK) | + (((mask >> 9) << UART_UCR2_RTSEN_SHIFT) & UART_UCR2_RTSEN_MASK) | + (((mask >> 10) << UART_UCR2_ATEN_SHIFT) & UART_UCR2_ATEN_MASK); + } + if (0x3FF000 & mask) + { + base->UCR3 |= (((mask >> 12) << UART_UCR3_DTREN_SHIFT) & UART_UCR3_DTREN_MASK) | + (((mask >> 13) << UART_UCR3_PARERREN_SHIFT) & UART_UCR3_PARERREN_MASK) | + (((mask >> 14) << UART_UCR3_FRAERREN_SHIFT) & UART_UCR3_FRAERREN_MASK) | + (((mask >> 15) << UART_UCR3_DCD_SHIFT) & UART_UCR3_DCD_MASK) | + (((mask >> 16) << UART_UCR3_RI_SHIFT) & UART_UCR3_RI_MASK) | + (((mask >> 17) << UART_UCR3_RXDSEN_SHIFT) & UART_UCR3_RXDSEN_MASK) | + (((mask >> 18) << UART_UCR3_AIRINTEN_SHIFT) & UART_UCR3_AIRINTEN_MASK) | + (((mask >> 19) << UART_UCR3_AWAKEN_SHIFT) & UART_UCR3_AWAKEN_MASK) | + (((mask >> 20) << UART_UCR3_DTRDEN_SHIFT) & UART_UCR3_DTRDEN_MASK) | + (((mask >> 21) << UART_UCR3_ACIEN_SHIFT) & UART_UCR3_ACIEN_MASK); + } + if (0x3F000000 & mask) + { + base->UCR4 |= (((mask >> 24) << UART_UCR4_ENIRI_SHIFT) & UART_UCR4_ENIRI_MASK) | + (((mask >> 25) << UART_UCR4_WKEN_SHIFT) & UART_UCR4_WKEN_MASK) | + (((mask >> 26) << UART_UCR4_TCEN_SHIFT) & UART_UCR4_TCEN_MASK) | + (((mask >> 27) << UART_UCR4_BKEN_SHIFT) & UART_UCR4_BKEN_MASK) | + (((mask >> 28) << UART_UCR4_OREN_SHIFT) & UART_UCR4_OREN_MASK) | + (((mask >> 29) << UART_UCR4_DREN_SHIFT) & UART_UCR4_DREN_MASK); + } +} + +void UART_DisableInterrupts(UART_Type *base, uint32_t mask) +{ + assert(0x3F3FF73FU & mask); + + if (0X3F & mask) + { + base->UCR1 &= ~(((mask << UART_UCR1_ADEN_SHIFT) & UART_UCR1_ADEN_MASK) | + (((mask >> 1) << UART_UCR1_TRDYEN_SHIFT) & UART_UCR1_TRDYEN_MASK) | + (((mask >> 2) << UART_UCR1_IDEN_SHIFT) & UART_UCR1_IDEN_MASK) | + (((mask >> 3) << UART_UCR1_RRDYEN_SHIFT) & UART_UCR1_RRDYEN_MASK) | + (((mask >> 4) << UART_UCR1_TXMPTYEN_SHIFT) & UART_UCR1_TXMPTYEN_MASK) | + (((mask >> 5) << UART_UCR1_RTSDEN_SHIFT) & UART_UCR1_RTSDEN_MASK)); + } + if (0X700U & mask) + { + base->UCR2 &= ~((((mask >> 8) << UART_UCR2_ESCI_SHIFT) & UART_UCR2_ESCI_MASK) | + (((mask >> 9) << UART_UCR2_RTSEN_SHIFT) & UART_UCR2_RTSEN_MASK) | + (((mask >> 10) << UART_UCR2_ATEN_SHIFT) & UART_UCR2_ATEN_MASK)); + } + if (0x3FF000 & mask) + { + base->UCR3 &= ~((((mask >> 12) << UART_UCR3_DTREN_SHIFT) & UART_UCR3_DTREN_MASK) | + (((mask >> 13) << UART_UCR3_PARERREN_SHIFT) & UART_UCR3_PARERREN_MASK) | + (((mask >> 14) << UART_UCR3_FRAERREN_SHIFT) & UART_UCR3_FRAERREN_MASK) | + (((mask >> 15) << UART_UCR3_DCD_SHIFT) & UART_UCR3_DCD_MASK) | + (((mask >> 16) << UART_UCR3_RI_SHIFT) & UART_UCR3_RI_MASK) | + (((mask >> 17) << UART_UCR3_RXDSEN_SHIFT) & UART_UCR3_RXDSEN_MASK) | + (((mask >> 18) << UART_UCR3_AIRINTEN_SHIFT) & UART_UCR3_AIRINTEN_MASK) | + (((mask >> 19) << UART_UCR3_AWAKEN_SHIFT) & UART_UCR3_AWAKEN_MASK) | + (((mask >> 20) << UART_UCR3_DTRDEN_SHIFT) & UART_UCR3_DTRDEN_MASK) | + (((mask >> 21) << UART_UCR3_ACIEN_SHIFT) & UART_UCR3_ACIEN_MASK)); + } + if (0x3F000000 & mask) + { + base->UCR4 &= ~((((mask >> 24) << UART_UCR4_ENIRI_SHIFT) & UART_UCR4_ENIRI_MASK) | + (((mask >> 25) << UART_UCR4_WKEN_SHIFT) & UART_UCR4_WKEN_MASK) | + (((mask >> 26) << UART_UCR4_TCEN_SHIFT) & UART_UCR4_TCEN_MASK) | + (((mask >> 27) << UART_UCR4_BKEN_SHIFT) & UART_UCR4_BKEN_MASK) | + (((mask >> 28) << UART_UCR4_OREN_SHIFT) & UART_UCR4_OREN_MASK) | + (((mask >> 29) << UART_UCR4_DREN_SHIFT) & UART_UCR4_DREN_MASK)); + } +} + +uint32_t UART_GetEnabledInterrupts(UART_Type *base) +{ + assert(base); + uint32_t temp = 0U; + /* Get enabled interrupts from UCR1 */ + temp |= ((base->UCR1 & UART_UCR1_ADEN_MASK) >> UART_UCR1_ADEN_SHIFT) | + (((base->UCR1 & UART_UCR1_TRDYEN_MASK) >> UART_UCR1_TRDYEN_SHIFT) << 1) | + (((base->UCR1 & UART_UCR1_IDEN_MASK) >> UART_UCR1_IDEN_SHIFT) << 2) | + (((base->UCR1 & UART_UCR1_RRDYEN_MASK) >> UART_UCR1_RRDYEN_SHIFT) << 3) | + (((base->UCR1 & UART_UCR1_TXMPTYEN_MASK) >> UART_UCR1_TXMPTYEN_SHIFT) << 4) | + (((base->UCR1 & UART_UCR1_RTSDEN_MASK) >> UART_UCR1_RTSDEN_SHIFT) << 5); + /* Get enabled interrupts from UCR2 */ + temp |= (((base->UCR2 & UART_UCR2_ESCI_MASK) >> UART_UCR2_ESCI_SHIFT) << 8) | + (((base->UCR2 & UART_UCR2_RTSEN_MASK) >> UART_UCR2_RTSEN_SHIFT) << 9) | + (((base->UCR2 & UART_UCR2_ATEN_MASK) >> UART_UCR2_ATEN_SHIFT) << 10); + /* Get enabled interrupts from UCR3 */ + temp |= (((base->UCR3 & UART_UCR3_DTREN_MASK) >> UART_UCR3_DTREN_SHIFT) << 12) | + (((base->UCR3 & UART_UCR3_PARERREN_MASK) >> UART_UCR3_PARERREN_SHIFT) << 13) | + (((base->UCR3 & UART_UCR3_FRAERREN_MASK) >> UART_UCR3_FRAERREN_SHIFT) << 14) | + (((base->UCR3 & UART_UCR3_DCD_MASK) >> UART_UCR3_DCD_SHIFT) << 15) | + (((base->UCR3 & UART_UCR3_RI_MASK) >> UART_UCR3_RI_SHIFT) << 16) | + (((base->UCR3 & UART_UCR3_RXDSEN_MASK) >> UART_UCR3_RXDSEN_SHIFT) << 17) | + (((base->UCR3 & UART_UCR3_AIRINTEN_MASK) >> UART_UCR3_AIRINTEN_SHIFT) << 18) | + (((base->UCR3 & UART_UCR3_AWAKEN_MASK) >> UART_UCR3_AWAKEN_SHIFT) << 19) | + (((base->UCR3 & UART_UCR3_DTRDEN_MASK) >> UART_UCR3_DTRDEN_SHIFT) << 20) | + (((base->UCR3 & UART_UCR3_ACIEN_MASK) >> UART_UCR3_ACIEN_SHIFT) << 21); + /* Get enabled interrupts from UCR4 */ + temp |= (((base->UCR4 & UART_UCR4_ENIRI_MASK) >> UART_UCR4_ENIRI_SHIFT) << 24) | + (((base->UCR4 & UART_UCR4_WKEN_MASK) >> UART_UCR4_WKEN_SHIFT) << 25) | + (((base->UCR4 & UART_UCR4_TCEN_MASK) >> UART_UCR4_TCEN_SHIFT) << 26) | + (((base->UCR4 & UART_UCR4_BKEN_MASK) >> UART_UCR4_BKEN_SHIFT) << 27) | + (((base->UCR4 & UART_UCR4_OREN_MASK) >> UART_UCR4_OREN_SHIFT) << 28) | + (((base->UCR4 & UART_UCR4_DREN_MASK) >> UART_UCR4_DREN_SHIFT) << 29); + + return temp; +} + +bool UART_GetStatusFlag(UART_Type *base, uint32_t flag) +{ + volatile uint32_t *uart_reg; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + return (bool)(((*uart_reg) >> (flag & 0x1FU)) & 0x1U); +} + +void UART_ClearStatusFlag(UART_Type *base, uint32_t flag) +{ + volatile uint32_t *uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + uart_mask = (1U << (flag & 0x1FU)); + + *uart_reg = uart_mask; +} + +void UART_EnableDMA(UART_Type *base, uint32_t dmaSource, bool enable) +{ + volatile uint32_t *uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (dmaSource >> 16)); + uart_mask = (1U << (dmaSource & 0x1FU)); + if (enable) + { + *uart_reg |= uart_mask; + } + else + { + *uart_reg &= ~uart_mask; + } +} + +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + assert(data); + + while (length--) + { + /* Wait for TX fifo valid. + * This API can only ensure that the data is written into the data buffer but can't + * ensure all data in the data buffer are sent into the transmit shift buffer. + */ + while (!(base->USR2 & UART_USR2_TXDC_MASK)) + { + } + UART_WriteByte(base, *(data++)); + } +} + +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + assert(data); + + while (length--) + { + /* Wait for receive data in URXD register is ready */ + while (!(base->USR2 & UART_USR2_RDR_MASK)) + { + /* Parity error check for receiving character */ + if (base->USR1 & UART_USR1_PARITYERR_MASK) + { + UART_ClearStatusFlag(base, kUART_ParityErrorFlag); + return kStatus_UART_ParityError; + } + /* Framing error check for receiving character */ + if (base->USR1 & UART_USR1_FRAMERR_MASK) + { + UART_ClearStatusFlag(base, kUART_FrameErrorFlag); + return kStatus_UART_FramingError; + } + /* Over run check for receiving character */ + if (base->USR2 & UART_USR2_ORE_MASK) + { + UART_ClearStatusFlag(base, kUART_RxOverrunFlag); + return kStatus_UART_RxHardwareOverrun; + } + } + /* Read data from URXD */ + *(data++) = UART_ReadByte(base); + } + + return kStatus_Success; +} + +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + assert(data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + * peripheral to write. UTXD register holds the parallel transmit data inputs. In 7-bit mode, + * D7 is ignored. In 8-bit mode, all bits are used. + */ + for (i = 0; i < length; i++) + { + base->UTXD = data[i] & UART_UTXD_TX_DATA_MASK; + } +} + +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + assert(data); + + size_t i; + + /* The Non Blocking read data API assume user have ensured there is enough space in + * peripheral to write. The URXD holds the received character,In 7-bit mode, + * the most significant bit (MSB) is forced to 0.In 8-bit mode, all bits are active. + */ + for (i = 0; i < length; i++) + { + data[i] = (uint8_t)((base->URXD & UART_URXD_RX_DATA_MASK) >> UART_URXD_RX_DATA_SHIFT); + } +} + +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Get instance from peripheral base address. */ + instance = UART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_uartHandle[instance - 1] = handle; + + s_uartIsr = UART_TransferHandleIRQ; + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_uartIRQ[instance]); +} + +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + assert(handle); + assert(ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + UART_EnableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); +} + +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kUART_RxIdle) + { + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + assert(xfer->dataSize); + assert(xfer->data); + + status_t status; + + /* Return error if current TX busy. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUART_TxBusy; + + /* Enable transmiter interrupt. */ + UART_EnableInterrupts(base, kUART_TxReadyEnable); + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + UART_DisableInterrupts(base, kUART_TxEmptyEnable); + + handle->txDataSize = 0; + handle->txState = kUART_TxIdle; +} + +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(count); + + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(handle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable UART RX IRQ, protect ring buffer. */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + } + + /* Enable UART RX IRQ if previously enabled. */ + UART_EnableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + + /* Enable RX/Rx overrun/framing error interrupt. */ + UART_EnableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(count); + + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + uint8_t count; + uint8_t tempCount; + + /* If RX framing error */ + if (UART_USR1_FRAMERR_MASK & base->USR1) + { + /* Write 1 to clear framing error flag */ + base->USR1 |= UART_USR1_FRAMERR_MASK; + + handle->rxState = kUART_RxFramingError; + handle->rxDataSize = 0U; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_FramingError, handle->userData); + } + } + + /* If RX parity error */ + if (UART_USR1_PARITYERR_MASK & base->USR1) + { + /* Write 1 to clear parity error flag. */ + base->USR1 |= UART_USR1_PARITYERR_MASK; + + handle->rxState = kUART_RxParityError; + handle->rxDataSize = 0U; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_ParityError, handle->userData); + } + } + + /* If RX overrun. */ + if (UART_USR2_ORE_MASK & base->USR2) + { + /* Write 1 to clear overrun flag. */ + base->USR2 |= UART_USR2_ORE_MASK; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data FIFO buffer reach the trigger level */ + if (((UART_USR1_RRDY_MASK)&base->USR1) && (UART_UCR1_RRDYEN_MASK & base->UCR1)) + { + /* Get the size that stored in receive FIFO buffer for this interrupt. */ + count = ((base->UFCR & UART_UFCR_RXTL_MASK) >> UART_UFCR_RXTL_SHIFT); + + /* If count and handle->rxDataSize are not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { + tempCount = MIN(handle->rxDataSize, count); + /* Using non block API to read the data from the registers. */ + UART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = + (uint8_t)((base->URXD & UART_URXD_RX_DATA_MASK) >> UART_URXD_RX_DATA_SHIFT); + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + + else if (!handle->rxDataSize) + { + /* Disable RX interrupt/overrun interrupt/framing error interrupt */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + else + { + } + } + /* Receive FIFO buffer has been idle for a time of 8 characters, and FIFO data level + * is less than RxFIFO threshold level. + */ + if (((UART_USR1_AGTIM_MASK)&base->USR1) && (UART_UCR2_ATEN_MASK & base->UCR2)) + { + /* If count and handle->rxDataSize are not 0, first save data to handle->rxData. */ + while ((base->USR2 & UART_USR2_RDR_MASK) && (handle->rxDataSize)) + { + /* Read one data from the URXD registers. */ + *handle->rxData = UART_ReadByte(base); + handle->rxData += 1; + handle->rxDataSize -= 1; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (base->USR2 & UART_USR2_RDR_MASK) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read one data from URXD register. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = UART_ReadByte(base); + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If ring buffer is not used and rxDataSize is 0 */ + else if (!handle->rxDataSize) + { + /* Disable RX interrupt/overrun interrupt/framing error interrupt */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + else + { + } + /* Clear aging timer flag for next interrupt */ + UART_ClearStatusFlag(base, kUART_AgingTimerFlag); + } + /* If frame error or parity error happened, stop the RX interrupt when ues no ring buffer */ + if (((handle->rxState == kUART_RxFramingError) || (handle->rxState == kUART_RxParityError)) && + (!handle->rxRingBuffer)) + { + /* Disable Receive ready interrupt, aging timer interrupt, receive over run interrupt, + * parity error interrupt and frame error interrupt. + */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + + /* Send data register empty and the interrupt is enabled. */ + if ((UART_USR1_TRDY_MASK & base->USR1) && (UART_UCR1_TRDYEN_MASK & base->UCR1)) + { + /* Get the bytes that available at this moment. */ + if (0U != ((base->UFCR & UART_UFCR_TXTL_MASK) >> UART_UFCR_TXTL_SHIFT)) + { + if (UART_UTS_TXEMPTY_MASK & (base->UTS)) + { + count = FSL_FEATURE_IUART_FIFO_SIZEn(base); + } + else + { + count = + FSL_FEATURE_IUART_FIFO_SIZEn(base) - ((base->UFCR & UART_UFCR_TXTL_MASK) >> UART_UFCR_TXTL_SHIFT); + } + } + else + { + count = 1; + } + + while ((count) && (handle->txDataSize)) + { + if (0U != ((base->UFCR & UART_UFCR_TXTL_MASK) >> UART_UFCR_TXTL_SHIFT)) + { + tempCount = MIN(handle->txDataSize, count); + } + else + { + tempCount = 1; + } + /* Using non block API to write the data to the registers. */ + UART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kUART_TxIdle; + /* Disable TX FIFO buffer empty interrupt. */ + UART_DisableInterrupts(base, kUART_TxReadyEnable); + /* Trigger callback. + * Note: This callback is called when all data have been send to TX FIFO, + * but this not mean transmit has completed, some data may still in + * FIFO buffer. + */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData); + } + } + } + } +} + +#if defined(UART1) +void UART1_DriverIRQHandler(void) +{ + s_uartIsr(UART1, s_uartHandle[0]); +} +#endif + +#if defined(UART2) +void UART2_DriverIRQHandler(void) +{ + s_uartIsr(UART2, s_uartHandle[1]); +} +#endif + +#if defined(UART3) +void UART3_DriverIRQHandler(void) +{ + s_uartIsr(UART3, s_uartHandle[2]); +} +#endif + +#if defined(UART4) +void UART4_DriverIRQHandler(void) +{ + s_uartIsr(UART4, s_uartHandle[3]); +} +#endif + +#if defined(UART5) +void UART5_DriverIRQHandler(void) +{ + s_uartIsr(UART5, s_uartHandle[4]); +} +#endif + +#if defined(UART6) +void UART6_DriverIRQHandler(void) +{ + s_uartIsr(UART6, s_uartHandle[5]); +} +#endif + +#if defined(UART7) +void UART7_DriverIRQHandler(void) +{ + s_uartIsr(UART7, s_uartHandle[6]); +} +#endif + +#if defined(UART8) +void UART8_DriverIRQHandler(void) +{ + s_uartIsr(UART8, s_uartHandle[7]); +} +#endif diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..0dd8ed82000ce144020be6aa4206f7b0724053b5 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.h @@ -0,0 +1,870 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_UART_H_ +#define _FSL_UART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup uart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief UART driver version 2.0.0. */ +#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Error codes for the UART driver. */ +enum _uart_status +{ + kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_IUART, 0), /*!< Transmitter is busy. */ + kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_IUART, 1), /*!< Receiver is busy. */ + kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_IUART, 2), /*!< UART transmitter is idle. */ + kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_IUART, 3), /*!< UART receiver is idle. */ + kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_IUART, 4), /*!< TX FIFO watermark too large */ + kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_IUART, 5), /*!< RX FIFO watermark too large */ + kStatus_UART_FlagCannotClearManually = + MAKE_STATUS(kStatusGroup_IUART, 6), /*!< UART flag can't be manually cleared. */ + kStatus_UART_Error = MAKE_STATUS(kStatusGroup_IUART, 7), /*!< Error happens on UART. */ + kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_IUART, 8), /*!< UART RX software ring buffer overrun. */ + kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_IUART, 9), /*!< UART RX receiver overrun. */ + kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_IUART, 10), /*!< UART noise error. */ + kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_IUART, 11), /*!< UART framing error. */ + kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_IUART, 12), /*!< UART parity error. */ + kStatus_UART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_IUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_UART_BreakDetect = MAKE_STATUS(kStatusGroup_IUART, 14), /*!< Receiver detect BREAK signal */ +}; + +/*! @brief UART data bits count. */ +typedef enum _uart_data_bits +{ + kUART_SevenDataBits = 0x0U, /*!< Seven data bit */ + kUART_EightDataBits = 0x1U, /*!< Eight data bit */ +} uart_data_bits_t; + +/*! @brief UART parity mode. */ +typedef enum _uart_parity_mode +{ + kUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUART_ParityEven = 0x2U, /*!< Even error check is selected */ + kUART_ParityOdd = 0x3U, /*!< Odd error check is selected */ +} uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _uart_stop_bit_count +{ + kUART_OneStopBit = 0x0U, /*!< One stop bit */ + kUART_TwoStopBit = 0x1U, /*!< Two stop bits */ +} uart_stop_bit_count_t; + +/*! @brief This structure contains the settings for all of the UART interrupt configurations. */ +enum _uart_interrupt_enable +{ + kUART_AutoBaudEnable = 0x1U, /* !< Automatic baud rate detection Interrupt Enable. */ + kUART_TxReadyEnable = (0X1U << 1), /* !< transmitter ready Interrupt Enable. */ + kUART_IdleEnable = (0x1U << 2), /* !< IDLE Interrupt Enable. */ + kUART_RxReadyEnable = (0x1U << 3), /* !< Receiver Ready Interrupt Enable. */ + kUART_TxEmptyEnable = (0x1U << 4), /* !< Transmitter Empty Interrupt Enable. */ + kUART_RtsDeltaEnable = (0x1U << 5), /* !< RTS Delta Interrupt Enable. */ + kUART_EscapeEnable = (0x1U << 8), /* !< Escape Sequence Interrupt Enable. */ + kUART_RtsEnable = (0x1U << 9), /* !< Request to Send Interrupt Enable. */ + kUART_AgingTimerEnable = (0x1U << 10), /* !< Aging Timer Interrupt Enable. */ + kUART_DtrEnable = (0x1U << 12), /* !< Data Terminal Ready Interrupt Enable. */ + kUART_ParityErrorEnable = (0x1U << 13), /* !< Parity Error Interrupt Enable. */ + kUART_FrameErrorEnable = (0x1U << 14), /* !< Frame Error Interrupt Enable. */ + kUART_DcdEnable = (0x1U << 15), /* !< Data Carrier Detect Interrupt Enable. */ + kUART_RiEnable = (0x1U << 16), /* !< Ring Indicator Interrupt Enable. */ + kUART_RxDsEnable = (0x1U << 17), /* !< Receive Status Interrupt Enable. */ + kUART_tAirWakeEnable = (0x1U << 18), /* !< Asynchronous IR WAKE Interrupt Enable. */ + kUART_AwakeEnable = (0x1U << 19), /* !< Asynchronous WAKE Interrupt Enable. */ + kUART_DtrDeltaEnable = (0x1U << 20), /* !< Data Terminal Ready Delta Interrupt Enable. */ + kUART_AutoBaudCntEnable = (0x1U << 21), /* !< Auto-baud Counter Interrupt Enable. */ + kUART_IrEnable = (0X1U << 24), /* !< Serial Infrared Interrupt Enable. */ + kUART_WakeEnable = (0X1U << 25), /* !< WAKE Interrupt Enable. */ + kUART_TxCompleteEnable = (0X1U << 26), /* !< TransmitComplete Interrupt Enable. */ + kUART_BreakDetectEnable = (0X1U << 27), /* !< BREAK Condition Detected Interrupt Enable. */ + kUART_RxOverrunEnable = (0X1U << 28), /* !< Receiver Overrun Interrupt Enable. */ + kUART_RxDataReadyEnable = (0X1U << 29), /* !< Receive Data Ready Interrupt Enable. */ + kUART_AllInterruptsEnable = kUART_AutoBaudEnable | kUART_TxReadyEnable | kUART_IdleEnable | kUART_RxReadyEnable | + kUART_TxEmptyEnable | kUART_RtsDeltaEnable | kUART_EscapeEnable | kUART_RtsEnable | + kUART_AgingTimerEnable | kUART_DtrEnable | kUART_ParityErrorEnable | + kUART_FrameErrorEnable | kUART_DcdEnable | kUART_RiEnable | kUART_RxDsEnable | + kUART_tAirWakeEnable | kUART_AwakeEnable | kUART_DtrDeltaEnable | + kUART_AutoBaudCntEnable | kUART_IrEnable | kUART_WakeEnable | kUART_TxCompleteEnable | + kUART_BreakDetectEnable | kUART_RxOverrunEnable | kUART_RxDataReadyEnable, +}; + +/*! + * @brief UART status flags. + * + * This provides constants for the UART status flags for use in the UART functions. + */ +enum _uart_flags +{ + kUART_RxCharReadyFlag = 0x0000000FU, /*!< Rx Character Ready Flag. */ + kUART_RxErrorFlag = 0x0000000EU, /*!< Rx Error Detect Flag. */ + kUART_RxOverrunErrorFlag = 0x0000000DU, /*!< Rx Overrun Flag. */ + kUART_RxFrameErrorFlag = 0x0000000CU, /*!< Rx Frame Error Flag. */ + kUART_RxBreakDetectFlag = 0x0000000BU, /*!< Rx Break Detect Flag. */ + kUART_RxParityErrorFlag = 0x0000000AU, /*!< Rx Parity Error Flag. */ + kUART_ParityErrorFlag = 0x0094000FU, /*!< Parity Error Interrupt Flag. */ + kUART_RtsStatusFlag = 0x0094000EU, /*!< RTS_B Pin Status Flag. */ + kUART_TxReadyFlag = 0x0094000DU, /*!< Transmitter Ready Interrupt/DMA Flag. */ + kUART_RtsDeltaFlag = 0x0094000CU, /*!< RTS Delta Flag. */ + kUART_EscapeFlag = 0x0094000BU, /*!< Escape Sequence Interrupt Flag. */ + kUART_FrameErrorFlag = 0x0094000AU, /*!< Frame Error Interrupt Flag. */ + kUART_RxReadyFlag = 0x00940009U, /*!< Receiver Ready Interrupt/DMA Flag. */ + kUART_AgingTimerFlag = 0x00940008U, /*!< Aging Timer Interrupt Flag. */ + kUART_DtrDeltaFlag = 0x00940007U, /*!< DTR Delta Flag. */ + kUART_RxDsFlag = 0x00940006U, /*!< Receiver IDLE Interrupt Flag. */ + kUART_tAirWakeFlag = 0x00940005U, /*!< Asynchronous IR WAKE Interrupt Flag. */ + kUART_AwakeFlag = 0x00940004U, /*!< Asynchronous WAKE Interrupt Flag. */ + kUART_Rs485SlaveAddrMatchFlag = 0x00940003U, /*!< RS-485 Slave Address Detected Interrupt Flag. */ + kUART_AutoBaudFlag = 0x0098000FU, /*!< Automatic Baud Rate Detect Complete Flag. */ + kUART_TxEmptyFlag = 0x0098000EU, /*!< Transmit Buffer FIFO Empty. */ + kUART_DtrFlag = 0x0098000DU, /*!< DTR edge triggered interrupt flag. */ + kUART_IdleFlag = 0x0098000CU, /*!< Idle Condition Flag. */ + kUART_AutoBaudCntStopFlag = 0x0098000BU, /*!< Auto-baud Counter Stopped Flag. */ + kUART_RiDeltaFlag = 0x0098000AU, /*!< Ring Indicator Delta Flag. */ + kUART_RiFlag = 0x00980009U, /*!< Ring Indicator Input Flag. */ + kUART_IrFlag = 0x00980008U, /*!< Serial Infrared Interrupt Flag. */ + kUART_WakeFlag = 0x00980007U, /*!< Wake Flag. */ + kUART_DcdDeltaFlag = 0x00980006U, /*!< Data Carrier Detect Delta Flag. */ + kUART_DcdFlag = 0x00980005U, /*!< Data Carrier Detect Input Flag. */ + kUART_RtsFlag = 0x00980004U, /*!< RTS Edge Triggered Interrupt Flag. */ + kUART_TxCompleteFlag = 0x00980003U, /*!< Transmitter Complete Flag. */ + kUART_BreakDetectFlag = 0x00980002U, /*!< BREAK Condition Detected Flag. */ + kUART_RxOverrunFlag = 0x00980001U, /*!< Overrun Error Flag. */ + kUART_RxDataReadyFlag = 0x00980000U, /*!< Receive Data Ready Flag. */ +}; + +/*! @brief UART configuration structure. */ +typedef struct _uart_config +{ + uint32_t baudRate_Bps; /*!< UART baud rate. */ + uart_parity_mode_t parityMode; /*!< Parity error check mode of this module. */ + uart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits in one frame. */ + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ + bool enableAutoBaudRate; /*!< Enable automatic baud rate detection */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} uart_config_t; + +/*! @brief UART transfer structure. */ +typedef struct _uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_handle uart_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); + +/*! @brief UART handle structure. */ +struct _uart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the UART using software. + * + * This function resets the transmit and receive state machines, all FIFOs and register + * USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3] + * + * @param base UART peripheral base address. + */ +static inline void UART_SoftwareReset(UART_Type *base) +{ + base->UCR2 &= ~UART_UCR2_SRST_MASK; + while ((base->UCR2 & UART_UCR2_SRST_MASK) == 0) + { + } +} + +/* @} */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an UART instance with the user configuration structure and the peripheral clock. + * + * This function configures the UART module with user-defined settings. Call the UART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the UART. + * @code + * uart_config_t uartConfig; + * uartConfig.baudRate_Bps = 115200U; + * uartConfig.parityMode = kUART_ParityDisabled; + * uartConfig.dataBitsCount = kUART_EightDataBits; + * uartConfig.stopBitCount = kUART_OneStopBit; + * uartConfig.txFifoWatermark = 2; + * uartConfig.rxFifoWatermark = 1; + * uartConfig.enableAutoBaudrate = false; + * uartConfig.enableTx = true; + * uartConfig.enableRx = true; + * UART_Init(UART1, &uartConfig, 24000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz UART clock source frequency in HZ. + * @retval kStatus_Success UART initialize succeed + */ +status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the UART clock. + * + * @param base UART peripheral base address. + */ +void UART_Deinit(UART_Type *base); + +/*!l + * @brief Gets the default configuration structure. + * + * This function initializes the UART configuration structure to a default value. The default + * values are: + * uartConfig->baudRate_Bps = 115200U; + * uartConfig->parityMode = kUART_ParityDisabled; + * uartConfig->dataBitsCount = kUART_EightDataBits; + * uartConfig->stopBitCount = kUART_OneStopBit; + * uartConfig->txFifoWatermark = 2; + * uartConfig->rxFifoWatermark = 1; + * uartConfig->enableAutoBaudrate = flase; + * uartConfig->enableTx = false; + * uartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void UART_GetDefaultConfig(uart_config_t *config); + +/*! + * @brief Sets the UART instance baud rate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the UART_Init. + * @code + * UART_SetBaudRate(UART1, 115200U, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param baudRate_Bps UART baudrate to be set. + * @param srcClock_Hz UART clock source freqency in Hz. + * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); +/*! + * @brief This function is used to Enable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Enable(UART_Type *base) +{ + base->UCR1 |= UART_UCR1_UARTEN_MASK; +} + +/*! + * @brief This function is used to Disable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Disable(UART_Type *base) +{ + base->UCR1 &= ~UART_UCR1_UARTEN_MASK; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief This function is used to get the current status of specific + * UART status flag(including interrupt flag). The available + * status flag can be select from @ref uart_status_flag_t enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to check. + * @retval current state of corresponding status flag. + */ +bool UART_GetStatusFlag(UART_Type *base, uint32_t flag); + +/*! + * @brief This function is used to clear the current status + * of specific UART status flag. The available status + * flag can be select from @ref uart_status_flag_t enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to clear. + */ +void UART_ClearStatusFlag(UART_Type *base, uint32_t flag); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables UART interrupts according to the provided mask. + * + * This function enables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to enable TX empty interrupt and RX data ready interrupt, do the following. + * @code + * UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_EnableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the UART interrupts according to the provided mask. + * + * This function disables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to disable TX empty interrupt and RX data ready interrupt do the following. + * @code + * UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_DisableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled UART interrupts. + * + * This function gets the enabled UART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _uart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); + * + * if (kUART_TxEmptyEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable. + */ +uint32_t UART_GetEnabledInterrupts(UART_Type *base); + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter. + * + * This function enables or disables the UART transmitter. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTx(UART_Type *base, bool enable) +{ + if (enable) + { + base->UCR2 |= UART_UCR2_TXEN_MASK; + } + else + { + base->UCR2 &= ~UART_UCR2_TXEN_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver. + * + * This function enables or disables the UART receiver. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRx(UART_Type *base, bool enable) +{ + if (enable) + { + base->UCR2 |= UART_UCR2_RXEN_MASK; + } + else + { + base->UCR2 &= ~UART_UCR2_RXEN_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function is used to write data to transmitter register. + * The upper layer must ensure that the TX register is empty or that + * the TX FIFO has room before calling this function. + * + * @param base UART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void UART_WriteByte(UART_Type *base, uint8_t data) +{ + base->UTXD = data & UART_UTXD_TX_DATA_MASK; +} + +/*! + * @brief Reads the receiver register. + * + * This function is used to read data from receiver register. + * The upper layer must ensure that the receiver register is full or that + * the RX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t UART_ReadByte(UART_Type *base) +{ + return (uint8_t)((base->URXD & UART_URXD_RX_DATA_MASK) >> UART_URXD_RX_DATA_SHIFT); +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note This function does not check whether all data is sent out to the bus. + * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the TX register. + * + * @param base UART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data. + * @retval kStatus_UART_NoiseError A noise error occurred while receiving data. + * @retval kStatus_UART_FramingError A framing error occurred while receiving data. + * @retval kStatus_UART_ParityError A parity error occurred while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the UART handle which can be used for other UART + * transactional APIs. Usually, for a specified UART instance, + * call this API once to get the initialized handle. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize Size of the ring buffer. + */ +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle UART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX, + * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure. See #uart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument The parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the UART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure, see #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_UART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle); + +/*@}*/ + +/*! + * @name DMA control functions. + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter DMA request. + * + * This function enables or disables the transmit request when the transmitter + * has one or more slots available in the TxFIFO. The fill level in the TxFIFO + * that generates the DMA request is controlled by the TXTL bits. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTxDMA(UART_Type *base, bool enable) +{ + assert(base); + + if (enable) + { + base->UCR1 |= UART_UCR1_TXDMAEN_MASK; + } + else + { + base->UCR1 &= ~UART_UCR1_TXDMAEN_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver DMA request. + * + * This function enables or disables the receive request when the receiver + * has data in the RxFIFO. The fill level in the RxFIFO at which a DMA request + * is generated is controlled by the RXTL bits . + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRxDMA(UART_Type *base, bool enable) +{ + assert(base); + + if (enable) + { + base->UCR1 |= UART_UCR1_RXDMAEN_MASK; + } + else + { + base->UCR1 &= ~UART_UCR1_RXDMAEN_MASK; + } +} + +/*@}*/ + +/*! + * @name FIFO control functions. + * @{ + */ + +/*! + * @brief This function is used to set the watermark of UART Tx FIFO. + * A maskable interrupt is generated whenever the data level in + * the TxFIFO falls below the Tx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Tx FIFO watermark. + */ +static inline void UART_SetTxFifoWatermark(UART_Type *base, uint8_t watermark) +{ + assert((watermark >= 2) && (watermark <= FSL_FEATURE_IUART_FIFO_SIZEn(base))); + base->UFCR = (base->UFCR & ~UART_UFCR_TXTL_MASK) | UART_UFCR_TXTL(watermark); +} + +/*! + * @brief This function is used to set the watermark of UART Rx FIFO. + * A maskable interrupt is generated whenever the data level in + * the RxFIFO reaches the Rx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Rx FIFO watermark. + */ +static inline void UART_SetRxFifoWatermark(UART_Type *base, uint8_t watermark) +{ + assert(watermark <= FSL_FEATURE_IUART_FIFO_SIZEn(base)); + base->UFCR = (base->UFCR & ~UART_UFCR_RXTL_MASK) | UART_UFCR_RXTL(watermark); +} + +/*@}*/ + +/*! + * @name Auto baud rate detection. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * Automatic Baud Rate Detection feature. + * + * @param base UART base pointer. + * @param enable Enable/Disable Automatic Baud Rate Detection feature. + * - true: Enable Automatic Baud Rate Detection feature. + * - false: Disable Automatic Baud Rate Detection feature. + */ +static inline void UART_EnableAutoBaudRate(UART_Type *base, bool enable) +{ + if (enable) + { + /* When ADET=0 and ADBR=1, automatic baud rate detection starts */ + /* Enable automatic baud rate detection */ + base->UCR1 |= UART_UCR1_ADBR_MASK; + /* Clear ADET brfore start automatic baud rate detection*/ + base->USR2 |= UART_USR2_ADET_MASK; + } + else + { + /* Disable automatic baud rate detection */ + base->UCR1 &= ~UART_UCR1_ADBR_MASK; + } +} +/*! + * @brief This function is used to read if the automatic baud rate detection + * has finished. + * + * @param base UART base pointer. + * @return - true: Automatic baud rate detection has finished. + * - false: Automatic baud rate detection has not finished. + */ +static inline bool UART_IsAutoBaudRateComplete(UART_Type *base) +{ + if (UART_USR2_ACST_MASK & base->USR2) + { + base->USR2 |= UART_USR2_ACST_MASK; + return true; + } + else + { + return false; + } +} + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.c new file mode 100644 index 0000000000000000000000000000000000000000..35e37e7cb3797592939b90154444a1b9fbaef52e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.c @@ -0,0 +1,1654 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_usdhc.h" +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#include "fsl_cache.h" +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + +#ifdef RT_USING_USERSPACE +#include "imx6ull.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock setting */ +/* Max SD clock divisor from base clock */ +#define USDHC_MAX_DVS ((USDHC_SYS_CTRL_DVS_MASK >> USDHC_SYS_CTRL_DVS_SHIFT) + 1U) +#define USDHC_PREV_DVS(x) ((x) -= 1U) +#define USDHC_PREV_CLKFS(x, y) ((x) >>= (y)) + +/* Typedef for interrupt handler. */ +typedef void (*usdhc_isr_t)(USDHC_Type *base, usdhc_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base USDHC peripheral base address. + * @return Instance number. + */ +static uint32_t USDHC_GetInstance(USDHC_Type *base); + +/*! + * @brief Set transfer interrupt. + * + * @param base USDHC peripheral base address. + * @param usingInterruptSignal True to use IRQ signal. + */ +static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal); + +/*! + * @brief Start transfer according to current transfer state + * + * @param base USDHC peripheral base address. + * @param command Command to be sent. + * @param data Data to be transferred. + */ +static status_t USDHC_SetTransferConfig(USDHC_Type *base, usdhc_command_t *command, usdhc_data_t *data); + +/*! + * @brief Receive command response + * + * @param base USDHC peripheral base address. + * @param command Command to be sent. + */ +static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command); + +/*! + * @brief Read DATAPORT when buffer enable bit is set. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time transaction. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Read data by using DATAPORT polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @retval kStatus_Fail Read DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); + +/*! + * @brief Write DATAPORT when buffer enable bit is set. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Write data by using DATAPORT polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Write DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); + +/*! + * @brief Transfer data by polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @param use DMA flag. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA); + +/*! + * @brief Handle card detect interrupt. + * + * @param handle USDHC handle. + * @param interruptFlags Card detect related interrupt flags. + */ +static void USDHC_TransferHandleCardDetect(usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle command interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Command related interrupt flags. + */ +static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle data interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Data related interrupt flags. + */ +static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle SDIO card interrupt signal. + * + * @param handle USDHC handle. + */ +static void USDHC_TransferHandleSdioInterrupt(usdhc_handle_t *handle); + +/*! + * @brief Handle SDIO block gap event. + * + * @param handle USDHC handle. + */ +static void USDHC_TransferHandleSdioBlockGap(usdhc_handle_t *handle); + +/*! +* @brief Handle retuning +* +* @param interrupt flags +*/ +static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! +* @brief wait command done +* +* @param base USDHC peripheral base address. +* @param command configuration +* @param execute tuning flag +*/ +static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool executeTuning); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief USDHC base pointer array */ +static USDHC_Type *const s_usdhcBase[] = USDHC_BASE_PTRS; + +/*! @brief USDHC internal handle pointer array */ +static usdhc_handle_t *s_usdhcHandle[ARRAY_SIZE(s_usdhcBase)] = {NULL}; + +/*! @brief USDHC IRQ name array */ +static const IRQn_Type s_usdhcIRQ[] = USDHC_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief USDHC clock array name */ +static const clock_ip_name_t s_usdhcClock[] = USDHC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* USDHC ISR for transactional APIs. */ +static usdhc_isr_t s_usdhcIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t USDHC_GetInstance(USDHC_Type *base) +{ + uint8_t instance = 0; + +#ifdef RT_USING_USERSPACE + while ((instance < ARRAY_SIZE(s_usdhcBase)) && (s_usdhcBase[instance] != rt_hw_kernel_virt_to_phys(base))) +#else + while ((instance < ARRAY_SIZE(s_usdhcBase)) && (s_usdhcBase[instance] != base)) +#endif + { + instance++; + } + + assert(instance < ARRAY_SIZE(s_usdhcBase)); + + return instance; +} + +static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal) +{ + uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */ + + /* Disable all interrupts */ + USDHC_DisableInterruptStatus(base, (uint32_t)kUSDHC_AllInterruptFlags); + USDHC_DisableInterruptSignal(base, (uint32_t)kUSDHC_AllInterruptFlags); + DisableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); + + interruptEnabled = (kUSDHC_CommandFlag | kUSDHC_CardInsertionFlag | kUSDHC_DataFlag | kUSDHC_CardRemovalFlag | + kUSDHC_SDR104TuningFlag); + + USDHC_EnableInterruptStatus(base, interruptEnabled); + + if (usingInterruptSignal) + { + USDHC_EnableInterruptSignal(base, interruptEnabled); + } +} + +static status_t USDHC_SetTransferConfig(USDHC_Type *base, usdhc_command_t *command, usdhc_data_t *data) +{ + assert(NULL != command); + + if ((data != NULL) && (data->blockCount > USDHC_MAX_BLOCK_COUNT)) + { + return kStatus_InvalidArgument; + } + + /* Define the flag corresponding to each response type. */ + switch (command->responseType) + { + case kCARD_ResponseTypeNone: + break; + case kCARD_ResponseTypeR1: /* Response 1 */ + case kCARD_ResponseTypeR5: /* Response 5 */ + case kCARD_ResponseTypeR6: /* Response 6 */ + case kCARD_ResponseTypeR7: /* Response 7 */ + + command->flags |= (kUSDHC_ResponseLength48Flag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); + break; + + case kCARD_ResponseTypeR1b: /* Response 1 with busy */ + case kCARD_ResponseTypeR5b: /* Response 5 with busy */ + command->flags |= + (kUSDHC_ResponseLength48BusyFlag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); + break; + + case kCARD_ResponseTypeR2: /* Response 2 */ + command->flags |= (kUSDHC_ResponseLength136Flag | kUSDHC_EnableCrcCheckFlag); + break; + + case kCARD_ResponseTypeR3: /* Response 3 */ + case kCARD_ResponseTypeR4: /* Response 4 */ + command->flags |= (kUSDHC_ResponseLength48Flag); + break; + + default: + break; + } + + if (command->type == kCARD_CommandTypeAbort) + { + command->flags |= kUSDHC_CommandTypeAbortFlag; + } + + if (data) + { + command->flags |= kUSDHC_DataPresentFlag; + + if (data->rxData) + { + command->flags |= kUSDHC_DataReadFlag; + } + if (data->blockCount > 1U) + { + command->flags |= (kUSDHC_MultipleBlockFlag | kUSDHC_EnableBlockCountFlag); + /* auto command 12 */ + if (data->enableAutoCommand12) + { + /* Enable Auto command 12. */ + command->flags |= kUSDHC_EnableAutoCommand12Flag; + } + /* auto command 23 */ + if (data->enableAutoCommand23) + { + command->flags |= kUSDHC_EnableAutoCommand23Flag; + } + } + /* config data block size/block count */ + base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | + (USDHC_BLK_ATT_BLKSIZE(data->blockSize) | USDHC_BLK_ATT_BLKCNT(data->blockCount))); + + /* auto command 23, auto send set block count cmd before multiple read/write */ + if (((command->flags & kUSDHC_EnableAutoCommand23Flag) != 0U)) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_AC23EN_MASK; + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; + /* config the block count to DS_ADDR */ + base->DS_ADDR = data->blockCount; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AC23EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; + } + } + + return kStatus_Success; +} + +static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command) +{ + uint32_t i; + + if (command->responseType != kCARD_ResponseTypeNone) + { + command->response[0U] = base->CMD_RSP0; + if (command->responseType == kCARD_ResponseTypeR2) + { + command->response[1U] = base->CMD_RSP1; + command->response[2U] = base->CMD_RSP2; + command->response[3U] = base->CMD_RSP3; + + i = 4U; + /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document + after removed internal CRC7 and end bit. */ + do + { + command->response[i - 1U] <<= 8U; + if (i > 1U) + { + command->response[i - 1U] |= ((command->response[i - 2U] & 0xFF000000U) >> 24U); + } + } while (i--); + } + } + /* check response error flag */ + if ((command->responseErrorFlags != 0U) && + ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || + (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) + { + if (((command->responseErrorFlags) & (command->response[0U])) != 0U) + { + return kStatus_USDHC_SendCommandFailed; + } + } + + return kStatus_Success; +} + +static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeRead; /* The words can be read at this time. */ + uint32_t readWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_RD_WML_MASK) >> USDHC_WTMK_LVL_RD_WML_SHIFT); + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ + if (readWatermark >= totalWords) + { + wordsCanBeRead = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, + transfers watermark level words. */ + else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) + { + wordsCanBeRead = readWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers left + words. */ + else + { + wordsCanBeRead = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeRead) + { + data->rxData[transferredWords++] = USDHC_ReadData(base); + i++; + } + + return transferredWords; +} + +static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) +{ + uint32_t totalWords; + uint32_t transferredWords = 0U, interruptStatus = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(USDHC_GetInterruptStatusFlags(base) & + (kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + { + } + + interruptStatus = USDHC_GetInterruptStatusFlags(base); + /* during std tuning process, software do not need to read data, but wait BRR is enough */ + if ((data->executeTuning) && (interruptStatus & kUSDHC_BufferReadReadyFlag)) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag | kUSDHC_TuningPassFlag); + return kStatus_Success; + } + else if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); + /* if tuning error occur ,return directly */ + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + /* clear data error flag */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); + } + else + { + } + + if (error == kStatus_Success) + { + transferredWords = USDHC_ReadDataPort(base, data, transferredWords); + /* clear buffer read ready */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag); + } + } + + /* Clear data complete flag after the last read operation. */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataCompleteFlag); + + return error; +} + +static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeWrote; /* Words can be wrote at this time. */ + uint32_t writeWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_WR_WML_MASK) >> USDHC_WTMK_LVL_WR_WML_SHIFT); + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data.*/ + if (writeWatermark >= totalWords) + { + wordsCanBeWrote = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than watermark, + transfers watermark level words. */ + else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) + { + wordsCanBeWrote = writeWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than watermark, transfers left + words. */ + else + { + wordsCanBeWrote = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeWrote) + { + USDHC_WriteData(base, data->txData[transferredWords++]); + i++; + } + + return transferredWords; +} + +static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) +{ + uint32_t totalWords; + + uint32_t transferredWords = 0U, interruptStatus = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = (data->blockCount * data->blockSize) / sizeof(uint32_t); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(USDHC_GetInterruptStatusFlags(base) & + (kUSDHC_BufferWriteReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + { + } + + interruptStatus = USDHC_GetInterruptStatusFlags(base); + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); + /* if tuning error occur ,return directly */ + return kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + /* clear data error flag */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); + } + else + { + } + + if (error == kStatus_Success) + { + transferredWords = USDHC_WriteDataPort(base, data, transferredWords); + /* clear buffer write ready */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferWriteReadyFlag); + } + } + + /* Wait write data complete or data transfer error after the last writing operation. */ + while (!(USDHC_GetInterruptStatusFlags(base) & (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag))) + { + } + + if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag)); + + return error; +} + +void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command) +{ + assert(NULL != command); + + uint32_t mixCtrl, xferType; + + mixCtrl = base->MIX_CTRL; + xferType = base->CMD_XFR_TYP; + + /* config mix parameter */ + mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | + USDHC_MIX_CTRL_AC12EN_MASK); + mixCtrl |= ((command->flags) & (USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | + USDHC_MIX_CTRL_AC12EN_MASK)); + + /* config cmd index */ + xferType &= ~(USDHC_CMD_XFR_TYP_CMDINX_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK | USDHC_CMD_XFR_TYP_CMDTYP_MASK | + USDHC_CMD_XFR_TYP_CICEN_MASK | USDHC_CMD_XFR_TYP_CCCEN_MASK | USDHC_CMD_XFR_TYP_RSPTYP_MASK); + + xferType = (((command->index << USDHC_CMD_XFR_TYP_CMDINX_SHIFT) & USDHC_CMD_XFR_TYP_CMDINX_MASK) | + ((command->flags) & + (USDHC_CMD_XFR_TYP_DPSEL_MASK | USDHC_CMD_XFR_TYP_CMDTYP_MASK | USDHC_CMD_XFR_TYP_CICEN_MASK | + USDHC_CMD_XFR_TYP_CCCEN_MASK | USDHC_CMD_XFR_TYP_RSPTYP_MASK))); + /* config the mix parameter */ + base->MIX_CTRL = mixCtrl; + /* config the command xfertype and argument */ + base->CMD_ARG = command->argument; + base->CMD_XFR_TYP = xferType; +} + +static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool executeTuning) +{ + assert(NULL != command); + + status_t error = kStatus_Success; + uint32_t interruptStatus = 0U; + /* tuning cmd do not need to wait command done */ + if (!executeTuning) + { + /* Wait command complete or USDHC encounters error. */ + while (!(USDHC_GetInterruptStatusFlags(base) & (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag))) + { + } + + interruptStatus = USDHC_GetInterruptStatusFlags(base); + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_CommandErrorFlag) != 0U) + { + error = kStatus_Fail; + } + else + { + } + /* Receive response when command completes successfully. */ + if (error == kStatus_Success) + { + error = USDHC_ReceiveCommandResponse(base, command); + } + + USDHC_ClearInterruptStatusFlags( + base, (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag | kUSDHC_TuningErrorFlag)); + } + + return error; +} + +static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA) +{ + status_t error = kStatus_Success; + uint32_t interruptStatus = 0U; + + if (enDMA) + { + /* Wait data complete or USDHC encounters error. */ + while (!(USDHC_GetInterruptStatusFlags(base) & + (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | kUSDHC_TuningErrorFlag))) + { + } + + interruptStatus = USDHC_GetInterruptStatusFlags(base); + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) != 0U) + { + if (!(data->enableIgnoreError) || (interruptStatus & kUSDHC_DataTimeoutFlag)) + { + error = kStatus_Fail; + } + } + else + { + } + + USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | + kUSDHC_TuningPassFlag | kUSDHC_TuningErrorFlag)); + } + else + { + if (data->rxData) + { + error = USDHC_ReadByDataPortBlocking(base, data); + } + else + { + error = USDHC_WriteByDataPortBlocking(base, data); + } + } + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* invalidate cache for read */ + if ((data != NULL) && (data->rxData != NULL)) + { + /* invalidate the DCACHE */ + DCACHE_InvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } +#endif + + return error; +} + +void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config) +{ + assert(config); + assert((config->writeWatermarkLevel >= 1U) && (config->writeWatermarkLevel <= 128U)); + assert((config->readWatermarkLevel >= 1U) && (config->readWatermarkLevel <= 128U)); + assert(config->writeBurstLen <= 16U); + + uint32_t proctl, sysctl, wml; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable USDHC clock. */ + CLOCK_EnableClock(s_usdhcClock[USDHC_GetInstance(base)]); +#endif + + /* Reset USDHC. */ + USDHC_Reset(base, kUSDHC_ResetAll, 100U); + + proctl = base->PROT_CTRL; + wml = base->WTMK_LVL; + sysctl = base->SYS_CTRL; + + proctl &= ~(USDHC_PROT_CTRL_EMODE_MASK | USDHC_PROT_CTRL_DMASEL_MASK); + /* Endian mode*/ + proctl |= USDHC_PROT_CTRL_EMODE(config->endianMode); + + /* Watermark level */ + wml &= ~(USDHC_WTMK_LVL_RD_WML_MASK | USDHC_WTMK_LVL_WR_WML_MASK | USDHC_WTMK_LVL_RD_BRST_LEN_MASK | + USDHC_WTMK_LVL_WR_BRST_LEN_MASK); + wml |= (USDHC_WTMK_LVL_RD_WML(config->readWatermarkLevel) | USDHC_WTMK_LVL_WR_WML(config->writeWatermarkLevel) | + USDHC_WTMK_LVL_RD_BRST_LEN(config->readBurstLen) | USDHC_WTMK_LVL_WR_BRST_LEN(config->writeBurstLen)); + + /* config the data timeout value */ + sysctl &= ~USDHC_SYS_CTRL_DTOCV_MASK; + sysctl |= USDHC_SYS_CTRL_DTOCV(config->dataTimeout); + + base->SYS_CTRL = sysctl; + base->WTMK_LVL = wml; + base->PROT_CTRL = proctl; + +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + /* disable external DMA */ + base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; +#endif + /* disable internal DMA */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + + /* Enable interrupt status but doesn't enable interrupt signal. */ + USDHC_SetTransferInterrupt(base, false); +} + +void USDHC_Deinit(USDHC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable clock. */ + CLOCK_DisableClock(s_usdhcClock[USDHC_GetInstance(base)]); +#endif +} + +bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout) +{ + base->SYS_CTRL |= (mask & (USDHC_SYS_CTRL_RSTA_MASK | USDHC_SYS_CTRL_RSTC_MASK | USDHC_SYS_CTRL_RSTD_MASK)); + /* Delay some time to wait reset success. */ + while ((base->SYS_CTRL & mask) != 0U) + { + if (timeout == 0U) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability) +{ + assert(capability); + + uint32_t htCapability; + uint32_t maxBlockLength; + + htCapability = base->HOST_CTRL_CAP; + + /* Get the capability of USDHC. */ + maxBlockLength = ((htCapability & USDHC_HOST_CTRL_CAP_MBL_MASK) >> USDHC_HOST_CTRL_CAP_MBL_SHIFT); + capability->maxBlockLength = (512U << maxBlockLength); + /* Other attributes not in HTCAPBLT register. */ + capability->maxBlockCount = USDHC_MAX_BLOCK_COUNT; + capability->flags = (htCapability & (kUSDHC_SupportAdmaFlag | kUSDHC_SupportHighSpeedFlag | kUSDHC_SupportDmaFlag | + kUSDHC_SupportSuspendResumeFlag | kUSDHC_SupportV330Flag)); + capability->flags |= (htCapability & kUSDHC_SupportV300Flag); + capability->flags |= (htCapability & kUSDHC_SupportV180Flag); + capability->flags |= + (htCapability & (kUSDHC_SupportDDR50Flag | kUSDHC_SupportSDR104Flag | kUSDHC_SupportSDR50Flag)); + /* USDHC support 4/8 bit data bus width. */ + capability->flags |= (kUSDHC_Support4BitFlag | kUSDHC_Support8BitFlag); +} + +uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) +{ + assert(srcClock_Hz != 0U); + assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz)); + + uint32_t totalDiv = 0U; + uint32_t divisor = 0U; + uint32_t prescaler = 0U; + uint32_t sysctl = 0U; + uint32_t nearestFrequency = 0U; + uint32_t maxClKFS = ((USDHC_SYS_CTRL_SDCLKFS_MASK >> USDHC_SYS_CTRL_SDCLKFS_SHIFT) + 1U); + bool enDDR = false; + /* DDR mode max clkfs can reach 512 */ + if ((base->MIX_CTRL & USDHC_MIX_CTRL_DDR_EN_MASK) != 0U) + { + enDDR = true; + maxClKFS *= 2U; + } + /* calucate total divisor first */ + totalDiv = srcClock_Hz / busClock_Hz; + + if (totalDiv != 0U) + { + /* calucate the divisor (srcClock_Hz / divisor) <= busClock_Hz */ + if ((srcClock_Hz / totalDiv) > busClock_Hz) + { + totalDiv++; + } + + /* divide the total divisor to div and prescaler */ + if (totalDiv > USDHC_MAX_DVS) + { + prescaler = totalDiv / USDHC_MAX_DVS; + /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */ + while (((maxClKFS % prescaler) != 0U) || (prescaler == 1U)) + { + prescaler++; + } + /* calucate the divisor */ + divisor = totalDiv / prescaler; + /* fine tuning the divisor until divisor * prescaler >= totalDiv */ + while ((divisor * prescaler) < totalDiv) + { + divisor++; + } + nearestFrequency = srcClock_Hz / divisor / prescaler; + } + else + { + /* in this situation , divsior and SDCLKFS can generate same clock + use SDCLKFS*/ + if ((USDHC_MAX_DVS % totalDiv) == 0U) + { + divisor = 0U; + prescaler = totalDiv; + } + else + { + divisor = totalDiv; + prescaler = 0U; + } + nearestFrequency = srcClock_Hz / totalDiv; + } + } + /* in this condition , srcClock_Hz = busClock_Hz, */ + else + { + /* in DDR mode , set SDCLKFS to 0, divisor = 0, actually the + totoal divider = 2U */ + divisor = 0U; + prescaler = 0U; + nearestFrequency = srcClock_Hz; + } + + /* calucate the value write to register */ + if (divisor != 0U) + { + USDHC_PREV_DVS(divisor); + } + /* calucate the value write to register */ + if (prescaler != 0U) + { + USDHC_PREV_CLKFS(prescaler, (enDDR ? 2U : 1U)); + } + + /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */ + sysctl = base->SYS_CTRL; + sysctl &= ~(USDHC_SYS_CTRL_DVS_MASK | USDHC_SYS_CTRL_SDCLKFS_MASK); + sysctl |= (USDHC_SYS_CTRL_DVS(divisor) | USDHC_SYS_CTRL_SDCLKFS(prescaler)); + base->SYS_CTRL = sysctl; + + /* Wait until the SD clock is stable. */ + while (!(base->PRES_STATE & USDHC_PRES_STATE_SDSTB_MASK)) + { + } + + return nearestFrequency; +} + +bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout) +{ + base->SYS_CTRL |= USDHC_SYS_CTRL_INITA_MASK; + /* Delay some time to wait card become active state. */ + while ((base->SYS_CTRL & USDHC_SYS_CTRL_INITA_MASK) == USDHC_SYS_CTRL_INITA_MASK) + { + if (!timeout) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config) +{ + assert(config); + assert(config->ackTimeoutCount <= (USDHC_MMC_BOOT_DTOCV_ACK_MASK >> USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)); + assert(config->blockCount <= (USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK >> USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)); + + uint32_t mmcboot = 0U; + + mmcboot = (USDHC_MMC_BOOT_DTOCV_ACK(config->ackTimeoutCount) | USDHC_MMC_BOOT_BOOT_MODE(config->bootMode) | + USDHC_MMC_BOOT_BOOT_BLK_CNT(config->blockCount)); + + if (config->enableBootAck) + { + mmcboot |= USDHC_MMC_BOOT_BOOT_ACK_MASK; + } + if (config->enableBoot) + { + mmcboot |= USDHC_MMC_BOOT_BOOT_EN_MASK; + } + if (config->enableAutoStopAtBlockGap) + { + mmcboot |= USDHC_MMC_BOOT_AUTO_SABG_EN_MASK; + } + + base->MMC_BOOT = mmcboot; +} + +status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + usdhc_data_t *dataConfig, + uint32_t flags) +{ + assert(NULL != dmaConfig); + assert(NULL != dmaConfig->admaTable); + assert(NULL != dataConfig); + + const uint32_t *startAddress; + uint32_t entries; + uint32_t i, dmaBufferLen = 0U; + usdhc_adma1_descriptor_t *adma1EntryAddress; + usdhc_adma2_descriptor_t *adma2EntryAddress; + uint32_t dataBytes = dataConfig->blockSize * dataConfig->blockCount; + const uint32_t *data = (dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData; + + /* check DMA data buffer address align or not */ + if (((dmaConfig->dmaMode == kUSDHC_DmaModeAdma1) && (((uint32_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0U)) || + ((dmaConfig->dmaMode == kUSDHC_DmaModeAdma2) && (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0U)) || + ((dmaConfig->dmaMode == kUSDHC_DmaModeSimple) && (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0U))) + { + return kStatus_USDHC_DMADataAddrNotAlign; + } + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (dataBytes % sizeof(uint32_t) != 0U) + { + /* make the data length as word-aligned */ + dataBytes += sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); + } + + startAddress = data; + + switch (dmaConfig->dmaMode) + { +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + case kUSDHC_ExternalDMA: + /* enable the external DMA */ + base->VEND_SPEC |= USDHC_VEND_SPEC_EXT_DMA_EN_MASK; + break; +#endif + case kUSDHC_DmaModeSimple: + /* in simple DMA mode if use auto CMD23, address should load to ADMA addr, + and block count should load to DS_ADDR*/ + if ((flags & kUSDHC_EnableAutoCommand23Flag) != 0U) + { + base->ADMA_SYS_ADDR = (uint32_t)data; + } + else + { + base->DS_ADDR = (uint32_t)data; + } + + break; + + case kUSDHC_DmaModeAdma1: + + /* Check if ADMA descriptor's number is enough. */ + if ((dataBytes % USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) + { + entries = dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + entries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + } + + /* ADMA1 needs two descriptors to finish a transfer */ + entries <<= 1U; + + if (entries > ((dmaConfig->admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma1_descriptor_t))) + { + return kStatus_OutOfRange; + } + + adma1EntryAddress = (usdhc_adma1_descriptor_t *)(dmaConfig->admaTable); + for (i = 0U; i < entries; i += 2U) + { + if (dataBytes > USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + dmaBufferLen = USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + dataBytes -= dmaBufferLen; + } + else + { + dmaBufferLen = dataBytes; + } + + adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); + adma1EntryAddress[i] |= kUSDHC_Adma1DescriptorTypeSetLength; + adma1EntryAddress[i + 1U] = ((uint32_t)(startAddress) << USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT); + adma1EntryAddress[i + 1U] |= kUSDHC_Adma1DescriptorTypeTransfer; + startAddress += dmaBufferLen / sizeof(uint32_t); + } + /* the end of the descriptor */ + adma1EntryAddress[i - 1U] |= kUSDHC_Adma1DescriptorEndFlag; + /* When use ADMA, disable simple DMA */ + base->DS_ADDR = 0U; + base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable); + break; + + case kUSDHC_DmaModeAdma2: + /* Check if ADMA descriptor's number is enough. */ + if ((dataBytes % USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) + { + entries = dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + entries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + } + + if (entries > ((dmaConfig->admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma2_descriptor_t))) + { + return kStatus_OutOfRange; + } + + adma2EntryAddress = (usdhc_adma2_descriptor_t *)(dmaConfig->admaTable); + for (i = 0U; i < entries; i++) + { + if (dataBytes > USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + dmaBufferLen = USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + dataBytes -= dmaBufferLen; + } + else + { + dmaBufferLen = dataBytes; + } + + /* Each descriptor for ADMA2 is 64-bit in length */ + adma2EntryAddress[i].address = startAddress; + adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); + adma2EntryAddress[i].attribute |= kUSDHC_Adma2DescriptorTypeTransfer; + startAddress += (dmaBufferLen / sizeof(uint32_t)); + } + /* set the end bit */ + adma2EntryAddress[i - 1U].attribute |= kUSDHC_Adma2DescriptorEndFlag; + /* When use ADMA, disable simple DMA */ + base->DS_ADDR = 0U; + base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable); + + break; + default: + return kStatus_USDHC_PrepareAdmaDescriptorFailed; + } + + /* for external dma */ + if (dmaConfig->dmaMode != kUSDHC_ExternalDMA) + { +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + /* disable the external DMA if support */ + base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; +#endif + /* select DMA mode and config the burst length */ + base->PROT_CTRL &= ~(USDHC_PROT_CTRL_DMASEL_MASK | USDHC_PROT_CTRL_BURST_LEN_EN_MASK); + base->PROT_CTRL |= + USDHC_PROT_CTRL_DMASEL(dmaConfig->dmaMode) | USDHC_PROT_CTRL_BURST_LEN_EN(dmaConfig->burstLen); + /* enable DMA */ + base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; + } + + /* disable the interrupt signal for interrupt mode */ + USDHC_DisableInterruptSignal(base, kUSDHC_BufferReadReadyFlag | kUSDHC_BufferWriteReadyFlag); + + return kStatus_Success; +} + +status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer) +{ + assert(transfer); + + status_t error = kStatus_Success; + usdhc_command_t *command = transfer->command; + usdhc_data_t *data = transfer->data; + bool enDMA = false; + + /* Wait until command/data bus out of busy status. */ + while (USDHC_GetPresentStatusFlags(base) & kUSDHC_CommandInhibitFlag) + { + } + while (data && (USDHC_GetPresentStatusFlags(base) & kUSDHC_DataInhibitFlag)) + { + } + /*check re-tuning request*/ + if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_ReTuningEventFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); + return kStatus_USDHC_ReTuningRequest; + } + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + if ((data != NULL) && (!(data->executeTuning))) + { + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif + + /* config the transfer parameter */ + if (kStatus_Success != USDHC_SetTransferConfig(base, command, data)) + { + return kStatus_InvalidArgument; + } + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if ((data != NULL) && (dmaConfig != NULL) && (!data->executeTuning)) + { +#if 0 //not use adma. there are some error not solved! + error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, command->flags); + /* if the target data buffer address is not align , we change the transfer mode + * to polling automatically, other DMA config error will not cover by driver, user + * should handle it + */ + if ((error != kStatus_USDHC_DMADataAddrNotAlign) && (error != kStatus_Success)) + { + return kStatus_USDHC_PrepareAdmaDescriptorFailed; + } + else if (error == kStatus_USDHC_DMADataAddrNotAlign) + { + enDMA = false; + /* disable DMA, using polling mode in this situation */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + } + else + { + enDMA = true; + } +#else + enDMA = false; + /* disable DMA, using polling mode in this situation */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; +#endif + } + else + { + /* disable DMA */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + } + /* send command */ + USDHC_SendCommand(base, command); + /* wait command done */ + error = USDHC_WaitCommandDone(base, command, ((data == NULL) ? false : data->executeTuning)); + /* transfer data */ + if ((data != NULL) && (error == kStatus_Success)) + { + return USDHC_TransferDataBlocking(base, data, enDMA); + } + + return error; +} + +status_t USDHC_TransferNonBlocking(USDHC_Type *base, + usdhc_handle_t *handle, + usdhc_adma_config_t *dmaConfig, + usdhc_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + status_t error = kStatus_Success; + usdhc_command_t *command = transfer->command; + usdhc_data_t *data = transfer->data; + + /* Wait until command/data bus out of busy status. */ + if ((USDHC_GetPresentStatusFlags(base) & kUSDHC_CommandInhibitFlag) || + (data && (USDHC_GetPresentStatusFlags(base) & kUSDHC_DataInhibitFlag))) + { + return kStatus_USDHC_BusyTransferring; + } + + /*check re-tuning request*/ + if ((USDHC_GetInterruptStatusFlags(base) & (kUSDHC_ReTuningEventFlag)) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); + return kStatus_USDHC_ReTuningRequest; + } + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + if ((data != NULL) && (!(data->executeTuning))) + { + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif + + /* Save command and data into handle before transferring. */ + handle->command = command; + handle->data = data; + handle->interruptFlags = 0U; + /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */ + handle->transferredWords = 0U; + + if (kStatus_Success != USDHC_SetTransferConfig(base, command, data)) + { + return kStatus_InvalidArgument; + } + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if ((data != NULL) && (dmaConfig != NULL) && (!data->executeTuning)) + { + error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, command->flags); + /* if the target data buffer address is not align , we change the transfer mode + * to polling automatically, other DMA config error will not cover by driver, user + * should handle it + */ + if ((error != kStatus_USDHC_DMADataAddrNotAlign) && (error != kStatus_Success)) + { + return kStatus_USDHC_PrepareAdmaDescriptorFailed; + } + else if (error == kStatus_USDHC_DMADataAddrNotAlign) + { + /* disable DMA, using polling mode in this situation */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + /* enable the interrupt signal for interrupt mode */ + USDHC_EnableInterruptSignal(base, kUSDHC_BufferReadReadyFlag | kUSDHC_BufferWriteReadyFlag); + } + else + { + } + } + else + { + /* disable DMA */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + } + + /* enable the buffer read ready for std tuning */ + if ((data != NULL) && (data->executeTuning)) + { + USDHC_EnableInterruptSignal(base, kUSDHC_BufferReadReadyFlag); + } + + /* send command */ + USDHC_SendCommand(base, command); + + return kStatus_Success; +} + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) +#else +void USDHC_EnableManualTuning(USDHC_Type *base, bool enable) +{ + if (enable) + { + /* make sure std_tun_en bit is clear */ + base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; + /* disable auto tuning here */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + /* execute tuning for SDR104 mode */ + base->MIX_CTRL |= + USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK | USDHC_MIX_CTRL_FBCLK_SEL_MASK; + } + else + { /* abort the tuning */ + base->MIX_CTRL &= ~(USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK); + } +} + +status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay) +{ + uint32_t clkTuneCtrl = 0U; + + clkTuneCtrl = base->CLK_TUNE_CTRL_STATUS; + + clkTuneCtrl &= ~USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK; + + clkTuneCtrl |= USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(delay); + + /* load the delay setting */ + base->CLK_TUNE_CTRL_STATUS = clkTuneCtrl; + /* check delat setting error */ + if (base->CLK_TUNE_CTRL_STATUS & + (USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable) +{ + uint32_t tuningCtrl = 0U; + + if (enable) + { + /* feedback clock */ + base->MIX_CTRL |= USDHC_MIX_CTRL_FBCLK_SEL_MASK; + /* config tuning start and step */ + tuningCtrl = base->TUNING_CTRL; + tuningCtrl &= ~(USDHC_TUNING_CTRL_TUNING_START_TAP_MASK | USDHC_TUNING_CTRL_TUNING_STEP_MASK); + tuningCtrl |= (USDHC_TUNING_CTRL_TUNING_START_TAP(tuningStartTap) | USDHC_TUNING_CTRL_TUNING_STEP(step) | + USDHC_TUNING_CTRL_STD_TUNING_EN_MASK); + base->TUNING_CTRL = tuningCtrl; + + /* excute tuning */ + base->AUTOCMD12_ERR_STATUS |= + (USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); + } + else + { + /* disable the standard tuning */ + base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; + /* clear excute tuning */ + base->AUTOCMD12_ERR_STATUS &= + ~(USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); + } +} + +void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base) +{ + uint32_t busWidth = 0U; + + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK; + busWidth = (base->PROT_CTRL & USDHC_PROT_CTRL_DTW_MASK) >> USDHC_PROT_CTRL_DTW_SHIFT; + if (busWidth == kUSDHC_DataBusWidth1Bit) + { + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else if (busWidth == kUSDHC_DataBusWidth4Bit) + { + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else if (busWidth == kUSDHC_DataBusWidth8Bit) + { + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else + { + } +} +#endif + +static void USDHC_TransferHandleCardDetect(usdhc_handle_t *handle, uint32_t interruptFlags) +{ + if (interruptFlags & kUSDHC_CardInsertionFlag) + { + if (handle->callback.CardInserted) + { + handle->callback.CardInserted(); + } + } + else + { + if (handle->callback.CardRemoved) + { + handle->callback.CardRemoved(); + } + } +} + +static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->command); + + if ((interruptFlags & kUSDHC_CommandErrorFlag) && (!(handle->data)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); + } + else + { + /* Receive response */ + if (kStatus_Success != USDHC_ReceiveCommandResponse(base, handle->command)) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); + } + else if ((!(handle->data)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + else + { + } + } +} + +static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->data); + + if ((!(handle->data->enableIgnoreError) || (interruptFlags & kUSDHC_DataTimeoutFlag)) && + (interruptFlags & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_TransferDataFailed, handle->userData); + } + else + { + if (interruptFlags & kUSDHC_BufferReadReadyFlag) + { + /* std tuning process only need to wait BRR */ + if (handle->data->executeTuning) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + else + { + handle->transferredWords = USDHC_ReadDataPort(base, handle->data, handle->transferredWords); + } + } + else if (interruptFlags & kUSDHC_BufferWriteReadyFlag) + { + handle->transferredWords = USDHC_WriteDataPort(base, handle->data, handle->transferredWords); + } + else if ((interruptFlags & kUSDHC_DataCompleteFlag) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + else + { + /* Do nothing when DMA complete flag is set. Wait until data complete flag is set. */ + } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* invalidate cache for read */ + if ((handle->data != NULL) && (handle->data->rxData != NULL)) + { + /* invalidate the DCACHE */ + DCACHE_InvalidateByRange((uint32_t)handle->data->rxData, + (handle->data->blockSize) * (handle->data->blockCount)); + } +#endif + } +} + +static void USDHC_TransferHandleSdioInterrupt(usdhc_handle_t *handle) +{ + if (handle->callback.SdioInterrupt) + { + handle->callback.SdioInterrupt(); + } +} + +static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->callback.ReTuning); + /* retuning request */ + if ((interruptFlags & kUSDHC_TuningErrorFlag) == kUSDHC_TuningErrorFlag) + { + handle->callback.ReTuning(); /* retuning fail */ + } +} + +static void USDHC_TransferHandleSdioBlockGap(usdhc_handle_t *handle) +{ + if (handle->callback.SdioBlockGap) + { + handle->callback.SdioBlockGap(); + } +} + +void USDHC_TransferCreateHandle(USDHC_Type *base, + usdhc_handle_t *handle, + const usdhc_transfer_callback_t *callback, + void *userData) +{ + assert(handle); + assert(callback); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the callback. */ + handle->callback.CardInserted = callback->CardInserted; + handle->callback.CardRemoved = callback->CardRemoved; + handle->callback.SdioInterrupt = callback->SdioInterrupt; + handle->callback.SdioBlockGap = callback->SdioBlockGap; + handle->callback.TransferComplete = callback->TransferComplete; + handle->callback.ReTuning = callback->ReTuning; + handle->userData = userData; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_usdhcHandle[USDHC_GetInstance(base)] = handle; + + /* Enable interrupt in NVIC. */ + USDHC_SetTransferInterrupt(base, true); + /* disable the tuning pass interrupt */ + USDHC_DisableInterruptSignal(base, kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag); + /* save IRQ handler */ + s_usdhcIsr = USDHC_TransferHandleIRQ; + + EnableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); +} + +void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle) +{ + assert(handle); + + uint32_t interruptFlags; + + interruptFlags = USDHC_GetInterruptStatusFlags(base); + handle->interruptFlags = interruptFlags; + + if (interruptFlags & kUSDHC_CardDetectFlag) + { + USDHC_TransferHandleCardDetect(handle, (interruptFlags & kUSDHC_CardDetectFlag)); + } + if (interruptFlags & kUSDHC_CommandFlag) + { + USDHC_TransferHandleCommand(base, handle, (interruptFlags & kUSDHC_CommandFlag)); + } + if (interruptFlags & kUSDHC_DataFlag) + { + USDHC_TransferHandleData(base, handle, (interruptFlags & kUSDHC_DataFlag)); + } + if (interruptFlags & kUSDHC_CardInterruptFlag) + { + USDHC_TransferHandleSdioInterrupt(handle); + } + if (interruptFlags & kUSDHC_BlockGapEventFlag) + { + USDHC_TransferHandleSdioBlockGap(handle); + } + if (interruptFlags & kUSDHC_SDR104TuningFlag) + { + USDHC_TransferHandleReTuning(base, handle, (interruptFlags & kUSDHC_SDR104TuningFlag)); + } + + USDHC_ClearInterruptStatusFlags(base, interruptFlags); +} + +#ifdef USDHC0 +void USDHC0_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[0U], s_usdhcHandle[0U]); +} +#endif + +#ifdef USDHC1 +void USDHC1_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[1U], s_usdhcHandle[1U]); +} +#endif + +#ifdef USDHC2 +void USDHC2_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[2U], s_usdhcHandle[2U]); +} + +#endif diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.h new file mode 100644 index 0000000000000000000000000000000000000000..bde8df88ba0e4ac1f5b430ab24c112098e4ac332 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.h @@ -0,0 +1,1380 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_USDHC_H_ +#define _FSL_USDHC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usdhc + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.1.1. */ +#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 1U)) +/*@}*/ + +/*! @brief Maximum block count can be set one time */ +#define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT) + +/*! @brief USDHC status */ +enum _usdhc_status +{ + kStatus_USDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_USDHC, 0U), /*!< Transfer is on-going */ + kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U), /*!< Set DMA descriptor failed */ + kStatus_USDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_USDHC, 2U), /*!< Send command failed */ + kStatus_USDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_USDHC, 3U), /*!< Transfer data failed */ + kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */ + kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */ + kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */ + +}; + +/*! @brief Host controller capabilities flag mask */ +enum _usdhc_capability_flag +{ + kUSDHC_SupportAdmaFlag = USDHC_HOST_CTRL_CAP_ADMAS_MASK, /*!< Support ADMA */ + kUSDHC_SupportHighSpeedFlag = USDHC_HOST_CTRL_CAP_HSS_MASK, /*!< Support high-speed */ + kUSDHC_SupportDmaFlag = USDHC_HOST_CTRL_CAP_DMAS_MASK, /*!< Support DMA */ + kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume */ + kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK, /*!< Support voltage 3.3V */ + kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK, /*!< Support voltage 3.0V */ + kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK, /*!< Support voltage 1.8V */ + /* Put additional two flags in HTCAPBLT_MBL's position. */ + kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Support 4 bit mode */ + kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), /*!< Support 8 bit mode */ + /* sd version 3.0 new feature */ + kUSDHC_SupportDDR50Flag = USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK, /*!< support DDR50 mode */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE) + kUSDHC_SupportSDR104Flag = 0, /*!< not support SDR104 mode */ +#else + kUSDHC_SupportSDR104Flag = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */ +#endif +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_SupportSDR50Flag = 0U, /*!< not support SDR50 mode */ +#else + kUSDHC_SupportSDR50Flag = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK, /*!< support SDR50 mode */ +#endif +}; + +/*! @brief Wakeup event mask */ +enum _usdhc_wakeup_event +{ + kUSDHC_WakeupEventOnCardInt = USDHC_PROT_CTRL_WECINT_MASK, /*!< Wakeup on card interrupt */ + kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, /*!< Wakeup on card insertion */ + kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK, /*!< Wakeup on card removal */ + + kUSDHC_WakeupEventsAll = (kUSDHC_WakeupEventOnCardInt | kUSDHC_WakeupEventOnCardInsert | + kUSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */ +}; + +/*! @brief Reset type mask */ +enum _usdhc_reset +{ + kUSDHC_ResetAll = USDHC_SYS_CTRL_RSTA_MASK, /*!< Reset all except card detection */ + kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, /*!< Reset command line */ + kUSDHC_ResetData = USDHC_SYS_CTRL_RSTD_MASK, /*!< Reset data line */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ResetTuning = 0U, /*!< no reset tuning circuit bit */ +#else + kUSDHC_ResetTuning = USDHC_SYS_CTRL_RSTT_MASK, /*!< reset tuning circuit */ +#endif + + kUSDHC_ResetsAll = + (kUSDHC_ResetAll | kUSDHC_ResetCommand | kUSDHC_ResetData | kUSDHC_ResetTuning), /*!< All reset types */ +}; + +/*! @brief Transfer flag mask */ +enum _usdhc_transfer_flag +{ + kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, /*!< Enable DMA */ + + kUSDHC_CommandTypeSuspendFlag = (USDHC_CMD_XFR_TYP_CMDTYP(1U)), /*!< Suspend command */ + kUSDHC_CommandTypeResumeFlag = (USDHC_CMD_XFR_TYP_CMDTYP(2U)), /*!< Resume command */ + kUSDHC_CommandTypeAbortFlag = (USDHC_CMD_XFR_TYP_CMDTYP(3U)), /*!< Abort command */ + + kUSDHC_EnableBlockCountFlag = USDHC_MIX_CTRL_BCEN_MASK, /*!< Enable block count */ + kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, /*!< Enable auto CMD12 */ + kUSDHC_DataReadFlag = USDHC_MIX_CTRL_DTDSEL_MASK, /*!< Enable data read */ + kUSDHC_MultipleBlockFlag = USDHC_MIX_CTRL_MSBSEL_MASK, /*!< Multiple block data read/write */ + kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, /*!< Enable auto CMD23 */ + + kUSDHC_ResponseLength136Flag = USDHC_CMD_XFR_TYP_RSPTYP(1U), /*!< 136 bit response length */ + kUSDHC_ResponseLength48Flag = USDHC_CMD_XFR_TYP_RSPTYP(2U), /*!< 48 bit response length */ + kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), /*!< 48 bit response length with busy status */ + + kUSDHC_EnableCrcCheckFlag = USDHC_CMD_XFR_TYP_CCCEN_MASK, /*!< Enable CRC check */ + kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, /*!< Enable index check */ + kUSDHC_DataPresentFlag = USDHC_CMD_XFR_TYP_DPSEL_MASK, /*!< Data present flag */ +}; + +/*! @brief Present status flag mask */ +enum _usdhc_present_status_flag +{ + kUSDHC_CommandInhibitFlag = USDHC_PRES_STATE_CIHB_MASK, /*!< Command inhibit */ + kUSDHC_DataInhibitFlag = USDHC_PRES_STATE_CDIHB_MASK, /*!< Data inhibit */ + kUSDHC_DataLineActiveFlag = USDHC_PRES_STATE_DLA_MASK, /*!< Data line active */ + kUSDHC_SdClockStableFlag = USDHC_PRES_STATE_SDSTB_MASK, /*!< SD bus clock stable */ + kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK, /*!< Write transfer active */ + kUSDHC_ReadTransferActiveFlag = USDHC_PRES_STATE_RTA_MASK, /*!< Read transfer active */ + kUSDHC_BufferWriteEnableFlag = USDHC_PRES_STATE_BWEN_MASK, /*!< Buffer write enable */ + kUSDHC_BufferReadEnableFlag = USDHC_PRES_STATE_BREN_MASK, /*!< Buffer read enable */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_DelaySettingFinishedFlag = 0U, /*!< not support */ + kUSDHC_ReTuningRequestFlag = 0U, /*!< not support */ +#else + kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, /*!< re-tuning request flag ,only used for SDR104 mode */ + kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, /*!< delay setting finished flag */ +#endif + + kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */ + kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */ + + kUSDHC_Data0LineLevelFlag = (1U << USDHC_PRES_STATE_DLSL_SHIFT), /*!< Data0 line signal level */ + kUSDHC_Data1LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U)), /*!< Data1 line signal level */ + kUSDHC_Data2LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U)), /*!< Data2 line signal level */ + kUSDHC_Data3LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U)), /*!< Data3 line signal level */ + kUSDHC_Data4LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U)), /*!< Data4 line signal level */ + kUSDHC_Data5LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U)), /*!< Data5 line signal level */ + kUSDHC_Data6LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U)), /*!< Data6 line signal level */ + kUSDHC_Data7LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */ +}; + +/*! @brief Interrupt status flag mask */ +enum _usdhc_interrupt_status_flag +{ + kUSDHC_CommandCompleteFlag = USDHC_INT_STATUS_CC_MASK, /*!< Command complete */ + kUSDHC_DataCompleteFlag = USDHC_INT_STATUS_TC_MASK, /*!< Data complete */ + kUSDHC_BlockGapEventFlag = USDHC_INT_STATUS_BGE_MASK, /*!< Block gap event */ + kUSDHC_DmaCompleteFlag = USDHC_INT_STATUS_DINT_MASK, /*!< DMA interrupt */ + kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK, /*!< Buffer write ready */ + kUSDHC_BufferReadReadyFlag = USDHC_INT_STATUS_BRR_MASK, /*!< Buffer read ready */ + kUSDHC_CardInsertionFlag = USDHC_INT_STATUS_CINS_MASK, /*!< Card inserted */ + kUSDHC_CardRemovalFlag = USDHC_INT_STATUS_CRM_MASK, /*!< Card removed */ + kUSDHC_CardInterruptFlag = USDHC_INT_STATUS_CINT_MASK, /*!< Card interrupt */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ReTuningEventFlag = 0U, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = 0U, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = 0U, /*!< SDR104 tuning error flag */ +#else + kUSDHC_ReTuningEventFlag = USDHC_INT_STATUS_RTE_MASK, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = USDHC_INT_STATUS_TP_MASK, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = USDHC_INT_STATUS_TNE_MASK, /*!< SDR104 tuning error flag */ +#endif + + kUSDHC_CommandTimeoutFlag = USDHC_INT_STATUS_CTOE_MASK, /*!< Command timeout error */ + kUSDHC_CommandCrcErrorFlag = USDHC_INT_STATUS_CCE_MASK, /*!< Command CRC error */ + kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK, /*!< Command end bit error */ + kUSDHC_CommandIndexErrorFlag = USDHC_INT_STATUS_CIE_MASK, /*!< Command index error */ + kUSDHC_DataTimeoutFlag = USDHC_INT_STATUS_DTOE_MASK, /*!< Data timeout error */ + kUSDHC_DataCrcErrorFlag = USDHC_INT_STATUS_DCE_MASK, /*!< Data CRC error */ + kUSDHC_DataEndBitErrorFlag = USDHC_INT_STATUS_DEBE_MASK, /*!< Data end bit error */ + kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_DmaErrorFlag = USDHC_INT_STATUS_DMAE_MASK, /*!< DMA error */ + + kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag | + kUSDHC_CommandIndexErrorFlag), /*!< Command error */ + kUSDHC_DataErrorFlag = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag | + kUSDHC_AutoCommand12ErrorFlag), /*!< Data error */ + kUSDHC_ErrorFlag = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */ + kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag | + kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< Data interrupts */ + kUSDHC_CommandFlag = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */ + kUSDHC_CardDetectFlag = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag), /*!< Card detection interrupts */ + kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag), + + kUSDHC_AllInterruptFlags = (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag | + kUSDHC_DataFlag | kUSDHC_ErrorFlag | kUSDHC_SDR104TuningFlag), /*!< All flags mask */ +}; + +/*! @brief Auto CMD12 error status flag mask */ +enum _usdhc_auto_command12_error_status_flag +{ + kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK, /*!< Not executed error */ + kUSDHC_AutoCommand12TimeoutFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK, /*!< Timeout error */ + kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK, /*!< End bit error */ + kUSDHC_AutoCommand12CrcErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK, /*!< CRC error */ + kUSDHC_AutoCommand12IndexErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK, /*!< Index error */ + kUSDHC_AutoCommand12NotIssuedFlag = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */ +}; + +/*! @brief standard tuning flag */ +enum _usdhc_standard_tuning +{ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ExecuteTuning = 0U, /*!< not support */ + kUSDHC_TuningSampleClockSel = 0U, /*!< not support */ +#else + kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */ + kUSDHC_TuningSampleClockSel = + USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK, /*!< when std_tuning_en bit is set, this bit is used + select sampleing clock */ +#endif +}; + +/*! @brief ADMA error status flag mask */ +enum _usdhc_adma_error_status_flag +{ + kUSDHC_AdmaLenghMismatchFlag = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, /*!< Length mismatch error */ + kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, /*!< Descriptor error */ +}; + +/*! + * @brief ADMA error state + * + * This state is the detail state when ADMA error has occurred. + */ +typedef enum _usdhc_adma_error_state +{ + kUSDHC_AdmaErrorStateStopDma = 0x00U, /*!< Stop DMA */ + kUSDHC_AdmaErrorStateFetchDescriptor = 0x01U, /*!< Fetch descriptor */ + kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address */ + kUSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */ +} usdhc_adma_error_state_t; + +/*! @brief Force event mask */ +enum _usdhc_force_event +{ + kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */ + kUSDHC_ForceEventAutoCommand12Timeout = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK, /*!< Auto CMD12 timeout error */ + kUSDHC_ForceEventAutoCommand12CrcError = USDHC_FORCE_EVENT_FEVTAC12CE_MASK, /*!< Auto CMD12 CRC error */ + kUSDHC_ForceEventEndBitError = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK, /*!< Auto CMD12 end bit error */ + kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK, /*!< Auto CMD12 index error */ + kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, /*!< Auto CMD12 not issued error */ + kUSDHC_ForceEventCommandTimeout = USDHC_FORCE_EVENT_FEVTCTOE_MASK, /*!< Command timeout error */ + kUSDHC_ForceEventCommandCrcError = USDHC_FORCE_EVENT_FEVTCCE_MASK, /*!< Command CRC error */ + kUSDHC_ForceEventCommandEndBitError = USDHC_FORCE_EVENT_FEVTCEBE_MASK, /*!< Command end bit error */ + kUSDHC_ForceEventCommandIndexError = USDHC_FORCE_EVENT_FEVTCIE_MASK, /*!< Command index error */ + kUSDHC_ForceEventDataTimeout = USDHC_FORCE_EVENT_FEVTDTOE_MASK, /*!< Data timeout error */ + kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK, /*!< Data CRC error */ + kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK, /*!< Data end bit error */ + kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_ForceEventCardInt = USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */ + kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK, /*!< Dma error */ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ForceEventTuningError = 0U, /*!< not support */ +#else + kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */ +#endif + kUSDHC_ForceEventsAll = + (kUSDHC_ForceEventAutoCommand12NotExecuted | kUSDHC_ForceEventAutoCommand12Timeout | + kUSDHC_ForceEventAutoCommand12CrcError | kUSDHC_ForceEventEndBitError | + kUSDHC_ForceEventAutoCommand12IndexError | kUSDHC_ForceEventAutoCommand12NotIssued | + kUSDHC_ForceEventCommandTimeout | kUSDHC_ForceEventCommandCrcError | kUSDHC_ForceEventCommandEndBitError | + kUSDHC_ForceEventCommandIndexError | kUSDHC_ForceEventDataTimeout | kUSDHC_ForceEventDataCrcError | + kUSDHC_ForceEventDataEndBitError | kUSDHC_ForceEventAutoCommand12Error | kUSDHC_ForceEventCardInt | + kUSDHC_ForceEventDmaError | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */ +}; + +/*! @brief Data transfer width */ +typedef enum _usdhc_data_bus_width +{ + kUSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */ + kUSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */ + kUSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */ +} usdhc_data_bus_width_t; + +/*! @brief Endian mode */ +typedef enum _usdhc_endian_mode +{ + kUSDHC_EndianModeBig = 0U, /*!< Big endian mode */ + kUSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kUSDHC_EndianModeLittle = 2U, /*!< Little endian mode */ +} usdhc_endian_mode_t; + +/*! @brief DMA mode */ +typedef enum _usdhc_dma_mode +{ + kUSDHC_DmaModeSimple = 0U, /*!< external DMA */ + kUSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */ + kUSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */ + kUSDHC_ExternalDMA = 3U, /*!< external dma mode select */ +} usdhc_dma_mode_t; + +/*! @brief SDIO control flag mask */ +enum _usdhc_sdio_control_flag +{ + kUSDHC_StopAtBlockGapFlag = USDHC_PROT_CTRL_SABGREQ_MASK, /*!< Stop at block gap */ + kUSDHC_ReadWaitControlFlag = USDHC_PROT_CTRL_RWCTL_MASK, /*!< Read wait control */ + kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK, /*!< Interrupt at block gap */ + kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */ + kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, /*!< Exact block number read */ +}; + +/*! @brief MMC card boot mode */ +typedef enum _usdhc_boot_mode +{ + kUSDHC_BootModeNormal = 0U, /*!< Normal boot */ + kUSDHC_BootModeAlternative = 1U, /*!< Alternative boot */ +} usdhc_boot_mode_t; + +/*! @brief The command type */ +typedef enum _usdhc_card_command_type +{ + kCARD_CommandTypeNormal = 0U, /*!< Normal command */ + kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ + kCARD_CommandTypeResume = 2U, /*!< Resume command */ + kCARD_CommandTypeAbort = 3U, /*!< Abort command */ +} usdhc_card_command_type_t; + +/*! + * @brief The command response type. + * + * Define the command response type from card to host controller. + */ +typedef enum _usdhc_card_response_type +{ + kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ + kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ + kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ + kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ + kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ + kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ + kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ + kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ + kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ + kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ +} usdhc_card_response_type_t; + +/*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_ADDRESS_ALIGN (4096U) +/*! @brief The alignment size for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_LENGTH_ALIGN (4096U) +/*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */ +#define USDHC_ADMA2_ADDRESS_ALIGN (4U) +/*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */ +#define USDHC_ADMA2_LENGTH_ALIGN (4U) + +/* ADMA1 descriptor table + * |------------------------|---------|--------------------------| + * | Address/page field |Reserved | Attribute | + * |------------------------|---------|--------------------------| + * |31 12|11 6|05 |04 |03|02 |01 |00 | + * |------------------------|---------|----|----|--|---|---|-----| + * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| + * |------------------------|---------|----|----|--|---|---|-----| + * + * + * |------|------|-----------------|-------|-------------| + * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | + * |------|------|-----------------|---------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------|-------------| + * | 0 | 1 | Set data length | 0000 | Data Length | + * |------|------|-----------------|-------|-------------| + * | 1 | 0 | Transfer data | Data address | + * |------|------|-----------------|---------------------| + * | 1 | 1 | Link descriptor | Descriptor address | + * |------|------|-----------------|---------------------| + */ +/*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U) +/*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU) +/*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U) +/*! @brief The mask for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK - 3U) + +/*! @brief The mask for the control/status field in ADMA1 descriptor */ +enum _usdhc_adma1_descriptor_flag +{ + kUSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */ + kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */ + kUSDHC_Adma1DescriptorTypeNop = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma1DescriptorTypeTransfer = + (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */ + kUSDHC_Adma1DescriptorTypeLink = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag | + kUSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */ + kUSDHC_Adma1DescriptorTypeSetLength = + (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Set data length */ +}; + +/* ADMA2 descriptor table + * |----------------|---------------|-------------|--------------------------| + * | Address field | Length | Reserved | Attribute | + * |----------------|---------------|-------------|--------------------------| + * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * + * + * | Act2 | Act1 | Comment | Operation | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 1 | Reserved | Read this line and go to next one | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 1 | Link descriptor | Link to another descriptor | + * |------|------|-----------------|-------------------------------------------------------------------| + */ +/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) +/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U) + +/*! @brief ADMA1 descriptor control and status mask */ +enum _usdhc_adma2_descriptor_flag +{ + kUSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */ + kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */ + + kUSDHC_Adma2DescriptorTypeNop = (kUSDHC_Adma2DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma2DescriptorTypeReserved = + (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Reserved */ + kUSDHC_Adma2DescriptorTypeTransfer = + (kUSDHC_Adma2DescriptorActivity2Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */ + kUSDHC_Adma2DescriptorTypeLink = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorActivity2Flag | + kUSDHC_Adma2DescriptorValidFlag), /*!< Link type */ +}; + +/*! @brief dma transfer burst len config. */ +typedef enum _usdhc_burst_len +{ + kUSDHC_EnBurstLenForINCR = 0x01U, /*!< enable burst len for INCR */ + kUSDHC_EnBurstLenForINCR4816 = 0x02U, /*!< enable burst len for INCR4/INCR8/INCR16 */ + kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, /*!< enable burst len for INCR4/8/16 WRAP */ +} usdhc_burst_len_t; + +/*! @brief Defines the adma1 descriptor structure. */ +typedef uint32_t usdhc_adma1_descriptor_t; + +/*! @brief Defines the ADMA2 descriptor structure. */ +typedef struct _usdhc_adma2_descriptor +{ + uint32_t attribute; /*!< The control and status field */ + const uint32_t *address; /*!< The address field */ +} usdhc_adma2_descriptor_t; + +/*! + * @brief USDHC capability information. + * + * Defines a structure to save the capability information of USDHC. + */ +typedef struct _usdhc_capability +{ + uint32_t sdVersion; /*!< support SD card/sdio version */ + uint32_t mmcVersion; /*!< support emmc card version */ + uint32_t maxBlockLength; /*!< Maximum block length united as byte */ + uint32_t maxBlockCount; /*!< Maximum block count can be set one time */ + uint32_t flags; /*!< Capability flags to indicate the support information(_usdhc_capability_flag) */ +} usdhc_capability_t; + +/*! @brief Data structure to configure the MMC boot feature */ +typedef struct _usdhc_boot_config +{ + uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */ + usdhc_boot_mode_t bootMode; /*!< Boot mode selection. */ + uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */ + bool enableBootAck; /*!< Enable or disable boot ACK */ + bool enableBoot; /*!< Enable or disable fast boot */ + bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */ +} usdhc_boot_config_t; + +/*! @brief Data structure to initialize the USDHC */ +typedef struct _usdhc_config +{ + uint32_t dataTimeout; /*!< Data timeout value */ + usdhc_endian_mode_t endianMode; /*!< Endian mode */ + uint8_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */ + uint8_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */ + uint8_t readBurstLen; /*!< Read burst len */ + uint8_t writeBurstLen; /*!< Write burst len */ +} usdhc_config_t; + +/*! + * @brief Card data descriptor + * + * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card + * driver + * want to ignore the error event to read/write all the data not to stop read/write immediately when error event + * happen for example bus testing procedure for MMC card. + */ +typedef struct _usdhc_data +{ + bool enableAutoCommand12; /*!< Enable auto CMD12 */ + bool enableAutoCommand23; /*!< Enable auto CMD23 */ + bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ + bool executeTuning; /*!< execute tuning flag */ + + size_t blockSize; /*!< Block size */ + uint32_t blockCount; /*!< Block count */ + uint32_t *rxData; /*!< Buffer to save data read */ + const uint32_t *txData; /*!< Data buffer to write */ +} usdhc_data_t; + +/*! + * @brief Card command descriptor + * + * Define card command-related attribute. + */ +typedef struct _usdhc_command +{ + uint32_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + usdhc_card_command_type_t type; /*!< Command type */ + usdhc_card_response_type_t responseType; /*!< Command response type */ + uint32_t response[4U]; /*!< Response for this command */ + uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check + the command reponse*/ + uint32_t flags; /*!< Cmd flags */ +} usdhc_command_t; + +/*! @brief ADMA configuration */ +typedef struct _usdhc_adma_config +{ + usdhc_dma_mode_t dmaMode; /*!< DMA mode */ + + usdhc_burst_len_t burstLen; /*!< burst len config */ + + uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */ + uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */ +} usdhc_adma_config_t; + +/*! @brief Transfer state */ +typedef struct _usdhc_transfer +{ + usdhc_data_t *data; /*!< Data to transfer */ + usdhc_command_t *command; /*!< Command to send */ +} usdhc_transfer_t; + +/*! @brief USDHC handle typedef */ +typedef struct _usdhc_handle usdhc_handle_t; + +/*! @brief USDHC callback functions. */ +typedef struct _usdhc_transfer_callback +{ + void (*CardInserted)(void); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ + void (*CardRemoved)(void); /*!< Card removed occurs */ + void (*SdioInterrupt)(void); /*!< SDIO card interrupt occurs */ + void (*SdioBlockGap)(void); /*!< SDIO card stopped at block gap occurs */ + void (*TransferComplete)(USDHC_Type *base, + usdhc_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ + void (*ReTuning)(void); /*!< handle the re-tuning */ +} usdhc_transfer_callback_t; + +/*! + * @brief USDHC handle + * + * Defines the structure to save the USDHC state information and callback function. The detailed interrupt status when + * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in + * usdhc_interrupt_flag_t. + * + * @note All the fields except interruptFlags and transferredWords must be allocated by the user. + */ +struct _usdhc_handle +{ + /* Transfer parameter */ + usdhc_data_t *volatile data; /*!< Data to transfer */ + usdhc_command_t *volatile command; /*!< Command to send */ + + /* Transfer status */ + volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */ + volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */ + + /* Callback functions */ + usdhc_transfer_callback_t callback; /*!< Callback function */ + void *userData; /*!< Parameter for transfer complete callback */ +}; + +/*! @brief USDHC transfer function. */ +typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content); + +/*! @brief USDHC host descriptor */ +typedef struct _usdhc_host +{ + USDHC_Type *base; /*!< USDHC peripheral base address */ + uint32_t sourceClock_Hz; /*!< USDHC source clock frequency united in Hz */ + usdhc_config_t config; /*!< USDHC configuration */ + usdhc_capability_t capability; /*!< USDHC capability information */ + usdhc_transfer_function_t transfer; /*!< USDHC transfer function */ +} usdhc_host_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief USDHC module initialization function. + * + * Configures the USDHC according to the user configuration. + * + * Example: + @code + usdhc_config_t config; + config.cardDetectDat3 = false; + config.endianMode = kUSDHC_EndianModeLittle; + config.dmaMode = kUSDHC_DmaModeAdma2; + config.readWatermarkLevel = 128U; + config.writeWatermarkLevel = 128U; + USDHC_Init(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config USDHC configuration information. + * @retval kStatus_Success Operate successfully. + */ +void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config); + +/*! + * @brief Deinitializes the USDHC. + * + * @param base USDHC peripheral base address. + */ +void USDHC_Deinit(USDHC_Type *base); + +/*! + * @brief Resets the USDHC. + * + * @param base USDHC peripheral base address. + * @param mask The reset type mask(_usdhc_reset). + * @param timeout Timeout for reset. + * @retval true Reset successfully. + * @retval false Reset failed. + */ +bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Sets the ADMA descriptor table configuration. + * + * @param base USDHC peripheral base address. + * @param adma configuration + * @param data Data descriptor + * @param command flags + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + usdhc_data_t *dataConfig, + uint32_t flags); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask Interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN |= mask; +} + +/*! + * @brief Disables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN &= ~mask; +} + +/*! + * @brief Enables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN |= mask; +} + +/*! + * @brief Disables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN &= ~mask; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the current interrupt status. + * + * @param base USDHC peripheral base address. + * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base) +{ + return base->INT_STATUS; +} + +/*! + * @brief Clears a specified interrupt status. + * write 1 clears + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS = mask; +} + +/*! + * @brief Gets the status of auto command 12 error. + * + * @param base USDHC peripheral base address. + * @return Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag). + */ +static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base) +{ + return base->AUTOCMD12_ERR_STATUS; +} + +/*! + * @brief Gets the status of the ADMA error. + * + * @param base USDHC peripheral base address. + * @return ADMA error status flags mask(_usdhc_adma_error_status_flag). + */ +static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base) +{ + return base->ADMA_ERR_STATUS; +} + +/*! + * @brief Gets a present status. + * + * This function gets the present USDHC's status except for an interrupt status and an error status. + * + * @param base USDHC peripheral base address. + * @return Present USDHC's status flags mask(_usdhc_present_status_flag). + */ +static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base) +{ + return base->PRES_STATE; +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Gets the capability information. + * + * @param base USDHC peripheral base address. + * @param capability Structure to save capability information. + */ +void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability); + +/*! + * @brief force the card clock on. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag. + */ +static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } +} + +/*! + * @brief Sets the SD bus clock frequency. + * + * @param base USDHC peripheral base address. + * @param srcClock_Hz USDHC source clock frequency united in Hz. + * @param busClock_Hz SD bus clock frequency united in Hz. + * + * @return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz); + +/*! + * @brief Sends 80 clocks to the card to set it to the active state. + * + * This function must be called each time the card is inserted to ensure that the card can receive the command + * correctly. + * + * @param base USDHC peripheral base address. + * @param timeout Timeout to initialize card. + * @retval true Set card active successfully. + * @retval false Set card active failed. + */ +bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout); + +/*! + * @brief trigger a hardware reset. + * + * @param base USDHC peripheral base address. + * @param 1 or 0 level + */ +static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high) +{ + if (high) + { + base->SYS_CTRL |= USDHC_SYS_CTRL_IPP_RST_N_MASK; + } + else + { + base->SYS_CTRL &= ~USDHC_SYS_CTRL_IPP_RST_N_MASK; + } +} + +/*! + * @brief Sets the data transfer width. + * + * @param base USDHC peripheral base address. + * @param width Data transfer width. + */ +static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width) +{ + base->PROT_CTRL = ((base->PROT_CTRL & ~USDHC_PROT_CTRL_DTW_MASK) | USDHC_PROT_CTRL_DTW(width)); +} + +/*! + * @brief Fills the the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @param data The data about to be sent. + */ +static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data) +{ + base->DATA_BUFF_ACC_PORT = data; +} + +/*! + * @brief Retrieves the data from the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @return The data has been read. + */ +static inline uint32_t USDHC_ReadData(USDHC_Type *base) +{ + return base->DATA_BUFF_ACC_PORT; +} + +/*! +* @brief send command function +* +* @param base USDHC peripheral base address. +* @param command configuration +*/ +void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command); + +/*! + * @brief Enables or disables a wakeup event in low-power mode. + * + * @param base USDHC peripheral base address. + * @param mask Wakeup events mask(_usdhc_wakeup_event). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= USDHC_PROT_CTRL_D3CD_MASK; + } + else + { + base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_DetectCardInsert(USDHC_Type *base) +{ + return (base->PRES_STATE & kUSDHC_CardInsertedFlag) ? true : false; +} + +/*! + * @brief Enables or disables the SDIO card control. + * + * @param base USDHC peripheral base address. + * @param mask SDIO card control flags mask(_usdhc_sdio_control_flag). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} +/*! + * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card. + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_SetContinueRequest(USDHC_Type *base) +{ + base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; +} + +/*! + * @brief Configures the MMC boot feature. + * + * Example: + @code + usdhc_boot_config_t config; + config.ackTimeoutCount = 4; + config.bootMode = kUSDHC_BootModeNormal; + config.blockCount = 5; + config.enableBootAck = true; + config.enableBoot = true; + config.enableAutoStopAtBlockGap = true; + USDHC_SetMmcBootConfig(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config The MMC boot configuration information. + */ +void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config); + +/*! + * @brief Forces generating events according to the given mask. + * + * @param base USDHC peripheral base address. + * @param mask The force events mask(_usdhc_force_event). + */ +static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask) +{ + base->FORCE_EVENT = mask; +} + +/*! + * @brief select the usdhc output voltage + * + * @param base USDHC peripheral base address. + * @param true 1.8V, false 3.0V + */ +static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v) +{ + if (en18v) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_VSELECT_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_VSELECT_MASK; + } +} + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) +#else + /*! + * @brief check the SDR50 mode request tuning bit + * When this bit set, user should call USDHC_StandardTuning function + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base) +{ + return base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK ? true : false; +} + +/*! + * @brief check the request re-tuning bit + * When this bit is set, user should do manual tuning or standard tuning function + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_RequestReTuning(USDHC_Type *base) +{ + return base->PRES_STATE & USDHC_PRES_STATE_RTR_MASK ? true : false; +} + +/*! + * @brief the SDR104 mode auto tuning enable and disable + * This function should call after tuning function execute pass, auto tuning will handle + * by hardware + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } +} + +/*! + * @brief the config the re-tuning timer for mode 1 and mode 3 + * This timer is used for standard tuning auto re-tuning, + * @param base USDHC peripheral base address. + * @param timer counter value + */ +static inline void USDHC_SetRetuningTimer(USDHC_Type *base, uint32_t counter) +{ + base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK; + base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter); +} + +/*! + * @brief the auto tuning enbale for CMD/DATA line + * + * @param base USDHC peripheral base address. + */ +void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base); + +/*! + * @brief manual tuning trigger or abort + * User should handle the tuning cmd and find the boundary of the delay + * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS + * This function should called before USDHC_AdjustDelayforSDR104 function + * @param base USDHC peripheral base address. + * @param tuning enable flag + */ +void USDHC_EnableManualTuning(USDHC_Type *base, bool enable); + +/*! + * @brief the SDR104 mode delay setting adjust + * This function should called after USDHC_ManualTuningForSDR104 + * @param base USDHC peripheral base address. + * @param delay setting configuration + * @retval kStatus_Fail config the delay setting fail + * @retval kStatus_Success config the delay setting success + */ +status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay); + +/*! + * @brief the enable standard tuning function + * The standard tuning window and tuning counter use the default config + * tuning cmd is send by the software, user need to check the tuning result + * can be used for SDR50,SDR104,HS200 mode tuning + * @param base USDHC peripheral base address. + * @param tuning start tap + * @param tuning step + * @param enable/disable flag + */ +void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable); + +/*! + * @brief Get execute std tuning status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK); +} + +/*! + * @brief check std tuning result + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); +} + +/*! + * @brief check tuning error + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base) +{ + return (base->CLK_TUNE_CTRL_STATUS & + (USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)); +} + +#endif +/*! + * @brief the enable/disable DDR mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + * @param nibble position + */ +static inline void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) +{ + if (enable) + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; + base->MIX_CTRL |= (USDHC_MIX_CTRL_DDR_EN_MASK | USDHC_MIX_CTRL_NIBBLE_POS(nibblePos)); + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DDR_EN_MASK; + } +} + +/*! + * @brief the enable/disable HS400 mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +#if FSL_FEATURE_USDHC_HAS_HS400_MODE +static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK; + } +} + +/*! + * @brief reset the strobe DLL + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_ResetStrobeDLL(USDHC_Type *base) +{ + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK; +} + +/*! + * @brief enable/disable the strobe DLL + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } + else + { + base->STROBE_DLL_CTRL &= ~USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } +} + +/*! + * @brief config the strobe DLL delay target and update interval + * + * @param base USDHC peripheral base address. + * @param delay target + * @param update interval + */ +static inline void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval) +{ + base->STROBE_DLL_CTRL &= (USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK); + + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(updateInterval) | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(delayTarget); +} + +/*! + * @brief get the strobe DLL status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base) +{ + return base->STROBE_DLL_STATUS; +} + +#endif + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Transfers the command/data using a blocking method. + * + * This function waits until the command response/data is received or the USDHC encounters an error by polling the + * status + * flag. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * @note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param adma configuration + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_USDHC_SendCommandFailed Send command failed. + * @retval kStatus_USDHC_TransferDataFailed Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer); + +/*! + * @brief Creates the USDHC handle. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle pointer. + * @param callback Structure pointer to contain all callback functions. + * @param userData Callback function parameter. + */ +void USDHC_TransferCreateHandle(USDHC_Type *base, + usdhc_handle_t *handle, + const usdhc_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Transfers the command/data using an interrupt and an asynchronous method. + * + * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an + * error. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * @note Call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param adma configuration. + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_BusyTransferring Busy transferring. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferNonBlocking(USDHC_Type *base, + usdhc_handle_t *handle, + usdhc_adma_config_t *dmaConfig, + usdhc_transfer_t *transfer); + +/*! + * @brief IRQ handler for the USDHC. + * + * This function deals with the IRQs on the given host controller. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + */ +void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif /* _FSL_USDHC_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.c new file mode 100644 index 0000000000000000000000000000000000000000..c7ca61fdfce5dd1481bc2d688504ccb550ac4852 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.c @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_wdog.h" + +#ifdef RT_USING_USERSPACE +#include "imx6ull.h" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of WDOG clock name. */ +static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WDOG_GetInstance(WDOG_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_wdogBases); instance++) + { +#ifdef RT_USING_USERSPACE + if (s_wdogBases[instance] == rt_hw_kernel_virt_to_phys(base)) +#else + if (s_wdogBases[instance] == base) +#endif + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_wdogBases)); + + return instance; +} + +void WDOG_GetDefaultConfig(wdog_config_t *config) +{ + assert(config); + + config->enableWdog = true; + config->workMode.enableWait = false; + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->enableInterrupt = false; + config->softwareResetExtension = false; + config->enablePowerDown = false; + config->softwareAssertion= true; + config->softwareResetSignal = true; + config->timeoutValue = 0xffu; + config->interruptTimeValue = 0x04u; +} + +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) +{ + assert(config); + + uint16_t value = 0u; + + value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) | + WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) | + WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) | + WDOG_WCR_WDA(config->softwareAssertion) | WDOG_WCR_SRS(config->softwareResetSignal); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set configruation */ + CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]); +#endif + base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt); + base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown); + base->WCR = value; +} + +void WDOG_Deinit(WDOG_Type *base) +{ + if (base->WCR & WDOG_WCR_WDBG_MASK) + { + WDOG_Disable(base); + } +} + +uint16_t WDOG_GetStatusFlags(WDOG_Type *base) +{ + uint16_t status_flag = 0U; + + status_flag |= (base->WCR & WDOG_WCR_WDE_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_POR_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_TOUT_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_SFTW_MASK); + status_flag |= (base->WICR & WDOG_WICR_WTIS_MASK); + + return status_flag; +} + +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask) +{ + if (mask & kWDOG_InterruptFlag) + { + base->WICR |= WDOG_WICR_WTIS_MASK; + } +} + +void WDOG_Refresh(WDOG_Type *base) +{ + base->WSR = WDOG_REFRESH_KEY & 0xFFFFU; + base->WSR = (WDOG_REFRESH_KEY >> 16U) & 0xFFFFU; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.h new file mode 100644 index 0000000000000000000000000000000000000000..d2bb5576d3625cc6cff9373ec8b731fecfb4af67 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.h @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_WDOG_H_ +#define _FSL_WDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wdog + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WDOG driver version */ +#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_REFRESH_KEY (0xAAAA5555U) +/*@}*/ + +/*! @brief Defines WDOG work mode. */ +typedef struct _wdog_work_mode +{ + bool enableWait; /*!< continue or suspend WDOG in wait mode */ + bool enableStop; /*!< continue or suspend WDOG in stop mode */ + bool enableDebug; /*!< continue or suspend WDOG in debug mode */ +} wdog_work_mode_t; + +/*! @brief Describes WDOG configuration structure. */ +typedef struct _wdog_config +{ + bool enableWdog; /*!< Enables or disables WDOG */ + wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ + bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ + uint16_t timeoutValue; /*!< Timeout value */ + uint16_t interruptTimeValue; /*!< Interrupt count timeout value */ + bool softwareResetExtension; /*!< software reset extension */ + bool enablePowerDown; /*!< power down enable bit */ + bool softwareAssertion; /*!< software assertion bit*/ + bool softwareResetSignal; /*!< software reset signalbit*/ +} wdog_config_t; + +/*! + * @brief WDOG interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the WDOG interrupt configurations. + */ +enum _wdog_interrupt_enable +{ + kWDOG_InterruptEnable = WDOG_WICR_WIE_MASK /*!< WDOG timeout generates an interrupt before reset*/ +}; + +/*! + * @brief WDOG status flags. + * + * This structure contains the WDOG status flags for use in the WDOG functions. + */ +enum _wdog_status_flags +{ + kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, /*!< Running flag, set when WDOG is enabled*/ + kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, /*!< Power On flag, set when reset is the result of a powerOnReset*/ + kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/ + kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/ + kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK /*!< interrupt flag,whether interrupt has occurred or not*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WDOG Initialization and De-initialization. + * @{ + */ + +/*! + * @brief Initializes the WDOG configuration sturcture. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * @code + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + * @endcode + * + * @param config Pointer to the WDOG configuration structure. + * @see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config); + +/*! + * @brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * + * This is an example. + * @code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0xffU; + * config->interruptTimeValue = 0x04u; + * WDOG_Init(wdog_base,&config); + * @endcode + * + * @param base WDOG peripheral base address + * @param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); + +/*! + * @brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Watchdog Enable bit is a write one once only bit. It is not + * possible to clear this bit by a software write, once the bit is set. + * This bit(WDE) can be set/reset only in debug mode(exception). + */ +void WDOG_Deinit(WDOG_Type *base); + +/*! + * @brief Enables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to enable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write, + * once the bit is set. only debug mode exception. + * @param base WDOG peripheral base address + */ +static inline void WDOG_Enable(WDOG_Type *base) +{ + base->WCR |= WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Disables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to disable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set. + * only debug mode exception + * @param base WDOG peripheral base address + */ +static inline void WDOG_Disable(WDOG_Type *base) +{ + base->WCR &= ~WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Enables the WDOG interrupt. + * + *This bit is a write once only bit. Once the software does a write access to this bit, it will get + *locked and cannot be reprogrammed until the next system reset assertion + * + * @param base WDOG peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined. + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint16_t mask) +{ + base->WICR |= mask; +} + +/*! + * @brief Gets the WDOG all reset status flags. + * + * This function gets all reset status flags. + * + * @code + * uint16_t status; + * status = WDOG_GetStatusFlags (wdog_base); + * @endcode + * @param base WDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ +uint16_t WDOG_GetStatusFlags(WDOG_Type *base); + +/*! + * @brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the interrupt flag. + * @code + * WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag); + * @endcode + * @param base WDOG peripheral base address + * @param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask); + +/*! + * @brief Sets the WDOG timeout value. + * + * This function sets the timeout value. + * This function writes a value into WCR registers. + * The time-out value can be written at any point of time but it is loaded to the counter at the time + * when WDOG is enabled or after the service routine has been performed. + * + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WCR = (base->WCR & ~WDOG_WCR_WT_MASK) | WDOG_WCR_WT(timeoutCount); +} + +/*! + * @brief Sets the WDOG interrupt count timeout value. + * + * This function sets the interrupt count timeout value. + * This function writes a value into WIC registers which are wirte-once. + * This field is write once only. Once the software does a write access to this field, it will get locked + * and cannot be reprogrammed until the next system reset assertion. + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetInterrputTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WICR = (base->WICR & ~WDOG_WICR_WICT_MASK) | WDOG_WICR_WICT(timeoutCount); +} + +/*! + * @brief Disable the WDOG power down enable bit. + * + * This function disable the WDOG power down enable(PDE). + * This function writes a value into WMCR registers which are wirte-once. + * This field is write once only. Once software sets this bit it cannot be reset until the next system reset. + * @param base WDOG peripheral base address + */ +static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base) +{ + base->WMCR &= ~WDOG_WMCR_PDE_MASK; +} + +/*! + * @brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WDOG_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.c new file mode 100644 index 0000000000000000000000000000000000000000..8125c4549947221cf7e3f179d148e7aa288be583 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "event.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get event instance. + * @param eventType The event type + * @return The event instance's pointer. + */ +static volatile uint32_t *EVENT_GetInstance(event_t eventType); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Card detect event. */ +static volatile uint32_t g_eventCardDetect; + +/*! @brief transfer complete event. */ +static volatile uint32_t g_eventTransferComplete; + +/******************************************************************************* + * Code + ******************************************************************************/ +void EVENT_InitTimer(void) +{ +} + +static volatile uint32_t *EVENT_GetInstance(event_t eventType) +{ + volatile uint32_t *event; + + switch (eventType) + { + case kEVENT_TransferComplete: + event = &g_eventTransferComplete; + break; + case kEVENT_CardDetect: + event = &g_eventCardDetect; + break; + default: + event = NULL; + break; + } + + return event; +} + +bool EVENT_Create(event_t eventType) +{ + volatile uint32_t *event = EVENT_GetInstance(eventType); + + if (event) + { + *event = 0; + return true; + } + else + { + return false; + } +} + +bool EVENT_Wait(event_t eventType, uint32_t timeoutMilliseconds) +{ + uint32_t currentTime; + + volatile uint32_t *event = EVENT_GetInstance(eventType); + + if (timeoutMilliseconds && event) + { + currentTime = 0; + do + { + rt_hw_us_delay(1000); + currentTime++; + } while ((*event == 0U) && (currentTime < timeoutMilliseconds)); + *event = 0U; + + return ((currentTime < timeoutMilliseconds) ? true : false); + } + else + { + return false; + } +} + +bool EVENT_Notify(event_t eventType) +{ + volatile uint32_t *event = EVENT_GetInstance(eventType); + + if (event) + { + *event = 1U; + return true; + } + else + { + return false; + } +} + +void EVENT_Delete(event_t eventType) +{ + volatile uint32_t *event = EVENT_GetInstance(eventType); + + if (event) + { + *event = 0U; + } +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.h new file mode 100644 index 0000000000000000000000000000000000000000..e173ddf52f8ea7475e1f1187906ca88a52a7e6b7 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _EVENT_H_ +#define _EVENT_H_ + +#include "fsl_common.h" +#include "bsp_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Event type */ +typedef enum _event +{ + kEVENT_TransferComplete = 0U, /*!< Transfer complete event */ + kEVENT_CardDetect = 1U, /*!< Card detect event */ +} event_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Event Function + * @{ + */ + +/*! + * @brief Initialize timer to implement wait event timeout. + */ +void EVENT_InitTimer(void); + +/* Callback function for SDHC */ + +/*! + * @brief Create event. + * @param eventType The event type + * @retval true Create event successfully. + * @retval false Create event failed. + */ +bool EVENT_Create(event_t eventType); + +/*! + * @brief Wait event. + * + * @param eventType The event type + * @param timeoutMilliseconds Timeout time in milliseconds. + * @retval true Wait event successfully. + * @retval false Wait event failed. + */ +bool EVENT_Wait(event_t eventType, uint32_t timeoutMilliseconds); + +/*! + * @brief Notify event. + * @param eventType The event type + * @retval true Notify event successfully. + * @retval false Notify event failed. + */ +bool EVENT_Notify(event_t eventType); + +/*! + * @brief Delete event. + * @param eventType The event type + */ +void EVENT_Delete(event_t eventType); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _EVENT_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_card.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_card.h new file mode 100644 index 0000000000000000000000000000000000000000..5136b9832996e08376a7972923a5c0a45afae600 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_card.h @@ -0,0 +1,668 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CARD_H_ +#define _FSL_CARD_H_ + +#include "fsl_common.h" +#include "fsl_specification.h" +#include "fsl_host.h" +#include "stdlib.h" +/*! + * @addtogroup CARD + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Driver version. */ +#define FSL_SDMMC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 4U)) /*2.1.4*/ + +/*! @brief Default block size */ +#define FSL_SDMMC_DEFAULT_BLOCK_SIZE (512U) +/*! @brief SDMMC global data buffer size, word unit*/ +#define SDMMC_GLOBAL_BUFFER_SIZE (64U) + +/*! @brief SD/MMC card API's running status. */ +enum _sdmmc_status +{ + kStatus_SDMMC_NotSupportYet = MAKE_STATUS(kStatusGroup_SDMMC, 0U), /*!< Haven't supported */ + kStatus_SDMMC_TransferFailed = MAKE_STATUS(kStatusGroup_SDMMC, 1U), /*!< Send command failed */ + kStatus_SDMMC_SetCardBlockSizeFailed = MAKE_STATUS(kStatusGroup_SDMMC, 2U), /*!< Set block size failed */ + kStatus_SDMMC_HostNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 3U), /*!< Host doesn't support */ + kStatus_SDMMC_CardNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 4U), /*!< Card doesn't support */ + kStatus_SDMMC_AllSendCidFailed = MAKE_STATUS(kStatusGroup_SDMMC, 5U), /*!< Send CID failed */ + kStatus_SDMMC_SendRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 6U), /*!< Send relative address failed */ + kStatus_SDMMC_SendCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 7U), /*!< Send CSD failed */ + kStatus_SDMMC_SelectCardFailed = MAKE_STATUS(kStatusGroup_SDMMC, 8U), /*!< Select card failed */ + kStatus_SDMMC_SendScrFailed = MAKE_STATUS(kStatusGroup_SDMMC, 9U), /*!< Send SCR failed */ + kStatus_SDMMC_SetDataBusWidthFailed = MAKE_STATUS(kStatusGroup_SDMMC, 10U), /*!< Set bus width failed */ + kStatus_SDMMC_GoIdleFailed = MAKE_STATUS(kStatusGroup_SDMMC, 11U), /*!< Go idle failed */ + kStatus_SDMMC_HandShakeOperationConditionFailed = + MAKE_STATUS(kStatusGroup_SDMMC, 12U), /*!< Send Operation Condition failed */ + kStatus_SDMMC_SendApplicationCommandFailed = + MAKE_STATUS(kStatusGroup_SDMMC, 13U), /*!< Send application command failed */ + kStatus_SDMMC_SwitchFailed = MAKE_STATUS(kStatusGroup_SDMMC, 14U), /*!< Switch command failed */ + kStatus_SDMMC_StopTransmissionFailed = MAKE_STATUS(kStatusGroup_SDMMC, 15U), /*!< Stop transmission failed */ + kStatus_SDMMC_WaitWriteCompleteFailed = MAKE_STATUS(kStatusGroup_SDMMC, 16U), /*!< Wait write complete failed */ + kStatus_SDMMC_SetBlockCountFailed = MAKE_STATUS(kStatusGroup_SDMMC, 17U), /*!< Set block count failed */ + kStatus_SDMMC_SetRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 18U), /*!< Set relative address failed */ + kStatus_SDMMC_SwitchBusTimingFailed = MAKE_STATUS(kStatusGroup_SDMMC, 19U), /*!< Switch high speed failed */ + kStatus_SDMMC_SendExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 20U), /*!< Send EXT_CSD failed */ + kStatus_SDMMC_ConfigureBootFailed = MAKE_STATUS(kStatusGroup_SDMMC, 21U), /*!< Configure boot failed */ + kStatus_SDMMC_ConfigureExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 22U), /*!< Configure EXT_CSD failed */ + kStatus_SDMMC_EnableHighCapacityEraseFailed = + MAKE_STATUS(kStatusGroup_SDMMC, 23U), /*!< Enable high capacity erase failed */ + kStatus_SDMMC_SendTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 24U), /*!< Send test pattern failed */ + kStatus_SDMMC_ReceiveTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 25U), /*!< Receive test pattern failed */ + kStatus_SDMMC_SDIO_ResponseError = MAKE_STATUS(kStatusGroup_SDMMC, 26U), /*!< sdio response error */ + kStatus_SDMMC_SDIO_InvalidArgument = + MAKE_STATUS(kStatusGroup_SDMMC, 27U), /*!< sdio invalid argument response error */ + kStatus_SDMMC_SDIO_SendOperationConditionFail = + MAKE_STATUS(kStatusGroup_SDMMC, 28U), /*!< sdio send operation condition fail */ + kStatus_SDMMC_InvalidVoltage = MAKE_STATUS(kStatusGroup_SDMMC, 29U), /*!< invaild voltage */ + kStatus_SDMMC_SDIO_SwitchHighSpeedFail = MAKE_STATUS(kStatusGroup_SDMMC, 30U), /*!< switch to high speed fail */ + kStatus_SDMMC_SDIO_ReadCISFail = MAKE_STATUS(kStatusGroup_SDMMC, 31U), /*!< read CIS fail */ + kStatus_SDMMC_SDIO_InvalidCard = MAKE_STATUS(kStatusGroup_SDMMC, 32U), /*!< invaild SDIO card */ + kStatus_SDMMC_TuningFail = MAKE_STATUS(kStatusGroup_SDMMC, 33U), /*!< tuning fail */ + kStatus_SDMMC_SwitchVoltageFail = MAKE_STATUS(kStatusGroup_SDMMC, 34U), /*!< switch voltage fail*/ + kStatus_SDMMC_ReTuningRequest = MAKE_STATUS(kStatusGroup_SDMMC, 35U), /*!< retuning request */ + kStatus_SDMMC_SetDriverStrengthFail = MAKE_STATUS(kStatusGroup_SDMMC, 36U), /*!< set driver strength fail */ + kStatus_SDMMC_SetPowerClassFail = MAKE_STATUS(kStatusGroup_SDMMC, 37U), /*!< set power class fail */ +}; + +/*! @brief SD card flags */ +enum _sd_card_flag +{ + kSD_SupportHighCapacityFlag = (1U << 1U), /*!< Support high capacity */ + kSD_Support4BitWidthFlag = (1U << 2U), /*!< Support 4-bit data width */ + kSD_SupportSdhcFlag = (1U << 3U), /*!< Card is SDHC */ + kSD_SupportSdxcFlag = (1U << 4U), /*!< Card is SDXC */ + kSD_SupportVoltage180v = (1U << 5U), /*!< card support 1.8v voltage*/ + kSD_SupportSetBlockCountCmd = (1U << 6U), /*!< card support cmd23 flag*/ + kSD_SupportSpeedClassControlCmd = (1U << 7U), /*!< card support speed class control flag */ +}; + +/*! @brief MMC card flags */ +enum _mmc_card_flag +{ + kMMC_SupportHighSpeed26MHZFlag = (1U << 0U), /*!< Support high speed 26MHZ */ + kMMC_SupportHighSpeed52MHZFlag = (1U << 1U), /*!< Support high speed 52MHZ */ + kMMC_SupportHighSpeedDDR52MHZ180V300VFlag = (1 << 2U), /*!< ddr 52MHZ 1.8V or 3.0V */ + kMMC_SupportHighSpeedDDR52MHZ120VFlag = (1 << 3U), /*!< DDR 52MHZ 1.2V */ + kMMC_SupportHS200200MHZ180VFlag = (1 << 4U), /*!< HS200 ,200MHZ,1.8V */ + kMMC_SupportHS200200MHZ120VFlag = (1 << 5U), /*!< HS200, 200MHZ, 1.2V */ + kMMC_SupportHS400DDR200MHZ180VFlag = (1 << 6U), /*!< HS400, DDR, 200MHZ,1.8V */ + kMMC_SupportHS400DDR200MHZ120VFlag = (1 << 7U), /*!< HS400, DDR, 200MHZ,1.2V */ + kMMC_SupportHighCapacityFlag = (1U << 8U), /*!< Support high capacity */ + kMMC_SupportAlternateBootFlag = (1U << 9U), /*!< Support alternate boot */ + kMMC_SupportDDRBootFlag = (1U << 10U), /*!< support DDR boot flag*/ + kMMC_SupportHighSpeedBootFlag = (1U << 11U), /*!< support high speed boot flag*/ + + kMMC_DataBusWidth4BitFlag = (1U << 12U), /*!< current data bus is 4 bit mode*/ + kMMC_DataBusWidth8BitFlag = (1U << 13U), /*!< current data bus is 8 bit mode*/ + kMMC_DataBusWidth1BitFlag = (1U << 14U), /*!< current data bus is 1 bit mode */ + +}; + +/*! @brief card operation voltage */ +typedef enum _card_operation_voltage +{ + kCARD_OperationVoltageNone = 0U, /*!< indicate current voltage setting is not setting bu suser*/ + kCARD_OperationVoltage330V = 1U, /*!< card operation voltage around 3.3v */ + kCARD_OperationVoltage300V = 2U, /*!< card operation voltage around 3.0v */ + kCARD_OperationVoltage180V = 3U, /*!< card operation voltage around 31.8v */ +} card_operation_voltage_t; + +/*! + * @brief SD card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _sd_card +{ + HOST_CONFIG host; /*!< Host information */ + + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + uint32_t version; /*!< Card version */ + uint32_t flags; /*!< Flags in _sd_card_flag */ + uint32_t rawCid[4U]; /*!< Raw CID content */ + uint32_t rawCsd[4U]; /*!< Raw CSD content */ + uint32_t rawScr[2U]; /*!< Raw CSD content */ + uint32_t ocr; /*!< Raw OCR content */ + sd_cid_t cid; /*!< CID */ + sd_csd_t csd; /*!< CSD */ + sd_scr_t scr; /*!< SCR */ + uint32_t blockCount; /*!< Card total block number */ + uint32_t blockSize; /*!< Card block size */ + sd_timing_mode_t currentTiming; /*!< current timing mode */ + sd_driver_strength_t driverStrength; /*!< driver strength */ + sd_max_current_t maxCurrent; /*!< card current limit */ + card_operation_voltage_t operationVoltage; /*!< card operation voltage */ +} sd_card_t; + +/*! + * @brief SDIO card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _sdio_card +{ + HOST_CONFIG host; /*!< Host information */ + + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + bool memPresentFlag; /*!< indicate if memory present */ + + uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + uint8_t sdVersion; /*!< SD version */ + uint8_t sdioVersion; /*!< SDIO version */ + uint8_t cccrVersioin; /*!< CCCR version */ + uint8_t ioTotalNumber; /*!< total number of IO function */ + uint32_t cccrflags; /*!< Flags in _sd_card_flag */ + uint32_t io0blockSize; /*!< record the io0 block size*/ + uint32_t ocr; /*!< Raw OCR content, only 24bit avalible for SDIO card */ + uint32_t commonCISPointer; /*!< point to common CIS */ + + sdio_fbr_t ioFBR[7U]; /*!< FBR table */ + + sdio_common_cis_t commonCIS; /*!< CIS table */ + sdio_func_cis_t funcCIS[7U]; /*!< function CIS table*/ + +} sdio_card_t; + +/*! + * @brief SD card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _mmc_card +{ + HOST_CONFIG host; /*!< Host information */ + + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + uint32_t busClock_Hz; /*!< MMC bus clock united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + bool enablePreDefinedBlockCount; /*!< Enable PRE-DEFINED block count when read/write */ + uint32_t flags; /*!< Capability flag in _mmc_card_flag */ + uint32_t rawCid[4U]; /*!< Raw CID content */ + uint32_t rawCsd[4U]; /*!< Raw CSD content */ + uint32_t rawExtendedCsd[MMC_EXTENDED_CSD_BYTES / 4U]; /*!< Raw MMC Extended CSD content */ + uint32_t ocr; /*!< Raw OCR content */ + mmc_cid_t cid; /*!< CID */ + mmc_csd_t csd; /*!< CSD */ + mmc_extended_csd_t extendedCsd; /*!< Extended CSD */ + uint32_t blockSize; /*!< Card block size */ + uint32_t userPartitionBlocks; /*!< Card total block number in user partition */ + uint32_t bootPartitionBlocks; /*!< Boot partition size united as block size */ + uint32_t eraseGroupBlocks; /*!< Erase group size united as block size */ + mmc_access_partition_t currentPartition; /*!< Current access partition */ + mmc_voltage_window_t hostVoltageWindowVCCQ; /*!< Host IO voltage window */ + mmc_voltage_window_t hostVoltageWindowVCC; /*!< application must set this value according to board specific */ + mmc_high_speed_timing_t currentTiming; /*!< indicate the current host timing mode*/ + +} mmc_card_t; + +/*! @brief MMC card boot configuration definition. */ +typedef struct _mmc_boot_config +{ + bool enableBootAck; /*!< Enable boot ACK */ + mmc_boot_partition_enable_t bootPartition; /*!< Boot partition */ + bool retainBootBusWidth; /*!< If retain boot bus width */ + mmc_data_bus_width_t bootDataBusWidth; /*!< Boot data bus width */ +} mmc_boot_config_t; + +/* define a function pointer for tuning */ +typedef status_t (*card_send_tuning_func)(void *cardType); + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SDCARD Function + * @{ + */ + +/*! + * @brief Initializes the card on a specific host controller. + * + * This function initializes the card on a specific host controller. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval kStatus_SDMMC_NotSupportYet Card not support. + * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. + * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval kStatus_SDMMC_SendScrFailed Send SCR failed. + * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. + * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_Init(sd_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * This function deinitializes the specific card. + * + * @param card Card descriptor. + */ +void SD_Deinit(sd_card_t *card); + +/*! + * @brief Checks whether the card is write-protected. + * + * This function checks if the card is write-protected via the CSD register. + * + * @param card The specific card. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool SD_CheckReadOnly(sd_card_t *card); + +/*! + * @brief Reads blocks from the specific card. + * + * This function reads blocks from the specific card with default block size defined by the + * SDHC_CARD_DEFAULT_BLOCK_SIZE. + * + * @param card Card descriptor. + * @param buffer The buffer to save the data read from card. + * @param startBlock The start block index. + * @param blockCount The number of blocks to read. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes blocks of data to the specific card. + * + * This function writes blocks to the specific card with default block size 512 bytes. + * + * @param card Card descriptor. + * @param buffer The buffer holding the data to be written to the card. + * @param startBlock The start block index. + * @param blockCount The number of blocks to write. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Erases blocks of the specific card. + * + * This function erases blocks of the specific card with default block size 512 bytes. + * + * @param card Card descriptor. + * @param startBlock The start block index. + * @param blockCount The number of blocks to erase. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); + +/* @} */ + +/*! + * @name MMCCARD Function + * @{ + */ + +/*! + * @brief Initializes the MMC card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval kStatus_SDMMC_SetRelativeAddressFailed Set relative address failed. + * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval kStatus_SDMMC_SendExtendedCsdFailed Send EXT_CSD failed. + * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. + * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_Init(mmc_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * @param card Card descriptor. + */ + +void MMC_Deinit(mmc_card_t *card); + +/*! + * @brief Checks if the card is read-only. + * + * @param card Card descriptor. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool MMC_CheckReadOnly(mmc_card_t *card); + +/*! + * @brief Reads data blocks from the card. + * + * @param card Card descriptor. + * @param buffer The buffer to save data. + * @param startBlock The start block index. + * @param blockCount The number of blocks to read. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes data blocks to the card. + * + * @param card Card descriptor. + * @param buffer The buffer to save data blocks. + * @param startBlock Start block number to write. + * @param blockCount Block count. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Erases groups of the card. + * + * Erase group is the smallest erase unit in MMC card. The erase range is [startGroup, endGroup]. + * + * @param card Card descriptor. + * @param startGroup Start group number. + * @param endGroup End group number. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); + +/*! + * @brief Selects the partition to access. + * + * @param card Card descriptor. + * @param partitionNumber The partition number. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber); + +/*! + * @brief Configures the boot activity of the card. + * + * @param card Card descriptor. + * @param config Boot configuration structure. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. + * @retval kStatus_SDMMC_ConfigureBootFailed Configure boot failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config); + +/*! + * @brief set SDIO card to inactive state + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_CardInActive(sdio_card_t *card); + +/*! + * @brief IO direct write transfer function + * + * @param card Card descriptor. + * @param function IO numner + * @param register address + * @param the data pinter to write + * @param raw flag, indicate read after write or write only + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw); + +/*! + * @brief IO direct read transfer function + * + * @param card Card descriptor. + * @param function IO number + * @param register address + * @param data pointer to read + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data); + +/*! + * @brief IO extended write transfer function + * + * @param card Card descriptor. + * @param function IO number + * @param register address + * @param data buffer to write + * @param data count + * @param write flags + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_SDMMC_SDIO_InvalidArgument + * @retval kStatus_Success + */ +status_t SDIO_IO_Write_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags); +/*! + * @brief IO extended read transfer function + * + * @param card Card descriptor. + * @param function IO number + * @param register address + * @param data buffer to read + * @param data count + * @param write flags + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_SDMMC_SDIO_InvalidArgument + * @retval kStatus_Success + */ +status_t SDIO_IO_Read_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags); +/*! + * @brief get SDIO card capability + * + * @param card Card descriptor. + * @param function IO number + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func); + +/*! + * @brief set SDIO card block size + * + * @param card Card descriptor. + * @param function io number + * @param block size + * @retval kStatus_SDMMC_SetCardBlockSizeFailed + * @retval kStatus_SDMMC_SDIO_InvalidArgument + * @retval kStatus_Success + */ +status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize); + +/*! + * @brief set SDIO card reset + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_CardReset(sdio_card_t *card); + +/*! + * @brief set SDIO card data bus width + * + * @param card Card descriptor. + * @param data bus width + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth); + +/*! + * @brief switch the card to high speed + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail + * @retval kStatus_Success + */ +status_t SDIO_SwitchToHighSpeed(sdio_card_t *card); + +/*! + * @brief read SDIO card CIS for each function + * + * @param card Card descriptor. + * @param function io number + * @param tuple code list + * @param tuple code number + * @retval kStatus_SDMMC_SDIO_ReadCISFail + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum); + +/*! + * @brief SDIO card init function + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_GoIdleFailed + * @retval kStatus_SDMMC_HandShakeOperationConditionFailed + * @retval kStatus_SDMMC_SDIO_InvalidCard + * @retval kStatus_SDMMC_SDIO_InvalidVoltage + * @retval kStatus_SDMMC_SendRelativeAddressFailed + * @retval kStatus_SDMMC_SelectCardFailed + * @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail + * @retval kStatus_SDMMC_SDIO_ReadCISFail + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_Init(sdio_card_t *card); + +/*! + * @brief enable IO interrupt + * + * @param card Card descriptor. + * @param function IO number + * @param enable/disable flag + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable); + +/*! + * @brief enable IO and wait IO ready + * + * @param card Card descriptor. + * @param function IO number + * @param enable/disable flag + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable); + +/*! + * @brief select IO + * + * @param card Card descriptor. + * @param function IO number + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func); + +/*! + * @brief Abort IO transfer + * + * @param card Card descriptor. + * @param function IO number + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func); + +/*! + * @brief SDIO card deinit + * + * @param card Card descriptor. + */ +void SDIO_DeInit(sdio_card_t *card); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* _FSL_CARD_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.c new file mode 100644 index 0000000000000000000000000000000000000000..aa2e2d3ceb84806bc9688fd795c6f213a9931f1e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_host.h" +#include "fsl_gpio.h" +#include "event.h" +#ifdef BOARD_USDHC_CD_PORT_BASE +#include "fsl_port.h" +#endif +/******************************************************************************* +* Definitions +******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief host controller error recovery. + * @param host base address. + */ +static void Host_ErrorRecovery(HOST_TYPE *hostBase); +/******************************************************************************* + * Variables + ******************************************************************************/ +/* DMA descriptor should allocate at non-cached memory */ +AT_NONCACHEABLE_SECTION_ALIGN(uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS], USDHC_ADMA2_ADDR_ALIGN); +extern volatile uint32_t g_timeMilliseconds; +static volatile bool g_sdInsertedFlag; +/******************************************************************************* + * Code + ******************************************************************************/ +static void DetectCardByGpio(void) +{ + g_sdInsertedFlag = true; //always return linked status! +} + +/* Card detect. */ +status_t CardInsertDetect(HOST_TYPE *hostBase) +{ + return kStatus_Success; //always return linked status! +} + +/* Card detect pin port interrupt handler. */ +void HOST_CARD_DETECT_INTERRUPT_HANDLER(void) +{ + if (HOST_CARD_DETECT_INTERRUPT_STATUS() & (1U << BOARD_USDHC_CD_GPIO_PIN)) + { + DetectCardByGpio(); + } + /* Clear interrupt flag.*/ + HOST_CARD_DETECT_INTERRUPT_CLEAR(~0U); + EVENT_Notify(kEVENT_CardDetect); +} + +/* User defined transfer function. */ +static status_t USDHC_TransferFunction(USDHC_Type *base, usdhc_transfer_t *content) +{ + usdhc_adma_config_t dmaConfig; + status_t error = kStatus_Success; + + if (content->data != NULL) + { + memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t)); + /* config adma */ + dmaConfig.dmaMode = USDHC_DMA_MODE; + dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR; + dmaConfig.admaTable = g_usdhcAdma2Table; + dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS; + } + + error = USDHC_TransferBlocking(base, &dmaConfig, content); + + if (error == kStatus_Fail) + { + /* host error recovery */ + Host_ErrorRecovery(base); + } + + return error; +} + +static void Host_ErrorRecovery(HOST_TYPE *hostBase) +{ + uint32_t status = 0U; + /* get host present status */ + status = USDHC_GetPresentStatusFlags(hostBase); + /* check command inhibit status flag */ + if ((status & kUSDHC_CommandInhibitFlag) != 0U) + { + /* reset command line */ + USDHC_Reset(hostBase, kUSDHC_ResetCommand, 100U); + } + /* check data inhibit status flag */ + if ((status & kUSDHC_DataInhibitFlag) != 0U) + { + /* reset data line */ + USDHC_Reset(hostBase, kUSDHC_ResetData, 100U); + } +} + +status_t HOST_Init(void *host) +{ + usdhc_host_t *usdhcHost = (usdhc_host_t *)host; + + /* init card power control */ + HOST_INIT_SD_POWER(); + HOST_INIT_MMC_POWER(); + + /* Initializes SDHC. */ + usdhcHost->config.dataTimeout = USDHC_DATA_TIMEOUT; + usdhcHost->config.endianMode = USDHC_ENDIAN_MODE; + usdhcHost->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL; + usdhcHost->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL; + usdhcHost->config.readBurstLen = USDHC_READ_BURST_LEN; + usdhcHost->config.writeBurstLen = USDHC_WRITE_BURST_LEN; + + USDHC_Init(usdhcHost->base, &(usdhcHost->config)); + + /* Define transfer function. */ + usdhcHost->transfer = USDHC_TransferFunction; + /* event init timer */ + EVENT_InitTimer(); + + return kStatus_Success; +} + +void HOST_Reset(HOST_TYPE *hostBase) +{ + /* voltage switch to normal but not 1.8V */ + HOST_SWITCH_VOLTAGE180V(hostBase, false); + /* Disable DDR mode */ + HOST_ENABLE_DDR_MODE(hostBase, false); + /* disable tuning */ + HOST_EXECUTE_STANDARD_TUNING_ENABLE(hostBase, false); + /* Disable HS400 mode */ + HOST_ENABLE_HS400_MODE(hostBase, false); + /* Disable DLL */ + HOST_ENABLE_STROBE_DLL(hostBase, false); +} + +void HOST_Deinit(void *host) +{ + usdhc_host_t *usdhcHost = (usdhc_host_t *)host; + USDHC_Deinit(usdhcHost->base); +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.h new file mode 100644 index 0000000000000000000000000000000000000000..7d5350ed9cc5029a963deb710716835a7a80dfb6 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.h @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_HOST_H +#define _FSL_HOST_H + +#include "fsl_common.h" +#include "usdhc_config.h" +#if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U +#include "fsl_sdhc.h" +#elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U +#include "fsl_sdif.h" +#elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U +#include "fsl_usdhc.h" +#if (FSL_FEATURE_SOC_IOMUXC_COUNT != 0U) +#include "fsl_iomuxc.h" +#else +#include "fsl_port.h" +#endif +#endif + +/*! + * @addtogroup CARD + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* add cache line size align */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#if defined(FSL_FEATURE_L2DCACHE_LINESIZE_BYTE) +#define SDMMC_DATA_BUFFER_ALIGN_CAHCE MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2DCACHE_LINESIZE_BYTE) +#else +#define SDMMC_DATA_BUFFER_ALIGN_CAHCE FSL_FEATURE_L1DCACHE_LINESIZE_BYTE +#endif +#else +#define SDMMC_DATA_BUFFER_ALIGN_CAHCE 1 +#endif +#else +#define SDMMC_DATA_BUFFER_ALIGN_CAHCE 1 +#endif + +#define HOST_NOT_SUPPORT 0U /*!< use this define to indicate the host not support feature*/ +#define HOST_SUPPORT 1U /*!< use this define to indicate the host support feature*/ +/* select host */ +#if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U + +/* SDR104 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#else +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#endif +/* HS200 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#else +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#endif +/* HS400 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ +#define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ /* host do not support HS400 */ +#else +#define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 +#endif + +/*define host baseaddr ,clk freq, IRQ number*/ +#define MMC_HOST_BASEADDR BOARD_SDHC_BASEADDR +#define MMC_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ +#define MMC_HOST_IRQ BOARD_SDHC_IRQ +#define SD_HOST_BASEADDR BOARD_SDHC_BASEADDR +#define SD_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ +#define SD_HOST_IRQ BOARD_SDHC_IRQ + +/* define for card bus speed/strength cnofig */ +#define CARD_BUS_FREQ_50MHZ (0U) +#define CARD_BUS_FREQ_100MHZ0 (0U) +#define CARD_BUS_FREQ_100MHZ1 (0U) +#define CARD_BUS_FREQ_200MHZ (0U) + +#define CARD_BUS_STRENGTH_0 (0U) +#define CARD_BUS_STRENGTH_1 (0U) +#define CARD_BUS_STRENGTH_2 (0U) +#define CARD_BUS_STRENGTH_3 (0U) +#define CARD_BUS_STRENGTH_4 (0U) +#define CARD_BUS_STRENGTH_5 (0U) +#define CARD_BUS_STRENGTH_6 (0U) +#define CARD_BUS_STRENGTH_7 (0U) + +#define HOST_TYPE SDHC_Type +#define HOST_CONFIG sdhc_host_t +#define HOST_TRANSFER sdhc_transfer_t +#define HOST_COMMAND sdhc_command_t +#define HOST_DATA sdhc_data_t +#define HOST_BUS_WIDTH_TYPE sdhc_data_bus_width_t +#define HOST_CAPABILITY sdhc_capability_t + +#define CARD_DATA0_STATUS_MASK kSDHC_Data0LineLevelFlag +#define CARD_DATA0_NOT_BUSY kSDHC_Data0LineLevelFlag +#define CARD_DATA1_STATUS_MASK kSDHC_Data1LineLevelFlag +#define CARD_DATA2_STATUS_MASK kSDHC_Data2LineLevelFlag +#define CARD_DATA3_STATUS_MASK kSDHC_Data3LineLevelFlag + +#define kHOST_DATABUSWIDTH1BIT kSDHC_DataBusWidth1Bit /*!< 1-bit mode */ +#define kHOST_DATABUSWIDTH4BIT kSDHC_DataBusWidth4Bit /*!< 4-bit mode */ +#define kHOST_DATABUSWIDTH8BIT kSDHC_DataBusWidth8Bit /*!< 8-bit mode */ + +#define HOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ +#define HOST_TUINIG_STEP (1U) /*!< standard tuning step */ +#define HOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ +#define HOST_TUNING_DELAY_MAX (0x7FU) +#define HOST_RETUNING_REQUEST (1U) +#define HOST_TUNING_ERROR (2U) + +/* function pointer define */ +#define HOST_TRANSFER_FUNCTION sdhc_transfer_function_t +#define GET_HOST_CAPABILITY(base, capability) (SDHC_GetCapability(base, capability)) +#define GET_HOST_STATUS(base) (SDHC_GetPresentStatusFlags(base)) +#define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) +#define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDHC_SetDataBusWidth(base, busWidth)) +#define HOST_SEND_CARD_ACTIVE(base, timeout) (SDHC_SetCardActive(base, timeout)) +#define HOST_SWITCH_VOLTAGE180V(base, enable18v) +#define HOST_SWITCH_VOLTAGE120V(base, enable12v) +#define HOST_CONFIG_IO_STRENGTH(speed, strength) +#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) +#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) +#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) +#define HOST_CONFIG_SD_IO(speed, strength) +#define HOST_CONFIG_MMC_IO(speed, strength) +#define HOST_ENABLE_DDR_MODE(base, flag) +#define HOST_FORCE_SDCLOCK_ON(base, enable) +#define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) +#define HOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) +#define HOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) +#define HOST_ENABLE_CARD_CLOCK(base, enable) (SDHC_EnableSdClock(base, enable)) +#define HOST_RESET_TUNING(base, timeout) +#define HOST_CHECK_TUNING_ERROR(base) (0U) +#define HOST_ADJUST_TUNING_DELAY(base, delay) +#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) + +#define HOST_ENABLE_HS400_MODE(base, flag) +#define HOST_RESET_STROBE_DLL(base) +#define HOST_ENABLE_STROBE_DLL(base, flag) +#define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval) +#define HOST_GET_STROBE_DLL_STATUS(base) +/* sd card power */ +#define HOST_INIT_SD_POWER() +#define HOST_ENABLE_SD_POWER(enable) +#define HOST_SWITCH_VCC_TO_180V() +#define HOST_SWITCH_VCC_TO_330V() +/* mmc card power */ +#define HOST_INIT_MMC_POWER() +#define HOST_ENABLE_MMC_POWER(enable) +#define HOST_ENABLE_TUNING_FLAG(data) +#define HOST_CARD_DETECT_INTERRUPT_HANDLER BOARD_SDHC_CD_PORT_IRQ_HANDLER +#define HOST_CARD_DETECT_IRQ BOARD_SDHC_CD_PORT_IRQ + +/*! @brief SDHC host capability*/ +enum _host_capability +{ + kHOST_SupportAdma = kSDHC_SupportAdmaFlag, + kHOST_SupportHighSpeed = kSDHC_SupportHighSpeedFlag, + kHOST_SupportDma = kSDHC_SupportDmaFlag, + kHOST_SupportSuspendResume = kSDHC_SupportSuspendResumeFlag, + kHOST_SupportV330 = kSDHC_SupportV330Flag, + kHOST_SupportV300 = HOST_NOT_SUPPORT, + kHOST_SupportV180 = HOST_NOT_SUPPORT, + kHOST_SupportV120 = HOST_NOT_SUPPORT, + kHOST_Support4BitBusWidth = kSDHC_Support4BitFlag, + kHOST_Support8BitBusWidth = kSDHC_Support8BitFlag, + kHOST_SupportDDR50 = HOST_NOT_SUPPORT, + kHOST_SupportSDR104 = HOST_NOT_SUPPORT, + kHOST_SupportSDR50 = HOST_NOT_SUPPORT, + kHOST_SupportHS200 = HOST_NOT_SUPPORT, + kHOST_SupportHS400 = HOST_NOT_SUPPORT, + +}; + +/* Endian mode. */ +#define SDHC_ENDIAN_MODE kSDHC_EndianModeLittle + +/* DMA mode */ +#define SDHC_DMA_MODE kSDHC_DmaModeAdma2 +/* address align */ +#define HOST_DMA_BUFFER_ADDR_ALIGN (SDHC_ADMA2_ADDRESS_ALIGN) + +/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ +#define SDHC_READ_WATERMARK_LEVEL (0x80U) +#define SDHC_WRITE_WATERMARK_LEVEL (0x80U) + +/* ADMA table length united as word. + * + * SD card driver can't support ADMA1 transfer mode currently. + * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. + * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. + */ +#define SDHC_ADMA_TABLE_WORDS (8U) + +#elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U + +/* SDR104 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#else +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#endif +/* HS200 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#else +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#endif +/* HS400 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ +#define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ /* host do not support HS400 */ +#else +#define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 +#endif + +/*define host baseaddr ,clk freq, IRQ number*/ +#define MMC_HOST_BASEADDR BOARD_SDIF_BASEADDR +#define MMC_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ +#define MMC_HOST_IRQ BOARD_SDIF_IRQ +#define SD_HOST_BASEADDR BOARD_SDIF_BASEADDR +#define SD_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ +#define SD_HOST_IRQ BOARD_SDIF_IRQ + +/* define for card bus speed/strength cnofig */ +#define CARD_BUS_FREQ_50MHZ (0U) +#define CARD_BUS_FREQ_100MHZ0 (0U) +#define CARD_BUS_FREQ_100MHZ1 (0U) +#define CARD_BUS_FREQ_200MHZ (0U) + +#define CARD_BUS_STRENGTH_0 (0U) +#define CARD_BUS_STRENGTH_1 (0U) +#define CARD_BUS_STRENGTH_2 (0U) +#define CARD_BUS_STRENGTH_3 (0U) +#define CARD_BUS_STRENGTH_4 (0U) +#define CARD_BUS_STRENGTH_5 (0U) +#define CARD_BUS_STRENGTH_6 (0U) +#define CARD_BUS_STRENGTH_7 (0U) + +#define HOST_TYPE SDIF_Type +#define HOST_CONFIG sdif_host_t +#define HOST_TRANSFER sdif_transfer_t +#define HOST_COMMAND sdif_command_t +#define HOST_DATA sdif_data_t +#define HOST_BUS_WIDTH_TYPE sdif_bus_width_t +#define HOST_CAPABILITY sdif_capability_t + +#define CARD_DATA0_STATUS_MASK SDIF_STATUS_DATA_BUSY_MASK +#define CARD_DATA0_NOT_BUSY 0U + +#define CARD_DATA1_STATUS_MASK (0U) +#define CARD_DATA2_STATUS_MASK (0U) +#define CARD_DATA3_STATUS_MASK (0U) + +#define kHOST_DATABUSWIDTH1BIT kSDIF_Bus1BitWidth /*!< 1-bit mode */ +#define kHOST_DATABUSWIDTH4BIT kSDIF_Bus4BitWidth /*!< 4-bit mode */ +#define kHOST_DATABUSWIDTH8BIT kSDIF_Bus8BitWidth /*!< 8-bit mode */ + +#define HOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ +#define HOST_TUINIG_STEP (1U) /*!< standard tuning step */ +#define HOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ +#define HOST_TUNING_DELAY_MAX (0x7FU) +#define HOST_RETUNING_REQUEST (1U) +#define HOST_TUNING_ERROR (2U) +/* function pointer define */ +#define HOST_TRANSFER_FUNCTION sdif_transfer_function_t +#define GET_HOST_CAPABILITY(base, capability) (SDIF_GetCapability(base, capability)) +#define GET_HOST_STATUS(base) (SDIF_GetControllerStatus(base)) +#define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDIF_SetCardClock(base, sourceClock_HZ, busClock_HZ)) +#define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDIF_SetCardBusWidth(base, busWidth)) +#define HOST_SEND_CARD_ACTIVE(base, timeout) (SDIF_SendCardActive(base, timeout)) +#define HOST_SWITCH_VOLTAGE180V(base, enable18v) +#define HOST_SWITCH_VOLTAGE120V(base, enable12v) +#define HOST_CONFIG_IO_STRENGTH(speed, strength) +#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) +#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) +#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) +#define HOST_CONFIG_SD_IO(speed, strength) +#define HOST_CONFIG_MMC_IO(speed, strength) +#define HOST_ENABLE_DDR_MODE(base, flag) +#define HOST_FORCE_SDCLOCK_ON(base, enable) +#define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) +#define HOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) +#define HOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) +#define HOST_ENABLE_CARD_CLOCK(base, enable) (SDIF_EnableCardClock(base, enable)) +#define HOST_RESET_TUNING(base, timeout) +#define HOST_CHECK_TUNING_ERROR(base) (0U) +#define HOST_ADJUST_TUNING_DELAY(base, delay) +#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) + +#define HOST_ENABLE_HS400_MODE(base, flag) +#define HOST_RESET_STROBE_DLL(base) +#define HOST_ENABLE_STROBE_DLL(base, flag) +#define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval) +#define HOST_GET_STROBE_DLL_STATUS(base) +/* sd card power */ +#define HOST_INIT_SD_POWER() +#define HOST_ENABLE_SD_POWER(enable) +#define HOST_SWITCH_VCC_TO_180V() +#define HOST_SWITCH_VCC_TO_330V() +/* mmc card power */ +#define HOST_INIT_MMC_POWER() +#define HOST_ENABLE_MMC_POWER(enable) +#define HOST_ENABLE_TUNING_FLAG(data) +/*! @brief SDIF host capability*/ +enum _host_capability +{ + kHOST_SupportHighSpeed = kSDIF_SupportHighSpeedFlag, + kHOST_SupportDma = kSDIF_SupportDmaFlag, + kHOST_SupportSuspendResume = kSDIF_SupportSuspendResumeFlag, + kHOST_SupportV330 = kSDIF_SupportV330Flag, + kHOST_SupportV300 = HOST_NOT_SUPPORT, + kHOST_SupportV180 = HOST_NOT_SUPPORT, + kHOST_SupportV120 = HOST_NOT_SUPPORT, + kHOST_Support4BitBusWidth = kSDIF_Support4BitFlag, + kHOST_Support8BitBusWidth = HOST_NOT_SUPPORT, /* mask the 8 bit here,user can change depend on your board */ + kHOST_SupportDDR50 = HOST_NOT_SUPPORT, + kHOST_SupportSDR104 = HOST_NOT_SUPPORT, + kHOST_SupportSDR50 = HOST_NOT_SUPPORT, + kHOST_SupportHS200 = HOST_NOT_SUPPORT, + kHOST_SupportHS400 = HOST_NOT_SUPPORT, + +}; + +/*! @brief DMA table length united as word + * One dma table item occupy four words which can transfer maximum 2*8188 bytes in dual DMA mode + * and 8188 bytes in chain mode + * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. + * user need check the DMA descriptor table lenght if bigger enough. + */ +#define SDIF_DMA_TABLE_WORDS (0x40U) +/* address align */ +#define HOST_DMA_BUFFER_ADDR_ALIGN (4U) + +#elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U +/* SDR104 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#define HOST_SUPPORT_SDR104_FREQ BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#else +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#endif +/* HS200 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ +#define HOST_SUPPORT_HS200_FREQ BOARD_SD_HOST_SUPPORT_HS200_FREQ +#else +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#endif +/* HS400 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ +#define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ +#else +#define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 +#endif + +/*define host baseaddr ,clk freq, IRQ number*/ +#define MMC_HOST_BASEADDR BOARD_MMC_HOST_BASEADDR +#define MMC_HOST_CLK_FREQ BOARD_MMC_HOST_CLK_FREQ +#define MMC_HOST_IRQ BOARD_MMC_HOST_IRQ +#define SD_HOST_BASEADDR BOARD_SD_HOST_BASEADDR +#define SD_HOST_CLK_FREQ BOARD_SD_HOST_CLK_FREQ +#define SD_HOST_IRQ BOARD_SD_HOST_IRQ + +#define HOST_TYPE USDHC_Type +#define HOST_CONFIG usdhc_host_t +#define HOST_TRANSFER usdhc_transfer_t +#define HOST_COMMAND usdhc_command_t +#define HOST_DATA usdhc_data_t + +#define CARD_DATA0_STATUS_MASK kUSDHC_Data0LineLevelFlag +#define CARD_DATA1_STATUS_MASK kUSDHC_Data1LineLevelFlag +#define CARD_DATA2_STATUS_MASK kUSDHC_Data2LineLevelFlag +#define CARD_DATA3_STATUS_MASK kUSDHC_Data3LineLevelFlag +#define CARD_DATA0_NOT_BUSY kUSDHC_Data0LineLevelFlag + +#define HOST_BUS_WIDTH_TYPE usdhc_data_bus_width_t +#define HOST_CAPABILITY usdhc_capability_t + +#define kHOST_DATABUSWIDTH1BIT kUSDHC_DataBusWidth1Bit /*!< 1-bit mode */ +#define kHOST_DATABUSWIDTH4BIT kUSDHC_DataBusWidth4Bit /*!< 4-bit mode */ +#define kHOST_DATABUSWIDTH8BIT kUSDHC_DataBusWidth8Bit /*!< 8-bit mode */ + +#define HOST_STANDARD_TUNING_START (10U) /*!< standard tuning start point */ +#define HOST_TUINIG_STEP (2U) /*!< standard tuning step */ +#define HOST_RETUNING_TIMER_COUNT (0U) /*!< Re-tuning timer */ +#define HOST_TUNING_DELAY_MAX (0x7FU) +#define HOST_RETUNING_REQUEST kStatus_USDHC_ReTuningRequest +#define HOST_TUNING_ERROR kStatus_USDHC_TuningError +/* define for card bus speed/strength cnofig */ +#define CARD_BUS_FREQ_50MHZ (0U) +#define CARD_BUS_FREQ_100MHZ0 (1U) +#define CARD_BUS_FREQ_100MHZ1 (2U) +#define CARD_BUS_FREQ_200MHZ (3U) + +#define CARD_BUS_STRENGTH_0 (0U) +#define CARD_BUS_STRENGTH_1 (1U) +#define CARD_BUS_STRENGTH_2 (2U) +#define CARD_BUS_STRENGTH_3 (3U) +#define CARD_BUS_STRENGTH_4 (4U) +#define CARD_BUS_STRENGTH_5 (5U) +#define CARD_BUS_STRENGTH_6 (6U) +#define CARD_BUS_STRENGTH_7 (7U) + +#define HOST_STROBE_DLL_DELAY_TARGET (7U) +#define HOST_STROBE_DLL_DELAY_UPDATE_INTERVAL (4U) + +/* function pointer define */ +#define HOST_TRANSFER_FUNCTION usdhc_transfer_function_t +#define GET_HOST_CAPABILITY(base, capability) (USDHC_GetCapability(base, capability)) +#define GET_HOST_STATUS(base) (USDHC_GetPresentStatusFlags(base)) +#define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (USDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) +#define HOST_ENABLE_CARD_CLOCK(base, enable) +#define HOST_FORCE_SDCLOCK_ON(base, enable) (USDHC_ForceClockOn(base, enable)) +#define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (USDHC_SetDataBusWidth(base, busWidth)) +#define HOST_SEND_CARD_ACTIVE(base, timeout) (USDHC_SetCardActive(base, timeout)) +#define HOST_SWITCH_VOLTAGE180V(base, enable18v) (UDSHC_SelectVoltage(base, enable18v)) +#define HOST_SWITCH_VOLTAGE120V(base, enable12v) +#define HOST_CONFIG_SD_IO(speed, strength) BOARD_SD_PIN_CONFIG(speed, strength) +#define HOST_CONFIG_MMC_IO(speed, strength) BOARD_MMC_PIN_CONFIG(speed, strength) +#define HOST_SWITCH_VCC_TO_180V() +#define HOST_SWITCH_VCC_TO_330V() + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) +#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) +#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) +#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) +#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) +#define HOST_CHECK_TUNING_ERROR(base) (0U) +#define HOST_ADJUST_TUNING_DELAY(base, delay) +#else +#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) \ + (USDHC_EnableStandardTuning(base, HOST_STANDARD_TUNING_START, HOST_TUINIG_STEP, flag)) +#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (USDHC_GetExecuteStdTuningStatus(base)) +#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (USDHC_CheckStdTuningResult(base)) +#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) (USDHC_SetRetuningTimer(base, HOST_RETUNING_TIMER_COUNT)) +#define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) (USDHC_EnableManualTuning(base, flag)) +#define HOST_ADJUST_TUNING_DELAY(base, delay) (USDHC_AdjustDelayForManualTuning(base, delay)) +#define HOST_AUTO_TUNING_ENABLE(base, flag) (USDHC_EnableAutoTuning(base, flag)) +#define HOST_CHECK_TUNING_ERROR(base) (USDHC_CheckTuningError(base)) +#endif + +#define HOST_AUTO_TUNING_CONFIG(base) (USDHC_EnableAutoTuningForCmdAndData(base)) +#define HOST_RESET_TUNING(base, timeout) \ + { \ + (USDHC_Reset(base, kUSDHC_ResetTuning | kUSDHC_ResetData | kUSDHC_ResetCommand, timeout)); \ + } + +#define HOST_ENABLE_DDR_MODE(base, flag) (USDHC_EnableDDRMode(base, flag, 1U)) + +#if FSL_FEATURE_USDHC_HAS_HS400_MODE +#define HOST_ENABLE_HS400_MODE(base, flag) (USDHC_EnableHS400Mode(base, flag)) +#define HOST_RESET_STROBE_DLL(base) (USDHC_ResetStrobeDLL(base)) +#define HOST_ENABLE_STROBE_DLL(base, flag) (USDHC_EnableStrobeDLL(base, flag)) +#define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval) (USDHC_ConfigStrobeDLL(base, delay, updateInterval)) +#define HOST_GET_STROBE_DLL_STATUS (base)(USDHC_GetStrobeDLLStatus(base)) +#else +#define HOST_ENABLE_HS400_MODE(base, flag) +#define HOST_RESET_STROBE_DLL(base) +#define HOST_ENABLE_STROBE_DLL(base, flag) +#define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval) +#define HOST_GET_STROBE_DLL_STATUS(base) +#endif + +/* sd card power */ +#define HOST_INIT_SD_POWER() BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() +#define HOST_ENABLE_SD_POWER(enable) BOARD_USDHC_SDCARD_POWER_CONTROL(enable) +/* mmc card power */ +#define HOST_INIT_MMC_POWER() BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() +#define HOST_ENABLE_MMC_POWER(enable) BOARD_USDHC_MMCCARD_POWER_CONTROL(enable) +/* sd card detect */ +#define HOST_CARD_DETECT_STATUS() BOARD_USDHC_CD_STATUS() +#define HOST_CARD_DETECT_INIT() BOARD_USDHC_CD_GPIO_INIT() +#define HOST_CARD_DETECT_INTERRUPT_STATUS() BOARD_USDHC_CD_INTERRUPT_STATUS() +#define HOST_CARD_DETECT_INTERRUPT_CLEAR(flag) BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) +#define HOST_CARD_DETECT_INTERRUPT_HANDLER BOARD_USDHC_CD_PORT_IRQ_HANDLER +#define HOST_CARD_DETECT_IRQ BOARD_USDHC_CD_PORT_IRQ +/* define card detect pin voltage level when card inserted */ +#if defined BOARD_USDHC_CARD_INSERT_CD_LEVEL +#define HOST_CARD_INSERT_CD_LEVEL BOARD_USDHC_CARD_INSERT_CD_LEVEL +#else +#define HOST_CARD_INSERT_CD_LEVEL (0U) +#endif +#define HOST_ENABLE_TUNING_FLAG(data) (data.executeTuning = true) +/*! @brief USDHC host capability*/ +enum _host_capability +{ + kHOST_SupportAdma = kUSDHC_SupportAdmaFlag, + kHOST_SupportHighSpeed = kUSDHC_SupportHighSpeedFlag, + kHOST_SupportDma = kUSDHC_SupportDmaFlag, + kHOST_SupportSuspendResume = kUSDHC_SupportSuspendResumeFlag, + kHOST_SupportV330 = kUSDHC_SupportV330Flag, /* this define should depend on your board config */ + kHOST_SupportV300 = kUSDHC_SupportV300Flag, /* this define should depend on your board config */ +#if defined(BOARD_SD_SUPPORT_180V) && !BOARD_SD_SUPPORT_180V + kHOST_SupportV180 = HOST_NOT_SUPPORT, /* this define should depend on you board config */ +#else + kHOST_SupportV180 = kUSDHC_SupportV180Flag, /* this define should depend on you board config */ +#endif + kHOST_SupportV120 = HOST_NOT_SUPPORT, + kHOST_Support4BitBusWidth = kUSDHC_Support4BitFlag, +#if defined(BOARD_MMC_SUPPORT_8BIT_BUS) +#if BOARD_MMC_SUPPORT_8BIT_BUS + kHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag, +#else + kHOST_Support8BitBusWidth = HOST_NOT_SUPPORT, +#endif +#else + kHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag, +#endif + kHOST_SupportDDR50 = kUSDHC_SupportDDR50Flag, + kHOST_SupportSDR104 = kUSDHC_SupportSDR104Flag, + kHOST_SupportSDR50 = kUSDHC_SupportSDR50Flag, + kHOST_SupportHS200 = kUSDHC_SupportSDR104Flag, +#if FSL_FEATURE_USDHC_HAS_HS400_MODE + kHOST_SupportHS400 = HOST_SUPPORT +#else + kHOST_SupportHS400 = HOST_NOT_SUPPORT, +#endif +}; + +/* Endian mode. */ +#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle + +/* DMA mode */ +#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2 +/* address align */ +#define HOST_DMA_BUFFER_ADDR_ALIGN (USDHC_ADMA2_ADDRESS_ALIGN) + +/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ +#define USDHC_READ_WATERMARK_LEVEL (0x80U) +#define USDHC_WRITE_WATERMARK_LEVEL (0x80U) + +/* ADMA table length united as word. + * + * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. + * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. + */ +#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ +#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ +#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ +#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ +#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ + +#endif + +/*! @brief host Endian mode +* corresponding to driver define +*/ +enum _host_endian_mode +{ + kHOST_EndianModeBig = 0U, /*!< Big endian mode */ + kHOST_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kHOST_EndianModeLittle = 2U, /*!< Little endian mode */ +}; + +#define EVENT_TIMEOUT_TRANSFER_COMPLETE (1000U) +#define EVENT_TIMEOUT_CARD_DETECT (~0U) + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name adaptor function + * @{ + */ + +/*! + * @brief host not support function, this function is used for host not support feature + * @param void parameter ,used to avoid build warning + * @retval kStatus_Fail ,host do not suppport + */ +static inline status_t HOST_NotSupport(void *parameter) +{ + parameter = parameter; + return kStatus_Success; +} + +/*! + * @brief Detect card insert, only need for SD cases. + * @param hostBase the pointer to host base address + * @retval kStatus_Success detect card insert + * @retval kStatus_Fail card insert event fail + */ +status_t CardInsertDetect(HOST_TYPE *hostBase); + +/*! + * @brief Init host controller. + * @param host the pointer to host structure in card structure. + * @retval kStatus_Success host init success + * @retval kStatus_Fail event fail + */ +status_t HOST_Init(void *host); + +/*! + * @brief reset host controller. + * @param host base address. + */ +void HOST_Reset(HOST_TYPE *hostBase); + +/*! + * @brief Deinit host controller. + * @param host the pointer to host structure in card structure. + */ +void HOST_Deinit(void *host); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sd.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sd.c new file mode 100644 index 0000000000000000000000000000000000000000..8cac2ffc51cf43aab7261cbf24dfbed39c7f3b5f --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sd.c @@ -0,0 +1,1688 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_card.h" +#include "fsl_sdmmc.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Send SELECT_CARD command to set the card to be transfer state or not. + * + * @param card Card descriptor. + * @param isSelected True to set the card into transfer state. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_SelectCard(sd_card_t *card, bool isSelected); + +/*! + * @brief Wait write process complete. + * + * @param card Card descriptor. + * @retval kStatus_Timeout Send command timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_WaitWriteComplete(sd_card_t *card); + +/*! + * @brief Send SEND_APPLICATION_COMMAND command. + * + * @param card Card descriptor. + * @param relativeaddress + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress); + +/*! + * @brief Send GO_IDLE command to set the card to be idle state. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_GoIdle(sd_card_t *card); + +/*! + * @brief Send STOP_TRANSMISSION command after multiple blocks read/write. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_StopTransmission(sd_card_t *card); + +/*! + * @brief Send SET_BLOCK_SIZE command. + * + * @param card Card descriptor. + * @param blockSize Block size. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize); + +/*! + * @brief Send GET_RCA command to get card relative address. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendRca(sd_card_t *card); + +/*! + * @brief Send SWITCH_FUNCTION command to switch the card function group. + * + * @param card Card descriptor. + * @param mode 0 to check function group. 1 to switch function group + * @param group Function group + * @param number Function number in the function group. + * @param status Switch function status. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status); + +/*! + * @brief Decode raw SCR register content in the data blocks. + * + * @param card Card descriptor. + * @param rawScr Raw SCR register content. + */ +static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr); + +/*! + * @brief Send GET_SCR command. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_NotSupportYet Not support yet. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendScr(sd_card_t *card); + +/*! + * @brief Switch the card to be high speed mode. + * + * @param card Card descriptor. + * @param group Group number. + * @param functio Function number. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SwitchFailed Switch failed. + * @retval kStatus_SDMMC_NotSupportYet Not support yet. + * @retval kStatus_Fail Switch failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function); + +/*! + * @brief Send SET_DATA_WIDTH command to set SD bus width. + * + * @param card Card descriptor. + * @param width Data bus width. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width); + +/*! + * @brief Decode raw CSD register content in the data blocks. + * + * @param card Card descriptor. + * @param rawCsd Raw CSD register content. + */ +static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd); + +/*! + * @brief Send SEND_CSD command to get CSD register content from Card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendCsd(sd_card_t *card); + +/*! + * @brief Decode raw CID register content in the data blocks. + * + * @param rawCid raw CID register content. + * @param card Card descriptor. + */ +static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid); + +/*! + * @brief Send GET_CID command to get CID from card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_AllSendCid(sd_card_t *card); + +/*! + * @brief Send SEND_OPERATION_CONDITION command. + * + * This function sends host capacity support information and asks the accessed card to send its operating condition + * register content. + * + * @param card Card descriptor. + * @param argument The argument of the send operation condition ncomamnd. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Timeout Timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument); + +/*! + * @brief Send GET_INTERFACE_CONDITION command to get card interface condition. + * + * This function checks card interface condition, which includes host supply voltage information and asks the card + * whether card supports the specified host voltage. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendInterfaceCondition(sd_card_t *card); + +/*! + * @brief Send switch voltage command + * switch card voltage to 1.8v + * + * @param card Card descriptor. + */ +static status_t SD_SwitchVoltage(sd_card_t *card); + +/*! + * @brief select bus timing + * select card timing + * @param card Card descriptor. + */ +static status_t SD_SelectBusTiming(sd_card_t *card); + +/*! + * @brief select card driver strength + * select card driver strength + * @param card Card descriptor. + * @param driverStrength Driver strength + */ +static status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength); + +/*! + * @brief select max current + * select max operation current + * @param card Card descriptor. + * @param maxCurrent Max current + */ +static status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent); + +/*! + * @brief Read data from specific SD card. + * + * @param card Card descriptor. + * @param buffer Buffer to save data blocks read. + * @param startBlock Card start block number to be read. + * @param blockSize Block size. + * @param blockCount Block count. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief Write data to specific card + * + * @param card Card descriptor. + * @param buffer Buffer to be sent. + * @param startBlock Card start block number to be written. + * @param blockSize Block size. + * @param blockCount Block count. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Write( + sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief Erase data for the given block range. + * + * @param card Card descriptor. + * @param startBlock Card start block number to be erased. + * @param blockCount The block count to be erased. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief card transfer function. + * + * @param card Card descriptor. + * @param content Transfer content. + * @param retry Retry times + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail + */ +static status_t SD_Transfer(sd_card_t *card, HOST_TRANSFER *content, uint32_t retry); + +/*! + * @brief card execute tuning function. + * + * @param card Card descriptor. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail. + * @retval kStatus_SDMMC_TransferFailed transfer fail + */ +static status_t inline SD_ExecuteTuning(sd_card_t *card); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* g_sdmmc statement */ +extern uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CAHCE)]; +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t inline SD_SelectCard(sd_card_t *card, bool isSelected) +{ + assert(card); + + return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); +} + +static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress) +{ + assert(card); + + return SDMMC_SendApplicationCommand(card->host.base, card->host.transfer, relativeAddress); +} + +static status_t inline SD_GoIdle(sd_card_t *card) +{ + assert(card); + + return SDMMC_GoIdle(card->host.base, card->host.transfer); +} + +static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize) +{ + assert(card); + + return SDMMC_SetBlockSize(card->host.base, card->host.transfer, blockSize); +} + +static status_t inline SD_ExecuteTuning(sd_card_t *card) +{ + assert(card); + + return SDMMC_ExecuteTuning(card->host.base, card->host.transfer, kSD_SendTuningBlock, 64U); +} + +static status_t SD_SwitchVoltage(sd_card_t *card) +{ + assert(card); + + return SDMMC_SwitchVoltage(card->host.base, card->host.transfer); +} + +static status_t SD_Transfer(sd_card_t *card, HOST_TRANSFER *content, uint32_t retry) +{ + assert(card->host.transfer); + assert(content); + status_t error; + + do + { + error = card->host.transfer(card->host.base, content); + if (((error == HOST_RETUNING_REQUEST) || (error == HOST_TUNING_ERROR) || + (content->command->response[0U] & kSDMMC_R1ErrorAllFlag)) && + ((card->currentTiming == kSD_TimingSDR104Mode) || (card->currentTiming == kSD_TimingSDR50Mode))) + { + /* tuning error need reset tuning circuit */ + if (error == HOST_TUNING_ERROR) + { + HOST_RESET_TUNING(card->host.base, 100U); + } + + /* execute re-tuning */ + if (SD_ExecuteTuning(card) != kStatus_Success) + { + error = kStatus_SDMMC_TuningFail; + } + else + { + continue; + } + } + else if (error != kStatus_Success) + { + error = kStatus_SDMMC_TransferFailed; + } + + if (retry != 0U) + { + retry--; + } + else + { + break; + } + + } while ((error != kStatus_Success) && (error != kStatus_SDMMC_TuningFail)); + + return error; +} + +static status_t SD_WaitWriteComplete(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SendStatus; + command.argument = card->relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + do + { + content.command = &command; + content.data = 0U; + if (kStatus_Success != SD_Transfer(card, &content, 2U)) + { + return kStatus_SDMMC_TransferFailed; + } + + if ((command.response[0U] & kSDMMC_R1ReadyForDataFlag) && + (SDMMC_R1_CURRENT_STATE(command.response[0U]) != kSDMMC_R1StateProgram)) + { + break; + } + } while (true); + + return kStatus_Success; +} + +static status_t SD_StopTransmission(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_StopTransmission; + command.argument = 0U; + command.type = kCARD_CommandTypeAbort; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = 0U; + if (kStatus_Success != SD_Transfer(card, &content, 1U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t SD_SendRca(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSD_SendRelativeAddress; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR6; + + content.command = &command; + content.data = NULL; + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + card->relativeAddress = (command.response[0U] >> 16U); + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status) +{ + assert(card); + assert(status); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + HOST_DATA data = {0}; + + command.index = kSD_Switch; + command.argument = (mode << 31U | 0x00FFFFFFU); + command.argument &= ~((uint32_t)(0xFU) << (group * 4U)); + command.argument |= (number << (group * 4U)); + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = 64U; + data.blockCount = 1U; + data.rxData = status; + + if (kStatus_Success != SD_SetBlockSize(card, data.blockSize)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + content.command = &command; + content.data = &data; + if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || + ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr) +{ + assert(card); + assert(rawScr); + + sd_scr_t *scr; + + scr = &(card->scr); + scr->scrStructure = (uint8_t)((rawScr[0U] & 0xF0000000U) >> 28U); + scr->sdSpecification = (uint8_t)((rawScr[0U] & 0xF000000U) >> 24U); + if ((uint8_t)((rawScr[0U] & 0x800000U) >> 23U)) + { + scr->flags |= kSD_ScrDataStatusAfterErase; + } + scr->sdSecurity = (uint8_t)((rawScr[0U] & 0x700000U) >> 20U); + scr->sdBusWidths = (uint8_t)((rawScr[0U] & 0xF0000U) >> 16U); + if ((uint8_t)((rawScr[0U] & 0x8000U) >> 15U)) + { + scr->flags |= kSD_ScrSdSpecification3; + } + scr->extendedSecurity = (uint8_t)((rawScr[0U] & 0x7800U) >> 10U); + scr->commandSupport = (uint8_t)(rawScr[0U] & 0x3U); + scr->reservedForManufacturer = rawScr[1U]; + /* Get specification version. */ + switch (scr->sdSpecification) + { + case 0U: + card->version = kSD_SpecificationVersion1_0; + break; + case 1U: + card->version = kSD_SpecificationVersion1_1; + break; + case 2U: + card->version = kSD_SpecificationVersion2_0; + if (card->scr.flags & kSD_ScrSdSpecification3) + { + card->version = kSD_SpecificationVersion3_0; + } + break; + default: + break; + } + if (card->scr.sdBusWidths & 0x4U) + { + card->flags |= kSD_Support4BitWidthFlag; + } + /* speed class control cmd */ + if (card->scr.commandSupport & 0x01U) + { + card->flags |= kSD_SupportSpeedClassControlCmd; + } + /* set block count cmd */ + if (card->scr.commandSupport & 0x02U) + { + card->flags |= kSD_SupportSetBlockCountCmd; + } +} + +static status_t SD_SendScr(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + HOST_DATA data = {0}; + uint32_t *rawScr = g_sdmmc; + + /* memset the global buffer */ + memset(g_sdmmc, 0U, sizeof(g_sdmmc)); + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = kSD_ApplicationSendScr; + command.responseType = kCARD_ResponseTypeR1; + command.argument = 0U; + + data.blockSize = 8U; + data.blockCount = 1U; + data.rxData = rawScr; + + content.data = &data; + content.command = &command; + if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || + ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* SCR register data byte sequence from card is big endian(MSB first). */ + switch (card->host.config.endianMode) + { + case kHOST_EndianModeLittle: + /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in a + word which will cause 4 byte's sequence in a word is not consistent with their original sequence from + card. So the sequence of 4 bytes received in a word should be converted. */ + rawScr[0U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[0U]); + rawScr[1U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[1U]); + break; + case kHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kHOST_EndianModeHalfWordBig: + rawScr[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[0U]); + rawScr[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[1U]); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + memcpy(card->rawScr, rawScr, sizeof(card->rawScr)); + SD_DecodeScr(card, rawScr); + + return kStatus_Success; +} + +static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function) +{ + assert(card); + + uint32_t *functionStatus = g_sdmmc; + uint16_t functionGroupInfo[6U] = {0}; + uint32_t currentFunctionStatus = 0U; + + /* memset the global buffer */ + memset(g_sdmmc, 0, sizeof(g_sdmmc)); + + /* check if card support CMD6 */ + if ((card->version < kSD_SpecificationVersion1_0) || (!(card->csd.cardCommandClass & kSDMMC_CommandClassSwitch))) + { + return kStatus_SDMMC_NotSupportYet; + } + + /* Check if card support high speed mode. */ + if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchCheck, group, function, functionStatus)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Switch function status byte sequence from card is big endian(MSB first). */ + switch (card->host.config.endianMode) + { + case kHOST_EndianModeLittle: + /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in + a word which will cause 4 byte's sequence in a word is not consistent with their original sequence from + card. So the sequence of 4 bytes received in a word should be converted. */ + functionStatus[0U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[0U]); + functionStatus[1U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[1U]); + functionStatus[2U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[2U]); + functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); + break; + case kHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kHOST_EndianModeHalfWordBig: + functionStatus[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[0U]); + functionStatus[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[1U]); + functionStatus[2U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[2U]); + functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + /* -functionStatus[0U]---bit511~bit480; + -functionStatus[1U]---bit479~bit448; + -functionStatus[2U]---bit447~bit416; + -functionStatus[3U]---bit415~bit384; + -functionStatus[4U]---bit383~bit352; + According to the "switch function status[bits 511~0]" return by switch command in mode "check function": + -Check if function 1(high speed) in function group 1 is supported by checking if bit 401 is set; + -check if function 1 is ready and can be switched by checking if bits 379~376 equal value 1; + */ + functionGroupInfo[5U] = (uint16_t)functionStatus[0U]; + functionGroupInfo[4U] = (uint16_t)(functionStatus[1U] >> 16U); + functionGroupInfo[3U] = (uint16_t)(functionStatus[1U]); + functionGroupInfo[2U] = (uint16_t)(functionStatus[2U] >> 16U); + functionGroupInfo[1U] = (uint16_t)(functionStatus[2U]); + functionGroupInfo[0U] = (uint16_t)(functionStatus[3U] >> 16U); + currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); + + /* check if function is support */ + if (((functionGroupInfo[group] & (1 << function)) == 0U) || + ((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) + { + return kStatus_SDMMC_NotSupportYet; + } + + /* Switch to high speed mode. */ + if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchSet, group, function, functionStatus)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Switch function status byte sequence from card is big endian(MSB first). */ + switch (card->host.config.endianMode) + { + case kHOST_EndianModeLittle: + /* In little endian mode is little endian, SD bus byte transferred first is the byte stored in lowest byte + position in a word which will cause 4 byte's sequence in a word is not consistent with their original + sequence from card. So the sequence of 4 bytes received in a word should be converted. */ + functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); + break; + case kHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kHOST_EndianModeHalfWordBig: + functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": + -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; + */ + currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); + + if (((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) + { + return kStatus_SDMMC_SwitchFailed; + } + + return kStatus_Success; +} + +static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = kSD_ApplicationSetBusWdith; + command.responseType = kCARD_ResponseTypeR1; + switch (width) + { + case kSD_DataBusWidth1Bit: + command.argument = 0U; + break; + case kSD_DataBusWidth4Bit: + command.argument = 2U; + break; + default: + return kStatus_InvalidArgument; + } + + content.command = &command; + content.data = NULL; + if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || + ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd) +{ + assert(card); + assert(rawCsd); + + sd_csd_t *csd; + + csd = &(card->csd); + csd->csdStructure = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); + csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); + csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); + csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); + csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); + csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); + if (rawCsd[2U] & 0x8000U) + { + csd->flags |= kSD_CsdReadBlockPartialFlag; + } + if (rawCsd[2U] & 0x4000U) + { + csd->flags |= kSD_CsdReadBlockPartialFlag; + } + if (rawCsd[2U] & 0x2000U) + { + csd->flags |= kSD_CsdReadBlockMisalignFlag; + } + if (rawCsd[2U] & 0x1000U) + { + csd->flags |= kSD_CsdDsrImplementedFlag; + } + switch (csd->csdStructure) + { + case 0: + csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FFU) << 2U); + csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xC0000000U) >> 30U); + csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); + csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x7000000U) >> 24U); + csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0xE00000U) >> 20U); + csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x1C0000U) >> 18U); + csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x38000U) >> 15U); + + /* Get card total block count and block size. */ + card->blockCount = ((csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U)); + card->blockSize = (1U << (csd->readBlockLength)); + if (card->blockSize != FSL_SDMMC_DEFAULT_BLOCK_SIZE) + { + card->blockCount = (card->blockCount * card->blockSize); + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + card->blockCount = (card->blockCount / card->blockSize); + } + break; + case 1: + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + + csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FU) << 16U); + csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xFFFF0000U) >> 16U); + if (csd->deviceSize >= 0xFFFFU) + { + card->flags |= kSD_SupportSdxcFlag; + } + + card->blockCount = ((csd->deviceSize + 1U) * 1024U); + break; + default: + break; + } + if ((uint8_t)((rawCsd[1U] & 0x4000U) >> 14U)) + { + csd->flags |= kSD_CsdEraseBlockEnabledFlag; + } + csd->eraseSectorSize = (uint8_t)((rawCsd[1U] & 0x3F80U) >> 7U); + csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x7FU); + if ((uint8_t)(rawCsd[0U] & 0x80000000U)) + { + csd->flags |= kSD_CsdWriteProtectGroupEnabledFlag; + } + csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); + csd->writeBlockLength = (uint8_t)((rawCsd[0U] & 0x3C00000U) >> 22U); + if ((uint8_t)((rawCsd[0U] & 0x200000U) >> 21U)) + { + csd->flags |= kSD_CsdWriteBlockPartialFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x8000U) >> 15U)) + { + csd->flags |= kSD_CsdFileFormatGroupFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x4000U) >> 14U)) + { + csd->flags |= kSD_CsdCopyFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x2000U) >> 13U)) + { + csd->flags |= kSD_CsdPermanentWriteProtectFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x1000U) >> 12U)) + { + csd->flags |= kSD_CsdTemporaryWriteProtectFlag; + } + csd->fileFormat = (uint8_t)((rawCsd[0U] & 0xC00U) >> 10U); +} + +static status_t SD_SendCsd(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SendCsd; + command.argument = (card->relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + memcpy(card->rawCsd, command.response, sizeof(card->rawCsd)); + /* The response is from bit 127:8 in R2, corrisponding to command.response[3U]:command.response[0U][31U:8]. */ + SD_DecodeCsd(card, command.response); + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid) +{ + assert(card); + assert(rawCid); + + sd_cid_t *cid; + + cid = &(card->cid); + cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); + cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); + + cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); + cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); + cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); + cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); + cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); + + cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); + + cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); + cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); + + cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U); +} + +static status_t SD_AllSendCid(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_AllSendCid; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + memcpy(card->rawCid, command.response, sizeof(card->rawCid)); + SD_DecodeCid(card, command.response); + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + status_t error = kStatus_Fail; + uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; + + command.index = kSD_ApplicationSendOperationCondition; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR3; + + while (i--) + { + if (kStatus_Success != SD_SendApplicationCmd(card, 0U)) + { + continue; + } + + content.command = &command; + content.data = NULL; + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Wait until card exit busy state. */ + if (command.response[0U] & kSD_OcrPowerUpBusyFlag) + { + /* high capacity check */ + if (command.response[0U] & kSD_OcrCardCapacitySupportFlag) + { + card->flags |= kSD_SupportHighCapacityFlag; + } + /* 1.8V support */ + if (command.response[0U] & kSD_OcrSwitch18AcceptFlag) + { + card->flags |= kSD_SupportVoltage180v; + } + error = kStatus_Success; + card->ocr = command.response[0U]; + break; + } + error = kStatus_Timeout; + } + + return error; +} + +static status_t SD_SendInterfaceCondition(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; + status_t error; + + command.index = kSD_SendInterfaceCondition; + command.argument = 0x1AAU; + command.responseType = kCARD_ResponseTypeR7; + + content.command = &command; + content.data = NULL; + do + { + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + error = kStatus_SDMMC_TransferFailed; + } + else + { + if ((command.response[0U] & 0xFFU) != 0xAAU) + { + error = kStatus_SDMMC_CardNotSupport; + } + else + { + error = kStatus_Success; + } + } + } while (--i && (error != kStatus_Success)); + + return error; +} + +static status_t SD_SelectBusTiming(sd_card_t *card) +{ + assert(card); + + status_t error = kStatus_SDMMC_SwitchBusTimingFailed; + + if (card->operationVoltage != kCARD_OperationVoltage180V) + { + /* Switch the card to high speed mode */ + if (card->host.capability.flags & kHOST_SupportHighSpeed) + { + /* group 1, function 1 ->high speed mode*/ + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); + /* If the result isn't "switching to high speed mode(50MHZ) successfully or card doesn't support high speed + * mode". Return failed status. */ + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + } + else if (error == kStatus_SDMMC_NotSupportYet) + { + /* if not support high speed, keep the card work at default mode */ + return kStatus_Success; + } + } + else + { + /* if not support high speed, keep the card work at default mode */ + return kStatus_Success; + } + } + /* card is in UHS_I mode */ + else if ((kHOST_SupportSDR104 != HOST_NOT_SUPPORT) || (kHOST_SupportSDR50 != HOST_NOT_SUPPORT) || + (kHOST_SupportDDR50 != HOST_NOT_SUPPORT)) + { + switch (card->currentTiming) + { + /* if not select timing mode, sdmmc will handle it automatically*/ + case kSD_TimingSDR12DefaultMode: + case kSD_TimingSDR104Mode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR104); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR104Mode; + card->busClock_Hz = + HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, HOST_SUPPORT_SDR104_FREQ); + break; + } + case kSD_TimingDDR50Mode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionDDR50); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingDDR50Mode; + card->busClock_Hz = + HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_100MHZ); + HOST_ENABLE_DDR_MODE(card->host.base, true); + } + break; + case kSD_TimingSDR50Mode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR50); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR50Mode; + card->busClock_Hz = + HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_100MHZ); + } + break; + case kSD_TimingSDR25HighSpeedMode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + } + break; + + default: + break; + } + } + else + { + } + + /* SDR50 and SDR104 mode need tuning */ + if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) + { + /* config IO strength in IOMUX*/ + if (card->currentTiming == kSD_TimingSDR50Mode) + { + HOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_7); + } + else + { + HOST_CONFIG_SD_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); + } + /* execute tuning */ + if (SD_ExecuteTuning(card) != kStatus_Success) + { + return kStatus_SDMMC_TuningFail; + } + } + else if (card->currentTiming == kSD_TimingDDR50Mode) + { + HOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_3); + } + + return error; +} + +static status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength) +{ + assert(card); + + status_t error; + uint32_t strength = driverStrength; + + error = SD_SelectFunction(card, kSD_GroupDriverStrength, strength); + + return error; +} + +static status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent) +{ + assert(card); + + status_t error; + uint32_t current = maxCurrent; + + error = SD_SelectFunction(card, kSD_GroupCurrentLimit, current); + + return error; +} + +static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + assert(blockSize); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + HOST_DATA data = {0}; + status_t error; + + if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || + (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4)) + { + return kStatus_SDMMC_CardNotSupport; + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer. */ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.rxData = (uint32_t *)buffer; + + command.index = kSDMMC_ReadMultipleBlock; + if (data.blockCount == 1U) + { + command.index = kSDMMC_ReadSingleBlock; + } + command.argument = startBlock; + if (!(card->flags & kSD_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = &data; + + error = SD_Transfer(card, &content, 1U); + if (kStatus_Success != error) + { + return error; + } + + /* Send STOP_TRANSMISSION command in multiple block transmission and host's AUTO_COMMAND12 isn't enabled. */ + if ((data.blockCount > 1U) && (!(data.enableAutoCommand12))) + { + if (kStatus_Success != SD_StopTransmission(card)) + { + return kStatus_SDMMC_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +static status_t SD_Write( + sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + assert(blockSize); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + HOST_DATA data = {0}; + status_t error; + + if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || + (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) + { + return kStatus_SDMMC_CardNotSupport; + } + + /* Wait for the card's buffer to be not full to write to improve the write performance. */ + while ((GET_HOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) + { + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.txData = (const uint32_t *)buffer; + + command.index = kSDMMC_WriteMultipleBlock; + if (data.blockCount == 1U) + { + command.index = kSDMMC_WriteSingleBlock; + } + command.argument = startBlock; + if (!(card->flags & kSD_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = &data; + + error = SD_Transfer(card, &content, 1U); + if (kStatus_Success != error) + { + return error; + } + + /* Send STOP_TRANSMISSION command in multiple block transmission and host's AUTO_COMMAND12 isn't enabled. */ + if ((data.blockCount > 1U) && (!(data.enableAutoCommand12))) + { + if (kStatus_Success != SD_StopTransmission(card)) + { + return kStatus_SDMMC_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(blockCount); + + uint32_t eraseBlockStart; + uint32_t eraseBlockEnd; + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + /* Wait for the card's buffer to be not full to write to improve the write performance. */ + while ((GET_HOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) + { + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + eraseBlockStart = startBlock; + eraseBlockEnd = eraseBlockStart + blockCount - 1U; + if (!(card->flags & kSD_SupportHighCapacityFlag)) + { + eraseBlockStart = eraseBlockStart * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + eraseBlockEnd = eraseBlockEnd * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + } + + /* Send ERASE_WRITE_BLOCK_START command to set the start block number to erase. */ + command.index = kSD_EraseWriteBlockStart; + command.argument = eraseBlockStart; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = NULL; + + if (kStatus_Success != SD_Transfer(card, &content, 1U)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Send ERASE_WRITE_BLOCK_END command to set the end block number to erase. */ + command.index = kSD_EraseWriteBlockEnd; + command.argument = eraseBlockEnd; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != SD_Transfer(card, &content, 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Send ERASE command to start erase process. */ + command.index = kSDMMC_Erase; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != SD_Transfer(card, &content, 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SD_Init(sd_card_t *card) +{ + assert(card); + + uint32_t applicationCommand41Argument = 0U; + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + error = HOST_Init(&(card->host)); + if (error != kStatus_Success) + { + return error; + } + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + } + else + { + /* reset the host */ + HOST_Reset(card->host.base); + } + + /*detect card insert*/ + error = CardInsertDetect(card->host.base); + if (error != kStatus_Success) + { + return error; + } + /* reset variables */ + card->flags = 0U; + /* set DATA bus width */ + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH1BIT); + /*set card freq to 400KHZ*/ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); + /* send card active */ + HOST_SEND_CARD_ACTIVE(card->host.base, 100U); + /* Get host capability. */ + GET_HOST_CAPABILITY(card->host.base, &(card->host.capability)); + + /* card go idle */ + if (kStatus_Success != SD_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + + if (kHOST_SupportV330 != HOST_NOT_SUPPORT) + { + applicationCommand41Argument |= (kSD_OcrVdd32_33Flag | kSD_OcrVdd33_34Flag); + card->operationVoltage = kCARD_OperationVoltage330V; + } + else if (kHOST_SupportV300 != HOST_NOT_SUPPORT) + { + applicationCommand41Argument |= kSD_OcrVdd29_30Flag; + card->operationVoltage = kCARD_OperationVoltage330V; + } + + /* allow user select the work voltage, if not select, sdmmc will handle it automatically */ + if (kHOST_SupportV180 != HOST_NOT_SUPPORT) + { + applicationCommand41Argument |= kSD_OcrSwitch18RequestFlag; + } + + /* Check card's supported interface condition. */ + if (kStatus_Success == SD_SendInterfaceCondition(card)) + { + /* SDHC or SDXC card */ + applicationCommand41Argument |= kSD_OcrHostCapacitySupportFlag; + card->flags |= kSD_SupportSdhcFlag; + } + else + { + /* SDSC card */ + if (kStatus_Success != SD_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + } + /* Set card interface condition according to SDHC capability and card's supported interface condition. */ + if (kStatus_Success != SD_ApplicationSendOperationCondition(card, applicationCommand41Argument)) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + /* check if card support 1.8V */ + if ((card->flags & kSD_SupportVoltage180v)) + { + if (kStatus_Success != SD_SwitchVoltage(card)) + { + return kStatus_SDMMC_InvalidVoltage; + } + card->operationVoltage = kCARD_OperationVoltage180V; + } + + /* Initialize card if the card is SD card. */ + if (kStatus_Success != SD_AllSendCid(card)) + { + return kStatus_SDMMC_AllSendCidFailed; + } + if (kStatus_Success != SD_SendRca(card)) + { + return kStatus_SDMMC_SendRelativeAddressFailed; + } + if (kStatus_Success != SD_SendCsd(card)) + { + return kStatus_SDMMC_SendCsdFailed; + } + if (kStatus_Success != SD_SelectCard(card, true)) + { + return kStatus_SDMMC_SelectCardFailed; + } + + if (kStatus_Success != SD_SendScr(card)) + { + return kStatus_SDMMC_SendScrFailed; + } + + /* Set to max frequency in non-high speed mode. */ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); + + /* Set to 4-bit data bus mode. */ + if (((card->host.capability.flags) & kHOST_Support4BitBusWidth) && (card->flags & kSD_Support4BitWidthFlag)) + { + if (kStatus_Success != SD_SetDataBusWidth(card, kSD_DataBusWidth4Bit)) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); + } + + /* set sd card driver strength */ + SD_SetDriverStrength(card, card->driverStrength); + /* set sd card current limit */ + SD_SetMaxCurrent(card, card->maxCurrent); + + /* set block size */ + if (SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + /* select bus timing */ + if (kStatus_Success != SD_SelectBusTiming(card)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + return kStatus_Success; +} + +void SD_Deinit(sd_card_t *card) +{ + assert(card); + + SD_SelectCard(card, false); + HOST_Deinit(&(card->host)); + /* should re-init host */ + card->isHostReady = false; +} + +bool SD_CheckReadOnly(sd_card_t *card) +{ + assert(card); + + return ((card->csd.flags & kSD_CsdPermanentWriteProtectFlag) || + (card->csd.flags & kSD_CsdTemporaryWriteProtectFlag)); +} + +status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + + uint32_t blockCountOneTime; + uint32_t blockLeft; + uint32_t blockDone; + uint8_t *nextBuffer; + status_t error; + + if ((blockCount + startBlock) > card->blockCount) + { + return kStatus_InvalidArgument; + } + + blockLeft = blockCount; + blockDone = 0U; + while (blockLeft) + { + if (blockLeft > card->host.capability.maxBlockCount) + { + blockLeft = (blockLeft - card->host.capability.maxBlockCount); + blockCountOneTime = card->host.capability.maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + + nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + error = SD_Read(card, nextBuffer, (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime); + if (error != kStatus_Success) + { + return error; + } + + blockDone += blockCountOneTime; + } + + return kStatus_Success; +} + +status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + + uint32_t blockCountOneTime; /* The block count can be wrote in one time sending WRITE_BLOCKS command. */ + uint32_t blockLeft; /* Left block count to be wrote. */ + uint32_t blockDone = 0U; /* The block count has been wrote. */ + const uint8_t *nextBuffer; + status_t error; + + if ((blockCount + startBlock) > card->blockCount) + { + return kStatus_InvalidArgument; + } + + blockLeft = blockCount; + while (blockLeft) + { + if (blockLeft > card->host.capability.maxBlockCount) + { + blockLeft = (blockLeft - card->host.capability.maxBlockCount); + blockCountOneTime = card->host.capability.maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + + nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + error = SD_Write(card, nextBuffer, (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime); + if (error != kStatus_Success) + { + return error; + } + + blockDone += blockCountOneTime; + } + + return kStatus_Success; +} + +status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(blockCount); + + uint32_t blockCountOneTime; /* The block count can be erased in one time sending ERASE_BLOCKS command. */ + uint32_t blockDone = 0U; /* The block count has been erased. */ + uint32_t blockLeft; /* Left block count to be erase. */ + status_t error; + + if ((blockCount + startBlock) > card->blockCount) + { + return kStatus_InvalidArgument; + } + + blockLeft = blockCount; + while (blockLeft) + { + if (blockLeft > (card->csd.eraseSectorSize + 1U)) + { + blockCountOneTime = card->csd.eraseSectorSize + 1U; + blockLeft = blockLeft - blockCountOneTime; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + + error = SD_Erase(card, (startBlock + blockDone), blockCountOneTime); + if (error != kStatus_Success) + { + return error; + } + + blockDone += blockCountOneTime; + } + + return kStatus_Success; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdio.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdio.c new file mode 100644 index 0000000000000000000000000000000000000000..4e88fb183eed28ce83dea8688a50df6665d8f9fe --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdio.c @@ -0,0 +1,1041 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_card.h" +#include "fsl_sdmmc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SDIO_COMMON_CIS_TUPLE_NUM (3U) /*!< define the tuple number will be read during init */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief send card operation condition + * @param card Card descriptor. + * @param command argment + * argument = 0U , means to get the operation condition + * argument !=0 , set the operation condition register + */ +static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument); + +/*! + * @brief card Send relative address + * @param card Card descriptor. + */ +static status_t SDIO_SendRca(sdio_card_t *card); + +/*! + * @brief card select card + * @param card Card descriptor. + * @param select/diselect flag + */ +static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected); + +/*! + * @brief card go idle + * @param card Card descriptor. + */ +static status_t inline SDIO_GoIdle(sdio_card_t *card); + +/*! + * @brief decode CIS + * @param card Card descriptor. + * @param func number + * @param data buffer pointer + * @param tuple code + * @param tuple link + */ +static status_t SDIO_DecodeCIS( + sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* define the tuple list */ +static const uint32_t g_tupleList[SDIO_COMMON_CIS_TUPLE_NUM] = { + SDIO_TPL_CODE_MANIFID, SDIO_TPL_CODE_FUNCID, SDIO_TPL_CODE_FUNCE, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected) +{ + assert(card); + + return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); +} + +static status_t inline SDIO_GoIdle(sdio_card_t *card) +{ + assert(card); + + return SDMMC_GoIdle(card->host.base, card->host.transfer); +} + +static status_t SDIO_SendRca(sdio_card_t *card) +{ + assert(card); + + uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDIO_SendRelativeAddress; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR6; + command.responseErrorFlags = kSDIO_StatusR6Error | kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError; + + content.command = &command; + content.data = NULL; + + while (--i) + { + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + /* check illegal state and cmd CRC error, may be the voltage or clock not stable, retry the cmd*/ + if (command.response[0U] & (kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError)) + { + continue; + } + + card->relativeAddress = (command.response[0U] >> 16U); + + return kStatus_Success; + } + } + + return kStatus_SDMMC_TransferFailed; +} + +status_t SDIO_CardInActive(sdio_card_t *card) +{ + assert(card); + + return SDMMC_SetCardInactive(card->host.base, card->host.transfer); +} + +static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument) +{ + assert(card); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; + + command.index = kSDIO_SendOperationCondition; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR4; + + content.command = &command; + content.data = NULL; + + while (--i) + { + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + continue; + } + + /* if argument equal 0, then should check and save the info */ + if (argument == 0U) + { + /* check if memory present */ + if ((command.response[0U] & kSDIO_OcrMemPresent) == kSDIO_OcrMemPresent) + { + card->memPresentFlag = true; + } + /* save the io number */ + card->ioTotalNumber = (command.response[0U] & kSDIO_OcrIONumber) >> 28U; + /* save the operation condition */ + card->ocr = command.response[0U] & 0xFFFFFFU; + + break; + } + /* wait the card is ready for after initialization */ + else if (command.response[0U] & kSDIO_OcrPowerUpBusyFlag) + { + break; + } + } + + return ((i != 0U) ? kStatus_Success : kStatus_Fail); +} + +status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + + command.index = kSDIO_RWIODirect; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (1U << SDIO_CMD_ARGUMENT_RW_POS) | ((raw ? 1U : 0U) << SDIO_DIRECT_CMD_ARGUMENT_RAW_POS) | + (*data & SDIO_DIRECT_CMD_DATA_MASK); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + content.command = &command; + content.data = NULL; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read data from response */ + *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; + + return kStatus_Success; +} + +status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + + command.index = kSDIO_RWIODirect; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + content.command = &command; + content.data = NULL; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read data from response */ + *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; + + return kStatus_Success; +} + +status_t SDIO_IO_Write_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) +{ + assert(card); + assert(buffer); + assert(func <= kSDIO_FunctionNum7); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + HOST_DATA data = {0U}; + bool blockMode = false; + bool opCode = false; + + /* check if card support block mode */ + if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) + { + blockMode = true; + } + + if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) + { + opCode = true; + } + + /* check the byte size counter in non-block mode + * so you need read CIS for each function first,before you do read/write + */ + if (!blockMode) + { + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (count > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && + (count > card->funcCIS[func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + } + + command.index = kSDIO_RWIOExtended; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (1U << SDIO_CMD_ARGUMENT_RW_POS) | (count & SDIO_EXTEND_CMD_COUNT_MASK) | + ((blockMode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | + ((opCode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + if (blockMode) + { + if (func == kSDIO_FunctionNum0) + { + data.blockSize = card->io0blockSize; + } + else + { + data.blockSize = card->ioFBR[func - 1U].ioBlockSize; + } + data.blockCount = count; + } + else + { + data.blockSize = count; + data.blockCount = 1U; + } + data.txData = (uint32_t *)buffer; + + content.command = &command; + content.data = &data; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_IO_Read_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) +{ + assert(card); + assert(buffer); + assert(func <= kSDIO_FunctionNum7); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + HOST_DATA data = {0U}; + bool blockMode = false; + bool opCode = false; + + /* check if card support block mode */ + if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) + { + blockMode = true; + } + + /* op code =0 : read/write to fixed addr + * op code =1 :read/write addr incrementing + */ + if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) + { + opCode = true; + } + + /* check the byte size counter in non-block mode + * so you need read CIS for each function first,before you do read/write + */ + if (!blockMode) + { + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (count > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && + (count > card->funcCIS[func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + } + + command.index = kSDIO_RWIOExtended; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (count & SDIO_EXTEND_CMD_COUNT_MASK) | + ((blockMode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | + ((opCode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + if (blockMode) + { + if (func == kSDIO_FunctionNum0) + { + data.blockSize = card->io0blockSize; + } + else + { + data.blockSize = card->ioFBR[func - 1U].ioBlockSize; + } + data.blockCount = count; + } + else + { + data.blockSize = count; + data.blockCount = 1U; + } + data.rxData = (uint32_t *)buffer; + + content.command = &command; + content.data = &data; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t tempBuffer[20] = {0U}; + uint32_t i = 0U; + + for (i = 0U; i < 20U; i++) + { + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + i, &tempBuffer[i])) + { + return kStatus_SDMMC_TransferFailed; + } + } + + switch (func) + { + case kSDIO_FunctionNum0: + + card->sdVersion = tempBuffer[1U]; + card->sdioVersion = tempBuffer[0U] >> 4U; + card->cccrVersioin = tempBuffer[0U] & 0xFU; + /* continuous SPI interrupt */ + if (tempBuffer[7U] & 0x40U) + { + card->cccrflags |= kSDIO_CCCRSupportContinuousSPIInt; + } + /* card capability register */ + card->cccrflags |= (tempBuffer[8U] & 0xDFU); + /* master power control */ + if (tempBuffer[18U] & 0x01U) + { + card->cccrflags |= kSDIO_CCCRSupportMasterPowerControl; + } + /* high speed flag */ + if (tempBuffer[19U] & 0x01U) + { + card->cccrflags |= kSDIO_CCCRSupportHighSpeed; + } + /* common CIS pointer */ + card->commonCISPointer = tempBuffer[9U] | (tempBuffer[10U] << 8U) | (tempBuffer[11U] << 16U); + + break; + + case kSDIO_FunctionNum1: + case kSDIO_FunctionNum2: + case kSDIO_FunctionNum3: + case kSDIO_FunctionNum4: + case kSDIO_FunctionNum5: + case kSDIO_FunctionNum6: + case kSDIO_FunctionNum7: + card->ioFBR[func - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU; + card->ioFBR[func - 1U].ioExtFunctionCode = tempBuffer[1U]; + card->ioFBR[func - 1U].ioPointerToCIS = tempBuffer[9U] | (tempBuffer[10U] << 8U) | (tempBuffer[11U] << 16U); + card->ioFBR[func - 1U].ioPointerToCSA = + tempBuffer[12U] | (tempBuffer[13U] << 8U) | (tempBuffer[14U] << 16U); + if (tempBuffer[2U] & 0x01U) + { + card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportPowerSelection; + } + if (tempBuffer[0U] & 0x40U) + { + card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportCSA; + } + + break; + + default: + break; + } + + return kStatus_Success; +} + +status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + assert(blockSize <= SDIO_MAX_BLOCK_SIZE); + + uint8_t temp = 0U; + + /* check the block size for block mode + * so you need read CIS for each function first,before you do read/write + */ + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (blockSize > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && + (blockSize > card->funcCIS[func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + + temp = blockSize & 0xFFU; + + if (kStatus_Success != + SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeLow, &temp, true)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + temp = (blockSize >> 8U) & 0xFFU; + + if (kStatus_Success != + SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeHigh, &temp, true)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + /* record the current block size */ + if (func == kSDIO_FunctionNum0) + { + card->io0blockSize = blockSize; + } + else + { + card->ioFBR[func - 1U].ioBlockSize = blockSize; + } + + return kStatus_Success; +} + +status_t SDIO_CardReset(sdio_card_t *card) +{ + uint8_t reset = 0x08U; + + return SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOAbort, &reset, false); +} + +status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth) +{ + assert(card); + + uint8_t regBusInterface = 0U; + + /* load bus interface register */ + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegBusInterface, ®BusInterface)) + { + return kStatus_SDMMC_TransferFailed; + } + /* set bus width */ + regBusInterface |= busWidth; + + /* write to register */ + if (kStatus_Success != + SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegBusInterface, ®BusInterface, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_SwitchToHighSpeed(sdio_card_t *card) +{ + assert(card); + + uint8_t temp = 0U; + + if (card->cccrflags & kSDIO_CCCRSupportHighSpeed) + { + /* enable high speed mode */ + temp = 0x02U; + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegHighSpeed, &temp, true)) + { + return kStatus_SDMMC_TransferFailed; + } + /* either EHS=0 and SHS=0 ,the card is still in default mode */ + if ((temp & 0x03U) == 0x03U) + { + /* set to 4bit data bus */ + SDIO_SetDataBusWidth(card, kSDIO_DataBus4Bit); + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); + /* high speed mode , set freq to 50MHZ */ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + } + else + { + return kStatus_SDMMC_SDIO_SwitchHighSpeedFail; + } + } + + return kStatus_Success; +} + +static status_t SDIO_DecodeCIS( + sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + if (func == kSDIO_FunctionNum0) + { + /* only decode MANIFID,FUNCID,FUNCE here */ + if (tplCode == SDIO_TPL_CODE_MANIFID) + { + card->commonCIS.mID = dataBuffer[0U] | (dataBuffer[1U] << 8U); + card->commonCIS.mInfo = dataBuffer[2U] | (dataBuffer[3U] << 8U); + } + else if (tplCode == SDIO_TPL_CODE_FUNCID) + { + card->commonCIS.funcID = dataBuffer[0U]; + } + else if (tplCode == SDIO_TPL_CODE_FUNCE) + { + /* max transfer block size and data size */ + card->commonCIS.fn0MaxBlkSize = dataBuffer[1U] | (dataBuffer[2U] << 8U); + /* max transfer speed */ + card->commonCIS.maxTransSpeed = dataBuffer[3U]; + } + else + { + /* reserved here */ + return kStatus_Fail; + } + } + else + { + /* only decode FUNCID,FUNCE here */ + if (tplCode == SDIO_TPL_CODE_FUNCID) + { + card->funcCIS[func].funcID = dataBuffer[0U]; + } + else if (tplCode == SDIO_TPL_CODE_FUNCE) + { + if (tplLink == 0x2A) + { + card->funcCIS[func - 1U].funcInfo = dataBuffer[1U]; + card->funcCIS[func - 1U].ioVersion = dataBuffer[2U]; + card->funcCIS[func - 1U].cardPSN = + dataBuffer[3U] | (dataBuffer[4U] << 8U) | (dataBuffer[5U] << 16U) | (dataBuffer[6U] << 24U); + card->funcCIS[func - 1U].ioCSASize = + dataBuffer[7U] | (dataBuffer[8U] << 8U) | (dataBuffer[9U] << 16U) | (dataBuffer[10U] << 24U); + card->funcCIS[func - 1U].ioCSAProperty = dataBuffer[11U]; + card->funcCIS[func - 1U].ioMaxBlockSize = dataBuffer[12U] | (dataBuffer[13U] << 8U); + card->funcCIS[func - 1U].ioOCR = + dataBuffer[14U] | (dataBuffer[15U] << 8U) | (dataBuffer[16U] << 16U) | (dataBuffer[17U] << 24U); + card->funcCIS[func - 1U].ioOPMinPwr = dataBuffer[18U]; + card->funcCIS[func - 1U].ioOPAvgPwr = dataBuffer[19U]; + card->funcCIS[func - 1U].ioOPMaxPwr = dataBuffer[20U]; + card->funcCIS[func - 1U].ioSBMinPwr = dataBuffer[21U]; + card->funcCIS[func - 1U].ioSBAvgPwr = dataBuffer[22U]; + card->funcCIS[func - 1U].ioSBMaxPwr = dataBuffer[23U]; + card->funcCIS[func - 1U].ioMinBandWidth = dataBuffer[24U] | (dataBuffer[25U] << 8U); + card->funcCIS[func - 1U].ioOptimumBandWidth = dataBuffer[26U] | (dataBuffer[27U] << 8U); + card->funcCIS[func - 1U].ioReadyTimeout = dataBuffer[28U] | (dataBuffer[29U] << 8U); + + card->funcCIS[func - 1U].ioHighCurrentAvgCurrent = dataBuffer[34U] | (dataBuffer[35U] << 8U); + card->funcCIS[func - 1U].ioHighCurrentMaxCurrent = dataBuffer[36U] | (dataBuffer[37U] << 8U); + card->funcCIS[func - 1U].ioLowCurrentAvgCurrent = dataBuffer[38U] | (dataBuffer[39U] << 8U); + card->funcCIS[func - 1U].ioLowCurrentMaxCurrent = dataBuffer[40U] | (dataBuffer[41U] << 8U); + } + else + { + return kStatus_Fail; + } + } + else + { + return kStatus_Fail; + } + } + + return kStatus_Success; +} + +status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + assert(tupleList); + + uint8_t tplCode = 0U; + uint8_t tplLink = 0U; + uint32_t cisPtr = 0U; + uint32_t i = 0U, num = 0U; + bool tupleMatch = false; + + uint8_t dataBuffer[255U] = {0U}; + + /* get the CIS pointer for each function */ + if (func == kSDIO_FunctionNum0) + { + cisPtr = card->commonCISPointer; + } + else + { + cisPtr = card->ioFBR[func - 1U].ioPointerToCIS; + } + + if (0U == cisPtr) + { + return kStatus_SDMMC_SDIO_ReadCISFail; + } + + do + { + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, cisPtr++, &tplCode)) + { + return kStatus_SDMMC_TransferFailed; + } + /* end of chain tuple */ + if (tplCode == 0xFFU) + { + break; + } + + if (tplCode == 0U) + { + continue; + } + + for (i = 0; i < tupleNum; i++) + { + if (tplCode == tupleList[i]) + { + tupleMatch = true; + break; + } + } + + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, cisPtr++, &tplLink)) + { + return kStatus_SDMMC_TransferFailed; + } + /* end of chain tuple */ + if (tplLink == 0xFFU) + { + break; + } + + if (tupleMatch) + { + memset(dataBuffer, 0U, 255U); + for (i = 0; i < tplLink; i++) + { + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, cisPtr++, &dataBuffer[i])) + { + return kStatus_SDMMC_TransferFailed; + } + } + tupleMatch = false; + /* pharse the data */ + SDIO_DecodeCIS(card, func, dataBuffer, tplCode, tplLink); + /* read finish then return */ + if (++num == tupleNum) + { + break; + } + } + else + { + /* move pointer */ + cisPtr += tplLink; + /* tuple code not match,continue read tuple code */ + continue; + } + } while (1); + return kStatus_Success; +} + +status_t SDIO_Init(sdio_card_t *card) +{ + assert(card); + assert(card->host.base); + + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + error = HOST_Init(&(card->host)); + if (error != kStatus_Success) + { + return error; + } + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + } + else + { + /* reset the host */ + HOST_Reset(card->host.base); + } + + error = CardInsertDetect(card->host.base); + if (error != kStatus_Success) + { + return error; + } + + /* Identify mode ,set clock to 400KHZ. */ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH1BIT); + HOST_SEND_CARD_ACTIVE(card->host.base, 100U); + + /* get host capability */ + GET_HOST_CAPABILITY(card->host.base, &(card->host.capability)); + + /* card go idle */ + if (kStatus_Success != SDIO_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + + /* Get IO OCR-CMD5 with arg0 ,set new voltage if needed*/ + if (kStatus_Success != SDIO_SendOperationCondition(card, 0U)) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + /* there is a memonly card */ + if ((card->ioTotalNumber == 0U) && (card->memPresentFlag)) + { + return kStatus_SDMMC_SDIO_InvalidCard; + } + /* verify the voltage and set the new voltage */ + if (card->host.capability.flags & kHOST_SupportV330) + { + if (kStatus_Success != SDIO_SendOperationCondition(card, kSDIO_OcrVdd32_33Flag | kSDIO_OcrVdd33_34Flag)) + { + return kStatus_SDMMC_InvalidVoltage; + } + } + else + { + return kStatus_SDMMC_InvalidVoltage; + } + + /* send relative address ,cmd3*/ + if (kStatus_Success != SDIO_SendRca(card)) + { + return kStatus_SDMMC_SendRelativeAddressFailed; + } + /* select card cmd7 */ + if (kStatus_Success != SDIO_SelectCard(card, true)) + { + return kStatus_SDMMC_SelectCardFailed; + } + + /* get card capability */ + if (kStatus_Success != SDIO_GetCardCapability(card, kSDIO_FunctionNum0)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read common CIS here */ + if (SDIO_ReadCIS(card, kSDIO_FunctionNum0, g_tupleList, SDIO_COMMON_CIS_TUPLE_NUM)) + { + return kStatus_SDMMC_SDIO_ReadCISFail; + } + + /* freq and bus width setting */ + if (card->cccrflags & kSDIO_CCCRSupportLowSpeed4Bit) + { + /* set to 4bit data bus */ + SDIO_SetDataBusWidth(card, kSDIO_DataBus4Bit); + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); + } + else if (card->cccrflags & kSDIO_CCCRSupportHighSpeed) + { + if (kStatus_Success != SDIO_SwitchToHighSpeed(card)) + { + return kStatus_SDMMC_SDIO_SwitchHighSpeedFail; + } + + return kStatus_Success; + } + + /* default mode 25MHZ */ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); + + return kStatus_Success; +} + +status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t intEn = 0U; + + /* load io interrupt enable register */ + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, &intEn)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (enable) + { + /* if already enable , do not need enable again */ + if ((((intEn >> func) & 0x01U) == 0x01U) && (intEn & 0x01U)) + { + return kStatus_Success; + } + + /* enable the interrupt and interrupt master */ + intEn |= (1U << func) | 0x01U; + } + else + { + /* if already disable , do not need enable again */ + if (((intEn >> func) & 0x01U) == 0x00U) + { + return kStatus_Success; + } + + /* disable the interrupt, don't disable the interrupt master here */ + intEn &= ~(1U << func); + } + + /* write to register */ + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, &intEn, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t ioEn = 0U, ioReady = 0U; + uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; + + /* load io enable register */ + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOEnable, &ioEn)) + { + return kStatus_SDMMC_TransferFailed; + } + /* if already enable/disable , do not need enable/disable again */ + if (((ioEn >> func) & 0x01U) == (enable ? 1U : 0U)) + { + return kStatus_Success; + } + + /* enable the io */ + if (enable) + { + ioEn |= (1U << func); + } + else + { + ioEn &= ~(1U << func); + } + + /* write to register */ + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOEnable, &ioEn, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* if enable io, need check the IO ready status */ + if (enable) + { + while (i--) + { + /* wait IO ready */ + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOReady, &ioReady)) + { + return kStatus_SDMMC_TransferFailed; + } + /* check if IO ready */ + if ((ioReady & (1 << func)) != 0U) + { + return kStatus_Success; + } + } + } + + return (i == 0U) ? kStatus_Fail : kStatus_Success; +} + +status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card); + assert(func <= kSDIO_FunctionMemory); + + uint8_t ioSel = func; + + /* write to register */ + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegFunctionSelect, &ioSel, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t ioAbort = func; + + /* write to register */ + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOAbort, &ioAbort, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +void SDIO_DeInit(sdio_card_t *card) +{ + assert(card); + /* disselect card */ + SDIO_CardReset(card); + SDIO_SelectCard(card, false); + HOST_Deinit(&(card->host)); + /* should re-init host */ + card->isHostReady = false; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.c new file mode 100644 index 0000000000000000000000000000000000000000..8cc9712c0d94f6e48e79a39dbcda13e382e81594 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.c @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_specification.h" +#include "fsl_card.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +SDK_ALIGN(uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CAHCE)], + MAX(SDMMC_DATA_BUFFER_ALIGN_CAHCE, HOST_DMA_BUFFER_ADDR_ALIGN)); +/******************************************************************************* + * Code + ******************************************************************************/ + +void SDMMC_Delay(uint32_t num) +{ + volatile uint32_t i, j; + + for (i = 0U; i < num; i++) + { + for (j = 0U; j < 10000U; j++) + { + __asm("nop"); + } + } +} + +status_t SDMMC_SelectCard(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress, bool isSelected) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SelectCard; + if (isSelected) + { + command.argument = relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + } + else + { + command.argument = 0U; + command.responseType = kCARD_ResponseTypeNone; + } + + content.command = &command; + content.data = NULL; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Wait until card to transfer state */ + return kStatus_Success; +} + +status_t SDMMC_SendApplicationCommand(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_ApplicationCommand; + command.argument = (relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (!(command.response[0U] & kSDMMC_R1ApplicationCommandFlag)) + { + return kStatus_SDMMC_CardNotSupport; + } + + return kStatus_Success; +} + +status_t SDMMC_SetBlockCount(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockCount) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SetBlockCount; + command.argument = blockCount; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_GoIdle(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_GoIdleState; + + content.command = &command; + content.data = 0U; + if (kStatus_Success != transfer(base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SetBlockSize(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockSize) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SetBlockLength; + command.argument = blockSize; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SetCardInactive(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_GoInactiveState; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeNone; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content))) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SwitchVoltage(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSD_VoltageSwitch; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != transfer(base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + /* disable card clock */ + HOST_ENABLE_CARD_CLOCK(base, false); + + /* check data line and cmd line status */ + if ((GET_HOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) != 0U) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + /* host switch to 1.8V */ + HOST_SWITCH_VOLTAGE180V(base, true); + + SDMMC_Delay(100U); + + /*enable sd clock*/ + HOST_ENABLE_CARD_CLOCK(base, true); + /*enable force clock on*/ + HOST_FORCE_SDCLOCK_ON(base, true); + /* dealy 1ms,not exactly correct when use while */ + SDMMC_Delay(10U); + /*disable force clock on*/ + HOST_FORCE_SDCLOCK_ON(base, false); + + /* check data line and cmd line status */ + if ((GET_HOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) == 0U) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + return kStatus_Success; +} + +status_t SDMMC_ExecuteTuning(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t tuningCmd, uint32_t blockSize) +{ + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + HOST_DATA data = {0U}; + uint32_t buffer[32U] = {0U}; + bool tuningError = true; + + command.index = tuningCmd; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = blockSize; + data.blockCount = 1U; + data.rxData = buffer; + /* add this macro for adpter to different driver */ + HOST_ENABLE_TUNING_FLAG(data); + + content.command = &command; + content.data = &data; + + /* enable the standard tuning */ + HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); + + while (true) + { + /* send tuning block */ + if ((kStatus_Success != transfer(base, &content))) + { + return kStatus_SDMMC_TransferFailed; + } + SDMMC_Delay(1U); + + /*wait excute tuning bit clear*/ + if ((HOST_EXECUTE_STANDARD_TUNING_STATUS(base) != 0U)) + { + continue; + } + + /* if tuning error , re-tuning again */ + if ((HOST_CHECK_TUNING_ERROR(base) != 0U) && tuningError) + { + tuningError = false; + /* enable the standard tuning */ + HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); + HOST_ADJUST_TUNING_DELAY(base, HOST_STANDARD_TUNING_START); + } + else + { + break; + } + } + + /* delay to wait the host controller stable */ + SDMMC_Delay(100U); + + /* check tuning result*/ + if (HOST_EXECUTE_STANDARD_TUNING_RESULT(base) == 0U) + { + return kStatus_SDMMC_TuningFail; + } + + HOST_AUTO_STANDARD_RETUNING_TIMER(base); + + return kStatus_Success; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.h new file mode 100644 index 0000000000000000000000000000000000000000..c616a951984647de0bdf89b8c50398477d8d9305 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SDMMC_H_ +#define _FSL_SDMMC_H_ + +#include "fsl_card.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Reverse byte sequence in uint32_t */ +#define SWAP_WORD_BYTE_SEQUENCE(x) (__REV(x)) +/*! @brief Reverse byte sequence for each half word in uint32_t */ +#define SWAP_HALF_WROD_BYTE_SEQUENCE(x) (__REV16(x)) + +/*! @brief Maximum loop count to check the card operation voltage range */ +#define FSL_SDMMC_MAX_VOLTAGE_RETRIES (1000U) +/*! @brief Maximum loop count to send the cmd */ +#define FSL_SDMMC_MAX_CMD_RETRIES (10U) +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Selects the card to put it into transfer state. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @param relativeAddress Relative address. + * @param isSelected True to put card into transfer state. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SelectCard(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress, bool isSelected); + +/*! + * @brief Sends an application command. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @param relativeAddress Card relative address. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SendApplicationCommand(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress); + +/*! + * @brief Sets the block count. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @param blockCount Block count. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SetBlockCount(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockCount); + +/*! + * @brief Sets the card to be idle state. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_GoIdle(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer); + +/*! + * @brief Sets data block size. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @param blockSize Block size. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SetBlockSize(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockSize); + +/*! + * @brief Sets card to inactive status + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SetCardInactive(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer); + +/*! + * @brief provide a simple delay function for sdmmc + * + * @param num Delay num*10000. + */ +void SDMMC_Delay(uint32_t num); + +/*! + * @brief provide a voltage switch function for SD/SDIO card + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + */ +status_t SDMMC_SwitchVoltage(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer); + +/*! + * @brief excute tuning + * + * @param base HOST peripheral base address. + * @param transfer Host transfer function + * @param tuningCmd Tuning cmd + * @param blockSize Tuning block size + */ +status_t SDMMC_ExecuteTuning(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t tuningCmd, uint32_t blockSize); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_SDMMC_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.c new file mode 100644 index 0000000000000000000000000000000000000000..4055e16d8c81c9fb47d6c3dd8c6464ba1cf65997 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.c @@ -0,0 +1,1273 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "fsl_sdspi.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +#define IS_BLOCK_ACCESS(x) ((x)->flags & kSDSPI_SupportHighCapacityFlag) + +/* Card command maximum timeout value */ +#define FSL_SDSPI_TIMEOUT (1000U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Wait card to be ready state. + * + * @param host Host state. + * @param milliseconds Timeout time in millseconds. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_WaitReady(sdspi_host_t *host, uint32_t milliseconds); + +/*! + * @brief Calculate CRC7 + * + * @param buffer Data buffer. + * @param length Data length. + * @param crc The orginal crc value. + * @return Generated CRC7. + */ +static uint32_t SDSPI_GenerateCRC7(uint8_t *buffer, uint32_t length, uint32_t crc); + +/*! + * @brief Send command. + * + * @param host Host state. + * @param command The command to be wrote. + * @param timeout The timeout value. + * @retval kStatus_SDSPI_WaitReadyFailed Wait ready failed. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Fail Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendCommand(sdspi_host_t *host, sdspi_command_t *command, uint32_t timeout); + +/*! + * @brief Send GO_IDLE command. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_ExchangeFailed Send timing byte failed. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_GoIdle(sdspi_card_t *card); + +/*! + * @brief Send GET_INTERFACE_CONDITION command. + * + * This function checks card interface condition, which includes host supply voltage information and asks the card + * whether it supports voltage. + * + * @param card Card descriptor. + * @param pattern The check pattern. + * @param response Buffer to save the command response. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendInterfaceCondition(sdspi_card_t *card, uint8_t pattern, uint8_t *response); + +/*! + * @brief Send SEND_APPLICATION_COMMAND command. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendApplicationCmd(sdspi_card_t *card); + +/*! + * @brief Send GET_OPERATION_CONDITION command. + * + * @param card Card descriptor. + * @param argument Operation condition. + * @param response Buffer to save command response. + * @retval kStatus_Timeout Timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_ApplicationSendOperationCondition(sdspi_card_t *card, uint32_t argument, uint8_t *response); + +/*! + * @brief Send READ_OCR command to get OCR register content. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_ReadOcr(sdspi_card_t *card); + +/*! + * @brief Send SET_BLOCK_SIZE command. + * + * This function sets the block length in bytes for SDSC cards. For SDHC cards, it does not affect memory + * read or write commands, always 512 bytes fixed block length is used. + * @param card Card descriptor. + * @param blockSize Block size. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SetBlockSize(sdspi_card_t *card, uint32_t blockSize); + +/*! + * @brief Read data from card + * + * @param host Host state. + * @param buffer Buffer to save data. + * @param size The data size to read. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_Read(sdspi_host_t *host, uint8_t *buffer, uint32_t size); + +/*! + * @brief Decode CSD register + * + * @param card Card descriptor. + * @param rawCsd Raw CSD register content. + */ +static void SDSPI_DecodeCsd(sdspi_card_t *card, uint8_t *rawCsd); + +/*! + * @brief Send GET-CSD command. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ReadFailed Read data blocks failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendCsd(sdspi_card_t *card); + +/*! + * @brief Set card to max frequence in normal mode. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SetFrequencyFailed Set frequency failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SetMaxFrequencyNormalMode(sdspi_card_t *card); + +/*! + * @brief Check the capacity of the card + * + * @param card Card descriptor. + */ +static void SDSPI_CheckCapacity(sdspi_card_t *card); + +/*! + * @brief Decode raw CID register. + * + * @param card Card descriptor. + * @param rawCid Raw CID register content. + */ +static void SDSPI_DecodeCid(sdspi_card_t *card, uint8_t *rawCid); + +/*! + * @brief Send GET-CID command + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ReadFailed Read data blocks failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendCid(sdspi_card_t *card); + +/*! + * @brief Decode SCR register. + * + * @param card Card descriptor. + * @param rawScr Raw SCR register content. + */ +static void SDSPI_DecodeScr(sdspi_card_t *card, uint8_t *rawScr); + +/*! + * @brief Send SEND_SCR command. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ReadFailed Read data blocks failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendScr(sdspi_card_t *card); + +/*! + * @brief Send STOP_TRANSMISSION command to card to stop ongoing data transferring. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_StopTransmission(sdspi_card_t *card); + +/*! + * @brief Write data to card + * + * @param host Host state. + * @param buffer Data to send. + * @param size Data size. + * @param token The data token. + * @retval kStatus_SDSPI_WaitReadyFailed Card is busy error. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_Write(sdspi_host_t *host, uint8_t *buffer, uint32_t size, uint8_t token); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Rate unit(divided by 1000) of transfer speed in non-high-speed mode. */ +static const uint32_t g_transferSpeedRateUnit[] = { + /* 100Kbps, 1Mbps, 10Mbps, 100Mbps*/ + 100U, 1000U, 10000U, 100000U, +}; + +/* Multiplier factor(multiplied by 1000) of transfer speed in non-high-speed mode. */ +static const uint32_t g_transferSpeedMultiplierFactor[] = { + 0U, 1000U, 1200U, 1300U, 1500U, 2000U, 2500U, 3000U, 3500U, 4000U, 4500U, 5000U, 5500U, 6000U, 7000U, 8000U, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t SDSPI_WaitReady(sdspi_host_t *host, uint32_t milliseconds) +{ + uint8_t response; + uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ + uint32_t startTime; + uint32_t currentTime; + uint32_t elapsedTime; + + startTime = host->getCurrentMilliseconds(); + do + { + if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + currentTime = host->getCurrentMilliseconds(); + elapsedTime = (currentTime - startTime); + } while ((response != 0xFFU) && (elapsedTime < milliseconds)); + + /* Response 0xFF means card is still busy. */ + if (response != 0xFFU) + { + return kStatus_SDSPI_ResponseError; + } + + return kStatus_Success; +} + +static uint32_t SDSPI_GenerateCRC7(uint8_t *buffer, uint32_t length, uint32_t crc) +{ + uint32_t index; + + static const uint8_t crcTable[] = {0x00U, 0x09U, 0x12U, 0x1BU, 0x24U, 0x2DU, 0x36U, 0x3FU, + 0x48U, 0x41U, 0x5AU, 0x53U, 0x6CU, 0x65U, 0x7EU, 0x77U}; + + while (length) + { + index = (((crc >> 3U) & 0x0FU) ^ ((*buffer) >> 4U)); + crc = ((crc << 4U) ^ crcTable[index]); + + index = (((crc >> 3U) & 0x0FU) ^ ((*buffer) & 0x0FU)); + crc = ((crc << 4U) ^ crcTable[index]); + + buffer++; + length--; + } + + return (crc & 0x7FU); +} + +static status_t SDSPI_SendCommand(sdspi_host_t *host, sdspi_command_t *command, uint32_t timeout) +{ + assert(host); + assert(command); + + uint8_t buffer[6U]; + uint8_t response; + uint8_t i; + uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ + + if ((kStatus_Success != SDSPI_WaitReady(host, timeout)) && (command->index != kSDMMC_GoIdleState)) + { + return kStatus_SDSPI_WaitReadyFailed; + } + + /* Send command. */ + buffer[0U] = (command->index | 0x40U); + buffer[1U] = ((command->argument >> 24U) & 0xFFU); + buffer[2U] = ((command->argument >> 16U) & 0xFFU); + buffer[3U] = ((command->argument >> 8U) & 0xFFU); + buffer[4U] = (command->argument & 0xFFU); + buffer[5U] = ((SDSPI_GenerateCRC7(buffer, 5U, 0U) << 1U) | 1U); + if (host->exchange(buffer, NULL, sizeof(buffer))) + { + return kStatus_SDSPI_ExchangeFailed; + } + + /* Wait for the response coming, the left most bit which is transfered first in first response byte is 0 */ + for (i = 0U; i < 9U; i++) + { + if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + /* Check if response 0 coming. */ + if (!(response & 0x80U)) + { + break; + } + } + if (response & 0x80U) /* Max index byte is high means response comming. */ + { + return kStatus_SDSPI_ResponseError; + } + + /* Receve all the response content. */ + command->response[0U] = response; + switch (command->responseType) + { + case kSDSPI_ResponseTypeR1: + break; + case kSDSPI_ResponseTypeR1b: + if (kStatus_Success != SDSPI_WaitReady(host, timeout)) + { + return kStatus_SDSPI_WaitReadyFailed; + } + break; + case kSDSPI_ResponseTypeR2: + if (kStatus_Success != host->exchange(&timingByte, &(command->response[1U]), 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + break; + case kSDSPI_ResponseTypeR3: + case kSDSPI_ResponseTypeR7: + /* Left 4 bytes in response type R3 and R7(total 5 bytes in SPI mode) */ + if (kStatus_Success != host->exchange(&timingByte, &(command->response[1U]), 4U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + break; + default: + return kStatus_Fail; + } + + return kStatus_Success; +} + +static status_t SDSPI_GoIdle(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_host_t *host; + sdspi_command_t command = {0}; + uint32_t retryCount = 200U; + + host = card->host; + /* SD card will enter SPI mode if the CS is asserted (negative) during the reception of the reset command (CMD0) + and the card will be IDLE state. */ + while (retryCount--) + { + command.index = kSDMMC_GoIdleState; + command.responseType = kSDSPI_ResponseTypeR1; + if ((kStatus_Success == SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) && + (command.response[0U] == kSDSPI_R1InIdleStateFlag)) + { + break; + } + } + + return kStatus_Success; +} + +static status_t SDSPI_SendInterfaceCondition(sdspi_card_t *card, uint8_t pattern, uint8_t *response) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSD_SendInterfaceCondition; + command.argument = (0x100U | (pattern & 0xFFU)); + command.responseType = kSDSPI_ResponseTypeR7; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + memcpy(response, command.response, sizeof(command.response)); + + return kStatus_Success; +} + +static status_t SDSPI_SendApplicationCmd(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_host_t *host; + sdspi_command_t command = {0}; + + host = card->host; + command.index = kSDMMC_ApplicationCommand; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if ((command.response[0U]) && (!(command.response[0U] & kSDSPI_R1InIdleStateFlag))) + { + return kStatus_SDSPI_ResponseError; + } + + return kStatus_Success; +} + +static status_t SDSPI_ApplicationSendOperationCondition(sdspi_card_t *card, uint32_t argument, uint8_t *response) +{ + assert(card); + assert(card->host); + assert(response); + + sdspi_command_t command = {0}; + uint32_t startTime; + uint32_t currentTime; + uint32_t elapsedTime = 0U; + sdspi_host_t *host; + + host = card->host; + command.index = kSD_ApplicationSendOperationCondition; + command.argument = argument; + command.responseType = kSDSPI_ResponseTypeR1; + startTime = host->getCurrentMilliseconds(); + do + { + if (kStatus_Success == SDSPI_SendApplicationCmd(card)) + { + if (kStatus_Success == SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + if (!command.response[0U]) + { + break; + } + } + } + + currentTime = host->getCurrentMilliseconds(); + elapsedTime = (currentTime - startTime); + } while (elapsedTime < FSL_SDSPI_TIMEOUT); + + if (response) + { + memcpy(response, command.response, sizeof(command.response)); + } + if (elapsedTime < FSL_SDSPI_TIMEOUT) + { + return kStatus_Success; + } + + return kStatus_Timeout; +} + +static status_t SDSPI_ReadOcr(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + uint32_t i; + sdspi_host_t *host; + sdspi_command_t command = {0}; + + host = card->host; + command.index = kSDMMC_ReadOcr; + command.responseType = kSDSPI_ResponseTypeR3; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (command.response[0U]) + { + return kStatus_SDSPI_ResponseError; + } + + /* Switch the bytes sequence. All register's content is transferred from highest byte to lowest byte. */ + card->ocr = 0U; + for (i = 4U; i > 0U; i--) + { + card->ocr |= (uint32_t)command.response[i] << ((4U - i) * 8U); + } + + return kStatus_Success; +} + +static status_t SDSPI_SetBlockSize(sdspi_card_t *card, uint32_t blockSize) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSDMMC_SetBlockLength; + command.argument = blockSize; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + return kStatus_Success; +} + +static status_t SDSPI_Read(sdspi_host_t *host, uint8_t *buffer, uint32_t size) +{ + assert(host); + assert(host->exchange); + assert(buffer); + assert(size); + + uint32_t startTime; + uint32_t currentTime; + uint32_t elapsedTime; + uint8_t response, i; + uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ + + memset(buffer, 0xFFU, size); + + /* Wait data token comming */ + startTime = host->getCurrentMilliseconds(); + do + { + if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + currentTime = host->getCurrentMilliseconds(); + elapsedTime = (currentTime - startTime); + } while ((response == 0xFFU) && (elapsedTime < 100U)); + + /* Check data token and exchange data. */ + if (response != kSDSPI_DataTokenBlockRead) + { + return kStatus_SDSPI_ResponseError; + } + if (host->exchange(buffer, buffer, size)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + /* Get 16 bit CRC */ + for (i = 0U; i < 2U; i++) + { + if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + } + + return kStatus_Success; +} + +static void SDSPI_DecodeCsd(sdspi_card_t *card, uint8_t *rawCsd) +{ + assert(rawCsd); + assert(card); + + sd_csd_t *csd; + + csd = &(card->csd); + csd->csdStructure = (rawCsd[0U] >> 6U); + csd->dataReadAccessTime1 = rawCsd[1U]; + csd->dataReadAccessTime2 = rawCsd[2U]; + csd->transferSpeed = rawCsd[3U]; + csd->cardCommandClass = (((uint32_t)rawCsd[4U] << 4U) | ((uint32_t)rawCsd[5U] >> 4U)); + csd->readBlockLength = ((rawCsd)[5U] & 0xFU); + if (rawCsd[6U] & 0x80U) + { + csd->flags |= kSD_CsdReadBlockPartialFlag; + } + if (rawCsd[6U] & 0x40U) + { + csd->flags |= kSD_CsdWriteBlockMisalignFlag; + } + if (rawCsd[6U] & 0x20U) + { + csd->flags |= kSD_CsdReadBlockMisalignFlag; + } + if (rawCsd[6U] & 0x10U) + { + csd->flags |= kSD_CsdDsrImplementedFlag; + } + + /* Some fileds is different when csdStructure is different. */ + if (csd->csdStructure == 0U) /* Decode the bits when CSD structure is version 1.0 */ + { + csd->deviceSize = + ((((uint32_t)rawCsd[6] & 0x3U) << 10U) | ((uint32_t)rawCsd[7U] << 2U) | ((uint32_t)rawCsd[8U] >> 6U)); + csd->readCurrentVddMin = ((rawCsd[8U] >> 3U) & 7U); + csd->readCurrentVddMax = (rawCsd[8U] >> 7U); + csd->writeCurrentVddMin = ((rawCsd[9U] >> 5U) & 7U); + csd->writeCurrentVddMax = (rawCsd[9U] >> 2U); + csd->deviceSizeMultiplier = (((rawCsd[9U] & 3U) << 1U) | (rawCsd[10U] >> 7U)); + card->blockCount = (csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U); + card->blockSize = (1U << (csd->readBlockLength)); + if (card->blockSize != FSL_SDSPI_DEFAULT_BLOCK_SIZE) + { + card->blockCount = (card->blockCount * card->blockSize); + card->blockSize = FSL_SDSPI_DEFAULT_BLOCK_SIZE; + card->blockCount = (card->blockCount / card->blockSize); + } + } + else if (csd->csdStructure == 1U) /* Decode the bits when CSD structure is version 2.0 */ + { + card->blockSize = FSL_SDSPI_DEFAULT_BLOCK_SIZE; + csd->deviceSize = + ((((uint32_t)rawCsd[7U] & 0x3FU) << 16U) | ((uint32_t)rawCsd[8U] << 8U) | ((uint32_t)rawCsd[9U])); + if (csd->deviceSize >= 0xFFFFU) + { + card->flags |= kSDSPI_SupportSdxcFlag; + } + card->blockCount = ((csd->deviceSize + 1U) * 1024U); + } + else + { + } + + if ((rawCsd[10U] >> 6U) & 1U) + { + csd->flags |= kSD_CsdEraseBlockEnabledFlag; + } + csd->eraseSectorSize = (((rawCsd[10U] & 0x3FU) << 1U) | (rawCsd[11U] >> 7U)); + csd->writeProtectGroupSize = (rawCsd[11U] & 0x7FU); + if (rawCsd[12U] >> 7U) + { + csd->flags |= kSD_CsdWriteProtectGroupEnabledFlag; + } + csd->writeSpeedFactor = ((rawCsd[12U] >> 2U) & 7U); + csd->writeBlockLength = (((rawCsd[12U] & 3U) << 2U) | (rawCsd[13U] >> 6U)); + if ((rawCsd[13U] >> 5U) & 1U) + { + csd->flags |= kSD_CsdWriteBlockPartialFlag; + } + if (rawCsd[14U] >> 7U) + { + csd->flags |= kSD_CsdFileFormatGroupFlag; + } + if ((rawCsd[14U] >> 6U) & 1U) + { + csd->flags |= kSD_CsdCopyFlag; + } + if ((rawCsd[14U] >> 5U) & 1U) + { + csd->flags |= kSD_CsdPermanentWriteProtectFlag; + } + if ((rawCsd[14U] >> 4U) & 1U) + { + csd->flags |= kSD_CsdTemporaryWriteProtectFlag; + } + csd->fileFormat = ((rawCsd[14U] >> 2U) & 3U); +} + +static status_t SDSPI_SendCsd(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSDMMC_SendCsd; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (kStatus_Success != SDSPI_Read(host, card->rawCsd, sizeof(card->rawCsd))) + { + return kStatus_SDSPI_ReadFailed; + } + + SDSPI_DecodeCsd(card, card->rawCsd); + + return kStatus_Success; +} + +static status_t SDSPI_SetMaxFrequencyNormalMode(sdspi_card_t *card) +{ + uint32_t maxFrequency; + + /* Calculate max frequency card supported in non-high-speed mode. */ + maxFrequency = g_transferSpeedRateUnit[SD_RD_TRANSFER_SPEED_RATE_UNIT(card->csd)] * + g_transferSpeedMultiplierFactor[SD_RD_TRANSFER_SPEED_TIME_VALUE(card->csd)]; + if (maxFrequency > card->host->busBaudRate) + { + maxFrequency = card->host->busBaudRate; + } + + if (kStatus_Success != card->host->setFrequency(maxFrequency)) + { + return kStatus_SDSPI_SetFrequencyFailed; + } + + return kStatus_Success; +} + +static void SDSPI_CheckCapacity(sdspi_card_t *card) +{ + uint32_t deviceSize; + uint32_t deviceSizeMultiplier; + uint32_t readBlockLength; + + if (card->csd.csdStructure) + { + /* SD CSD structure v2.xx */ + deviceSize = card->csd.deviceSize; + if (deviceSize >= 0xFFFFU) /* Bigger than 32GB */ + { + /* extended capacity */ + card->flags |= kSDSPI_SupportSdxcFlag; + } + else + { + card->flags |= kSDSPI_SupportSdhcFlag; + } + deviceSizeMultiplier = 10U; + deviceSize += 1U; + readBlockLength = 9U; + } + else + { + /* SD CSD structure v1.xx */ + deviceSize = (card->csd.deviceSize + 1U); + deviceSizeMultiplier = (card->csd.deviceSizeMultiplier + 2U); + readBlockLength = card->csd.readBlockLength; + /* Card maximum capacity is 2GB when CSD structure version is 1.0 */ + card->flags |= kSDSPI_SupportSdscFlag; + } + if (readBlockLength != 9U) + { + /* Force to use 512-byte length block */ + deviceSizeMultiplier += (readBlockLength - 9U); + readBlockLength = 9U; + } + + card->blockSize = (1U << readBlockLength); + card->blockCount = (deviceSize << deviceSizeMultiplier); +} + +static void SDSPI_DecodeCid(sdspi_card_t *card, uint8_t *rawCid) +{ + assert(card); + assert(rawCid); + + sd_cid_t *cid = &(card->cid); + cid->manufacturerID = rawCid[0U]; + cid->applicationID = (((uint32_t)rawCid[1U] << 8U) | (uint32_t)(rawCid[2U])); + memcpy(cid->productName, &rawCid[3U], SD_PRODUCT_NAME_BYTES); + cid->productVersion = rawCid[8U]; + cid->productSerialNumber = (((uint32_t)rawCid[9U] << 24U) | ((uint32_t)rawCid[10U] << 16U) | + ((uint32_t)rawCid[11U] << 8U) | ((uint32_t)rawCid[12U])); + cid->manufacturerData = ((((uint32_t)rawCid[13U] & 0x0FU) << 8U) | ((uint32_t)rawCid[14U])); +} + +static status_t SDSPI_SendCid(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSDMMC_SendCid; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (kStatus_Success != (SDSPI_Read(host, card->rawCid, sizeof(card->rawCid)))) + { + return kStatus_SDSPI_ReadFailed; + } + + SDSPI_DecodeCid(card, card->rawCid); + + return kStatus_Success; +} + +static void SDSPI_DecodeScr(sdspi_card_t *card, uint8_t *rawScr) +{ + assert(card); + assert(rawScr); + + sd_scr_t *scr = &(card->scr); + scr->scrStructure = ((rawScr[0U] & 0xF0U) >> 4U); + scr->sdSpecification = (rawScr[0U] & 0x0FU); + if (rawScr[1U] & 0x80U) + { + scr->flags |= kSD_ScrDataStatusAfterErase; + } + scr->sdSecurity = ((rawScr[1U] & 0x70U) >> 4U); + scr->sdBusWidths = (rawScr[1U] & 0x0FU); + if (rawScr[2U] & 0x80U) + { + scr->flags |= kSD_ScrSdSpecification3; + } + scr->extendedSecurity = ((rawScr[2U] & 0x78U) >> 3U); + scr->commandSupport = (rawScr[3U] & 0x03U); + scr->reservedForManufacturer = (((uint32_t)rawScr[4U] << 24U) | ((uint32_t)rawScr[5U] << 16U) | + ((uint32_t)rawScr[6U] << 8U) | (uint32_t)rawScr[7U]); +} + +static status_t SDSPI_SendScr(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + if (kStatus_Success != SDSPI_SendApplicationCmd(card)) + { + return kStatus_SDSPI_SendApplicationCommandFailed; + } + + command.index = kSD_ApplicationSendScr; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (kStatus_Success != (SDSPI_Read(host, card->rawScr, sizeof(card->rawScr)))) + { + return kStatus_SDSPI_ReadFailed; + } + + SDSPI_DecodeScr(card, card->rawScr); + + return kStatus_Success; +} + +static status_t SDSPI_StopTransmission(sdspi_card_t *card) +{ + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSDMMC_StopTransmission; + command.responseType = kSDSPI_ResponseTypeR1b; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + return kStatus_Success; +} + +static status_t SDSPI_Write(sdspi_host_t *host, uint8_t *buffer, uint32_t size, uint8_t token) +{ + assert(host); + assert(host->exchange); + + uint8_t response; + uint8_t i; + uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ + + if (kStatus_Success != SDSPI_WaitReady(host, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_WaitReadyFailed; + } + + /* Write data token. */ + if (host->exchange(&token, NULL, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + if (token == kSDSPI_DataTokenStopTransfer) + { + return kStatus_Success; + } + + if ((!size) || (!buffer)) + { + return kStatus_InvalidArgument; + } + + /* Write data. */ + if (kStatus_Success != host->exchange(buffer, NULL, size)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + /* Get the last two bytes CRC */ + for (i = 0U; i < 2U; i++) + { + if (host->exchange(&timingByte, NULL, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + } + + /* Get the response token. */ + if (host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + if ((response & SDSPI_DATA_RESPONSE_TOKEN_MASK) != kSDSPI_DataResponseTokenAccepted) + { + return kStatus_SDSPI_ResponseError; + } + + return kStatus_Success; +} + +status_t SDSPI_Init(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + assert(card->host->setFrequency); + assert(card->host->exchange); + assert(card->host->getCurrentMilliseconds); + + sdspi_host_t *host; + uint32_t applicationCommand41Argument = 0U; + uint32_t startTime; + uint32_t currentTime; + uint32_t elapsedTime; + uint8_t response[5U]; + uint8_t applicationCommand41Response[5U]; + bool likelySdV1 = false; + + host = card->host; + /* Card must be initialized in 400KHZ. */ + if (host->setFrequency(SDMMC_CLOCK_400KHZ)) + { + return kStatus_SDSPI_SetFrequencyFailed; + } + + /* Reset the card by CMD0. */ + if (kStatus_Success != SDSPI_GoIdle(card)) + { + return kStatus_SDSPI_GoIdleFailed; + } + + /* Check the card's supported interface condition. */ + if (kStatus_Success != SDSPI_SendInterfaceCondition(card, 0xAAU, response)) + { + likelySdV1 = true; + } + else if ((response[3U] == 0x1U) || (response[4U] == 0xAAU)) + { + applicationCommand41Argument |= kSD_OcrHostCapacitySupportFlag; + } + else + { + return kStatus_SDSPI_SendInterfaceConditionFailed; + } + + /* Set card's interface condition according to host's capability and card's supported interface condition */ + startTime = host->getCurrentMilliseconds(); + do + { + if (kStatus_Success != + SDSPI_ApplicationSendOperationCondition(card, applicationCommand41Argument, applicationCommand41Response)) + { + return kStatus_SDSPI_SendOperationConditionFailed; + } + + currentTime = host->getCurrentMilliseconds(); + elapsedTime = (currentTime - startTime); + if (elapsedTime > 500U) + { + return kStatus_Timeout; + } + + if (!applicationCommand41Response[0U]) + { + break; + } + } while (applicationCommand41Response[0U] & kSDSPI_R1InIdleStateFlag); + + if (!likelySdV1) + { + if (kStatus_Success != SDSPI_ReadOcr(card)) + { + return kStatus_SDSPI_ReadOcrFailed; + } + if (card->ocr & kSD_OcrCardCapacitySupportFlag) + { + card->flags |= kSDSPI_SupportHighCapacityFlag; + } + } + + /* Force to use 512-byte length block, no matter which version. */ + if (kStatus_Success != SDSPI_SetBlockSize(card, 512U)) + { + return kStatus_SDSPI_SetBlockSizeFailed; + } + if (kStatus_Success != SDSPI_SendCsd(card)) + { + return kStatus_SDSPI_SendCsdFailed; + } + + /* Set to max frequency according to the max frequency information in CSD register. */ + SDSPI_SetMaxFrequencyNormalMode(card); + + /* Save capacity, read only attribute and CID, SCR registers. */ + SDSPI_CheckCapacity(card); + SDSPI_CheckReadOnly(card); + if (kStatus_Success != SDSPI_SendCid(card)) + { + return kStatus_SDSPI_SendCidFailed; + } + if (kStatus_Success != SDSPI_SendScr(card)) + { + return kStatus_SDSPI_SendCidFailed; + } + + return kStatus_Success; +} + +void SDSPI_Deinit(sdspi_card_t *card) +{ + assert(card); + + memset(card, 0, sizeof(sdspi_card_t)); +} + +bool SDSPI_CheckReadOnly(sdspi_card_t *card) +{ + assert(card); + + if ((card->csd.flags & kSD_CsdPermanentWriteProtectFlag) || (card->csd.flags & kSD_CsdTemporaryWriteProtectFlag)) + { + return true; + } + + return false; +} + +status_t SDSPI_ReadBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(card->host); + assert(buffer); + assert(blockCount); + + uint32_t offset; + uint32_t i; + sdspi_command_t command = {0}; + sdspi_host_t *host; + + offset = startBlock; + if (!IS_BLOCK_ACCESS(card)) + { + offset *= card->blockSize; + } + + /* Send command and reads data. */ + host = card->host; + command.argument = offset; + command.responseType = kSDSPI_ResponseTypeR1; + if (blockCount == 1U) + { + command.index = kSDMMC_ReadSingleBlock; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (kStatus_Success != SDSPI_Read(host, buffer, card->blockSize)) + { + return kStatus_SDSPI_ReadFailed; + } + } + else + { + command.index = kSDMMC_ReadMultipleBlock; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + for (i = 0U; i < blockCount; i++) + { + if (kStatus_Success != SDSPI_Read(host, buffer, card->blockSize)) + { + return kStatus_SDSPI_ReadFailed; + } + buffer += card->blockSize; + } + + /* Write stop transmission command after the last data block. */ + if (kStatus_Success != SDSPI_StopTransmission(card)) + { + return kStatus_SDSPI_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +status_t SDSPI_WriteBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(card->host); + assert(buffer); + assert(blockCount); + + uint32_t offset; + uint32_t i; + sdspi_host_t *host; + sdspi_command_t command = {0}; + + if (SDSPI_CheckReadOnly(card)) + { + return kStatus_SDSPI_WriteProtected; + } + + offset = startBlock; + if (!IS_BLOCK_ACCESS(card)) + { + offset *= card->blockSize; + } + + /* Send command and writes data. */ + host = card->host; + if (blockCount == 1U) + { + command.index = kSDMMC_WriteSingleBlock; + command.argument = offset; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (command.response[0U]) + { + return kStatus_SDSPI_ResponseError; + } + + if (kStatus_Success != SDSPI_Write(host, buffer, card->blockSize, kSDSPI_DataTokenSingleBlockWrite)) + { + return kStatus_SDSPI_WriteFailed; + } + } + else + { +#if defined FSL_SDSPI_ENABLE_PRE_ERASE_ON_WRITE + /* Pre-erase before writing data */ + if (kStatus_Success != SDSPI_SendApplicationCmd(card)) + { + return kStatus_SDSPI_SendApplicationCommandFailed; + } + + command.index = kSDAppSetWrBlkEraseCount; + command.argument = blockCount; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host->base, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (req->response[0U]) + { + return kStatus_SDSPI_ResponseError; + } +#endif + + memset(&command, 0U, sizeof(sdspi_command_t)); + command.index = kSDMMC_WriteMultipleBlock; + command.argument = offset; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (command.response[0U]) + { + return kStatus_SDSPI_ResponseError; + } + + for (i = 0U; i < blockCount; i++) + { + if (kStatus_Success != SDSPI_Write(host, buffer, card->blockSize, kSDSPI_DataTokenMultipleBlockWrite)) + { + return kStatus_SDSPI_WriteFailed; + } + buffer += card->blockSize; + } + if (kStatus_Success != SDSPI_Write(host, 0U, 0U, kSDSPI_DataTokenStopTransfer)) + { + return kStatus_SDSPI_WriteFailed; + } + + /* Wait the card programming end. */ + if (kStatus_Success != SDSPI_WaitReady(host, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_WaitReadyFailed; + } + } + + return kStatus_Success; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.h new file mode 100644 index 0000000000000000000000000000000000000000..ee5c8a71f7231c18fd3371edfcc51e5a8c6854cc --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SDSPI_H_ +#define _FSL_SDSPI_H_ + +#include "fsl_common.h" +#include "fsl_specification.h" + +/****************************************************************************** + * Definitions + *****************************************************************************/ +/*! @brief Driver version. */ +#define FSL_SDSPI_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 1U)) /*2.1.1*/ + +/*! @brief Default block size */ +#define FSL_SDSPI_DEFAULT_BLOCK_SIZE (512U) + +/*! + * @addtogroup SDSPI + * @{ + */ + +/*! @brief SDSPI API status */ +enum _sdspi_status +{ + kStatus_SDSPI_SetFrequencyFailed = MAKE_STATUS(kStatusGroup_SDSPI, 0U), /*!< Set frequency failed */ + kStatus_SDSPI_ExchangeFailed = MAKE_STATUS(kStatusGroup_SDSPI, 1U), /*!< Exchange data on SPI bus failed */ + kStatus_SDSPI_WaitReadyFailed = MAKE_STATUS(kStatusGroup_SDSPI, 2U), /*!< Wait card ready failed */ + kStatus_SDSPI_ResponseError = MAKE_STATUS(kStatusGroup_SDSPI, 3U), /*!< Response is error */ + kStatus_SDSPI_WriteProtected = MAKE_STATUS(kStatusGroup_SDSPI, 4U), /*!< Write protected */ + kStatus_SDSPI_GoIdleFailed = MAKE_STATUS(kStatusGroup_SDSPI, 5U), /*!< Go idle failed */ + kStatus_SDSPI_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDSPI, 6U), /*!< Send command failed */ + kStatus_SDSPI_ReadFailed = MAKE_STATUS(kStatusGroup_SDSPI, 7U), /*!< Read data failed */ + kStatus_SDSPI_WriteFailed = MAKE_STATUS(kStatusGroup_SDSPI, 8U), /*!< Write data failed */ + kStatus_SDSPI_SendInterfaceConditionFailed = + MAKE_STATUS(kStatusGroup_SDSPI, 9U), /*!< Send interface condition failed */ + kStatus_SDSPI_SendOperationConditionFailed = + MAKE_STATUS(kStatusGroup_SDSPI, 10U), /*!< Send operation condition failed */ + kStatus_SDSPI_ReadOcrFailed = MAKE_STATUS(kStatusGroup_SDSPI, 11U), /*!< Read OCR failed */ + kStatus_SDSPI_SetBlockSizeFailed = MAKE_STATUS(kStatusGroup_SDSPI, 12U), /*!< Set block size failed */ + kStatus_SDSPI_SendCsdFailed = MAKE_STATUS(kStatusGroup_SDSPI, 13U), /*!< Send CSD failed */ + kStatus_SDSPI_SendCidFailed = MAKE_STATUS(kStatusGroup_SDSPI, 14U), /*!< Send CID failed */ + kStatus_SDSPI_StopTransmissionFailed = MAKE_STATUS(kStatusGroup_SDSPI, 15U), /*!< Stop transmission failed */ + kStatus_SDSPI_SendApplicationCommandFailed = + MAKE_STATUS(kStatusGroup_SDSPI, 16U), /*!< Send application command failed */ +}; + +/*! @brief SDSPI card flag */ +enum _sdspi_card_flag +{ + kSDSPI_SupportHighCapacityFlag = (1U << 0U), /*!< Card is high capacity */ + kSDSPI_SupportSdhcFlag = (1U << 1U), /*!< Card is SDHC */ + kSDSPI_SupportSdxcFlag = (1U << 2U), /*!< Card is SDXC */ + kSDSPI_SupportSdscFlag = (1U << 3U), /*!< Card is SDSC */ +}; + +/*! @brief SDSPI response type */ +typedef enum _sdspi_response_type +{ + kSDSPI_ResponseTypeR1 = 0U, /*!< Response 1 */ + kSDSPI_ResponseTypeR1b = 1U, /*!< Response 1 with busy */ + kSDSPI_ResponseTypeR2 = 2U, /*!< Response 2 */ + kSDSPI_ResponseTypeR3 = 3U, /*!< Response 3 */ + kSDSPI_ResponseTypeR7 = 4U, /*!< Response 7 */ +} sdspi_response_type_t; + +/*! @brief SDSPI command */ +typedef struct _sdspi_command +{ + uint8_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + uint8_t responseType; /*!< Response type */ + uint8_t response[5U]; /*!< Response content */ +} sdspi_command_t; + +/*! @brief SDSPI host state. */ +typedef struct _sdspi_host +{ + uint32_t busBaudRate; /*!< Bus baud rate */ + + status_t (*setFrequency)(uint32_t frequency); /*!< Set frequency of SPI */ + status_t (*exchange)(uint8_t *in, uint8_t *out, uint32_t size); /*!< Exchange data over SPI */ + uint32_t (*getCurrentMilliseconds)(void); /*!< Get current time in milliseconds */ +} sdspi_host_t; + +/*! + * @brief SD Card Structure + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _sdspi_card +{ + sdspi_host_t *host; /*!< Host state information */ + uint32_t relativeAddress; /*!< Relative address of the card */ + uint32_t flags; /*!< Flags defined in _sdspi_card_flag. */ + uint8_t rawCid[16U]; /*!< Raw CID content */ + uint8_t rawCsd[16U]; /*!< Raw CSD content */ + uint8_t rawScr[8U]; /*!< Raw SCR content */ + uint32_t ocr; /*!< Raw OCR content */ + sd_cid_t cid; /*!< CID */ + sd_csd_t csd; /*!< CSD */ + sd_scr_t scr; /*!< SCR */ + uint32_t blockCount; /*!< Card total block number */ + uint32_t blockSize; /*!< Card block size */ +} sdspi_card_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SDSPI Function + * @{ + */ + +/*! + * @brief Initializes the card on a specific SPI instance. + * + * This function initializes the card on a specific SPI instance. + * + * @param card Card descriptor + * @retval kStatus_SDSPI_SetFrequencyFailed Set frequency failed. + * @retval kStatus_SDSPI_GoIdleFailed Go idle failed. + * @retval kStatus_SDSPI_SendInterfaceConditionFailed Send interface condition failed. + * @retval kStatus_SDSPI_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_Timeout Send command timeout. + * @retval kStatus_SDSPI_NotSupportYet Not support yet. + * @retval kStatus_SDSPI_ReadOcrFailed Read OCR failed. + * @retval kStatus_SDSPI_SetBlockSizeFailed Set block size failed. + * @retval kStatus_SDSPI_SendCsdFailed Send CSD failed. + * @retval kStatus_SDSPI_SendCidFailed Send CID failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDSPI_Init(sdspi_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * This function deinitializes the specific card. + * + * @param card Card descriptor + */ +void SDSPI_Deinit(sdspi_card_t *card); + +/*! + * @brief Checks whether the card is write-protected. + * + * This function checks if the card is write-protected via CSD register. + * + * @param card Card descriptor. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool SDSPI_CheckReadOnly(sdspi_card_t *card); + +/*! + * @brief Reads blocks from the specific card. + * + * This function reads blocks from specific card. + * + * @param card Card descriptor. + * @param buffer the buffer to hold the data read from card + * @param startBlock the start block index + * @param blockCount the number of blocks to read + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ReadFailed Read data failed. + * @retval kStatus_SDSPI_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDSPI_ReadBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes blocks of data to the specific card. + * + * This function writes blocks to specific card + * + * @param card Card descriptor. + * @param buffer the buffer holding the data to be written to the card + * @param startBlock the start block index + * @param blockCount the number of blocks to write + * @retval kStatus_SDSPI_WriteProtected Card is write protected. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_SDSPI_WriteFailed Write data failed. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_SDSPI_WaitReadyFailed Wait card to be ready status failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDSPI_WriteBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* _FSL_SDSPI_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_specification.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_specification.h new file mode 100644 index 0000000000000000000000000000000000000000..1320b202291d189cc5cd831b03aa4b8f07700809 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_specification.h @@ -0,0 +1,1080 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SPECIFICATION_H_ +#define _FSL_SPECIFICATION_H_ + +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief SD/MMC card initialization clock frequency */ +#define SDMMC_CLOCK_400KHZ (400000U) +/*! @brief SD card bus frequency 1 in high-speed mode */ +#define SD_CLOCK_25MHZ (25000000U) +/*! @brief SD card bus frequency 2 in high-speed mode */ +#define SD_CLOCK_50MHZ (50000000U) +/*! @brief SD card bus frequency in SDR50 mode */ +#define SD_CLOCK_100MHZ (100000000U) +/*! @brief SD card bus frequency in SDR104 mode */ +#define SD_CLOCK_208MHZ (208000000U) +/*! @brief MMC card bus frequency 1 in high-speed mode */ +#define MMC_CLOCK_26MHZ (26000000U) +/*! @brief MMC card bus frequency 2 in high-speed mode */ +#define MMC_CLOCK_52MHZ (52000000U) +/*! @brief MMC card bus frequency in high-speed DDR52 mode */ +#define MMC_CLOCK_DDR52 (104000000U) +/*! @brief MMC card bus frequency in high-speed HS200 mode */ +#define MMC_CLOCK_HS200 (200000000U) +/*! @brief MMC card bus frequency in high-speed HS400 mode */ +#define MMC_CLOCK_HS400 (400000000U) + +/*! @brief Card status bit in R1 */ +enum _sdmmc_r1_card_status_flag +{ + kSDMMC_R1OutOfRangeFlag = (1U << 31U), /*!< Out of range status bit */ + kSDMMC_R1AddressErrorFlag = (1U << 30U), /*!< Address error status bit */ + kSDMMC_R1BlockLengthErrorFlag = (1U << 29U), /*!< Block length error status bit */ + kSDMMC_R1EraseSequenceErrorFlag = (1U << 28U), /*!< Erase sequence error status bit */ + kSDMMC_R1EraseParameterErrorFlag = (1U << 27U), /*!< Erase parameter error status bit */ + kSDMMC_R1WriteProtectViolationFlag = (1U << 26U), /*!< Write protection violation status bit */ + kSDMMC_R1CardIsLockedFlag = (1U << 25U), /*!< Card locked status bit */ + kSDMMC_R1LockUnlockFailedFlag = (1U << 24U), /*!< lock/unlock error status bit */ + kSDMMC_R1CommandCrcErrorFlag = (1U << 23U), /*!< CRC error status bit */ + kSDMMC_R1IllegalCommandFlag = (1U << 22U), /*!< Illegal command status bit */ + kSDMMC_R1CardEccFailedFlag = (1U << 21U), /*!< Card ecc error status bit */ + kSDMMC_R1CardControllerErrorFlag = (1U << 20U), /*!< Internal card controller error status bit */ + kSDMMC_R1ErrorFlag = (1U << 19U), /*!< A general or an unknown error status bit */ + kSDMMC_R1CidCsdOverwriteFlag = (1U << 16U), /*!< Cid/csd overwrite status bit */ + kSDMMC_R1WriteProtectEraseSkipFlag = (1U << 15U), /*!< Write protection erase skip status bit */ + kSDMMC_R1CardEccDisabledFlag = (1U << 14U), /*!< Card ecc disabled status bit */ + kSDMMC_R1EraseResetFlag = (1U << 13U), /*!< Erase reset status bit */ + kSDMMC_R1ReadyForDataFlag = (1U << 8U), /*!< Ready for data status bit */ + kSDMMC_R1SwitchErrorFlag = (1U << 7U), /*!< Switch error status bit */ + kSDMMC_R1ApplicationCommandFlag = (1U << 5U), /*!< Application command enabled status bit */ + kSDMMC_R1AuthenticationSequenceErrorFlag = (1U << 3U), /*!< error in the sequence of authentication process */ + + kSDMMC_R1ErrorAllFlag = + (kSDMMC_R1OutOfRangeFlag | kSDMMC_R1AddressErrorFlag | kSDMMC_R1BlockLengthErrorFlag | + kSDMMC_R1EraseSequenceErrorFlag | kSDMMC_R1EraseParameterErrorFlag | kSDMMC_R1WriteProtectViolationFlag | + kSDMMC_R1CardIsLockedFlag | kSDMMC_R1LockUnlockFailedFlag | kSDMMC_R1CommandCrcErrorFlag | + kSDMMC_R1IllegalCommandFlag | kSDMMC_R1CardEccFailedFlag | kSDMMC_R1CardControllerErrorFlag | + kSDMMC_R1ErrorFlag | kSDMMC_R1CidCsdOverwriteFlag | + kSDMMC_R1AuthenticationSequenceErrorFlag), /*!< Card error status */ +}; + +/*! @brief R1: current state */ +#define SDMMC_R1_CURRENT_STATE(x) (((x)&0x00001E00U) >> 9U) + +/*! @brief CURRENT_STATE filed in R1 */ +typedef enum _sdmmc_r1_current_state +{ + kSDMMC_R1StateIdle = 0U, /*!< R1: current state: idle */ + kSDMMC_R1StateReady = 1U, /*!< R1: current state: ready */ + kSDMMC_R1StateIdentify = 2U, /*!< R1: current state: identification */ + kSDMMC_R1StateStandby = 3U, /*!< R1: current state: standby */ + kSDMMC_R1StateTransfer = 4U, /*!< R1: current state: transfer */ + kSDMMC_R1StateSendData = 5U, /*!< R1: current state: sending data */ + kSDMMC_R1StateReceiveData = 6U, /*!< R1: current state: receiving data */ + kSDMMC_R1StateProgram = 7U, /*!< R1: current state: programming */ + kSDMMC_R1StateDisconnect = 8U, /*!< R1: current state: disconnect */ +} sdmmc_r1_current_state_t; + +/*! @brief Error bit in SPI mode R1 */ +enum _sdspi_r1_error_status_flag +{ + kSDSPI_R1InIdleStateFlag = (1U << 0U), /*!< In idle state */ + kSDSPI_R1EraseResetFlag = (1U << 1U), /*!< Erase reset */ + kSDSPI_R1IllegalCommandFlag = (1U << 2U), /*!< Illegal command */ + kSDSPI_R1CommandCrcErrorFlag = (1U << 3U), /*!< Com crc error */ + kSDSPI_R1EraseSequenceErrorFlag = (1U << 4U), /*!< Erase sequence error */ + kSDSPI_R1AddressErrorFlag = (1U << 5U), /*!< Address error */ + kSDSPI_R1ParameterErrorFlag = (1U << 6U), /*!< Parameter error */ +}; + +/*! @brief Error bit in SPI mode R2 */ +enum _sdspi_r2_error_status_flag +{ + kSDSPI_R2CardLockedFlag = (1U << 0U), /*!< Card is locked */ + kSDSPI_R2WriteProtectEraseSkip = (1U << 1U), /*!< Write protect erase skip */ + kSDSPI_R2LockUnlockFailed = (1U << 1U), /*!< Lock/unlock command failed */ + kSDSPI_R2ErrorFlag = (1U << 2U), /*!< Unknown error */ + kSDSPI_R2CardControllerErrorFlag = (1U << 3U), /*!< Card controller error */ + kSDSPI_R2CardEccFailedFlag = (1U << 4U), /*!< Card ecc failed */ + kSDSPI_R2WriteProtectViolationFlag = (1U << 5U), /*!< Write protect violation */ + kSDSPI_R2EraseParameterErrorFlag = (1U << 6U), /*!< Erase parameter error */ + kSDSPI_R2OutOfRangeFlag = (1U << 7U), /*!< Out of range */ + kSDSPI_R2CsdOverwriteFlag = (1U << 7U), /*!< CSD overwrite */ +}; + +/*! @brief The bit mask for COMMAND VERSION field in R7 */ +#define SDSPI_R7_VERSION_SHIFT (28U) +/*! @brief The bit mask for COMMAND VERSION field in R7 */ +#define SDSPI_R7_VERSION_MASK (0xFU) +/*! @brief The bit shift for VOLTAGE ACCEPTED field in R7 */ +#define SDSPI_R7_VOLTAGE_SHIFT (8U) +/*! @brief The bit mask for VOLTAGE ACCEPTED field in R7 */ +#define SDSPI_R7_VOLTAGE_MASK (0xFU) +/*! @brief The bit mask for VOLTAGE 2.7V to 3.6V field in R7 */ +#define SDSPI_R7_VOLTAGE_27_36_MASK (0x1U << SDSPI_R7_VOLTAGE_SHIFT) +/*! @brief The bit shift for ECHO field in R7 */ +#define SDSPI_R7_ECHO_SHIFT (0U) +/*! @brief The bit mask for ECHO field in R7 */ +#define SDSPI_R7_ECHO_MASK (0xFFU) + +/*! @brief Data error token mask */ +#define SDSPI_DATA_ERROR_TOKEN_MASK (0xFU) +/*! @brief Data Error Token mask bit */ +enum _sdspi_data_error_token +{ + kSDSPI_DataErrorTokenError = (1U << 0U), /*!< Data error */ + kSDSPI_DataErrorTokenCardControllerError = (1U << 1U), /*!< Card controller error */ + kSDSPI_DataErrorTokenCardEccFailed = (1U << 2U), /*!< Card ecc error */ + kSDSPI_DataErrorTokenOutOfRange = (1U << 3U), /*!< Out of range */ +}; + +/*! @brief Data Token */ +typedef enum _sdspi_data_token +{ + kSDSPI_DataTokenBlockRead = 0xFEU, /*!< Single block read, multiple block read */ + kSDSPI_DataTokenSingleBlockWrite = 0xFEU, /*!< Single block write */ + kSDSPI_DataTokenMultipleBlockWrite = 0xFCU, /*!< Multiple block write */ + kSDSPI_DataTokenStopTransfer = 0xFDU, /*!< Stop transmission */ +} sdspi_data_token_t; + +/* Data Response Token mask */ +#define SDSPI_DATA_RESPONSE_TOKEN_MASK (0x1FU) /*!< Mask for data response bits */ +/*! @brief Data Response Token */ +typedef enum _sdspi_data_response_token +{ + kSDSPI_DataResponseTokenAccepted = 0x05U, /*!< Data accepted */ + kSDSPI_DataResponseTokenCrcError = 0x0BU, /*!< Data rejected due to CRC error */ + kSDSPI_DataResponseTokenWriteError = 0x0DU, /*!< Data rejected due to write error */ +} sdspi_data_response_token_t; + +/*! @brief SD card individual commands */ +typedef enum _sd_command +{ + kSD_SendRelativeAddress = 3U, /*!< Send Relative Address */ + kSD_Switch = 6U, /*!< Switch Function */ + kSD_SendInterfaceCondition = 8U, /*!< Send Interface Condition */ + kSD_VoltageSwitch = 11U, /*!< Voltage Switch */ + kSD_SpeedClassControl = 20U, /*!< Speed Class control */ + kSD_EraseWriteBlockStart = 32U, /*!< Write Block Start */ + kSD_EraseWriteBlockEnd = 33U, /*!< Write Block End */ + kSD_SendTuningBlock = 19U, /*!< Send Tuning Block */ +} sd_command_t; + +/*! @brief SD card individual application commands */ +typedef enum _sd_application_command +{ + kSD_ApplicationSetBusWdith = 6U, /*!< Set Bus Width */ + kSD_ApplicationStatus = 13U, /*!< Send SD status */ + kSD_ApplicationSendNumberWriteBlocks = 22U, /*!< Send Number Of Written Blocks */ + kSD_ApplicationSetWriteBlockEraseCount = 23U, /*!< Set Write Block Erase Count */ + kSD_ApplicationSendOperationCondition = 41U, /*!< Send Operation Condition */ + kSD_ApplicationSetClearCardDetect = 42U, /*!< Set Connnect/Disconnect pull up on detect pin */ + kSD_ApplicationSendScr = 51U, /*!< Send Scr */ +} sd_application_command_t; + +/*! @brief SD card command class */ +enum _sdmmc_command_class +{ + kSDMMC_CommandClassBasic = (1U << 0U), /*!< Card command class 0 */ + kSDMMC_CommandClassBlockRead = (1U << 2U), /*!< Card command class 2 */ + kSDMMC_CommandClassBlockWrite = (1U << 4U), /*!< Card command class 4 */ + kSDMMC_CommandClassErase = (1U << 5U), /*!< Card command class 5 */ + kSDMMC_CommandClassWriteProtect = (1U << 6U), /*!< Card command class 6 */ + kSDMMC_CommandClassLockCard = (1U << 7U), /*!< Card command class 7 */ + kSDMMC_CommandClassApplicationSpecific = (1U << 8U), /*!< Card command class 8 */ + kSDMMC_CommandClassInputOutputMode = (1U << 9U), /*!< Card command class 9 */ + kSDMMC_CommandClassSwitch = (1U << 10U), /*!< Card command class 10 */ +}; + +/*! @brief OCR register in SD card */ +enum _sd_ocr_flag +{ + kSD_OcrPowerUpBusyFlag = (1U << 31U), /*!< Power up busy status */ + kSD_OcrHostCapacitySupportFlag = (1U << 30U), /*!< Card capacity status */ + kSD_OcrCardCapacitySupportFlag = kSD_OcrHostCapacitySupportFlag, /*!< Card capacity status */ + kSD_OcrSwitch18RequestFlag = (1U << 24U), /*!< Switch to 1.8V request */ + kSD_OcrSwitch18AcceptFlag = kSD_OcrSwitch18RequestFlag, /*!< Switch to 1.8V accepted */ + kSD_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ + kSD_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ + kSD_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ + kSD_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ + kSD_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ + kSD_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ + kSD_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ + kSD_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ + kSD_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ +}; + +/*! @brief SD card specification version number */ +enum _sd_specification_version +{ + kSD_SpecificationVersion1_0 = (1U << 0U), /*!< SD card version 1.0-1.01 */ + kSD_SpecificationVersion1_1 = (1U << 1U), /*!< SD card version 1.10 */ + kSD_SpecificationVersion2_0 = (1U << 2U), /*!< SD card version 2.00 */ + kSD_SpecificationVersion3_0 = (1U << 3U), /*!< SD card version 3.0 */ +}; + +/*! @brief SD card bus width */ +typedef enum _sd_data_bus_width +{ + kSD_DataBusWidth1Bit = 0U, /*!< SD data bus width 1-bit mode */ + kSD_DataBusWidth4Bit = 1U, /*!< SD data bus width 4-bit mode */ +} sd_data_bus_width_t; + +/*! @brief SD card switch mode */ +typedef enum _sd_switch_mode +{ + kSD_SwitchCheck = 0U, /*!< SD switch mode 0: check function */ + kSD_SwitchSet = 1U, /*!< SD switch mode 1: set function */ +} sd_switch_mode_t; + +/*! @brief SD card CSD register flags */ +enum _sd_csd_flag +{ + kSD_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed [79:79] */ + kSD_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment [78:78] */ + kSD_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment [77:77] */ + kSD_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented [76:76] */ + kSD_CsdEraseBlockEnabledFlag = (1U << 4U), /*!< Erase single block enabled [46:46] */ + kSD_CsdWriteProtectGroupEnabledFlag = (1U << 5U), /*!< Write protect group enabled [31:31] */ + kSD_CsdWriteBlockPartialFlag = (1U << 6U), /*!< Partial blocks for write allowed [21:21] */ + kSD_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group [15:15] */ + kSD_CsdCopyFlag = (1U << 8U), /*!< Copy flag [14:14] */ + kSD_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection [13:13] */ + kSD_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection [12:12] */ +}; + +/*! @brief SD card SCR register flags */ +enum _sd_scr_flag +{ + kSD_ScrDataStatusAfterErase = (1U << 0U), /*!< Data status after erases [55:55] */ + kSD_ScrSdSpecification3 = (1U << 1U), /*!< Specification version 3.00 or higher [47:47]*/ +}; + +/*! @brief SD timing function number */ +enum _sd_timing_function +{ + kSD_FunctionSDR12Deafult = 0U, /*!< SDR12 mode & default*/ + kSD_FunctionSDR25HighSpeed = 1U, /*!< SDR25 & high speed*/ + kSD_FunctionSDR50 = 2U, /*!< SDR50 mode*/ + kSD_FunctionSDR104 = 3U, /*!< SDR104 mode*/ + kSD_FunctionDDR50 = 4U, /*!< DDR50 mode*/ +}; + +/*! @brief SD group number */ +enum _sd_group_num +{ + kSD_GroupTimingMode = 0U, /*!< acess mode group*/ + kSD_GroupCommandSystem = 1U, /*!< command system group*/ + kSD_GroupDriverStrength = 2U, /*!< driver strength group*/ + kSD_GroupCurrentLimit = 3U, /*!< current limit group*/ +}; + +/*! @brief SD card timing mode flags */ +typedef enum _sd_timing_mode +{ + kSD_TimingSDR12DefaultMode = 0U, /*!< Identification mode & SDR12 */ + kSD_TimingSDR25HighSpeedMode = 1U, /*!< High speed mode & SDR25 */ + kSD_TimingSDR50Mode = 2U, /*!< SDR50 mode*/ + kSD_TimingSDR104Mode = 3U, /*!< SDR104 mode */ + kSD_TimingDDR50Mode = 4U, /*!< DDR50 mode */ +} sd_timing_mode_t; + +/*! @brief SD card driver strength */ +typedef enum _sd_driver_strength +{ + kSD_DriverStrengthTypeB = 0U, /*!< default driver strength*/ + kSD_DriverStrengthTypeA = 1U, /*!< driver strength TYPE A */ + kSD_DriverStrengthTypeC = 2U, /*!< driver strength TYPE C */ + kSD_DriverStrengthTypeD = 3U, /*!< driver strength TYPE D */ +} sd_driver_strength_t; + +/*! @brief SD card current limit */ +typedef enum _sd_max_current +{ + kSD_CurrentLimit200MA = 0U, /*!< default current limit */ + kSD_CurrentLimit400MA = 1U, /*!< current limit to 400MA */ + kSD_CurrentLimit600MA = 2U, /*!< current limit to 600MA */ + kSD_CurrentLimit800MA = 3U, /*!< current limit to 800MA */ +} sd_max_current_t; + +/*! @brief SD/MMC card common commands */ +typedef enum _sdmmc_command +{ + kSDMMC_GoIdleState = 0U, /*!< Go Idle State */ + kSDMMC_AllSendCid = 2U, /*!< All Send CID */ + kSDMMC_SetDsr = 4U, /*!< Set DSR */ + kSDMMC_SelectCard = 7U, /*!< Select Card */ + kSDMMC_SendCsd = 9U, /*!< Send CSD */ + kSDMMC_SendCid = 10U, /*!< Send CID */ + kSDMMC_StopTransmission = 12U, /*!< Stop Transmission */ + kSDMMC_SendStatus = 13U, /*!< Send Status */ + kSDMMC_GoInactiveState = 15U, /*!< Go Inactive State */ + kSDMMC_SetBlockLength = 16U, /*!< Set Block Length */ + kSDMMC_ReadSingleBlock = 17U, /*!< Read Single Block */ + kSDMMC_ReadMultipleBlock = 18U, /*!< Read Multiple Block */ + kSDMMC_SetBlockCount = 23U, /*!< Set Block Count */ + kSDMMC_WriteSingleBlock = 24U, /*!< Write Single Block */ + kSDMMC_WriteMultipleBlock = 25U, /*!< Write Multiple Block */ + kSDMMC_ProgramCsd = 27U, /*!< Program CSD */ + kSDMMC_SetWriteProtect = 28U, /*!< Set Write Protect */ + kSDMMC_ClearWriteProtect = 29U, /*!< Clear Write Protect */ + kSDMMC_SendWriteProtect = 30U, /*!< Send Write Protect */ + kSDMMC_Erase = 38U, /*!< Erase */ + kSDMMC_LockUnlock = 42U, /*!< Lock Unlock */ + kSDMMC_ApplicationCommand = 55U, /*!< Send Application Command */ + kSDMMC_GeneralCommand = 56U, /*!< General Purpose Command */ + kSDMMC_ReadOcr = 58U, /*!< Read OCR */ +} sdmmc_command_t; + +/*! @brief sdio card cccr register addr */ +enum _sdio_cccr_reg +{ + kSDIO_RegCCCRSdioVer = 0x00U, /*!< CCCR & SDIO version*/ + kSDIO_RegSDVersion = 0x01U, /*!< SD version */ + kSDIO_RegIOEnable = 0x02U, /*!< io enable register */ + kSDIO_RegIOReady = 0x03U, /*!< io ready register */ + kSDIO_RegIOIntEnable = 0x04U, /*!< io interrupt enable register */ + kSDIO_RegIOIntPending = 0x05U, /*!< io interrupt pending register */ + kSDIO_RegIOAbort = 0x06U, /*!< io abort register */ + kSDIO_RegBusInterface = 0x07U, /*!< bus interface register */ + kSDIO_RegCardCapability = 0x08U, /*!< card capability register */ + kSDIO_RegCommonCISPointer = 0x09U, /*!< common CIS pointer register */ + kSDIO_RegBusSuspend = 0x0C, /*!< bus suspend register */ + kSDIO_RegFunctionSelect = 0x0DU, /*!< function select register */ + kSDIO_RegExecutionFlag = 0x0EU, /*!< execution flag register */ + kSDIO_RegReadyFlag = 0x0FU, /*!< ready flag register */ + kSDIO_RegFN0BlockSizeLow = 0x10U, /*!< FN0 block size register */ + kSDIO_RegFN0BlockSizeHigh = 0x11U, /*!< FN0 block size register */ + kSDIO_RegPowerControl = 0x12U, /*!< power control register */ + kSDIO_RegHighSpeed = 0x13U, /*!< high speed register */ +}; + +/*! @brief sdio card individual commands */ +typedef enum _sdio_command +{ + kSDIO_SendRelativeAddress = 3U, /*!< send relative address */ + kSDIO_SendOperationCondition = 5U, /*!< send operation condition */ + kSDIO_SendInterfaceCondition = 8U, /*!< send interface condition */ + kSDIO_RWIODirect = 52U, /*!< read/write IO direct command */ + kSDIO_RWIOExtended = 53U, /*!< read/write IO extended command */ +} sdio_command_t; + +/*! @brief sdio card individual commands */ +typedef enum _sdio_func_num +{ + kSDIO_FunctionNum0, /*!< sdio function0*/ + kSDIO_FunctionNum1, /*!< sdio function1*/ + kSDIO_FunctionNum2, /*!< sdio function2*/ + kSDIO_FunctionNum3, /*!< sdio function3*/ + kSDIO_FunctionNum4, /*!< sdio function4*/ + kSDIO_FunctionNum5, /*!< sdio function5*/ + kSDIO_FunctionNum6, /*!< sdio function6*/ + kSDIO_FunctionNum7, /*!< sdio function7*/ + kSDIO_FunctionMemory, /*!< for combo card*/ +} sdio_func_num_t; + +#define SDIO_CMD_ARGUMENT_RW_POS (31U) /*!< read/write flag position */ +#define SDIO_CMD_ARGUMENT_FUNC_NUM_POS (28U) /*!< function number position */ +#define SDIO_DIRECT_CMD_ARGUMENT_RAW_POS (27U) /*!< direct raw flag position */ +#define SDIO_CMD_ARGUMENT_REG_ADDR_POS (9U) /*!< direct reg addr position */ +#define SDIO_CMD_ARGUMENT_REG_ADDR_MASK (0x1FFFFU) /*!< direct reg addr mask */ +#define SDIO_DIRECT_CMD_DATA_MASK (0xFFU) /*!< data mask */ + +#define SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS (27U) /*!< extended command argument block mode bit position */ +#define SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS (26U) /*!< extended command argument OP Code bit position */ +#define SDIO_EXTEND_CMD_BLOCK_MODE_MASK (0x08000000U) /*!< block mode mask */ +#define SDIO_EXTEND_CMD_OP_CODE_MASK (0x04000000U) /*!< op code mask */ +#define SDIO_EXTEND_CMD_COUNT_MASK (0x1FFU) /*!< byte/block count mask */ +#define SDIO_MAX_BLOCK_SIZE (2048U) /*!< max block size */ +#define SDIO_FBR_BASE(x) (x * 0x100U) /*!< function basic register */ +#define SDIO_TPL_CODE_END (0xFFU) /*!< tuple end */ +#define SDIO_TPL_CODE_MANIFID (0x20U) /*!< manufacturer ID */ +#define SDIO_TPL_CODE_FUNCID (0x21U) /*!< function ID */ +#define SDIO_TPL_CODE_FUNCE (0x22U) /*!< function extension tuple*/ +/*! @brief sdio command response flag */ +enum _sdio_status_flag +{ + kSDIO_StatusCmdCRCError = 0x8000U, /*!< the CRC check of the previous cmd fail*/ + kSDIO_StatusIllegalCmd = 0x4000U, /*!< cmd illegal for the card state */ + kSDIO_StatusR6Error = 0x2000U, /*!< special for R6 error status */ + kSDIO_StatusError = 0x0800U, /*!< A general or an unknown error occurred */ + kSDIO_StatusFunctionNumError = 0x0200U, /*!< invail function error */ + kSDIO_StatusOutofRange = 0x0100U, /*!< cmd argument was out of the allowed range*/ +}; + +/*! @brief sdio operation condition flag */ +enum _sdio_ocr_flag +{ + kSDIO_OcrPowerUpBusyFlag = (1U << 31U), /*!< Power up busy status */ + kSDIO_OcrIONumber = (7U << 28U), /*!< number of IO function */ + kSDIO_OcrMemPresent = (1U << 27U), /*!< memory present flag */ + + kSDIO_OcrVdd20_21Flag = (1U << 8U), /*!< VDD 2.0-2.1 */ + kSDIO_OcrVdd21_22Flag = (1U << 9U), /*!< VDD 2.1-2.2 */ + kSDIO_OcrVdd22_23Flag = (1U << 10U), /*!< VDD 2.2-2.3 */ + kSDIO_OcrVdd23_24Flag = (1U << 11U), /*!< VDD 2.3-2.4 */ + kSDIO_OcrVdd24_25Flag = (1U << 12U), /*!< VDD 2.4-2.5 */ + kSDIO_OcrVdd25_26Flag = (1U << 13U), /*!< VDD 2.5-2.6 */ + kSDIO_OcrVdd26_27Flag = (1U << 14U), /*!< VDD 2.6-2.7 */ + kSDIO_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ + kSDIO_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ + kSDIO_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ + kSDIO_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ + kSDIO_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ + kSDIO_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ + kSDIO_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ + kSDIO_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ + kSDIO_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ + +}; + +/*! @brief sdio capability flag */ +enum _sdio_capability_flag +{ + kSDIO_CCCRSupportDirectCmdDuringDataTrans = (1U << 0U), /*!< support direct cmd during data transfer */ + kSDIO_CCCRSupportMultiBlock = (1U << 1U), /*!< support multi block mode */ + kSDIO_CCCRSupportReadWait = (1U << 2U), /*!< support read wait */ + kSDIO_CCCRSupportSuspendResume = (1U << 3U), /*!< support suspend resume */ + kSDIO_CCCRSupportIntDuring4BitDataTrans = (1U << 4U), /*!< support interrupt during 4-bit data transfer */ + kSDIO_CCCRSupportLowSpeed1Bit = (1U << 6U), /*!< support low speed 1bit mode */ + kSDIO_CCCRSupportLowSpeed4Bit = (1U << 7U), /*!< support low speed 4bit mode */ + kSDIO_CCCRSupportMasterPowerControl = (1U << 8U), /*!< support master power control */ + kSDIO_CCCRSupportHighSpeed = (1U << 9U), /*!< support high speed */ + kSDIO_CCCRSupportContinuousSPIInt = (1U << 10U), /*!< support continuous SPI interrupt */ + kSDIO_FBRSupportCSA = (1U << 11U), /*!< function support CSA */ + kSDIO_FBRSupportPowerSelection = (1U << 12U), /*!< function support power selection */ + +}; + +/*! @brief sdio bus width */ +typedef enum _sdio_bus_width +{ + kSDIO_DataBus1Bit = 0x00U, /*!< 1bit bus mode */ + kSDIO_DataBus4Bit = 0X02U, /*!< 4 bit bus mode*/ +} sdio_bus_width_t; + +/*! @brief MMC card individual commands */ +typedef enum _mmc_command +{ + kMMC_SendOperationCondition = 1U, /*!< Send Operation Condition */ + kMMC_SetRelativeAddress = 3U, /*!< Set Relative Address */ + kMMC_SleepAwake = 5U, /*!< Sleep Awake */ + kMMC_Switch = 6U, /*!< Switch */ + kMMC_SendExtendedCsd = 8U, /*!< Send EXT_CSD */ + kMMC_ReadDataUntilStop = 11U, /*!< Read Data Until Stop */ + kMMC_BusTestRead = 14U, /*!< Test Read */ + kMMC_SendingBusTest = 19U, /*!< test bus width cmd*/ + kMMC_WriteDataUntilStop = 20U, /*!< Write Data Until Stop */ + kMMC_SendTuningBlock = 21U, /*!< MMC sending tuning block */ + kMMC_ProgramCid = 26U, /*!< Program CID */ + kMMC_EraseGroupStart = 35U, /*!< Erase Group Start */ + kMMC_EraseGroupEnd = 36U, /*!< Erase Group End */ + kMMC_FastInputOutput = 39U, /*!< Fast IO */ + kMMC_GoInterruptState = 40U, /*!< Go interrupt State */ +} mmc_command_t; + +/*! @brief MMC card classified as voltage range */ +typedef enum _mmc_classified_voltage +{ + kMMC_ClassifiedVoltageHigh = 0U, /*!< High-voltage MMC card */ + kMMC_ClassifiedVoltageDual = 1U, /*!< Dual-voltage MMC card */ +} mmc_classified_voltage_t; + +/*! @brief MMC card classified as density level */ +typedef enum _mmc_classified_density +{ + kMMC_ClassifiedDensityWithin2GB = 0U, /*!< Density byte is less than or equal 2GB */ + kMMC_ClassifiedDensityHigher2GB = 1U, /* Density byte is higher than 2GB */ +} mmc_classified_density_t; + +/*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ +#define MMC_OCR_V170TO195_SHIFT (7U) +/*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ +#define MMC_OCR_V170TO195_MASK (0x00000080U) +/*! @brief The bit shift for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ +#define MMC_OCR_V200TO260_SHIFT (8U) +/*! @brief The bit mask for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ +#define MMC_OCR_V200TO260_MASK (0x00007F00U) +/*! @brief The bit shift for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ +#define MMC_OCR_V270TO360_SHIFT (15U) +/*! @brief The bit mask for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ +#define MMC_OCR_V270TO360_MASK (0x00FF8000U) +/*! @brief The bit shift for ACCESS MODE field in OCR */ +#define MMC_OCR_ACCESS_MODE_SHIFT (29U) +/*! @brief The bit mask for ACCESS MODE field in OCR */ +#define MMC_OCR_ACCESS_MODE_MASK (0x60000000U) +/*! @brief The bit shift for BUSY field in OCR */ +#define MMC_OCR_BUSY_SHIFT (31U) +/*! @brief The bit mask for BUSY field in OCR */ +#define MMC_OCR_BUSY_MASK (1U << MMC_OCR_BUSY_SHIFT) + +/*! @brief MMC card access mode(Access mode in OCR). */ +typedef enum _mmc_access_mode +{ + kMMC_AccessModeByte = 0U, /*!< The card should be accessed as byte */ + kMMC_AccessModeSector = 2U, /*!< The card should be accessed as sector */ +} mmc_access_mode_t; + +/*! @brief MMC card voltage window(VDD voltage window in OCR). */ +typedef enum _mmc_voltage_window +{ + kMMC_VoltageWindowNone = 0U, /*!< voltage window is not define by user*/ + kMMC_VoltageWindow120 = 0x01U, /*!< Voltage window is 1.20V */ + kMMC_VoltageWindow170to195 = 0x02U, /*!< Voltage window is 1.70V to 1.95V */ + kMMC_VoltageWindows270to360 = 0x1FFU, /*!< Voltage window is 2.70V to 3.60V */ +} mmc_voltage_window_t; + +/*! @brief CSD structure version(CSD_STRUCTURE in CSD). */ +typedef enum _mmc_csd_structure_version +{ + kMMC_CsdStrucureVersion10 = 0U, /*!< CSD version No. 1.0 */ + kMMC_CsdStrucureVersion11 = 1U, /*!< CSD version No. 1.1 */ + kMMC_CsdStrucureVersion12 = 2U, /*!< CSD version No. 1.2 */ + kMMC_CsdStrucureVersionInExtcsd = 3U, /*!< Version coded in Extended CSD */ +} mmc_csd_structure_version_t; + +/*! @brief MMC card specification version(SPEC_VERS in CSD). */ +typedef enum _mmc_specification_version +{ + kMMC_SpecificationVersion0 = 0U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion1 = 1U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion2 = 2U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion3 = 3U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion4 = 4U, /*!< Version 4.1/4.2/4.3/4.41-4.5-4.51-5.0 */ +} mmc_specification_version_t; + +/*! @brief The bit shift for FREQUENCY UNIT field in TRANSFER SPEED(TRAN-SPEED in Extended CSD) */ +#define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT (0U) +/*! @brief The bit mask for FRQEUENCY UNIT in TRANSFER SPEED */ +#define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK (0x07U) +/*! @brief The bit shift for MULTIPLIER field in TRANSFER SPEED */ +#define MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT (3U) +/*! @brief The bit mask for MULTIPLIER field in TRANSFER SPEED */ +#define MMC_TRANSFER_SPEED_MULTIPLIER_MASK (0x78U) + +/*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED. */ +#define READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(CSD) \ + (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK) >> MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT) +/*! @brief Read the value of MULTIPLER filed in TRANSFER SPEED. */ +#define READ_MMC_TRANSFER_SPEED_MULTIPLIER(CSD) \ + (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_MULTIPLIER_MASK) >> MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT) + +/*! @brief MMC card Extended CSD fix version(EXT_CSD_REV in Extended CSD) */ +enum _mmc_extended_csd_revision +{ + kMMC_ExtendedCsdRevision10 = 0U, /*!< Revision 1.0 */ + kMMC_ExtendedCsdRevision11 = 1U, /*!< Revision 1.1 */ + kMMC_ExtendedCsdRevision12 = 2U, /*!< Revision 1.2 */ + kMMC_ExtendedCsdRevision13 = 3U, /*!< Revision 1.3 MMC4.3*/ + kMMC_ExtendedCsdRevision14 = 4U, /*!< Revision 1.4 obsolete*/ + kMMC_ExtendedCsdRevision15 = 5U, /*!< Revision 1.5 MMC4.41*/ + kMMC_ExtendedCsdRevision16 = 6U, /*!< Revision 1.6 MMC4.5*/ + kMMC_ExtendedCsdRevision17 = 7U, /*!< Revision 1.7 MMC5.0 */ +}; + +/*! @brief MMC card command set(COMMAND_SET in Extended CSD) */ +typedef enum _mmc_command_set +{ + kMMC_CommandSetStandard = 0U, /*!< Standard MMC */ + kMMC_CommandSet1 = 1U, /*!< Command set 1 */ + kMMC_CommandSet2 = 2U, /*!< Command set 2 */ + kMMC_CommandSet3 = 3U, /*!< Command set 3 */ + kMMC_CommandSet4 = 4U, /*!< Command set 4 */ +} mmc_command_set_t; + +/*! @brief boot support(BOOT_INFO in Extended CSD) */ +enum _mmc_support_boot_mode +{ + kMMC_SupportAlternateBoot = 1U, /*!< support alternative boot mode*/ + kMMC_SupportDDRBoot = 2U, /*!< support DDR boot mode*/ + kMMC_SupportHighSpeedBoot = 4U, /*!< support high speed boot mode*/ +}; +/*! @brief The power class value bit mask when bus in 4 bit mode */ +#define MMC_POWER_CLASS_4BIT_MASK (0x0FU) +/*! @brief The power class current value bit mask when bus in 8 bit mode */ +#define MMC_POWER_CLASS_8BIT_MASK (0xF0U) + +/*! @brief MMC card high-speed timing(HS_TIMING in Extended CSD) */ +typedef enum _mmc_high_speed_timing +{ + kMMC_HighSpeedTimingNone = 0U, /*!< MMC card using none high-speed timing */ + kMMC_HighSpeedTiming = 1U, /*!< MMC card using high-speed timing */ + kMMC_HighSpeed200Timing = 2U, /*!< MMC card high speed 200 timing*/ + kMMC_HighSpeed400Timing = 3U, /*!< MMC card high speed 400 timing*/ + kMMC_HighSpeed26MHZTiming = 4U, /*!< MMC high speed 26MHZ timing */ + kMMC_HighSpeed52MHZTiming = 5U, /*!< MMC high speed 52MHZ timing */ + kMMC_HighSpeedDDR52Timing = 6U, /*!< MMC high speed timing DDR52 1.8V */ +} mmc_high_speed_timing_t; + +/*! @brief The number of data bus width type */ +#define MMC_DATA_BUS_WIDTH_TYPE_NUMBER (3U) +/*! @brief MMC card data bus width(BUS_WIDTH in Extended CSD) */ +typedef enum _mmc_data_bus_width +{ + kMMC_DataBusWidth1bit = 0U, /*!< MMC data bus width is 1 bit */ + kMMC_DataBusWidth4bit = 1U, /*!< MMC data bus width is 4 bits */ + kMMC_DataBusWidth8bit = 2U, /*!< MMC data bus width is 8 bits */ + kMMC_DataBusWidth4bitDDR = 5U, /*!< MMC data bus width is 4 bits ddr */ + kMMC_DataBusWidth8bitDDR = 6U, /*!< MMC data bus width is 8 bits ddr */ +} mmc_data_bus_width_t; + +/*! @brief MMC card boot partition enabled(BOOT_PARTITION_ENABLE in Extended CSD) */ +typedef enum _mmc_boot_partition_enable +{ + kMMC_BootPartitionEnableNot = 0U, /*!< Device not boot enabled (default) */ + kMMC_BootPartitionEnablePartition1 = 1U, /*!< Boot partition 1 enabled for boot */ + kMMC_BootPartitionEnablePartition2 = 2U, /*!< Boot partition 2 enabled for boot */ + kMMC_BootPartitionEnableUserAera = 7U, /*!< User area enabled for boot */ +} mmc_boot_partition_enable_t; + +/*! @brief MMC card partition to be accessed(BOOT_PARTITION_ACCESS in Extended CSD) */ +typedef enum _mmc_access_partition +{ + kMMC_AccessPartitionUserAera = 0U, /*!< No access to boot partition (default), normal partition */ + kMMC_AccessPartitionBoot1 = 1U, /*!< Read/Write boot partition 1 */ + kMMC_AccessPartitionBoot2 = 2U, /*!< Read/Write boot partition 2*/ + kMMC_AccessRPMB = 3U, /*!< Replay protected mem block */ + kMMC_AccessGeneralPurposePartition1 = 4U, /*!< access to general purpose partition 1 */ + kMMC_AccessGeneralPurposePartition2 = 5U, /*!< access to general purpose partition 2 */ + kMMC_AccessGeneralPurposePartition3 = 6U, /*!< access to general purpose partition 3 */ + kMMC_AccessGeneralPurposePartition4 = 7U, /*!< access to general purpose partition 4 */ +} mmc_access_partition_t; + +/*! @brief The bit shift for PARTITION ACCESS filed in BOOT CONFIG (BOOT_CONFIG in Extend CSD) */ +#define MMC_BOOT_CONFIG_PARTITION_ACCESS_SHIFT (0U) +/*! @brief The bit mask for PARTITION ACCESS field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_PARTITION_ACCESS_MASK (0x00000007U) +/*! @brief The bit shift for PARTITION ENABLE field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_PARTITION_ENABLE_SHIFT (3U) +/*! @brief The bit mask for PARTITION ENABLE field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_PARTITION_ENABLE_MASK (0x00000038U) +/*! @brief The bit shift for ACK field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_ACK_SHIFT (6U) +/*! @brief The bit mask for ACK field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_ACK_MASK (0x00000040U) +/*! @brief The bit shift for BOOT BUS WIDTH field in BOOT CONFIG */ +#define MMC_BOOT_BUS_WIDTH_WIDTH_SHIFT (8U) +/*! @brief The bit mask for BOOT BUS WIDTH field in BOOT CONFIG */ +#define MMC_BOOT_BUS_WIDTH_WIDTH_MASK (0x00000300U) +/*! @brief The bit shift for BOOT BUS WIDTH RESET field in BOOT CONFIG */ +#define MMC_BOOT_BUS_WIDTH_RESET_SHIFT (10U) +/*! @brief The bit mask for BOOT BUS WIDTH RESET field in BOOT CONFIG */ +#define MMC_BOOT_BUS_WIDTH_RESET_MASK (0x00000400U) + +/*! @brief MMC card CSD register flags */ +enum _mmc_csd_flag +{ + kMMC_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed */ + kMMC_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment */ + kMMC_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment */ + kMMC_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented */ + kMMC_CsdWriteProtectGroupEnabledFlag = (1U << 4U), /*!< Write protect group enabled */ + kMMC_CsdWriteBlockPartialFlag = (1U << 5U), /*!< Partial blocks for write allowed */ + kMMC_ContentProtectApplicationFlag = (1U << 6U), /*!< Content protect application */ + kMMC_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group */ + kMMC_CsdCopyFlag = (1U << 8U), /*!< Copy flag */ + kMMC_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection */ + kMMC_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection */ +}; + +/*! @brief Extended CSD register access mode(Access mode in CMD6). */ +typedef enum _mmc_extended_csd_access_mode +{ + kMMC_ExtendedCsdAccessModeCommandSet = 0U, /*!< Command set related setting */ + kMMC_ExtendedCsdAccessModeSetBits = 1U, /*!< Set bits in specific byte in Extended CSD */ + kMMC_ExtendedCsdAccessModeClearBits = 2U, /*!< Clear bits in specific byte in Extended CSD */ + kMMC_ExtendedCsdAccessModeWriteBits = 3U, /*!< Write a value to specific byte in Extended CSD */ +} mmc_extended_csd_access_mode_t; + +/*! @brief EXT CSD byte index */ +typedef enum _mmc_extended_csd_index +{ + kMMC_ExtendedCsdIndexEraseGroupDefinition = 175U, /*!< Erase Group Def */ + kMMC_ExtendedCsdIndexBootBusWidth = 177U, /*!< Boot Bus Width */ + kMMC_ExtendedCsdIndexBootConfig = 179U, /*!< Boot Config */ + kMMC_ExtendedCsdIndexBusWidth = 183U, /*!< Bus Width */ + kMMC_ExtendedCsdIndexHighSpeedTiming = 185U, /*!< High-speed Timing */ + kMMC_ExtendedCsdIndexPowerClass = 187U, /*!< Power Class */ + kMMC_ExtendedCsdIndexCommandSet = 191U, /*!< Command Set */ +} mmc_extended_csd_index_t; + +/*! @brief mmc driver strength */ +enum _mmc_driver_strength +{ + kMMC_DriverStrength0 = 0U, /*!< Driver type0 ,nominal impedance 50ohm */ + kMMC_DriverStrength1 = 1U, /*!< Driver type1 ,nominal impedance 33ohm */ + kMMC_DriverStrength2 = 2U, /*!< Driver type2 ,nominal impedance 66ohm */ + kMMC_DriverStrength3 = 3U, /*!< Driver type3 ,nominal impedance 100ohm */ + kMMC_DriverStrength4 = 4U, /*!< Driver type4 ,nominal impedance 40ohm */ +}; + +/*! @brief mmc extended csd flags*/ +typedef enum _mmc_extended_csd_flags +{ + kMMC_ExtCsdExtPartitionSupport = (1 << 0U), /*!< partitioning support[160] */ + kMMC_ExtCsdEnhancePartitionSupport = (1 << 1U), /*!< partitioning support[160] */ + kMMC_ExtCsdPartitioningSupport = (1 << 2U), /*!< partitioning support[160] */ + kMMC_ExtCsdPrgCIDCSDInDDRModeSupport = (1 << 3U), /*!< CMD26 and CMD27 are support dual data rate [130]*/ + kMMC_ExtCsdBKOpsSupport = (1 << 4U), /*!< background operation feature support [502]*/ + kMMC_ExtCsdDataTagSupport = (1 << 5U), /*!< data tag support[499]*/ + kMMC_ExtCsdModeOperationCodeSupport = (1 << 6U), /*!< mode operation code support[493]*/ +} mmc_extended_csd_flags_t; + +/*! @brief The length of Extended CSD register, unit as bytes. */ +#define MMC_EXTENDED_CSD_BYTES (512U) + +/*! @brief MMC card default relative address */ +#define MMC_DEFAULT_RELATIVE_ADDRESS (2U) + +/*! @brief SD card product name length united as bytes. */ +#define SD_PRODUCT_NAME_BYTES (5U) + +/*! @brief sdio card FBR register */ +typedef struct _sdio_fbr +{ + uint8_t flags; /*!< current io flags */ + uint8_t ioStdFunctionCode; /*!< current io standard function code */ + uint8_t ioExtFunctionCode; /*!< current io extended function code*/ + uint32_t ioPointerToCIS; /*!< current io pointer to CIS */ + uint32_t ioPointerToCSA; /*!< current io pointer to CSA*/ + uint16_t ioBlockSize; /*!< current io block size */ +} sdio_fbr_t; + +/*! @brief sdio card common CIS */ +typedef struct _sdio_common_cis +{ + /* manufacturer identification string tuple */ + uint16_t mID; /*!< manufacturer code */ + uint16_t mInfo; /*!< manufacturer information */ + + /*function identification tuple */ + uint8_t funcID; /*!< function ID */ + + /* function extension tuple */ + uint16_t fn0MaxBlkSize; /*!< function 0 max block size */ + uint8_t maxTransSpeed; /*!< max data transfer speed for all function */ + +} sdio_common_cis_t; + +/*! @brief sdio card function CIS */ +typedef struct _sdio_func_cis +{ + /*function identification tuple */ + uint8_t funcID; /*!< function ID */ + + /* function extension tuple */ + uint8_t funcInfo; /*!< function info */ + uint8_t ioVersion; /*!< level of application specification this io support */ + uint32_t cardPSN; /*!< product serial number */ + uint32_t ioCSASize; /*!< avaliable CSA size for io */ + uint8_t ioCSAProperty; /*!< CSA property */ + uint16_t ioMaxBlockSize; /*!< io max transfer data size */ + uint32_t ioOCR; /*!< io ioeration condition */ + uint8_t ioOPMinPwr; /*!< min current in operation mode */ + uint8_t ioOPAvgPwr; /*!< average current in operation mode */ + uint8_t ioOPMaxPwr; /*!< max current in operation mode */ + uint8_t ioSBMinPwr; /*!< min current in standby mode */ + uint8_t ioSBAvgPwr; /*!< average current in standby mode */ + uint8_t ioSBMaxPwr; /*!< max current in standby mode */ + + uint16_t ioMinBandWidth; /*!< io min transfer bandwidth */ + uint16_t ioOptimumBandWidth; /*!< io optimum transfer bandwidth */ + uint16_t ioReadyTimeout; /*!< timeout value from enalbe to ready */ + uint16_t ioHighCurrentAvgCurrent; /*!< the average peak current (mA) + when IO operating in high current mode */ + uint16_t ioHighCurrentMaxCurrent; /*!< the max peak current (mA) + when IO operating in high current mode */ + uint16_t ioLowCurrentAvgCurrent; /*!< the average peak current (mA) + when IO operating in lower current mode */ + uint16_t ioLowCurrentMaxCurrent; /*!< the max peak current (mA) + when IO operating in lower current mode */ +} sdio_func_cis_t; + +/*! @brief SD card CID register */ +typedef struct _sd_cid +{ + uint8_t manufacturerID; /*!< Manufacturer ID [127:120] */ + uint16_t applicationID; /*!< OEM/Application ID [119:104] */ + uint8_t productName[SD_PRODUCT_NAME_BYTES]; /*!< Product name [103:64] */ + uint8_t productVersion; /*!< Product revision [63:56] */ + uint32_t productSerialNumber; /*!< Product serial number [55:24] */ + uint16_t manufacturerData; /*!< Manufacturing date [19:8] */ +} sd_cid_t; + +/*! @brief SD card CSD register */ +typedef struct _sd_csd +{ + uint8_t csdStructure; /*!< CSD structure [127:126] */ + uint8_t dataReadAccessTime1; /*!< Data read access-time-1 [119:112] */ + uint8_t dataReadAccessTime2; /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ + uint8_t transferSpeed; /*!< Maximum data transfer rate [103:96] */ + uint16_t cardCommandClass; /*!< Card command classes [95:84] */ + uint8_t readBlockLength; /*!< Maximum read data block length [83:80] */ + uint16_t flags; /*!< Flags in _sd_csd_flag */ + uint32_t deviceSize; /*!< Device size [73:62] */ + /* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */ + uint8_t readCurrentVddMin; /*!< Maximum read current at VDD min [61:59] */ + uint8_t readCurrentVddMax; /*!< Maximum read current at VDD max [58:56] */ + uint8_t writeCurrentVddMin; /*!< Maximum write current at VDD min [55:53] */ + uint8_t writeCurrentVddMax; /*!< Maximum write current at VDD max [52:50] */ + uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ + + uint8_t eraseSectorSize; /*!< Erase sector size [45:39] */ + uint8_t writeProtectGroupSize; /*!< Write protect group size [38:32] */ + uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ + uint8_t writeBlockLength; /*!< Maximum write data block length [25:22] */ + uint8_t fileFormat; /*!< File format [11:10] */ +} sd_csd_t; + +/*! @brief The bit shift for RATE UNIT field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_RATE_UNIT_SHIFT (0U) +/*! @brief The bit mask for RATE UNIT field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_RATE_UNIT_MASK (0x07U) +/*! @brief The bit shift for TIME VALUE field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_TIME_VALUE_SHIFT (2U) +/*! @brief The bit mask for TIME VALUE field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_TIME_VALUE_MASK (0x78U) +/*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED field */ +#define SD_RD_TRANSFER_SPEED_RATE_UNIT(x) \ + (((x.transferSpeed) & SD_TRANSFER_SPEED_RATE_UNIT_MASK) >> SD_TRANSFER_SPEED_RATE_UNIT_SHIFT) +/*! @brief Read the value of TIME VALUE in TRANSFER SPEED field */ +#define SD_RD_TRANSFER_SPEED_TIME_VALUE(x) \ + (((x.transferSpeed) & SD_TRANSFER_SPEED_TIME_VALUE_MASK) >> SD_TRANSFER_SPEED_TIME_VALUE_SHIFT) + +/*! @brief SD card SCR register */ +typedef struct _sd_scr +{ + uint8_t scrStructure; /*!< SCR Structure [63:60] */ + uint8_t sdSpecification; /*!< SD memory card specification version [59:56] */ + uint16_t flags; /*!< SCR flags in _sd_scr_flag */ + uint8_t sdSecurity; /*!< Security specification supported [54:52] */ + uint8_t sdBusWidths; /*!< Data bus widths supported [51:48] */ + uint8_t extendedSecurity; /*!< Extended security support [46:43] */ + uint8_t commandSupport; /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ + uint32_t reservedForManufacturer; /*!< reserved for manufacturer usage [31:0] */ +} sd_scr_t; + +/*! @brief MMC card product name length united as bytes. */ +#define MMC_PRODUCT_NAME_BYTES (6U) +/*! @brief MMC card CID register. */ +typedef struct _mmc_cid +{ + uint8_t manufacturerID; /*!< Manufacturer ID */ + uint16_t applicationID; /*!< OEM/Application ID */ + uint8_t productName[MMC_PRODUCT_NAME_BYTES]; /*!< Product name */ + uint8_t productVersion; /*!< Product revision */ + uint32_t productSerialNumber; /*!< Product serial number */ + uint8_t manufacturerData; /*!< Manufacturing date */ +} mmc_cid_t; + +/*! @brief MMC card CSD register. */ +typedef struct _mmc_csd +{ + uint8_t csdStructureVersion; /*!< CSD structure [127:126] */ + uint8_t systemSpecificationVersion; /*!< System specification version [125:122] */ + uint8_t dataReadAccessTime1; /*!< Data read access-time 1 [119:112] */ + uint8_t dataReadAccessTime2; /*!< Data read access-time 2 in CLOCK cycles (NSAC*100) [111:104] */ + uint8_t transferSpeed; /*!< Max. bus clock frequency [103:96] */ + uint16_t cardCommandClass; /*!< card command classes [95:84] */ + uint8_t readBlockLength; /*!< Max. read data block length [83:80] */ + uint16_t flags; /*!< Contain flags in _mmc_csd_flag */ + uint16_t deviceSize; /*!< Device size [73:62] */ + uint8_t readCurrentVddMin; /*!< Max. read current @ VDD min [61:59] */ + uint8_t readCurrentVddMax; /*!< Max. read current @ VDD max [58:56] */ + uint8_t writeCurrentVddMin; /*!< Max. write current @ VDD min [55:53] */ + uint8_t writeCurrentVddMax; /*!< Max. write current @ VDD max [52:50] */ + uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ + uint8_t eraseGroupSize; /*!< Erase group size [46:42] */ + uint8_t eraseGroupSizeMultiplier; /*!< Erase group size multiplier [41:37] */ + uint8_t writeProtectGroupSize; /*!< Write protect group size [36:32] */ + uint8_t defaultEcc; /*!< Manufacturer default ECC [30:29] */ + uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ + uint8_t maxWriteBlockLength; /*!< Max. write data block length [25:22] */ + uint8_t fileFormat; /*!< File format [11:10] */ + uint8_t eccCode; /*!< ECC code [9:8] */ +} mmc_csd_t; + +/*! @brief MMC card Extended CSD register (unit: byte). */ +typedef struct _mmc_extended_csd +{ + uint32_t flags; + uint8_t SecureRemoveType; /*!< secure removal type[16]*/ + uint8_t enProductStateAware; /*!< product state awareness enablement[17]*/ + uint32_t maxPreLoadDataSize; /*!< max preload data size[21-18]*/ + uint32_t preLoadDataSize; /*!< pre-load data size[25-22]*/ + uint8_t ffuStatus; /*!< FFU status [26]*/ + uint8_t modeOperationCode; /*!< mode operation code[29]*/ + uint8_t modeConfig; /*!< mode config [30]*/ + uint8_t cacheCtrl; /*!< control to turn on/off cache[33]*/ + uint8_t pwroffNotify; /*!< power off notification[34]*/ + uint8_t packedCmdFailIndex; /*!< packed cmd fail index [35]*/ + uint8_t packedCmdStatus; /*!< packed cmd status[36]*/ + uint32_t contextConfig[4U]; /*!< context configuration[51-37]*/ + uint16_t extPartitionAttr; /*!< extended partitions attribut[53-52]*/ + uint16_t exceptEventStatus; /*!< exception events status[55-54]*/ + uint16_t exceptEventControl; /*!< exception events control[57-56]*/ + uint8_t toReleaseAddressedGroup; /*!< number of group to be released[58]*/ + uint8_t class6CmdCtrl; /*!< class 6 command control[59]*/ + uint8_t intTimeoutEmu; /*!< 1st initiallization after disabling sector size emu[60]*/ + uint8_t sectorSize; /*!< sector size[61] */ + uint8_t sectorSizeEmu; /*!< sector size emulation[62]*/ + uint8_t nativeSectorSize; /*!< native sector size[63]*/ + uint8_t periodWakeup; /*!< period wakeup [131]*/ + uint8_t tCASESupport; /*!< package case temperature is controlled[132]*/ + uint8_t productionStateAware; /*!< production state awareness[133]*/ + uint32_t enhanceUsrDataStartAddr; /*!< enhanced user data start addr [139-136]*/ + uint32_t enhanceUsrDataSize; /*!< enhanced user data area size[142-140]*/ + uint32_t generalPartitionSize[3]; /*!< general purpose partition size[154-143]*/ + uint8_t partitionAttribute; /*!< partition attribute [156]*/ + uint32_t maxEnhanceAreaSize; /*!< max enhance area size [159-157]*/ + uint8_t hpiManagementEn; /*!< HPI management [161]*/ + uint8_t writeReliabilityParameter; /*!< write reliability parameter register[166] */ + uint8_t writeReliabilitySet; /*!< write reliability setting register[167] */ + uint8_t rpmbSizeMult; /*!< RPMB size multi [168]*/ + uint8_t fwConfig; /*!< FW configuration[169]*/ + uint8_t userWPRegister; /*!< user write protect register[171] */ + uint8_t bootWPRegister; /*!< boot write protect register[173]*/ + uint8_t bootWPStatusRegister; /*!< boot write protect status register[174]*/ + uint8_t highDensityEraseGroupDefinition; /*!< High-density erase group definition [175] */ + uint8_t bootDataBusWidth; /*!< Boot bus width [177] */ + uint8_t bootConfigProtect; /*!< Boot config protection [178]*/ + uint8_t partitionConfig; /*!< Boot configuration [179] */ + uint8_t eraseMemoryContent; /*!< Erased memory content [181] */ + uint8_t dataBusWidth; /*!< Data bus width mode [183] */ + uint8_t highSpeedTiming; /*!< High-speed interface timing [185] */ + uint8_t powerClass; /*!< Power class [187] */ + uint8_t commandSetRevision; /*!< Command set revision [189] */ + uint8_t commandSet; /*!< Command set [191] */ + uint8_t extendecCsdVersion; /*!< Extended CSD revision [192] */ + uint8_t csdStructureVersion; /*!< CSD structure version [194] */ + uint8_t cardType; /*!< Card Type [196] */ + uint8_t ioDriverStrength; /*!< IO driver strength [197] */ + uint8_t OutofInterruptBusyTiming; /*!< out of interrupt busy timing [198] */ + uint8_t partitionSwitchTiming; /*!< partition switch timing [199] */ + uint8_t powerClass52MHz195V; /*!< Power Class for 52MHz @ 1.95V [200] */ + uint8_t powerClass26MHz195V; /*!< Power Class for 26MHz @ 1.95V [201] */ + uint8_t powerClass52MHz360V; /*!< Power Class for 52MHz @ 3.6V [202] */ + uint8_t powerClass26MHz360V; /*!< Power Class for 26MHz @ 3.6V [203] */ + uint8_t minimumReadPerformance4Bit26MHz; /*!< Minimum Read Performance for 4bit at 26MHz [205] */ + uint8_t minimumWritePerformance4Bit26MHz; /*!< Minimum Write Performance for 4bit at 26MHz [206] */ + uint8_t minimumReadPerformance8Bit26MHz4Bit52MHz; + /*!< Minimum read Performance for 8bit at 26MHz/4bit @52MHz [207] */ + uint8_t minimumWritePerformance8Bit26MHz4Bit52MHz; + /*!< Minimum Write Performance for 8bit at 26MHz/4bit @52MHz [208] */ + uint8_t minimumReadPerformance8Bit52MHz; /*!< Minimum Read Performance for 8bit at 52MHz [209] */ + uint8_t minimumWritePerformance8Bit52MHz; /*!< Minimum Write Performance for 8bit at 52MHz [210] */ + uint32_t sectorCount; /*!< Sector Count [215:212] */ + uint8_t sleepNotificationTimeout; /*!< sleep notification timeout [216]*/ + uint8_t sleepAwakeTimeout; /*!< Sleep/awake timeout [217] */ + uint8_t productionStateAwareTimeout; /*!< Production state awareness timeout [218]*/ + uint8_t sleepCurrentVCCQ; /*!< Sleep current (VCCQ) [219] */ + uint8_t sleepCurrentVCC; /*!< Sleep current (VCC) [220] */ + uint8_t highCapacityWriteProtectGroupSize; /*!< High-capacity write protect group size [221] */ + uint8_t reliableWriteSectorCount; /*!< Reliable write sector count [222] */ + uint8_t highCapacityEraseTimeout; /*!< High-capacity erase timeout [223] */ + uint8_t highCapacityEraseUnitSize; /*!< High-capacity erase unit size [224] */ + uint8_t accessSize; /*!< Access size [225] */ + uint8_t bootSizeMultiplier; /*!< Boot partition size [226] */ + uint8_t bootInformation; /*!< Boot information [228] */ + uint8_t secureTrimMultiplier; /*!< secure trim multiplier[229]*/ + uint8_t secureEraseMultiplier; /*!< secure erase multiplier[230]*/ + uint8_t secureFeatureSupport; /*!< secure feature support[231]*/ + uint32_t trimMultiplier; /*!< trim multiplier[232]*/ + uint8_t minReadPerformance8bitAt52MHZDDR; /*!< Minimum read performance for 8bit at DDR 52MHZ[234]*/ + uint8_t minWritePerformance8bitAt52MHZDDR; /*!< Minimum write performance for 8bit at DDR 52MHZ[235]*/ + uint8_t powerClass200MHZVCCQ130VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.3V,VCC=3.6V[236]*/ + uint8_t powerClass200MHZVCCQ195VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.95V,VCC=3.6V[237]*/ + uint8_t powerClass52MHZDDR195V; /*!< power class for 52MHZ,DDR at Vcc 1.95V[238]*/ + uint8_t powerClass52MHZDDR360V; /*!< power class for 52MHZ,DDR at Vcc 3.6V[239]*/ + uint8_t iniTimeoutAP; /*!< 1st initialization time after partitioning[241]*/ + uint32_t correctPrgSectorNum; /*!< correct prg sectors number[245-242]*/ + uint8_t bkOpsStatus; /*!< background operations status[246]*/ + uint8_t powerOffNotifyTimeout; /*!< power off notification timeout[247]*/ + uint8_t genericCMD6Timeout; /*!< generic CMD6 timeout[248]*/ + uint32_t cacheSize; /*!< cache size[252-249]*/ + uint8_t powerClass200MHZDDR360V; /*!< power class for 200MHZ, DDR at VCC=2.6V[253]*/ + uint32_t fwVer[2U]; /*!< fw VERSION [261-254]*/ + uint16_t deviveVer; /*!< device version[263-262]*/ + uint8_t optimalTrimSize; /*!< optimal trim size[264]*/ + uint8_t optimalWriteSize; /*!< optimal write size[265]*/ + uint8_t optimalReadSize; /*!< optimal read size[266]*/ + uint8_t preEolInfo; /*!< pre EOL information[267]*/ + uint8_t deviceLifeTimeEstimationA; /*!< device life time estimation typeA[268]*/ + uint8_t deviceLifeTimeEstimationB; /*!< device life time estimation typeB[269]*/ + uint32_t correctPrgFWSectorNum; /*!< number of FW sectors correctly programmed[305-302]*/ + uint32_t ffuArg; /*!< FFU argument[490-487]*/ + uint8_t operationCodeTimeout; /*!< operation code timeout[491]*/ + uint8_t supportMode; /*!< support mode [493]*/ + uint8_t extPartitionSupport; /*!< extended partition attribute support[494]*/ + uint8_t largeUnitSize; /*!< large unit size[495]*/ + uint8_t contextManageCap; /*!< context management capability[496]*/ + uint8_t tagResourceSize; /*!< tag resource size[497]*/ + uint8_t tagUnitSize; /*!< tag unit size[498]*/ + uint8_t maxPackedWriteCmd; /*!< max packed write cmd[500]*/ + uint8_t maxPackedReadCmd; /*!< max packed read cmd[501]*/ + uint8_t hpiFeature; /*!< HPI feature[503]*/ + uint8_t supportedCommandSet; /*!< Supported Command Sets [504] */ + uint8_t extSecurityCmdError; /*!< extended security commands error[505]*/ +} mmc_extended_csd_t; + +/*! @brief The bit shift for COMMAND SET field in SWITCH command. */ +#define MMC_SWITCH_COMMAND_SET_SHIFT (0U) +/*! @brief The bit mask for COMMAND set field in SWITCH command. */ +#define MMC_SWITCH_COMMAND_SET_MASK (0x00000007U) +/*! @brief The bit shift for VALUE field in SWITCH command */ +#define MMC_SWITCH_VALUE_SHIFT (8U) +/*! @brief The bit mask for VALUE field in SWITCH command */ +#define MMC_SWITCH_VALUE_MASK (0x0000FF00U) +/*! @brief The bit shift for BYTE INDEX field in SWITCH command */ +#define MMC_SWITCH_BYTE_INDEX_SHIFT (16U) +/*! @brief The bit mask for BYTE INDEX field in SWITCH command */ +#define MMC_SWITCH_BYTE_INDEX_MASK (0x00FF0000U) +/*! @brief The bit shift for ACCESS MODE field in SWITCH command */ +#define MMC_SWITCH_ACCESS_MODE_SHIFT (24U) +/*! @brief The bit mask for ACCESS MODE field in SWITCH command */ +#define MMC_SWTICH_ACCESS_MODE_MASK (0x03000000U) + +/*! @brief MMC Extended CSD configuration. */ +typedef struct _mmc_extended_csd_config +{ + mmc_command_set_t commandSet; /*!< Command set */ + uint8_t ByteValue; /*!< The value to set */ + uint8_t ByteIndex; /*!< The byte index in Extended CSD(mmc_extended_csd_index_t) */ + mmc_extended_csd_access_mode_t accessMode; /*!< Access mode */ +} mmc_extended_csd_config_t; + +#endif /* _FSL_SPECIFICATION_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/usdhc_config.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/usdhc_config.h new file mode 100644 index 0000000000000000000000000000000000000000..89aeab67696454e4153df6a0faaeee9862252d58 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/usdhc_config.h @@ -0,0 +1,49 @@ +/* + * SD-Card board config + * SD-Card board config file + * + * Change Logs: + * Date Author Notes + * 2021-04-23 Lyons first version + */ + +#ifndef _BOARD_SDCARD_H_ +#define _BOARD_SDCARD_H_ + +#define BOARD_SD_PIN_CONFIG(speed, strength) +#define BOARD_MMC_PIN_CONFIG(speed, strength) + +#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() +#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) + +#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() +#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state) + +/* + * Insert detection is not used + * Following setting no needed to care + */ +#define BOARD_USDHC_CD_STATUS() 0 +#define BOARD_USDHC_CD_GPIO_INIT() +#define BOARD_USDHC_CD_INTERRUPT_STATUS() 0 +#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) + +#define BOARD_USDHC_CD_GPIO_BASE GPIO1 +#define BOARD_USDHC_CD_GPIO_PIN 19 +#define BOARD_USDHC_CD_PORT_IRQ GPIO1_Combined_16_31_IRQn +#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO_IRQ_Handler + +#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U)) +#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U)) + +#define BOARD_SD_HOST_BASEADDR USDHC1_BASE +#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ +#define BOARD_SD_HOST_IRQ USDHC1_IRQn + +#define BOARD_SD_SUPPORT_180V (0U) +#define BOARD_MMC_SUPPORT_8BIT_BUS (0U) + +#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (130000000U) +#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (150000000U) + +#endif /* _BOARD_SDCARD_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/fsl_device_registers.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/fsl_device_registers.h new file mode 100644 index 0000000000000000000000000000000000000000..d89474b8a1fc88f153e5397d7b5718d77ec7654c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/fsl_device_registers.h @@ -0,0 +1,59 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +#include //define CPU Type here + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCIMX6Y2CVM05) || defined(CPU_MCIMX6Y2CVM08) || defined(CPU_MCIMX6Y2DVM05) || \ + defined(CPU_MCIMX6Y2DVM09)) + +#define MCIMX6Y2_SERIES + +/* CMSIS-style register definitions */ +#include "MCIMX6Y2.h" +/* CPU specific feature definitions */ +#include "MCIMX6Y2_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.c new file mode 100644 index 0000000000000000000000000000000000000000..d6717da2ac77cd60ba5b28d739c10131da097254 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.c @@ -0,0 +1,489 @@ +/* +** ################################################################### +** Processors: MCIMX6Y2CVM05 +** MCIMX6Y2CVM08 +** MCIMX6Y2DVM05 +** MCIMX6Y2DVM09 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: IMX6ULLRM, Rev. 1, Feb. 2017 +** Version: rev. 3.0, 2017-02-28 +** Build: b170410 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-12-18) +** Initial version. +** - rev. 2.0 (2016-08-02) +** Rev.B Header GA +** - rev. 3.0 (2017-02-28) +** Rev.1 Header GA +** +** ################################################################### +*/ + +/*! + * @file MCIMX6Y2 + * @version 3.0 + * @date 2017-02-28 + * @brief Device specific configuration file for MCIMX6Y2 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +/* Transaction Drivers Handler Declaration */ +extern void CAN1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void CAN2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ECSPI1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ECSPI2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ECSPI3_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ECSPI4_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ENET1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ENET1_Driver1588IRQHandler (uint32_t giccIar, void *userParam); +extern void ENET2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ENET2_Driver1588IRQHandler (uint32_t giccIar, void *userParam); +extern void I2C1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2C2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2C3_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2C4_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2S1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2S2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2S3_Tx_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2S3_Rx_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART3_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART4_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART5_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART6_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART7_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART8_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void USDHC1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void USDHC2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void SDMA_DriverIRQHandler (uint32_t giccIar, void *userParam); + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma weak CAN1_DriverIRQHandler=defaultIrqHandler +#pragma weak CAN2_DriverIRQHandler=defaultIrqHandler +#pragma weak ECSPI1_DriverIRQHandler=defaultIrqHandler +#pragma weak ECSPI2_DriverIRQHandler=defaultIrqHandler +#pragma weak ECSPI3_DriverIRQHandler=defaultIrqHandler +#pragma weak ECSPI4_DriverIRQHandler=defaultIrqHandler +#pragma weak ENET1_DriverIRQHandler=defaultIrqHandler +#pragma weak ENET2_DriverIRQHandler=defaultIrqHandler +#pragma weak ENET1_Driver1588IRQHandler=defaultIrqHandler +#pragma weak ENET2_Driver1588IRQHandler=defaultIrqHandler +#pragma weak I2C1_DriverIRQHandler=defaultIrqHandler +#pragma weak I2C2_DriverIRQHandler=defaultIrqHandler +#pragma weak I2C3_DriverIRQHandler=defaultIrqHandler +#pragma weak I2C4_DriverIRQHandler=defaultIrqHandler +#pragma weak I2S1_DriverIRQHandler=defaultIrqHandler +#pragma weak I2S2_DriverIRQHandler=defaultIrqHandler +#pragma weak I2S3_Tx_DriverIRQHandler=defaultIrqHandler +#pragma weak I2S3_Rx_DriverIRQHandler=defaultIrqHandler +#pragma weak UART1_DriverIRQHandler=defaultIrqHandler +#pragma weak UART2_DriverIRQHandler=defaultIrqHandler +#pragma weak UART3_DriverIRQHandler=defaultIrqHandler +#pragma weak UART4_DriverIRQHandler=defaultIrqHandler +#pragma weak UART5_DriverIRQHandler=defaultIrqHandler +#pragma weak UART6_DriverIRQHandler=defaultIrqHandler +#pragma weak UART7_DriverIRQHandler=defaultIrqHandler +#pragma weak UART8_DriverIRQHandler=defaultIrqHandler +#pragma weak USDHC1_DriverIRQHandler=defaultIrqHandler +#pragma weak USDHC2_DriverIRQHandler=defaultIrqHandler +#pragma weak SDMA_DriverIRQHandler=defaultIrqHandler +#elif defined(__GNUC__) +void CAN1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void CAN2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ECSPI1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ECSPI2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ECSPI3_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ECSPI4_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ENET1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ENET2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ENET1_Driver1588IRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ENET2_Driver1588IRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2C1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2C2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2C3_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2C4_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2S1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2S2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2S3_Tx_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2S3_Rx_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART3_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART4_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART5_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART6_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART7_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART8_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void USDHC1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void USDHC2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void SDMA_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +#else + #error Not supported compiler type +#endif + +extern uint32_t __VECTOR_TABLE[]; + +/* Local irq table and nesting level value */ +static sys_irq_handle_t irqTable[NUMBER_OF_INT_VECTORS]; +static uint32_t irqNesting; + +/* Local IRQ functions */ +static void defaultIrqHandler (uint32_t giccIar, void *userParam) { + while(1) { + } +} + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { + uint32_t sctlr; + uint32_t actlr; +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + uint32_t cpacr; + uint32_t fpexc; +#endif + + L1C_InvalidateInstructionCacheAll(); + L1C_InvalidateDataCacheAll(); + + actlr = __get_ACTLR(); + actlr = (actlr | ACTLR_SMP_Msk); /* Change to SMP mode before enable DCache */ + __set_ACTLR(actlr); + + sctlr = __get_SCTLR(); + sctlr = (sctlr & ~(SCTLR_V_Msk | /* Use low vector */ + SCTLR_A_Msk | /* Disable alignment fault checking */ + SCTLR_M_Msk)) /* Disable MMU */ + | (SCTLR_I_Msk | /* Enable ICache */ + SCTLR_Z_Msk | /* Enable Prediction */ + SCTLR_CP15BEN_Msk | /* Enable CP15 barrier operations */ + SCTLR_C_Msk); /* Enable DCache */ + __set_SCTLR(sctlr); + + /* Set vector base address */ + GIC_Init(); + __set_VBAR((uint32_t)__VECTOR_TABLE); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + cpacr = __get_CPACR(); + /* Enable NEON and FPU */ + cpacr = (cpacr & ~(CPACR_ASEDIS_Msk | CPACR_D32DIS_Msk)) + | (3UL << CPACR_cp10_Pos) | (3UL << CPACR_cp11_Pos); + __set_CPACR(cpacr); + + fpexc = __get_FPEXC(); + fpexc |= 0x40000000UL; /* Enable NEON and FPU */ + __set_FPEXC(fpexc); +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + /* i.MX6ULL systemCoreClockUpdate */ + uint32_t PLL1SWClock; + uint32_t PLL2MainClock; + if (CCM->CCSR & CCM_CCSR_PLL1_SW_CLK_SEL_MASK) + { + if (CCM->CCSR & CCM_CCSR_STEP_SEL_MASK) + { + /* Get SYS PLL clock*/ + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + PLL2MainClock = (24000000UL * 22UL + (uint64_t)(24000000UL) * (uint64_t)(CCM_ANALOG->PLL_SYS_NUM) / (uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + } + else + { + PLL2MainClock = (24000000UL * 20UL + (uint64_t)(24000000UL) * (uint64_t)(CCM_ANALOG->PLL_SYS_NUM) / (uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + } + + if (CCM->CCSR & CCM_CCSR_SECONDARY_CLK_SEL_MASK) + { + /* PLL2 ---> Secondary_clk ---> Step Clock ---> CPU Clock */ + PLL1SWClock = PLL2MainClock; + } + else + { + /* PLL2 PFD2 ---> Secondary_clk ---> Step Clock ---> CPU Clock */ + PLL1SWClock = ((uint64_t)PLL2MainClock * 18) / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + } + } + else + { + /* Osc_clk (24M) ---> Step Clock ---> CPU Clock */ + PLL1SWClock = 24000000UL; + } + } + else + { + /* ARM PLL ---> CPU Clock */ + PLL1SWClock = 24000000UL; + PLL1SWClock = ( PLL1SWClock * (CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) >> 1UL; + } + + SystemCoreClock = PLL1SWClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1UL); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitIrqTable() + ---------------------------------------------------------------------------- */ + +void SystemInitIrqTable (void) { + uint32_t i; + + /* First set all handler to default */ + for (i = 0; i < NUMBER_OF_INT_VECTORS; i++) { + SystemInstallIrqHandler((IRQn_Type)i, defaultIrqHandler, NULL); + } + + /* Then set transaction drivers handler */ + /* FlexCAN transaction drivers handler */ + SystemInstallIrqHandler(CAN1_IRQn, CAN1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(CAN2_IRQn, CAN2_DriverIRQHandler, NULL); + /* ECSPI transaction drivers handler */ + SystemInstallIrqHandler(eCSPI1_IRQn, ECSPI1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(eCSPI2_IRQn, ECSPI2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(eCSPI3_IRQn, ECSPI3_DriverIRQHandler, NULL); + SystemInstallIrqHandler(eCSPI4_IRQn, ECSPI4_DriverIRQHandler, NULL); + /* ENET transaction drivers handler */ + SystemInstallIrqHandler(ENET1_IRQn, ENET1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(ENET1_1588_IRQn, ENET1_Driver1588IRQHandler, NULL); + SystemInstallIrqHandler(ENET2_IRQn, ENET2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(ENET2_1588_IRQn, ENET2_Driver1588IRQHandler, NULL); + /* I2C transaction drivers handler */ + SystemInstallIrqHandler(I2C1_IRQn, I2C1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(I2C2_IRQn, I2C2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(I2C3_IRQn, I2C3_DriverIRQHandler, NULL); + SystemInstallIrqHandler(I2C4_IRQn, I2C4_DriverIRQHandler, NULL); + /* I2S transaction drivers handler */ + SystemInstallIrqHandler(SAI1_IRQn, I2S1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(SAI2_IRQn, I2S2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(SAI3_TX_IRQn, I2S3_Tx_DriverIRQHandler, NULL); + SystemInstallIrqHandler(SAI3_RX_IRQn, I2S3_Rx_DriverIRQHandler, NULL); + /* UART transaction drivers handler */ + SystemInstallIrqHandler(UART1_IRQn, UART1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART2_IRQn, UART2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART3_IRQn, UART3_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART4_IRQn, UART4_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART5_IRQn, UART5_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART6_IRQn, UART6_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART7_IRQn, UART7_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART8_IRQn, UART8_DriverIRQHandler, NULL); + /* USDHC transaction drivers handler */ + SystemInstallIrqHandler(USDHC1_IRQn, USDHC1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(USDHC2_IRQn, USDHC2_DriverIRQHandler, NULL); + /* SDMA transaction driver handler */ + SystemInstallIrqHandler(SDMA_IRQn, SDMA_DriverIRQHandler, NULL); +} + +/* ---------------------------------------------------------------------------- + -- SystemInstallIrqHandler() + ---------------------------------------------------------------------------- */ + +void SystemInstallIrqHandler(IRQn_Type irq, system_irq_handler_t handler, void *userParam) { + irqTable[irq].irqHandler = handler; + irqTable[irq].userParam = userParam; +} + +/* ---------------------------------------------------------------------------- + -- SystemIrqHandler() + ---------------------------------------------------------------------------- */ + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma weak SystemIrqHandler +void SystemIrqHandler(uint32_t giccIar) { +#elif defined(__GNUC__) +__attribute__((weak)) void SystemIrqHandler(uint32_t giccIar) { +#else + #error Not supported compiler type +#endif + uint32_t intNum = giccIar & 0x3FFUL; + + /* Spurious interrupt ID or Wrong interrupt number */ + if ((intNum == 1023) || (intNum >= NUMBER_OF_INT_VECTORS)) + { + return; + } + + irqNesting++; + + __enable_irq(); /* Support nesting interrupt */ + + /* Now call the real irq handler for intNum */ + irqTable[intNum].irqHandler(giccIar, irqTable[intNum].userParam); + + __disable_irq(); + + irqNesting--; +} + +uint32_t SystemGetIRQNestingLevel(void) +{ + return irqNesting; +} + +/* Leverage GPT1 to provide Systick */ +void SystemSetupSystick(uint32_t tickRateHz, void *tickHandler, uint32_t intPriority) +{ + uint32_t clockFreq; + uint32_t spllTmp; + + /* Install IRQ handler for GPT1 */ + SystemInstallIrqHandler(GPT1_IRQn, (system_irq_handler_t)(uint32_t)tickHandler, NULL); + + /* Enable Systick all the time */ + CCM->CCGR1 |= CCM_CCGR1_CG10_MASK | CCM_CCGR1_CG11_MASK; + + GPT1->CR = GPT_CR_SWR_MASK; + /* Wait reset finished. */ + while (GPT1->CR == GPT_CR_SWR_MASK) + { + } + /* Use peripheral clock source IPG */ + GPT1->CR = GPT_CR_WAITEN_MASK | GPT_CR_STOPEN_MASK | GPT_CR_DOZEEN_MASK | + GPT_CR_DBGEN_MASK | GPT_CR_ENMOD_MASK | GPT_CR_CLKSRC(1UL); + /* Set clock divider to 1 */ + GPT1->PR = 0; + + /* Get IPG clock*/ + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + clockFreq = (24000000UL * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + clockFreq = 24000000UL; + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + clockFreq = 0U; + break; + } + + clockFreq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pll2_main_clk ---> Periph_clk */ + else + { + /* Get SYS PLL clock*/ + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + spllTmp = (24000000UL * 22UL + (uint64_t)(24000000UL) * (uint64_t)(CCM_ANALOG->PLL_SYS_NUM) / (uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + } + else + { + spllTmp = (24000000UL * 20UL + (uint64_t)(24000000UL) * (uint64_t)(CCM_ANALOG->PLL_SYS_NUM) / (uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + } + + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + clockFreq = spllTmp; + break; + + /* PLL2 PFD2 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + clockFreq = ((uint64_t)spllTmp * 18) / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + /* PLL2 PFD0 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + clockFreq = ((uint64_t)spllTmp * 18) / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + /* PLL2 PFD2 divided(/2) ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + clockFreq = ((((uint64_t)spllTmp * 18) / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) >> 1U); + break; + + default: + clockFreq = 0U; + break; + } + } + clockFreq /= (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + clockFreq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); + + /* Set timeout value and enable interrupt */ + GPT1->OCR[0] = clockFreq / tickRateHz - 1UL; + GPT1->IR = GPT_IR_OF1IE_MASK; + + /* Set interrupt priority */ + GIC_SetPriority(GPT1_IRQn, intPriority); + /* Enable IRQ */ + GIC_EnableIRQ(GPT1_IRQn); + + /* Start GPT counter */ + GPT1->CR |= GPT_CR_EN_MASK; +} + +void SystemClearSystickFlag(void) +{ + GPT1->SR = GPT_SR_OF1_MASK; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.h new file mode 100644 index 0000000000000000000000000000000000000000..c8b88e8c8cfe8b01edd319c55da264d49cb78668 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.h @@ -0,0 +1,176 @@ +/* +** ################################################################### +** Processors: MCIMX6Y2CVM05 +** MCIMX6Y2CVM08 +** MCIMX6Y2DVM05 +** MCIMX6Y2DVM09 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: IMX6ULLRM, Rev. 1, Feb. 2017 +** Version: rev. 3.0, 2017-02-28 +** Build: b170410 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-12-18) +** Initial version. +** - rev. 2.0 (2016-08-02) +** Rev.B Header GA +** - rev. 3.0 (2017-02-28) +** Rev.1 Header GA +** +** ################################################################### +*/ + +/*! + * @file MCIMX6Y2 + * @version 3.0 + * @date 2017-02-28 + * @brief Device specific configuration file for MCIMX6Y2 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCIMX6Y2_H_ +#define _SYSTEM_MCIMX6Y2_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 528000000u /* Default System clock value */ + +typedef void (*system_irq_handler_t) (uint32_t giccIar, void *param); +/** + * @brief IRQ handle for specific IRQ + */ +typedef struct _sys_irq_handle +{ + system_irq_handler_t irqHandler; /**< IRQ handler for specific IRQ */ + void *userParam; /**< User param for handler callback */ +} sys_irq_handle_t; + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief Initialize IRQ table, set default handlers + */ +void SystemInitIrqTable (void); + +/** + * @brief Install IRQ handler for specific IRQ + * + * It can't be called at interrupt context to avoid IRQ table corrupt during interrupt preemption + * + * @param irq IRQ number corresponds to the installed handler + * @param handler IRQ handler for the IRQ number + * @param userParam User specified parameter for IRQ handler callback + */ +void SystemInstallIrqHandler (IRQn_Type irq, system_irq_handler_t handler, void *userParam); + +/** + * @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler. + * + * It is called from IRQ exception context and dispatches to registered handler according to + * GICC_IAR interrupt number. + * The default implementation is weak and user can override this function with his own SystemIrqHandler. + * + * @param giccIar IRQ acknowledge value read from GICC_IAR + */ +void SystemIrqHandler (uint32_t giccIar); + +/** + * @brief Get IRQ nesting level of current context. + * + * If the return value is 0, then the context is not ISR, otherwise the context is ISR. + * + * @return IRQ nesting level + */ +uint32_t SystemGetIRQNestingLevel (void); + +/** + * @brief Setup systick for RTOS system. + * + * @param tickRateHz Tick number per second + * @param tickHandler IRQ callback handler for tick + * @param intPriority IRQ interrupt priority (the smaller, the higher priority) + */ +void SystemSetupSystick (uint32_t tickRateHz, void *tickHandler, uint32_t intPriority); + +/** + * @brief Clear systick flag status so that next tick interrupt may occur. + */ +void SystemClearSystickFlag (void); +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCIMX6Y2_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..4c815c49b835a3a5ea61f337dc17154dd316d7d1 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/link.lds b/bsp/imx6ull-artpi-smart/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..a08c26754c15b61158d2b733eea00a4cd1165434 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/link.lds @@ -0,0 +1,110 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SECTIONS +{ + . = 0x80001000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + /* section information for uRPC */ + . = ALIGN(4); + __uRPCSvcTab_start = .; + KEEP(*(uRPCSvcTab)) + __uRPCSvcTab_end = .; + } =0 + __text_end = .; + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(8); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(8); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/imx6ull-artpi-smart/link_smart.lds b/bsp/imx6ull-artpi-smart/link_smart.lds new file mode 100644 index 0000000000000000000000000000000000000000..6d130ed184c936ad1bf0c2932bb79df5bf5eed04 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/link_smart.lds @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 linzhenxing first version + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */ + +SECTIONS +{ + . = 0xc0001000; + . = ALIGN(4096); + .text : + { + KEEP(*(.text.entrypoint)) /* The entry point */ + *(.vectors) + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + + /* section information for finsh shell */ + . = ALIGN(16); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(16); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(16); + + /* section information for initial. */ + . = ALIGN(16); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(16); + + /* section information for uRPC */ + . = ALIGN(4); + __uRPCSvcTab_start = .; + KEEP(*(uRPCSvcTab)) + __uRPCSvcTab_end = .; + + . = ALIGN(16); + _etext = .; + } + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + . = ALIGN(16); + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(16); + _gp = ABSOLUTE(.); /* Base of small data */ + + *(.sdata) + *(.sdata.*) + } + + . = ALIGN(16); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(16); + .bss : + { + PROVIDE(__bss_start = .); + *(.bss) + *(.bss.*) + *(.dynbss) + + *(COMMON) + PROVIDE(__bss_end = .); + } + _end = .; + +} + +__bss_size = (__bss_end - __bss_start)>>3; diff --git a/bsp/imx6ull-artpi-smart/mkimage.py b/bsp/imx6ull-artpi-smart/mkimage.py new file mode 100644 index 0000000000000000000000000000000000000000..592f7bb8c0444a9ab77910de2db27e347fc0ce0f --- /dev/null +++ b/bsp/imx6ull-artpi-smart/mkimage.py @@ -0,0 +1,235 @@ +# @Time : 2020/12/31 +# @Author : David Dai +# @File : mkimage.py +#!/usr/bin/python2 + +import os +import argparse +import struct + +parser = argparse.ArgumentParser() + +parser.add_argument('-t', '--type') +parser.add_argument('-b', '--bin') +parser.add_argument('-o', '--out', default = "load.bin") +parser.add_argument('-g', '--img', default = "load.img") +parser.add_argument('-a', '--addr', default = "0x00000000") +parser.add_argument('-e', '--ep', default = "0x00000000") + +args = parser.parse_args() + +args.addr = int(args.addr, 16) +args.ep = int(args.ep, 16) + +def stm32image(): + checksum = 0 + + with open(args.out, 'wb') as f: + #write head 'STM32' + f.write(struct.pack('H', 32)) + f.write(struct.pack('H', (len(dcdConfig) << 3) + 8)) + f.write(struct.pack('H', (len(dcdConfig) << 3) + 4)) + f.write(struct.pack('I', int(d[0], 16))) + f.write(struct.pack('>I', int(d[1], 16))) + + #padding data + for i in range(0x27B): + f.write(struct.pack(' rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +\ + 'python mkimage.py ' + MKIMAGE + '\n' diff --git a/bsp/imxrt/imxrt1052-atk-commander/.config b/bsp/imxrt/imxrt1052-atk-commander/.config index a707d7ab616682ed3d0bd892fdcbd21c3cb4f6a0..31b61577bca3b32608706a41f399c934a15e4f69 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/.config +++ b/bsp/imxrt/imxrt1052-atk-commander/.config @@ -7,6 +7,8 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -63,8 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_CPU_FFS=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y # # RT-Thread Components @@ -110,6 +117,7 @@ CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_ELMFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set @@ -119,19 +127,22 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_CORTEXM=y # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -142,18 +153,17 @@ CONFIG_RT_USING_SFUD=y CONFIG_RT_SFUD_USING_SFDP=y # CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE is not set # CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 # CONFIG_RT_DEBUG_SFUD is not set -# CONFIG_RT_USING_W25QXX is not set -# CONFIG_RT_USING_GD is not set # CONFIG_RT_USING_ENC28J60 is not set # CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -170,6 +180,7 @@ CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set @@ -183,14 +194,14 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -205,10 +216,10 @@ CONFIG_RT_USING_POSIX=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -217,14 +228,20 @@ CONFIG_RT_USING_POSIX=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -246,6 +263,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -257,13 +276,32 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set # CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -271,6 +309,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -285,6 +325,9 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -297,16 +340,27 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages # # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -314,6 +368,16 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -321,6 +385,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -329,15 +394,44 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set # CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -348,12 +442,15 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -365,6 +462,53 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set # # Hardware Drivers Config @@ -394,3 +538,5 @@ CONFIG_BSP_USING_SPI3=y # # CONFIG_BSP_USING_SPI_FLASH is not set # CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_USB_DEVICE is not set +CONFIG_SOC_IMXRT1052=y diff --git a/bsp/imxrt/imxrt1052-atk-commander/Kconfig b/bsp/imxrt/imxrt1052-atk-commander/Kconfig index c9221717cb4e42111c0276448be858c983657b2b..7156555e031e22dd37e80c0f62b76d3e68282f63 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/Kconfig +++ b/bsp/imxrt/imxrt1052-atk-commander/Kconfig @@ -14,3 +14,9 @@ source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" source "../libraries/Kconfig" source "board/Kconfig" + +config SOC_IMXRT1052 + bool + select ARCH_ARM_CORTEX_M7 + select RT_USING_CACHE + default y diff --git a/bsp/imxrt/imxrt1052-atk-commander/rtconfig.h b/bsp/imxrt/imxrt1052-atk-commander/rtconfig.h index 5c5cb81922c194f80e4a59ad3f1c34319d2b0b37..4f01487d1032b43cb4d98423115bb1d4c812baed 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/rtconfig.h +++ b/bsp/imxrt/imxrt1052-atk-commander/rtconfig.h @@ -40,7 +40,12 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 /* RT-Thread Components */ @@ -85,13 +90,12 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_CPUTIME +#define RT_USING_CPUTIME_CORTEXM #define RT_USING_PIN #define RT_USING_SPI #define RT_USING_SFUD #define RT_SFUD_USING_SFDP - -/* Using WiFi */ - +#define RT_SFUD_SPI_MAX_HZ 50000000 /* Using USB */ @@ -106,10 +110,10 @@ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -161,6 +165,12 @@ /* samples: kernel and components samples */ +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + + /* Hardware Drivers Config */ #define SOC_IMXRT1052CVL5B @@ -181,5 +191,6 @@ /* Onboard Peripheral Drivers */ +#define SOC_IMXRT1052 #endif diff --git a/bsp/imxrt/imxrt1052-fire-pro/.config b/bsp/imxrt/imxrt1052-fire-pro/.config index b70593a8cc53caec04535665549e3a36e7c2a3ac..52cc14f2e3009ef35475593869249575f9c69bf5 100644 --- a/bsp/imxrt/imxrt1052-fire-pro/.config +++ b/bsp/imxrt/imxrt1052-fire-pro/.config @@ -7,6 +7,8 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -63,8 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_CPU_FFS=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y # # RT-Thread Components @@ -108,19 +115,22 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_CORTEXM=y # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -128,10 +138,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -145,6 +155,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set # # Network @@ -156,14 +167,14 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -178,10 +189,10 @@ CONFIG_RT_USING_LIBC=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -190,14 +201,20 @@ CONFIG_RT_USING_LIBC=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -219,6 +236,8 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -230,13 +249,32 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set # CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -244,6 +282,8 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -258,6 +298,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -270,16 +313,27 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages # # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -287,6 +341,16 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -294,6 +358,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -302,15 +367,44 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set # CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -321,12 +415,15 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -338,6 +435,53 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set # # Hardware Drivers Config @@ -349,6 +493,7 @@ CONFIG_SOC_IMXRT1052CVL5B=y # # CONFIG_BSP_USING_DMA is not set CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_CAN is not set CONFIG_BSP_USING_LPUART=y CONFIG_BSP_USING_LPUART1=y # CONFIG_BSP_LPUART1_RX_USING_DMA is not set @@ -372,3 +517,4 @@ CONFIG_BSP_USING_LPUART1=y # # Board extended module Drivers # +CONFIG_SOC_IMXRT1052=y diff --git a/bsp/imxrt/imxrt1052-fire-pro/Kconfig b/bsp/imxrt/imxrt1052-fire-pro/Kconfig index c9221717cb4e42111c0276448be858c983657b2b..7156555e031e22dd37e80c0f62b76d3e68282f63 100644 --- a/bsp/imxrt/imxrt1052-fire-pro/Kconfig +++ b/bsp/imxrt/imxrt1052-fire-pro/Kconfig @@ -14,3 +14,9 @@ source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" source "../libraries/Kconfig" source "board/Kconfig" + +config SOC_IMXRT1052 + bool + select ARCH_ARM_CORTEX_M7 + select RT_USING_CACHE + default y diff --git a/bsp/imxrt/imxrt1052-fire-pro/rtconfig.h b/bsp/imxrt/imxrt1052-fire-pro/rtconfig.h index 6ab1a06a926715f80ba1a644e48915bbe48a486e..1d558f328f78ca458e52d08bde35ba7d6b98799c 100644 --- a/bsp/imxrt/imxrt1052-fire-pro/rtconfig.h +++ b/bsp/imxrt/imxrt1052-fire-pro/rtconfig.h @@ -40,7 +40,12 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 /* RT-Thread Components */ @@ -78,14 +83,10 @@ #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_CAN -#define RT_CAN_USING_HDR #define RT_USING_CPUTIME +#define RT_USING_CPUTIME_CORTEXM #define RT_USING_PIN -/* Using WiFi */ - - /* Using USB */ @@ -98,10 +99,10 @@ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -153,6 +154,12 @@ /* samples: kernel and components samples */ +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + + /* Hardware Drivers Config */ #define SOC_IMXRT1052CVL5B @@ -160,8 +167,6 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO -#define BSP_USING_CAN -#define BSP_USING_CAN2 #define BSP_USING_LPUART #define BSP_USING_LPUART1 @@ -170,5 +175,6 @@ /* Board extended module Drivers */ +#define SOC_IMXRT1052 #endif diff --git a/bsp/imxrt/imxrt1052-nxp-evk/.config b/bsp/imxrt/imxrt1052-nxp-evk/.config index 6c073109cc676c3f9d1513c03f09fdeb29b8a87c..1d533718b15600550045f9648f930aa2ea22c1df 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/.config +++ b/bsp/imxrt/imxrt1052-nxp-evk/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -65,8 +66,12 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x40003 -# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_CPU_FFS=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y # # RT-Thread Components @@ -117,6 +122,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_CORTEXM=y # CONFIG_RT_USING_I2C is not set CONFIG_RT_USING_PHY=y CONFIG_RT_USING_PIN=y @@ -177,9 +183,6 @@ CONFIG_NETDEV_IPV6=0 # light weight TCP/IP stack # # CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_LWIP141 is not set -# CONFIG_RT_USING_LWIP202 is not set -# CONFIG_RT_USING_LWIP212 is not set # # AT commands @@ -197,6 +200,7 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -205,14 +209,20 @@ CONFIG_NETDEV_IPV6=0 # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -234,6 +244,8 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -245,12 +257,32 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -258,6 +290,8 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -272,6 +306,9 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -284,16 +321,27 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages # # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -301,6 +349,16 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -308,7 +366,7 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -317,14 +375,44 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -335,12 +423,15 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -352,6 +443,53 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set # # Hardware Drivers Config @@ -379,3 +517,4 @@ CONFIG_BSP_USING_LPUART1=y # # Board extended module Drivers # +CONFIG_SOC_IMXRT1052=y diff --git a/bsp/imxrt/imxrt1052-nxp-evk/Kconfig b/bsp/imxrt/imxrt1052-nxp-evk/Kconfig index c9221717cb4e42111c0276448be858c983657b2b..7156555e031e22dd37e80c0f62b76d3e68282f63 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/Kconfig +++ b/bsp/imxrt/imxrt1052-nxp-evk/Kconfig @@ -14,3 +14,9 @@ source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" source "../libraries/Kconfig" source "board/Kconfig" + +config SOC_IMXRT1052 + bool + select ARCH_ARM_CORTEX_M7 + select RT_USING_CACHE + default y diff --git a/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h b/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h index 1ed1ff6671104ff57efa4ae317898b4dea8c9b6a..3410c16c7ae110daf620ae35bc238d6ecb80b0b4 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h +++ b/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h @@ -41,6 +41,11 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 /* RT-Thread Components */ @@ -78,6 +83,7 @@ #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_CPUTIME +#define RT_USING_CPUTIME_CORTEXM #define RT_USING_PHY #define RT_USING_PIN @@ -155,6 +161,12 @@ /* samples: kernel and components samples */ +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + + /* Hardware Drivers Config */ #define BSP_USING_HYPERFLASH @@ -171,5 +183,6 @@ /* Board extended module Drivers */ +#define SOC_IMXRT1052 #endif diff --git a/bsp/imxrt/imxrt1064-nxp-evk/.config b/bsp/imxrt/imxrt1064-nxp-evk/.config index 83cfa1e49580ea3cd398caf6769a6891fc2dff42..1edcd2f9f60fefe6e3e0576365f48e2989c0f273 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/.config +++ b/bsp/imxrt/imxrt1064-nxp-evk/.config @@ -7,6 +7,8 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -63,8 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_CPU_FFS=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y # # RT-Thread Components @@ -108,19 +115,22 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_CORTEXM=y # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -128,10 +138,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -145,6 +155,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set # # Network @@ -156,14 +167,14 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -178,10 +189,10 @@ CONFIG_RT_USING_LIBC=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -190,14 +201,20 @@ CONFIG_RT_USING_LIBC=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -219,6 +236,8 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -230,12 +249,32 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -243,6 +282,8 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -257,6 +298,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -269,16 +313,27 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages # # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -286,6 +341,16 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -293,7 +358,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -302,14 +367,44 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -320,12 +415,15 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -337,6 +435,53 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set # # Hardware Drivers Config @@ -355,7 +500,10 @@ CONFIG_BSP_USING_LPUART1=y # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_ETH is not set # # Board extended module Drivers # +CONFIG_SOC_IMXRT1064=y diff --git a/bsp/imxrt/imxrt1064-nxp-evk/Kconfig b/bsp/imxrt/imxrt1064-nxp-evk/Kconfig index c9221717cb4e42111c0276448be858c983657b2b..1d44b9ded2a25d0fa3f63a7be014f5815962b229 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/Kconfig +++ b/bsp/imxrt/imxrt1064-nxp-evk/Kconfig @@ -14,3 +14,9 @@ source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" source "../libraries/Kconfig" source "board/Kconfig" + +config SOC_IMXRT1064 + bool + select ARCH_ARM_CORTEX_M7 + select RT_USING_CACHE + default y diff --git a/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.h b/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.h index dfba538fd70a13f67217545877c02afa2b15628b..642cb532d83c0c6020d60226a8997b430f51a27d 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.h +++ b/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.h @@ -10,7 +10,7 @@ #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK @@ -40,7 +40,12 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 /* RT-Thread Components */ @@ -78,11 +83,9 @@ #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_CPUTIME +#define RT_USING_CPUTIME_CORTEXM #define RT_USING_PIN -/* Using WiFi */ - - /* Using USB */ @@ -95,10 +98,10 @@ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -150,6 +153,12 @@ /* samples: kernel and components samples */ +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + + /* Hardware Drivers Config */ #define BSP_USING_4MFLASH @@ -163,7 +172,9 @@ /* Onboard Peripheral Drivers */ + /* Board extended module Drivers */ +#define SOC_IMXRT1064 #endif diff --git a/bsp/lpc176x/rtconfig.h b/bsp/lpc176x/rtconfig.h index 6b28d64d326ca796bb6cdcf735724b7690ef4f82..adc9d5105d4d067627d1ed183c248b105b0da9d8 100644 --- a/bsp/lpc176x/rtconfig.h +++ b/bsp/lpc176x/rtconfig.h @@ -92,7 +92,7 @@ //
// -// #define RT_USING_LIBC +#define RT_USING_LIBC // // #define RT_USING_PTHREADS //
diff --git a/bsp/lpc178x/rtconfig.h b/bsp/lpc178x/rtconfig.h index 25f99888f751bb59459e04ba1d109dc5ed3d6a30..798ba4a50b6bab7862913965c8502ae09e0ef444 100644 --- a/bsp/lpc178x/rtconfig.h +++ b/bsp/lpc178x/rtconfig.h @@ -88,6 +88,7 @@ //
//
+#define RT_USING_LIBC // // #define RT_USING_NEWLIB // diff --git a/bsp/lpc408x/.config b/bsp/lpc408x/.config index b07e256c2620311ff2c689882f95c38eaac3353f..844d162e98e16430b31c3ab05a4f744371ebcd9c 100644 --- a/bsp/lpc408x/.config +++ b/bsp/lpc408x/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -65,11 +66,12 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_VER_NUM=0x40003 -CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CACHE is not set CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -131,6 +133,7 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set @@ -148,6 +151,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -176,9 +180,14 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set # # Network @@ -295,6 +304,9 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -320,6 +332,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -340,6 +353,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_BS8116A is not set # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -368,6 +382,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -419,6 +434,9 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_AGILE_CONSOLE is not set # CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -457,6 +475,45 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set # CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_LPC4088=y # diff --git a/bsp/lpc408x/rtconfig.h b/bsp/lpc408x/rtconfig.h index 25bba085a6490ff33c62909adc2286c2d04fe6bc..1d621a5719df0c24ee0439215f5667fdeef0a2d8 100644 --- a/bsp/lpc408x/rtconfig.h +++ b/bsp/lpc408x/rtconfig.h @@ -41,8 +41,8 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_VER_NUM 0x40003 -#define ARCH_ARM #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 @@ -107,7 +107,8 @@ /* POSIX layer and C standard library */ -#define RT_LIBC_USING_TIME +#define RT_USING_LIBC +#define RT_USING_POSIX /* Network */ @@ -168,6 +169,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_LPC4088 /* Hardware Drivers Config */ diff --git a/bsp/mini2440/.config b/bsp/mini2440/.config index 1e1372162c24f6c9f740998632ebfe2295a7280d..97c5a7151996a3f1edbcd5371fe7ec3af4d22485 100644 --- a/bsp/mini2440/.config +++ b/bsp/mini2440/.config @@ -9,6 +9,7 @@ CONFIG_BOARD_MINI2440=y # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -69,10 +70,11 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart" CONFIG_RT_VER_NUM=0x40003 -CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CACHE=y # CONFIG_RT_USING_CPU_FFS is not set -CONFIG_ARCH_ARM_ARM9=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_ARM9=y # # RT-Thread Components @@ -134,6 +136,7 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set @@ -154,8 +157,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -193,6 +198,7 @@ CONFIG_PTHREAD_NUM_MAX=8 CONFIG_RT_USING_POSIX=y CONFIG_RT_USING_POSIX_MMAP=y CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_GETLINE is not set CONFIG_RT_USING_POSIX_AIO=y CONFIG_RT_USING_MODULE=y CONFIG_RT_USING_CUSTOM_DLMODULE=y @@ -230,9 +236,10 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set -# CONFIG_RT_USING_LWIP202 is not set -CONFIG_RT_USING_LWIP210=y +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP212 is not set # CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 CONFIG_RT_LWIP_IGMP=y CONFIG_RT_LWIP_ICMP=y # CONFIG_RT_LWIP_SNMP is not set @@ -274,6 +281,7 @@ CONFIG_SO_REUSE=1 CONFIG_LWIP_SO_RCVTIMEO=1 CONFIG_LWIP_SO_SNDTIMEO=1 CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 CONFIG_RT_LWIP_NETIF_LOOPBACK=y CONFIG_LWIP_NETIF_LOOPBACK=1 CONFIG_RT_LWIP_STATS=y @@ -309,12 +317,15 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -341,6 +352,7 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -353,7 +365,7 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -375,6 +387,10 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -383,6 +399,7 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -399,6 +416,7 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -417,6 +435,9 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -428,6 +449,7 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -440,6 +462,11 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -458,6 +485,8 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_LEDBLINK is not set # CONFIG_PKG_USING_LITTLED is not set # CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set @@ -475,12 +504,23 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set # CONFIG_PKG_USING_MAX7219 is not set # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -517,3 +557,46 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_MDNS is not set +# CONFIG_PKG_USING_UPNP is not set +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set diff --git a/bsp/mini2440/Kconfig b/bsp/mini2440/Kconfig index 48e4f26a38ab111b9ee8fc5c806e655aebdc3f95..4040e73c9f5362a64749a14ea048a901afbfc227 100644 --- a/bsp/mini2440/Kconfig +++ b/bsp/mini2440/Kconfig @@ -20,6 +20,7 @@ config BOARD_MINI2440 select ARCH_ARM_ARM9 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y choice diff --git a/bsp/mini2440/rtconfig.h b/bsp/mini2440/rtconfig.h index 37c215bdd0e99dc3aa29c693d220178414888747..6c6156c1531925d05435810ebf1f8c4e0542f24c 100644 --- a/bsp/mini2440/rtconfig.h +++ b/bsp/mini2440/rtconfig.h @@ -45,6 +45,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart" #define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define ARCH_ARM #define ARCH_ARM_ARM9 @@ -153,7 +154,8 @@ /* light weight TCP/IP stack */ #define RT_USING_LWIP -#define RT_USING_LWIP210 +#define RT_USING_LWIP202 +#define RT_LWIP_MEM_ALIGNMENT 4 #define RT_LWIP_IGMP #define RT_LWIP_ICMP #define RT_LWIP_DNS @@ -189,6 +191,7 @@ #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 #define RT_LWIP_NETIF_LOOPBACK #define LWIP_NETIF_LOOPBACK 1 #define RT_LWIP_STATS @@ -246,4 +249,10 @@ /* samples: kernel and components samples */ +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + + #endif diff --git a/bsp/qemu-vexpress-a9/.config b/bsp/qemu-vexpress-a9/.config index d333d8865b29330351b3976c2abb47b0deef3355..3f8ba34cf98ce33a2a4977292a4dd73e14e6a721 100644 --- a/bsp/qemu-vexpress-a9/.config +++ b/bsp/qemu-vexpress-a9/.config @@ -8,19 +8,19 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set -CONFIG_RT_USING_SMP=y -CONFIG_RT_CPUS_NR=2 +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 +# CONFIG_RT_THREAD_PRIORITY_32 is not set +CONFIG_RT_THREAD_PRIORITY_256=y +CONFIG_RT_THREAD_PRIORITY_MAX=256 CONFIG_RT_TICK_PER_SECOND=100 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 @@ -45,7 +45,7 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y -CONFIG_RT_USING_SIGNALS=y +# CONFIG_RT_USING_SIGNALS is not set # # Memory Management @@ -68,12 +68,21 @@ CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x40002 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_USING_CACHE=y # CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0xc0000000 +CONFIG_PV_OFFSET=0xa0000000 +# CONFIG_RT_IOREMAP_LATE is not set CONFIG_ARCH_ARM_CORTEX_A=y CONFIG_ARCH_ARM_CORTEX_A9=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_ARCH_ARM_SECURE_MODE is not set +CONFIG_RT_BACKTRACE_FUNCTION_NAME=y # # RT-Thread Components @@ -86,25 +95,24 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features # -CONFIG_RT_USING_CPLUSPLUS=y +# CONFIG_RT_USING_CPLUSPLUS is not set # # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_HISTORY_LINES=10 CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 +CONFIG_FINSH_CMD_SIZE=256 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # @@ -112,9 +120,9 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=8 -CONFIG_DFS_FD_MAX=16 +CONFIG_DFS_FD_MAX=32 # CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_RT_USING_DFS_ELMFAT=y @@ -135,6 +143,7 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set @@ -144,25 +153,34 @@ CONFIG_RT_USING_DFS_RAMFS=y # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_SERIAL_RB_BUFSZ=256 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y # CONFIG_RT_USING_PWM is not set CONFIG_RT_USING_MTD_NOR=y CONFIG_RT_USING_MTD_NAND=y CONFIG_RT_MTD_NAND_DEBUG=y -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set @@ -181,6 +199,7 @@ CONFIG_RT_USING_SFUD=y CONFIG_RT_SFUD_USING_SFDP=y CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y # CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 # CONFIG_RT_DEBUG_SFUD is not set # CONFIG_RT_USING_ENC28J60 is not set # CONFIG_RT_USING_SPI_WIFI is not set @@ -188,15 +207,9 @@ CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set - -# -# Using Hardware Crypto drivers -# # CONFIG_RT_USING_HWCRYPTO is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -209,12 +222,16 @@ CONFIG_RT_USING_WDT=y # POSIX layer and C standard library # CONFIG_RT_USING_LIBC=y -CONFIG_RT_USING_PTHREADS=y -CONFIG_PTHREAD_NUM_MAX=8 +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y +# CONFIG_RT_USING_MLIB is not set +# CONFIG_RT_USING_PTHREADS is not set CONFIG_RT_USING_POSIX=y CONFIG_RT_USING_POSIX_MMAP=y -CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_GETLINE is not set CONFIG_RT_USING_POSIX_AIO=y +CONFIG_RT_POSIX_AIO_THREAD_STACK_SIZE=2048 +CONFIG_RT_USING_POSIX_CLOCKTIME=y # CONFIG_RT_USING_MODULE is not set # @@ -240,9 +257,9 @@ CONFIG_NETDEV_USING_IFCONFIG=y CONFIG_NETDEV_USING_PING=y CONFIG_NETDEV_USING_NETSTAT=y CONFIG_NETDEV_USING_AUTO_DEFAULT=y -# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_USING_IPV6=y CONFIG_NETDEV_IPV4=1 -CONFIG_NETDEV_IPV6=0 +CONFIG_NETDEV_IPV6=1 # CONFIG_NETDEV_IPV6_SCOPES is not set # @@ -251,8 +268,9 @@ CONFIG_NETDEV_IPV6=0 CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y -# CONFIG_RT_USING_LWIP210 is not set -# CONFIG_RT_USING_LWIP_IPV6 is not set +# CONFIG_RT_USING_LWIP212 is not set +CONFIG_RT_USING_LWIP_IPV6=y +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 # CONFIG_RT_LWIP_IGMP is not set CONFIG_RT_LWIP_ICMP=y # CONFIG_RT_LWIP_SNMP is not set @@ -281,7 +299,7 @@ CONFIG_RT_LWIP_TCP_SND_BUF=8196 CONFIG_RT_LWIP_TCP_WND=8196 CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=2048 # CONFIG_LWIP_NO_RX_THREAD is not set # CONFIG_LWIP_NO_TX_THREAD is not set CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 @@ -294,6 +312,7 @@ CONFIG_SO_REUSE=1 CONFIG_LWIP_SO_RCVTIMEO=1 CONFIG_LWIP_SO_SNDTIMEO=1 CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 # CONFIG_RT_LWIP_NETIF_LOOPBACK is not set CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_RT_LWIP_STATS is not set @@ -301,11 +320,6 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 CONFIG_RT_LWIP_USING_PING=y # CONFIG_RT_LWIP_DEBUG is not set -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set - # # AT commands # @@ -323,7 +337,15 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set # # RT-Thread online packages @@ -332,14 +354,20 @@ CONFIG_RT_USING_LWP=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -361,9 +389,12 @@ CONFIG_RT_USING_LWP=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set # # IoT Cloud @@ -372,20 +403,53 @@ CONFIG_RT_USING_LWP=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set # CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set # # security packages # # CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_LIBSODIUM is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -393,13 +457,46 @@ CONFIG_RT_USING_LWP=y # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set # # multimedia packages # + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set # # tools packages @@ -408,28 +505,109 @@ CONFIG_RT_USING_LWP=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set # # system packages # + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_RT_USING_ARDUINO is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_USB_STACK is not set # # peripheral libraries and drivers @@ -437,18 +615,24 @@ CONFIG_RT_USING_LWP=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -456,35 +640,120 @@ CONFIG_RT_USING_LWP=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages # + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set CONFIG_SOC_VEXPRESS_A9=y CONFIG_RT_USING_UART0=y CONFIG_RT_USING_UART1=y +CONFIG_BSP_DRV_CLCD=y +CONFIG_BSP_LCD_WIDTH=640 +CONFIG_BSP_LCD_HEIGHT=480 CONFIG_BSP_DRV_EMAC=y # CONFIG_BSP_DRV_AUDIO is not set diff --git a/bsp/qemu-vexpress-a9/.gitignore b/bsp/qemu-vexpress-a9/.gitignore index fba5a7a92ebed8855971b5a8a20308dcdd96e170..0ce2d51447d4e9a98b2429f171655766260f06be 100644 --- a/bsp/qemu-vexpress-a9/.gitignore +++ b/bsp/qemu-vexpress-a9/.gitignore @@ -42,3 +42,4 @@ settings/ cconfig.h .settings drivers/automac.h +romfs.c diff --git a/bsp/qemu-vexpress-a9/Kconfig b/bsp/qemu-vexpress-a9/Kconfig index 25921e6e7c61267fa3ac5a0c6fafaf61ca729cbb..4f518f891fcd1e35771e1e28f48194498b582167 100644 --- a/bsp/qemu-vexpress-a9/Kconfig +++ b/bsp/qemu-vexpress-a9/Kconfig @@ -21,6 +21,8 @@ source "$PKGS_DIR/Kconfig" config SOC_VEXPRESS_A9 bool select ARCH_ARM_CORTEX_A9 + select RT_USING_CACHE + select ARCH_ARM_MMU select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y diff --git a/bsp/qemu-vexpress-a9/SConscript b/bsp/qemu-vexpress-a9/SConscript index fe0ae941ae9a759ae478de901caec1c961e56af8..c7ef7659ecea92b1dd9b71a97736a8552ee02551 100644 --- a/bsp/qemu-vexpress-a9/SConscript +++ b/bsp/qemu-vexpress-a9/SConscript @@ -1,8 +1,8 @@ # for module compiling import os -Import('RTT_ROOT') +from building import * -cwd = str(Dir('#')) +cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) diff --git a/bsp/qemu-vexpress-a9/SConstruct b/bsp/qemu-vexpress-a9/SConstruct index ddfe03da28069040e4db9e96b30b6a4d0e2dba4f..cebe3f6ac5d39296d36ccfe41e8fb89949c2bdd8 100644 --- a/bsp/qemu-vexpress-a9/SConstruct +++ b/bsp/qemu-vexpress-a9/SConstruct @@ -1,6 +1,7 @@ import os import sys import rtconfig +import re if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') @@ -11,16 +12,26 @@ sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * TARGET = 'rtthread.' + rtconfig.TARGET_EXT +TRACE_CONFIG = "" + +content = "" +with open("rtconfig.h") as f: + for line in f.readlines(): + if line.find("RT_BACKTRACE_FUNCTION_NAME") != -1: + for token in line.split(" "): + if re.match(r'RT_BACKTRACE_FUNCTION_NAME$', token, flags=0): + TRACE_CONFIG = " -mpoke-function-name" DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env = Environment(tools=['mingw'], + AS=rtconfig.AS, ASFLAGS=rtconfig.AFLAGS + TRACE_CONFIG, + CC=rtconfig.CC, CFLAGS=rtconfig.CFLAGS + TRACE_CONFIG, + CXX=rtconfig.CXX, CXXFLAGS=rtconfig.CXXFLAGS + TRACE_CONFIG, + AR=rtconfig.AR, ARFLAGS='-rc', + LINK=rtconfig.LINK, LINKFLAGS=rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' Export('RTT_ROOT') Export('rtconfig') diff --git a/bsp/qemu-vexpress-a9/applications/SConscript b/bsp/qemu-vexpress-a9/applications/SConscript index 2ec6848e1dde4b705a2515ce2593b73bcdda0b38..89083a964a159e254033baaa552061b3f03addb0 100644 --- a/bsp/qemu-vexpress-a9/applications/SConscript +++ b/bsp/qemu-vexpress-a9/applications/SConscript @@ -4,7 +4,7 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd, str(Dir('#'))] +CPPPATH = [cwd] group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/qemu-vexpress-a9/applications/main.c b/bsp/qemu-vexpress-a9/applications/main.c index d59513bce87ec6d98d1b704ffb8ada261ce7acc3..d6a5fedd0719e44aec0cb01f9a2fa14c883d6569 100644 --- a/bsp/qemu-vexpress-a9/applications/main.c +++ b/bsp/qemu-vexpress-a9/applications/main.c @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/10/7 bernard the first version + */ #include #include #include diff --git a/bsp/qemu-vexpress-a9/applications/mnt.c b/bsp/qemu-vexpress-a9/applications/mnt.c index de2cd0b87cc42d869990e9583cd5f13af71ac9d5..0fc9b62860b9a1d6090c433bed5a5c7873844649 100644 --- a/bsp/qemu-vexpress-a9/applications/mnt.c +++ b/bsp/qemu-vexpress-a9/applications/mnt.c @@ -2,16 +2,24 @@ #ifdef RT_USING_DFS #include +#include int mnt_init(void) { - rt_thread_delay(RT_TICK_PER_SECOND); + if (dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) != 0) + { + rt_kprintf("Dir / mount failed!\n"); + return -1; + } - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + rt_thread_mdelay(200); + if (dfs_mount("sd", "/mnt", "elm", 0, NULL) != 0) { - rt_kprintf("file system initialization done!\n"); + rt_kprintf("Dir /mnt mount failed!\n"); + return -1; } + rt_kprintf("file system initialization done!\n"); return 0; } INIT_ENV_EXPORT(mnt_init); diff --git a/bsp/qemu-vexpress-a9/applications/romfs.c b/bsp/qemu-vexpress-a9/applications/romfs.c new file mode 100644 index 0000000000000000000000000000000000000000..c28ba8ea7f2e52f05d808138b39f60d531ee57a2 --- /dev/null +++ b/bsp/qemu-vexpress-a9/applications/romfs.c @@ -0,0 +1,16 @@ +/* Generated by mkromfs. Edit with caution. */ +#include +#include + + + + + +static const struct romfs_dirent _romfs_root[] = { + {ROMFS_DIRENT_DIR, "etc", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "mnt", RT_NULL, 0} +}; + +const struct romfs_dirent romfs_root = { + ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root)/sizeof(_romfs_root[0]) +}; diff --git a/bsp/qemu-vexpress-a9/drivers/Kconfig b/bsp/qemu-vexpress-a9/drivers/Kconfig index d2aa5bc8e4cc568e85e1c9e9481d0b001d4d80f0..ce3d2c397893717c1c9965d1b7f7c13dc2999ca5 100644 --- a/bsp/qemu-vexpress-a9/drivers/Kconfig +++ b/bsp/qemu-vexpress-a9/drivers/Kconfig @@ -8,7 +8,6 @@ config RT_USING_UART1 config BSP_DRV_CLCD bool "CLCD driver" - depends on PKG_USING_GUIENGINE default y if BSP_DRV_CLCD @@ -23,7 +22,6 @@ endif config BSP_DRV_EMAC bool "EMAC driver" - depends on RT_USING_LWIP default y config BSP_DRV_AUDIO diff --git a/bsp/qemu-vexpress-a9/drivers/automac.h b/bsp/qemu-vexpress-a9/drivers/automac.h deleted file mode 100644 index 5f08b79a41d262ffab75f25f61ecb6f4e20fdd5f..0000000000000000000000000000000000000000 --- a/bsp/qemu-vexpress-a9/drivers/automac.h +++ /dev/null @@ -1,15 +0,0 @@ - -#ifndef __MAC_AUTO_GENERATE_H__ -#define __MAC_AUTO_GENERATE_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* mac configure file for RT-Thread qemu */ - -#define AUTOMAC0 0x52 -#define AUTOMAC1 0x54 -#define AUTOMAC2 0x00 -#define AUTOMAC3 0x28 -#define AUTOMAC4 0xae -#define AUTOMAC5 0xeb - -#endif diff --git a/bsp/qemu-vexpress-a9/drivers/board.c b/bsp/qemu-vexpress-a9/drivers/board.c index e236c68b80b1f611bd8fe51b714228d8998ed7c4..2c6e172f0b5661295ba50cdeaf2ec45e57b2f6cb 100644 --- a/bsp/qemu-vexpress-a9/drivers/board.c +++ b/bsp/qemu-vexpress-a9/drivers/board.c @@ -18,11 +18,21 @@ #include "drv_timer.h" #include +#ifdef RT_USING_USERSPACE +#include +#include +#endif +#ifdef RT_USING_USERSPACE +struct mem_desc platform_mem_desc[] = { + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0fffffff, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM} +}; +#else struct mem_desc platform_mem_desc[] = { {0x10000000, 0x50000000, 0x10000000, DEVICE_MEM}, - {0x60000000, 0xe0000000, 0x60000000, NORMAL_MEM} + {0x60000000, 0x70000000, 0x60000000, NORMAL_MEM} }; +#endif const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); @@ -36,12 +46,37 @@ void idle_wfi(void) } /** - * This function will initialize beaglebone board + * This function will initialize board */ + +rt_mmu_info mmu_info; + +extern size_t MMUTable[]; + +#ifdef RT_USING_USERSPACE +rt_region_t init_page_region = { + (uint32_t)PAGE_START, + (uint32_t)PAGE_END, +}; +#endif + void rt_hw_board_init(void) { +#ifdef RT_USING_USERSPACE + rt_hw_mmu_map_init(&mmu_info, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); + + rt_page_init(init_page_region); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0xf0000000, 0x10000000); + + arch_kuser_init(&mmu_info, (void*)0xffff0000); +#else + rt_hw_mmu_map_init(&mmu_info, (void*)0x80000000, 0x10000000, MMUTable, 0); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0x80000000, 0x10000000); +#endif + /* initialize hardware interrupt */ rt_hw_interrupt_init(); + /* initialize system heap */ rt_system_heap_init(HEAP_BEGIN, HEAP_END); diff --git a/bsp/qemu-vexpress-a9/drivers/board.h b/bsp/qemu-vexpress-a9/drivers/board.h index ccbe0f8c9e4c09c235d7a4bf117d9ef3f100aaea..10c7bf27dbc453241daa9d045308ceb3c26b7398 100644 --- a/bsp/qemu-vexpress-a9/drivers/board.h +++ b/bsp/qemu-vexpress-a9/drivers/board.h @@ -15,9 +15,13 @@ #ifndef __BOARD_H__ #define __BOARD_H__ +#include #include #include "vexpress_a9.h" +#include "mmu.h" +#include "ioremap.h" + #if defined(__CC_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) @@ -26,8 +30,16 @@ extern int __bss_end; #define HEAP_BEGIN ((void*)&__bss_end) #endif -#define HEAP_END (void*)(0x60000000 + 8 * 1024 * 1024) +#ifdef RT_USING_USERSPACE +#define HEAP_END (void*)(KERNEL_VADDR_START + 16 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END (void*)(KERNEL_VADDR_START + 128 * 1024 * 1024) +#else +#define HEAP_END (void*)(0x60000000 + 64 * 1024 * 1024) +#endif void rt_hw_board_init(void); +extern rt_mmu_info mmu_info; + #endif diff --git a/bsp/qemu-vexpress-a9/drivers/drv_clcd.c b/bsp/qemu-vexpress-a9/drivers/drv_clcd.c index 62b5aa772d70de97477e0c7130d57bd666621763..1b48b279ee01a53efbf82aca0524409301b7305e 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_clcd.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_clcd.c @@ -3,7 +3,13 @@ #include #include +#include + +#include +#include + #include "drv_clcd.h" +#include "rt_lcd.h" #define CLCD_WIDTH (BSP_LCD_WIDTH) #define CLCD_HEIGHT (BSP_LCD_HEIGHT) @@ -35,6 +41,7 @@ struct drv_clcd_device int height; uint8_t *fb; + uint8_t *fb_virt; }; struct drv_clcd_device _lcd; @@ -42,7 +49,7 @@ static rt_err_t drv_clcd_init(struct rt_device *device) { struct drv_clcd_device *lcd = CLCD_DEVICE(device); - lcd = lcd; /* nothing, right now */ + (void)lcd; /* nothing, right now */ return RT_EOK; } @@ -56,7 +63,8 @@ static rt_err_t drv_clcd_control(struct rt_device *device, int cmd, void *args) { struct rt_device_rect_info *info = (struct rt_device_rect_info*)args; - info = info; /* nothing, right now */ + (void)info; /* nothing, right now */ + rt_kprintf("update screen...\n"); } break; @@ -66,20 +74,44 @@ static rt_err_t drv_clcd_control(struct rt_device *device, int cmd, void *args) RT_ASSERT(info != RT_NULL); info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; - // info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_ARGB888; info->bits_per_pixel= 16; info->width = lcd->width; info->height = lcd->height; info->framebuffer = lcd->fb; } break; + + case FBIOGET_FSCREENINFO: + { +#ifdef RT_USING_USERSPACE + struct fb_fix_screeninfo *info = (struct fb_fix_screeninfo *)args; + strncpy(info->id, "lcd", sizeof(info->id)); + info->smem_len = lcd->width * lcd->height * 2; + info->smem_start = (uint32_t)lwp_map_user_phy(lwp_self(), RT_NULL, lcd->fb, + info->smem_len, 1); + info->line_length = lcd->width * 2; +#endif + } + break; + + case FBIOGET_VSCREENINFO: + { + struct fb_var_screeninfo *info = (struct fb_var_screeninfo *)args; + info->bits_per_pixel = 16; + info->xres = lcd->width; + info->yres = lcd->height; + } + break; + + case FBIOGET_DISPINFO: + break; } return RT_EOK; } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops clcd_ops = +const static struct rt_device_ops clcd_ops = { drv_clcd_init, RT_NULL, @@ -100,7 +132,21 @@ int drv_clcd_hw_init(void) _lcd.width = CLCD_WIDTH; _lcd.height = CLCD_HEIGHT; - _lcd.fb = rt_malloc (_lcd.width * _lcd.height * 2); + rt_kprintf("try to allocate fb... | w - %d, h - %d | ", _lcd.width, _lcd.height); +#ifdef RT_USING_USERSPACE + _lcd.fb_virt= rt_pages_alloc (rt_page_bits(_lcd.width * _lcd.height * 2)); + _lcd.fb = _lcd.fb_virt + PV_OFFSET; + rt_kprintf("done!\n"); + rt_kprintf("fb => 0x%08x\n", _lcd.fb); + if (_lcd.fb == NULL) + { + rt_kprintf("initialize frame buffer failed!\n"); + return -1; + } + + memset(_lcd.fb_virt, 0xff, _lcd.width * _lcd.height * 2); +#else + _lcd.fb = rt_malloc(_lcd.width * _lcd.height * 2); if (_lcd.fb == NULL) { rt_kprintf("initialize frame buffer failed!\n"); @@ -108,10 +154,11 @@ int drv_clcd_hw_init(void) } memset(_lcd.fb, 0xff, _lcd.width * _lcd.height * 2); +#endif - plio = (PL111MMIO*)PL111_IOBASE; + plio = (PL111MMIO *)rt_ioremap((void*)PL111_IOBASE, 0x1000); - plio->tim0 = 0x3F1F3C00 | ((CLCD_WIDTH/16 - 1) << 2); + plio->tim0 = 0x3F1F3C00 | ((CLCD_WIDTH / 16 - 1) << 2); plio->tim1 = 0x080B6000 | (CLCD_HEIGHT - 1); plio->upbase = (uint32_t)_lcd.fb; diff --git a/bsp/qemu-vexpress-a9/drivers/drv_keyboard.c b/bsp/qemu-vexpress-a9/drivers/drv_keyboard.c index 246e053a60ed5d1dcbf01ddcdcbe2bca593c9ade..3f961b40ae0c07aea803e97be3777d36b9e83669 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_keyboard.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_keyboard.c @@ -422,9 +422,11 @@ int rt_hw_keyboard_init(void) rt_uint8_t value; rt_uint32_t id; struct keyboard_pl050_pdata_t *pdat; - virtual_addr_t virt = (virtual_addr_t)KEYBOARD_ADDRESS; + virtual_addr_t virt; int irq = KEYBOARD_IRQ_NUM; - + + virt = (virtual_addr_t)rt_ioremap((void*)KEYBOARD_ADDRESS, 0x1000); + id = (((read32(virt + 0xfec) & 0xff) << 24) | ((read32(virt + 0xfe8) & 0xff) << 16) | ((read32(virt + 0xfe4) & 0xff) << 8) | @@ -469,3 +471,4 @@ int rt_hw_keyboard_init(void) INIT_DEVICE_EXPORT(rt_hw_keyboard_init); #endif + diff --git a/bsp/qemu-vexpress-a9/drivers/drv_mouse.c b/bsp/qemu-vexpress-a9/drivers/drv_mouse.c index 07e3ed16f6feeabd78664701eed2d8be38ca5881..d3244bcd29f2f2627f0f755b3cf3466690f40b78 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_mouse.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_mouse.c @@ -227,9 +227,11 @@ int rt_hw_mouse_init(void) rt_uint8_t value; rt_uint32_t id; struct mouse_pl050_pdata_t *pdat; - virtual_addr_t virt = MOUSE_ADDRESS; + virtual_addr_t virt; int irq = MOUSE_IRQ_NUM; + virt = (virtual_addr_t)rt_ioremap((void*)MOUSE_ADDRESS, 0x1000); + id = (((read32(virt + 0xfec) & 0xff) << 24) | ((read32(virt + 0xfe8) & 0xff) << 16) | ((read32(virt + 0xfe4) & 0xff) << 8) | @@ -295,3 +297,4 @@ int rt_hw_mouse_init(void) INIT_DEVICE_EXPORT(rt_hw_mouse_init); #endif + diff --git a/bsp/qemu-vexpress-a9/drivers/drv_mouse.h b/bsp/qemu-vexpress-a9/drivers/drv_mouse.h index c5d190950a6e1b49b0ea4ab46130a505b3eab3c3..cfceabc00d461735b863e4970711d7473161cceb 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_mouse.h +++ b/bsp/qemu-vexpress-a9/drivers/drv_mouse.h @@ -3,4 +3,16 @@ int rt_hw_mouse_init(void); +struct mouse_info +{ + uint32_t type; + uint32_t button; + uint32_t x; + uint32_t y; + uint32_t ts; + uint32_t id; +}; + +#define CMD_MOUSE_SET_NOTIFY 0 /* arg is shmid, in the shm, a sem point is given */ + #endif \ No newline at end of file diff --git a/bsp/qemu-vexpress-a9/drivers/drv_sdio.c b/bsp/qemu-vexpress-a9/drivers/drv_sdio.c index 26282226273dbf1beba0f6698ac2751c04a270fa..d4aaf285e4f2cef7772dd00e8120711b3794534a 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_sdio.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_sdio.c @@ -6,6 +6,7 @@ #include #include +#include "board.h" #include "drv_sdio.h" #ifdef RT_USING_SDIO @@ -285,13 +286,13 @@ static rt_err_t sdhci_pl180_setclock(struct sdhci_t * sdhci, rt_uint32_t clock) if(clock) { - temp = read32(pdat->virt + PL180_CLOCK) | (0x1<<8); - temp = temp; // skip warning + temp = read32(pdat->virt + PL180_CLOCK) | (0x1 << 8); + (void)temp; // skip warning write32(pdat->virt + PL180_CLOCK, 0x100); } else { - //write32(pdat->virt + PL180_CLOCK, read32(pdat->virt + PL180_CLOCK) & (~(0x1<<8))); + //write32(pdat->virt + PL180_CLOCK, read32(pdat->virt + PL180_CLOCK) & (~(0x1 << 8))); } return RT_EOK; } @@ -379,7 +380,7 @@ static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io LOG_D("clock:%d bus_width:%d", io_cfg->clock, io_cfg->bus_width); } -static const struct rt_mmcsd_host_ops ops = +static const struct rt_mmcsd_host_ops ops = { mmc_request_send, mmc_set_iocfg, @@ -410,7 +411,8 @@ int pl180_init(void) } rt_memset(sdhci, 0, sizeof(struct sdhci_t)); - virt = MMC_BASE_ADDR; + virt = (rt_uint32_t)rt_ioremap((void*)MMC_BASE_ADDR, 0x1000); + id = (((read32((virt + 0xfec)) & 0xff) << 24) | ((read32((virt + 0xfe8)) & 0xff) << 16) | ((read32((virt + 0xfe4)) & 0xff) << 8) | diff --git a/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c b/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c index 91a931125567d641c154787804a564b7907c0e15..7493c8a4e52a4ec311e67dc31ef816aade7d29b3 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c @@ -1,16 +1,22 @@ #include #include +#include +#include #include #include -#include + +#include "mmu.h" +#include "drv_smc911x.h" #define MAX_ADDR_LEN 6 #define SMC911X_EMAC_DEVICE(eth) (struct eth_device_smc911x*)(eth) -#include "drv_smc911x.h" - #define DRIVERNAME "EMAC" +#define DBG_LVL DBG_LOG +#define DBG_TAG "EMAC" +#include + struct eth_device_smc911x { /* inherit from Ethernet device */ @@ -116,7 +122,7 @@ static int smc911x_detect_chip(struct eth_device_smc911x *dev) } else if (val != 0x87654321) { - rt_kprintf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); + LOG_E("Invalid chip endian 0x%08lx\n", val); return -1; } @@ -320,7 +326,7 @@ static void smc911x_isr(int vector, void *param) emac = SMC911X_EMAC_DEVICE(param); status = smc911x_reg_read(emac, INT_STS); - + if (status & INT_STS_RSFL) { eth_device_ready(&emac->parent); @@ -347,21 +353,12 @@ static rt_err_t smc911x_emac_init(rt_device_t dev) /* Turn on Tx + Rx */ smc911x_enable(emac); -#if 1 /* Interrupt on every received packet */ smc911x_reg_write(emac, FIFO_INT, 0x01 << 8); smc911x_reg_write(emac, INT_EN, INT_EN_RDFL_EN | INT_EN_RSFL_EN); /* enable interrupt */ smc911x_reg_write(emac, INT_CFG, INT_CFG_IRQ_EN | INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE); -#else - - /* disable interrupt */ - smc911x_reg_write(emac, INT_EN, 0); - value = smc911x_reg_read(emac, INT_CFG); - value &= ~INT_CFG_IRQ_EN; - smc911x_reg_write(emac, INT_CFG, value); -#endif rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x"); rt_hw_interrupt_umask(emac->irqno); @@ -383,6 +380,7 @@ static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args) if(args) rt_memcpy(args, emac->enetaddr, 6); else return -RT_ERROR; break; + default : break; } @@ -432,12 +430,12 @@ rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p) if (!status) return 0; - rt_kprintf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n", - status & TX_STS_LOC ? "TX_STS_LOC " : "", - status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "", - status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "", - status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "", - status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : ""); + LOG_E("failed to send packet: %s%s%s%s%s", + status & TX_STS_LOC ? "TX_STS_LOC " : "", + status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "", + status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "", + status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "", + status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : ""); return -RT_EIO; } @@ -500,7 +498,9 @@ const static struct rt_device_ops smc911x_emac_ops = int smc911x_emac_hw_init(void) { - _emac.iobase = VEXPRESS_ETH_BASE; + rt_memset(&_emac, 0x0, sizeof(_emac)); + + _emac.iobase = (uint32_t)rt_ioremap((void*)VEXPRESS_ETH_BASE, 0x1000); _emac.irqno = IRQ_VEXPRESS_A9_ETH; if (smc911x_detect_chip(&_emac)) diff --git a/bsp/qemu-vexpress-a9/drivers/drv_timer.c b/bsp/qemu-vexpress-a9/drivers/drv_timer.c index 7abfea0fae6fe1aa68b86ad9905a4d67c8ee987d..8dcc6e2c3e78b9158c4bd4312a25a9f5e593bc96 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_timer.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_timer.c @@ -12,10 +12,17 @@ #include #include +#include "mmu.h" #include "board.h" -#define TIMER01_HW_BASE 0x10011000 -#define TIMER23_HW_BASE 0x10012000 +#define TIMER01_HW_BASE_PHY 0x10011000 +#define TIMER23_HW_BASE_PHY 0x10012000 + +void* timer01_hw_base; +void* timer23_hw_base; + +#define TIMER01_HW_BASE timer01_hw_base +#define TIMER23_HW_BASE timer23_hw_base #define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00) #define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04) @@ -51,8 +58,10 @@ #define TIMER_MIS(hw_base) __REG32(hw_base + 0x14) #define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18) -#define SYS_CTRL __REG32(REALVIEW_SCTL_BASE) -#define TIMER_HW_BASE REALVIEW_TIMER2_3_BASE +void* sys_ctrl; +#define SYS_CTRL __REG32(sys_ctrl) +void* timer_hw_base; +#define TIMER_HW_BASE timer_hw_base static void rt_hw_timer_isr(int vector, void *param) { @@ -65,6 +74,9 @@ int rt_hw_timer_init(void) { rt_uint32_t val; + sys_ctrl = (void*)rt_ioremap((void*)REALVIEW_SCTL_BASE, 0x1000); + timer_hw_base = (void*)rt_ioremap((void*)REALVIEW_TIMER2_3_BASE, 0x1000); + SYS_CTRL |= REALVIEW_REFCLK; /* Setup Timer0 for generating irq */ @@ -89,8 +101,9 @@ void timer_init(int timer, unsigned int preload) { uint32_t val; - if (timer == 0) + if (timer == 0) { + timer01_hw_base = (void*)rt_ioremap((void*)TIMER01_HW_BASE_PHY, 0x1000); /* Setup Timer0 for generating irq */ val = TIMER_CTRL(TIMER01_HW_BASE); val &= ~TIMER_CTRL_ENABLE; @@ -101,9 +114,10 @@ void timer_init(int timer, unsigned int preload) /* enable timer */ TIMER_CTRL(TIMER01_HW_BASE) |= TIMER_CTRL_ENABLE; - } - else + } + else { + timer23_hw_base = (void*)rt_ioremap((void*)TIMER23_HW_BASE_PHY, 0x1000); /* Setup Timer1 for generating irq */ val = TIMER_CTRL(TIMER23_HW_BASE); val &= ~TIMER_CTRL_ENABLE; @@ -122,7 +136,7 @@ void timer_clear_pending(int timer) if (timer == 0) { TIMER_INTCLR(TIMER01_HW_BASE) = 0x01; - } + } else { TIMER_INTCLR(TIMER23_HW_BASE) = 0x01; diff --git a/bsp/qemu-vexpress-a9/drivers/realview.h b/bsp/qemu-vexpress-a9/drivers/realview.h index 1a369dbdd053a8892f62b2e7048da67997d1030d..d63df40f452004d7a0f59946eb20b0ffc057f78e 100644 --- a/bsp/qemu-vexpress-a9/drivers/realview.h +++ b/bsp/qemu-vexpress-a9/drivers/realview.h @@ -316,7 +316,8 @@ struct rt_hw_register unsigned long ORIG_r0; }; -#include +#include +#include /* Interrupt Control Interface */ #define ARM_GIC_CPU_BASE 0x1E000000 diff --git a/bsp/qemu-vexpress-a9/drivers/rt_lcd.h b/bsp/qemu-vexpress-a9/drivers/rt_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..e496a871da38693db597dcc45ac9a181c8d0c55a --- /dev/null +++ b/bsp/qemu-vexpress-a9/drivers/rt_lcd.h @@ -0,0 +1,59 @@ +#ifndef RT_LCD_H__ +#define RT_LCD_H__ + + +/* ioctls + 0x46 is 'F' */ +#define FBIOGET_VSCREENINFO 0x4600 +#define FBIOPUT_VSCREENINFO 0x4601 +#define FBIOGET_FSCREENINFO 0x4602 +#define FBIOGETCMAP 0x4604 +#define FBIOPUTCMAP 0x4605 +#define FBIOPAN_DISPLAY 0x4606 +#define FBIO_CURSOR 0x4608 +/* #define FBIOGET_MONITORSPEC 0x460C */ +/* #define FBIOPUT_MONITORSPEC 0x460D */ +/* #define FBIOSWITCH_MONIBIT 0x460E */ +#define FBIOGET_CON2FBMAP 0x460F +#define FBIOPUT_CON2FBMAP 0x4610 +#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ +#define FBIOGET_VBLANK 0x4612 +#define FBIO_ALLOC 0x4613 +#define FBIO_FREE 0x4614 +#define FBIOGET_GLYPH 0x4615 +#define FBIOGET_HWCINFO 0x4616 +#define FBIOPUT_MODEINFO 0x4617 +#define FBIOGET_DISPINFO 0x4618 +#define FBIO_WAITFORVSYNC 0x4620 + +struct fb_bitfield +{ + uint32_t offset; /* beginning of bitfield */ + uint32_t length; /* length of bitfield */ + uint32_t msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +struct fb_var_screeninfo +{ + uint32_t xres; + uint32_t yres; + + uint32_t bits_per_pixel; + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ +}; + +struct fb_fix_screeninfo +{ + char id[16]; + unsigned long smem_start; + uint32_t smem_len; + + uint32_t line_length; +}; + +#endif diff --git a/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c index 3b0428859f4a52c335cf63ea254dded17a56a461..b455beb53afe3a48a936e7365826826078a3741c 100644 --- a/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c +++ b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c @@ -19,6 +19,10 @@ #ifdef RT_USING_SMP #include +#ifdef RT_USING_USERSPACE +#include +#endif + static void rt_hw_timer2_isr(int vector, void *param) { rt_tick_increase(); @@ -28,20 +32,32 @@ static void rt_hw_timer2_isr(int vector, void *param) void rt_hw_secondary_cpu_up(void) { - extern void set_secondary_cpu_boot_address(void); + volatile void **plat_boot_reg = (volatile void **)0x10000034; + char *entry = (char *)rt_secondary_cpu_entry; - set_secondary_cpu_boot_address(); - __asm__ volatile ("dsb":::"memory"); +#ifdef RT_USING_USERSPACE + plat_boot_reg = (volatile void **)rt_hw_mmu_map(&mmu_info, 0, (void *)plat_boot_reg, 0x1000, MMU_MAP_K_RW); + if (!plat_boot_reg) + { + /* failed */ + return; + } + entry += PV_OFFSET; +#endif + *plat_boot_reg-- = (void *)(size_t)-1; + *plat_boot_reg = (void *)entry; + rt_hw_dsb(); rt_hw_ipi_send(0, 1 << 1); } -void secondary_cpu_c_start(void) +/* Interface */ +void rt_hw_secondary_cpu_bsp_start(void) { rt_hw_vector_init(); rt_hw_spin_lock(&_cpus_lock); - arm_gic_cpu_init(0, REALVIEW_GIC_CPU_BASE); + arm_gic_cpu_init(0, 0); arm_gic_set_cpu(0, IRQ_PBA8_TIMER0_1, 0x2); timer_init(0, 10000); diff --git a/bsp/qemu-vexpress-a9/drivers/serial.c b/bsp/qemu-vexpress-a9/drivers/serial.c index 786a26a4ba0f115f594870da23094c6e647296d1..c6bc451c8bb40b28060e8766352adf58521e53a1 100644 --- a/bsp/qemu-vexpress-a9/drivers/serial.c +++ b/bsp/qemu-vexpress-a9/drivers/serial.c @@ -31,6 +31,8 @@ #include #include "serial.h" +#include "board.h" +#include "mmu.h" struct hw_uart_device { @@ -151,6 +153,7 @@ int rt_hw_uart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef RT_USING_UART0 + _uart0_device.hw_base = (uint32_t)rt_ioremap((void*)_uart0_device.hw_base, 0x1000); uart = &_uart0_device; _serial0.ops = &_uart_ops; @@ -166,6 +169,7 @@ int rt_hw_uart_init(void) #endif #ifdef RT_USING_UART1 + _uart1_device.hw_base = (uint32_t)rt_ioremap((void*)_uart1_device.hw_base, 0x1000); uart = &_uart1_device; _serial1.ops = &_uart_ops; _serial1.config = config; diff --git a/bsp/qemu-vexpress-a9/gdb.init b/bsp/qemu-vexpress-a9/gdb.init new file mode 100644 index 0000000000000000000000000000000000000000..b16f519fc68630344fcf9ff3405b4ac444410f78 --- /dev/null +++ b/bsp/qemu-vexpress-a9/gdb.init @@ -0,0 +1,3 @@ +target remote localhost:1234 +b *0x100010 +add-symbol-file ../../../userapps/gnu-apps/wget/wget-1.20/src/wget 0x100000 diff --git a/bsp/qemu-vexpress-a9/link.lds b/bsp/qemu-vexpress-a9/link.lds index 797cd7e3ef8c0707525878d8665574b95186e615..c3d6e540043583707c1a9810930ea0af6ee4c2fe 100644 --- a/bsp/qemu-vexpress-a9/link.lds +++ b/bsp/qemu-vexpress-a9/link.lds @@ -2,7 +2,8 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) SECTIONS { - . = 0x60010000; + /*. = 0x60010000; */ + . = 0xc0010000; __text_start = .; .text : @@ -16,7 +17,7 @@ SECTIONS __rt_utest_tc_tab_start = .; KEEP(*(UtestTcTab)) __rt_utest_tc_tab_end = .; - + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -42,9 +43,12 @@ SECTIONS } =0 __text_end = .; - __exidx_start = .; - .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } - __exidx_end = .; + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } __rodata_start = .; .rodata : { *(.rodata) *(.rodata.*) } @@ -54,16 +58,16 @@ SECTIONS .ctors : { PROVIDE(__ctors_start__ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) PROVIDE(__ctors_end__ = .); } .dtors : { PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) PROVIDE(__dtors_end__ = .); } @@ -76,7 +80,7 @@ SECTIONS } __data_end = .; - . = ALIGN(8); + . = ALIGN(4); __bss_start = .; .bss : { diff --git a/bsp/qemu-vexpress-a9/qemu-dbg.bat b/bsp/qemu-vexpress-a9/qemu-dbg.bat index b4a04cf2a94d9fb42a2c56103d5b926d9d6908e8..9190b74398dd95584cabc86ab00a8927ee250934 100644 --- a/bsp/qemu-vexpress-a9/qemu-dbg.bat +++ b/bsp/qemu-vexpress-a9/qemu-dbg.bat @@ -3,4 +3,4 @@ if exist sd.bin goto run qemu-img create -f raw sd.bin 64M :run -qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial stdio -sd sd.bin -S -s +qemu-system-arm -M vexpress-a9 -kernel rtthread.bin -serial stdio -sd sd.bin -S -s diff --git a/bsp/qemu-vexpress-a9/qemu-dbg.sh b/bsp/qemu-vexpress-a9/qemu-dbg.sh index 44bc1ad9676e8a0c2abeb3446d32195da737cc19..4f2067cbc899a7c7199974e190ac584263ec7beb 100755 --- a/bsp/qemu-vexpress-a9/qemu-dbg.sh +++ b/bsp/qemu-vexpress-a9/qemu-dbg.sh @@ -2,5 +2,6 @@ if [ ! -f "sd.bin" ]; then dd if=/dev/zero of=sd.bin bs=1024 count=65536 fi +#qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial vc -serial vc -sd sd.bin -S -s +qemu-system-arm -M vexpress-a9 -kernel rtthread.bin -nographic -sd sd.bin -S -s -qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial vc -serial vc -sd sd.bin -S -s \ No newline at end of file diff --git a/bsp/qemu-vexpress-a9/qemu-nographic.bat b/bsp/qemu-vexpress-a9/qemu-nographic.bat index 4b978dc967c878822c58a87553eaed5d1903fdff..323d70b77f264e37f67f77ca3ba13c63ad9f775c 100644 --- a/bsp/qemu-vexpress-a9/qemu-nographic.bat +++ b/bsp/qemu-vexpress-a9/qemu-nographic.bat @@ -3,4 +3,4 @@ if exist sd.bin goto run qemu-img create -f raw sd.bin 64M :run -qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -nographic -sd sd.bin +qemu-system-arm -M vexpress-a9 -kernel rtthread.bin -nographic -sd sd.bin diff --git a/bsp/qemu-vexpress-a9/qemu-nographic.sh b/bsp/qemu-vexpress-a9/qemu-nographic.sh index b4168b8d5c9f78c2ea23735cf04e558463721e83..5519c6c2213e4e3168781cf11b2b2c227ce8d95e 100755 --- a/bsp/qemu-vexpress-a9/qemu-nographic.sh +++ b/bsp/qemu-vexpress-a9/qemu-nographic.sh @@ -2,5 +2,4 @@ if [ ! -f "sd.bin" ]; then dd if=/dev/zero of=sd.bin bs=1024 count=65536 fi -qemu-system-arm -M vexpress-a9 -smp cpus=2 -kernel rtthread.bin -nographic -sd sd.bin -net nic -net tap - +qemu-system-arm -M vexpress-a9 -smp cpus=2 -kernel rtthread.bin -nographic -sd sd.bin diff --git a/bsp/qemu-vexpress-a9/rtconfig.h b/bsp/qemu-vexpress-a9/rtconfig.h index cec4ec6ba4b882c2af8cca0c2efb1c4208bcfba5..eefc4acb134d67bdc4401466756329e0eb38059e 100644 --- a/bsp/qemu-vexpress-a9/rtconfig.h +++ b/bsp/qemu-vexpress-a9/rtconfig.h @@ -7,17 +7,16 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 -#define RT_USING_SMP -#define RT_CPUS_NR 2 +#define RT_USING_SMART #define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_256 +#define RT_THREAD_PRIORITY_MAX 256 #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 1024 +#define IDLE_THREAD_STACK_SIZE 4096 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 1024 @@ -31,7 +30,6 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -#define RT_USING_SIGNALS /* Memory Management */ @@ -49,10 +47,17 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x40002 +#define RT_VER_NUM 0x50000 +#define RT_USING_CACHE +#define ARCH_MM_MMU #define ARCH_ARM +#define ARCH_ARM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0xc0000000 +#define PV_OFFSET 0xa0000000 #define ARCH_ARM_CORTEX_A #define ARCH_ARM_CORTEX_A9 +#define RT_BACKTRACE_FUNCTION_NAME /* RT-Thread Components */ @@ -63,30 +68,29 @@ /* C++ features */ -#define RT_USING_CPLUSPLUS /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" #define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 +#define FINSH_HISTORY_LINES 10 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT +#define FINSH_CMD_SIZE 256 #define FINSH_ARG_MAX 10 /* Device virtual file system */ #define RT_USING_DFS #define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 8 -#define DFS_FD_MAX 16 +#define DFS_FD_MAX 32 #define RT_USING_DFS_ELMFAT /* elm-chan's FatFs, Generic FAT Filesystem Module */ @@ -106,16 +110,21 @@ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 #define RT_PIPE_BUFSZ 512 #define RT_USING_SYSTEM_WORKQUEUE #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 +#define RT_SERIAL_RB_BUFSZ 256 +#define RT_USING_TTY #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM #define RT_USING_MTD_NOR #define RT_USING_MTD_NAND #define RT_MTD_NAND_DEBUG @@ -132,26 +141,21 @@ #define RT_USING_SFUD #define RT_SFUD_USING_SFDP #define RT_SFUD_USING_FLASH_INFO_TABLE +#define RT_SFUD_SPI_MAX_HZ 50000000 #define RT_USING_WDT -/* Using Hardware Crypto drivers */ - - -/* Using WiFi */ - - /* Using USB */ /* POSIX layer and C standard library */ #define RT_USING_LIBC -#define RT_USING_PTHREADS -#define PTHREAD_NUM_MAX 8 +#define RT_USING_MUSL #define RT_USING_POSIX #define RT_USING_POSIX_MMAP -#define RT_USING_POSIX_TERMIOS #define RT_USING_POSIX_AIO +#define RT_POSIX_AIO_THREAD_STACK_SIZE 2048 +#define RT_USING_POSIX_CLOCKTIME /* Network */ @@ -171,13 +175,16 @@ #define NETDEV_USING_PING #define NETDEV_USING_NETSTAT #define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_USING_IPV6 #define NETDEV_IPV4 1 -#define NETDEV_IPV6 0 +#define NETDEV_IPV6 1 /* light weight TCP/IP stack */ #define RT_USING_LWIP #define RT_USING_LWIP202 +#define RT_USING_LWIP_IPV6 +#define RT_LWIP_MEM_ALIGNMENT 4 #define RT_LWIP_ICMP #define RT_LWIP_DNS #define RT_LWIP_DHCP @@ -202,7 +209,7 @@ #define RT_LWIP_TCP_WND 8196 #define RT_LWIP_TCPTHREAD_PRIORITY 10 #define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_STACKSIZE 2048 #define RT_LWIP_ETHTHREAD_PRIORITY 12 #define RT_LWIP_ETHTHREAD_STACKSIZE 1024 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 @@ -213,12 +220,10 @@ #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 #define LWIP_NETIF_LOOPBACK 0 #define RT_LWIP_USING_PING -/* Modbus master and slave stack */ - - /* AT commands */ @@ -226,7 +231,14 @@ /* Utilities */ + #define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 /* RT-Thread online packages */ @@ -252,24 +264,51 @@ /* multimedia packages */ +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + /* tools packages */ /* system packages */ +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + /* peripheral libraries and drivers */ -/* miscellaneous packages */ +/* AI packages */ + +/* miscellaneous packages */ /* samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + #define SOC_VEXPRESS_A9 #define RT_USING_UART0 #define RT_USING_UART1 +#define BSP_DRV_CLCD +#define BSP_LCD_WIDTH 640 +#define BSP_LCD_HEIGHT 480 #define BSP_DRV_EMAC #endif diff --git a/bsp/qemu-vexpress-a9/rtconfig.py b/bsp/qemu-vexpress-a9/rtconfig.py index 49727b6d202b2f6aa78172cfa6c0fda7bcd6ca6a..2ce2fad659ca29ae0ffbbfb49d9bb08574e372ab 100644 --- a/bsp/qemu-vexpress-a9/rtconfig.py +++ b/bsp/qemu-vexpress-a9/rtconfig.py @@ -1,8 +1,8 @@ import os import uuid -def get_mac_address(): - mac=uuid.UUID(int = uuid.getnode()).hex[-12:] +def get_mac_address(): + mac=uuid.UUID(int = uuid.getnode()).hex[-12:] return "#define AUTOMAC".join([str(int(e/2) + 1) + ' 0x' + mac[e:e+2] + '\n' for e in range(5,11,2)]) header = ''' @@ -26,62 +26,45 @@ with open(automac_h_fn, 'w') as f: f.write(header + get_mac_address() + end) # toolchains options -ARCH='arm' -CPU='cortex-a' -CROSS_TOOL='gcc' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# only support GNU GCC compiler. +ARCH ='arm' +CPU ='cortex-a' +CROSS_TOOL = 'gcc' PLATFORM = 'gcc' -EXEC_PATH = '/usr/bin' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' +EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin' +BUILD = 'debug' if PLATFORM == 'gcc': # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' + SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - STRIP = PREFIX + 'strip' - - DEVICE = ' -march=armv7-a -marm -msoft-float' - CFLAGS = DEVICE + ' -Wall' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__ -I.' - LINK_SCRIPT = 'link.lds' - LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors'+\ - ' -T %s' % LINK_SCRIPT - - CPATH = '' - LPATH = '' - - # generate debug info in all cases - AFLAGS += ' -gdwarf-2' - CFLAGS += ' -g -gdwarf-2' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + CFPFLAGS = ' -msoft-float' + AFPFLAGS = ' -mfloat-abi=softfp -mfpu=neon' + DEVICE = ' -march=armv7-a -mtune=cortex-a7 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' + + CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall' + CFLAGS = DEVICE + CFPFLAGS + ' -Wall -std=gnu99' + AFLAGS = DEVICE + ' -c' + AFPFLAGS + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static' + CPATH = '' + LPATH = '' if BUILD == 'debug': - CFLAGS += ' -O0' + CFLAGS += ' -O0 -gdwarf-2' + CXXFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti' - - M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' - M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' - M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ - ' -shared -fPIC -nostartfiles -nostdlib -static-libgcc' - M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + CFLAGS += ' -Os' + CXXFLAGS += ' -Os' + CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti' - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ - SIZE + ' $TARGET \n' +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/qemu-vexpress-gemini/.config b/bsp/qemu-vexpress-gemini/.config index 8be74ae0c02e8c91868088cc3b760f4c3ac124a3..01ce42ff807225c31ebba8a1a9a4925340038b28 100644 --- a/bsp/qemu-vexpress-gemini/.config +++ b/bsp/qemu-vexpress-gemini/.config @@ -7,6 +7,9 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=6 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y @@ -15,6 +18,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set @@ -61,10 +65,15 @@ CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_ARCH_ARM=y +# CONFIG_RT_IOREMAP_LATE is not set CONFIG_ARCH_ARM_CORTEX_A=y CONFIG_ARCH_ARM_CORTEX_A9=y +# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set # # RT-Thread Components @@ -108,32 +117,43 @@ CONFIG_DFS_FD_MAX=4 # CONFIG_RT_USING_DFS_ELMFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set -# CONFIG_RT_USING_DFS_NFS is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set # # Using USB @@ -146,10 +166,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_PTHREADS=y +CONFIG_PTHREAD_NUM_MAX=8 CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set # # Network @@ -161,14 +184,14 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -192,16 +215,10 @@ CONFIG_RT_VBUS_RFS_DEV_NAME="rfs" # # Utilities # -CONFIG_RT_USING_LOGTRACE=y -CONFIG_LOG_TRACE_MAX_SESSION=16 -# CONFIG_LOG_TRACE_USING_LEVEL_NOTRACE is not set -# CONFIG_LOG_TRACE_USING_LEVEL_ERROR is not set -# CONFIG_LOG_TRACE_USING_LEVEL_WARNING is not set -CONFIG_LOG_TRACE_USING_LEVEL_INFO=y -# CONFIG_LOG_TRACE_USING_LEVEL_VERBOSE is not set -# CONFIG_LOG_TRACE_USING_LEVEL_DEBUG is not set -# CONFIG_LOG_TRACE_USING_MEMLOG is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -210,12 +227,20 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -233,10 +258,15 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set # # IoT Cloud @@ -245,6 +275,32 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -252,6 +308,8 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -265,6 +323,10 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -273,6 +335,19 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -284,18 +359,78 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -306,19 +441,73 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # -# sample package -# -# CONFIG_PKG_USING_SAMPLES is not set - -# -# example package: hello +# samples: kernel and components samples # +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set -CONFIG_SOC_VEXPRESS_GEMINI=y +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +CONFIG_SOC_VEXPRESS_A9=y # CONFIG_RT_USING_UART0 is not set CONFIG_RT_USING_UART1=y diff --git a/bsp/qemu-vexpress-gemini/Kconfig b/bsp/qemu-vexpress-gemini/Kconfig index e86e36974747c5e91c116810f6290c6b719477bf..425a81578ecbb4a75ca131b0bd41301ed1650c5f 100644 --- a/bsp/qemu-vexpress-gemini/Kconfig +++ b/bsp/qemu-vexpress-gemini/Kconfig @@ -18,9 +18,10 @@ config PKGS_DIR source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" -config SOC_VEXPRESS_GEMINI +config SOC_VEXPRESS_A9 bool select ARCH_ARM_CORTEX_A9 + select RT_USING_CACHE select RT_USING_COMPONENTS_INIT # select RT_USING_USER_MAIN default y diff --git a/bsp/qemu-vexpress-gemini/rtconfig.h b/bsp/qemu-vexpress-gemini/rtconfig.h index 0d7ead92ddca7afcdff365014c39129add9800e8..190aa3520d11b12a4ef634a0d5ebe2b50d7acdc0 100644 --- a/bsp/qemu-vexpress-gemini/rtconfig.h +++ b/bsp/qemu-vexpress-gemini/rtconfig.h @@ -8,28 +8,16 @@ #define RT_NAME_MAX 6 #define RT_ALIGN_SIZE 4 -/* RT_THREAD_PRIORITY_8 is not set */ #define RT_THREAD_PRIORITY_32 -/* RT_THREAD_PRIORITY_256 is not set */ #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 512 -/* RT_USING_TIMER_SOFT is not set */ #define RT_DEBUG #define RT_DEBUG_COLOR -/* RT_DEBUG_INIT_CONFIG is not set */ -/* RT_DEBUG_THREAD_CONFIG is not set */ -/* RT_DEBUG_SCHEDULER_CONFIG is not set */ -/* RT_DEBUG_IPC_CONFIG is not set */ -/* RT_DEBUG_TIMER_CONFIG is not set */ -/* RT_DEBUG_IRQ_CONFIG is not set */ -/* RT_DEBUG_MEM_CONFIG is not set */ -/* RT_DEBUG_SLAB_CONFIG is not set */ -/* RT_DEBUG_MEMHEAP_CONFIG is not set */ -/* RT_DEBUG_MODULE_CONFIG is not set */ /* Inter-Thread communication */ @@ -38,27 +26,22 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ #define RT_USING_MEMPOOL -/* RT_USING_MEMHEAP is not set */ -/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ -/* RT_USING_MEMTRACE is not set */ #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE -/* RT_USING_DEVICE_OPS is not set */ #define RT_USING_INTERRUPT_INFO #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -/* RT_USING_MODULE is not set */ +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define ARCH_ARM #define ARCH_ARM_CORTEX_A #define ARCH_ARM_CORTEX_A9 @@ -66,11 +49,9 @@ /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT -/* RT_USING_USER_MAIN is not set */ /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ @@ -80,14 +61,11 @@ #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION -/* FINSH_ECHO_DISABLE_DEFAULT is not set */ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT -/* FINSH_USING_MSH_ONLY is not set */ #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -97,14 +75,7 @@ #define DFS_FILESYSTEMS_MAX 2 #define DFS_FILESYSTEM_TYPES_MAX 2 #define DFS_FD_MAX 4 -/* RT_USING_DFS_MNTTABLE is not set */ -/* RT_USING_DFS_ELMFAT is not set */ #define RT_USING_DFS_DEVFS -/* RT_USING_DFS_ROMFS is not set */ -/* RT_USING_DFS_RAMFS is not set */ -/* RT_USING_DFS_UFFS is not set */ -/* RT_USING_DFS_JFFS2 is not set */ -/* RT_USING_DFS_NFS is not set */ /* Device Drivers */ @@ -112,58 +83,36 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_CPUTIME is not set */ -/* RT_USING_I2C is not set */ +#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* RT_USING_PWM is not set */ -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_RTC is not set */ -/* RT_USING_SDIO is not set */ -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_WIFI is not set */ -/* RT_USING_AUDIO is not set */ /* Using USB */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ #define RT_USING_LIBC #define RT_USING_PTHREADS +#define PTHREAD_NUM_MAX 8 #define RT_USING_POSIX -/* RT_USING_POSIX_MMAP is not set */ -/* RT_USING_POSIX_TERMIOS is not set */ -/* RT_USING_POSIX_AIO is not set */ /* Network */ /* Socket abstraction layer */ -/* RT_USING_SAL is not set */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* RT_USING_LWIP is not set */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ -/* RT_USING_MODBUS is not set */ /* AT commands */ -/* RT_USING_AT is not set */ /* VBUS(Virtual Software BUS) */ #define RT_USING_VBUS -/* RT_USING_VBUS_RFS is not set */ -/* RT_USING_VBUS_RSHELL is not set */ #define RT_VBUS_USING_TESTS #define _RT_VBUS_RING_BASE 0x6f800000 #define _RT_VBUS_RING_SZ 2097152 @@ -174,117 +123,53 @@ /* Utilities */ -#define LOG_TRACE_MAX_SESSION 16 -/* LOG_TRACE_USING_LEVEL_NOTRACE is not set */ -/* LOG_TRACE_USING_LEVEL_ERROR is not set */ -/* LOG_TRACE_USING_LEVEL_WARNING is not set */ -#define LOG_TRACE_USING_LEVEL_INFO -/* LOG_TRACE_USING_LEVEL_VERBOSE is not set */ -/* LOG_TRACE_USING_LEVEL_DEBUG is not set */ -/* LOG_TRACE_USING_MEMLOG is not set */ -/* RT_USING_RYM is not set */ /* RT-Thread online packages */ /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_JSMN is not set */ -/* PKG_USING_LJSON is not set */ -/* PKG_USING_EZXML is not set */ -/* PKG_USING_NANOPB is not set */ /* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ -/* PKG_USING_WLAN_WICED is not set */ -/* PKG_USING_COAP is not set */ -/* PKG_USING_NOPOLL is not set */ -/* PKG_USING_NETUTILS is not set */ -/* PKG_USING_AT_DEVICE is not set */ /* IoT Cloud */ -/* PKG_USING_ONENET is not set */ -/* PKG_USING_GAGENT_CLOUD is not set */ -/* PKG_USING_ALI_IOTKIT is not set */ -/* PKG_USING_AZURE is not set */ /* security packages */ -/* PKG_USING_MBEDTLS is not set */ -/* PKG_USING_libsodium is not set */ -/* PKG_USING_TINYCRYPT is not set */ /* language packages */ -/* PKG_USING_LUA is not set */ -/* PKG_USING_JERRYSCRIPT is not set */ -/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ -/* PKG_USING_OPENMV is not set */ -/* PKG_USING_MUPDF is not set */ /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYFLASH is not set */ -/* PKG_USING_EASYLOGGER is not set */ -/* PKG_USING_SYSTEMVIEW is not set */ /* system packages */ -/* PKG_USING_GUIENGINE is not set */ -/* PKG_USING_PERSIMMON is not set */ -/* PKG_USING_CAIRO is not set */ -/* PKG_USING_PIXMAN is not set */ -/* PKG_USING_LWEXT4 is not set */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_FAL is not set */ -/* PKG_USING_SQLITE is not set */ -/* PKG_USING_RTI is not set */ -/* PKG_USING_LITTLEVGL2RTT is not set */ /* peripheral libraries and drivers */ -/* PKG_USING_STM32F4_HAL is not set */ -/* PKG_USING_STM32F4_DRIVERS is not set */ -/* PKG_USING_REALTEK_AMEBA is not set */ -/* PKG_USING_SHT2X is not set */ -/* PKG_USING_AHT10 is not set */ /* miscellaneous packages */ -/* PKG_USING_LIBCSV is not set */ -/* PKG_USING_OPTPARSE is not set */ -/* PKG_USING_FASTLZ is not set */ -/* PKG_USING_MINILZO is not set */ -/* PKG_USING_QUICKLZ is not set */ -/* PKG_USING_MULTIBUTTON is not set */ -/* PKG_USING_CANFESTIVAL is not set */ -/* PKG_USING_ZLIB is not set */ -/* PKG_USING_DSTR is not set */ -/* sample package */ +/* samples: kernel and components samples */ + + +/* Privated Packages of RealThread */ -/* PKG_USING_SAMPLES is not set */ -/* example package: hello */ +/* Network Utilities */ -/* PKG_USING_HELLO is not set */ -#define SOC_VEXPRESS_GEMINI -/* RT_USING_UART0 is not set */ +#define SOC_VEXPRESS_A9 #define RT_USING_UART1 #endif diff --git a/bsp/qemu-virt64-aarch64/.config b/bsp/qemu-virt64-aarch64/.config new file mode 100644 index 0000000000000000000000000000000000000000..7038815cac33dacb899d1dea18a3080d6de05be4 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/.config @@ -0,0 +1,647 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_MEMTRACE=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +CONFIG_RT_USING_INTERRUPT_INFO=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0xffff000000000000 +CONFIG_PV_OFFSET=0x1000040000000 +CONFIG_ARCH_ARMV8=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=10 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=256 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=8 +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=256 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y +# CONFIG_RT_USING_MLIB is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_USING_POSIX_CLOCKTIME=y +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_RT_USING_ARDUINO is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_USB_STACK is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +CONFIG_SOC_VIRT64_AARCH64=y + +# +# AARCH64 qemu virt64 configs +# +CONFIG_BSP_SUPPORT_FPU=y +CONFIG_BSP_USING_UART=y +CONFIG_RT_USING_UART0=y +CONFIG_BSP_USING_GIC=y +CONFIG_BSP_USING_GIC390=y diff --git a/bsp/qemu-virt64-aarch64/Kconfig b/bsp/qemu-virt64-aarch64/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..07a0454272436dad5a4cbb4d1c1d704f225f2f5d --- /dev/null +++ b/bsp/qemu-virt64-aarch64/Kconfig @@ -0,0 +1,35 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_VIRT64_AARCH64 + bool + select ARCH_ARMV8 + select ARCH_CPU_64BIT + select ARCH_ARM_MMU + select RT_USING_CACHE + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_GIC + select BSP_USING_GIC + select BSP_USING_GIC390 + select ARCH_MM_MMU + default y + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/qemu-virt64-aarch64/README.md b/bsp/qemu-virt64-aarch64/README.md new file mode 100644 index 0000000000000000000000000000000000000000..4c384d17fc7f8a530b4fd9256b7e40bd2a8a5716 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/README.md @@ -0,0 +1,59 @@ +# QEMU/virt aarch64板级支持包说明 + +## 1. 简介 + +The virt board is a platform which does not correspond to any real hardware; it is designed for use in virtual machines. + +Supported guest CPU types: +cortex-a7 (32-bit) +cortex-a15 (32-bit; the default) +cortex-a53 (64-bit) +cortex-a57 (64-bit) +cortex-a72 (64-bit) +host (with KVM only) +max (same as host for KVM; best possible emulation with TCG) + +Guest code can rely on and hard-code the following addresses: +Flash memory starts at address 0x0000_0000 +RAM starts at 0x4000_0000 + +## 2. 编译说明 + +推荐使用[env工具][2]，可以在console下进入到`bsp/qemu-virt64-aarch64`目录中，运行以下命令： + + scons + +来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。 + +**注：** RT-Thread/ENV中携带的工具版本是： + + gcc version 5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496] + +如果在Linux下使用，请自行下载[GNU GCC工具链][3]。 + +## 3. 执行 + +当要执行编译好的RT-Thread时，在这个bsp目录下已经提供了运行脚本文件：qemu.bat/qemu.sh + +这个执行脚本默认把串口输出到stdio（即控制台）上，所以直接执行脚本后就可以输出结果了。 + +```text + \ | / +- RT - Thread Smart Operating System + / | \ 5.0.0 build Aug 18 2021 + 2006 - 2020 Copyright by rt-thread team +hello rt-thread +msh /> +``` + +## 4. 支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0 | +| SD/MMC | 不支持 | | +| CLCD | 不支持 | | +| Key | 不支持 | | +| Mouse | 不支持 | | +| EMAC | 不支持 | | + diff --git a/bsp/qemu-virt64-aarch64/SConscript b/bsp/qemu-virt64-aarch64/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/qemu-virt64-aarch64/SConstruct b/bsp/qemu-virt64-aarch64/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..658dcf291d4fb6e8e49f6d48bd394a6a8ef61df7 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/SConstruct @@ -0,0 +1,44 @@ +import os +import sys +import rtconfig +import re + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..') + + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +TRACE_CONFIG = "" + +content = "" +with open("rtconfig.h") as f: + for line in f.readlines(): + if line.find("RT_BACKTRACE_FUNCTION_NAME") != -1: + for token in line.split(" "): + if re.match(r'RT_BACKTRACE_FUNCTION_NAME$', token, flags=0): + TRACE_CONFIG = " " + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS + TRACE_CONFIG, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS + TRACE_CONFIG, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS + TRACE_CONFIG, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/raspberry-pi/raspi4-64/driver/SConscript b/bsp/qemu-virt64-aarch64/applications/SConscript similarity index 85% rename from bsp/raspberry-pi/raspi4-64/driver/SConscript rename to bsp/qemu-virt64-aarch64/applications/SConscript index 533df8ac31d12aaf4a835cde3a1554d8d65d955a..c583d3016e0f932c30df95aacb80ae6a049bb0f4 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/SConscript +++ b/bsp/qemu-virt64-aarch64/applications/SConscript @@ -2,7 +2,7 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd, str(Dir('#'))] +CPPPATH = [cwd] group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/qemu-virt64-aarch64/applications/main.c b/bsp/qemu-virt64-aarch64/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..6c6d5af268b2142ef656cf62be9c21298e1c1244 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/10/7 bernard the first version + */ + +#include + +int main(void) +{ + printf("hello rt-thread\n"); + + return 0; +} diff --git a/bsp/qemu-virt64-aarch64/applications/mnt.c b/bsp/qemu-virt64-aarch64/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..ed84f210d5b751d794e9b5c5b825cd6b46da6258 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/applications/mnt.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021/08/19 bernard the first version + */ + +#include + +#ifdef RT_USING_DFS +#include +#include + +int mnt_init(void) +{ + if (dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) != 0) + { + rt_kprintf("Dir / mount failed!\n"); + return -1; + } + + rt_kprintf("file system initialization done!\n"); + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif diff --git a/bsp/qemu-virt64-aarch64/drivers/Kconfig b/bsp/qemu-virt64-aarch64/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5e3d969ab7ad9a0b2f06d5a14d92cbe4f8d77b76 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/drivers/Kconfig @@ -0,0 +1,25 @@ + +menu "AARCH64 qemu virt64 configs" + menuconfig BSP_SUPPORT_FPU + bool "Using Float" + default y + + menuconfig BSP_USING_UART + bool "Using UART" + select RT_USING_SERIAL + default y + + if BSP_USING_UART + config RT_USING_UART0 + bool "Enabel UART 0" + default y + endif + + config BSP_USING_GIC + bool + default y + + config BSP_USING_GIC390 + bool + default y +endmenu diff --git a/libcpu/aarch64/common/gic/SConscript b/bsp/qemu-virt64-aarch64/drivers/SConscript similarity index 32% rename from libcpu/aarch64/common/gic/SConscript rename to bsp/qemu-virt64-aarch64/drivers/SConscript index b114ba7678faa780a82a80d4f1ee7c6b64c1992d..4de25c676a04d80d9289653816161eb73b3c36e8 100644 --- a/libcpu/aarch64/common/gic/SConscript +++ b/bsp/qemu-virt64-aarch64/drivers/SConscript @@ -3,22 +3,12 @@ from building import * cwd = GetCurrentDir() -CPPPATH = [cwd] - -gic400_group = Split(''' -gic_pl400.c -''') - -gic500_group = Split(''' -gic_pl500.c +src = Split(''' +board.c +drv_uart.c ''') +CPPPATH = [cwd] -src = () -if GetDepend('BSP_USING_GIC400'): - src = gic400_group -if GetDepend('BSP_USING_GIC500'): - src = gic500_group - -group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/qemu-virt64-aarch64/drivers/board.c b/bsp/qemu-virt64-aarch64/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..e7670c1a8d1b2fafc6e37672e28bbe95b9ac957f --- /dev/null +++ b/bsp/qemu-virt64-aarch64/drivers/board.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-11-20 Bernard the first version + * 2018-11-22 Jesven add rt_hw_spin_lock + * add rt_hw_spin_unlock + * add smp ipi init + */ + +#include +#include +#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif +#include "board.h" + +#ifdef RT_USING_USERSPACE +struct mem_desc platform_mem_desc[] = { + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0fffffff, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM} +}; +#else +struct mem_desc platform_mem_desc[] = { + {0x10000000, 0x50000000, 0x10000000, DEVICE_MEM}, + {0x40000000, 0x50000000, 0x40000000, NORMAL_MEM} +}; +#endif + +const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); + +#define SYS_CTRL __REG32(REALVIEW_SCTL_BASE) + +extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); + +void idle_wfi(void) +{ + asm volatile ("wfi"); +} + +/** + * This function will initialize board + */ + +rt_mmu_info mmu_info; + +extern size_t MMUTable[]; + +#ifdef RT_USING_USERSPACE +rt_region_t init_page_region = { + PAGE_START, + PAGE_END, +}; +#endif + +void rt_hw_board_init(void) +{ +#ifdef RT_USING_USERSPACE + rt_page_init(init_page_region); + + rt_hw_mmu_setup(platform_mem_desc, platform_mem_desc_size); + + rt_hw_mmu_map_init(&mmu_info, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET); + + arch_kuser_init(&mmu_info, (void*)0xffffffffffff0000); +#else + rt_hw_mmu_map_init(&mmu_info, (void*)0x80000000, 0x10000000, MMUTable, 0); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0x80000000, 0x10000000); +#endif + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize system heap */ + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); + + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + rt_thread_idle_sethook(idle_wfi); + +#ifdef RT_USING_SMP + /* install IPI handle */ + rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler); +#endif +} diff --git a/bsp/qemu-virt64-aarch64/drivers/board.h b/bsp/qemu-virt64-aarch64/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..829ea27bd8ab26d496c6349f5c4091b4ac93dea5 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/drivers/board.h @@ -0,0 +1,70 @@ +/* + * File : board.h + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard the first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "mmu.h" +#include "ioremap.h" + +extern unsigned char __bss_start; +extern unsigned char __bss_end; + +#define HEAP_BEGIN ((void*)&__bss_end) + +#ifdef RT_USING_USERSPACE +#define HEAP_END ((size_t)KERNEL_VADDR_START + 16 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END ((size_t)KERNEL_VADDR_START + 128 * 1024 * 1024) +#else +#define HEAP_END ((size_t)0x40000000 + 64 * 1024 * 1024) +#endif + +#define __REG32(x) (*((volatile unsigned int *)(x))) +#define __REG16(x) (*((volatile unsigned short *)(x))) + +/* UART PL011 */ +#define PL011_UARTDR (0x000) +#define PL011_UARTFR (0x018) +#define PL011_UARTFR_TXFF_BIT (5) +#define PL011_UART0_BASE (0x09000000) +#define PL011_UART0_SIZE (0x00001000) +#define PL011_UART0_IRQNUM (33) + +/* GIC PL390 DIST and CPU */ +#define GIC_PL390_DISTRIBUTOR_PPTR (0x08000000) +#define GIC_PL390_CONTROLLER_PPTR (0x08010000) + +#define MAX_HANDLERS (96) +#define GIC_IRQ_START (0) +/* number of interrupts on board */ +#define ARM_GIC_NR_IRQS (96) +/* only one GIC available */ +#define ARM_GIC_MAX_NR (1) + +/* the basic constants and interfaces needed by gic */ +rt_inline rt_uint64_t platform_get_gic_dist_base(void) +{ + return GIC_PL390_DISTRIBUTOR_PPTR; +} + +rt_inline rt_uint64_t platform_get_gic_cpu_base(void) +{ + return GIC_PL390_CONTROLLER_PPTR; +} + +void rt_hw_board_init(void); + +extern rt_mmu_info mmu_info; + +#endif diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c b/bsp/qemu-virt64-aarch64/drivers/drv_uart.c similarity index 50% rename from bsp/raspberry-pi/raspi4-64/driver/drv_uart.c rename to bsp/qemu-virt64-aarch64/drivers/drv_uart.c index 6a70cdfb3a87dbaf1561cd7b1568d0b859d3b3bb..804d3afc998fb0f1a169d52044e3fbe5f93d014d 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c +++ b/bsp/qemu-virt64-aarch64/drivers/drv_uart.c @@ -1,55 +1,48 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * serial.c UART driver + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-04-16 bigmagic first version + * Date Author Notes + * 2013-03-30 Bernard the first verion */ #include -#include #include #include "board.h" -#include "drv_uart.h" -#include "drv_gpio.h" +#include "mmu.h" struct hw_uart_device { - rt_ubase_t hw_base; - rt_uint32_t irqno; + rt_size_t hw_base; + rt_size_t irqno; }; -static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +#define UART_DR(base) __REG32(base + 0x00) +#define UART_FR(base) __REG32(base + 0x18) +#define UART_CR(base) __REG32(base + 0x30) +#define UART_IMSC(base) __REG32(base + 0x38) +#define UART_ICR(base) __REG32(base + 0x44) + +#define UARTFR_RXFE 0x10 +#define UARTFR_TXFF 0x20 +#define UARTIMSC_RXIM 0x10 +#define UARTIMSC_TXIM 0x20 +#define UARTICR_RXIC 0x10 +#define UARTICR_TXIC 0x20 + +static void rt_hw_uart_isr(int irqno, void *param) { - struct hw_uart_device *uart; - uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16; - uint32_t ibrd = bauddiv / 1000; + struct rt_serial_device *serial = (struct rt_serial_device *)param; - RT_ASSERT(serial != RT_NULL); - uart = (struct hw_uart_device *)serial->parent.user_data; - if(uart->hw_base == PL011_BASE) - { - uint32_t gpfsel = 0; - - gpfsel &= ~((uint32_t)(0x07 << (4 * 3))); - gpfsel |= (uint32_t)(ALT0 << (4 * 3)); - GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel; - - gpfsel &= ~((uint32_t)(0x07 << (5 * 3))); - gpfsel |= (uint32_t)(ALT0 << (5 * 3)); - GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel; - - PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/ - PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/ - PL011_REG_IBRD(uart->hw_base) = ibrd; - PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000); - PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/ - PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/ - } + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ return RT_EOK; } @@ -64,13 +57,12 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM); - rt_hw_interrupt_mask(uart->irqno); + UART_IMSC(uart->hw_base) &= ~UARTIMSC_RXIM; break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM; + UART_IMSC(uart->hw_base) |= UARTIMSC_RXIM; rt_hw_interrupt_umask(uart->irqno); break; } @@ -85,23 +77,24 @@ static int uart_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct hw_uart_device *)serial->parent.user_data; - while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF)); - PL011_REG_DR(uart->hw_base) = (uint8_t)c; + while (UART_FR(uart->hw_base) & UARTFR_TXFF); + UART_DR(uart->hw_base) = c; return 1; } static int uart_getc(struct rt_serial_device *serial) { - int ch = -1; + int ch; struct hw_uart_device *uart; RT_ASSERT(serial != RT_NULL); uart = (struct hw_uart_device *)serial->parent.user_data; - if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0) + ch = -1; + if (!(UART_FR(uart->hw_base) & UARTFR_RXFE)) { - ch = PL011_REG_DR(uart->hw_base) & 0xff; + ch = UART_DR(uart->hw_base) & 0xff; } return ch; @@ -115,38 +108,37 @@ static const struct rt_uart_ops _uart_ops = uart_getc, }; -static void rt_hw_uart_isr(int irqno, void *param) -{ - struct rt_serial_device *serial = (struct rt_serial_device*)param; - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE; -} - - +#ifdef RT_USING_UART0 /* UART device driver structure */ static struct hw_uart_device _uart0_device = { - PL011_BASE, - IRQ_PL011, + PL011_UART0_BASE, + PL011_UART0_IRQNUM, }; - static struct rt_serial_device _serial0; +#endif int rt_hw_uart_init(void) { struct hw_uart_device *uart; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef RT_USING_UART0 + _uart0_device.hw_base = (rt_size_t)rt_ioremap((void*)_uart0_device.hw_base, PL011_UART0_SIZE); uart = &_uart0_device; _serial0.ops = &_uart_ops; _serial0.config = config; /* register UART1 device */ - rt_hw_serial_register(&_serial0, "uart", + rt_hw_serial_register(&_serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); - rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart"); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0"); + /* enable Rx and Tx of UART */ + UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9); +#endif return 0; } +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/qemu-virt64-aarch64/drivers/drv_uart.h b/bsp/qemu-virt64-aarch64/drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..1cd7a583ff44a54e2e5b72d697c52d0aaef9e83e --- /dev/null +++ b/bsp/qemu-virt64-aarch64/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/qemu-virt64-aarch64/link.lds b/bsp/qemu-virt64-aarch64/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..0f02657b5873ffd2e0bb16aa93c59455d5acec8d --- /dev/null +++ b/bsp/qemu-virt64-aarch64/link.lds @@ -0,0 +1,110 @@ +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +SECTIONS +{ + /*. = 0x60080000; */ + /*. = 0x40000000; */ + . = 0xffff000000080000; + + __text_start = .; + .text : + { + KEEP(*(.text.entrypoint)) + KEEP(*(.vectors)) + *(.text) + *(.text.*) + + /* section information for utest */ + . = ALIGN(8); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for modules */ + . = ALIGN(8); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } =0 + __text_end = .; + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(8); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(8); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(8); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(8); + } + . = ALIGN(8); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + __data_size = SIZEOF(.data); + __bss_size = SIZEOF(.bss); + + _end = .; +} diff --git a/bsp/qemu-virt64-aarch64/qemu.bat b/bsp/qemu-virt64-aarch64/qemu.bat new file mode 100644 index 0000000000000000000000000000000000000000..507893a97cac84a82a94704c773b46f98690cf0d --- /dev/null +++ b/bsp/qemu-virt64-aarch64/qemu.bat @@ -0,0 +1 @@ +qemu-system-aarch64 -M virt -cpu cortex-a53 -smp 1 -kernel rtthread.bin -nographic diff --git a/bsp/qemu-virt64-aarch64/qemu.sh b/bsp/qemu-virt64-aarch64/qemu.sh new file mode 100755 index 0000000000000000000000000000000000000000..c04526736252d1cf6859a5e57b48990423fcd4c0 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/qemu.sh @@ -0,0 +1 @@ +qemu-system-aarch64 -M virt -cpu cortex-a53 -smp 1 -kernel rtthread.bin -nographic -monitor pty diff --git a/bsp/qemu-virt64-aarch64/rtconfig.h b/bsp/qemu-virt64-aarch64/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..d220c74b40685a9f43b0ed8f2b5323309209b80b --- /dev/null +++ b/bsp/qemu-virt64-aarch64/rtconfig.h @@ -0,0 +1,218 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_USING_SMART +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 8192 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 8192 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_MEMTRACE +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_INTERRUPT_INFO +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50000 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_MM_MMU +#define ARCH_ARM +#define ARCH_ARM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0xffff000000000000 +#define PV_OFFSET 0x1000040000000 +#define ARCH_ARMV8 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 10 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 256 +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 8 +#define DFS_FD_MAX 32 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 256 +#define RT_USING_TTY +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_MUSL +#define RT_USING_POSIX +#define RT_USING_POSIX_CLOCKTIME + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_VIRT64_AARCH64 + +/* AARCH64 qemu virt64 configs */ + +#define BSP_SUPPORT_FPU +#define BSP_USING_UART +#define RT_USING_UART0 +#define BSP_USING_GIC +#define BSP_USING_GIC390 + +#endif diff --git a/bsp/qemu-virt64-aarch64/rtconfig.py b/bsp/qemu-virt64-aarch64/rtconfig.py new file mode 100755 index 0000000000000000000000000000000000000000..db9ff4c993d77b6ebd8ff910f0b0a4f0764c6863 --- /dev/null +++ b/bsp/qemu-virt64-aarch64/rtconfig.py @@ -0,0 +1,45 @@ +import os + +# toolchains options +ARCH ='aarch64' +CPU ='cortex-a' +CROSS_TOOL = 'gcc' +PLATFORM = 'gcc' +EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin' +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-linux-musleabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + CFPFLAGS = ' ' + AFPFLAGS = ' ' + DEVICE = ' -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' + + CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall' + CFLAGS = DEVICE + CFPFLAGS + ' -Wall -std=gnu99' + AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + CXXFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + CXXFLAGS += ' -Os' + CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti' + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/qemu-virt64-riscv/.config b/bsp/qemu-virt64-riscv/.config new file mode 100644 index 0000000000000000000000000000000000000000..ce753d63fba36c8967da5977c1ec0f747145e0d8 --- /dev/null +++ b/bsp/qemu-virt64-riscv/.config @@ -0,0 +1,645 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=20 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +# CONFIG_RT_USING_OVERFLOW_CHECK is not set +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=16384 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=16384 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMTRACE=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x50000 +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0x150000000 +CONFIG_PV_OFFSET=0 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV64=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=16384 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y +# CONFIG_RT_USING_MLIB is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_USING_POSIX_CLOCKTIME=y +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_RT_USING_ARDUINO is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_USB_STACK is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +CONFIG_BOARD_virt=y +CONFIG_ENABLE_FPU=y +# CONFIG_RT_USING_USERSPACE_32BIT_LIMIT is not set + +# +# General Purpose UARTs +# +# CONFIG_BSP_USING_UART1 is not set +CONFIG___STACKSIZE__=16384 diff --git a/bsp/qemu-virt64-riscv/.gitignore b/bsp/qemu-virt64-riscv/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..341f703a73fbbdc8bfac9d951714376688ade55a --- /dev/null +++ b/bsp/qemu-virt64-riscv/.gitignore @@ -0,0 +1,3 @@ +mnt.c +romfs_data.c +opensbi diff --git a/bsp/qemu-virt64-riscv/Kconfig b/bsp/qemu-virt64-riscv/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..514054133530813272c73e6d0a78a52b2d6fb543 --- /dev/null +++ b/bsp/qemu-virt64-riscv/Kconfig @@ -0,0 +1,46 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config BOARD_virt + bool + select ARCH_RISCV64 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_CACHE + select ARCH_MM_MMU + default y + +config RT_USING_USERSPACE + bool + default y + +config ENABLE_FPU + bool "Enable FPU" + default y + +config RT_USING_USERSPACE_32BIT_LIMIT + bool "Enable userspace 32bit limit" + default n + +source "driver/Kconfig" + +config __STACKSIZE__ + int "stack size for interrupt" + default 4096 diff --git a/bsp/qemu-virt64-riscv/SConscript b/bsp/qemu-virt64-riscv/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/qemu-virt64-riscv/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/qemu-virt64-riscv/SConstruct b/bsp/qemu-virt64-riscv/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..422e592ccd8d50cd7c32ef5e6141ccf992037f81 --- /dev/null +++ b/bsp/qemu-virt64-riscv/SConstruct @@ -0,0 +1,38 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') +rtconfig.CPU='virt64' +rtconfig.ARCH='risc-v' + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +stack_size = 4096 + +stack_lds = open('link_stacksize.lds', 'w') +if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__') +stack_lds.write('__STACKSIZE__ = %d;' % stack_size) +stack_lds.close() + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/qemu-virt64-riscv/applications/SConscript b/bsp/qemu-virt64-riscv/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..743ad207ab0cf9ab677d0e7d53f7bd247f66867e --- /dev/null +++ b/bsp/qemu-virt64-riscv/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/finsh/finsh_parser.h b/bsp/qemu-virt64-riscv/applications/main.c similarity index 39% rename from components/finsh/finsh_parser.h rename to bsp/qemu-virt64-riscv/applications/main.c index 8e149a7e00e8de07c36ff27aad3c4d53a25594c6..288d4f08bae009ef1161fae8b2fb9a4240083f99 100644 --- a/components/finsh/finsh_parser.h +++ b/bsp/qemu-virt64-riscv/applications/main.c @@ -5,14 +5,18 @@ * * Change Logs: * Date Author Notes - * 2010-03-22 Bernard first version */ -#ifndef __FINSH_PARSER_H__ -#define __FINSH_PARSER_H__ -#include +#include +#include +#include +#include -int finsh_parser_init(struct finsh_parser* self); -void finsh_parser_run(struct finsh_parser* self, const uint8_t* string); +int main(void) +{ + void rt_hw_uart_start_rx_thread(); + rt_hw_uart_start_rx_thread(); + printf("Hello RISC-V\n"); -#endif + return 0; +} diff --git a/bsp/qemu-virt64-riscv/driver/Kconfig b/bsp/qemu-virt64-riscv/driver/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5744c89702d7f4444a41c20860f929c9372a4a74 --- /dev/null +++ b/bsp/qemu-virt64-riscv/driver/Kconfig @@ -0,0 +1,18 @@ + + +menu "General Purpose UARTs" + +menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_TXD_PIN + int "uart1 TXD pin number" + default 20 + config BSP_UART1_RXD_PIN + int "uart1 RXD pin number" + default 21 + endif + +endmenu + diff --git a/bsp/qemu-virt64-riscv/driver/SConscript b/bsp/qemu-virt64-riscv/driver/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..faea9c1bd9bd1920667d46d5b0b9c1b7b68a0726 --- /dev/null +++ b/bsp/qemu-virt64-riscv/driver/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +objs = [group] + +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/qemu-virt64-riscv/driver/asm/sbiasm.h b/bsp/qemu-virt64-riscv/driver/asm/sbiasm.h new file mode 100644 index 0000000000000000000000000000000000000000..4639fba68cface55c39c15143440c4312dae8f27 --- /dev/null +++ b/bsp/qemu-virt64-riscv/driver/asm/sbiasm.h @@ -0,0 +1,10 @@ +#ifndef _SBI_ASM_H +#define _SBI_ASM_H + +.macro SBI_CALL which + li a7, \which + ecall + nop +.endm + +#endif /* _SBI_ASM_H */ diff --git a/bsp/qemu-virt64-riscv/driver/asm/sbidef.h b/bsp/qemu-virt64-riscv/driver/asm/sbidef.h new file mode 100644 index 0000000000000000000000000000000000000000..5bcf58ade7c3eeba38e86013137392a91223f63f --- /dev/null +++ b/bsp/qemu-virt64-riscv/driver/asm/sbidef.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ +#ifndef _ASM_SBI_DEF_H +#define _ASM_SBI_DEF_H + +#define SBI_SET_TIMER 0 +#define SBI_CONSOLE_PUTCHAR 1 +#define SBI_CONSOLE_GETCHAR 2 +#define SBI_CLEAR_IPI 3 +#define SBI_SEND_IPI 4 +#define SBI_REMOTE_FENCE_I 5 +#define SBI_REMOTE_SFENCE_VMA 6 +#define SBI_REMOTE_SFENCE_VMA_ASID 7 +#define SBI_SHUTDOWN 8 + +#define SBI_CONSOLE_PUTSTR 9 + +#define SBI_SD_WRITE 10 +#define SBI_SD_READ 11 +#define SBI_NET_WRITE 12 +#define SBI_NET_READ 13 + +#endif /* _ASM_SBI_DEF_H */ diff --git a/bsp/qemu-virt64-riscv/driver/board.c b/bsp/qemu-virt64-riscv/driver/board.c new file mode 100644 index 0000000000000000000000000000000000000000..0756de9c8877d29e28598bfdabd08718c79d55f9 --- /dev/null +++ b/bsp/qemu-virt64-riscv/driver/board.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#include +#include +#include + +#include "board.h" +#include "tick.h" + +#include "drv_uart.h" +#include "encoding.h" +#include "stack.h" +#include "sbi.h" +#include "riscv.h" +#include "plic.h" +#include "stack.h" + +#ifdef RT_USING_USERSPACE + #include "riscv_mmu.h" + #include "mmu.h" + #include "page.h" + #include "lwp_arch.h" + + rt_region_t init_page_region = + { + (rt_size_t)RT_HW_PAGE_START, + (rt_size_t)RT_HW_PAGE_END + }; + + volatile rt_size_t MMUTable[__SIZE(VPN2_BIT)] __attribute__((aligned(4 * 1024))); + rt_mmu_info mmu_info; + +#endif + +void init_bss(void) +{ + unsigned int *dst; + + dst = &__bss_start; + while (dst < &__bss_end) + { + *dst++ = 0; + } +} + +void primary_cpu_entry(void) +{ + extern void entry(void); + + /* disable global interrupt */ + init_bss(); + rt_hw_interrupt_disable(); + entry(); +} + +void rt_hw_interrupt_init() +{ + /* Enable machine external interrupts. */ + set_csr(sie, SIP_SEIP); +} + +void rt_hw_board_init(void) +{ + /* initalize interrupt */ + rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_uart_init(); + + rt_hw_tick_init(); + + #ifdef RT_USING_HEAP + rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END); + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + #endif + + #ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device("uart"); + #endif /* RT_USING_CONSOLE */ + + #ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); + #endif + + #ifdef RT_USING_USERSPACE + rt_page_init(init_page_region); + rt_hw_mmu_map_init(&mmu_info,(void *)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, (rt_size_t *)MMUTable, 0); + rt_hw_mmu_kernel_map_init(&mmu_info, 0x00000000UL, USER_VADDR_START - 1); + switch_mmu((void *)MMUTable); + #endif + + plic_init(); +} + +void rt_hw_cpu_reset(void) +{ + sbi_shutdown(); + + while(1); +} +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); + +void dump_regs(struct rt_hw_stack_frame *regs) +{ + rt_kprintf("--------------Dump Registers-----------------\n"); + + rt_kprintf("Function Registers:\n"); + rt_kprintf("\tra(x1) = 0x%p\tuser_sp = 0x%p\n",regs -> ra,regs -> user_sp_exc_stack); + rt_kprintf("\tgp(x3) = 0x%p\ttp(x4) = 0x%p\n",regs -> gp,regs -> tp); + rt_kprintf("Temporary Registers:\n"); + rt_kprintf("\tt0(x5) = 0x%p\tt1(x6) = 0x%p\n",regs -> t0,regs -> t1); + rt_kprintf("\tt2(x7) = 0x%p\n",regs -> t2); + rt_kprintf("\tt3(x28) = 0x%p\tt4(x29) = 0x%p\n",regs -> t3,regs -> t4); + rt_kprintf("\tt5(x30) = 0x%p\tt6(x31) = 0x%p\n",regs -> t5,regs -> t6); + rt_kprintf("Saved Registers:\n"); + rt_kprintf("\ts0/fp(x8) = 0x%p\ts1(x9) = 0x%p\n",regs -> s0_fp,regs -> s1); + rt_kprintf("\ts2(x18) = 0x%p\ts3(x19) = 0x%p\n",regs -> s2,regs -> s3); + rt_kprintf("\ts4(x20) = 0x%p\ts5(x21) = 0x%p\n",regs -> s4,regs -> s5); + rt_kprintf("\ts6(x22) = 0x%p\ts7(x23) = 0x%p\n",regs -> s6,regs -> s7); + rt_kprintf("\ts8(x24) = 0x%p\ts9(x25) = 0x%p\n",regs -> s8,regs -> s9); + rt_kprintf("\ts10(x26) = 0x%p\ts11(x27) = 0x%p\n",regs -> s10,regs -> s11); + rt_kprintf("Function Arguments Registers:\n"); + rt_kprintf("\ta0(x10) = 0x%p\ta1(x11) = 0x%p\n",regs -> a0,regs -> a1); + rt_kprintf("\ta2(x12) = 0x%p\ta3(x13) = 0x%p\n",regs -> a2,regs -> a3); + rt_kprintf("\ta4(x14) = 0x%p\ta5(x15) = 0x%p\n",regs -> a4,regs -> a5); + rt_kprintf("\ta6(x16) = 0x%p\ta7(x17) = 0x%p\n",regs -> a6,regs -> a7); + rt_kprintf("sstatus = 0x%p\n",regs -> sstatus); + rt_kprintf("\t%s\n",(regs -> sstatus & SSTATUS_SIE) ? "Supervisor Interrupt Enabled" : "Supervisor Interrupt Disabled"); + rt_kprintf("\t%s\n",(regs -> sstatus & SSTATUS_SPIE) ? "Last Time Supervisor Interrupt Enabled" : "Last Time Supervisor Interrupt Disabled"); + rt_kprintf("\t%s\n",(regs -> sstatus & SSTATUS_SPP) ? "Last Privilege is Supervisor Mode" : "Last Privilege is User Mode"); + rt_kprintf("\t%s\n",(regs -> sstatus & SSTATUS_PUM) ? "Permit to Access User Page" : "Not Permit to Access User Page"); + rt_kprintf("\t%s\n",(regs -> sstatus & (1 << 19)) ? "Permit to Read Executable-only Page" : "Not Permit to Read Executable-only Page"); + rt_size_t satp_v = read_csr(satp); + rt_kprintf("satp = 0x%p\n",satp_v); + rt_kprintf("\tCurrent Page Table(Physical) = 0x%p\n",__MASKVALUE(satp_v,__MASK(44)) << PAGE_OFFSET_BIT); + rt_kprintf("\tCurrent ASID = 0x%p\n",__MASKVALUE(satp_v >> 44,__MASK(16)) << PAGE_OFFSET_BIT); + const char *mode_str = "Unknown Address Translation/Protection Mode"; + + switch(__MASKVALUE(satp_v >> 60,__MASK(4))) + { + case 0: + mode_str = "No Address Translation/Protection Mode"; + break; + + case 8: + mode_str = "Page-based 39-bit Virtual Addressing Mode"; + break; + + case 9: + mode_str = "Page-based 48-bit Virtual Addressing Mode"; + break; + } + + rt_kprintf("\tMode = %s\n",mode_str); + rt_kprintf("-----------------Dump OK---------------------\n"); +} + +static const char *Exception_Name[] = + { + "Instruction Address Misaligned", + "Instruction Access Fault", + "Illegal Instruction", + "Breakpoint", + "Load Address Misaligned", + "Load Access Fault", + "Store/AMO Address Misaligned", + "Store/AMO Access Fault", + "Environment call from U-mode", + "Environment call from S-mode", + "Reserved-10", + "Reserved-11", + "Instruction Page Fault", + "Load Page Fault", + "Reserved-14", + "Store/AMO Page Fault" + }; + +static const char *Interrupt_Name[] = + { + "User Software Interrupt", + "Supervisor Software Interrupt", + "Reversed-2", + "Reversed-3", + "User Timer Interrupt", + "Supervisor Timer Interrupt", + "Reversed-6", + "Reversed-7", + "User External Interrupt", + "Supervisor External Interrupt", + "Reserved-10", + "Reserved-11", + }; + +void handle_trap(rt_size_t scause,rt_size_t stval,rt_size_t sepc,struct rt_hw_stack_frame *sp) +{ + // rt_kprintf("."); + if(scause == (uint64_t)(0x8000000000000005)) + { + rt_interrupt_enter(); + tick_isr(); + rt_interrupt_leave(); + } + /*else if(scause == (uint64_t)(0x8000000000000009)) + { + rt_kprintf("a\n"); + while(1); + extern struct rt_serial_device serial1; + rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_RX_IND); + }*/ + else + { + rt_size_t id = __MASKVALUE(scause,__MASK(63UL)); + const char *msg; + + if(scause >> 63) + { + if(id < sizeof(Interrupt_Name) / sizeof(const char *)) + { + msg = Interrupt_Name[id]; + } + else + { + msg = "Unknown Interrupt"; + } + + rt_kprintf("Unhandled Interrupt %ld:%s\n",id,msg); + } + else + { + #ifdef RT_USING_USERSPACE + if(id == 15) + { + arch_expand_user_stack((void *)stval); + return; + } + #endif + + if(id < sizeof(Exception_Name) / sizeof(const char *)) + { + msg = Exception_Name[id]; + } + else + { + msg = "Unknown Exception"; + } + + rt_kprintf("Unhandled Exception %ld:%s\n",id,msg); + } + + rt_kprintf("scause:0x%p,stval:0x%p,sepc:0x%p\n",scause,stval,sepc); + dump_regs(sp); + while(1); + } +} diff --git a/bsp/qemu-virt64-riscv/driver/board.h b/bsp/qemu-virt64-riscv/driver/board.h new file mode 100644 index 0000000000000000000000000000000000000000..3193346508103032d2e570acc25a64f1582adedf --- /dev/null +++ b/bsp/qemu-virt64-riscv/driver/board.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ + +#include + +extern unsigned int __bss_start; +extern unsigned int __bss_end; + +#define RT_HW_HEAP_BEGIN ((void *)&__bss_end) +#define RT_HW_HEAP_END ((void *)(((rt_size_t)RT_HW_HEAP_BEGIN) + 100 * 1024 * 1024)) +#define RT_HW_PAGE_START RT_HW_HEAP_END +#define RT_HW_PAGE_END ((void *)(((rt_size_t)RT_HW_PAGE_START) + 100 * 1024 * 1024)) + +void rt_hw_board_init(void); +void rt_init_user_mem(struct rt_thread *thread, const char *name, unsigned long *entry); + +#endif diff --git a/bsp/qemu-virt64-riscv/driver/drv_uart.c b/bsp/qemu-virt64-riscv/driver/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..1d050e8cae99dcb26f85382bf7957baaa87ee3d6 --- /dev/null +++ b/bsp/qemu-virt64-riscv/driver/drv_uart.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#include +#include "sbi.h" + +#define UART_DEFAULT_BAUDRATE 115200 + +struct device_uart +{ + rt_ubase_t hw_base; + rt_uint32_t irqno; +}; + +static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int drv_uart_putc(struct rt_serial_device *serial, char c); +static int drv_uart_getc(struct rt_serial_device *serial); + +const struct rt_uart_ops _uart_ops = +{ + rt_uart_configure, + uart_control, + drv_uart_putc, + drv_uart_getc, + //TODO: add DMA support + RT_NULL +}; + +void uart_init(void) +{ + return ; +} + +struct rt_serial_device serial1; +struct device_uart uart1; + +/* + * UART interface + */ +static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct device_uart *uart; + + RT_ASSERT(serial != RT_NULL); + serial->config = *cfg; + + return (RT_EOK); +} + +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ + +#define UART_RBR(hw) HWREG32(hw + 0x00) +#define UART_IER(hw) HWREG32(hw + 0x04) +#define UART_LSR(hw) HWREG32(hw + 0x14) + +static volatile uint64_t uart_hwbase = 0x10000000; + +void uart_putc(char c) +{ + while ((UART_LSR(uart_hwbase) & UART_LSR_THRE) == 0); + + UART_RBR(uart_hwbase) = c; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct device_uart *uart; + + uart = serial->parent.user_data; + rt_uint32_t channel = 1; + + RT_ASSERT(uart != RT_NULL); + RT_ASSERT(channel != 3); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* Disable the UART Interrupt */ + //rt_hw_interrupt_mask(uart->irqno); + //uart[channel]->IER &= ~0x1; + //UART_IER(uart_hwbase) &= ~0x1; + break; + + case RT_DEVICE_CTRL_SET_INT: + /* install interrupt */ + // rt_hw_interrupt_install(uart->irqno, uart_irq_handler, + // serial, serial->parent.parent.name); + // rt_hw_interrupt_umask(uart->irqno); + //uart[channel]->IER |= 0x1; + UART_IER(uart_hwbase) |= 0x1; + break; + } + + return (RT_EOK); +} + +static int drv_uart_putc(struct rt_serial_device *serial, char c) +{ + sbi_console_putchar(c); + + return (1); +} + +static int drv_uart_getc(struct rt_serial_device *serial) +{ + return sbi_console_getchar(); +} + +#if 0 +void drv_uart_puts(char *str) +{ + sbi_console_putstr(str); +} + +char rt_hw_console_getchar(void) +{ + return SBI_CALL_0(SBI_CONSOLE_GETCHAR); +} +#endif + +static void uart_rx(void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + while(1) + { + rt_hw_serial_isr((struct rt_serial_device *)serial,RT_SERIAL_EVENT_RX_IND); + rt_thread_mdelay(10); + } +} + +void rt_hw_uart_start_rx_thread() +{ + rt_thread_t th; + RT_ASSERT((th = rt_thread_create("uartrx",uart_rx,(void *)&serial1,8192,8,20)) != RT_NULL); + RT_ASSERT(rt_thread_startup(th) == RT_EOK); +} + +/* + * UART Initiation + */ +int rt_hw_uart_init(void) +{ + struct rt_serial_device *serial; + struct device_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + { + serial = &serial1; + uart = &uart1; + + serial->ops = &_uart_ops; + serial->config = config; + serial->config.baud_rate = UART_DEFAULT_BAUDRATE; + + uart->hw_base = 0x10000000; + uart->irqno = 0xa; + + rt_hw_serial_register(serial, + "uart", + RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + } + + return 0; +} + +/* WEAK for SDK 0.5.6 */ +RT_WEAK void uart_debug_init(int uart_channel) +{ +} diff --git a/bsp/qemu-virt64-riscv/driver/drv_uart.h b/bsp/qemu-virt64-riscv/driver/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..a7a18d0ddeabc8045f058a7bccc252cf4bcbe5c0 --- /dev/null +++ b/bsp/qemu-virt64-riscv/driver/drv_uart.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +void rt_hw_uart_start_rx_thread(); +int rt_hw_uart_init(void); +void drv_uart_puts(char *str); // for syscall + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/qemu-virt64-riscv/link.lds b/bsp/qemu-virt64-riscv/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..a6e8a061a04dfab99844aa267f288c79e44f169d --- /dev/null +++ b/bsp/qemu-virt64-riscv/link.lds @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/12/12 bernard The first version + */ + +INCLUDE "link_stacksize.lds" + +OUTPUT_ARCH( "riscv" ) + +/* + * Memory layout: + * 0x80000000 - 0x80200000: SBI + * 0x80200000 - 0x81200000: Kernel + */ + +MEMORY +{ + SRAM : ORIGIN = 0x80200000, LENGTH = 0x1000000 +} + +ENTRY(_start) +SECTIONS +{ + . = 0x80200000 ; + + /* __STACKSIZE__ = 4096; */ + + .start : + { + *(.start); + } > SRAM + + . = ALIGN(8); + + .text : + { + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for initial. */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(8); + + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + . = ALIGN(8); + _etext = .; + } > SRAM + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } > SRAM + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM + + . = ALIGN(8); + + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.sdata) + *(.sdata.*) + } > SRAM + + . = ALIGN(8); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__ctors_end__ = .); + } > SRAM + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__dtors_end__ = .); + } > SRAM + + /* stack for dual core */ + .stack : + { + . = ALIGN(64); + __stack_start__ = .; + + . += __STACKSIZE__; + __stack_cpu0 = .; + + . += __STACKSIZE__; + __stack_cpu1 = .; + } > SRAM + + .sbss : + { + __bss_start = .; + *(.sbss) + *(.sbss.*) + *(.dynsbss) + *(.scommon) + } > SRAM + + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + __bss_end = .; + } > SRAM + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/qemu-virt64-riscv/link_stacksize.lds b/bsp/qemu-virt64-riscv/link_stacksize.lds new file mode 100644 index 0000000000000000000000000000000000000000..8685bc0f1c2d15f0a4bf11d75e743e5a61b16d95 --- /dev/null +++ b/bsp/qemu-virt64-riscv/link_stacksize.lds @@ -0,0 +1 @@ +__STACKSIZE__ = 16384; \ No newline at end of file diff --git a/bsp/qemu-virt64-riscv/qemu-dbg.sh b/bsp/qemu-virt64-riscv/qemu-dbg.sh new file mode 100644 index 0000000000000000000000000000000000000000..a47cae45edeb0c68a668590d36e77bb1fa07cbc4 --- /dev/null +++ b/bsp/qemu-virt64-riscv/qemu-dbg.sh @@ -0,0 +1 @@ +qemu-system-riscv64 -s -S -nographic -machine virt -m 256M -kernel rtthread.bin diff --git a/bsp/qemu-virt64-riscv/qemu-dumpdtb.sh b/bsp/qemu-virt64-riscv/qemu-dumpdtb.sh new file mode 100644 index 0000000000000000000000000000000000000000..12068b571a902632cf99935b62acd253a402669c --- /dev/null +++ b/bsp/qemu-virt64-riscv/qemu-dumpdtb.sh @@ -0,0 +1 @@ +qemu-system-riscv64 -nographic -machine virt,dumpdtb=virt.dtb -m 256M -kernel rtthread.bin diff --git a/bsp/qemu-virt64-riscv/qemu-nographic.bat b/bsp/qemu-virt64-riscv/qemu-nographic.bat new file mode 100644 index 0000000000000000000000000000000000000000..69e606306d69678762a282fc769df014a439993f --- /dev/null +++ b/bsp/qemu-virt64-riscv/qemu-nographic.bat @@ -0,0 +1 @@ +qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin -bios default diff --git a/bsp/qemu-virt64-riscv/qemu-nographic.sh b/bsp/qemu-virt64-riscv/qemu-nographic.sh new file mode 100755 index 0000000000000000000000000000000000000000..5394923bece1ff9b8493c96c4bf24ed5e577f687 --- /dev/null +++ b/bsp/qemu-virt64-riscv/qemu-nographic.sh @@ -0,0 +1 @@ +qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin -bios default diff --git a/bsp/qemu-virt64-riscv/rtconfig.h b/bsp/qemu-virt64-riscv/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..db8cec7b60cbd01ab9d8329d3e75b7a4e5d9ef29 --- /dev/null +++ b/bsp/qemu-virt64-riscv/rtconfig.h @@ -0,0 +1,208 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 20 +#define RT_USING_SMART +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 16384 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 16384 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMTRACE +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x50000 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_MM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0x150000000 +#define PV_OFFSET 0 +#define ARCH_RISCV +#define ARCH_RISCV64 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 16384 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 32 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_TTY +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_MUSL +#define RT_USING_POSIX +#define RT_USING_POSIX_CLOCKTIME + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define BOARD_virt +#define ENABLE_FPU + +/* General Purpose UARTs */ + +#define __STACKSIZE__ 16384 + +#endif diff --git a/bsp/qemu-virt64-riscv/rtconfig.py b/bsp/qemu-virt64-riscv/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..9202bd684a891ecbd7f006a065ff370ce54ac8dc --- /dev/null +++ b/bsp/qemu-virt64-riscv/rtconfig.py @@ -0,0 +1,56 @@ +import os + +# toolchains options +ARCH ='risc-v' +CPU ='virt64' +CROSS_TOOL ='gcc' + +RTT_ROOT = os.getenv('RTT_ROOT') or os.path.join(os.getcwd(), '..', '..') + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + #EXEC_PATH = r'/home/lizhirui/workspace/riscv64-toolchains/bin' + EXEC_PATH = r'/opt/rtt_riscv64_musl/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + #PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-elf-' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64' + CFLAGS = DEVICE + ' -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -ggdb' + AFLAGS += ' -ggdb' + else: + CFLAGS += ' -O2 -Os' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/raspberry-pi/raspi3-32/.config b/bsp/raspberry-pi/raspi3-32/.config index 78d7e6fbafa2a76ad1b194e9aa72db27b3a37ad5..29190154f7bb9f8637039fb6cf4fd6d4569b363c 100644 --- a/bsp/raspberry-pi/raspi3-32/.config +++ b/bsp/raspberry-pi/raspi3-32/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set CONFIG_RT_USING_SMP=y CONFIG_RT_CPUS_NR=4 CONFIG_RT_ALIGN_SIZE=4 @@ -66,12 +67,15 @@ CONFIG_RT_USING_DEVICE_OPS=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y # CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +# CONFIG_RT_IOREMAP_LATE is not set CONFIG_ARCH_ARM_CORTEX_A=y CONFIG_ARCH_ARM_CORTEX_A7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set # # RT-Thread Components @@ -133,6 +137,7 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set @@ -150,9 +155,12 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set # CONFIG_RT_USING_I2C_BITOPS is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -178,6 +186,8 @@ CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -194,6 +204,7 @@ CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set @@ -241,10 +252,15 @@ CONFIG_RT_USING_POSIX=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -271,6 +287,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -282,7 +300,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -290,6 +311,21 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_AIRKISS_OPEN is not set # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -297,6 +333,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -311,6 +349,9 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -323,6 +364,15 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -334,6 +384,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -341,6 +392,16 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -348,6 +409,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -356,10 +418,16 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -367,7 +435,27 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -378,12 +466,15 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -396,6 +487,52 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set # CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_BCM2836_SOC=y # diff --git a/bsp/raspberry-pi/raspi3-32/Kconfig b/bsp/raspberry-pi/raspi3-32/Kconfig index f7693c837813f47b0315f2305537b4922259e3c8..25c2022babb2afd6fca5e37e2fa5142688dacab2 100644 --- a/bsp/raspberry-pi/raspi3-32/Kconfig +++ b/bsp/raspberry-pi/raspi3-32/Kconfig @@ -23,6 +23,7 @@ config BCM2836_SOC select ARCH_ARM_CORTEX_A7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y source "driver/Kconfig" diff --git a/bsp/raspberry-pi/raspi3-32/rtconfig.h b/bsp/raspberry-pi/raspi3-32/rtconfig.h index b861bf8827bd157c85906f5e5ac49a1520a03cf8..ad8d9de89c39b060c274cb6d83725a0eeee4b69d 100644 --- a/bsp/raspberry-pi/raspi3-32/rtconfig.h +++ b/bsp/raspberry-pi/raspi3-32/rtconfig.h @@ -7,13 +7,10 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 -/* RT_USING_ARCH_DATA_TYPE is not set */ #define RT_USING_SMP #define RT_CPUS_NR 4 #define RT_ALIGN_SIZE 4 -/* RT_THREAD_PRIORITY_8 is not set */ #define RT_THREAD_PRIORITY_32 -/* RT_THREAD_PRIORITY_256 is not set */ #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK @@ -21,19 +18,8 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 -/* RT_USING_TIMER_SOFT is not set */ #define RT_DEBUG #define RT_DEBUG_COLOR -/* RT_DEBUG_INIT_CONFIG is not set */ -/* RT_DEBUG_THREAD_CONFIG is not set */ -/* RT_DEBUG_SCHEDULER_CONFIG is not set */ -/* RT_DEBUG_IPC_CONFIG is not set */ -/* RT_DEBUG_TIMER_CONFIG is not set */ -/* RT_DEBUG_IRQ_CONFIG is not set */ -/* RT_DEBUG_MEM_CONFIG is not set */ -/* RT_DEBUG_SLAB_CONFIG is not set */ -/* RT_DEBUG_MEMHEAP_CONFIG is not set */ -/* RT_DEBUG_MODULE_CONFIG is not set */ /* Inter-Thread communication */ @@ -42,16 +28,12 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ #define RT_USING_MEMPOOL #define RT_USING_MEMHEAP -/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ -/* RT_USING_MEMHEAP_AS_HEAP is not set */ #define RT_USING_MEMTRACE #define RT_USING_HEAP @@ -59,16 +41,14 @@ #define RT_USING_DEVICE #define RT_USING_DEVICE_OPS -/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define ARCH_ARM -/* RT_USING_CPU_FFS is not set */ #define ARCH_ARM_CORTEX_A #define ARCH_ARM_CORTEX_A7 -/* ARCH_CPU_STACK_GROWS_UPWARD is not set */ /* RT-Thread Components */ @@ -79,7 +59,6 @@ /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ @@ -89,11 +68,9 @@ #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION -/* FINSH_ECHO_DISABLE_DEFAULT is not set */ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT #define FINSH_USING_MSH_ONLY @@ -106,261 +83,112 @@ #define DFS_FILESYSTEMS_MAX 2 #define DFS_FILESYSTEM_TYPES_MAX 2 #define DFS_FD_MAX 16 -/* RT_USING_DFS_MNTTABLE is not set */ #define RT_USING_DFS_ELMFAT /* elm-chan's FatFs, Generic FAT Filesystem Module */ #define RT_DFS_ELM_CODE_PAGE 437 #define RT_DFS_ELM_WORD_ACCESS -/* RT_DFS_ELM_USE_LFN_0 is not set */ -/* RT_DFS_ELM_USE_LFN_1 is not set */ -/* RT_DFS_ELM_USE_LFN_2 is not set */ #define RT_DFS_ELM_USE_LFN_3 #define RT_DFS_ELM_USE_LFN 3 #define RT_DFS_ELM_MAX_LFN 255 #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 -/* RT_DFS_ELM_USE_ERASE is not set */ #define RT_DFS_ELM_REENTRANT #define RT_USING_DFS_DEVFS -/* RT_USING_DFS_ROMFS is not set */ -/* RT_USING_DFS_RAMFS is not set */ -/* RT_USING_DFS_UFFS is not set */ -/* RT_USING_DFS_JFFS2 is not set */ /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 -/* RT_USING_SYSTEM_WORKQUEUE is not set */ #define RT_USING_SERIAL -/* RT_SERIAL_USING_DMA is not set */ #define RT_SERIAL_RB_BUFSZ 64 -/* RT_USING_CAN is not set */ #define RT_USING_HWTIMER -/* RT_USING_CPUTIME is not set */ #define RT_USING_I2C -/* RT_USING_I2C_BITOPS is not set */ #define RT_USING_PIN -/* RT_USING_ADC is not set */ -/* RT_USING_PWM is not set */ -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_PM is not set */ #define RT_USING_RTC -/* RT_USING_ALARM is not set */ -/* RT_USING_SOFT_RTC is not set */ #define RT_USING_SDIO #define RT_SDIO_STACK_SIZE 512 #define RT_SDIO_THREAD_PRIORITY 15 #define RT_MMCSD_STACK_SIZE 1024 #define RT_MMCSD_THREAD_PREORITY 22 #define RT_MMCSD_MAX_PARTITION 16 -/* RT_SDIO_DEBUG is not set */ #define RT_USING_SPI -/* RT_USING_QSPI is not set */ -/* RT_USING_SPI_MSD is not set */ -/* RT_USING_SFUD is not set */ -/* RT_USING_ENC28J60 is not set */ -/* RT_USING_SPI_WIFI is not set */ #define RT_USING_WDT -/* RT_USING_AUDIO is not set */ -/* RT_USING_SENSOR is not set */ -/* RT_USING_TOUCH is not set */ -/* RT_USING_HWCRYPTO is not set */ -/* RT_USING_WIFI is not set */ /* Using USB */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ #define RT_USING_LIBC -/* RT_USING_PTHREADS is not set */ #define RT_USING_POSIX -/* RT_USING_POSIX_MMAP is not set */ -/* RT_USING_POSIX_TERMIOS is not set */ -/* RT_USING_POSIX_AIO is not set */ -/* RT_USING_MODULE is not set */ /* Network */ /* Socket abstraction layer */ -/* RT_USING_SAL is not set */ /* Network interface device */ -/* RT_USING_NETDEV is not set */ /* light weight TCP/IP stack */ -/* RT_USING_LWIP is not set */ /* AT commands */ -/* RT_USING_AT is not set */ /* VBUS(Virtual Software BUS) */ -/* RT_USING_VBUS is not set */ /* Utilities */ -/* RT_USING_RYM is not set */ -/* RT_USING_ULOG is not set */ -/* RT_USING_UTEST is not set */ -/* RT_USING_LWP is not set */ /* RT-Thread online packages */ /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_WEBNET is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_JSMN is not set */ -/* PKG_USING_LIBMODBUS is not set */ -/* PKG_USING_FREEMODBUS is not set */ -/* PKG_USING_LJSON is not set */ -/* PKG_USING_EZXML is not set */ -/* PKG_USING_NANOPB is not set */ /* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ -/* PKG_USING_WLAN_WICED is not set */ -/* PKG_USING_RW007 is not set */ -/* PKG_USING_COAP is not set */ -/* PKG_USING_NOPOLL is not set */ -/* PKG_USING_NETUTILS is not set */ -/* PKG_USING_AT_DEVICE is not set */ -/* PKG_USING_ATSRV_SOCKET is not set */ -/* PKG_USING_WIZNET is not set */ /* IoT Cloud */ -/* PKG_USING_ONENET is not set */ -/* PKG_USING_GAGENT_CLOUD is not set */ -/* PKG_USING_ALI_IOTKIT is not set */ -/* PKG_USING_AZURE is not set */ -/* PKG_USING_TENCENT_IOTHUB is not set */ -/* PKG_USING_NIMBLE is not set */ -/* PKG_USING_OTA_DOWNLOADER is not set */ -/* PKG_USING_IPMSG is not set */ -/* PKG_USING_LSSDP is not set */ -/* PKG_USING_AIRKISS_OPEN is not set */ -/* PKG_USING_LIBRWS is not set */ -/* PKG_USING_TCPSERVER is not set */ /* security packages */ -/* PKG_USING_MBEDTLS is not set */ -/* PKG_USING_libsodium is not set */ -/* PKG_USING_TINYCRYPT is not set */ /* language packages */ -/* PKG_USING_LUA is not set */ -/* PKG_USING_JERRYSCRIPT is not set */ -/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ -/* PKG_USING_OPENMV is not set */ -/* PKG_USING_MUPDF is not set */ -/* PKG_USING_STEMWIN is not set */ /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYFLASH is not set */ -/* PKG_USING_EASYLOGGER is not set */ -/* PKG_USING_SYSTEMVIEW is not set */ -/* PKG_USING_RDB is not set */ -/* PKG_USING_QRCODE is not set */ -/* PKG_USING_ULOG_EASYFLASH is not set */ -/* PKG_USING_ADBD is not set */ /* system packages */ -/* PKG_USING_GUIENGINE is not set */ -/* PKG_USING_PERSIMMON is not set */ -/* PKG_USING_CAIRO is not set */ -/* PKG_USING_PIXMAN is not set */ -/* PKG_USING_LWEXT4 is not set */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_FAL is not set */ -/* PKG_USING_SQLITE is not set */ -/* PKG_USING_RTI is not set */ -/* PKG_USING_LITTLEVGL2RTT is not set */ -/* PKG_USING_CMSIS is not set */ -/* PKG_USING_DFS_YAFFS is not set */ -/* PKG_USING_LITTLEFS is not set */ -/* PKG_USING_THREAD_POOL is not set */ /* peripheral libraries and drivers */ -/* PKG_USING_SENSORS_DRIVERS is not set */ -/* PKG_USING_REALTEK_AMEBA is not set */ -/* PKG_USING_SHT2X is not set */ -/* PKG_USING_STM32_SDIO is not set */ -/* PKG_USING_ICM20608 is not set */ -/* PKG_USING_U8G2 is not set */ -/* PKG_USING_BUTTON is not set */ -/* PKG_USING_PCF8574 is not set */ -/* PKG_USING_SX12XX is not set */ -/* PKG_USING_SIGNAL_LED is not set */ -/* PKG_USING_LEDBLINK is not set */ -/* PKG_USING_WM_LIBRARIES is not set */ -/* PKG_USING_KENDRYTE_SDK is not set */ -/* PKG_USING_INFRARED is not set */ -/* PKG_USING_ROSSERIAL is not set */ -/* PKG_USING_AT24CXX is not set */ -/* PKG_USING_MOTIONDRIVER2RTT is not set */ -/* PKG_USING_AD7746 is not set */ -/* PKG_USING_PCA9685 is not set */ -/* PKG_USING_I2C_TOOLS is not set */ -/* PKG_USING_NRF24L01 is not set */ -/* PKG_USING_TOUCH_DRIVERS is not set */ -/* PKG_USING_LCD_DRIVERS is not set */ /* miscellaneous packages */ -/* PKG_USING_LIBCSV is not set */ -/* PKG_USING_OPTPARSE is not set */ -/* PKG_USING_FASTLZ is not set */ -/* PKG_USING_MINILZO is not set */ -/* PKG_USING_QUICKLZ is not set */ -/* PKG_USING_MULTIBUTTON is not set */ -/* PKG_USING_CANFESTIVAL is not set */ -/* PKG_USING_ZLIB is not set */ -/* PKG_USING_DSTR is not set */ -/* PKG_USING_TINYFRAME is not set */ -/* PKG_USING_KENDRYTE_DEMO is not set */ -/* PKG_USING_DIGITALCTRL is not set */ /* samples: kernel and components samples */ -/* PKG_USING_KERNEL_SAMPLES is not set */ -/* PKG_USING_FILESYSTEM_SAMPLES is not set */ -/* PKG_USING_NETWORK_SAMPLES is not set */ -/* PKG_USING_PERIPHERAL_SAMPLES is not set */ -/* PKG_USING_HELLO is not set */ -/* PKG_USING_VI is not set */ -/* PKG_USING_NNOM is not set */ -/* PKG_USING_LIBANN is not set */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define BCM2836_SOC /* Hardware Drivers Config */ @@ -368,7 +196,6 @@ /* BCM Peripheral Drivers */ #define BSP_USING_UART -/* RT_USING_UART0 is not set */ #define RT_USING_UART1 #define BSP_USING_PIN #define BSP_USING_SYSTIMER @@ -383,7 +210,6 @@ #define BSP_USING_SPI0_DEVICE1 #define BSP_USING_WDT #define BSP_USING_RTC -/* BSP_USING_ALARM is not set */ #define BSP_USING_SDIO #define BSP_USING_SDIO0 #define BSP_USING_HDMI diff --git a/bsp/raspberry-pi/raspi4-32/.config b/bsp/raspberry-pi/raspi4-32/.config index 60727061a2ccd75bd7c53391f644af92d120b261..748d809aec9dcc8d933207006e62b459d601d107 100644 --- a/bsp/raspberry-pi/raspi4-32/.config +++ b/bsp/raspberry-pi/raspi4-32/.config @@ -8,23 +8,24 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=2048 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set +CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set # CONFIG_RT_DEBUG_THREAD_CONFIG is not set # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set @@ -50,10 +51,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_MEMHEAP=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -62,14 +64,23 @@ CONFIG_RT_USING_HEAP=y # CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLEBUF_SIZE=512 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y # CONFIG_RT_USING_CPU_FFS is not set -CONFIG_ARCH_ARMV8=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0xc0000000 +CONFIG_PV_OFFSET=0x40100000 +CONFIG_RT_IOREMAP_LATE=y +CONFIG_ARCH_ARM_CORTEX_A=y +# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set +CONFIG_ARCH_ARMV8=y # # RT-Thread Components @@ -88,6 +99,7 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 @@ -98,9 +110,6 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # @@ -108,8 +117,8 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_RT_USING_DFS_ELMFAT=y @@ -130,7 +139,8 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 # CONFIG_RT_DFS_ELM_USE_ERASE is not set CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set @@ -141,22 +151,33 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y -CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +CONFIG_RT_USING_SOFT_RTC=y CONFIG_RT_USING_SDIO=y CONFIG_RT_SDIO_STACK_SIZE=512 CONFIG_RT_SDIO_THREAD_PRIORITY=15 @@ -189,12 +210,15 @@ CONFIG_RT_USING_WDT=y # POSIX layer and C standard library # CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y # CONFIG_RT_USING_PTHREADS is not set CONFIG_RT_USING_POSIX=y -# CONFIG_RT_USING_POSIX_MMAP is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set +CONFIG_RT_USING_POSIX_MMAP=y +CONFIG_RT_USING_POSIX_TERMIOS=y # CONFIG_RT_USING_POSIX_GETLINE is not set -# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_USING_POSIX_AIO=y +CONFIG_RT_USING_POSIX_CLOCKTIME=y # CONFIG_RT_USING_MODULE is not set # @@ -204,7 +228,13 @@ CONFIG_RT_USING_POSIX=y # # Socket abstraction layer # -# CONFIG_RT_USING_SAL is not set +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +CONFIG_SAL_USING_POSIX=y # # Network interface device @@ -214,9 +244,9 @@ CONFIG_NETDEV_USING_IFCONFIG=y CONFIG_NETDEV_USING_PING=y CONFIG_NETDEV_USING_NETSTAT=y CONFIG_NETDEV_USING_AUTO_DEFAULT=y -# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_USING_IPV6=y CONFIG_NETDEV_IPV4=1 -CONFIG_NETDEV_IPV6=0 +CONFIG_NETDEV_IPV6=1 # CONFIG_NETDEV_IPV6_SCOPES is not set # @@ -226,7 +256,7 @@ CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y # CONFIG_RT_USING_LWIP212 is not set -# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_USING_LWIP_IPV6=y CONFIG_RT_LWIP_MEM_ALIGNMENT=4 CONFIG_RT_LWIP_IGMP=y CONFIG_RT_LWIP_ICMP=y @@ -239,30 +269,30 @@ CONFIG_IP_SOF_BROADCAST_RECV=1 # # Static IPv4 Address # -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_IPADDR="192.168.137.100" +CONFIG_RT_LWIP_GWADDR="192.168.137.1" CONFIG_RT_LWIP_MSKADDR="255.255.255.0" CONFIG_RT_LWIP_UDP=y CONFIG_RT_LWIP_TCP=y CONFIG_RT_LWIP_RAW=y # CONFIG_RT_LWIP_PPP is not set -CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_MEMP_NUM_NETCONN=16 CONFIG_RT_LWIP_PBUF_NUM=16 CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=8 +CONFIG_RT_LWIP_TCP_PCB_NUM=8 CONFIG_RT_LWIP_TCP_SEG_NUM=40 CONFIG_RT_LWIP_TCP_SND_BUF=8196 CONFIG_RT_LWIP_TCP_WND=8196 CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=4096 # CONFIG_LWIP_NO_RX_THREAD is not set # CONFIG_LWIP_NO_TX_THREAD is not set CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=4096 CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 -# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_RT_LWIP_REASSEMBLY_FRAG=y CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 CONFIG_LWIP_NETIF_LINK_CALLBACK=1 CONFIG_SO_REUSE=1 @@ -294,6 +324,14 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +# CONFIG_RT_USING_GDBSERVER is not set +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_RT_LWP_SHM_MAX_NR=64 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 # # RT-Thread online packages @@ -362,8 +400,6 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -376,6 +412,12 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PDULIB is not set # CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set # # security packages @@ -402,6 +444,8 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set # CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -413,9 +457,12 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set @@ -423,11 +470,24 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set # CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set # # system packages # # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_LWEXT4 is not set @@ -440,6 +500,8 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set @@ -449,8 +511,25 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_RAMDISK is not set # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set # # peripheral libraries and drivers @@ -459,6 +538,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -505,6 +585,30 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set # # miscellaneous packages @@ -514,6 +618,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -534,56 +639,25 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set # CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_MDNS is not set -# CONFIG_PKG_USING_UPNP is not set -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RDBD_SRC is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set CONFIG_BCM2711_SOC=y # CONFIG_BSP_SUPPORT_FPU is not set @@ -604,10 +678,7 @@ CONFIG_BSP_USING_GIC=y CONFIG_BSP_USING_GIC400=y # CONFIG_BSP_USING_GIC500 is not set CONFIG_BSP_USING_PIN=y -CONFIG_BSP_USING_SPI=y -CONFIG_BSP_USING_SPI0_BUS=y -CONFIG_BSP_USING_SPI0_DEVICE0=y -# CONFIG_BSP_USING_SPI0_DEVICE1 is not set +# CONFIG_BSP_USING_SPI is not set CONFIG_BSP_USING_CORETIMER=y # CONFIG_BSP_USING_SYSTIMER is not set CONFIG_BSP_USING_WDT=y @@ -619,4 +690,4 @@ CONFIG_BSP_USING_SDIO0=y # Board Peripheral Drivers # CONFIG_BSP_USING_HDMI=y -CONFIG_BSP_USING_HDMI_DISPLAY=y +# CONFIG_BSP_USING_HDMI_DISPLAY is not set diff --git a/bsp/raspberry-pi/raspi4-32/Kconfig b/bsp/raspberry-pi/raspi4-32/Kconfig index 1e49c4768057b5c709aa6388681959b4e6f8537f..0be620567316d6cb3601d139b0ba5f675eba5c89 100644 --- a/bsp/raspberry-pi/raspi4-32/Kconfig +++ b/bsp/raspberry-pi/raspi4-32/Kconfig @@ -21,6 +21,9 @@ source "$PKGS_DIR/Kconfig" config BCM2711_SOC bool select ARCH_ARMV8 + select ARCH_ARM_CORTEX_A + select RT_USING_CACHE + select ARCH_ARM_MMU select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y diff --git a/bsp/raspberry-pi/raspi4-32/SConstruct b/bsp/raspberry-pi/raspi4-32/SConstruct index 93f349aab8045ad3c742e72664514a7c240b2b6e..1e5eae0d35bab98fb21d3a49a48c4e57e15e45e4 100644 --- a/bsp/raspberry-pi/raspi4-32/SConstruct +++ b/bsp/raspberry-pi/raspi4-32/SConstruct @@ -2,7 +2,10 @@ import os import sys import rtconfig -from rtconfig import RTT_ROOT +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * @@ -11,20 +14,20 @@ TARGET = 'rtthread.' + rtconfig.TARGET_EXT DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' Export('RTT_ROOT') Export('rtconfig') # prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) +objs = PrepareBuilding(env, RTT_ROOT) # make a building DoBuilding(TARGET, objs) - diff --git a/bsp/raspberry-pi/raspi4-32/applications/main.c b/bsp/raspberry-pi/raspi4-32/applications/main.c index 15dc74dc582601d00de51258784e529e14195c9e..6a1321235e7e6231f0c3dc443d127c15e13094d6 100644 --- a/bsp/raspberry-pi/raspi4-32/applications/main.c +++ b/bsp/raspberry-pi/raspi4-32/applications/main.c @@ -4,28 +4,15 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-04-16 bigmagic first version + * Date Author Notes + * 2017-5-30 bernard the first version */ - #include -#include -#include - -#define ACTLED (42) +#include int main(int argc, char** argv) -{ - rt_kprintf("Hi, this is RT-Thread!!\n"); - - rt_pin_mode(ACTLED, PIN_MODE_OUTPUT); +{ + rt_kprintf("hello rt-thread!\n"); - while(1) - { - rt_pin_write(ACTLED, PIN_HIGH); - rt_thread_mdelay(1000); - rt_pin_write(ACTLED, PIN_LOW); - rt_thread_mdelay(1000); - } - return RT_EOK; + return 0; } diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.c b/bsp/raspberry-pi/raspi4-32/driver/board.c index ed25fa4176cc1e37aa797bebbbb96de7a10044ba..8eeca85f50bbb7fe222a7eea483241d6e393ae7f 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/board.c +++ b/bsp/raspberry-pi/raspi4-32/driver/board.c @@ -16,15 +16,52 @@ #include "cp15.h" #include "mmu.h" +#include "mbox.h" +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +rt_mmu_info mmu_info; +extern size_t MMUTable[]; + +size_t gpio_base_addr = GPIO_BASE_ADDR; + +size_t uart_base_addr = UART_BASE; + +size_t gic_base_addr = GIC_V2_BASE; + +size_t arm_timer_base = ARM_TIMER_BASE; + +size_t pactl_cs_base = PACTL_CS_ADDR; + +size_t stimer_base_addr = STIMER_BASE; + +size_t mmc2_base_addr = MMC2_BASE_ADDR; + +size_t videocore_mbox = VIDEOCORE_MBOX; + +size_t mbox_addr = MBOX_ADDR; + +size_t wdt_base_addr = WDT_BASE; + +uint8_t *mac_reg_base_addr = (uint8_t *)MAC_REG; + +uint8_t *eth_send_no_cache = (uint8_t *)SEND_DATA_NO_CACHE; +uint8_t *eth_recv_no_cache = (uint8_t *)RECV_DATA_NO_CACHE; + +#ifdef RT_USING_USERSPACE +struct mem_desc platform_mem_desc[] = { + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0fffffff, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM} +}; +#else struct mem_desc platform_mem_desc[] = { {0x0, 0x6400000, 0x0, NORMAL_MEM}, - {0x8000000, 0x8800000, 0x8000000, DEVICE_MEM}, //mbox msg - {0x0EA00000, 0x0EE00000, 0x0EA00000, DEVICE_MEM}, //framebuffer - {0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac - {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM}, //peripheral - {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic + {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM},//uart gpio + {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic }; +#endif const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); @@ -36,21 +73,26 @@ void rt_hw_timer_isr(int vector, void *parameter) void rt_hw_timer_init(void) { - rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_umask(ARM_TIMER_IRQ); + rt_uint32_t apb_clock = 0; + rt_uint32_t timer_clock = 1000000; /* timer_clock = apb_clock/(pre_divider + 1) */ - ARM_TIMER_PREDIV = (250 - 1); + apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID); + ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1); ARM_TIMER_RELOAD = 0; ARM_TIMER_LOAD = 0; ARM_TIMER_IRQCLR = 0; ARM_TIMER_CTRL = 0; - ARM_TIMER_RELOAD = 10000; - ARM_TIMER_LOAD = 10000; + ARM_TIMER_RELOAD = 1000000/RT_TICK_PER_SECOND; + ARM_TIMER_LOAD = 1000000/RT_TICK_PER_SECOND; /* 23-bit counter, enable interrupt, enable timer */ ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7); + + rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(ARM_TIMER_IRQ); + } void idle_wfi(void) @@ -58,30 +100,90 @@ void idle_wfi(void) asm volatile ("wfi"); } +#ifdef RT_USING_USERSPACE +rt_region_t init_page_region = { + (uint32_t)(KERNEL_VADDR_START + 32 * 1024 * 1024), + (uint32_t)(KERNEL_VADDR_START + 64 * 1024 * 1024), +}; +#endif + /** * Initialize the Hardware related stuffs. Called from rtthread_startup() * after interrupt disabled. */ void rt_hw_board_init(void) { + /* io device remap */ +#ifdef RT_USING_USERSPACE + rt_hw_mmu_map_init(&mmu_info, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); + + rt_page_init(init_page_region); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0xf0000000, 0x10000000); + + arch_kuser_init(&mmu_info, (void*)0xffff0000); +#else + rt_hw_mmu_map_init(&mmu_info, (void*)GPIO_BASE_ADDR, 0x10000000, MMUTable, 0); +#endif + + /* map peripheral address to virtual address */ +#ifdef RT_USING_HEAP + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + + //gpio + gpio_base_addr = (size_t)rt_ioremap((void*)GPIO_BASE_ADDR, 0x1000); + //uart + //uart_base_addr = (size_t)rt_ioremap((void*)UART_BASE, 0x1000); + //aux + //aux_addr = (size_t)rt_ioremap((void*)AUX_BASE_ADDR, 0x1000); + //timer + arm_timer_base = (size_t)rt_ioremap((void*)ARM_TIMER_BASE, 0x1000); + //gic + //gic_base_addr = (size_t)rt_ioremap((void*)GIC_V2_BASE, 0x10000); + //pactl + pactl_cs_base = (size_t)rt_ioremap((void*)PACTL_CS_ADDR, 0x1000); + + //stimer + stimer_base_addr = (size_t)rt_ioremap((void*)STIMER_BASE, 0x1000); + + //mmc2_base_addr + mmc2_base_addr = (size_t)rt_ioremap((void*)MMC2_BASE_ADDR, 0x1000); + + //mbox + videocore_mbox = (size_t)rt_ioremap((void*)VIDEOCORE_MBOX, 0x1000); + + //mbox msg + mbox_addr = (size_t)rt_ioremap((void*)MBOX_ADDR, 0x1000); + mbox = (volatile unsigned int *)mbox_addr; + + //wdt + wdt_base_addr = (size_t)rt_ioremap((void*)WDT_BASE, 0x1000); + + //mac + mac_reg_base_addr = (void *)rt_ioremap((void*)MAC_REG, 0x80000); + + //eth data + eth_send_no_cache = (void *)rt_ioremap((void*)SEND_DATA_NO_CACHE, 0x200000); + eth_recv_no_cache = (void *)rt_ioremap((void*)RECV_DATA_NO_CACHE, 0x200000); + /* initialize hardware interrupt */ rt_hw_interrupt_init(); + /* initialize uart */ - rt_hw_uart_init(); // driver/drv_uart.c + rt_hw_uart_init(); + #ifdef RT_USING_CONSOLE /* set console device */ rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif /* RT_USING_CONSOLE */ -#ifdef RT_USING_HEAP - /* initialize memory system */ - rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); -#endif - /* initialize timer for os tick */ + /* initialize timer for os tick */ rt_hw_timer_init(); rt_thread_idle_sethook(idle_wfi); + rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.h b/bsp/raspberry-pi/raspi4-32/driver/board.h index d675cc658e06c599df8007db4e67e608afa7a45a..5298fd9697b7485a7a1e7023e266c4f0e892e557 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/board.h +++ b/bsp/raspberry-pi/raspi4-32/driver/board.h @@ -13,6 +13,8 @@ #include #include "raspi4.h" +#include "mmu.h" +#include "ioremap.h" extern unsigned char __bss_start; extern unsigned char __bss_end; @@ -22,4 +24,6 @@ extern unsigned char __bss_end; void rt_hw_board_init(void); +extern rt_mmu_info mmu_info; + #endif diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c index a26c3c8519a60cb18eaf0f4b9593bf548303727e..6a40a67588644ce9f88d26cdbb314318ad5f8985 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c @@ -19,13 +19,19 @@ #include "raspi4.h" #include "drv_eth.h" -#define RECV_CACHE_BUF (1024) -#define SEND_DATA_NO_CACHE (0x08200000) -#define RECV_DATA_NO_CACHE (0x08400000) -#define DMA_DISC_ADDR_SIZE (4 * 1024 *1024) +#define DBG_LEVEL DBG_LOG +#include +#define LOG_TAG "drv.eth" -#define RX_DESC_BASE (MAC_REG + GENET_RX_OFF) -#define TX_DESC_BASE (MAC_REG + GENET_TX_OFF) +static int link_speed = 0; +static int link_flag = 0; + +#define RECV_CACHE_BUF (2048) +#define SEND_CACHE_BUF (2048) +#define DMA_DISC_ADDR_SIZE (2 * 1024 *1024) + +#define RX_DESC_BASE (mac_reg_base_addr + GENET_RX_OFF) +#define TX_DESC_BASE (mac_reg_base_addr + GENET_TX_OFF) #define MAX_ADDR_LEN (6) @@ -34,12 +40,15 @@ #define BIT(nr) (1UL << (nr)) +static rt_thread_t link_thread_tid = RT_NULL; +#define LINK_THREAD_STACK_SIZE (1024) +#define LINK_THREAD_PRIORITY (20) +#define LINK_THREAD_TIMESLICE (10) + static rt_uint32_t tx_index = 0; static rt_uint32_t rx_index = 0; static rt_uint32_t index_flag = 0; -static rt_uint32_t send_cache_pbuf[RECV_CACHE_BUF]; - struct rt_eth_dev { struct eth_device parent; @@ -49,11 +58,13 @@ struct rt_eth_dev int state; int index; struct rt_timer link_timer; - struct rt_timer rx_poll_timer; void *priv; }; static struct rt_eth_dev eth_dev; -static struct rt_semaphore sem_lock; + +static struct rt_semaphore send_finsh_sem_lock; + +static struct rt_semaphore link_ack; static inline rt_uint32_t read32(void *addr) { @@ -65,22 +76,39 @@ static inline void write32(void *addr, rt_uint32_t value) (*((volatile unsigned int*)(addr))) = value; } -void eth_rx_irq(void *param) +static void eth_rx_irq(int irq, void *param) { - eth_device_ready(ð_dev.parent); + rt_uint32_t val = 0; + + val = read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT); + val &= ~read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT_MASK); + + write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR, val); + + if (val & GENET_IRQ_RXDMA_DONE) + { + eth_device_ready(ð_dev.parent); + } + + if (val & GENET_IRQ_TXDMA_DONE) + { + rt_sem_release(&send_finsh_sem_lock); + } } /* We only support RGMII (as used on the RPi4). */ static int bcmgenet_interface_set(void) { int phy_mode = PHY_INTERFACE_MODE_RGMII; - switch (phy_mode) { + switch (phy_mode) + { case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_RXID: - write32(MAC_REG + SYS_PORT_CTRL,PORT_MODE_EXT_GPHY); + write32(mac_reg_base_addr + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY); break; + default: - rt_kprintf("unknown phy mode: %d\n", MAC_REG); + rt_kprintf("unknown phy mode: %d\n", mac_reg_base_addr); return -1; } return 0; @@ -89,44 +117,48 @@ static int bcmgenet_interface_set(void) static void bcmgenet_umac_reset(void) { rt_uint32_t reg; - reg = read32(MAC_REG + SYS_RBUF_FLUSH_CTRL); + reg = read32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL); reg |= BIT(1); - write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg); + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); reg &= ~BIT(1); - write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),reg); + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); DELAY_MICROS(10); - write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),0); + + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), 0); DELAY_MICROS(10); - write32(MAC_REG + UMAC_CMD, 0); - write32(MAC_REG + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN)); + + write32(mac_reg_base_addr + UMAC_CMD, 0); + write32(mac_reg_base_addr + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN)); DELAY_MICROS(2); - write32(MAC_REG + UMAC_CMD, 0); + + write32(mac_reg_base_addr + UMAC_CMD, 0); /* clear tx/rx counter */ - write32(MAC_REG + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT); - write32(MAC_REG + UMAC_MIB_CTRL, 0); - write32(MAC_REG + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE); + write32(mac_reg_base_addr + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT); + write32(mac_reg_base_addr + UMAC_MIB_CTRL, 0); + write32(mac_reg_base_addr + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE); + /* init rx registers, enable ip header optimization */ - reg = read32(MAC_REG + RBUF_CTRL); + reg = read32(mac_reg_base_addr + RBUF_CTRL); reg |= RBUF_ALIGN_2B; - write32(MAC_REG + RBUF_CTRL, reg); - write32(MAC_REG + RBUF_TBUF_SIZE_CTRL, 1); + write32(mac_reg_base_addr + RBUF_CTRL, reg); + write32(mac_reg_base_addr + RBUF_TBUF_SIZE_CTRL, 1); } static void bcmgenet_disable_dma(void) { rt_uint32_t tdma_reg = 0, rdma_reg = 0; - tdma_reg = read32(MAC_REG + TDMA_REG_BASE + DMA_CTRL); + tdma_reg = read32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL); tdma_reg &= ~(1UL << DMA_EN); - write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, tdma_reg); - rdma_reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, tdma_reg); + rdma_reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL); rdma_reg &= ~(1UL << DMA_EN); - write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, rdma_reg); - write32(MAC_REG + UMAC_TX_FLUSH, 1); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, rdma_reg); + write32(mac_reg_base_addr + UMAC_TX_FLUSH, 1); DELAY_MICROS(100); - write32(MAC_REG + UMAC_TX_FLUSH, 0); + write32(mac_reg_base_addr + UMAC_TX_FLUSH, 0); } static void bcmgenet_enable_dma(void) @@ -135,30 +167,30 @@ static void bcmgenet_enable_dma(void) rt_uint32_t dma_ctrl = 0; dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; - write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, dma_ctrl); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, dma_ctrl); - reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL); - write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg); + reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg); } static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value) { int count = 10000; rt_uint32_t val; - val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |(reg << MDIO_REG_SHIFT) | (0xffff & value); - write32(MAC_REG + MDIO_CMD, val); + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT) | (0xffff & value); + write32(mac_reg_base_addr + MDIO_CMD, val); - rt_uint32_t reg_val = read32(MAC_REG + MDIO_CMD); + rt_uint32_t reg_val = read32(mac_reg_base_addr + MDIO_CMD); reg_val = reg_val | MDIO_START_BUSY; - write32(MAC_REG + MDIO_CMD, reg_val); + write32(mac_reg_base_addr + MDIO_CMD, reg_val); - while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + { DELAY_MICROS(1); - - reg_val = read32(MAC_REG + MDIO_CMD); + } + reg_val = read32(mac_reg_base_addr + MDIO_CMD); return reg_val & 0xffff; - } static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg) @@ -168,32 +200,32 @@ static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg) rt_uint32_t reg_val = 0; val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); - write32(MAC_REG + MDIO_CMD, val); + write32(mac_reg_base_addr + MDIO_CMD, val); - reg_val = read32(MAC_REG + MDIO_CMD); + reg_val = read32(mac_reg_base_addr + MDIO_CMD); reg_val = reg_val | MDIO_START_BUSY; - write32(MAC_REG + MDIO_CMD, reg_val); + write32(mac_reg_base_addr + MDIO_CMD, reg_val); - while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + { DELAY_MICROS(1); + } + reg_val = read32(mac_reg_base_addr + MDIO_CMD); - reg_val = read32(MAC_REG + MDIO_CMD); - - return reg_val & 0xffff; + return reg_val & 0xffff; } static int bcmgenet_gmac_write_hwaddr(void) { - //{0xdc,0xa6,0x32,0x28,0x22,0x50}; rt_uint8_t addr[6]; rt_uint32_t reg; bcm271x_mbox_hardware_get_mac_address(&addr[0]); reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; - write32(MAC_REG + UMAC_MAC0, reg); + write32(mac_reg_base_addr + UMAC_MAC0, reg); reg = addr[4] << 8 | addr[5]; - write32(MAC_REG + UMAC_MAC1, reg); + write32(mac_reg_base_addr + UMAC_MAC1, reg); return 0; } @@ -207,9 +239,9 @@ static int get_ethernet_uid(void) uid_low = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_LOW); uid = (uid_high << 16 | uid_low); - if(BCM54213PE_VERSION_B1 == uid) + if (BCM54213PE_VERSION_B1 == uid) { - rt_kprintf("version is B1\n"); + LOG_I("version is B1\n"); } return uid; } @@ -219,10 +251,8 @@ static void bcmgenet_mdio_init(void) rt_uint32_t ret = 0; /*get ethernet uid*/ ret = get_ethernet_uid(); - if(ret == 0) - { - return; - } + if (ret == 0) return; + /* reset phy */ bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET); /* read control reg */ @@ -236,45 +266,47 @@ static void bcmgenet_mdio_init(void) /* read status reg */ bcmgenet_mdio_read(1, BCM54213PE_IEEE_EXTENDED_STATUS); bcmgenet_mdio_read(1, BCM54213PE_AUTO_NEGOTIATION_ADV); + bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS); bcmgenet_mdio_read(1, BCM54213PE_CONTROL); /* half full duplex capability */ bcmgenet_mdio_write(1, BCM54213PE_CONTROL, (CONTROL_HALF_DUPLEX_CAPABILITY | CONTROL_FULL_DUPLEX_CAPABILITY)); bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL); + /* set mii control */ - bcmgenet_mdio_write(1,BCM54213PE_MII_CONTROL,(MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART| MII_CONTROL_PHY_FULL_DUPLEX| MII_CONTROL_SPEED_SELECTION)); + bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, (MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART | MII_CONTROL_PHY_FULL_DUPLEX | MII_CONTROL_SPEED_SELECTION)); } static void rx_ring_init(void) { - write32(MAC_REG + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); - write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR,0x0 ); - write32(MAC_REG + RDMA_READ_PTR, 0x0); - write32(MAC_REG + RDMA_WRITE_PTR, 0x0); - write32(MAC_REG + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1); - - write32(MAC_REG + RDMA_PROD_INDEX, 0x0); - write32(MAC_REG + RDMA_CONS_INDEX, 0x0); - write32(MAC_REG + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); - write32(MAC_REG + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE); - write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); + write32(mac_reg_base_addr + RDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + RDMA_WRITE_PTR, 0x0); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1); + + write32(mac_reg_base_addr + RDMA_PROD_INDEX, 0x0); + write32(mac_reg_base_addr + RDMA_CONS_INDEX, 0x0); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(mac_reg_base_addr + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); } static void tx_ring_init(void) { - write32(MAC_REG + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); - write32(MAC_REG + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); - write32(MAC_REG + TDMA_READ_PTR, 0x0); - write32(MAC_REG + TDMA_READ_PTR, 0x0); - write32(MAC_REG + TDMA_READ_PTR, 0x0); - write32(MAC_REG + TDMA_WRITE_PTR, 0x0); - write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR,TX_DESCS * DMA_DESC_SIZE / 4 - 1); - write32(MAC_REG + TDMA_PROD_INDEX, 0x0); - write32(MAC_REG + TDMA_CONS_INDEX, 0x0); - write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH,0x1); - write32(MAC_REG + TDMA_FLOW_PERIOD,0x0); - write32(MAC_REG + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); - write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); + write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_WRITE_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1); + write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0x0); + write32(mac_reg_base_addr + TDMA_CONS_INDEX, 0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1); + write32(mac_reg_base_addr + TDMA_FLOW_PERIOD, 0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); } static void rx_descs_init(void) @@ -284,55 +316,21 @@ static void rx_descs_init(void) void *desc_base = (void *)RX_DESC_BASE; len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; - for (i = 0; i < RX_DESCS; i++) { - write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO), lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); - write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI),upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); - write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS),len_stat); - } -} - -static int phy_startup(void) -{ - int count = 1000000; - while ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) && (--count)) - DELAY_MICROS(1); - if(count > 0) + for (i = 0; i < RX_DESCS; i++) { - rt_kprintf("bcmgenet: PHY startup ok!\n"); - } - else - { - rt_kprintf("bcmgenet: PHY startup err!\n"); - return 1; - } - - if(bcmgenet_mdio_read(1, BCM54213PE_STATUS) == 0) - { - //todo - } - else - { - rt_kprintf("bcmgenet: BCM54213PE_STATUS err!\n"); - } - - if(bcmgenet_mdio_read(1, BCM54213PE_CONTROL) == (CONTROL_FULL_DUPLEX_CAPABILITY| CONTROL_HALF_DUPLEX_CAPABILITY)) - { - //todo - } - else - { - rt_kprintf("bcmgenet: BCM54213PE_CONTROL err!\n"); + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO), lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI), upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS), len_stat); } - - return 0; } static int bcmgenet_adjust_link(void) { rt_uint32_t speed; - rt_uint32_t phy_dev_speed = SPEED_100; - - switch (phy_dev_speed) { + rt_uint32_t phy_dev_speed = link_speed; + + switch (phy_dev_speed) + { case SPEED_1000: speed = UMAC_SPEED_1000; break; @@ -347,17 +345,25 @@ static int bcmgenet_adjust_link(void) return -1; } - rt_uint32_t reg1 = read32(MAC_REG + EXT_RGMII_OOB_CTRL); + rt_uint32_t reg1 = read32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL); //reg1 &= ~(1UL << OOB_DISABLE); //rt_kprintf("OOB_DISABLE is %d\n", OOB_DISABLE); reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); - write32(MAC_REG + EXT_RGMII_OOB_CTRL, reg1); + write32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL, reg1); DELAY_MICROS(1000); - write32(MAC_REG + UMAC_CMD, speed << CMD_SPEED_SHIFT); + write32(mac_reg_base_addr + UMAC_CMD, speed << CMD_SPEED_SHIFT); return 0; } +void link_irq(void *param) +{ + if ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) != 0) + { + rt_sem_release(&link_ack); + } +} + static int bcmgenet_gmac_eth_start(void) { rt_uint32_t ret; @@ -375,41 +381,37 @@ static int bcmgenet_gmac_eth_start(void) /* Enable RX/TX DMA */ bcmgenet_enable_dma(); - /* read PHY properties over the wire from generic PHY set-up */ - ret = phy_startup(); - if (ret) { - rt_kprintf("bcmgenet: PHY startup failed: %d\n", ret); - return ret; - } - /* Update MAC registers based on PHY property */ ret = bcmgenet_adjust_link(); - if (ret) { + if(ret) + { rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret); return ret; } /* wait tx index clear */ - while ((read32(MAC_REG + TDMA_CONS_INDEX) != 0) && (--count)) - DELAY_MICROS(1); + while ((read32(mac_reg_base_addr + TDMA_CONS_INDEX) != 0) && (--count)) + DELAY_MICROS(1); - tx_index = read32(MAC_REG + TDMA_CONS_INDEX); - write32(MAC_REG + TDMA_PROD_INDEX, tx_index); + tx_index = read32(mac_reg_base_addr + TDMA_CONS_INDEX); + write32(mac_reg_base_addr + TDMA_PROD_INDEX, tx_index); - index_flag = read32(MAC_REG + RDMA_PROD_INDEX); + index_flag = read32(mac_reg_base_addr + RDMA_PROD_INDEX); - rx_index = index_flag % 256; + rx_index = index_flag % RX_DESCS; - write32(MAC_REG + RDMA_CONS_INDEX, index_flag); - write32(MAC_REG + RDMA_PROD_INDEX, index_flag); + write32(mac_reg_base_addr + RDMA_CONS_INDEX, index_flag); + write32(mac_reg_base_addr + RDMA_PROD_INDEX, index_flag); /* Enable Rx/Tx */ rt_uint32_t rx_tx_en; - rx_tx_en = read32(MAC_REG + UMAC_CMD); - + rx_tx_en = read32(mac_reg_base_addr + UMAC_CMD); rx_tx_en |= (CMD_TX_EN | CMD_RX_EN); - write32(MAC_REG + UMAC_CMD, rx_tx_en); + write32(mac_reg_base_addr + UMAC_CMD, rx_tx_en); + + // eanble IRQ for TxDMA done and RxDMA done + write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE); return 0; } @@ -419,21 +421,20 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) { void* desc_base; rt_uint32_t length = 0, addr = 0; - rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX); - //get next - if(prod_index == index_flag) + rt_uint32_t prod_index = read32(mac_reg_base_addr + RDMA_PROD_INDEX); + if(prod_index == index_flag) //no buff { cur_recv_cnt = index_flag; - //no buff + index_flag = 0x7fffffff; return 0; } else { - if(prev_recv_cnt == prod_index) + if(prev_recv_cnt == (prod_index & 0xffff)) //no new buff { return 0; } - + desc_base = RX_DESC_BASE + rx_index * DMA_DESC_SIZE; length = read32(desc_base + DMA_DESC_LENGTH_STATUS); length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; @@ -442,110 +443,163 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) * This would actually not be needed if we don't program * RBUF_ALIGN_2B */ - *packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET); + //Convert to memory address + addr = addr + eth_recv_no_cache - RECV_DATA_NO_CACHE; + rt_hw_cpu_dcache_invalidate(addr,length); + *packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET); rx_index = rx_index + 1; - if(rx_index >= 256) + if(rx_index >= RX_DESCS) { rx_index = 0; } - write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt); + + write32(mac_reg_base_addr + RDMA_CONS_INDEX, cur_recv_cnt); cur_recv_cnt = cur_recv_cnt + 1; + + if(cur_recv_cnt > 0xffff) + { + cur_recv_cnt = 0; + } prev_recv_cnt = cur_recv_cnt; - return length; + return length - RX_BUF_OFFSET; } } -static int bcmgenet_gmac_eth_send(void *packet, int length) +static int bcmgenet_gmac_eth_send(rt_uint32_t packet, int length,struct pbuf *p) { - void* desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE); + rt_ubase_t level; + void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE); + pbuf_copy_partial(p, (void*)(packet + tx_index * SEND_CACHE_BUF), p->tot_len, 0); rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT; - - rt_uint32_t prod_index, cons; - rt_uint32_t tries = 100; - - prod_index = read32(MAC_REG + TDMA_PROD_INDEX); - len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; + rt_hw_cpu_dcache_clean((void*)(packet + tx_index * SEND_CACHE_BUF),length); + + rt_uint32_t prod_index; - write32((desc_base + DMA_DESC_ADDRESS_LO),SEND_DATA_NO_CACHE); - write32((desc_base + DMA_DESC_ADDRESS_HI),0); - write32((desc_base + DMA_DESC_LENGTH_STATUS),len_stat); + prod_index = read32(mac_reg_base_addr + TDMA_PROD_INDEX); - if(++tx_index>= TX_DESCS) + write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE + tx_index * SEND_CACHE_BUF); + write32((desc_base + DMA_DESC_ADDRESS_HI), 0); + write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat); + + tx_index++; + if(tx_index >= TX_DESCS) { tx_index = 0; } - prod_index++; - /* Start Transmisson */ - write32(MAC_REG + TDMA_PROD_INDEX,prod_index); + prod_index = prod_index+1; - do { - cons = read32(MAC_REG + TDMA_CONS_INDEX); - } while ((cons & 0xffff) < prod_index && --tries); - if (!tries) + if (prod_index > 0xffff) { - return -1; + prod_index = 0; } + + /* Start Transmisson */ + write32(mac_reg_base_addr + TDMA_PROD_INDEX, prod_index); return 0; } -static rt_err_t bcmgenet_eth_init(rt_device_t device) +static void link_task_entry(void *param) { - struct eth_device *eth_device = (struct eth_device *)device; + struct eth_device *eth_device = (struct eth_device *)param; RT_ASSERT(eth_device != RT_NULL); + struct rt_eth_dev *dev = ð_dev; + + //start mdio + bcmgenet_mdio_init(); + + //start timer link + rt_timer_init(&dev->link_timer, "link_timer", + link_irq, + NULL, + 100, + RT_TIMER_FLAG_PERIODIC); + rt_timer_start(&dev->link_timer); + + //link wait forever + rt_sem_take(&link_ack, RT_WAITING_FOREVER); + eth_device_linkchange(ð_dev.parent, RT_TRUE); //link up + rt_timer_stop(&dev->link_timer); + + //set mac + // bcmgenet_gmac_write_hwaddr(); + bcmgenet_gmac_write_hwaddr(); + + //check link speed + if ((bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 10)) || (bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 11))) + { + link_speed = 1000; + rt_kprintf("Support link mode Speed 1000M\n"); + } + else if ((bcmgenet_mdio_read(1, 0x05) & (1 << 7)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 8)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 9))) + { + link_speed = 100; + rt_kprintf("Support link mode Speed 100M\n"); + } + else + { + link_speed = 10; + rt_kprintf("Support link mode Speed 10M\n"); + } + + + //Convert to memory address + bcmgenet_gmac_eth_start(); + + rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq"); + rt_hw_interrupt_umask(ETH_IRQ); + + link_flag = 1; +} + +static rt_err_t bcmgenet_eth_init(rt_device_t device) +{ rt_uint32_t ret = 0; rt_uint32_t hw_reg = 0; - struct rt_eth_dev *dev = ð_dev; - + /* Read GENET HW version */ rt_uint8_t major = 0; - hw_reg = read32(MAC_REG + SYS_REV_CTRL); + hw_reg = read32(mac_reg_base_addr + SYS_REV_CTRL); major = (hw_reg >> 24) & 0x0f; - if (major != 6) { + if (major != 6) + { if (major == 5) + { major = 4; + } else if (major == 0) + { major = 1; - + } rt_kprintf("Uns upported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f); return RT_ERROR; } - /* set interface */ ret = bcmgenet_interface_set(); if (ret) { return ret; - } + } /* rbuf clear */ - write32(MAC_REG + SYS_RBUF_FLUSH_CTRL, 0); + write32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL, 0); /* disable MAC while updating its registers */ - write32(MAC_REG + UMAC_CMD, 0); + write32(mac_reg_base_addr + UMAC_CMD, 0); /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ - write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN); - - bcmgenet_mdio_init(); - - bcmgenet_gmac_write_hwaddr(); - bcmgenet_gmac_write_hwaddr(); - - bcmgenet_gmac_eth_start(); - - //irq or poll - rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer", - eth_rx_irq, - NULL, - 1, - RT_TIMER_FLAG_PERIODIC); - - rt_timer_start(&dev->rx_poll_timer); + write32(mac_reg_base_addr + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN); + link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device, + LINK_THREAD_STACK_SIZE, + LINK_THREAD_PRIORITY, LINK_THREAD_TIMESLICE); + if (link_thread_tid != RT_NULL) + { + rt_thread_startup(link_thread_tid); + } return RT_EOK; } @@ -554,10 +608,16 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args) switch (cmd) { case NIOCTL_GADDR: - if (args) rt_memcpy(args, eth_dev.dev_addr, 6); - else return -RT_ERROR; + if (args) + { + rt_memcpy(args, eth_dev.dev_addr, 6); + } + else + { + return -RT_ERROR; + } break; - default : + default: break; } return RT_EOK; @@ -565,50 +625,43 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args) rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) { - rt_uint32_t sendbuf = SEND_DATA_NO_CACHE; - /* lock eth device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - //struct rt_eth_dev *dev = (struct rt_eth_dev *) device; - pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0); - rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len); - - bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len); - rt_sem_release(&sem_lock); + if (link_flag == 1) + { + bcmgenet_gmac_eth_send((rt_uint32_t)eth_send_no_cache, p->tot_len,p); + rt_sem_take(&send_finsh_sem_lock,RT_WAITING_FOREVER); + } return RT_EOK; } -char recv_data[RX_BUF_LENGTH]; struct pbuf *rt_eth_rx(rt_device_t device) { int recv_len = 0; - rt_uint32_t addr_point[8]; + rt_uint8_t* addr_point = RT_NULL; struct pbuf *pbuf = RT_NULL; - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - - recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]); - - if(recv_len > 0) + if (link_flag == 1) { - pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); - rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len); + recv_len = bcmgenet_gmac_eth_recv(&addr_point); + if (recv_len > 0) + { + pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); + if(pbuf) + rt_memcpy(pbuf->payload, addr_point, recv_len); + } } - rt_sem_release(&sem_lock); return pbuf; } int rt_hw_eth_init(void) { rt_uint8_t mac_addr[6]; - - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - + rt_sem_init(&send_finsh_sem_lock,"send_finsh_sem_lock",TX_DESCS,RT_IPC_FLAG_FIFO); + rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO); memset(ð_dev, 0, sizeof(eth_dev)); - memset((void *)SEND_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE)); - memset((void *)RECV_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE)); - + memset((void *)eth_send_no_cache, 0, DMA_DISC_ADDR_SIZE); + memset((void *)eth_recv_no_cache, 0, DMA_DISC_ADDR_SIZE); bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]); - eth_dev.iobase = MAC_REG; + eth_dev.iobase = mac_reg_base_addr; eth_dev.name = "e0"; eth_dev.dev_addr[0] = mac_addr[0]; eth_dev.dev_addr[1] = mac_addr[1]; @@ -629,9 +682,8 @@ int rt_hw_eth_init(void) eth_dev.parent.eth_tx = rt_eth_tx; eth_dev.parent.eth_rx = rt_eth_rx; - eth_device_init(&(eth_dev.parent), "e0"); - eth_device_linkchange(ð_dev.parent, RT_TRUE); //linkup the e0 for lwip to check + eth_device_linkchange(ð_dev.parent, RT_FALSE); //link down return 0; } INIT_COMPONENT_EXPORT(rt_hw_eth_init); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h index 708e626975c36d10307c74f534ce37a28b1af4ee..860674847a4916b0c78e498913caf24836815aa8 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h @@ -12,7 +12,6 @@ #ifndef __DRV_ETH_H__ #define __DRV_ETH_H__ -#define MAC_REG (void *)(0xfd580000) //#define BIT(nr) (1UL << (nr)) @@ -53,6 +52,17 @@ #define MDIO_REG_SHIFT (16) #define MDIO_REG_MASK (0x1f) +#define GENET_INTRL2_OFF (0x0200) +#define GENET_INTRL2_CPU_STAT (GENET_INTRL2_OFF + 0x00) +#define GENET_INTRL2_CPU_CLEAR (GENET_INTRL2_OFF + 0x08) +#define GENET_INTRL2_CPU_STAT_MASK (GENET_INTRL2_OFF + 0x0c) +#define GENET_INTRL2_CPU_SET_MASK (GENET_INTRL2_OFF + 0x10) +#define GENET_INTRL2_CPU_CLEAR_MASK (GENET_INTRL2_OFF + 0x14) +#define GENET_IRQ_MDIO_ERROR BIT(24) +#define GENET_IRQ_MDIO_DONE BIT(23) +#define GENET_IRQ_TXDMA_DONE BIT(16) +#define GENET_IRQ_RXDMA_DONE BIT(13) + #define CMD_TX_EN BIT(0) #define CMD_RX_EN BIT(1) #define UMAC_SPEED_10 (0) diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c index b2d2ed79c49a34198094442da0c8a92d09917c63..b9f6689ae3e38ea8d4e8a9fd7a92f862b3a72248 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c @@ -23,26 +23,26 @@ static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM]; uint32_t raspi_get_pin_state(uint32_t fselnum) { uint32_t gpfsel = 0; - + switch (fselnum) { case 0: - gpfsel = GPIO_REG_GPFSEL0(GPIO_BASE); + gpfsel = GPIO_REG_GPFSEL0(gpio_base_addr); break; case 1: - gpfsel = GPIO_REG_GPFSEL1(GPIO_BASE); + gpfsel = GPIO_REG_GPFSEL1(gpio_base_addr); break; case 2: - gpfsel = GPIO_REG_GPFSEL2(GPIO_BASE); + gpfsel = GPIO_REG_GPFSEL2(gpio_base_addr); break; case 3: - gpfsel = GPIO_REG_GPFSEL3(GPIO_BASE); + gpfsel = GPIO_REG_GPFSEL3(gpio_base_addr); break; case 4: - gpfsel = GPIO_REG_GPFSEL4(GPIO_BASE); + gpfsel = GPIO_REG_GPFSEL4(gpio_base_addr); break; case 5: - gpfsel = GPIO_REG_GPFSEL5(GPIO_BASE); + gpfsel = GPIO_REG_GPFSEL5(gpio_base_addr); break; default: break; @@ -55,22 +55,22 @@ void raspi_set_pin_state(uint32_t fselnum, uint32_t gpfsel) switch (fselnum) { case 0: - GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel; + GPIO_REG_GPFSEL0(gpio_base_addr) = gpfsel; break; case 1: - GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel; + GPIO_REG_GPFSEL1(gpio_base_addr) = gpfsel; break; case 2: - GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel; + GPIO_REG_GPFSEL2(gpio_base_addr) = gpfsel; break; case 3: - GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel; + GPIO_REG_GPFSEL3(gpio_base_addr) = gpfsel; break; case 4: - GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel; + GPIO_REG_GPFSEL4(gpio_base_addr) = gpfsel; break; case 5: - GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel; + GPIO_REG_GPFSEL5(gpio_base_addr) = gpfsel; break; default: break; @@ -86,22 +86,22 @@ static void gpio_set_pud(GPIO_PIN pin, GPIO_PUPD_FUNC mode) switch (fselnum) { case 0: - reg_value = GPIO_PUP_PDN_CNTRL_REG0(GPIO_BASE); - GPIO_PUP_PDN_CNTRL_REG0(GPIO_BASE) = (reg_value | (mode << (fselrest*2))); + reg_value = GPIO_PUP_PDN_CNTRL_REG0(gpio_base_addr); + GPIO_PUP_PDN_CNTRL_REG0(gpio_base_addr) = (reg_value | (mode << (fselrest*2))); break; case 1: - reg_value = GPIO_PUP_PDN_CNTRL_REG1(GPIO_BASE); - GPIO_PUP_PDN_CNTRL_REG1(GPIO_BASE) = (reg_value | (mode << (fselrest*2))); + reg_value = GPIO_PUP_PDN_CNTRL_REG1(gpio_base_addr); + GPIO_PUP_PDN_CNTRL_REG1(gpio_base_addr) = (reg_value | (mode << (fselrest*2))); break; case 2: - reg_value = GPIO_PUP_PDN_CNTRL_REG2(GPIO_BASE); - GPIO_PUP_PDN_CNTRL_REG2(GPIO_BASE) = (reg_value | (mode << (fselrest*2))); + reg_value = GPIO_PUP_PDN_CNTRL_REG2(gpio_base_addr); + GPIO_PUP_PDN_CNTRL_REG2(gpio_base_addr) = (reg_value | (mode << (fselrest*2))); break; case 3: - reg_value = GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE); - GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE) = (reg_value | (mode << (fselrest*2))); + reg_value = GPIO_PUP_PDN_CNTRL_REG3(gpio_base_addr); + GPIO_PUP_PDN_CNTRL_REG3(gpio_base_addr) = (reg_value | (mode << (fselrest*2))); break; default: break; @@ -128,23 +128,24 @@ void prev_raspi_pin_write(GPIO_PIN pin, int pin_value) { if(pin_value == 1) { - GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32); + GPIO_REG_GPSET0(gpio_base_addr) = 1 << (pin % 32); } else { - GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32); + GPIO_REG_GPCLR0(gpio_base_addr) = 1 << (pin % 32); } } else { if(pin_value == 1) { - GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32); + GPIO_REG_GPSET1(gpio_base_addr) = 1 << (pin % 32); } else { - GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32); + GPIO_REG_GPCLR1(gpio_base_addr) = 1 << (pin % 32); } + } } @@ -187,7 +188,7 @@ static int raspi_pin_read(struct rt_device *device, rt_base_t pin) if(num == 0) { - if(GPIO_REG_GPLEV0(GPIO_BASE) & (1 << pin)) + if(GPIO_REG_GPLEV0(gpio_base_addr) & (1 << pin)) { pin_level = 1; } @@ -199,7 +200,7 @@ static int raspi_pin_read(struct rt_device *device, rt_base_t pin) } else { - if(GPIO_REG_GPLEV1(GPIO_BASE) & (1 << pin)) + if(GPIO_REG_GPLEV1(gpio_base_addr) & (1 << pin)) { pin_level = 1; } @@ -235,65 +236,65 @@ static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, r case PIN_IRQ_MODE_RISING: if(pin_num == 0) { - reg_value = GPIO_REG_GPREN0(GPIO_BASE); - GPIO_REG_GPREN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPREN0(gpio_base_addr); + GPIO_REG_GPREN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); } else { - reg_value = GPIO_REG_GPREN1(GPIO_BASE); - GPIO_REG_GPREN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPREN1(gpio_base_addr); + GPIO_REG_GPREN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); } break; case PIN_IRQ_MODE_FALLING: if(pin_num == 0) { - reg_value = GPIO_REG_GPFEN0(GPIO_BASE); - GPIO_REG_GPFEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPFEN0(gpio_base_addr); + GPIO_REG_GPFEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); } else { - reg_value = GPIO_REG_GPFEN1(GPIO_BASE); - GPIO_REG_GPFEN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPFEN1(gpio_base_addr); + GPIO_REG_GPFEN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); } break; case PIN_IRQ_MODE_RISING_FALLING: if(pin_num == 0) { - reg_value = GPIO_REG_GPAREN0(GPIO_BASE); - GPIO_REG_GPAREN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); - reg_value = GPIO_REG_GPFEN0(GPIO_BASE); - GPIO_REG_GPFEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPAREN0(gpio_base_addr); + GPIO_REG_GPAREN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPFEN0(gpio_base_addr); + GPIO_REG_GPFEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); } else { - reg_value = GPIO_REG_GPAREN1(GPIO_BASE); - GPIO_REG_GPAREN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); - reg_value = GPIO_REG_GPFEN1(GPIO_BASE); - GPIO_REG_GPFEN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPAREN1(gpio_base_addr); + GPIO_REG_GPAREN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPFEN1(gpio_base_addr); + GPIO_REG_GPFEN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); } break; case PIN_IRQ_MODE_HIGH_LEVEL: if(pin_num == 0) { - reg_value = GPIO_REG_GPHEN0(GPIO_BASE); - GPIO_REG_GPHEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPHEN0(gpio_base_addr); + GPIO_REG_GPHEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); } else { - reg_value = GPIO_REG_GPHEN1(GPIO_BASE); - GPIO_REG_GPHEN1(GPIO_BASE) = (reg_value & ~ mask) | ( mask); + reg_value = GPIO_REG_GPHEN1(gpio_base_addr); + GPIO_REG_GPHEN1(gpio_base_addr) = (reg_value & ~ mask) | ( mask); } break; case PIN_IRQ_MODE_LOW_LEVEL: if(pin_num == 0) { - reg_value = GPIO_REG_GPLEN0(GPIO_BASE); - GPIO_REG_GPLEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPLEN0(gpio_base_addr); + GPIO_REG_GPLEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); } else { - reg_value = GPIO_REG_GPLEN1(GPIO_BASE); - GPIO_REG_GPLEN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPLEN1(gpio_base_addr); + GPIO_REG_GPLEN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); } break; } @@ -357,30 +358,30 @@ static void gpio_irq_handler(int irq, void *param) if(irq == IRQ_GPIO0) { /* 0~27 */ - value = GPIO_REG_GPEDS0(GPIO_BASE); + value = GPIO_REG_GPEDS0(gpio_base_addr); value &= 0x0fffffff; pin = 0; - GPIO_REG_GPEDS0(GPIO_BASE) = value; + GPIO_REG_GPEDS0(gpio_base_addr) = value; } else if(irq == IRQ_GPIO1) { /* 28-45 */ - tmpvalue = GPIO_REG_GPEDS0(GPIO_BASE); + tmpvalue = GPIO_REG_GPEDS0(gpio_base_addr); tmpvalue &= (~0x0fffffff); - GPIO_REG_GPEDS0(GPIO_BASE) = tmpvalue; + GPIO_REG_GPEDS0(gpio_base_addr) = tmpvalue; - value = GPIO_REG_GPEDS1(GPIO_BASE); + value = GPIO_REG_GPEDS1(gpio_base_addr); value &= 0x3fff; - GPIO_REG_GPEDS1(GPIO_BASE) = value; + GPIO_REG_GPEDS1(gpio_base_addr) = value; value = (value) | tmpvalue; pin = 28; } else if (irq == IRQ_GPIO2) { /* 46-53 */ - value = GPIO_REG_GPEDS1(GPIO_BASE); + value = GPIO_REG_GPEDS1(gpio_base_addr); value &= (~0x3fff); - GPIO_REG_GPEDS1(GPIO_BASE) = value; + GPIO_REG_GPEDS1(gpio_base_addr) = value; pin = 46; } @@ -405,23 +406,23 @@ int rt_hw_gpio_init(void) rt_device_pin_register("gpio", &ops, RT_NULL); //disable all intr - GPIO_REG_GPEDS0(GPIO_BASE) = 0xffffffff; - GPIO_REG_GPEDS1(GPIO_BASE) = 0xffffffff; + GPIO_REG_GPEDS0(gpio_base_addr) = 0xffffffff; + GPIO_REG_GPEDS1(gpio_base_addr) = 0xffffffff; - GPIO_REG_GPREN0(GPIO_BASE) = 0x0; - GPIO_REG_GPREN1(GPIO_BASE) = 0x0; + GPIO_REG_GPREN0(gpio_base_addr) = 0x0; + GPIO_REG_GPREN1(gpio_base_addr) = 0x0; - GPIO_REG_GPFEN0(GPIO_BASE) = 0x0; - GPIO_REG_GPFEN1(GPIO_BASE) = 0x0; + GPIO_REG_GPFEN0(gpio_base_addr) = 0x0; + GPIO_REG_GPFEN1(gpio_base_addr) = 0x0; - GPIO_REG_GPHEN0(GPIO_BASE) = 0x0; - GPIO_REG_GPHEN1(GPIO_BASE) = 0x0; + GPIO_REG_GPHEN0(gpio_base_addr) = 0x0; + GPIO_REG_GPHEN1(gpio_base_addr) = 0x0; - GPIO_REG_GPAREN0(GPIO_BASE) = 0x0; - GPIO_REG_GPAREN1(GPIO_BASE) = 0x0; + GPIO_REG_GPAREN0(gpio_base_addr) = 0x0; + GPIO_REG_GPAREN1(gpio_base_addr) = 0x0; - GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0; - GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0; + GPIO_REG_GPAFEN0(gpio_base_addr) = 0x0; + GPIO_REG_GPAFEN0(gpio_base_addr) = 0x0; rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq"); rt_hw_interrupt_umask(IRQ_GPIO0); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c index 8d34f3ab739dda30a3794b78fd8703e45843151f..9d4824e310d9233f3bed3f1e8d5b301bb16b2388 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c @@ -103,8 +103,8 @@ rt_err_t sd_int(struct sdhci_pdata_t * pdat, rt_uint32_t mask) { write32(pdat->virt + EMMC_INTERRUPT, r); //qemu maybe can not use sdcard - //rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS)); - //return -RT_ETIMEOUT; + rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS)); + return -RT_ETIMEOUT; } else if (r & INT_ERROR_MASK) { @@ -552,9 +552,8 @@ static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat) // Clear control2 write32(pdat->virt + EMMC_CONTROL2, 0); - - // Get the base clock rate - mmc_base_clock = bcm271x_mbox_clock_get_rate(12); + // Get the base clock rate //12 + mmc_base_clock = bcm271x_mbox_clock_get_rate(EMMC_CLK_ID); if(mmc_base_clock == 0) { rt_kprintf("EMMC: assuming clock rate to be 100MHz\n"); @@ -590,7 +589,6 @@ int raspi_sdmmc_init(void) struct rt_mmcsd_host * host = RT_NULL; struct sdhci_pdata_t * pdat = RT_NULL; struct sdhci_t * sdhci = RT_NULL; - #ifdef BSP_USING_SDIO0 host = mmcsd_alloc_host(); if (!host) @@ -598,7 +596,6 @@ int raspi_sdmmc_init(void) rt_kprintf("alloc host failed"); goto err; } - sdhci = rt_malloc(sizeof(struct sdhci_t)); if (!sdhci) { @@ -607,18 +604,16 @@ int raspi_sdmmc_init(void) } rt_memset(sdhci, 0, sizeof(struct sdhci_t)); - virt = MMC2_BASE_ADDR; - + virt = mmc2_base_addr; pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t)); RT_ASSERT(pdat != RT_NULL); pdat->virt = (rt_uint32_t)virt; reset_emmc(pdat); - sdhci->name = "sd0"; sdhci->voltages = VDD_33_34; sdhci->width = MMCSD_BUSWIDTH_4; - sdhci->clock = 250 * 1000 * 1000; + sdhci->clock = 1000 * 1000 * 1000; sdhci->removeable = RT_TRUE; sdhci->detect = sdhci_detect; @@ -634,10 +629,9 @@ int raspi_sdmmc_init(void) host->max_seg_size = 2048; host->max_dma_segs = 10; host->max_blk_size = 512; - host->max_blk_count = 4096; + host->max_blk_count = 1; host->private_data = sdhci; - write32((pdat->virt + EMMC_IRPT_EN),0xffffffff); write32((pdat->virt + EMMC_IRPT_MASK),0xffffffff); #ifdef RT_MMCSD_DBG diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c index 90ea26f7ab6715cb589a1337f5955612b0548c78..d072869048fac5dd2d4c874f512e08cb6805b1a3 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c @@ -14,7 +14,7 @@ #include "raspi4.h" #include "drv_spi.h" -#ifdef RT_USING_SPI +#ifdef BSP_USING_SPI #define RPI_CORE_CLK_HZ (250000000) #define BSP_SPI_MAX_HZ (30* 1000 *1000) diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c index ae61d8422437f72bc5027b70f6d233c6ca9681f0..e0b849c34dd3b4f4e7ca76c67ad0f098b5ef31c7 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c @@ -16,6 +16,12 @@ #include "board.h" #include "drv_uart.h" #include "drv_gpio.h" +#include + +size_t uart0_addr = 0; +size_t uart3_addr = 0; +size_t uart4_addr = 0; +size_t uart5_addr = 0; #ifdef RT_USING_UART0 static struct rt_serial_device _serial0; @@ -68,25 +74,25 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co return RT_EOK; } - if(uart->hw_base == UART0_BASE) + if(uart->hw_base == uart0_addr) { prev_raspi_pin_mode(GPIO_PIN_14, ALT0); prev_raspi_pin_mode(GPIO_PIN_15, ALT0); } - if(uart->hw_base == UART3_BASE) + if(uart->hw_base == uart3_addr) { prev_raspi_pin_mode(GPIO_PIN_4, ALT4); prev_raspi_pin_mode(GPIO_PIN_5, ALT4); } - if(uart->hw_base == UART4_BASE) + if(uart->hw_base == uart4_addr) { prev_raspi_pin_mode(GPIO_PIN_8, ALT4); prev_raspi_pin_mode(GPIO_PIN_9, ALT4); } - if(uart->hw_base == UART5_BASE) + if(uart->hw_base == uart5_addr) { prev_raspi_pin_mode(GPIO_PIN_12, ALT4); prev_raspi_pin_mode(GPIO_PIN_13, ALT4); @@ -108,20 +114,9 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg RT_ASSERT(serial != RT_NULL); uart = (struct hw_uart_device *)serial->parent.user_data; - switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - if(uart->hw_base == AUX_BASE) - { - AUX_MU_IER_REG(uart->hw_base) = 0x0; - } - else - { - PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM); - } - rt_hw_interrupt_mask(uart->irqno); break; case RT_DEVICE_CTRL_SET_INT: @@ -143,7 +138,6 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg static int uart_putc(struct rt_serial_device *serial, char c) { struct hw_uart_device *uart; - RT_ASSERT(serial != RT_NULL); uart = (struct hw_uart_device *)serial->parent.user_data; if(uart->hw_base == AUX_BASE) @@ -208,7 +202,7 @@ static void rt_hw_uart_isr(int irqno, void *param) { PACTL_CS &= ~(IRQ_UART0); rt_hw_serial_isr(&_serial0, RT_SERIAL_EVENT_RX_IND); - PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE; + PL011_REG_ICR(uart0_addr) = PL011_INTERRUPT_RECEIVE; } #endif @@ -217,7 +211,7 @@ static void rt_hw_uart_isr(int irqno, void *param) { PACTL_CS &= ~(IRQ_UART3); rt_hw_serial_isr(&_serial3, RT_SERIAL_EVENT_RX_IND); - PL011_REG_ICR(UART3_BASE) = PL011_INTERRUPT_RECEIVE; + PL011_REG_ICR(uart3_addr) = PL011_INTERRUPT_RECEIVE; } #endif @@ -226,7 +220,7 @@ static void rt_hw_uart_isr(int irqno, void *param) { PACTL_CS &= ~(IRQ_UART4); rt_hw_serial_isr(&_serial4, RT_SERIAL_EVENT_RX_IND); - PL011_REG_ICR(UART4_BASE) = PL011_INTERRUPT_RECEIVE; + PL011_REG_ICR(uart4_addr) = PL011_INTERRUPT_RECEIVE; } #endif @@ -235,7 +229,7 @@ static void rt_hw_uart_isr(int irqno, void *param) { PACTL_CS &= ~(IRQ_UART5); rt_hw_serial_isr(&_serial5, RT_SERIAL_EVENT_RX_IND); - PL011_REG_ICR(UART5_BASE) = PL011_INTERRUPT_RECEIVE; + PL011_REG_ICR(uart5_addr) = PL011_INTERRUPT_RECEIVE; } #endif } @@ -292,11 +286,16 @@ int rt_hw_uart_init(void) _serial0.ops = &_uart_ops; _serial0.config = config; + uart0_addr = (size_t)rt_ioremap((void*)UART0_BASE, 0x1000); + uart0->hw_base = uart0_addr; + + /* register UART0 device */ rt_hw_serial_register(&_serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart0); rt_hw_interrupt_install(uart0->irqno, rt_hw_uart_isr, &_serial0, "uart0"); + #endif #ifdef RT_USING_UART1 @@ -305,6 +304,8 @@ int rt_hw_uart_init(void) _serial1.ops = &_uart_ops; _serial1.config = config; + + uart1->hw_base = (size_t)rt_ioremap((void*)AUX_BASE, 0x1000); /* register UART1 device */ rt_hw_serial_register(&_serial1, "uart1", @@ -320,6 +321,9 @@ int rt_hw_uart_init(void) _serial3.ops = &_uart_ops; _serial3.config = config; + uart3_addr = (size_t)rt_ioremap((void*)UART3_BASE, 0x1000); + uart3->hw_base = uart3_addr; + /* register UART3 device */ rt_hw_serial_register(&_serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, @@ -334,6 +338,9 @@ int rt_hw_uart_init(void) _serial4.ops = &_uart_ops; _serial4.config = config; + uart4_addr = (size_t)rt_ioremap((void*)UART4_BASE, 0x1000); + uart4->hw_base = uart4_addr; + /* register UART4 device */ rt_hw_serial_register(&_serial4, "uart4", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, @@ -348,6 +355,9 @@ int rt_hw_uart_init(void) _serial5.ops = &_uart_ops; _serial5.config = config; + uart5_addr = (size_t)rt_ioremap((void*)UART5_BASE, 0x1000); + uart5->hw_base = uart5_addr; + /* register UART5 device */ rt_hw_serial_register(&_serial5, "uart5", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, @@ -356,3 +366,4 @@ int rt_hw_uart_init(void) #endif return 0; } + diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.c b/bsp/raspberry-pi/raspi4-32/driver/mbox.c index b0c79e09bd7e676c073b73738b360a4b4482ade5..177b043a8a22cb8c11c8044e62e9d4adef856f90 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/mbox.c +++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.c @@ -11,18 +11,20 @@ */ /* mailbox message buffer */ +#include #include "mbox.h" #include "mmu.h" //volatile unsigned int __attribute__((aligned(16))) mbox[36]; -volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR; + #define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) +volatile unsigned int *mbox; /** * Make a mailbox call. Returns 0 on failure, non-zero on success */ int mbox_call(unsigned char ch, int mmu_enable) { - unsigned int r = (((MBOX_ADDR)&~0xF) | (ch&0xF)); + unsigned int r = ((((rt_uint32_t)MBOX_ADDR)&~0xF) | (ch&0xF)); if(mmu_enable) r = BUS_ADDRESS(r); /* wait until we can write to the mailbox */ diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.h b/bsp/raspberry-pi/raspi4-32/driver/mbox.h index ec31370f6bb40cd11de0cf8e3481c83d738f2279..eae6572503d6ade713b59dcae09b2d9cf318345b 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/mbox.h +++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.h @@ -40,12 +40,13 @@ extern volatile unsigned int* mbox; #define MMIO_BASE 0xFE000000 #define VIDEOCORE_MBOX (MMIO_BASE+0x0000B880) -#define MBOX_READ ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0)) -#define MBOX_POLL ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10)) -#define MBOX_SENDER ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14)) -#define MBOX_STATUS ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18)) -#define MBOX_CONFIG ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C)) -#define MBOX_WRITE ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20)) +extern uint32_t videocore_mbox; +#define MBOX_READ ((volatile unsigned int*)(videocore_mbox+0x0)) +#define MBOX_POLL ((volatile unsigned int*)(videocore_mbox+0x10)) +#define MBOX_SENDER ((volatile unsigned int*)(videocore_mbox+0x14)) +#define MBOX_STATUS ((volatile unsigned int*)(videocore_mbox+0x18)) +#define MBOX_CONFIG ((volatile unsigned int*)(videocore_mbox+0x1C)) +#define MBOX_WRITE ((volatile unsigned int*)(videocore_mbox+0x20)) #define MBOX_RESPONSE 0x80000000 #define MBOX_FULL 0x80000000 #define MBOX_EMPTY 0x40000000 @@ -133,6 +134,19 @@ enum { #define MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 #define MBOX_ADDR 0x08000000 +extern uint32_t mbox_addr; + +#define RES_CLK_ID (0x000000000) +#define EMMC_CLK_ID (0x000000001) +#define UART_CLK_ID (0x000000002) +#define ARM_CLK_ID (0x000000003) +#define CORE_CLK_ID (0x000000004) +#define V3D_CLK_ID (0x000000005) +#define H264_CLK_ID (0x000000006) +#define ISP_CLK_ID (0x000000007) +#define SDRAM_CLK_ID (0x000000008) +#define PIXEL_CLK_ID (0x000000009) +#define PWM_CLK_ID (0x00000000a) int mbox_call(unsigned char ch, int mmu_enable); int bcm271x_notify_reboot(void); diff --git a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h index 5a91796d403103c5a110410cbdf4bd3e36df6618..be46bfd9589a29b2c50b75519ac6232349879754 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h +++ b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h @@ -1,5 +1,6 @@ #ifndef __RASPI4_H__ #define __RASPI4_H__ + //https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/rpi_DATA_2711_1p0.pdf #define __REG32(x) (*((volatile unsigned int *)(x))) @@ -14,6 +15,8 @@ //gpio offset #define GPIO_BASE_OFFSET (0x00200000) + +#define PL011_UART_BASE_OFFSET (0x00201000) //pl011 offset #define PL011_UART0_BASE_OFFSET (0x00201000) #define PL011_UART2_BASE_OFFSET (0x00201400) @@ -28,7 +31,9 @@ #define AUX_BASE_OFFSET (0x00215000) /* GPIO */ -#define GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET) +#define GPIO_BASE_ADDR (PER_BASE + GPIO_BASE_OFFSET) +extern uint32_t gpio_base_addr; +#define GPIO_BASE (gpio_base_addr) #define GPIO_IRQ_NUM (3) //40 pin mode #define IRQ_GPIO0 (96 + 49) //bank0 (0 to 27) #define IRQ_GPIO1 (96 + 50) //bank1 (28 to 45) @@ -37,45 +42,43 @@ /* Timer (ARM side) */ #define ARM_TIMER_IRQ (64) +extern uint32_t arm_timer_base; #define ARM_TIMER_BASE (PER_BASE + 0xB000) -#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400) -#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404) -#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408) -#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C) -#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410) -#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414) -#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418) -#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C) -#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420) +#define ARM_TIMER_LOAD HWREG32(arm_timer_base + 0x400) +#define ARM_TIMER_VALUE HWREG32(arm_timer_base + 0x404) +#define ARM_TIMER_CTRL HWREG32(arm_timer_base + 0x408) +#define ARM_TIMER_IRQCLR HWREG32(arm_timer_base + 0x40C) +#define ARM_TIMER_RAWIRQ HWREG32(arm_timer_base + 0x410) +#define ARM_TIMER_MASKIRQ HWREG32(arm_timer_base + 0x414) +#define ARM_TIMER_RELOAD HWREG32(arm_timer_base + 0x418) +#define ARM_TIMER_PREDIV HWREG32(arm_timer_base + 0x41C) +#define ARM_TIMER_CNTR HWREG32(arm_timer_base + 0x420) /* UART PL011 */ -#define UART0_BASE (PER_BASE + PL011_UART0_BASE_OFFSET) -#define UART2_BASE (PER_BASE + PL011_UART2_BASE_OFFSET) -#define UART3_BASE (PER_BASE + PL011_UART3_BASE_OFFSET) -#define UART4_BASE (PER_BASE + PL011_UART4_BASE_OFFSET) -#define UART5_BASE (PER_BASE + PL011_UART5_BASE_OFFSET) +#define UART_BASE (PER_BASE + PL011_UART_BASE_OFFSET) +//extern uint32_t uart_base_addr; +#define UART0_BASE (UART_BASE + 0x0) +#define UART2_BASE (UART_BASE + 0x400) +#define UART3_BASE (UART_BASE + 0x600) +#define UART4_BASE (UART_BASE + 0x800) +#define UART5_BASE (UART_BASE + 0xA00) #define IRQ_AUX_UART (96 + 29) #define UART_REFERENCE_CLOCK (48000000) /* AUX */ +//#define AUX_BASE_ADDR (PER_BASE + AUX_BASE_OFFSET) +//extern uint32_t aux_addr; +//#define AUX_BASE (aux_addr + 0x0) + #define AUX_BASE (PER_BASE + AUX_BASE_OFFSET) #define IRQ_PL011 (96 + 57) -/* SPI */ -#define SPI_0_BASE_OFFSET (0x00204000) -#define SPI_3_BASE_OFFSET (0x00204600) -#define SPI_4_BASE_OFFSET (0x00204800) -#define SPI_5_BASE_OFFSET (0x00204A00) -#define SPI_6_BASE_OFFSET (0x00204C00) - -#define SPI_0_BASE (PER_BASE + SPI_0_BASE_OFFSET) -#define SPI_3_BASE (PER_BASE + SPI_3_BASE_OFFSET) -#define SPI_4_BASE (PER_BASE + SPI_4_BASE_OFFSET) -#define SPI_5_BASE (PER_BASE + SPI_5_BASE_OFFSET) -#define SPI_6_BASE (PER_BASE + SPI_6_BASE_OFFSET) /* Peripheral IRQ OR-ing */ -#define PACTL_CS HWREG32((PER_BASE + PACTL_CS_OFFSET)) -typedef enum { +#define PACTL_CS_ADDR (PER_BASE + PACTL_CS_OFFSET) +extern uint32_t pactl_cs_base; +#define PACTL_CS HWREG32(pactl_cs_base) +typedef enum +{ IRQ_SPI0 = 0x00000000, IRQ_SPI1 = 0x00000002, IRQ_SPI2 = 0x00000004, @@ -107,10 +110,12 @@ typedef enum { #define INTC_BASE (0xff800000) #define ARM_GIC_NR_IRQS (512) #define ARM_GIC_MAX_NR (512) -#define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000) -#define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000) -#define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000) -#define GIC_V2_VIRTUAL_CPU_BASE (INTC_BASE + 0x00046000) +#define GIC_V2_BASE (INTC_BASE + 0x00040000) +extern uint32_t gic_base_addr; +#define GIC_V2_DISTRIBUTOR_BASE (gic_base_addr + 0x1000) +#define GIC_V2_CPU_INTERFACE_BASE (gic_base_addr + 0x2000) +#define GIC_V2_HYPERVISOR_BASE (gic_base_addr + 0x4000) +#define GIC_V2_VIRTUAL_CPU_BASE (gic_base_addr + 0x6000) #define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE #define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE @@ -119,10 +124,13 @@ typedef enum { #define GIC_ACK_INTID_MASK 0x000003ff + //watchdog -#define PM_RSTC HWREG32(PER_BASE + 0x0010001c) -#define PM_RSTS HWREG32(PER_BASE + 0x00100020) -#define PM_WDOG HWREG32(PER_BASE + 0x00100024) +#define WDT_BASE (PER_BASE + 0x00100000) +extern uint32_t wdt_base_addr; +#define PM_RSTC HWREG32(wdt_base_addr + 0x1c) +#define PM_RSTS HWREG32(wdt_base_addr + 0x20) +#define PM_WDOG HWREG32(wdt_base_addr + 0x24) #define PM_PASSWORD (0x5A000000) #define PM_WDOG_TIME_SET (0x000fffff) @@ -134,23 +142,38 @@ typedef enum { //timer #define ST_BASE_OFFSET (0x003000) #define STIMER_BASE (PER_BASE + ST_BASE_OFFSET) -#define STIMER_CS __REG32(STIMER_BASE + 0x0000) -#define STIMER_CLO __REG32(STIMER_BASE + 0x0004) -#define STIMER_CHI __REG32(STIMER_BASE + 0x0008) -#define STIMER_C0 __REG32(STIMER_BASE + 0x000C) -#define STIMER_C1 __REG32(STIMER_BASE + 0x0010) -#define STIMER_C2 __REG32(STIMER_BASE + 0x0014) -#define STIMER_C3 __REG32(STIMER_BASE + 0x0018) - -#define DELAY_MICROS(micros) \ - do{ \ - rt_uint32_t compare = STIMER_CLO + micros * 25; \ - while (STIMER_CLO < compare); \ - } while (0) \ +extern uint32_t stimer_base_addr; +#define STIMER_CS __REG32(stimer_base_addr + 0x0000) +#define STIMER_CLO __REG32(stimer_base_addr + 0x0004) +#define STIMER_CHI __REG32(stimer_base_addr + 0x0008) +#define STIMER_C0 __REG32(stimer_base_addr + 0x000C) +#define STIMER_C1 __REG32(stimer_base_addr + 0x0010) +#define STIMER_C2 __REG32(stimer_base_addr + 0x0014) +#define STIMER_C3 __REG32(stimer_base_addr + 0x0018) + +#define DELAY_MICROS(micros) \ + do{ \ + rt_uint32_t compare = STIMER_CLO + micros * 25; \ + while (STIMER_CLO < compare); \ + } while (0) //External Mass Media Controller (SD Card) -#define MMC0_BASE_ADDR (PER_BASE+0x300000) -#define MMC2_BASE_ADDR (PER_BASE+0x340000) +#define MMC0_BASE_ADDR (PER_BASE+0x300000) +extern uint32_t mmc0_base_addr; +#define MMC2_BASE_ADDR (PER_BASE+0x340000) +extern uint32_t mmc2_base_addr; + +//mac +#define MAC_REG (void *)(0xfd580000) +extern uint8_t * mac_reg_base_addr; + +#define ETH_IRQ (160+29) + +#define SEND_DATA_NO_CACHE (0x08200000) +extern uint8_t * eth_send_no_cache; + +#define RECV_DATA_NO_CACHE (0x08400000) +extern uint8_t * eth_recv_no_cache; /* the basic constants and interfaces needed by gic */ rt_inline rt_uint32_t platform_get_gic_dist_base(void) @@ -163,9 +186,4 @@ rt_inline rt_uint32_t platform_get_gic_cpu_base(void) return GIC_PL400_CONTROLLER_PPTR; } -static inline void __DSB(void) -{ - __asm__ volatile ("dsb 0xF":::"memory"); -} - #endif diff --git a/bsp/raspberry-pi/raspi4-32/link.lds b/bsp/raspberry-pi/raspi4-32/link.lds index 3f2f8ca413034e705b3f44d0629a1e36f0acad30..23b99f0c39019ca189e435baa266605750dd8278 100644 --- a/bsp/raspberry-pi/raspi4-32/link.lds +++ b/bsp/raspberry-pi/raspi4-32/link.lds @@ -24,7 +24,7 @@ SECTIONS { - . = 0x8000; + . = 0xc0000000; . = ALIGN(4096); .text : { @@ -63,6 +63,12 @@ SECTIONS _etext = .; } + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + .eh_frame_hdr : { *(.eh_frame_hdr) diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.h b/bsp/raspberry-pi/raspi4-32/rtconfig.h index 1edd99a54929a43d464e99ae22a9426f59f8ec2c..4d9c88360046ec88bd23e067a081034fd672e322 100644 --- a/bsp/raspberry-pi/raspi4-32/rtconfig.h +++ b/bsp/raspberry-pi/raspi4-32/rtconfig.h @@ -7,19 +7,21 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 +#define RT_USING_SMART #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 2048 +#define IDLE_THREAD_STACK_SIZE 4096 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 2048 +#define RT_TIMER_THREAD_STACK_SIZE 512 #define RT_DEBUG +#define RT_DEBUG_COLOR /* Inter-Thread communication */ @@ -32,16 +34,26 @@ /* Memory Management */ #define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP #define RT_USING_SMALL_MEM #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE +#define RT_USING_INTERRUPT_INFO #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 512 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define ARCH_ARM +#define ARCH_ARM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0xc0000000 +#define PV_OFFSET 0x40100000 +#define RT_IOREMAP_LATE +#define ARCH_ARM_CORTEX_A #define ARCH_ARMV8 /* RT-Thread Components */ @@ -57,6 +69,7 @@ /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH #define FINSH_THREAD_NAME "tshell" #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -65,16 +78,14 @@ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT #define FINSH_ARG_MAX 10 /* Device virtual file system */ #define RT_USING_DFS #define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 #define DFS_FD_MAX 16 #define RT_USING_DFS_ELMFAT @@ -89,15 +100,26 @@ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_DFS_ELM_REENTRANT #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL -#define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_HWTIMER +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS #define RT_USING_PIN +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_RTC +#define RT_USING_SOFT_RTC #define RT_USING_SDIO #define RT_SDIO_STACK_SIZE 512 #define RT_SDIO_THREAD_PRIORITY 15 @@ -113,12 +135,23 @@ /* POSIX layer and C standard library */ #define RT_USING_LIBC +#define RT_USING_MUSL #define RT_USING_POSIX +#define RT_USING_POSIX_MMAP +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_AIO +#define RT_USING_POSIX_CLOCKTIME /* Network */ /* Socket abstraction layer */ +#define RT_USING_SAL + +/* protocol stack implement */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX /* Network interface device */ @@ -127,13 +160,15 @@ #define NETDEV_USING_PING #define NETDEV_USING_NETSTAT #define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_USING_IPV6 #define NETDEV_IPV4 1 -#define NETDEV_IPV6 0 +#define NETDEV_IPV6 1 /* light weight TCP/IP stack */ #define RT_USING_LWIP #define RT_USING_LWIP202 +#define RT_USING_LWIP_IPV6 #define RT_LWIP_MEM_ALIGNMENT 4 #define RT_LWIP_IGMP #define RT_LWIP_ICMP @@ -144,26 +179,27 @@ /* Static IPv4 Address */ -#define RT_LWIP_IPADDR "192.168.1.30" -#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_IPADDR "192.168.137.100" +#define RT_LWIP_GWADDR "192.168.137.1" #define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP #define RT_LWIP_TCP #define RT_LWIP_RAW -#define RT_MEMP_NUM_NETCONN 8 +#define RT_MEMP_NUM_NETCONN 16 #define RT_LWIP_PBUF_NUM 16 #define RT_LWIP_RAW_PCB_NUM 4 -#define RT_LWIP_UDP_PCB_NUM 4 -#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 8 +#define RT_LWIP_TCP_PCB_NUM 8 #define RT_LWIP_TCP_SEG_NUM 40 #define RT_LWIP_TCP_SND_BUF 8196 #define RT_LWIP_TCP_WND 8196 #define RT_LWIP_TCPTHREAD_PRIORITY 10 #define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 #define RT_LWIP_ETHTHREAD_PRIORITY 12 -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_STACKSIZE 4096 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_REASSEMBLY_FRAG #define LWIP_NETIF_STATUS_CALLBACK 1 #define LWIP_NETIF_LINK_CALLBACK 1 #define SO_REUSE 1 @@ -182,6 +218,13 @@ /* Utilities */ +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define RT_LWP_SHM_MAX_NR 64 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 /* RT-Thread online packages */ @@ -214,19 +257,22 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ -/* miscellaneous packages */ +/* AI packages */ -/* samples: kernel and components samples */ +/* miscellaneous packages */ -/* Privated Packages of RealThread */ +/* samples: kernel and components samples */ -/* Network Utilities */ +/* entertainment: terminal games and other interesting software packages */ #define BCM2711_SOC @@ -241,9 +287,6 @@ #define BSP_USING_GIC #define BSP_USING_GIC400 #define BSP_USING_PIN -#define BSP_USING_SPI -#define BSP_USING_SPI0_BUS -#define BSP_USING_SPI0_DEVICE0 #define BSP_USING_CORETIMER #define BSP_USING_WDT #define BSP_USING_SDIO @@ -252,6 +295,5 @@ /* Board Peripheral Drivers */ #define BSP_USING_HDMI -#define BSP_USING_HDMI_DISPLAY #endif diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.py b/bsp/raspberry-pi/raspi4-32/rtconfig.py index 681ec91b9e6702014cd0e758322166839f7a63c0..7feaeee4d9c8c2441ef4d128ee4a3bdfb2006dc5 100644 --- a/bsp/raspberry-pi/raspi4-32/rtconfig.py +++ b/bsp/raspberry-pi/raspi4-32/rtconfig.py @@ -3,28 +3,16 @@ import os # toolchains options ARCH ='arm' CPU ='cortex-a' -CROSS_TOOL ='gcc' - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = r'../../..' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - +RTT_ROOT = os.getenv('RTT_ROOT') or r'../../..' +CROSS_TOOL = os.getenv('RTT_CC') or 'gcc' PLATFORM = 'gcc' -EXEC_PATH = r'/usr/bin' - -BUILD = 'debug' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') +EXEC_PATH = os.getenv('RTT_EXEC_PATH') or r'/opt/gcc-arm-none-eabi-5_4-2016q3/bin/' +BUILD = os.getenv('RTT_BUILD') or 'debug' if PLATFORM == 'gcc': # toolchains # PREFIX = 'arm-none-eabi-' - PREFIX = 'arm-none-eabi-' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-' CC = PREFIX + 'gcc' CXX = PREFIX + 'g++' AS = PREFIX + 'gcc' @@ -35,20 +23,22 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -march=armv8-a -mtune=cortex-a72' - CFLAGS = DEVICE + ' -Wall' + DEVICE = ' -march=armv8-a -mtune=cortex-a72 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' + CXXFLAGS= DEVICE + ' -Wall' + CFLAGS = DEVICE + ' -Wall -std=gnu99' AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' - LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds ' + ' -lsupc++ -lgcc ' CPATH = '' LPATH = '' if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0 -gdwarf-2' + CXXFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS + CFLAGS += ' -Os' + CXXFLAGS += ' -Os' + CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti' DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n' diff --git a/bsp/raspberry-pi/raspi4-64/.config b/bsp/raspberry-pi/raspi4-64/.config index 0ab68e8fe393a353ef54c1eb9c651b41556a9b09..39180551f5d894369ccfd45da75cb0df239ba222 100644 --- a/bsp/raspberry-pi/raspi4-64/.config +++ b/bsp/raspberry-pi/raspi4-64/.config @@ -8,23 +8,24 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=2048 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set +CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set # CONFIG_RT_DEBUG_THREAD_CONFIG is not set # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set @@ -50,10 +51,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_MEMHEAP=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -62,22 +64,27 @@ CONFIG_RT_USING_HEAP=y # CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" -CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_CONSOLEBUF_SIZE=512 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y # CONFIG_RT_USING_CPU_FFS is not set -CONFIG_ARCH_ARMV8=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0xffff000000000000 +CONFIG_PV_OFFSET=0x0001000000200000 +CONFIG_ARCH_ARMV8=y # # RT-Thread Components # CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 CONFIG_RT_MAIN_THREAD_PRIORITY=10 # @@ -89,6 +96,7 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 @@ -96,12 +104,9 @@ CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_THREAD_STACK_SIZE=8192 CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # @@ -109,40 +114,81 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_MNTTABLE is not set -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y -CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +CONFIG_RT_USING_SOFT_RTC=y +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=8192 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=8192 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set @@ -161,11 +207,16 @@ CONFIG_RT_USING_PIN=y # POSIX layer and C standard library # CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y # CONFIG_RT_USING_PTHREADS is not set CONFIG_RT_USING_POSIX=y -# CONFIG_RT_USING_POSIX_MMAP is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_USING_POSIX_MMAP=y +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_GETLINE is not set +CONFIG_RT_USING_POSIX_AIO=y +CONFIG_RT_POSIX_AIO_THREAD_STACK_SIZE=8192 +CONFIG_RT_USING_POSIX_CLOCKTIME=y # CONFIG_RT_USING_MODULE is not set # @@ -175,22 +226,90 @@ CONFIG_RT_USING_POSIX=y # # Socket abstraction layer # -# CONFIG_RT_USING_SAL is not set +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +CONFIG_SAL_USING_POSIX=y # # Network interface device # -# CONFIG_RT_USING_NETDEV is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set # # light weight TCP/IP stack # -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP212 is not set +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.137.100" +CONFIG_RT_LWIP_GWADDR="192.168.137.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=16 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=8 +CONFIG_RT_LWIP_TCP_PCB_NUM=8 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=8192 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_REASSEMBLY_FRAG=y +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set # # AT commands # # CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set # # VBUS(Virtual Software BUS) @@ -203,6 +322,15 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +# CONFIG_RT_USING_GDBSERVER is not set +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_RT_LWP_SHM_MAX_NR=64 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set # # RT-Thread online packages @@ -211,7 +339,9 @@ CONFIG_RT_USING_POSIX=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set @@ -257,7 +387,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -279,6 +409,12 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set # # security packages @@ -287,6 +423,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -303,6 +440,9 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -314,14 +454,26 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set # # system packages @@ -345,6 +497,27 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set # # peripheral libraries and drivers @@ -353,6 +526,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -382,6 +556,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set @@ -390,6 +565,21 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set # CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set # # miscellaneous packages @@ -399,6 +589,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -419,6 +610,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_NNOM is not set # CONFIG_PKG_USING_LIBANN is not set # CONFIG_PKG_USING_ELAPACK is not set @@ -426,6 +618,64 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_MDNS is not set +# CONFIG_PKG_USING_UPNP is not set +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set CONFIG_BCM2711_SOC=y # CONFIG_BSP_SUPPORT_FPU is not set @@ -438,17 +688,24 @@ CONFIG_BCM2711_SOC=y # CONFIG_BSP_USING_UART=y CONFIG_RT_USING_UART0=y +# CONFIG_RT_USING_UART1 is not set +CONFIG_RT_USING_UART3=y +CONFIG_RT_USING_UART4=y +# CONFIG_RT_USING_UART5 is not set CONFIG_BSP_USING_GIC=y CONFIG_BSP_USING_GIC400=y # CONFIG_BSP_USING_GIC500 is not set CONFIG_BSP_USING_PIN=y +# CONFIG_BSP_USING_SPI is not set CONFIG_BSP_USING_CORETIMER=y # CONFIG_BSP_USING_SYSTIMER is not set -# CONFIG_BSP_USING_WDT is not set +CONFIG_BSP_USING_WDT=y # CONFIG_BSP_USING_RTC is not set -# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDIO0=y # # Board Peripheral Drivers # -# CONFIG_BSP_USING_HDMI is not set +CONFIG_BSP_USING_HDMI=y +# CONFIG_BSP_USING_HDMI_DISPLAY is not set diff --git a/bsp/raspberry-pi/raspi4-64/Kconfig b/bsp/raspberry-pi/raspi4-64/Kconfig index c1ee600450f624c1df7fbb2cf7d842c87f038705..5b683102b23c1443141085c4bac6c334bbcc54b4 100644 --- a/bsp/raspberry-pi/raspi4-64/Kconfig +++ b/bsp/raspberry-pi/raspi4-64/Kconfig @@ -21,9 +21,11 @@ source "$PKGS_DIR/Kconfig" config BCM2711_SOC bool select ARCH_ARMV8 + select ARCH_CPU_64BIT + select RT_USING_CACHE + select ARCH_ARM_MMU select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN - select ARCH_CPU_64BIT default y -source "driver/Kconfig" +source "drivers/Kconfig" diff --git a/bsp/raspberry-pi/raspi4-64/README.md b/bsp/raspberry-pi/raspi4-64/README.md index b2456277b8a46c4fc63462bb90c6c1ad82fe4612..94eac22e670438fda538ead78a0834fac04bc0bb 100644 --- a/bsp/raspberry-pi/raspi4-64/README.md +++ b/bsp/raspberry-pi/raspi4-64/README.md @@ -11,88 +11,108 @@ ## 2. 编译说明 +推荐使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到`bsp\raspberry-pi\raspi4-32`目录中，运行以下命令： +``` +scons +``` -### 2.1 Window上的环境搭建 - -Windows环境下推荐使用[env工具](https://www.rt-thread.org/page/download.html)进行编译。 - -首先下载windows上的aarch64的gcc交叉编译工具，版本为gcc-arm-8.3选择aarch64-elf就可以。 +来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、kernel7.img文件。 -将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。 -接着修改`bsp\raspberry-pi\raspi4-64\rtconfig.py` +## 3. 环境搭建 +### 3.1 准备好串口线 -修改路径： +目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示： -``` -EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin' -``` +![raspi2](../raspi3-32/figures/raspberrypi-console.png) -然后在`bsp\raspberry-pi\raspi4-64\`下输入scons编译即可。 +串口参数： 115200 8N1 ，硬件和软件流控为关。 -**window环境搭建注意** +### 3.2 RTT固件放在SD卡运行 -下载完成`gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf.tar.xz`交叉编译工具链后，最好采用7-zip解压工具进行两次解压。 -确保解压目录下的`/bin/aarch64-elf-ld.exe`文件的size不为0。 -否则编译会出现如下错误: +首先需要准备一张空的32GB以下的SD卡，如果不想自己制作启动固件，可以直接从百度网盘上下载boot的固件。 ``` -collect2.exe:fatal error:CreateProcess:No such file or directory +链接：https://pan.baidu.com/s/1PxgvXAChUIOgueNXhgMs8w +提取码：pioj ``` -### 2.2 Linux上的环境搭建 +解压后将sd目录下的文件拷贝到sd卡即可。以后每次编译后，将生成的kernel7.img进行替换即可。上电后可以看到程序正常运行。 -Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。 +### 3.3 RTT程序用uboot加载 -将工具链解压到指定目录,并修改当前bsp下的`EXEC_PATH`为自定义gcc目录。 +为了调试方便，已经将uboot引导程序放入uboot目录下，直接将这些文件放到sd卡中即可。 -``` -PLATFORM = 'gcc' -EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' -``` +需要注意的以下步骤： -直接进入`bsp\raspberry-pi\raspi4-64`，输入scons编译即可。 +**1.电脑上启动tftp服务器** +windows系统电脑上可以安装tftpd搭建tftp服务器。将目录指定到`bsp\raspberry-pi\raspi4-32`。 -## 3. 执行 +**2.修改设置uboot** -### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡 +在控制台输入下列命令： -首先下载镜像 +``` +setenv bootcmd "dhcp 0x00200000 x.x.x.x:kernel7.img;dcache flush;go 0x00200000" +saveenv +reset +``` -* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb) -* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe) -* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg) +其中`x.x.x.x`为tftp服务器的pc的ip地址。 -### 3.2 准备好串口线 +**3.修改链接脚本** -目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示： +将树莓派`bsp\raspberry-pi\raspi4-32\link.ld`的文件链接地址改为`0x200000`。 -![raspi2](../raspi3-32/figures/raspberrypi-console.png) +``` +SECTIONS +{ + . = 0x8000; + . = ALIGN(4096); + . + . + . +} +``` -串口参数： 115200 8N1 ，硬件和软件流控为关。 +改为 -### 3.3 程序下载 +``` +SECTIONS +{ + . = 0x200000; + . = ALIGN(4096); + . + . + . +} +``` -当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下： +重新编译程序： ``` -enable_uart=1 -arm_64bit=1 -kernel=rtthread.bin -core_freq=250 +scons -c +scons ``` -按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息： +**3.插入网线** + +上述准备完成后，将网线插入，保证开发板和tftp服务器在同一个网段的路由器上。上电后uboot可以自动从tftp服务器上获取固件，然后开始执行了。 + +完成后可以看到串口的输出信息 -```text -heap: 0x000c9350 - 0x040c9350 +``` +heap: 0x000607e8 - 0x040607e8 \ | / - RT - Thread Operating System - / | \ 4.0.3 build Apr 16 2020 + / | \ 4.0.3 build Oct 27 2020 2006 - 2020 Copyright by rt-thread team +[I/SDIO] SD card capacity 31205376 KB. +found part[0], begin: 1048576, size: 29.777GB +file system initialization done! Hi, this is RT-Thread!! msh /> ``` @@ -101,9 +121,20 @@ msh /> | 驱动 | 支持情况 | 备注 | | ------ | ---- | :------: | -| UART | 支持 | UART0| +| UART | 支持 | UART0,UART2,UART3,UART4,UART5 | +| GPIO | 支持 | - | +| SPI | 支持 | SPI0 | +| MAILBOX | 支持 | - | +| WATCHDOG | 支持 | - | +| HDMI | 支持 | - | +| SDIO | 支持 | - | +| ETH | 支持 | - | + +## 5. 注意事项 + +目前rt-thread程序可以使用的内存在100MB以内，可以通过调整`board.c`中`platform_mem_desc`表的数据进行相关内存的映射以及修改`board.h`来确定程序使用的堆栈大小。目前在地址`0x08000000`处的1M空间被映射成非cache区供树莓派4的CPU与GPU通信的消息管道。若需要扩大系统内存使用，可自行修改代码进行调整。 -## 5. 联系人信息 +## 6. 联系人信息 维护人：[bernard][5] diff --git a/bsp/raspberry-pi/raspi4-64/SConstruct b/bsp/raspberry-pi/raspi4-64/SConstruct index 93f349aab8045ad3c742e72664514a7c240b2b6e..1e5eae0d35bab98fb21d3a49a48c4e57e15e45e4 100644 --- a/bsp/raspberry-pi/raspi4-64/SConstruct +++ b/bsp/raspberry-pi/raspi4-64/SConstruct @@ -2,7 +2,10 @@ import os import sys import rtconfig -from rtconfig import RTT_ROOT +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * @@ -11,20 +14,20 @@ TARGET = 'rtthread.' + rtconfig.TARGET_EXT DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' Export('RTT_ROOT') Export('rtconfig') # prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) +objs = PrepareBuilding(env, RTT_ROOT) # make a building DoBuilding(TARGET, objs) - diff --git a/bsp/raspberry-pi/raspi4-64/applications/main.c b/bsp/raspberry-pi/raspi4-64/applications/main.c index 9664e67d01d0e45ad84ec3aa9e3ee72edf26c950..26a2bf3ee7f75ebdb74c93965390251695ba5e6f 100644 --- a/bsp/raspberry-pi/raspi4-64/applications/main.c +++ b/bsp/raspberry-pi/raspi4-64/applications/main.c @@ -4,16 +4,14 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-04-16 bigmagic first version + * Date Author Notes + * 2017-5-30 bernard the first version */ - #include -#include -#include int main(int argc, char** argv) { - rt_kprintf("Hi, this is RT-Thread!!\n"); + rt_kprintf("hello rt-thread!\n"); + return 0; } diff --git a/bsp/raspberry-pi/raspi4-64/applications/mnt.c b/bsp/raspberry-pi/raspi4-64/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..215f810bbc559939cbcdb7b08cd4f393dacfcf2f --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/applications/mnt.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 bernard the first version + */ + +#include + +#ifdef BSP_USING_SDIO0 +#include + +int mnt_init(void) +{ + rt_thread_delay(RT_TICK_PER_SECOND); + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("%s %d\n", __FILE__, __LINE__); + rt_kprintf("file system initialization done!\n"); + } + + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif diff --git a/bsp/raspberry-pi/raspi4-64/driver/board.c b/bsp/raspberry-pi/raspi4-64/driver/board.c deleted file mode 100644 index 79a24d184f1c3b03f29e19c3caca55772661faab..0000000000000000000000000000000000000000 --- a/bsp/raspberry-pi/raspi4-64/driver/board.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-04-16 bigmagic first version - */ - -#include -#include - -#include "board.h" -#include "drv_uart.h" - -#include "cp15.h" -#include "mmu.h" - -static rt_uint64_t timerStep; - -int rt_hw_get_gtimer_frq(void); -void rt_hw_set_gtimer_val(rt_uint64_t value); -int rt_hw_get_gtimer_val(void); -int rt_hw_get_cntpct_val(void); -void rt_hw_gtimer_enable(void); - -void core0_timer_enable_interrupt_controller(void) -{ - CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ; -} - -void rt_hw_timer_isr(int vector, void *parameter) -{ - rt_hw_set_gtimer_val(timerStep); - rt_tick_increase(); -} - -void rt_hw_timer_init(void) -{ - rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_umask(TIMER_IRQ); - __ISB(); - timerStep = rt_hw_get_gtimer_frq(); - __DSB(); - timerStep /= RT_TICK_PER_SECOND; - - rt_hw_gtimer_enable(); - rt_hw_set_gtimer_val(timerStep); - core0_timer_enable_interrupt_controller(); -} - -void idle_wfi(void) -{ - asm volatile ("wfi"); -} - -/** - * Initialize the Hardware related stuffs. Called from rtthread_startup() - * after interrupt disabled. - */ -void rt_hw_board_init(void) -{ - mmu_init(); - armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY); - armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio - armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer - mmu_enable(); - - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device - rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors); - - /* initialize uart */ - rt_hw_uart_init(); // driver/drv_uart.c -#ifdef RT_USING_CONSOLE - /* set console device */ - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif /* RT_USING_CONSOLE */ - -#ifdef RT_USING_HEAP - /* initialize memory system */ - rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); -#endif - /* initialize timer for os tick */ - rt_hw_timer_init(); - rt_thread_idle_sethook(idle_wfi); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif -} diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c deleted file mode 100644 index bba20a86a436191d2fa450284c66b77cfae5d02f..0000000000000000000000000000000000000000 --- a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-04-16 bigmagic first version - */ - -#include "drv_gpio.h" - -#ifdef BSP_USING_PIN - -static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) -{ - uint32_t fselnum = pin / 10; - uint32_t fselrest = pin % 10; - - uint32_t gpfsel = 0; - gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3))); - gpfsel |= (uint32_t)(mode << (fselrest * 3)); - - switch (fselnum) - { - case 0: - GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel; - break; - case 1: - GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel; - break; - case 2: - GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel; - break; - case 3: - GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel; - break; - case 4: - GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel; - break; - case 5: - GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel; - break; - default: - break; - } -} - -static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) -{ - uint32_t num = pin / 32; - - if(num == 0) - { - if(value == 0) - { - GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32); - } - else - { - GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32); - } - } - else - { - if(value == 0) - { - GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32); - } - else - { - GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32); - } - - } -} - -static int raspi_pin_read(struct rt_device *device, rt_base_t pin) -{ - return 0; -} - -static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) -{ - return RT_EOK; -} - -static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin) -{ - return RT_EOK; -} - -rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) -{ - return RT_EOK; -} - -static const struct rt_pin_ops ops = -{ - raspi_pin_mode, - raspi_pin_write, - raspi_pin_read, - raspi_pin_attach_irq, - raspi_pin_detach_irq, - raspi_pin_irq_enable, - RT_NULL, -}; -#endif - -int rt_hw_gpio_init(void) -{ -#ifdef BSP_USING_PIN - rt_device_pin_register("gpio", &ops, RT_NULL); -#endif - - return 0; -} -INIT_DEVICE_EXPORT(rt_hw_gpio_init); diff --git a/bsp/raspberry-pi/raspi4-64/driver/raspi4.h b/bsp/raspberry-pi/raspi4-64/driver/raspi4.h deleted file mode 100644 index 3f1835390479ec152c1b1b4f2728454b2e9d1e1c..0000000000000000000000000000000000000000 --- a/bsp/raspberry-pi/raspi4-64/driver/raspi4.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __RASPI4_H__ -#define __RASPI4_H__ - -//gpio -#define GPIO_BASE (0xFE000000 + 0x00200000) - -//uart -#define UART0_BASE (0xFE000000 + 0x00201000) -#define PL011_BASE UART0_BASE -#define IRQ_PL011 (121 + 32) -#define UART_REFERENCE_CLOCK (48000000) - -// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control -#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040) -#define TIMER_IRQ 30 -#define NON_SECURE_TIMER_IRQ (1 << 1) - -//gic max -#define ARM_GIC_NR_IRQS (512) -#define INTC_BASE (0xff800000) -#define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000) -#define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000) -#define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000) -#define GIC_V2_VIRTUAL_CPU_BASE (INTC_BASE + 0x00046000) - -#define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE -#define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE - -#endif diff --git a/bsp/raspberry-pi/raspi4-64/driver/Kconfig b/bsp/raspberry-pi/raspi4-64/drivers/Kconfig similarity index 70% rename from bsp/raspberry-pi/raspi4-64/driver/Kconfig rename to bsp/raspberry-pi/raspi4-64/drivers/Kconfig index 208b4b43000a16ecb3a10c0f2edc1e9de1f1c76e..5dca313513f414da4293c9de58990412cee43bb9 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/Kconfig +++ b/bsp/raspberry-pi/raspi4-64/drivers/Kconfig @@ -14,6 +14,22 @@ menu "Hardware Drivers Config" config RT_USING_UART0 bool "Enabel UART 0" default y + + config RT_USING_UART1 + bool "Enabel UART 1" + default n + + config RT_USING_UART3 + bool "Enabel UART 3" + default n + + config RT_USING_UART4 + bool "Enabel UART 4" + default n + + config RT_USING_UART5 + bool "Enabel UART 5" + default n endif menuconfig BSP_USING_GIC @@ -34,6 +50,25 @@ menu "Hardware Drivers Config" select RT_USING_PIN default y + menuconfig BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default n + + if BSP_USING_SPI + config BSP_USING_SPI0_BUS + bool "Enable SPI0 BUS" + default n + config BSP_USING_SPI0_DEVICE0 + bool "Enable SPI0 DEVICE0" + select BSP_USING_SPI0_BUS + default n + config BSP_USING_SPI0_DEVICE1 + bool "Enable SPI0 DEVICE1" + select BSP_USING_SPI0_BUS + default n + endif + config BSP_USING_CORETIMER bool "Using core timer" select RT_USING_CORETIMER diff --git a/bsp/raspberry-pi/raspi4-64/drivers/SConscript b/bsp/raspberry-pi/raspi4-64/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..64c764c1b3b3fdde2a31dfa5e8622069b4bcbd85 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/SConscript @@ -0,0 +1,19 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH) + +# build for sub-directory +list = os.listdir(cwd) +objs = [] + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +group = group + objs + +Return('group') diff --git a/bsp/raspberry-pi/raspi4-64/drivers/board.c b/bsp/raspberry-pi/raspi4-64/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..6bc919595d78a8957191661bbb3f2169c6eb48ae --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/board.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#include "cp15.h" +#include "mmu.h" +#include "mbox.h" + +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +rt_mmu_info mmu_info; +extern size_t MMUTable[]; + +size_t gpio_base_addr = GPIO_BASE_ADDR; + +size_t uart_base_addr = UART_BASE; + +size_t gic_base_addr = GIC_V2_BASE; + +size_t arm_timer_base = ARM_TIMER_BASE; + +size_t pactl_cs_base = PACTL_CS_ADDR; + +size_t stimer_base_addr = STIMER_BASE; + +size_t mmc2_base_addr = MMC2_BASE_ADDR; + +size_t videocore_mbox = VIDEOCORE_MBOX; + +size_t mbox_addr = MBOX_ADDR; + +size_t wdt_base_addr = WDT_BASE; + +uint8_t *mac_reg_base_addr = (uint8_t *)MAC_REG; + +uint8_t *eth_send_no_cache = (uint8_t *)SEND_DATA_NO_CACHE; +uint8_t *eth_recv_no_cache = (uint8_t *)RECV_DATA_NO_CACHE; + +#ifdef RT_USING_USERSPACE +struct mem_desc platform_mem_desc[] = { + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0fffffff, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM} +}; +#else +struct mem_desc platform_mem_desc[] = { + {0x0, 0x6400000, 0x0, NORMAL_MEM}, + {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM},//uart gpio + {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic +}; +#endif + +const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); + +void rt_hw_timer_isr(int vector, void *parameter) +{ + ARM_TIMER_IRQCLR = 1; + rt_tick_increase(); +} + +void rt_hw_timer_init(void) +{ + rt_uint32_t apb_clock = 0; + rt_uint32_t timer_clock = 1000000; + + /* timer_clock = apb_clock/(pre_divider + 1) */ + apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID); + ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1); + + ARM_TIMER_CTRL = 0; + ARM_TIMER_IRQCLR = 1; + ARM_TIMER_RELOAD = 0; + ARM_TIMER_LOAD = 0; + + ARM_TIMER_RELOAD = 1000000/RT_TICK_PER_SECOND; + ARM_TIMER_LOAD = 1000000/RT_TICK_PER_SECOND; + + /* 23-bit counter, enable interrupt, enable timer */ + ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7); + + rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(ARM_TIMER_IRQ); +} + +void idle_wfi(void) +{ + //rt_ubase_t level; + asm volatile ("wfi"); + //level = rt_hw_interrupt_disable(); + //gic_dump(); + //rt_hw_interrupt_enable(level); +} + +/** + * This function will initialize board + */ + +rt_mmu_info mmu_info; + +extern size_t MMUTable[]; + +#ifdef RT_USING_USERSPACE +rt_region_t init_page_region = { + PAGE_START, + PAGE_END, +}; +#endif + +/** + * Initialize the Hardware related stuffs. Called from rtthread_startup() + * after interrupt disabled. + */ +void rt_hw_board_init(void) +{ + /* io device remap */ +#ifdef RT_USING_USERSPACE + rt_page_init(init_page_region); + rt_hw_mmu_setup(platform_mem_desc, platform_mem_desc_size); + + rt_hw_mmu_map_init(&mmu_info, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET); + + arch_kuser_init(&mmu_info, (void*)0xffffffffffff0000); +#else + rt_hw_mmu_map_init(&mmu_info, (void*)GPIO_BASE_ADDR, 0x10000000, MMUTable, 0); +#endif + /* map peripheral address to virtual address */ +#ifdef RT_USING_HEAP + /* initialize system heap */ + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + //gpio + gpio_base_addr = (size_t)rt_ioremap((void*)GPIO_BASE_ADDR, 0x1000); + //uart + //uart_base_addr = (size_t)rt_ioremap((void*)UART_BASE, 0x1000); + //aux + //aux_addr = (size_t)rt_ioremap((void*)AUX_BASE_ADDR, 0x1000); + //timer + arm_timer_base = (size_t)rt_ioremap((void*)ARM_TIMER_BASE, 0x1000); + //gic + //gic_base_addr = (size_t)rt_ioremap((void*)GIC_V2_BASE, 0x10000); + //pactl + pactl_cs_base = (size_t)rt_ioremap((void*)PACTL_CS_ADDR, 0x1000); + + //stimer + stimer_base_addr = (size_t)rt_ioremap((void*)STIMER_BASE, 0x1000); + + //mmc2_base_addr + mmc2_base_addr = (size_t)rt_ioremap((void*)MMC2_BASE_ADDR, 0x1000); + + //mbox + videocore_mbox = (size_t)rt_ioremap((void*)VIDEOCORE_MBOX, 0x1000); + + //mbox msg + mbox_addr = (size_t)rt_ioremap((void*)MBOX_ADDR, 0x1000); + mbox = (volatile unsigned int *)mbox_addr; + + //wdt + wdt_base_addr = (size_t)rt_ioremap((void*)WDT_BASE, 0x1000); + + //mac + mac_reg_base_addr = (void *)rt_ioremap((void*)MAC_REG, 0x80000); + + //eth data + eth_send_no_cache = (void *)rt_ioremap((void*)SEND_DATA_NO_CACHE, 0x200000); + eth_recv_no_cache = (void *)rt_ioremap((void*)RECV_DATA_NO_CACHE, 0x200000); + + /* initialize uart */ + rt_hw_uart_init(); + + /* initialize timer for os tick */ + rt_hw_timer_init(); + +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_CONSOLE */ + + rt_kprintf("heap: 0x%08x - 0x%08x\n", HEAP_BEGIN, HEAP_END); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + rt_thread_idle_sethook(idle_wfi); +} + +#ifdef RT_USING_GDBSERVER +#include + +#define GDB_CONNECT_DEVICE "/dev/uart4" + +/* for gdb */ +int gdb_com_open(void) +{ + return open(GDB_CONNECT_DEVICE, O_RDWR); +} + +void gdb_com_close(int fd) +{ + close(fd); +} + +ssize_t gdb_com_read(int fd, void *buff, size_t len) +{ + return read(fd, buff, len); +} + +ssize_t gdb_com_write(int fd, void *buff, size_t len) +{ + return write(fd, buff, len); +} + +#endif diff --git a/bsp/raspberry-pi/raspi4-64/driver/board.h b/bsp/raspberry-pi/raspi4-64/drivers/board.h similarity index 45% rename from bsp/raspberry-pi/raspi4-64/driver/board.h rename to bsp/raspberry-pi/raspi4-64/drivers/board.h index d675cc658e06c599df8007db4e67e608afa7a45a..64e79dc50a34400d94615cd816e0056aae391999 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/board.h +++ b/bsp/raspberry-pi/raspi4-64/drivers/board.h @@ -13,13 +13,22 @@ #include #include "raspi4.h" +#include "mmu.h" +#include "ioremap.h" -extern unsigned char __bss_start; -extern unsigned char __bss_end; +extern int __bss_end; +#define HEAP_BEGIN ((void*)&__bss_end) -#define RT_HW_HEAP_BEGIN (void*)&__bss_end -#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024) +#ifdef RT_USING_USERSPACE +#define HEAP_END ((size_t)KERNEL_VADDR_START + 16 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END ((size_t)KERNEL_VADDR_START + 128 * 1024 * 1024) +#else +#define HEAP_END ((size_t)0x60000000 + 64 * 1024 * 1024) +#endif void rt_hw_board_init(void); +extern rt_mmu_info mmu_info; + #endif diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.c new file mode 100644 index 0000000000000000000000000000000000000000..da65b94bb9e3d53ce9288c476eb82cbcff97bc21 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.c @@ -0,0 +1,698 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 bigmagic first version + */ + +#include +#include +#include +#include +#include + +#include "mbox.h" +#include "raspi4.h" +#include "drv_eth.h" + +#define DBG_LEVEL DBG_LOG +#include +#define LOG_TAG "drv.eth" + +static int link_speed = 0; +static int link_flag = 0; + +#define RECV_CACHE_BUF (2048) +#define DMA_DISC_ADDR_SIZE (4 * 1024 *1024) + +#define RX_DESC_BASE (mac_reg_base_addr + GENET_RX_OFF) +#define TX_DESC_BASE (mac_reg_base_addr + GENET_TX_OFF) + +#define MAX_ADDR_LEN (6) + +#define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16)) +#define lower_32_bits(n) ((rt_uint32_t)(n)) + +#define BIT(nr) (1UL << (nr)) + +static rt_thread_t link_thread_tid = RT_NULL; +#define LINK_THREAD_STACK_SIZE (8192) +#define LINK_THREAD_PRIORITY (20) +#define LINK_THREAD_TIMESLICE (10) + +static rt_uint32_t tx_index = 0; +static rt_uint32_t rx_index = 0; +static rt_uint32_t index_flag = 0; + +static rt_uint8_t send_cache_pbuf[RECV_CACHE_BUF]; +//static rt_uint8_t recv_data[RX_BUF_LENGTH]; + +struct rt_eth_dev +{ + struct eth_device parent; + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + char *name; + void *iobase; + int state; + int index; + struct rt_timer link_timer; + void *priv; +}; +static struct rt_eth_dev eth_dev; +static struct rt_semaphore sem_lock; +static struct rt_semaphore link_ack; + +static inline rt_uint32_t read32(void *addr) +{ + return (*((volatile unsigned int*)(addr))); +} + +static inline void write32(void *addr, rt_uint32_t value) +{ + (*((volatile unsigned int*)(addr))) = value; +} + +static void eth_rx_irq(int irq, void *param) +{ + rt_uint32_t val = 0; + + val = read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT); + val &= ~read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT_MASK); + + write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR, val); + + if (val & GENET_IRQ_RXDMA_DONE) + { + eth_device_ready(ð_dev.parent); + } + + if (val & GENET_IRQ_TXDMA_DONE) + { + //todo + } +} + +/* We only support RGMII (as used on the RPi4). */ +static int bcmgenet_interface_set(void) +{ + int phy_mode = PHY_INTERFACE_MODE_RGMII; + switch (phy_mode) + { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + write32(mac_reg_base_addr + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY); + break; + + default: + rt_kprintf("unknown phy mode: %d\n", mac_reg_base_addr); + return -1; + } + return 0; +} + +static void bcmgenet_umac_reset(void) +{ + rt_uint32_t reg; + reg = read32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL); + reg |= BIT(1); + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); + + reg &= ~BIT(1); + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); + + DELAY_MICROS(10); + + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), 0); + DELAY_MICROS(10); + + write32(mac_reg_base_addr + UMAC_CMD, 0); + write32(mac_reg_base_addr + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN)); + DELAY_MICROS(2); + + write32(mac_reg_base_addr + UMAC_CMD, 0); + /* clear tx/rx counter */ + write32(mac_reg_base_addr + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT); + write32(mac_reg_base_addr + UMAC_MIB_CTRL, 0); + write32(mac_reg_base_addr + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE); + + /* init rx registers, enable ip header optimization */ + reg = read32(mac_reg_base_addr + RBUF_CTRL); + reg |= RBUF_ALIGN_2B; + write32(mac_reg_base_addr + RBUF_CTRL, reg); + write32(mac_reg_base_addr + RBUF_TBUF_SIZE_CTRL, 1); +} + +static void bcmgenet_disable_dma(void) +{ + rt_uint32_t tdma_reg = 0, rdma_reg = 0; + + tdma_reg = read32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL); + tdma_reg &= ~(1UL << DMA_EN); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, tdma_reg); + rdma_reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL); + rdma_reg &= ~(1UL << DMA_EN); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, rdma_reg); + write32(mac_reg_base_addr + UMAC_TX_FLUSH, 1); + DELAY_MICROS(100); + write32(mac_reg_base_addr + UMAC_TX_FLUSH, 0); +} + +static void bcmgenet_enable_dma(void) +{ + rt_uint32_t reg = 0; + rt_uint32_t dma_ctrl = 0; + + dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, dma_ctrl); + + reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg); +} + +static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value) +{ + int count = 10000; + rt_uint32_t val; + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT) | (0xffff & value); + write32(mac_reg_base_addr + MDIO_CMD, val); + + rt_uint32_t reg_val = read32(mac_reg_base_addr + MDIO_CMD); + reg_val = reg_val | MDIO_START_BUSY; + write32(mac_reg_base_addr + MDIO_CMD, reg_val); + + while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + DELAY_MICROS(1); + + reg_val = read32(mac_reg_base_addr + MDIO_CMD); + + return reg_val & 0xffff; +} + +static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg) +{ + int count = 10000; + rt_uint32_t val = 0; + rt_uint32_t reg_val = 0; + + val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); + write32(mac_reg_base_addr + MDIO_CMD, val); + + reg_val = read32(mac_reg_base_addr + MDIO_CMD); + reg_val = reg_val | MDIO_START_BUSY; + write32(mac_reg_base_addr + MDIO_CMD, reg_val); + + while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + DELAY_MICROS(1); + + reg_val = read32(mac_reg_base_addr + MDIO_CMD); + + return reg_val & 0xffff; +} + +static int bcmgenet_gmac_write_hwaddr(void) +{ + rt_uint8_t addr[6]; + rt_uint32_t reg; + bcm271x_mbox_hardware_get_mac_address(&addr[0]); + + reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; + write32(mac_reg_base_addr + UMAC_MAC0, reg); + + reg = addr[4] << 8 | addr[5]; + write32(mac_reg_base_addr + UMAC_MAC1, reg); + return 0; +} + +static int get_ethernet_uid(void) +{ + rt_uint32_t uid_high = 0; + rt_uint32_t uid_low = 0; + rt_uint32_t uid = 0; + + uid_high = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_HIGH); + uid_low = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_LOW); + uid = (uid_high << 16 | uid_low); + + if (BCM54213PE_VERSION_B1 == uid) + { + LOG_I("version is B1\n"); + } + return uid; +} + +static void bcmgenet_mdio_init(void) +{ + rt_uint32_t ret = 0; + /*get ethernet uid*/ + ret = get_ethernet_uid(); + if (ret == 0) return; + + /* reset phy */ + bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET); + /* read control reg */ + bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL); + /* reset phy again */ + bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET); + /* read control reg */ + bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL); + /* read status reg */ + bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS); + /* read status reg */ + bcmgenet_mdio_read(1, BCM54213PE_IEEE_EXTENDED_STATUS); + bcmgenet_mdio_read(1, BCM54213PE_AUTO_NEGOTIATION_ADV); + + bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS); + bcmgenet_mdio_read(1, BCM54213PE_CONTROL); + /* half full duplex capability */ + bcmgenet_mdio_write(1, BCM54213PE_CONTROL, (CONTROL_HALF_DUPLEX_CAPABILITY | CONTROL_FULL_DUPLEX_CAPABILITY)); + bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL); + + /* set mii control */ + bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, (MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART | MII_CONTROL_PHY_FULL_DUPLEX | MII_CONTROL_SPEED_SELECTION)); +} + +static void rx_ring_init(void) +{ + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); + write32(mac_reg_base_addr + RDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + RDMA_WRITE_PTR, 0x0); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1); + + write32(mac_reg_base_addr + RDMA_PROD_INDEX, 0x0); + write32(mac_reg_base_addr + RDMA_CONS_INDEX, 0x0); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(mac_reg_base_addr + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); +} + +static void tx_ring_init(void) +{ + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); + write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_WRITE_PTR, 0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1); + write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0x0); + write32(mac_reg_base_addr + TDMA_CONS_INDEX, 0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1); + write32(mac_reg_base_addr + TDMA_FLOW_PERIOD, 0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); +} + +static void rx_descs_init(void) +{ + char *rxbuffs = (char *)RECV_DATA_NO_CACHE; + rt_uint32_t len_stat, i; + void *desc_base = (void *)RX_DESC_BASE; + + len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; + for (i = 0; i < RX_DESCS; i++) + { + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO), lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI), upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS), len_stat); + } +} + +static int bcmgenet_adjust_link(void) +{ + rt_uint32_t speed; + rt_uint32_t phy_dev_speed = link_speed; + + switch (phy_dev_speed) + { + case SPEED_1000: + speed = UMAC_SPEED_1000; + break; + case SPEED_100: + speed = UMAC_SPEED_100; + break; + case SPEED_10: + speed = UMAC_SPEED_10; + break; + default: + rt_kprintf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev_speed); + return -1; + } + + rt_uint32_t reg1 = read32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL); + //reg1 &= ~(1UL << OOB_DISABLE); + + //rt_kprintf("OOB_DISABLE is %d\n", OOB_DISABLE); + reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); + write32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL, reg1); + DELAY_MICROS(1000); + write32(mac_reg_base_addr + UMAC_CMD, speed << CMD_SPEED_SHIFT); + return 0; +} + +void link_irq(void *param) +{ + if ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) != 0) + { + rt_sem_release(&link_ack); + } +} + +static int bcmgenet_gmac_eth_start(void) +{ + rt_uint32_t ret; + rt_uint32_t count = 10000; + + bcmgenet_umac_reset(); + + bcmgenet_gmac_write_hwaddr(); + /* Disable RX/TX DMA and flush TX queues */ + bcmgenet_disable_dma(); + rx_ring_init(); + rx_descs_init(); + tx_ring_init(); + + /* Enable RX/TX DMA */ + bcmgenet_enable_dma(); + + /* Update MAC registers based on PHY property */ + ret = bcmgenet_adjust_link(); + if(ret) + { + rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret); + return ret; + } + + /* wait tx index clear */ + while ((read32(mac_reg_base_addr + TDMA_CONS_INDEX) != 0) && (--count)) + DELAY_MICROS(1); + + tx_index = read32(mac_reg_base_addr + TDMA_CONS_INDEX); + write32(mac_reg_base_addr + TDMA_PROD_INDEX, tx_index); + + index_flag = read32(mac_reg_base_addr + RDMA_PROD_INDEX); + + rx_index = index_flag % 256; + + write32(mac_reg_base_addr + RDMA_CONS_INDEX, index_flag); + write32(mac_reg_base_addr + RDMA_PROD_INDEX, index_flag); + + /* Enable Rx/Tx */ + rt_uint32_t rx_tx_en; + rx_tx_en = read32(mac_reg_base_addr + UMAC_CMD); + rx_tx_en |= (CMD_TX_EN | CMD_RX_EN); + + write32(mac_reg_base_addr + UMAC_CMD, rx_tx_en); + + // eanble IRQ for TxDMA done and RxDMA done + write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE); + return 0; +} + +static rt_uint32_t prev_recv_cnt = 0; +static rt_uint32_t cur_recv_cnt = 0; +static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) +{ + void* desc_base; + rt_uint32_t length = 0; + size_t addr = 0; + rt_uint32_t prod_index = read32(mac_reg_base_addr + RDMA_PROD_INDEX); + //get next + if(prod_index == index_flag) + { + cur_recv_cnt = index_flag; + index_flag = 0x7fffffff; + //no buff + return 0; + } + else + { + if(prev_recv_cnt == (prod_index & 0xffffUL)) + { + return 0; + } + + desc_base = RX_DESC_BASE + rx_index * DMA_DESC_SIZE; + length = read32(desc_base + DMA_DESC_LENGTH_STATUS); + length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; + addr = read32(desc_base + DMA_DESC_ADDRESS_LO); + /* To cater for the IP headepr alignment the hardware does. + * This would actually not be needed if we don't program + * RBUF_ALIGN_2B + */ + *packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET); + + rx_index = rx_index + 1; + if(rx_index >= 256) + { + rx_index = 0; + } + write32(mac_reg_base_addr + RDMA_CONS_INDEX, cur_recv_cnt); + + cur_recv_cnt = cur_recv_cnt + 1; + + if(cur_recv_cnt > 0xffff) + { + cur_recv_cnt = 0; + } + prev_recv_cnt = cur_recv_cnt; + + return length; + } +} + +static int bcmgenet_gmac_eth_send(void *packet, int length) +{ + rt_ubase_t level; + void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE); + rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT; + + rt_uint32_t prod_index, cons; + rt_uint32_t tries = 100; + + prod_index = read32(mac_reg_base_addr + TDMA_PROD_INDEX); + + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; + + write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE); + write32((desc_base + DMA_DESC_ADDRESS_HI), 0); + write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat); + + tx_index = tx_index == 255? 0 : tx_index + 1; + prod_index = prod_index + 1; + + if (prod_index == 0xe000) + { + write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0); + prod_index = 0; + } + + /* Start Transmisson */ + write32(mac_reg_base_addr + TDMA_PROD_INDEX, prod_index); + + level = rt_hw_interrupt_disable(); + do + { + cons = read32(mac_reg_base_addr + TDMA_CONS_INDEX); + } while ((cons & 0xffff) < prod_index && --tries); + rt_hw_interrupt_enable(level); + + if (!tries) + { + rt_kprintf("send err! tries is %d\n", tries); + return -1; + } + + return 0; +} + +static void link_task_entry(void *param) +{ + struct eth_device *eth_device = (struct eth_device *)param; + RT_ASSERT(eth_device != RT_NULL); + struct rt_eth_dev *dev = ð_dev; + + //start mdio + bcmgenet_mdio_init(); + + //start timer link + rt_timer_init(&dev->link_timer, "link_timer", + link_irq, + NULL, + 100, + RT_TIMER_FLAG_PERIODIC); + rt_timer_start(&dev->link_timer); + + //link wait forever + rt_sem_take(&link_ack, RT_WAITING_FOREVER); + eth_device_linkchange(ð_dev.parent, RT_TRUE); //link up + rt_timer_stop(&dev->link_timer); + + //set mac + // bcmgenet_gmac_write_hwaddr(); + bcmgenet_gmac_write_hwaddr(); + + //check link speed + if ((bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 10)) || (bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 11))) + { + link_speed = 1000; + rt_kprintf("Support link mode Speed 1000M\n"); + } + else if ((bcmgenet_mdio_read(1, 0x05) & (1 << 7)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 8)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 9))) + { + link_speed = 100; + rt_kprintf("Support link mode Speed 100M\n"); + } + else + { + link_speed = 10; + rt_kprintf("Support link mode Speed 10M\n"); + } + + bcmgenet_gmac_eth_start(); + + rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq"); + rt_hw_interrupt_umask(ETH_IRQ); + + link_flag = 1; +} + +static rt_err_t bcmgenet_eth_init(rt_device_t device) +{ + rt_uint32_t ret = 0; + rt_uint32_t hw_reg = 0; + + /* Read GENET HW version */ + rt_uint8_t major = 0; + hw_reg = read32(mac_reg_base_addr + SYS_REV_CTRL); + major = (hw_reg >> 24) & 0x0f; + if (major != 6) + { + if (major == 5) + major = 4; + else if (major == 0) + major = 1; + + rt_kprintf("Uns upported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f); + return RT_ERROR; + } + /* set interface */ + ret = bcmgenet_interface_set(); + if (ret) + { + return ret; + } + + /* rbuf clear */ + write32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL, 0); + + /* disable MAC while updating its registers */ + write32(mac_reg_base_addr + UMAC_CMD, 0); + /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ + write32(mac_reg_base_addr + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN); + + link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device, + LINK_THREAD_STACK_SIZE, + LINK_THREAD_PRIORITY, LINK_THREAD_TIMESLICE); + if (link_thread_tid != RT_NULL) + rt_thread_startup(link_thread_tid); + + return RT_EOK; +} + +static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case NIOCTL_GADDR: + if (args) + rt_memcpy(args, eth_dev.dev_addr, 6); + else + return -RT_ERROR; + break; + default: + break; + } + return RT_EOK; +} + +rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) +{ + size_t sendbuf = (size_t)eth_send_no_cache; + /* lock eth device */ + if (link_flag == 1) + { + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0); + rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len); + + bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len); + rt_sem_release(&sem_lock); + } + return RT_EOK; +} + +struct pbuf *rt_eth_rx(rt_device_t device) +{ + int recv_len = 0; + size_t addr_point[8]; + struct pbuf *pbuf = RT_NULL; + if (link_flag == 1) + { + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]); + if (recv_len > 0) + { + pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); + //calc offset + addr_point[0] = (size_t)(addr_point[0] + (eth_recv_no_cache - RECV_DATA_NO_CACHE)); + rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len); + } + rt_sem_release(&sem_lock); + } + return pbuf; +} + +int rt_hw_eth_init(void) +{ + rt_uint8_t mac_addr[6]; + + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO); + + memset(ð_dev, 0, sizeof(eth_dev)); + memset((void *)eth_send_no_cache, 0, sizeof(DMA_DISC_ADDR_SIZE)); + memset((void *)eth_recv_no_cache, 0, sizeof(DMA_DISC_ADDR_SIZE)); + bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]); + + eth_dev.iobase = mac_reg_base_addr; + eth_dev.name = "e0"; + eth_dev.dev_addr[0] = mac_addr[0]; + eth_dev.dev_addr[1] = mac_addr[1]; + eth_dev.dev_addr[2] = mac_addr[2]; + eth_dev.dev_addr[3] = mac_addr[3]; + eth_dev.dev_addr[4] = mac_addr[4]; + eth_dev.dev_addr[5] = mac_addr[5]; + + eth_dev.parent.parent.type = RT_Device_Class_NetIf; + eth_dev.parent.parent.init = bcmgenet_eth_init; + eth_dev.parent.parent.open = RT_NULL; + eth_dev.parent.parent.close = RT_NULL; + eth_dev.parent.parent.read = RT_NULL; + eth_dev.parent.parent.write = RT_NULL; + eth_dev.parent.parent.control = bcmgenet_eth_control; + eth_dev.parent.parent.user_data = RT_NULL; + + eth_dev.parent.eth_tx = rt_eth_tx; + eth_dev.parent.eth_rx = rt_eth_rx; + + eth_device_init(&(eth_dev.parent), "e0"); + eth_device_linkchange(ð_dev.parent, RT_FALSE); //link down + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_eth_init); diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.h b/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.h new file mode 100644 index 0000000000000000000000000000000000000000..860674847a4916b0c78e498913caf24836815aa8 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.h @@ -0,0 +1,224 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 bigmagic first version + */ + +#ifndef __DRV_ETH_H__ +#define __DRV_ETH_H__ + + +//#define BIT(nr) (1UL << (nr)) + +#define SYS_REV_CTRL (0x00) +#define SYS_PORT_CTRL (0x04) +#define PORT_MODE_EXT_GPHY (3) + +#define GENET_SYS_OFF (0x0000) +#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) +#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) + +#define GENET_EXT_OFF (0x0080) +#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) +#define RGMII_LINK BIT(4) +#define OOB_DISABLE BIT(5) +#define RGMII_MODE_EN BIT(6) +#define ID_MODE_DIS BIT(16) + +#define GENET_RBUF_OFF (0x0300) +#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) +#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) +#define RBUF_ALIGN_2B BIT(1) + +#define GENET_UMAC_OFF (0x0800) +#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) +#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) +#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) +#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) +#define UMAC_CMD (GENET_UMAC_OFF + 0x008) +#define MDIO_CMD (GENET_UMAC_OFF + 0x614) +#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) +#define MDIO_START_BUSY BIT(29) +#define MDIO_READ_FAIL BIT(28) +#define MDIO_RD (2 << 26) +#define MDIO_WR BIT(26) +#define MDIO_PMD_SHIFT (21) +#define MDIO_PMD_MASK (0x1f) +#define MDIO_REG_SHIFT (16) +#define MDIO_REG_MASK (0x1f) + +#define GENET_INTRL2_OFF (0x0200) +#define GENET_INTRL2_CPU_STAT (GENET_INTRL2_OFF + 0x00) +#define GENET_INTRL2_CPU_CLEAR (GENET_INTRL2_OFF + 0x08) +#define GENET_INTRL2_CPU_STAT_MASK (GENET_INTRL2_OFF + 0x0c) +#define GENET_INTRL2_CPU_SET_MASK (GENET_INTRL2_OFF + 0x10) +#define GENET_INTRL2_CPU_CLEAR_MASK (GENET_INTRL2_OFF + 0x14) +#define GENET_IRQ_MDIO_ERROR BIT(24) +#define GENET_IRQ_MDIO_DONE BIT(23) +#define GENET_IRQ_TXDMA_DONE BIT(16) +#define GENET_IRQ_RXDMA_DONE BIT(13) + +#define CMD_TX_EN BIT(0) +#define CMD_RX_EN BIT(1) +#define UMAC_SPEED_10 (0) +#define UMAC_SPEED_100 (1) +#define UMAC_SPEED_1000 (2) +#define UMAC_SPEED_2500 (3) +#define CMD_SPEED_SHIFT (2) +#define CMD_SPEED_MASK (3) +#define CMD_SW_RESET BIT(13) +#define CMD_LCL_LOOP_EN BIT(15) +#define CMD_TX_EN BIT(0) +#define CMD_RX_EN BIT(1) + +#define MIB_RESET_RX BIT(0) +#define MIB_RESET_RUNT BIT(1) +#define MIB_RESET_TX BIT(2) + +/* total number of Buffer Descriptors, same for Rx/Tx */ +#define TOTAL_DESCS (256) +#define RX_DESCS TOTAL_DESCS +#define TX_DESCS TOTAL_DESCS + +#define DEFAULT_Q (0x10) + +#define ETH_DATA_LEN (1500) +#define ETH_HLEN (14) +#define VLAN_HLEN (4) +#define ETH_FCS_LEN (4) +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. + * 1536 is multiple of 256 bytes + */ +#define ENET_BRCM_TAG_LEN (6) +#define ENET_PAD (8) +#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ + VLAN_HLEN + ENET_BRCM_TAG_LEN + \ + ETH_FCS_LEN + ENET_PAD) + +/* Tx/Rx Dma Descriptor common bits */ +#define DMA_EN BIT(0) +#define DMA_RING_BUF_EN_SHIFT (0x01) +#define DMA_RING_BUF_EN_MASK (0xffff) +#define DMA_BUFLENGTH_MASK (0x0fff) +#define DMA_BUFLENGTH_SHIFT (16) +#define DMA_RING_SIZE_SHIFT (16) +#define DMA_OWN (0x8000) +#define DMA_EOP (0x4000) +#define DMA_SOP (0x2000) +#define DMA_WRAP (0x1000) +#define DMA_MAX_BURST_LENGTH (0x8) +/* Tx specific DMA descriptor bits */ +#define DMA_TX_UNDERRUN (0x0200) +#define DMA_TX_APPEND_CRC (0x0040) +#define DMA_TX_OW_CRC (0x0020) +#define DMA_TX_DO_CSUM (0x0010) +#define DMA_TX_QTAG_SHIFT (7) + +/* DMA rings size */ +#define DMA_RING_SIZE (0x40) +#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) + +/* DMA descriptor */ +#define DMA_DESC_LENGTH_STATUS (0x00) +#define DMA_DESC_ADDRESS_LO (0x04) +#define DMA_DESC_ADDRESS_HI (0x08) +#define DMA_DESC_SIZE (12) + +#define GENET_RX_OFF (0x2000) +#define GENET_RDMA_REG_OFF \ + (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) +#define GENET_TX_OFF (0x4000) +#define GENET_TDMA_REG_OFF \ + (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) + +#define DMA_FC_THRESH_HI (RX_DESCS >> 4) +#define DMA_FC_THRESH_LO (5) +#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ + DMA_FC_THRESH_HI) + +#define DMA_XOFF_THRESHOLD_SHIFT (16) + +#define TDMA_RING_REG_BASE \ + (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) +#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) +#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) +#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) +#define DMA_RING_BUF_SIZE (0x10) +#define DMA_START_ADDR (0x14) +#define DMA_END_ADDR (0x1c) +#define DMA_MBUF_DONE_THRESH (0x24) +#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) +#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) + +#define RDMA_RING_REG_BASE \ + (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) +#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) +#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) +#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) +#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) +#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) + +#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) +#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) +#define DMA_RING_CFG (0x00) +#define DMA_CTRL (0x04) +#define DMA_SCB_BURST_SIZE (0x0c) + +#define RX_BUF_LENGTH (2048) +#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) +#define RX_BUF_OFFSET (2) + +#define PHY_INTERFACE_MODE_RGMII (7) +#define PHY_INTERFACE_MODE_RGMII_RXID (9) + +#define BCM54213PE_MII_CONTROL (0x00) +#define BCM54213PE_MII_STATUS (0x01) +#define BCM54213PE_PHY_IDENTIFIER_HIGH (0x02) +#define BCM54213PE_PHY_IDENTIFIER_LOW (0x03) + +#define BCM54213PE_AUTO_NEGOTIATION_ADV (0x04) +#define BCM54213PE_AUTO_NEGOTIATION_LINK (0x05) +#define BCM54213PE_AUTO_NEGOTIATION_EXPANSION (0x06) + +#define BCM54213PE_NEXT_PAGE_TX (0x07) + +#define BCM54213PE_PARTNER_RX (0x08) + +#define BCM54213PE_CONTROL (0x09) +#define BCM54213PE_STATUS (0x0A) + +#define BCM54213PE_IEEE_EXTENDED_STATUS (0x0F) +#define BCM54213PE_PHY_EXTENDED_CONTROL (0x10) +#define BCM54213PE_PHY_EXTENDED_STATUS (0x11) + +#define BCM54213PE_RECEIVE_ERROR_COUNTER (0x12) +#define BCM54213PE_FALSE_C_S_COUNTER (0x13) +#define BCM54213PE_RECEIVE_NOT_OK_COUNTER (0x14) + +#define BCM54213PE_VERSION_B1 (0x600d84a2) +#define BCM54213PE_VERSION_X (0x600d84a0) + +//BCM54213PE_MII_CONTROL +#define MII_CONTROL_PHY_RESET (1 << 15) +#define MII_CONTROL_AUTO_NEGOTIATION_ENABLED (1 << 12) +#define MII_CONTROL_AUTO_NEGOTIATION_RESTART (1 << 9) +#define MII_CONTROL_PHY_FULL_DUPLEX (1 << 8) +#define MII_CONTROL_SPEED_SELECTION (1 << 6) + +//BCM54213PE_MII_STATUS +#define MII_STATUS_LINK_UP (1 << 2) + +//BCM54213PE_CONTROL +#define CONTROL_FULL_DUPLEX_CAPABILITY (1 << 9) +#define CONTROL_HALF_DUPLEX_CAPABILITY (1 << 8) + +#define SPEED_1000 (1000) +#define SPEED_100 (100) +#define SPEED_10 (10) + +#endif/* __DRV_ETH_H__ */ diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..b9f6689ae3e38ea8d4e8a9fd7a92f862b3a72248 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.c @@ -0,0 +1,440 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + * 2020-06-16 bigmagic add gpio irq + */ + +#include "drv_gpio.h" + +#ifdef BSP_USING_PIN + +/* + * gpio_int[0] for BANK0 (pins 0-27) + * gpio_int[1] for BANK1 (pins 28-45) + * gpio_int[2] for BANK2 (pins 46-53) + */ +static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM]; + +uint32_t raspi_get_pin_state(uint32_t fselnum) +{ + uint32_t gpfsel = 0; + + switch (fselnum) + { + case 0: + gpfsel = GPIO_REG_GPFSEL0(gpio_base_addr); + break; + case 1: + gpfsel = GPIO_REG_GPFSEL1(gpio_base_addr); + break; + case 2: + gpfsel = GPIO_REG_GPFSEL2(gpio_base_addr); + break; + case 3: + gpfsel = GPIO_REG_GPFSEL3(gpio_base_addr); + break; + case 4: + gpfsel = GPIO_REG_GPFSEL4(gpio_base_addr); + break; + case 5: + gpfsel = GPIO_REG_GPFSEL5(gpio_base_addr); + break; + default: + break; + } + return gpfsel; +} + +void raspi_set_pin_state(uint32_t fselnum, uint32_t gpfsel) +{ + switch (fselnum) + { + case 0: + GPIO_REG_GPFSEL0(gpio_base_addr) = gpfsel; + break; + case 1: + GPIO_REG_GPFSEL1(gpio_base_addr) = gpfsel; + break; + case 2: + GPIO_REG_GPFSEL2(gpio_base_addr) = gpfsel; + break; + case 3: + GPIO_REG_GPFSEL3(gpio_base_addr) = gpfsel; + break; + case 4: + GPIO_REG_GPFSEL4(gpio_base_addr) = gpfsel; + break; + case 5: + GPIO_REG_GPFSEL5(gpio_base_addr) = gpfsel; + break; + default: + break; + } +} + +static void gpio_set_pud(GPIO_PIN pin, GPIO_PUPD_FUNC mode) +{ + uint32_t fselnum = pin / 16; + uint32_t fselrest = pin % 16; + uint32_t reg_value = 0; + + switch (fselnum) + { + case 0: + reg_value = GPIO_PUP_PDN_CNTRL_REG0(gpio_base_addr); + GPIO_PUP_PDN_CNTRL_REG0(gpio_base_addr) = (reg_value | (mode << (fselrest*2))); + break; + case 1: + reg_value = GPIO_PUP_PDN_CNTRL_REG1(gpio_base_addr); + GPIO_PUP_PDN_CNTRL_REG1(gpio_base_addr) = (reg_value | (mode << (fselrest*2))); + break; + + case 2: + reg_value = GPIO_PUP_PDN_CNTRL_REG2(gpio_base_addr); + GPIO_PUP_PDN_CNTRL_REG2(gpio_base_addr) = (reg_value | (mode << (fselrest*2))); + break; + + case 3: + reg_value = GPIO_PUP_PDN_CNTRL_REG3(gpio_base_addr); + GPIO_PUP_PDN_CNTRL_REG3(gpio_base_addr) = (reg_value | (mode << (fselrest*2))); + break; + default: + break; + } +} + +void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode) +{ + uint32_t fselnum = pin / 10; + uint32_t fselrest = pin % 10; + uint32_t gpfsel = 0; + + gpfsel = raspi_get_pin_state(fselnum); + gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3))); + gpfsel |= (uint32_t)(mode << (fselrest * 3)); + raspi_set_pin_state(fselnum, gpfsel); +} + +void prev_raspi_pin_write(GPIO_PIN pin, int pin_value) +{ + uint32_t num = pin / 32; + + if(num == 0) + { + if(pin_value == 1) + { + GPIO_REG_GPSET0(gpio_base_addr) = 1 << (pin % 32); + } + else + { + GPIO_REG_GPCLR0(gpio_base_addr) = 1 << (pin % 32); + } + } + else + { + if(pin_value == 1) + { + GPIO_REG_GPSET1(gpio_base_addr) = 1 << (pin % 32); + } + else + { + GPIO_REG_GPCLR1(gpio_base_addr) = 1 << (pin % 32); + } + + } +} + +static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) +{ + GPIO_FUNC raspi_mode = OUTPUT; + + switch (mode) + { + case PIN_MODE_OUTPUT: + raspi_mode = OUTPUT; + break; + case PIN_MODE_INPUT: + raspi_mode = INPUT; + break; + case PIN_MODE_INPUT_PULLUP: + gpio_set_pud(pin, RASPI_PULL_UP); + raspi_mode = INPUT; + break; + case PIN_MODE_INPUT_PULLDOWN: + gpio_set_pud(pin, RASPI_PULL_DOWN); + raspi_mode = INPUT; + break; + case PIN_MODE_OUTPUT_OD: + raspi_mode = OUTPUT; + break; + } + prev_raspi_pin_mode((GPIO_PIN)pin, raspi_mode); +} + +static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) +{ + prev_raspi_pin_write(pin, value); +} + +static int raspi_pin_read(struct rt_device *device, rt_base_t pin) +{ + uint32_t num = pin / 32; + uint32_t pin_level = 0; + + if(num == 0) + { + if(GPIO_REG_GPLEV0(gpio_base_addr) & (1 << pin)) + { + pin_level = 1; + } + else + { + pin_level = 0; + } + + } + else + { + if(GPIO_REG_GPLEV1(gpio_base_addr) & (1 << pin)) + { + pin_level = 1; + } + else + { + pin_level = 0; + } + } + + return pin_level; +} + +static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_uint8_t index; + rt_uint32_t reg_value; + if (pin <= 27) + index = 0; + else if (pin <= 45) + index = 1; + else + index = 2; + _g_gpio_irq_tbl[index].irq_cb[pin] = hdr; + _g_gpio_irq_tbl[index].irq_arg[pin] = args; + _g_gpio_irq_tbl[index].irq_type[pin] = mode; + + rt_uint8_t shift = pin % 32; + rt_uint8_t pin_num = pin / 32; + rt_uint32_t mask = 1 << shift; + + switch (mode) + { + case PIN_IRQ_MODE_RISING: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPREN0(gpio_base_addr); + GPIO_REG_GPREN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPREN1(gpio_base_addr); + GPIO_REG_GPREN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); + } + break; + case PIN_IRQ_MODE_FALLING: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPFEN0(gpio_base_addr); + GPIO_REG_GPFEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPFEN1(gpio_base_addr); + GPIO_REG_GPFEN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); + } + break; + case PIN_IRQ_MODE_RISING_FALLING: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPAREN0(gpio_base_addr); + GPIO_REG_GPAREN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPFEN0(gpio_base_addr); + GPIO_REG_GPFEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPAREN1(gpio_base_addr); + GPIO_REG_GPAREN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPFEN1(gpio_base_addr); + GPIO_REG_GPFEN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); + } + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPHEN0(gpio_base_addr); + GPIO_REG_GPHEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPHEN1(gpio_base_addr); + GPIO_REG_GPHEN1(gpio_base_addr) = (reg_value & ~ mask) | ( mask); + } + break; + case PIN_IRQ_MODE_LOW_LEVEL: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPLEN0(gpio_base_addr); + GPIO_REG_GPLEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPLEN1(gpio_base_addr); + GPIO_REG_GPLEN1(gpio_base_addr) = (reg_value & ~ mask) | (mask); + } + break; + } + return RT_EOK; +} + +static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_uint8_t index; + if (pin <= 27) + index = 0; + else if (pin <= 45) + index = 1; + else + index = 2; + + _g_gpio_irq_tbl[index].irq_cb[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_arg[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_type[pin] = RT_NULL; + _g_gpio_irq_tbl[index].state[pin] = RT_NULL; + + return RT_EOK; +} + +rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + rt_uint8_t index; + if (pin <= 27) + index = 0; + else if (pin <= 45) + index = 1; + else + index = 2; + + if (enabled) + _g_gpio_irq_tbl[index].state[pin] = 1; + else + _g_gpio_irq_tbl[index].state[pin] = 0; + + return RT_EOK; +} + +static const struct rt_pin_ops ops = +{ + raspi_pin_mode, + raspi_pin_write, + raspi_pin_read, + raspi_pin_attach_irq, + raspi_pin_detach_irq, + raspi_pin_irq_enable, + RT_NULL, +}; + +static void gpio_irq_handler(int irq, void *param) +{ + struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param; + rt_uint32_t pin; + rt_uint32_t value; + rt_uint32_t tmpvalue; + + if(irq == IRQ_GPIO0) + { + /* 0~27 */ + value = GPIO_REG_GPEDS0(gpio_base_addr); + value &= 0x0fffffff; + pin = 0; + GPIO_REG_GPEDS0(gpio_base_addr) = value; + } + else if(irq == IRQ_GPIO1) + { + /* 28-45 */ + tmpvalue = GPIO_REG_GPEDS0(gpio_base_addr); + tmpvalue &= (~0x0fffffff); + GPIO_REG_GPEDS0(gpio_base_addr) = tmpvalue; + + value = GPIO_REG_GPEDS1(gpio_base_addr); + value &= 0x3fff; + GPIO_REG_GPEDS1(gpio_base_addr) = value; + value = (value) | tmpvalue; + pin = 28; + } + else if (irq == IRQ_GPIO2) + { + /* 46-53 */ + value = GPIO_REG_GPEDS1(gpio_base_addr); + value &= (~0x3fff); + GPIO_REG_GPEDS1(gpio_base_addr) = value; + pin = 46; + } + + while (value) + { + if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL)) + { + if(irq_def->state[pin]) + { + irq_def->irq_cb[pin](irq_def->irq_arg[pin]); + } + } + pin++; + value = value >> 1; + } +} +#endif + +int rt_hw_gpio_init(void) +{ +#ifdef BSP_USING_PIN + rt_device_pin_register("gpio", &ops, RT_NULL); + + //disable all intr + GPIO_REG_GPEDS0(gpio_base_addr) = 0xffffffff; + GPIO_REG_GPEDS1(gpio_base_addr) = 0xffffffff; + + GPIO_REG_GPREN0(gpio_base_addr) = 0x0; + GPIO_REG_GPREN1(gpio_base_addr) = 0x0; + + GPIO_REG_GPFEN0(gpio_base_addr) = 0x0; + GPIO_REG_GPFEN1(gpio_base_addr) = 0x0; + + GPIO_REG_GPHEN0(gpio_base_addr) = 0x0; + GPIO_REG_GPHEN1(gpio_base_addr) = 0x0; + + GPIO_REG_GPAREN0(gpio_base_addr) = 0x0; + GPIO_REG_GPAREN1(gpio_base_addr) = 0x0; + + GPIO_REG_GPAFEN0(gpio_base_addr) = 0x0; + GPIO_REG_GPAFEN0(gpio_base_addr) = 0x0; + + rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq"); + rt_hw_interrupt_umask(IRQ_GPIO0); + + rt_hw_interrupt_install(IRQ_GPIO1, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq"); + rt_hw_interrupt_umask(IRQ_GPIO1); + + rt_hw_interrupt_install(IRQ_GPIO2, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq"); + rt_hw_interrupt_umask(IRQ_GPIO2); + +#endif + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_gpio_init); diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.h similarity index 70% rename from bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h rename to bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.h index c4658fcebbaf27ea0833b8f2c41ba7a55d1e312f..7594759f97687aff3953b2d1e8ddffa06b5d356a 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.h @@ -17,6 +17,14 @@ #include "board.h" #include "interrupt.h" +struct gpio_irq_def +{ + void *irq_arg[32]; + void (*irq_cb[32])(void *param); + rt_uint8_t irq_type[32]; + rt_uint8_t state[32]; +}; + #define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00) #define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04) #define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08) @@ -59,6 +67,54 @@ #define GPIO_REG_GPPUDCLK1(BASE) HWREG32(BASE + 0x9C) #define GPIO_REG_REV9(BASE) HWREG32(BASE + 0xA0) #define GPIO_REG_TEST(BASE) HWREG32(BASE + 0xA4) +#define GPIO_PUP_PDN_CNTRL_REG0(BASE) HWREG32(BASE + 0xE4) +#define GPIO_PUP_PDN_CNTRL_REG1(BASE) HWREG32(BASE + 0xE8) +#define GPIO_PUP_PDN_CNTRL_REG2(BASE) HWREG32(BASE + 0xEC) +#define GPIO_PUP_PDN_CNTRL_REG3(BASE) HWREG32(BASE + 0xF0) + +typedef enum { + GPIO_PIN_0, + GPIO_PIN_1, + GPIO_PIN_2, + GPIO_PIN_3, + GPIO_PIN_4, + GPIO_PIN_5, + GPIO_PIN_6, + GPIO_PIN_7, + GPIO_PIN_8, + GPIO_PIN_9, + GPIO_PIN_10, + GPIO_PIN_11, + GPIO_PIN_12, + GPIO_PIN_13, + GPIO_PIN_14, + GPIO_PIN_15, + GPIO_PIN_16, + GPIO_PIN_17, + GPIO_PIN_18, + GPIO_PIN_19, + GPIO_PIN_20, + GPIO_PIN_21, + GPIO_PIN_22, + GPIO_PIN_23, + GPIO_PIN_24, + GPIO_PIN_25, + GPIO_PIN_26, + GPIO_PIN_27, + GPIO_PIN_28, + GPIO_PIN_29, + GPIO_PIN_30, + GPIO_PIN_31, + GPIO_PIN_32, + GPIO_PIN_33, + GPIO_PIN_34, + GPIO_PIN_35, + GPIO_PIN_36, + GPIO_PIN_37, + GPIO_PIN_38, + GPIO_PIN_39, + GPIO_PIN_40, +} GPIO_PIN; typedef enum { INPUT = 0b000, @@ -71,7 +127,14 @@ typedef enum { ALT5 = 0b010 } GPIO_FUNC; +typedef enum { + RASPI_NO_RESISTOR = 0x00, + RASPI_PULL_UP = 0x01, + RASPI_PULL_DOWN = 0x10 +} GPIO_PUPD_FUNC; +void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode); +void prev_raspi_pin_write(GPIO_PIN pin, int pin_value); int rt_hw_gpio_init(void); #endif /* __DRV_GPIO_H__ */ diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_hdmi.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_hdmi.c new file mode 100644 index 0000000000000000000000000000000000000000..d51ab2898e47add29ee281d18f4eae29d0c93002 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_hdmi.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-26 bigmagic first version + */ + +#include +#include +#include "mbox.h" +#include "drv_hdmi.h" + +#ifdef BSP_USING_HDMI +#define LCD_WIDTH (800) +#define LCD_HEIGHT (480) +#define LCD_DEPTH (32) +#define LCD_BPP (32) + +#define TAG_ALLOCATE_BUFFER 0x00040001 +#define TAG_SET_PHYS_WIDTH_HEIGHT 0x00048003 +#define TAG_SET_VIRT_WIDTH_HEIGHT 0x00048004 +#define TAG_SET_DEPTH 0x00048005 +#define TAG_SET_PIXEL_ORDER 0x00048006 +#define TAG_GET_PITCH 0x00040008 +#define TAG_SET_VIRT_OFFSET 0x00048009 +#define TAG_END 0x00000000 + + +enum { + MBOX_TAG_FB_GET_GPIOVIRT = 0x00040010, + MBOX_TAG_FB_ALLOCATE_BUFFER = 0x00040001, + MBOX_TAG_FB_RELEASE_BUFFER = 0x00048001, + MBOX_TAG_FB_BLANK_SCREEN = 0x00040002, + MBOX_TAG_FB_GET_PHYS_WH = 0x00040003, + MBOX_TAG_FB_TEST_PHYS_WH = 0x00044003, + MBOX_TAG_FB_SET_PHYS_WH = 0x00048003, + MBOX_TAG_FB_GET_VIRT_WH = 0x00040004, + MBOX_TAG_FB_TEST_VIRT_WH = 0x00044004, + MBOX_TAG_FB_SET_VIRT_WH = 0x00048004, + MBOX_TAG_FB_GET_DEPTH = 0x00040005, + MBOX_TAG_FB_TEST_DEPTH = 0x00044005, + MBOX_TAG_FB_SET_DEPTH = 0x00048005, + MBOX_TAG_FB_GET_PIXEL_ORDER = 0x00040006, + MBOX_TAG_FB_TEST_PIXEL_ORDER = 0x00044006, + MBOX_TAG_FB_SET_PIXEL_ORDER = 0x00048006, + MBOX_TAG_FB_GET_ALPHA_MODE = 0x00040007, + MBOX_TAG_FB_TEST_ALPHA_MODE = 0x00044007, + MBOX_TAG_FB_SET_ALPHA_MODE = 0x00048007, + MBOX_TAG_FB_GET_PITCH = 0x00040008, + MBOX_TAG_FB_GET_VIRT_OFFSET = 0x00040009, + MBOX_TAG_FB_TEST_VIRT_OFFSET = 0x00044009, + MBOX_TAG_FB_SET_VIRT_OFFSET = 0x00048009, + MBOX_TAG_FB_GET_OVERSCAN = 0x0004000a, + MBOX_TAG_FB_TEST_OVERSCAN = 0x0004400a, + MBOX_TAG_FB_SET_OVERSCAN = 0x0004800a, + MBOX_TAG_FB_GET_PALETTE = 0x0004000b, + MBOX_TAG_FB_TEST_PALETTE = 0x0004400b, + MBOX_TAG_FB_SET_PALETTE = 0x0004800b, +}; + +#define LCD_DEVICE(dev) (struct rt_hdmi_fb_device*)(dev) + +static struct rt_hdmi_fb_device _hdmi; + +typedef rt_uint16_t color_t; + +rt_err_t hdmi_fb_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +rt_err_t hdmi_fb_close(rt_device_t dev) +{ + return RT_EOK; +} + +rt_size_t hdmi_fb_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size) +{ + return 0; +} + +rt_size_t hdmi_fb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + return size; +} + +rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args) +{ + struct rt_hdmi_fb_device *lcd = LCD_DEVICE(dev); + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + { + struct rt_device_rect_info *info = (struct rt_device_rect_info*)args; + info = info; + } + break; + + case RTGRAPHIC_CTRL_GET_INFO: + { + struct rt_device_graphic_info* info = (struct rt_device_graphic_info*)args; + + RT_ASSERT(info != RT_NULL); + info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; + info->bits_per_pixel= LCD_DEPTH; + info->width = lcd->width; + info->height = lcd->height; + info->framebuffer = lcd->fb; + } + break; + } + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops hdmi_fb_ops = +{ + RT_NULL, + hdmi_fb_open, + hdmi_fb_close, + hdmi_fb_read, + hdmi_fb_write, + hdmi_fb_control, +}; +#endif + +rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *name) +{ + struct rt_device *device; + RT_ASSERT(hdmi_fb != RT_NULL); + + device = &hdmi_fb->parent; + + /* set device type */ + device->type = RT_Device_Class_Graphic; + /* initialize device interface */ +#ifdef RT_USING_DEVICE_OPS + device->ops = &hdmi_fb_ops; +#else + device->init = RT_NULL; + device->open = hdmi_fb_open; + device->close = hdmi_fb_close; + device->read = hdmi_fb_read; + device->write = hdmi_fb_write; + device->control = hdmi_fb_control; +#endif + + /* register to device manager */ + rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); + + return RT_EOK; +} + +rt_uint32_t bcm271x_mbox_fb_get_gpiovirt(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_GET_GPIOVIRT; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return (mbox[5] & 0x3fffffff); +} + +rt_uint32_t bcm271x_mbox_fb_get_pitch(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_GET_PITCH; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return mbox[5]; +} + +void bcm271x_mbox_fb_set_porder(int rgb) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_SET_PIXEL_ORDER; + mbox[3] = 4; // buffer size + mbox[4] = 4; // len + + mbox[5] = rgb; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); +} + +void bcm271x_mbox_fb_setoffset(int xoffset, int yoffset) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_SET_VIRT_OFFSET; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = xoffset; // id + mbox[6] = yoffset; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); +} + + +void bcm271x_mbox_fb_setalpha(int alpha) +{ + + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_SET_ALPHA_MODE; + mbox[3] = 4; // buffer size + mbox[4] = 4; // len + + mbox[5] = alpha; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); +} + +void *bcm271x_mbox_fb_alloc(int width, int height, int bpp, int nrender) +{ + mbox[0] = 4 * 35; + mbox[1] = MBOX_REQUEST; + + mbox[2] = TAG_ALLOCATE_BUFFER;//get framebuffer, gets alignment on request + mbox[3] = 8; //size + mbox[4] = 4; //len + mbox[5] = 4096; //The design of MBOX driver forces us to give the virtual address 0x3C100000 + mbox[6] = 0; //FrameBufferInfo.size + + mbox[7] = TAG_SET_PHYS_WIDTH_HEIGHT; + mbox[8] = 8; + mbox[9] = 8; + mbox[10] = width; + mbox[11] = height; + + mbox[12] = TAG_SET_VIRT_WIDTH_HEIGHT; + mbox[13] = 8; + mbox[14] = 8; + mbox[15] = width; + mbox[16] = height * nrender; + + mbox[17] = TAG_SET_DEPTH; + mbox[18] = 4; + mbox[19] = 4; + mbox[20] = bpp; + + mbox[21] = TAG_SET_PIXEL_ORDER; + mbox[22] = 4; + mbox[23] = 0; + mbox[24] = 0; //RGB, not BGR preferably + + mbox[25] = TAG_GET_PITCH; + mbox[26] = 4; + mbox[27] = 0; + mbox[28] = 0; + + mbox[29] = TAG_SET_VIRT_OFFSET; + mbox[30] = 8; + mbox[31] = 8; + mbox[32] = 0; + mbox[33] = 0; + + mbox[34] = TAG_END; + + mbox_call(8, MMU_DISABLE); + return (void *)((size_t)(mbox[5] & 0x3fffffff)); +} + +int hdmi_fb_init(void) +{ + _hdmi.fb = (rt_uint8_t *)bcm271x_mbox_fb_alloc(LCD_WIDTH, LCD_HEIGHT, LCD_BPP, 1); + bcm271x_mbox_fb_setoffset(0, 0); + bcm271x_mbox_fb_set_porder(0); + _hdmi.width = LCD_WIDTH; + _hdmi.height = LCD_HEIGHT; + _hdmi.depth = LCD_DEPTH; + _hdmi.pitch = 0; + _hdmi.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; + + //rt_kprintf("_hdmi.fb is %p\n", _hdmi.fb); + rt_hdmi_fb_device_init(&_hdmi, "lcd"); + + return 0; +} + +INIT_DEVICE_EXPORT(hdmi_fb_init); +#endif /*BSP_USING_HDMI */ diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_hdmi.h b/bsp/raspberry-pi/raspi4-64/drivers/drv_hdmi.h new file mode 100644 index 0000000000000000000000000000000000000000..c9a06358d0db14152b9598e100ac1b31837b3914 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_hdmi.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-26 bigmagic first version + */ +#ifndef __DRV_HDMI_H__ +#define __DRV_HDMI_H__ + +#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b))) + +struct rt_hdmi_fb_device +{ + struct rt_device parent; + + rt_uint32_t width; + rt_uint32_t height; + rt_uint32_t depth; + rt_uint32_t pitch; + rt_uint32_t pixel_format; + + rt_uint8_t *fb; +}; +#endif/* __DRV_HDMI_H__ */ diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_sdio.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_sdio.c new file mode 100644 index 0000000000000000000000000000000000000000..9b03519fe87e0939ca95976c04e27c171cc5076c --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_sdio.c @@ -0,0 +1,651 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-27 bigmagic first version + */ + +#include "mbox.h" +#include "raspi4.h" +#include "drv_sdio.h" + +static rt_uint32_t mmc_base_clock = 0; + +static rt_uint32_t sdCommandTable[] = { + SD_CMD_INDEX(0), + SD_CMD_RESERVED(1), + SD_CMD_INDEX(2) | SD_RESP_R2, + SD_CMD_INDEX(3) | SD_RESP_R1, + SD_CMD_INDEX(4), + SD_CMD_RESERVED(5), //SD_CMD_INDEX(5) | SD_RESP_R4, + SD_CMD_INDEX(6) | SD_RESP_R1, + SD_CMD_INDEX(7) | SD_RESP_R1b, + SD_CMD_INDEX(8) | SD_RESP_R1, + SD_CMD_INDEX(9) | SD_RESP_R2, + SD_CMD_INDEX(10) | SD_RESP_R2, + SD_CMD_INDEX(11) | SD_RESP_R1, + SD_CMD_INDEX(12) | SD_RESP_R1b | SD_CMD_TYPE_ABORT, + SD_CMD_INDEX(13) | SD_RESP_R1, + SD_CMD_RESERVED(14), + SD_CMD_INDEX(15), + SD_CMD_INDEX(16) | SD_RESP_R1, + SD_CMD_INDEX(17) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_INDEX(18) | SD_RESP_R1 | SD_DATA_READ | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN, + SD_CMD_INDEX(19) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_INDEX(20) | SD_RESP_R1b, + SD_CMD_RESERVED(21), + SD_CMD_RESERVED(22), + SD_CMD_INDEX(23) | SD_RESP_R1, + SD_CMD_INDEX(24) | SD_RESP_R1 | SD_DATA_WRITE, + SD_CMD_INDEX(25) | SD_RESP_R1 | SD_DATA_WRITE | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN, + SD_CMD_INDEX(26) | SD_RESP_R1 | SD_DATA_WRITE, //add + SD_CMD_INDEX(27) | SD_RESP_R1 | SD_DATA_WRITE, + SD_CMD_INDEX(28) | SD_RESP_R1b, + SD_CMD_INDEX(29) | SD_RESP_R1b, + SD_CMD_INDEX(30) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_RESERVED(31), + SD_CMD_INDEX(32) | SD_RESP_R1, + SD_CMD_INDEX(33) | SD_RESP_R1, + SD_CMD_RESERVED(34), + SD_CMD_INDEX(35) | SD_RESP_R1, //add + SD_CMD_INDEX(36) | SD_RESP_R1, //add + SD_CMD_RESERVED(37), + SD_CMD_INDEX(38) | SD_RESP_R1b, + SD_CMD_INDEX(39) | SD_RESP_R4, //add + SD_CMD_INDEX(40) | SD_RESP_R5, //add + SD_CMD_INDEX(41) | SD_RESP_R3, //add, mov from harbote + SD_CMD_RESERVED(42) | SD_RESP_R1, + SD_CMD_RESERVED(43), + SD_CMD_RESERVED(44), + SD_CMD_RESERVED(45), + SD_CMD_RESERVED(46), + SD_CMD_RESERVED(47), + SD_CMD_RESERVED(48), + SD_CMD_RESERVED(49), + SD_CMD_RESERVED(50), + SD_CMD_INDEX(51) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_RESERVED(52), + SD_CMD_RESERVED(53), + SD_CMD_RESERVED(54), + SD_CMD_INDEX(55) | SD_RESP_R3, + SD_CMD_INDEX(56) | SD_RESP_R1 | SD_CMD_ISDATA, + SD_CMD_RESERVED(57), + SD_CMD_RESERVED(58), + SD_CMD_RESERVED(59), + SD_CMD_RESERVED(60), + SD_CMD_RESERVED(61), + SD_CMD_RESERVED(62), + SD_CMD_RESERVED(63) +}; + +static inline rt_uint32_t read32(size_t addr) +{ + return (*((volatile unsigned int*)(addr))); +} + +static inline void write32(size_t addr, rt_uint32_t value) +{ + (*((volatile unsigned int*)(addr))) = value; +} + +rt_err_t sd_int(struct sdhci_pdata_t * pdat, rt_uint32_t mask) +{ + rt_uint32_t r; + rt_uint32_t m = mask | INT_ERROR_MASK; + int cnt = 1000000; + while (!(read32(pdat->virt + EMMC_INTERRUPT) & (m | INT_ERROR_MASK)) && cnt--) + DELAY_MICROS(1); + r = read32(pdat->virt + EMMC_INTERRUPT); + if (cnt <= 0 || (r & INT_CMD_TIMEOUT) || (r & INT_DATA_TIMEOUT)) + { + write32(pdat->virt + EMMC_INTERRUPT, r); + //qemu maybe can not use sdcard + rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS)); + return -RT_ETIMEOUT; + } + else if (r & INT_ERROR_MASK) + { + write32(pdat->virt + EMMC_INTERRUPT, r); + rt_kprintf("send cmd/data error %x -> %x\n",r, read32(pdat->virt + EMMC_INTERRUPT)); + return -RT_ERROR; + } + write32(pdat->virt + EMMC_INTERRUPT, mask); + return RT_EOK; +} + +rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask) +{ + int cnt = 500000; + while ((read32(pdat->virt + EMMC_STATUS) & mask) && !(read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) && cnt--) + DELAY_MICROS(1); + if (cnt <= 0) + { + return -RT_ETIMEOUT; + } + else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t raspi_transfer_command(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd) +{ + rt_uint32_t cmdidx; + rt_err_t ret = RT_EOK; + ret = sd_status(pdat, SR_CMD_INHIBIT); + if (ret) + { + rt_kprintf("ERROR: EMMC busy %d\n", ret); + return ret; + } + + cmdidx = sdCommandTable[cmd->cmdidx]; + if (cmdidx == 0xFFFFFFFF) + return -RT_EINVAL; + if (cmd->datarw == DATA_READ) + cmdidx |= SD_DATA_READ; + if (cmd->datarw == DATA_WRITE) + cmdidx |= SD_DATA_WRITE; + mmcsd_dbg("transfer cmd %x(%d) %x %x\n", cmdidx, cmd->cmdidx, cmd->cmdarg, read32(pdat->virt + EMMC_INTERRUPT)); + write32(pdat->virt + EMMC_INTERRUPT,read32(pdat->virt + EMMC_INTERRUPT)); + write32(pdat->virt + EMMC_ARG1, cmd->cmdarg); + write32(pdat->virt + EMMC_CMDTM, cmdidx); + if (cmd->cmdidx == SD_APP_OP_COND) + DELAY_MICROS(1000); + else if ((cmd->cmdidx == SD_SEND_IF_COND) || (cmd->cmdidx == APP_CMD)) + DELAY_MICROS(100); + + ret = sd_int(pdat, INT_CMD_DONE); + if (ret) + { + return ret; + } + if (cmd->resptype & RESP_MASK) + { + + if (cmd->resptype & RESP_R2) + { + rt_uint32_t resp[4]; + resp[0] = read32(pdat->virt + EMMC_RESP0); + resp[1] = read32(pdat->virt + EMMC_RESP1); + resp[2] = read32(pdat->virt + EMMC_RESP2); + resp[3] = read32(pdat->virt + EMMC_RESP3); + if (cmd->resptype == RESP_R2) + { + cmd->response[0] = resp[3]<<8 |((resp[2]>>24)&0xff); + cmd->response[1] = resp[2]<<8 |((resp[1]>>24)&0xff); + cmd->response[2] = resp[1]<<8 |((resp[0]>>24)&0xff); + cmd->response[3] = resp[0]<<8 ; + } + else + { + cmd->response[0] = resp[0]; + cmd->response[1] = resp[1]; + cmd->response[2] = resp[2]; + cmd->response[3] = resp[3]; + } + } + else + cmd->response[0] = read32(pdat->virt + EMMC_RESP0); + } + mmcsd_dbg("response: %x: %x %x %x %x (%x, %x)\n", cmd->resptype, cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3], read32(pdat->virt + EMMC_STATUS),read32(pdat->virt + EMMC_INTERRUPT)); + return ret; +} + +static rt_err_t read_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize) +{ + int c = 0; + rt_err_t ret; + int d; + while (c < blkcount) + { + if ((ret = sd_int(pdat, INT_READ_RDY))) + { + rt_kprintf("timeout happens when reading block %d\n",c); + return ret; + } + for (d=0; d < blksize / 4; d++) + if (read32(pdat->virt + EMMC_STATUS) & SR_READ_AVAILABLE) + buf[d] = read32(pdat->virt + EMMC_DATA); + c++; + buf += blksize / 4; + } + return RT_EOK; +} + +static rt_err_t write_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize) +{ + int c = 0; + rt_err_t ret; + int d; + while (c < blkcount) + { + if ((ret = sd_int(pdat, INT_WRITE_RDY))) + { + return ret; + } + for (d=0; d < blksize / 4; d++) + write32(pdat->virt + EMMC_DATA, buf[d]); + c++; + buf += blksize / 4; + } + + if ((ret = sd_int(pdat, INT_DATA_DONE))) + { + return ret; + } + return RT_EOK; +} + +static rt_err_t raspi_transfer_data(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat) +{ + rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz); + rt_err_t ret = sd_status(pdat, SR_DAT_INHIBIT); + if (ret) + { + rt_kprintf("ERROR: EMMC busy\n"); + return ret; + } + if (dat->blkcnt > 1) + { + struct sdhci_cmd_t newcmd; + newcmd.cmdidx = SET_BLOCK_COUNT; + newcmd.cmdarg = dat->blkcnt; + newcmd.resptype = RESP_R1; + ret = raspi_transfer_command(pdat, &newcmd); + if (ret) return ret; + } + + if(dlen < 512) + { + write32(pdat->virt + EMMC_BLKSIZECNT, dlen | 1 << 16); + } + else + { + write32(pdat->virt + EMMC_BLKSIZECNT, 512 | (dat->blkcnt) << 16); + } + if (dat->flag & DATA_DIR_READ) + { + cmd->datarw = DATA_READ; + ret = raspi_transfer_command(pdat, cmd); + if (ret) return ret; + mmcsd_dbg("read_block %d, %d\n", dat->blkcnt, dat->blksz ); + ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz); + } + else if (dat->flag & DATA_DIR_WRITE) + { + cmd->datarw = DATA_WRITE; + ret = raspi_transfer_command(pdat, cmd); + if (ret) return ret; + mmcsd_dbg("write_block %d, %d", dat->blkcnt, dat->blksz ); + ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz); + } + return ret; +} + +static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat) +{ + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv; + if (!dat) + return raspi_transfer_command(pdat, cmd); + + return raspi_transfer_data(pdat, cmd, dat); +} + +static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data; + struct sdhci_cmd_t cmd; + struct sdhci_cmd_t stop; + struct sdhci_data_t dat; + rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t)); + rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t)); + rt_memset(&dat, 0, sizeof(struct sdhci_data_t)); + + cmd.cmdidx = req->cmd->cmd_code; + cmd.cmdarg = req->cmd->arg; + cmd.resptype =resp_type(req->cmd); + if (req->data) + { + dat.buf = (rt_uint8_t *)req->data->buf; + dat.flag = req->data->flags; + dat.blksz = req->data->blksize; + dat.blkcnt = req->data->blks; + + req->cmd->err = sdhci_transfer(sdhci, &cmd, &dat); + } + else + { + req->cmd->err = sdhci_transfer(sdhci, &cmd, RT_NULL); + } + + req->cmd->resp[3] = cmd.response[3]; + req->cmd->resp[2] = cmd.response[2]; + req->cmd->resp[1] = cmd.response[1]; + req->cmd->resp[0] = cmd.response[0]; + + if (req->stop) + { + stop.cmdidx = req->stop->cmd_code; + stop.cmdarg = req->stop->arg; + cmd.resptype =resp_type(req->stop); + req->stop->err = sdhci_transfer(sdhci, &stop, RT_NULL); + } + + mmcsd_req_complete(host); +} + +rt_int32_t mmc_card_status(struct rt_mmcsd_host *host) +{ + return 0; +} + +static rt_err_t sdhci_detect(struct sdhci_t * sdhci) +{ + return RT_EOK; +} + +static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width) +{ + rt_uint32_t temp = 0; + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv; + if (width == MMCSD_BUS_WIDTH_4) + { + temp = read32((pdat->virt + EMMC_CONTROL0)); + temp |= C0_HCTL_HS_EN; + temp |= C0_HCTL_DWITDH; // always use 4 data lines: + write32((pdat->virt + EMMC_CONTROL0), temp); + } + return RT_EOK; +} + + +static uint32_t sd_get_clock_divider(rt_uint32_t sdHostVer ,rt_uint32_t base_clock, rt_uint32_t target_rate) +{ + rt_uint32_t targetted_divisor = 0; + rt_uint32_t freq_select = 0; + rt_uint32_t upper_bits = 0; + rt_uint32_t ret = 0; + + if(target_rate > base_clock) + targetted_divisor = 1; + else + { + targetted_divisor = base_clock / target_rate; + rt_uint32_t mod = base_clock % target_rate; + if(mod) + targetted_divisor--; + } + + // Decide on the clock mode to use + + // Currently only 10-bit divided clock mode is supported + + // HCI version 3 or greater supports 10-bit divided clock mode + // This requires a power-of-two divider + + // Find the first bit set + int divisor = -1; + for(int first_bit = 31; first_bit >= 0; first_bit--) + { + rt_uint32_t bit_test = (1 << first_bit); + if(targetted_divisor & bit_test) + { + divisor = first_bit; + targetted_divisor &= ~bit_test; + if(targetted_divisor) + { + // The divisor is not a power-of-two, increase it + divisor++; + } + break; + } + } + + if(divisor == -1) + divisor = 31; + if(divisor >= 32) + divisor = 31; + + if(divisor != 0) + divisor = (1 << (divisor - 1)); + + if(divisor >= 0x400) + divisor = 0x3ff; + + freq_select = divisor & 0xff; + upper_bits = (divisor >> 8) & 0x3; + ret = (freq_select << 8) | (upper_bits << 6) | (0 << 5); + + return ret; +} + +static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock) +{ + rt_uint32_t temp = 0; + rt_uint32_t sdHostVer = 0; + int count = 100000; + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)(sdhci->priv); + + while ((read32(pdat->virt + EMMC_STATUS) & (SR_CMD_INHIBIT | SR_DAT_INHIBIT)) && (--count)) + DELAY_MICROS(1); + if (count <= 0) + { + rt_kprintf("EMMC: Set clock: timeout waiting for inhibit flags. Status %08x.\n",read32(pdat->virt + EMMC_STATUS)); + return RT_ERROR; + } + + // Switch clock off. + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp &= ~C1_CLK_EN; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + // Request the new clock setting and enable the clock + temp = read32(pdat->virt + EMMC_SLOTISR_VER); + sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT; + int cdiv = sd_get_clock_divider(sdHostVer, mmc_base_clock, clock); + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp |= 1; + temp |= cdiv; + temp |= (7 << 16); + + temp = (temp & 0xffff003f) | cdiv; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + + // Enable the clock. + temp = read32(pdat->virt + EMMC_CONTROL1); + temp |= C1_CLK_EN; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + + // Wait for clock to be stable. + count = 10000; + while (!(read32(pdat->virt + EMMC_CONTROL1) & C1_CLK_STABLE) && count--) + DELAY_MICROS(10); + if (count <= 0) + { + rt_kprintf("EMMC: ERROR: failed to get stable clock %d.\n", clock); + return RT_ERROR; + } + + mmcsd_dbg("set stable clock %d.\n", clock); + return RT_EOK; +} + +static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + struct sdhci_t * sdhci = (struct sdhci_t *)host->private_data; + sdhci_setclock(sdhci, io_cfg->clock); + sdhci_setwidth(sdhci, io_cfg->bus_width); +} + +static const struct rt_mmcsd_host_ops ops = +{ + mmc_request_send, + mmc_set_iocfg, + RT_NULL, + RT_NULL, +}; + +static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat) +{ + rt_uint32_t control1; + + //Reset the controller + control1 = read32((pdat->virt + EMMC_CONTROL1)); + control1 |= (1 << 24); + // Disable clock + control1 &= ~(1 << 2); + control1 &= ~(1 << 0); + //temp |= C1_CLK_INTLEN | C1_TOUNIT_MAX; + write32((pdat->virt + EMMC_CONTROL1),control1); + int cnt = 10000; + do + { + DELAY_MICROS(10); + cnt = cnt - 1; + if(cnt == 0) + { + break; + } + } while ((read32(pdat->virt + EMMC_CONTROL1) & (0x7 << 24)) != 0); + + // Enable SD Bus Power VDD1 at 3.3V + rt_uint32_t control0 = read32(pdat->virt + EMMC_CONTROL0); + control0 |= 0x0F << 8; + write32(pdat->virt + EMMC_CONTROL0, control0); + + rt_thread_delay(100); + //usleep(2000); + + + // Check for a valid card + mmcsd_dbg("EMMC: checking for an inserted card\n"); + cnt = 10000; + do + { + DELAY_MICROS(10); + cnt = cnt - 1; + if(cnt == 0) + { + break; + } + } while ((read32(pdat->virt + EMMC_STATUS) & (0x1 << 16)) == 0); + + rt_uint32_t status_reg = read32(pdat->virt + EMMC_STATUS); + + if((status_reg & (1 << 16)) == 0) + { + rt_kprintf("EMMC: no card inserted\n"); + return -1; + } + else + { + mmcsd_dbg("EMMC: status: %08x\n", status_reg); + } + + // Clear control2 + write32(pdat->virt + EMMC_CONTROL2, 0); + // Get the base clock rate //12 + mmc_base_clock = bcm271x_mbox_clock_get_rate(EMMC_CLK_ID); + if(mmc_base_clock == 0) + { + rt_kprintf("EMMC: assuming clock rate to be 100MHz\n"); + mmc_base_clock = 100000000; + } + mmcsd_dbg("EMMC: setting clock rate is %d\n", mmc_base_clock); + return RT_EOK; +} + +#ifdef RT_MMCSD_DBG +void dump_registers(struct sdhci_pdata_t * pdat) +{ + rt_kprintf("EMMC registers:"); + int i = EMMC_ARG2; + for (; i <= EMMC_CONTROL2; i += 4) + rt_kprintf("\t%x:%x\n", i, read32(pdat->virt + i)); + rt_kprintf("\t%x:%x\n", 0x50, read32(pdat->virt + 0x50)); + rt_kprintf("\t%x:%x\n", 0x70, read32(pdat->virt + 0x70)); + rt_kprintf("\t%x:%x\n", 0x74, read32(pdat->virt + 0x74)); + rt_kprintf("\t%x:%x\n", 0x80, read32(pdat->virt + 0x80)); + rt_kprintf("\t%x:%x\n", 0x84, read32(pdat->virt + 0x84)); + rt_kprintf("\t%x:%x\n", 0x88, read32(pdat->virt + 0x88)); + rt_kprintf("\t%x:%x\n", 0x8c, read32(pdat->virt + 0x8c)); + rt_kprintf("\t%x:%x\n", 0x90, read32(pdat->virt + 0x90)); + rt_kprintf("\t%x:%x\n", 0xf0, read32(pdat->virt + 0xf0)); + rt_kprintf("\t%x:%x\n", 0xfc, read32(pdat->virt + 0xfc)); +} +#endif + +int raspi_sdmmc_init(void) +{ + size_t virt; + struct rt_mmcsd_host * host = RT_NULL; + struct sdhci_pdata_t * pdat = RT_NULL; + struct sdhci_t * sdhci = RT_NULL; + +#ifdef BSP_USING_SDIO0 + host = mmcsd_alloc_host(); + if (!host) + { + rt_kprintf("alloc host failed"); + goto err; + } + sdhci = rt_malloc(sizeof(struct sdhci_t)); + if (!sdhci) + { + rt_kprintf("alloc sdhci failed"); + goto err; + } + rt_memset(sdhci, 0, sizeof(struct sdhci_t)); + + virt = mmc2_base_addr; + pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t)); + RT_ASSERT(pdat != RT_NULL); + + pdat->virt = virt; + reset_emmc(pdat); + sdhci->name = "sd0"; + sdhci->voltages = VDD_33_34; + sdhci->width = MMCSD_BUSWIDTH_4; + sdhci->clock = 1000 * 1000 * 1000; + sdhci->removeable = RT_TRUE; + + sdhci->detect = sdhci_detect; + sdhci->setwidth = sdhci_setwidth; + sdhci->setclock = sdhci_setclock; + sdhci->transfer = sdhci_transfer; + sdhci->priv = pdat; + host->ops = &ops; + host->freq_min = 400000; + host->freq_max = 50000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4; + host->max_seg_size = 2048; + host->max_dma_segs = 10; + host->max_blk_size = 512; + host->max_blk_count = 1; + + host->private_data = sdhci; + write32((pdat->virt + EMMC_IRPT_EN),0xffffffff); + write32((pdat->virt + EMMC_IRPT_MASK),0xffffffff); +#ifdef RT_MMCSD_DBG + dump_registers(pdat); +#endif + mmcsd_change(host); +#endif + return RT_EOK; +err: + if (host) rt_free(host); + if (sdhci) rt_free(sdhci); + + return -RT_EIO; +} + +INIT_DEVICE_EXPORT(raspi_sdmmc_init); diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_sdio.h b/bsp/raspberry-pi/raspi4-64/drivers/drv_sdio.h new file mode 100644 index 0000000000000000000000000000000000000000..1abedf2a0ba7ec52e271e9e8b5529ef212a6bd6b --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_sdio.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-27 bigmagic first version + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +#include +#include +#include + +#include "board.h" +#include "raspi4.h" + +/* Struct for Intrrrupt Information */ +#define SDXC_CmdDone BIT(0) +#define SDXC_DataDone BIT(1) +#define SDXC_BlockGap BIT(2) +#define SDXC_WriteRdy BIT(4) +#define SDXC_ReadRdy BIT(5) +#define SDXC_Card BIT(8) +#define SDXC_Retune BIT(12) +#define SDXC_BootAck BIT(13) +#define SDXC_EndBoot BIT(14) +#define SDXC_Err BIT(15) +#define SDXC_CTOErr BIT(16) +#define SDXC_CCRCErr BIT(17) +#define SDXC_CENDErr BIT(18) +#define SDXC_CBADErr BIT(19) +#define SDXC_DTOErr BIT(20) +#define SDXC_DCRCErr BIT(21) +#define SDXC_DENDErr BIT(22) +#define SDXC_ACMDErr BIT(24) + +#define SDXC_BLKCNT_EN BIT(1) +#define SDXC_AUTO_CMD12_EN BIT(2) +#define SDXC_AUTO_CMD23_EN BIT(3) +#define SDXC_DAT_DIR BIT(4) //from card to host +#define SDXC_MULTI_BLOCK BIT(5) +#define SDXC_CMD_RSPNS_136 BIT(16) +#define SDXC_CMD_RSPNS_48 BIT(17) +#define SDXC_CMD_RSPNS_48busy BIT(16)|BIT(17) +#define SDXC_CHECK_CRC_CMD BIT(19) +#define SDXC_CMD_IXCHK_EN BIT(20) +#define SDXC_CMD_ISDATA BIT(21) +#define SDXC_CMD_SUSPEND BIT(22) +#define SDXC_CMD_RESUME BIT(23) +#define SDXC_CMD_ABORT BIT(23)|BIT(22) + +#define SDXC_CMD_INHIBIT BIT(0) +#define SDXC_DAT_INHIBIT BIT(1) +#define SDXC_DAT_ACTIVE BIT(2) +#define SDXC_WRITE_TRANSFER BIT(8) +#define SDXC_READ_TRANSFER BIT(9) + +struct sdhci_cmd_t +{ + rt_uint32_t cmdidx; + rt_uint32_t cmdarg; + rt_uint32_t resptype; + rt_uint32_t datarw; +#define DATA_READ 1 +#define DATA_WRITE 2 + rt_uint32_t response[4]; +}; + +struct sdhci_data_t +{ + rt_uint8_t * buf; + rt_uint32_t flag; + rt_uint32_t blksz; + rt_uint32_t blkcnt; +}; + +struct sdhci_t +{ + char * name; + rt_uint32_t voltages; + rt_uint32_t width; + rt_uint32_t clock; + rt_err_t removeable; + void * sdcard; + + rt_err_t (*detect)(struct sdhci_t * sdhci); + rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width); + rt_err_t (*setclock)(struct sdhci_t * sdhci, rt_uint32_t clock); + rt_err_t (*transfer)(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat); + void * priv; +}; + +struct sdhci_pdata_t +{ + size_t virt; +}; + +// EMMC command flags +#define CMD_TYPE_NORMAL (0x00000000) +#define CMD_TYPE_SUSPEND (0x00400000) +#define CMD_TYPE_RESUME (0x00800000) +#define CMD_TYPE_ABORT (0x00c00000) +#define CMD_IS_DATA (0x00200000) +#define CMD_IXCHK_EN (0x00100000) +#define CMD_CRCCHK_EN (0x00080000) +#define CMD_RSPNS_NO (0x00000000) +#define CMD_RSPNS_136 (0x00010000) +#define CMD_RSPNS_48 (0x00020000) +#define CMD_RSPNS_48B (0x00030000) +#define TM_MULTI_BLOCK (0x00000020) +#define TM_DAT_DIR_HC (0x00000000) +#define TM_DAT_DIR_CH (0x00000010) +#define TM_AUTO_CMD23 (0x00000008) +#define TM_AUTO_CMD12 (0x00000004) +#define TM_BLKCNT_EN (0x00000002) +#define TM_MULTI_DATA (CMD_IS_DATA|TM_MULTI_BLOCK|TM_BLKCNT_EN) + +#define RCA_NO (1) +#define RCA_YES (2) + +// INTERRUPT register settings +#define INT_AUTO_ERROR (0x01000000) +#define INT_DATA_END_ERR (0x00400000) +#define INT_DATA_CRC_ERR (0x00200000) +#define INT_DATA_TIMEOUT (0x00100000) +#define INT_INDEX_ERROR (0x00080000) +#define INT_END_ERROR (0x00040000) +#define INT_CRC_ERROR (0x00020000) +#define INT_CMD_TIMEOUT (0x00010000) +#define INT_ERR (0x00008000) +#define INT_ENDBOOT (0x00004000) +#define INT_BOOTACK (0x00002000) +#define INT_RETUNE (0x00001000) +#define INT_CARD (0x00000100) +#define INT_READ_RDY (0x00000020) +#define INT_WRITE_RDY (0x00000010) +#define INT_BLOCK_GAP (0x00000004) +#define INT_DATA_DONE (0x00000002) +#define INT_CMD_DONE (0x00000001) +#define INT_ERROR_MASK (INT_CRC_ERROR|INT_END_ERROR|INT_INDEX_ERROR| \ + INT_DATA_TIMEOUT|INT_DATA_CRC_ERR|INT_DATA_END_ERR| \ + INT_ERR|INT_AUTO_ERROR) +#define INT_ALL_MASK (INT_CMD_DONE|INT_DATA_DONE|INT_READ_RDY|INT_WRITE_RDY|INT_ERROR_MASK) + +#define EMMC_ARG2 (0x00) +#define EMMC_BLKSIZECNT (0x04) +#define EMMC_ARG1 (0x08) +#define EMMC_CMDTM (0x0c) +#define EMMC_RESP0 (0x10) +#define EMMC_RESP1 (0x14) +#define EMMC_RESP2 (0x18) +#define EMMC_RESP3 (0x1c) +#define EMMC_DATA (0x20) +#define EMMC_STATUS (0x24) +#define EMMC_CONTROL0 (0x28) +#define EMMC_CONTROL1 (0x2c) +#define EMMC_INTERRUPT (0x30) +#define EMMC_IRPT_MASK (0x34) +#define EMMC_IRPT_EN (0x38) +#define EMMC_CONTROL2 (0x3c) +#define EMMC_CAPABILITIES_0 (0x40) +#define EMMC_CAPABILITIES_1 (0x44) +#define EMMC_BOOT_TIMEOUT (0x70) +#define EMMC_EXRDFIFO_EN (0x84) +#define EMMC_SPI_INT_SPT (0xf0) +#define EMMC_SLOTISR_VER (0xfc) + +// CONTROL register settings +#define C0_SPI_MODE_EN (0x00100000) +#define C0_HCTL_HS_EN (0x00000004) +#define C0_HCTL_DWITDH (0x00000002) + +#define C1_SRST_DATA (0x04000000) +#define C1_SRST_CMD (0x02000000) +#define C1_SRST_HC (0x01000000) +#define C1_TOUNIT_DIS (0x000f0000) +#define C1_TOUNIT_MAX (0x000e0000) +#define C1_CLK_GENSEL (0x00000020) +#define C1_CLK_EN (0x00000004) +#define C1_CLK_STABLE (0x00000002) +#define C1_CLK_INTLEN (0x00000001) + +#define FREQ_SETUP (400000) // 400 Khz +#define FREQ_NORMAL (25000000) // 25 Mhz + +// SLOTISR_VER values +#define HOST_SPEC_NUM 0x00ff0000 +#define HOST_SPEC_NUM_SHIFT 16 +#define HOST_SPEC_V3 2 +#define HOST_SPEC_V2 1 +#define HOST_SPEC_V1 0 + +// STATUS register settings +#define SR_DAT_LEVEL1 (0x1e000000) +#define SR_CMD_LEVEL (0x01000000) +#define SR_DAT_LEVEL0 (0x00f00000) +#define SR_DAT3 (0x00800000) +#define SR_DAT2 (0x00400000) +#define SR_DAT1 (0x00200000) +#define SR_DAT0 (0x00100000) +#define SR_WRITE_PROT (0x00080000) // From SDHC spec v2, BCM says reserved +#define SR_READ_AVAILABLE (0x00000800) // ???? undocumented +#define SR_WRITE_AVAILABLE (0x00000400) // ???? undocumented +#define SR_READ_TRANSFER (0x00000200) +#define SR_WRITE_TRANSFER (0x00000100) +#define SR_DAT_ACTIVE (0x00000004) +#define SR_DAT_INHIBIT (0x00000002) +#define SR_CMD_INHIBIT (0x00000001) + +#define CONFIG_MMC_USE_DMA +#define DMA_ALIGN (32U) + +#define SD_CMD_INDEX(a) ((a) << 24) +#define SD_CMD_RESERVED(a) (0xffffffff) +#define SD_CMD_INDEX(a) ((a) << 24) +#define SD_CMD_TYPE_NORMAL (0x0) +#define SD_CMD_TYPE_SUSPEND (1 << 22) +#define SD_CMD_TYPE_RESUME (2 << 22) +#define SD_CMD_TYPE_ABORT (3 << 22) +#define SD_CMD_TYPE_MASK (3 << 22) +#define SD_CMD_ISDATA (1 << 21) +#define SD_CMD_IXCHK_EN (1 << 20) +#define SD_CMD_CRCCHK_EN (1 << 19) +#define SD_CMD_RSPNS_TYPE_NONE (0) // For no response +#define SD_CMD_RSPNS_TYPE_136 (1 << 16) // For response R2 (with CRC), R3,4 (no CRC) +#define SD_CMD_RSPNS_TYPE_48 (2 << 16) // For responses R1, R5, R6, R7 (with CRC) +#define SD_CMD_RSPNS_TYPE_48B (3 << 16) // For responses R1b, R5b (with CRC) +#define SD_CMD_RSPNS_TYPE_MASK (3 << 16) +#define SD_CMD_MULTI_BLOCK (1 << 5) +#define SD_CMD_DAT_DIR_HC (0) +#define SD_CMD_DAT_DIR_CH (1 << 4) +#define SD_CMD_AUTO_CMD_EN_NONE (0) +#define SD_CMD_AUTO_CMD_EN_CMD12 (1 << 2) +#define SD_CMD_AUTO_CMD_EN_CMD23 (2 << 2) +#define SD_CMD_BLKCNT_EN (1 << 1) +#define SD_CMD_DMA (1) +#define SD_RESP_NONE SD_CMD_RSPNS_TYPE_NONE +#define SD_RESP_R1 (SD_CMD_RSPNS_TYPE_48) // | SD_CMD_CRCCHK_EN) +#define SD_RESP_R1b (SD_CMD_RSPNS_TYPE_48B) // | SD_CMD_CRCCHK_EN) +#define SD_RESP_R2 (SD_CMD_RSPNS_TYPE_136) // | SD_CMD_CRCCHK_EN) +#define SD_RESP_R3 SD_CMD_RSPNS_TYPE_48 +#define SD_RESP_R4 SD_CMD_RSPNS_TYPE_136 +#define SD_RESP_R5 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) +#define SD_RESP_R5b (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN) +#define SD_RESP_R6 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) +#define SD_RESP_R7 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) +#define SD_DATA_READ (SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH) +#define SD_DATA_WRITE (SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC) +#endif diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_spi.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..d072869048fac5dd2d4c874f512e08cb6805b1a3 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_spi.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-22 bigmagic first version + */ +#include +#include +#include + +#include "raspi4.h" +#include "drv_spi.h" + +#ifdef BSP_USING_SPI + +#define RPI_CORE_CLK_HZ (250000000) +#define BSP_SPI_MAX_HZ (30* 1000 *1000) +#define SPITIMEOUT 0x0FFF + +static rt_uint8_t raspi_byte_reverse_table[] = +{ + 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, + 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, + 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, + 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, + 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, + 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, + 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, + 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, + 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, + 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, + 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, + 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, + 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, + 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, + 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, + 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, + 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, + 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, + 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, + 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, + 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, + 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, + 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, + 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, + 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, + 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, + 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, + 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, + 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, + 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, + 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, + 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff +}; + +#if defined (BSP_USING_SPI0_BUS) +#define SPI0_BUS_NAME "spi0" +#define SPI0_DEVICE0_NAME "spi0.0" +#define SPI0_DEVICE1_NAME "spi0.1" + +struct rt_spi_bus spi0_bus; + +#if defined (BSP_USING_SPI0_DEVICE0) +static struct rt_spi_device spi0_device0; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) +static struct rt_spi_device spi0_device1; +#endif +#endif + +static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(device != RT_NULL); + rt_uint16_t divider; + struct raspi_spi_device* hw_config = (struct raspi_spi_device *)(device->parent.user_data); + struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config; + // spi clear fifo + SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX); + if(cfg->mode & RT_SPI_CPOL) + { + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPOL; + } + + if(cfg->mode & RT_SPI_CPHA) + { + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPHA; + } + + if(cfg->mode & RT_SPI_CS_HIGH) + { + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH; + } + + //set clk + if (cfg->max_hz > BSP_SPI_MAX_HZ) + cfg->max_hz = BSP_SPI_MAX_HZ; + + divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz); + divider &= 0xFFFE; + + SPI_REG_CLK(hwcfg->hw_base) = divider; + + return RT_EOK; +} + +rt_uint8_t correct_order(rt_uint8_t b, rt_uint8_t flag) +{ + if (flag) + return raspi_byte_reverse_table[b];//reverse + else + return b; +} + +static rt_err_t spi_transfernb(struct raspi_spi_hw_config *hwcfg, rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len, rt_uint8_t flag) +{ + rt_uint32_t TXCnt=0; + rt_uint32_t RXCnt=0; + + /* Clear TX and RX fifos */ + SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX); + + /* Set TA = 1 */ + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_TA; + + /* Use the FIFO's to reduce the interbyte times */ + while ((TXCnt < len) || (RXCnt < len)) + { + /* TX fifo not full, so add some more bytes */ + while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_TX_DATA)) && (TXCnt < len)) + { + SPI_REG_FIFO(hwcfg->hw_base) = correct_order(tbuf[TXCnt],flag); + TXCnt++; + } + /* Rx fifo not empty, so get the next received bytes */ + while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_RX_DATA)) && (RXCnt < len)) + { + rbuf[RXCnt] = correct_order(SPI_REG_FIFO(hwcfg->hw_base), flag); + RXCnt++; + } + } + /* Wait for DONE to be set */ + while (!(SPI_REG_CS(hwcfg->hw_base) & SPI_CS_DONE)); + /* Set TA = 0, and also set the barrier */ + SPI_REG_CS(hwcfg->hw_base) |= (0 & SPI_CS_TA); + + return RT_EOK; +} + +static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_err_t res; + rt_uint8_t flag; + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->parent.user_data != RT_NULL); + RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); + + struct rt_spi_configuration config = device->config; + struct raspi_spi_device * hw_config = (struct raspi_spi_device *)device->parent.user_data; + GPIO_PIN cs_pin = (GPIO_PIN)hw_config->cs_pin; + struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config; + + if (config.mode & RT_SPI_MSB) + { + flag = 0; + } + else + { + flag = 1; + } + + if (message->cs_take) + { + (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 1):prev_raspi_pin_write(cs_pin, 0); + } + + res = spi_transfernb(hwcfg, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, flag); + if (message->cs_release) + { + (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 0):prev_raspi_pin_write(cs_pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; + + return message->length; +} + +rt_err_t raspi_spi_bus_attach_device(const char *bus_name, struct raspi_spi_device *device) +{ + rt_err_t ret; + RT_ASSERT(device != RT_NULL); + ret = rt_spi_bus_attach_device(device->spi_device, device->device_name, bus_name, (void *)(device)); + return ret; +} + +rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg) +{ + prev_raspi_pin_mode(hwcfg->sclk_pin, hwcfg->sclk_mode); + prev_raspi_pin_mode(hwcfg->miso_pin, hwcfg->miso_mode); + prev_raspi_pin_mode(hwcfg->mosi_pin, hwcfg->mosi_mode); +#if defined (BSP_USING_SPI0_DEVICE0) + prev_raspi_pin_mode(hwcfg->ce0_pin, hwcfg->ce0_mode); +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + prev_raspi_pin_mode(hwcfg->ce1_pin, hwcfg->ce1_mode); +#endif + //clear rx and tx + SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX); + //enable chip select +#if defined (BSP_USING_SPI0_DEVICE0) + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_0; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_1; +#endif + +#if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1) + HWREG32(SPI_REG_CS(hwcfg->hw_base)) |= (SPI_CS_CHIP_SELECT_0 | SPI_CS_CHIP_SELECT_1); +#endif + return RT_EOK; +} + +static struct rt_spi_ops raspi_spi_ops = +{ + .configure = raspi_spi_configure, + .xfer = raspi_spi_xfer +}; + +struct raspi_spi_hw_config raspi_spi0_hw = +{ + .spi_num = 0, + .sclk_pin = GPIO_PIN_11, + .sclk_mode = ALT0, + .mosi_pin = GPIO_PIN_10, + .mosi_mode = ALT0, + .miso_pin = GPIO_PIN_9, + .miso_mode = ALT0, + +#if defined (BSP_USING_SPI0_DEVICE0) + .ce0_pin = GPIO_PIN_8, + .ce0_mode = ALT0, +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + .ce1_pin = GPIO_PIN_7, + .ce1_mode = ALT0, +#endif + .hw_base = SPI_0_BASE, +}; +#endif + +#if defined (BSP_USING_SPI0_DEVICE0) +struct raspi_spi_device raspi_spi0_device0 = +{ + .device_name = SPI0_DEVICE0_NAME, + .spi_bus = &spi0_bus, + .spi_device = &spi0_device0, + .spi_hw_config = &raspi_spi0_hw, + .cs_pin = GPIO_PIN_8, +}; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) +struct raspi_spi_device raspi_spi0_device1 = +{ + .device_name = SPI0_DEVICE1_NAME, + .spi_bus = &spi0_bus, + .spi_device = &spi0_device1, + .cs_pin = GPIO_PIN_7, +}; +#endif + +int rt_hw_spi_init(void) +{ +#if defined (BSP_USING_SPI0_BUS) + raspi_spi_hw_init(&raspi_spi0_hw); + rt_spi_bus_register(&spi0_bus, SPI0_BUS_NAME, &raspi_spi_ops); + +#if defined (BSP_USING_SPI0_DEVICE0) + raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device0); +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device1); +#endif +#endif + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spi_init); diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_spi.h b/bsp/raspberry-pi/raspi4-64/drivers/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..9cd8e031e4edd4e8f7e141ffdc2c9d83f12d8ecb --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_spi.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-16 bigmagic first version + */ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include "drv_gpio.h" + +#define SPI_REG_CS(BASE) HWREG32(BASE + 0x00) +#define SPI_REG_FIFO(BASE) HWREG32(BASE + 0x04) +#define SPI_REG_CLK(BASE) HWREG32(BASE + 0x08) +#define SPI_REG_DLEN(BASE) HWREG32(BASE + 0x0C) +#define SPI_REG_LTOH(BASE) HWREG32(BASE + 0x10) +#define SPI_REG_DC(BASE) HWREG32(BASE + 0x14) + +/* CS Register */ +#define SPI_CS_LOSSI_LONG_32BIT (1 << 25) +#define SPI_CS_LOSSI_DMA_MODE (1 << 24) +#define SPI_CS_CSPOL2 (1 << 23) +#define SPI_CS_CSPOL1 (1 << 22) +#define SPI_CS_CSPOL0 (1 << 21) +#define SPI_CS_RX_FIFO_FULL (1 << 20) +#define SPI_CS_RX_FIFO_3_QUARTER (1 << 19) +#define SPI_CS_TX_DATA (1 << 18) +#define SPI_CS_RX_DATA (1 << 17) +#define SPI_CS_DONE (1 << 16) +#define SPI_CS_LOSSI_EN (1 << 13) +#define SPI_CS_READ_EN (1 << 12) +#define SPI_CS_AUTO_CS (1 << 11) +#define SPI_CS_INTR_RXR (1 << 10) +#define SPI_CS_INTR_DONE (1 << 9) +#define SPI_CS_DMA_EN (1 << 8) +#define SPI_CS_TA (1 << 7) +#define SPI_CS_CSPOL_HIGH (1 << 6) +#define SPI_CS_CLEAR_RX (2 << 4) +#define SPI_CS_CLEAR_TX (1 << 4) +#define SPI_CS_CPOL (1 << 3) +#define SPI_CS_CPHA (1 << 2) +#define SPI_CS_CHIP_SELECT_2 (2 << 0) +#define SPI_CS_CHIP_SELECT_1 (1 << 0) +#define SPI_CS_CHIP_SELECT_0 (0 << 0) + +struct raspi_spi_hw_config +{ + rt_uint8_t spi_num; + GPIO_PIN sclk_pin; + GPIO_FUNC sclk_mode; + GPIO_PIN mosi_pin; + GPIO_FUNC mosi_mode; + GPIO_PIN miso_pin; + GPIO_FUNC miso_mode; +#if defined (BSP_USING_SPI0_DEVICE0) || defined (BSP_USING_SPI1_DEVICE0) + GPIO_PIN ce0_pin; + GPIO_FUNC ce0_mode; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) || defined (BSP_USING_SPI1_DEVICE1) + GPIO_PIN ce1_pin; + GPIO_FUNC ce1_mode; +#endif + +#if defined (BSP_USING_SPI1_DEVICE2) + GPIO_PIN ce2_pin; + GPIO_FUNC ce2_mode; +#endif + rt_ubase_t hw_base; + +}; + +struct raspi_spi_device +{ + char *device_name; + struct rt_spi_bus *spi_bus; + struct rt_spi_device *spi_device; + struct raspi_spi_hw_config *spi_hw_config; + GPIO_PIN cs_pin; +}; + +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..e0b849c34dd3b4f4e7ca76c67ad0f098b5ef31c7 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.c @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + * 2020-05-26 bigmagic add other uart + */ + +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" +#include "drv_gpio.h" +#include + +size_t uart0_addr = 0; +size_t uart3_addr = 0; +size_t uart4_addr = 0; +size_t uart5_addr = 0; + +#ifdef RT_USING_UART0 +static struct rt_serial_device _serial0; +#endif + +#ifdef RT_USING_UART1 +static struct rt_serial_device _serial1; +#endif + +#ifdef RT_USING_UART3 +static struct rt_serial_device _serial3; +#endif + +#ifdef RT_USING_UART4 +static struct rt_serial_device _serial4; +#endif + +#ifdef RT_USING_UART5 +static struct rt_serial_device _serial5; +#endif + +struct hw_uart_device +{ + rt_ubase_t hw_base; + rt_uint32_t irqno; +}; + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct hw_uart_device *uart; + uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16; + uint32_t ibrd = bauddiv / 1000; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + if(uart->hw_base == AUX_BASE) + { + prev_raspi_pin_mode(GPIO_PIN_14, ALT5); + prev_raspi_pin_mode(GPIO_PIN_15, ALT5); + + AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */ + AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */ + AUX_MU_CNTL_REG(uart->hw_base) = 0; /* Disable Transmitter and Receiver */ + AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */ + AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */ + AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */ + AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */ + AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */ + return RT_EOK; + } + + if(uart->hw_base == uart0_addr) + { + prev_raspi_pin_mode(GPIO_PIN_14, ALT0); + prev_raspi_pin_mode(GPIO_PIN_15, ALT0); + } + + if(uart->hw_base == uart3_addr) + { + prev_raspi_pin_mode(GPIO_PIN_4, ALT4); + prev_raspi_pin_mode(GPIO_PIN_5, ALT4); + } + + if(uart->hw_base == uart4_addr) + { + prev_raspi_pin_mode(GPIO_PIN_8, ALT4); + prev_raspi_pin_mode(GPIO_PIN_9, ALT4); + } + + if(uart->hw_base == uart5_addr) + { + prev_raspi_pin_mode(GPIO_PIN_12, ALT4); + prev_raspi_pin_mode(GPIO_PIN_13, ALT4); + } + + PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/ + PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/ + PL011_REG_IBRD(uart->hw_base) = ibrd; + PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000); + PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/ + PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/ + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + if(uart->hw_base == AUX_BASE) + { + AUX_MU_IER_REG(uart->hw_base) = 0x1; + } + else + { + PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM; + } + rt_hw_interrupt_umask(uart->irqno); + break; + } + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + if(uart->hw_base == AUX_BASE) + { + while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20)); + AUX_MU_IO_REG(uart->hw_base) = c; + } + else + { + while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF)); + PL011_REG_DR(uart->hw_base) = (uint8_t)c; + } + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + if(uart->hw_base == AUX_BASE) + { + if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01)) + { + ch = AUX_MU_IO_REG(uart->hw_base) & 0xff; + } + } + else + { + if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0) + { + ch = PL011_REG_DR(uart->hw_base) & 0xff; + } + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +#ifdef RT_USING_UART1 +static void rt_hw_aux_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device*)param; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} +#endif + +static void rt_hw_uart_isr(int irqno, void *param) +{ +#ifdef RT_USING_UART0 + if((PACTL_CS & IRQ_UART0) == IRQ_UART0) + { + PACTL_CS &= ~(IRQ_UART0); + rt_hw_serial_isr(&_serial0, RT_SERIAL_EVENT_RX_IND); + PL011_REG_ICR(uart0_addr) = PL011_INTERRUPT_RECEIVE; + } +#endif + +#ifdef RT_USING_UART3 + if((PACTL_CS & IRQ_UART3) == IRQ_UART3) + { + PACTL_CS &= ~(IRQ_UART3); + rt_hw_serial_isr(&_serial3, RT_SERIAL_EVENT_RX_IND); + PL011_REG_ICR(uart3_addr) = PL011_INTERRUPT_RECEIVE; + } +#endif + +#ifdef RT_USING_UART4 + if((PACTL_CS & IRQ_UART4) == IRQ_UART4) + { + PACTL_CS &= ~(IRQ_UART4); + rt_hw_serial_isr(&_serial4, RT_SERIAL_EVENT_RX_IND); + PL011_REG_ICR(uart4_addr) = PL011_INTERRUPT_RECEIVE; + } +#endif + +#ifdef RT_USING_UART5 + if((PACTL_CS & IRQ_UART5) == IRQ_UART5) + { + PACTL_CS &= ~(IRQ_UART5); + rt_hw_serial_isr(&_serial5, RT_SERIAL_EVENT_RX_IND); + PL011_REG_ICR(uart5_addr) = PL011_INTERRUPT_RECEIVE; + } +#endif +} + +#ifdef RT_USING_UART0 +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + UART0_BASE, + IRQ_PL011, +}; +#endif + +#ifdef RT_USING_UART1 +/* UART device driver structure */ +static struct hw_uart_device _uart1_device = +{ + AUX_BASE, + IRQ_AUX_UART, +}; +#endif + +#ifdef RT_USING_UART3 +static struct hw_uart_device _uart3_device = +{ + UART3_BASE, + IRQ_PL011, +}; +#endif + +#ifdef RT_USING_UART4 +static struct hw_uart_device _uart4_device = +{ + UART4_BASE, + IRQ_PL011, +}; +#endif + +#ifdef RT_USING_UART5 +static struct hw_uart_device _uart5_device = +{ + UART5_BASE, + IRQ_PL011, +}; +#endif + +int rt_hw_uart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef RT_USING_UART0 + struct hw_uart_device *uart0; + uart0 = &_uart0_device; + + _serial0.ops = &_uart_ops; + _serial0.config = config; + + uart0_addr = (size_t)rt_ioremap((void*)UART0_BASE, 0x1000); + uart0->hw_base = uart0_addr; + + + /* register UART0 device */ + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart0); + rt_hw_interrupt_install(uart0->irqno, rt_hw_uart_isr, &_serial0, "uart0"); + +#endif + +#ifdef RT_USING_UART1 + struct hw_uart_device *uart1; + uart1 = &_uart1_device; + + _serial1.ops = &_uart_ops; + _serial1.config = config; + + uart1->hw_base = (size_t)rt_ioremap((void*)AUX_BASE, 0x1000); + + /* register UART1 device */ + rt_hw_serial_register(&_serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart1); + rt_hw_interrupt_install(uart1->irqno, rt_hw_aux_uart_isr, &_serial1, "uart1"); +#endif + +#ifdef RT_USING_UART3 + struct hw_uart_device *uart3; + uart3 = &_uart3_device; + + _serial3.ops = &_uart_ops; + _serial3.config = config; + + uart3_addr = (size_t)rt_ioremap((void*)UART3_BASE, 0x1000); + uart3->hw_base = uart3_addr; + + /* register UART3 device */ + rt_hw_serial_register(&_serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart3); + rt_hw_interrupt_install(uart3->irqno, rt_hw_uart_isr, &_serial3, "uart3"); +#endif + +#ifdef RT_USING_UART4 + struct hw_uart_device *uart4; + uart4 = &_uart4_device; + + _serial4.ops = &_uart_ops; + _serial4.config = config; + + uart4_addr = (size_t)rt_ioremap((void*)UART4_BASE, 0x1000); + uart4->hw_base = uart4_addr; + + /* register UART4 device */ + rt_hw_serial_register(&_serial4, "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart4); + rt_hw_interrupt_install(uart4->irqno, rt_hw_uart_isr, &_serial4, "uart4"); +#endif + +#ifdef RT_USING_UART5 + struct hw_uart_device *uart5; + uart5 = &_uart5_device; + + _serial5.ops = &_uart_ops; + _serial5.config = config; + + uart5_addr = (size_t)rt_ioremap((void*)UART5_BASE, 0x1000); + uart5->hw_base = uart5_addr; + + /* register UART5 device */ + rt_hw_serial_register(&_serial5, "uart5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart5); + rt_hw_interrupt_install(uart5->irqno, rt_hw_uart_isr, &_serial5, "uart5"); +#endif + return 0; +} + diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h b/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.h similarity index 63% rename from bsp/raspberry-pi/raspi4-64/driver/drv_uart.h rename to bsp/raspberry-pi/raspi4-64/drivers/drv_uart.h index 714043efd37c90aba5101a43d817108401eee59b..d57f4e52f4e3fb53436e4af2b0990b8907479ed2 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.h @@ -78,6 +78,30 @@ #define PL011_REG_ITOP(BASE) HWREG32(BASE + 0x88) #define PL011_REG_TDR(BASE) HWREG32(BASE + 0x8C) +/* + * Auxiliary + */ +#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ +#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ +#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ +#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */ +#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */ +#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ +#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */ +#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ +#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */ +#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ +#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */ +#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */ +#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ +#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */ +#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */ +#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ +#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ +#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */ +#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */ +#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */ + int rt_hw_uart_init(void); #endif /* DRV_UART_H__ */ diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..3c091354bb6e163649136de8d392356c009e158a --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-26 bigmagic first version + */ +#include +#include "drv_wdt.h" +#include "raspi4.h" + +#ifdef BSP_USING_WDT + +#define SECS_TO_WDOG_TICKS(x) ((x) << 16) +#define WDOG_TICKS_TO_SECS(x) ((x) >> 16) + +static struct raspi_wdt_driver bcm_wdt; + +void raspi_watchdog_init(rt_uint32_t time_init) +{ + bcm_wdt.timeout = time_init; +} + +void raspi_watchdog_start() +{ + volatile rt_uint32_t cur; + PM_WDOG = PM_PASSWORD | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET); + cur = (PM_RSTC); + PM_RSTC = PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; +} + +void raspi_watchdog_stop() +{ + PM_RSTC = PM_PASSWORD | PM_RSTC_RESET; +} + +void raspi_watchdog_clr() +{ + bcm_wdt.timeout = 0; +} + +void raspi_watchdog_set_timeout(rt_uint32_t timeout_us) +{ + bcm_wdt.timeout = timeout_us; +} + +rt_uint64_t raspi_watchdog_get_timeout() +{ + return bcm_wdt.timeout; +} + +rt_uint64_t raspi_watchdog_get_timeleft() +{ + rt_uint32_t ret = (PM_WDOG); + return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET); +} + +static rt_err_t raspi_wdg_init(rt_watchdog_t *wdt) +{ + /*init for 10S*/ + raspi_watchdog_init(1000000); + raspi_watchdog_start(); + raspi_watchdog_stop(); + return RT_EOK; +} + +static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + rt_uint64_t timeout_us = 0; + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + timeout_us = *((rt_uint32_t *)arg) * 1000000; + if (timeout_us >= 0xFFFFFFFF) + timeout_us = 0xFFFFFFFF; + raspi_watchdog_set_timeout((rt_uint32_t)timeout_us); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + timeout_us = raspi_watchdog_get_timeout(); + *((rt_uint32_t *)arg) = timeout_us / 1000000; + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + timeout_us = raspi_watchdog_get_timeleft(); + *((rt_uint32_t *)arg) = timeout_us / 1000000; + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + raspi_watchdog_clr(); + break; + case RT_DEVICE_CTRL_WDT_START: + raspi_watchdog_start(); + break; + case RT_DEVICE_CTRL_WDT_STOP: + raspi_watchdog_stop(); + break; + default: + return RT_EIO; + } + return RT_EOK; +} + +static const struct rt_watchdog_ops raspi_wdg_pos = +{ + raspi_wdg_init, + raspi_wdg_control, +}; + +static rt_watchdog_t raspi_wdg; + +int rt_hw_wdt_init(void) +{ + raspi_wdg.ops = &raspi_wdg_pos; + rt_hw_watchdog_register(&raspi_wdg, "wdg", 0, RT_NULL); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_wdt_init); + +void reboot(void) +{ + unsigned int r; + + rt_kprintf("reboot system...\n"); + rt_thread_mdelay(100); + r = PM_RSTS; + // trigger a restart by instructing the GPU to boot from partition 0 + r &= ~0xfffffaaa; + PM_RSTS |= (PM_PASSWORD | r); // boot from partition 0 + PM_WDOG |= (PM_PASSWORD | 0x0A); + PM_RSTC |= (PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET); + + while (1); +} +MSH_CMD_EXPORT(reboot,reboot system...); +#endif /*BSP_USING_WDT */ diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.h b/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..4c9454ed91c57ac749b602d01890a3e73dd5574b --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-26 bigmagic first version + */ +#ifndef __DRV_WDT_H__ +#define __DRV_WDT_H__ + +#include +#include + +#include "board.h" + +struct raspi_wdt_driver +{ + rt_uint32_t timeout; +}; + +int rt_hw_wdt_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi4-64/drivers/mbox.c b/bsp/raspberry-pi/raspi4-64/drivers/mbox.c new file mode 100644 index 0000000000000000000000000000000000000000..177b043a8a22cb8c11c8044e62e9d4adef856f90 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/mbox.c @@ -0,0 +1,499 @@ +/* + * File : mbox.c + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-29 zdzn first version + * 2020-09-10 bigmagic add other mbox option + */ + +/* mailbox message buffer */ +#include +#include "mbox.h" +#include "mmu.h" +//volatile unsigned int __attribute__((aligned(16))) mbox[36]; + +#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) +volatile unsigned int *mbox; + +/** + * Make a mailbox call. Returns 0 on failure, non-zero on success + */ +int mbox_call(unsigned char ch, int mmu_enable) +{ + unsigned int r = ((((rt_uint32_t)MBOX_ADDR)&~0xF) | (ch&0xF)); + if(mmu_enable) + r = BUS_ADDRESS(r); + /* wait until we can write to the mailbox */ + do + { + asm volatile("nop"); + } while (*MBOX_STATUS & MBOX_FULL); + /* write the address of our message to the mailbox with channel identifier */ + *MBOX_WRITE = r; + /* now wait for the response */ + while(1) + { + /* is there a response? */ + do + { + asm volatile("nop"); + } while (*MBOX_STATUS & MBOX_EMPTY); + /* is it a response to our message? */ + if (r == *MBOX_READ){ + /* is it a valid successful response? */ + return mbox[1] == MBOX_RESPONSE; + } + } + return 0; +} + +int bcm271x_notify_reboot(void) +{ + mbox[0] = 7*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + mbox[2] = MBOX_TAG_NOTIFY_REBOOT; // (the tag id) + mbox[3] = 0x00000004; // length + 4 + mbox[4] = 0x00000000; // size of the data + mbox[5] = 0x00000000; // request + + mbox[6] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return 0; +} + +int bcm271x_notify_xhci_reset(void) +{ + mbox[0] = 7*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + mbox[2] = MBOX_TAG_NOTIFY_XHCI_RESET; // (the tag id) + mbox[3] = 0x00000004; // length + 4 + mbox[4] = 0x00000004; // size of the data + mbox[5] = 0x00100000; // request + mbox[6] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return 0; +} + +int bcm271x_gpu_enable(void) +{ + mbox[0] = 12*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_SET_RATE; + mbox[3] = 0x00000008; // (the tag id) + mbox[4] = 0x00000008; // (the tag id) + mbox[5] = 5; // V3D + mbox[6] = 250 * 1000 * 1000; + mbox[7] = MBOX_TAG_ENABLE_QPU; // (the tag id) + mbox[8] = 0x00000004; // (size of the buffer) + mbox[9] = 0x00000004; // (size of the data) + mbox[10] = 0x00000001; + mbox[11] = MBOX_TAG_LAST; // end tag + mbox_call(8, MMU_DISABLE); + return mbox[1]; +} + +int bcm271x_mbox_hardware_get_model(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_MODEL; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + return mbox[5]; +} + +int bcm271x_mbox_hardware_get_revison(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_REV; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + return mbox[5]; +} + +int bcm271x_mbox_hardware_get_mac_address(uint8_t * mac) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS; + mbox[3] = 6; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + char * mac_str = (char *)&mbox[5]; + mac[0] = mac_str[0]; + mac[1] = mac_str[1]; + mac[2] = mac_str[2]; + mac[3] = mac_str[3]; + mac[4] = mac_str[4]; + mac[5] = mac_str[5]; + return 0; +} + + +int bcm271x_mbox_hardware_get_serial(rt_uint64_t* sn) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL; + mbox[3] = 8; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + sn = (rt_uint64_t *)&mbox[5]; + + return 0; +} + +int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY; + mbox[3] = 8; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + *base = mbox[5]; + *size = mbox[6]; + + return 0; + +} + +int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_HARDWARE_GET_VC_MEMORY; + mbox[3] = 8; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + *base = mbox[5]; + *size = mbox[6]; + + return 0; +} + +int bcm271x_mbox_clock_get_turbo(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_TURBO; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = 0; // id + mbox[6] = 0; // val + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != 0) + { + return -1; + } + + return mbox[6]; +} + +int bcm271x_mbox_clock_set_turbo(int level) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_SET_TURBO; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = 0; // id + mbox[6] = level ? 1 : 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != 0) + { + return -1; + } + + return mbox[6]; +} + +int bcm271x_mbox_clock_get_state(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_STATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return (mbox[6] & 0x3); +} + +int bcm271x_mbox_clock_set_state(int id, int state) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_SET_STATE; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = id; // id + mbox[6] = state & 0x3; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return (mbox[6] & 0x3); +} + +int bcm271x_mbox_clock_get_rate(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_RATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return mbox[6]; +} + +int bcm271x_mbox_clock_set_rate(int id, int rate) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_SET_RATE; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = id; // id + mbox[6] = rate; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return mbox[6]; +} + +int bcm271x_mbox_clock_get_max_rate(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_MAX_RATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return mbox[6]; +} + +int bcm271x_mbox_clock_get_min_rate(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return mbox[6]; +} + +int bcm271x_mbox_power_get_state(int id) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_POWER_GET_STATE; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = id; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return (mbox[6] & 0x3); +} + +int bcm271x_mbox_power_set_state(int id, int state) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_POWER_SET_STATE; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = id; // id + mbox[6] = state & 0x3; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != id) + { + return -1; + } + + return (mbox[6] & 0x3); +} + +int bcm271x_mbox_temp_get(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_TEMP_GET; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = 0; //id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != 0) + { + return -1; + } + + return mbox[6]; +} + +int bcm271x_mbox_temp_get_max(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_TEMP_GET_MAX; + mbox[3] = 8; // buffer size + mbox[4] = 4; // len + + mbox[5] = 0; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + + if(mbox[5] != 0) + { + return -1; + } + + return mbox[6]; +} diff --git a/bsp/raspberry-pi/raspi4-64/drivers/mbox.h b/bsp/raspberry-pi/raspi4-64/drivers/mbox.h new file mode 100644 index 0000000000000000000000000000000000000000..40c50f4080a0fe131c57d5da558a38c87ccaebf4 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/mbox.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-10 bigmagic first version + */ + +#ifndef __MBOX_H__ +#define __MBOX_H__ + +#include + +//https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface +//https://github.com/hermanhermitage/videocoreiv + +/* a properly aligned buffer */ +extern volatile unsigned int* mbox; + +#define MBOX_REQUEST 0 + +/* channels */ +#define MBOX_CH_POWER 0 +#define MBOX_CH_FB 1 +#define MBOX_CH_VUART 2 +#define MBOX_CH_VCHIQ 3 +#define MBOX_CH_LEDS 4 +#define MBOX_CH_BTNS 5 +#define MBOX_CH_TOUCH 6 +#define MBOX_CH_COUNT 7 +#define MBOX_CH_PROP 8 + +/* tags */ +#define MBOX_TAG_SETPOWER 0x28001 +#define MBOX_TAG_SETCLKRATE 0x38002 +#define MBOX_GET_MAC_ADDRESS 0x10003 +#define MBOX_TAG_LAST 0 + +#define MMIO_BASE 0xFE000000 +#define VIDEOCORE_MBOX (MMIO_BASE+0x0000B880) +extern size_t videocore_mbox; +#define MBOX_READ ((volatile unsigned int*)(videocore_mbox+0x0)) +#define MBOX_POLL ((volatile unsigned int*)(videocore_mbox+0x10)) +#define MBOX_SENDER ((volatile unsigned int*)(videocore_mbox+0x14)) +#define MBOX_STATUS ((volatile unsigned int*)(videocore_mbox+0x18)) +#define MBOX_CONFIG ((volatile unsigned int*)(videocore_mbox+0x1C)) +#define MBOX_WRITE ((volatile unsigned int*)(videocore_mbox+0x20)) +#define MBOX_RESPONSE 0x80000000 +#define MBOX_FULL 0x80000000 +#define MBOX_EMPTY 0x40000000 + +#define DEVICE_ID_SD_CARD (0) +#define DEVICE_ID_USB_HCD (3) +#define POWER_STATE_OFF (0 << 0) +#define POWER_STATE_ON (1 << 0) +#define POWER_STATE_WAIT (1 << 1) +#define POWER_STATE_NO_DEVICE (1 << 1) // in response +#define MMU_ENABLE (1) +#define MMU_DISABLE (0) + +/* + * raspi hardware info + */ +enum { + MBOX_TAG_HARDWARE_GET_MODEL = 0x00010001, + MBOX_TAG_HARDWARE_GET_REV = 0x00010002, + MBOX_TAG_HARDWARE_GET_MAC_ADDRESS = 0x00010003, + MBOX_TAG_HARDWARE_GET_SERIAL = 0x00010004, + MBOX_TAG_HARDWARE_GET_ARM_MEMORY = 0x00010005, + MBOX_TAG_HARDWARE_GET_VC_MEMORY = 0x00010006, + MBOX_TAG_HARDWARE_GET_CLOCKS = 0x00010007, +}; + +/* + * raspi clock + */ +enum { + MBOX_TAG_CLOCK_GET_TURBO = 0x00030009, + MBOX_TAG_CLOCK_SET_TURBO = 0x00038009, + MBOX_TAG_CLOCK_GET_STATE = 0x00030001, + MBOX_TAG_CLOCK_SET_STATE = 0x00038001, + MBOX_TAG_CLOCK_GET_RATE = 0x00030002, + MBOX_TAG_CLOCK_SET_RATE = 0x00038002, + MBOX_TAG_CLOCK_GET_MAX_RATE = 0x00030004, + MBOX_TAG_CLOCK_GET_MIN_RATE = 0x00030007, +}; + +/* + * raspi power + */ +enum { + MBOX_TAG_POWER_GET_STATE = 0x00020001, + MBOX_TAG_POWER_SET_STATE = 0x00028001, +}; + +/* + * raspi temperature + */ +enum { + MBOX_TAG_TEMP_GET = 0x00030006, + MBOX_TAG_TEMP_GET_MAX = 0x0003000A, +}; + +/* + * raspi Memory + */ +enum { + MBOX_TAG_ALLOCATE_MEMORY = 0x0003000C, // Memory: Allocates Contiguous Memory On The GPU (Response: Handle) + MBOX_TAG_LOCK_MEMORY = 0x0003000D, // Memory: Unlock Buffer (Response: Status) + MBOX_TAG_UNLOCK_MEMORY = 0x0003000E, // Memory: Unlock Buffer (Response: Status) + MBOX_TAG_RELEASE_MEMORY = 0x0003000F, // Memory: Free The Memory Buffer (Response: Status) + MBOX_TAG_EXECUTE_CODE = 0x00030010, // Memory: Calls The Function At Given (Bus) Address And With Arguments Given +}; + +/* + * raspi GPU + */ +enum { + MBOX_TAG_EXECUTE_QPU = 0x00030011, // QPU: Calls The QPU Function At Given (Bus) Address And With Arguments Given (Response: Number Of QPUs, Control, No Flush, Timeout In ms) + MBOX_TAG_ENABLE_QPU = 0x00030012, // QPU: Enables The QPU (Response: Enable State) +}; + +/* + * raspi HDMI + */ +#define MBOX_TAG_GET_EDID_BLOCK 0x00030020 // HDMI: Read Specificed EDID Block From Attached HDMI/DVI Device (Response: Block Number, Status, EDID Block (128 Bytes)) + +/* + * raspi NOTIFY + */ +#define MBOX_TAG_NOTIFY_REBOOT 0x00030048 +#define MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 + +#define MBOX_ADDR 0x08000000 +extern size_t mbox_addr; + +#define RES_CLK_ID (0x000000000) +#define EMMC_CLK_ID (0x000000001) +#define UART_CLK_ID (0x000000002) +#define ARM_CLK_ID (0x000000003) +#define CORE_CLK_ID (0x000000004) +#define V3D_CLK_ID (0x000000005) +#define H264_CLK_ID (0x000000006) +#define ISP_CLK_ID (0x000000007) +#define SDRAM_CLK_ID (0x000000008) +#define PIXEL_CLK_ID (0x000000009) +#define PWM_CLK_ID (0x00000000a) + +int mbox_call(unsigned char ch, int mmu_enable); +int bcm271x_notify_reboot(void); +int bcm271x_notify_xhci_reset(void); +int bcm271x_gpu_enable(void); +int bcm271x_mbox_hardware_get_model(void); +int bcm271x_mbox_hardware_get_revison(void); +int bcm271x_mbox_hardware_get_mac_address(uint8_t * mac); +int bcm271x_mbox_hardware_get_serial(rt_uint64_t* sn); +int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size); +int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size); +int bcm271x_mbox_clock_get_turbo(void); +int bcm271x_mbox_clock_set_turbo(int level); +int bcm271x_mbox_clock_get_state(int id); +int bcm271x_mbox_clock_set_state(int id, int state); +int bcm271x_mbox_clock_get_rate(int id); +int bcm271x_mbox_clock_set_rate(int id, int rate); +int bcm271x_mbox_clock_get_max_rate(int id); +int bcm271x_mbox_clock_get_min_rate(int id); +int bcm271x_mbox_power_get_state(int id); +int bcm271x_mbox_power_set_state(int id, int state); +int bcm271x_mbox_temp_get(void); +int bcm271x_mbox_temp_get_max(void); + +#endif diff --git a/bsp/raspberry-pi/raspi4-64/drivers/raspi4.h b/bsp/raspberry-pi/raspi4-64/drivers/raspi4.h new file mode 100644 index 0000000000000000000000000000000000000000..f3e6ed89274fd7a91452bafb4f950cc2437ba5c2 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-64/drivers/raspi4.h @@ -0,0 +1,189 @@ +#ifndef __RASPI4_H__ +#define __RASPI4_H__ + +//https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/rpi_DATA_2711_1p0.pdf + +#define __REG32(x) (*((volatile unsigned int *)(x))) +#define __REG16(x) (*((volatile unsigned short *)(x))) + +/* GIC IRQ MAX */ +#define MAX_HANDLERS (256) + +/* base address */ +#define PER_BASE (0xFE000000) + +//gpio offset +#define GPIO_BASE_OFFSET (0x00200000) + + +#define PL011_UART_BASE_OFFSET (0x00201000) +//pl011 offset +#define PL011_UART0_BASE_OFFSET (0x00201000) +#define PL011_UART2_BASE_OFFSET (0x00201400) +#define PL011_UART3_BASE_OFFSET (0x00201600) +#define PL011_UART4_BASE_OFFSET (0x00201800) +#define PL011_UART5_BASE_OFFSET (0x00201A00) + +//pactl cs offset +#define PACTL_CS_OFFSET (0x00204E00) + +//aux offset +#define AUX_BASE_OFFSET (0x00215000) + +/* GPIO */ +#define GPIO_BASE_ADDR (PER_BASE + GPIO_BASE_OFFSET) +extern size_t gpio_base_addr; +#define GPIO_BASE (gpio_base_addr) +#define GPIO_IRQ_NUM (3) //40 pin mode +#define IRQ_GPIO0 (96 + 49) //bank0 (0 to 27) +#define IRQ_GPIO1 (96 + 50) //bank1 (28 to 45) +#define IRQ_GPIO2 (96 + 51) //bank2 (46 to 57) +#define IRQ_GPIO3 (96 + 52) //bank3 + +/* Timer (ARM side) */ +#define ARM_TIMER_IRQ (64) +extern size_t arm_timer_base; +#define ARM_TIMER_BASE (PER_BASE + 0xB000) +#define ARM_TIMER_LOAD HWREG32(arm_timer_base + 0x400) +#define ARM_TIMER_VALUE HWREG32(arm_timer_base + 0x404) +#define ARM_TIMER_CTRL HWREG32(arm_timer_base + 0x408) +#define ARM_TIMER_IRQCLR HWREG32(arm_timer_base + 0x40C) +#define ARM_TIMER_RAWIRQ HWREG32(arm_timer_base + 0x410) +#define ARM_TIMER_MASKIRQ HWREG32(arm_timer_base + 0x414) +#define ARM_TIMER_RELOAD HWREG32(arm_timer_base + 0x418) +#define ARM_TIMER_PREDIV HWREG32(arm_timer_base + 0x41C) +#define ARM_TIMER_CNTR HWREG32(arm_timer_base + 0x420) + +/* UART PL011 */ +#define UART_BASE (PER_BASE + PL011_UART_BASE_OFFSET) +//extern uint32_t uart_base_addr; +#define UART0_BASE (UART_BASE + 0x0) +#define UART2_BASE (UART_BASE + 0x400) +#define UART3_BASE (UART_BASE + 0x600) +#define UART4_BASE (UART_BASE + 0x800) +#define UART5_BASE (UART_BASE + 0xA00) +#define IRQ_AUX_UART (96 + 29) +#define UART_REFERENCE_CLOCK (48000000) + +/* AUX */ +//#define AUX_BASE_ADDR (PER_BASE + AUX_BASE_OFFSET) +//extern uint32_t aux_addr; +//#define AUX_BASE (aux_addr + 0x0) + +#define AUX_BASE (PER_BASE + AUX_BASE_OFFSET) +#define IRQ_PL011 (96 + 57) + +/* Peripheral IRQ OR-ing */ +#define PACTL_CS_ADDR (PER_BASE + PACTL_CS_OFFSET) +extern size_t pactl_cs_base; +#define PACTL_CS HWREG32(pactl_cs_base) +typedef enum +{ + IRQ_SPI0 = 0x00000000, + IRQ_SPI1 = 0x00000002, + IRQ_SPI2 = 0x00000004, + IRQ_SPI3 = 0x00000008, + IRQ_SPI4 = 0x00000010, + IRQ_SPI5 = 0x00000020, + IRQ_SPI6 = 0x00000040, + IRQ_I2C0 = 0x00000100, + IRQ_I2C1 = 0x00000200, + IRQ_I2C2 = 0x00000400, + IRQ_I2C3 = 0x00000800, + IRQ_I2C4 = 0x00001000, + IRQ_I2C5 = 0x00002000, + IRQ_I2C6 = 0x00004000, + IRQ_I2C7 = 0x00008000, + IRQ_UART5 = 0x00010000, + IRQ_UART4 = 0x00020000, + IRQ_UART3 = 0x00040000, + IRQ_UART2 = 0x00080000, + IRQ_UART0 = 0x00100000 +} PACTL_CS_VAL; + +// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control +#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040) +#define TIMER_IRQ 30 +#define NON_SECURE_TIMER_IRQ (1 << 1) + +/* GIC */ +#define INTC_BASE (0xff800000) +#define ARM_GIC_NR_IRQS (512) +#define ARM_GIC_MAX_NR (512) +#define GIC_V2_BASE (INTC_BASE + 0x00040000) +extern size_t gic_base_addr; +#define GIC_V2_DISTRIBUTOR_BASE (gic_base_addr + 0x1000) +#define GIC_V2_CPU_INTERFACE_BASE (gic_base_addr + 0x2000) +#define GIC_V2_HYPERVISOR_BASE (gic_base_addr + 0x4000) +#define GIC_V2_VIRTUAL_CPU_BASE (gic_base_addr + 0x6000) + +#define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE +#define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE + +#define GIC_IRQ_START 0 + +#define GIC_ACK_INTID_MASK 0x000003ff + + +//watchdog +#define WDT_BASE (PER_BASE + 0x00100000) +extern size_t wdt_base_addr; +#define PM_RSTC HWREG32(wdt_base_addr + 0x1c) +#define PM_RSTS HWREG32(wdt_base_addr + 0x20) +#define PM_WDOG HWREG32(wdt_base_addr + 0x24) + +#define PM_PASSWORD (0x5A000000) +#define PM_WDOG_TIME_SET (0x000fffff) +#define PM_RSTS_HADWRH_SET (0x00000040) +#define PM_RSTC_WRCFG_FULL_RESET (0x00000020) +#define PM_RSTC_WRCFG_CLR (0xffffffcf) +#define PM_RSTC_RESET (0x00000102) + +//timer +#define ST_BASE_OFFSET (0x003000) +#define STIMER_BASE (PER_BASE + ST_BASE_OFFSET) +extern size_t stimer_base_addr; +#define STIMER_CS __REG32(stimer_base_addr + 0x0000) +#define STIMER_CLO __REG32(stimer_base_addr + 0x0004) +#define STIMER_CHI __REG32(stimer_base_addr + 0x0008) +#define STIMER_C0 __REG32(stimer_base_addr + 0x000C) +#define STIMER_C1 __REG32(stimer_base_addr + 0x0010) +#define STIMER_C2 __REG32(stimer_base_addr + 0x0014) +#define STIMER_C3 __REG32(stimer_base_addr + 0x0018) + +#define DELAY_MICROS(micros) \ + do{ \ + rt_uint32_t compare = STIMER_CLO + micros * 25; \ + while (STIMER_CLO < compare); \ + } while (0) + +//External Mass Media Controller (SD Card) +#define MMC0_BASE_ADDR (PER_BASE+0x300000) +extern size_t mmc0_base_addr; +#define MMC2_BASE_ADDR (PER_BASE+0x340000) +extern size_t mmc2_base_addr; + +//mac +#define MAC_REG (void *)(0xfd580000) +extern uint8_t * mac_reg_base_addr; + +#define ETH_IRQ (160+29) + +#define SEND_DATA_NO_CACHE (0x08200000) +extern uint8_t * eth_send_no_cache; + +#define RECV_DATA_NO_CACHE (0x08400000) +extern uint8_t * eth_recv_no_cache; + +/* the basic constants and interfaces needed by gic */ +rt_inline size_t platform_get_gic_dist_base(void) +{ + return GIC_PL400_DISTRIBUTOR_PPTR; +} + +rt_inline size_t platform_get_gic_cpu_base(void) +{ + return GIC_PL400_CONTROLLER_PPTR; +} + +#endif diff --git a/bsp/raspberry-pi/raspi4-64/link.lds b/bsp/raspberry-pi/raspi4-64/link.lds index b7b2dcc32c4ea7a9014424da7dd11a5efca53466..6d0dfd4dcccb93dbe5675a9df187fd618b59015c 100644 --- a/bsp/raspberry-pi/raspi4-64/link.lds +++ b/bsp/raspberry-pi/raspi4-64/link.lds @@ -1,92 +1,61 @@ -/* - * File : link.lds - * COPYRIGHT (C) 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * 2017-5-30 bernard first version - */ - -/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */ - +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) SECTIONS { - . = 0x80000; - . = ALIGN(4096); + /*. = 0x0x208000; */ + . = 0xffff000000008000; + + __text_start = .; .text : { - KEEP(*(.text.entrypoint)) /* The entry point */ - *(.vectors) - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ + KEEP(*(.text.entrypoint)) + KEEP(*(.vectors)) + *(.text) + *(.text.*) - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; - *(COMMON) - /* section information for finsh shell */ - . = ALIGN(16); + . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) __fsymtab_end = .; - . = ALIGN(16); + . = ALIGN(4); __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; - . = ALIGN(16); + . = ALIGN(4); - /* section information for initial. */ - . = ALIGN(16); + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); __rt_init_start = .; KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; - . = ALIGN(16); - - . = ALIGN(16); - _etext = .; - } + } =0 + __text_end = .; - .eh_frame_hdr : + .ARM.exidx : { - *(.eh_frame_hdr) - *(.eh_frame_entry) + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; } - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } - . = ALIGN(16); - .data : - { - *(.data) - *(.data.*) - - *(.data1) - *(.data1.*) + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; - . = ALIGN(16); - _gp = ABSOLUTE(.); /* Base of small data */ - - *(.sdata) - *(.sdata.*) - } - - . = ALIGN(16); + . = ALIGN(4); .ctors : { PROVIDE(__ctors_start__ = .); @@ -103,51 +72,38 @@ SECTIONS PROVIDE(__dtors_end__ = .); } - . = ALIGN(16); - .bss : + . = ALIGN(8); + __data_start = .; + .data : { - PROVIDE(__bss_start = .); - *(.bss) - *(.bss.*) - *(.dynbss) - - PROVIDE(__bss_end = .); + *(.data) + *(.data.*) } - _end = .; + __data_end = .; + + . = ALIGN(8); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} + .comment 0 : { *(.comment) } + + __data_size = SIZEOF(.data); + __bss_size = SIZEOF(.bss); -__bss_size = (__bss_end - __bss_start)>>3; + _end = .; +} diff --git a/bsp/raspberry-pi/raspi4-64/rtconfig.h b/bsp/raspberry-pi/raspi4-64/rtconfig.h index bdde9d5f4a392964d6aca9e5d856f2982672ee99..62ab56578bd71ccbe6d76ac6cb7354e746bd3899 100644 --- a/bsp/raspberry-pi/raspi4-64/rtconfig.h +++ b/bsp/raspberry-pi/raspi4-64/rtconfig.h @@ -7,19 +7,21 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 +#define RT_USING_SMART #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 2048 +#define IDLE_THREAD_STACK_SIZE 8192 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 2048 +#define RT_TIMER_THREAD_STACK_SIZE 8192 #define RT_DEBUG +#define RT_DEBUG_COLOR /* Inter-Thread communication */ @@ -32,24 +34,31 @@ /* Memory Management */ #define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP #define RT_USING_SMALL_MEM #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE +#define RT_USING_INTERRUPT_INFO #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart" -#define RT_VER_NUM 0x40003 +#define RT_CONSOLEBUF_SIZE 512 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50000 #define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_ARM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0xffff000000000000 +#define PV_OFFSET 0x0001000000200000 #define ARCH_ARMV8 /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_STACK_SIZE 8192 #define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ @@ -58,35 +67,65 @@ /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH #define FINSH_THREAD_NAME "tshell" #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION #define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 8192 #define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT #define FINSH_ARG_MAX 10 /* Device virtual file system */ #define RT_USING_DFS #define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 #define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL -#define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_HWTIMER +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS #define RT_USING_PIN +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_RTC +#define RT_USING_SOFT_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 8192 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 8192 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_SPI +#define RT_USING_WDT /* Using USB */ @@ -94,18 +133,79 @@ /* POSIX layer and C standard library */ #define RT_USING_LIBC +#define RT_USING_MUSL #define RT_USING_POSIX +#define RT_USING_POSIX_MMAP +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_AIO +#define RT_POSIX_AIO_THREAD_STACK_SIZE 8192 +#define RT_USING_POSIX_CLOCKTIME /* Network */ /* Socket abstraction layer */ +#define RT_USING_SAL + +/* protocol stack implement */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX /* Network interface device */ +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 /* light weight TCP/IP stack */ +#define RT_USING_LWIP +#define RT_USING_LWIP202 +#define RT_LWIP_MEM_ALIGNMENT 4 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.137.100" +#define RT_LWIP_GWADDR "192.168.137.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 16 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 8 +#define RT_LWIP_TCP_PCB_NUM 8 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 8192 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 8192 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_REASSEMBLY_FRAG +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING /* AT commands */ @@ -115,6 +215,13 @@ /* Utilities */ +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define RT_LWP_SHM_MAX_NR 64 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 /* RT-Thread online packages */ @@ -147,6 +254,9 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ @@ -155,6 +265,15 @@ /* samples: kernel and components samples */ + +/* games: games run on RT-Thread console */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define BCM2711_SOC /* Hardware Drivers Config */ @@ -163,12 +282,18 @@ #define BSP_USING_UART #define RT_USING_UART0 +#define RT_USING_UART3 +#define RT_USING_UART4 #define BSP_USING_GIC #define BSP_USING_GIC400 #define BSP_USING_PIN #define BSP_USING_CORETIMER +#define BSP_USING_WDT +#define BSP_USING_SDIO +#define BSP_USING_SDIO0 /* Board Peripheral Drivers */ +#define BSP_USING_HDMI #endif diff --git a/bsp/raspberry-pi/raspi4-64/rtconfig.py b/bsp/raspberry-pi/raspi4-64/rtconfig.py index a1dd168d3d5f128b756affa3764d1198562b78e6..870c797b0e0c0eed13f32922a3f7adeb0f167259 100644 --- a/bsp/raspberry-pi/raspi4-64/rtconfig.py +++ b/bsp/raspberry-pi/raspi4-64/rtconfig.py @@ -2,26 +2,15 @@ import os # toolchains options ARCH ='aarch64' -CPU ='cortex-a72' -CROSS_TOOL ='gcc' - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = r'../../..' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - +CPU ='cortex-a' +CROSS_TOOL = 'gcc' PLATFORM = 'gcc' -EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' - -BUILD = 'debug' +EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin' +BUILD = 'debug' if PLATFORM == 'gcc': # toolchains - # PREFIX = 'arm-none-eabi-' - PREFIX = 'aarch64-elf-' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-' CC = PREFIX + 'gcc' CXX = PREFIX + 'g++' AS = PREFIX + 'gcc' @@ -31,21 +20,27 @@ if PLATFORM == 'gcc': SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -march=armv8-a -mtune=cortex-a72' - CFLAGS = DEVICE + ' -Wall' - AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' - LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + STRIP = PREFIX + 'strip' + CFPFLAGS = ' ' + AFPFLAGS = ' ' + DEVICE = ' -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' + + CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall' + CFLAGS = DEVICE + CFPFLAGS + ' -Wall -std=gnu99' + AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc' CPATH = '' LPATH = '' if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0 -gdwarf-2' + CXXFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS + CFLAGS += ' -Os' + CXXFLAGS += ' -Os' + CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti' DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' -POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n' +POST_ACTION += 'cp kernel7.img /tftpboot \n' diff --git a/bsp/realview-a8/rtconfig.h b/bsp/realview-a8/rtconfig.h index a83c9e020d11cc84bf94e81b0f0a3abdafa65896..a818feff63c424c3a8d413f8be51a18a3ec1ccc1 100644 --- a/bsp/realview-a8/rtconfig.h +++ b/bsp/realview-a8/rtconfig.h @@ -67,6 +67,8 @@ // #define RT_USING_SLAB //
+#define RT_USING_CACHE + //
#define RT_USING_DEVICE // diff --git a/bsp/stm32/stm32f401-st-nucleo/.config b/bsp/stm32/stm32f401-st-nucleo/.config index 00205aa5bf8bdf29544f7240143499c450cb9084..a1d2c659cc83d88984aaec5692f66ebcec35f899 100644 --- a/bsp/stm32/stm32f401-st-nucleo/.config +++ b/bsp/stm32/stm32f401-st-nucleo/.config @@ -7,6 +7,8 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -21,6 +23,7 @@ CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set # CONFIG_RT_DEBUG_THREAD_CONFIG is not set # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set @@ -62,11 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -110,6 +115,7 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 @@ -117,12 +123,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -130,10 +137,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -147,6 +154,7 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y # # Network @@ -158,14 +166,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -180,16 +188,9 @@ CONFIG_RT_USING_PIN=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set - -# -# ARM CMSIS -# -# CONFIG_RT_USING_CMSIS_OS is not set -# CONFIG_RT_USING_RTT_CMSIS is not set # CONFIG_RT_USING_LWP is not set # @@ -199,13 +200,20 @@ CONFIG_RT_USING_PIN=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -227,7 +235,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set # @@ -237,9 +248,32 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -247,6 +281,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -260,6 +296,10 @@ CONFIG_RT_USING_PIN=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -272,6 +312,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -283,40 +332,78 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers # - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -327,11 +414,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -342,37 +433,54 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set # # Privated Packages of RealThread # # CONFIG_PKG_USING_CODEC is not set # CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set # CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set # # Network Utilities # # CONFIG_PKG_USING_WICED is not set # CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_POWER_MANAGER is not set # CONFIG_PKG_USING_RT_OTA is not set # CONFIG_PKG_USING_RDBD_SRC is not set # CONFIG_PKG_USING_RTINSIGHT is not set # CONFIG_PKG_USING_SMARTCONFIG is not set - -# -# rtpkgs online packages -# -# CONFIG_PKG_USING_CSTRING is not set -# CONFIG_PKG_USING_ARGPARSE is not set -# CONFIG_PKG_USING_LIBBMPREAD is not set -# CONFIG_PKG_USING_LIBUTILS is not set -# CONFIG_PKG_USING_SAM is not set -# CONFIG_PKG_USING_LIBCALLBACK is not set -# CONFIG_PKG_USING_Z_EVENT is not set -# CONFIG_PKG_USING_LIBSTM32HAL is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -392,6 +500,10 @@ CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART2=y # CONFIG_BSP_UART2_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f401-st-nucleo/applications/SConscript b/bsp/stm32/stm32f401-st-nucleo/applications/SConscript index 6f66f7ab7360b02f3561ec14d3f28841190e7e83..80072aa77178b765581f76a1503a85d118fbac78 100644 --- a/bsp/stm32/stm32f401-st-nucleo/applications/SConscript +++ b/bsp/stm32/stm32f401-st-nucleo/applications/SConscript @@ -2,10 +2,8 @@ import rtconfig from building import * cwd = GetCurrentDir() -CPPPATH = [cwd, str(Dir('#'))] -src = Split(""" -main.c -""") +CPPPATH = [cwd] +src = Glob("*.c") group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/stm32/stm32f401-st-nucleo/rtconfig.h b/bsp/stm32/stm32f401-st-nucleo/rtconfig.h index 5aeb7b7cedf90da6d970981d6d6c3ca35027fd1d..91c8ce03b08e2cea88892971611d0b2a6b54a462 100644 --- a/bsp/stm32/stm32f401-st-nucleo/rtconfig.h +++ b/bsp/stm32/stm32f401-st-nucleo/rtconfig.h @@ -38,7 +38,8 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart2" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x40003 +#define RT_USING_CPU_FFS #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 @@ -81,24 +82,22 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* Using WiFi */ - - /* Using USB */ /* POSIX layer and C standard library */ +#define RT_LIBC_USING_TIME /* Network */ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -110,9 +109,6 @@ /* Utilities */ -/* ARM CMSIS */ - - /* RT-Thread online packages */ /* IoT - internet of things */ @@ -146,8 +142,6 @@ /* peripheral libraries and drivers */ -/* sensors drivers */ - /* miscellaneous packages */ @@ -160,9 +154,6 @@ /* Network Utilities */ - -/* rtpkgs online packages */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F4 diff --git a/bsp/stm32/stm32f411-st-nucleo/.config b/bsp/stm32/stm32f411-st-nucleo/.config index e23cf3dd0be1396101bbcd2731da419080bc8000..02e51ffd9266e5a0499ecc848f7a5f53f4801948 100644 --- a/bsp/stm32/stm32f411-st-nucleo/.config +++ b/bsp/stm32/stm32f411-st-nucleo/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -64,11 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x50000 +# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -87,6 +90,7 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 @@ -97,9 +101,6 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -CONFIG_FINSH_USING_MSH_ONLY=y CONFIG_FINSH_ARG_MAX=10 # @@ -120,12 +121,16 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -133,10 +138,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -150,6 +155,7 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y # # Network @@ -161,14 +167,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -183,10 +189,10 @@ CONFIG_RT_USING_PIN=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_LWP is not set # @@ -196,14 +202,20 @@ CONFIG_RT_USING_PIN=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -225,7 +237,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set # @@ -235,9 +250,38 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set # # security packages @@ -245,6 +289,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -259,6 +305,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set # # tools packages @@ -267,28 +322,93 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set # # system packages # + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set # # peripheral libraries and drivers @@ -296,19 +416,82 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages @@ -318,12 +501,18 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -334,8 +523,72 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set - +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set +# CONFIG_PKG_USING_RIL is not set +# CONFIG_PKG_USING_WATCH_DCM_SVC is not set +# CONFIG_PKG_USING_GUI_TEST is not set +# CONFIG_PKG_USING_PMEM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -360,6 +613,8 @@ CONFIG_BSP_USING_UART2=y # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f411-st-nucleo/rtconfig.h b/bsp/stm32/stm32f411-st-nucleo/rtconfig.h index cc625a5f65ded827a4b33613658f7f8636e80af6..af1b0ae3506314097214bdffe938e4413d6bd8e1 100644 --- a/bsp/stm32/stm32f411-st-nucleo/rtconfig.h +++ b/bsp/stm32/stm32f411-st-nucleo/rtconfig.h @@ -39,7 +39,8 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart2" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x50000 +#define RT_USING_CPU_FFS #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 @@ -57,6 +58,7 @@ /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH #define FINSH_THREAD_NAME "tshell" #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -65,9 +67,6 @@ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_USING_MSH_ONLY #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -81,24 +80,22 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* Using WiFi */ - - /* Using USB */ /* POSIX layer and C standard library */ +#define RT_LIBC_USING_TIME /* Network */ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -140,15 +137,32 @@ /* system packages */ +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + /* peripheral libraries and drivers */ +/* AI packages */ + + /* miscellaneous packages */ /* samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F4 diff --git a/bsp/stm32/stm32f746-st-disco/.config b/bsp/stm32/stm32f746-st-disco/.config index f71ec97d68b81ead3c9f3ebdbfd7acbfb409ff02..a394fc8d24b6608821331d73979fabb0235cc94b 100644 --- a/bsp/stm32/stm32f746-st-disco/.config +++ b/bsp/stm32/stm32f746-st-disco/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -64,12 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -121,12 +123,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -134,15 +137,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using Hardware Crypto drivers -# +# CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_HWCRYPTO is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -154,8 +152,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set # # Network @@ -176,11 +175,6 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LWIP is not set -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set - # # AT commands # @@ -206,14 +200,20 @@ CONFIG_RT_USING_PIN=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -235,6 +235,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -246,13 +248,32 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set # CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -260,6 +281,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -274,6 +297,9 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -286,6 +312,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -297,6 +332,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -304,6 +340,16 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -311,6 +357,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -319,15 +366,44 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set # CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -338,12 +414,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -355,6 +434,53 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F7=y @@ -387,6 +513,9 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_SDIO is not set # CONFIG_BSP_USING_FMC is not set # CONFIG_BSP_USING_LTDC is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f746-st-disco/board/Kconfig b/bsp/stm32/stm32f746-st-disco/board/Kconfig index 378eafb110f7d634f0e2b52de07f8a113dc5a926..2816b47814c8e73b2a65b088d89c50a8b8133e24 100644 --- a/bsp/stm32/stm32f746-st-disco/board/Kconfig +++ b/bsp/stm32/stm32f746-st-disco/board/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32F746NG select SOC_SERIES_STM32F7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32f746-st-disco/rtconfig.h b/bsp/stm32/stm32f746-st-disco/rtconfig.h index da5b84d4a9020b10faaf90bb3c90e23a71ad7092..0bbc6a243b3cbe3b8c7cc595e398ab495d6f4495 100644 --- a/bsp/stm32/stm32f746-st-disco/rtconfig.h +++ b/bsp/stm32/stm32f746-st-disco/rtconfig.h @@ -39,9 +39,10 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 -#define ARCH_ARM +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -84,17 +85,12 @@ #define RT_USING_HWTIMER #define RT_USING_PIN -/* Using Hardware Crypto drivers */ - - -/* Using WiFi */ - - /* Using USB */ /* POSIX layer and C standard library */ +#define RT_USING_LIBC /* Network */ @@ -107,9 +103,6 @@ /* light weight TCP/IP stack */ -/* Modbus master and slave stack */ - - /* AT commands */ @@ -158,6 +151,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F7 diff --git a/bsp/stm32/stm32f767-atk-apollo/.config b/bsp/stm32/stm32f767-atk-apollo/.config index 0f1f57a9860318a90342a4cb884170f9eae66969..1335385dc5b575438e4e1d440a8a93b7d30c0143 100644 --- a/bsp/stm32/stm32f767-atk-apollo/.config +++ b/bsp/stm32/stm32f767-atk-apollo/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -64,12 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -121,8 +123,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -148,9 +152,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set # # Network @@ -196,10 +200,15 @@ CONFIG_RT_LIBC_USING_TIME=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -226,6 +235,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -237,7 +248,10 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -245,6 +259,21 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_AIRKISS_OPEN is not set # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -252,6 +281,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -267,6 +298,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -279,6 +312,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -290,6 +332,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -298,6 +341,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -305,6 +357,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -313,10 +366,16 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -324,7 +383,27 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -335,12 +414,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -353,6 +435,52 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set # CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F7=y @@ -393,6 +521,7 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_I2C2 is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_USBH is not set # CONFIG_BSP_USING_SDIO is not set CONFIG_BSP_USING_LTDC=y # CONFIG_BSP_USING_CRC is not set diff --git a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig index 82efc63223edaa0a00d6b37f8ddaadf25ad9ea12..b12e02859b7780cae9688edefc2a5c18dbae541d 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32F767IG select SOC_SERIES_STM32F7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32f767-atk-apollo/rtconfig.h b/bsp/stm32/stm32f767-atk-apollo/rtconfig.h index af5b56592b323826932a2ba6f9ef2990101b3a40..78c896456aa2f046c624391bde73e59f761c4429 100644 --- a/bsp/stm32/stm32f767-atk-apollo/rtconfig.h +++ b/bsp/stm32/stm32f767-atk-apollo/rtconfig.h @@ -40,9 +40,10 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 -#define ARCH_ARM +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -89,7 +90,7 @@ /* POSIX layer and C standard library */ -#define RT_LIBC_USING_TIME +#define RT_USING_LIBC /* Network */ @@ -150,6 +151,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F7 diff --git a/bsp/stm32/stm32f767-fire-challenger/.config b/bsp/stm32/stm32f767-fire-challenger/.config index d9bdefcf566bedff7c8417e8f5c58105280e54ba..de5772b051fcaf92f6e9979ea55453a26b07fc05 100644 --- a/bsp/stm32/stm32f767-fire-challenger/.config +++ b/bsp/stm32/stm32f767-fire-challenger/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -64,12 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -121,12 +123,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -134,15 +137,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using Hardware Crypto drivers -# +# CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_HWCRYPTO is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -154,8 +152,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set # # Network @@ -176,11 +175,6 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LWIP is not set -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set - # # AT commands # @@ -206,14 +200,20 @@ CONFIG_RT_USING_PIN=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -235,6 +235,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -246,12 +248,32 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -259,6 +281,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -273,6 +297,9 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -285,6 +312,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -296,6 +332,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -303,6 +340,16 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -310,7 +357,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -319,15 +366,44 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set # CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -338,12 +414,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -355,6 +434,53 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F7=y @@ -393,6 +519,9 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_SDIO is not set # CONFIG_BSP_USING_FMC is not set # CONFIG_BSP_USING_LTDC is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig index 1769b1cfd717188909d3adc3b57c4d2ed02b4a75..0ec3596030e761fb11e585472ad4cf526c8b809c 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32F767IG select SOC_SERIES_STM32F7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32f767-fire-challenger/rtconfig.h b/bsp/stm32/stm32f767-fire-challenger/rtconfig.h index 5cdccf196042a3199d6432c5bdc4f6558ce72688..d448b583161195e2d0af8a2a39d41a22ac8af38b 100644 --- a/bsp/stm32/stm32f767-fire-challenger/rtconfig.h +++ b/bsp/stm32/stm32f767-fire-challenger/rtconfig.h @@ -40,9 +40,10 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 -#define ARCH_ARM +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -83,17 +84,12 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* Using Hardware Crypto drivers */ - - -/* Using WiFi */ - - /* Using USB */ /* POSIX layer and C standard library */ +#define RT_USING_LIBC /* Network */ @@ -106,9 +102,6 @@ /* light weight TCP/IP stack */ -/* Modbus master and slave stack */ - - /* AT commands */ @@ -157,6 +150,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F7 diff --git a/bsp/stm32/stm32f767-st-nucleo/.config b/bsp/stm32/stm32f767-st-nucleo/.config new file mode 100644 index 0000000000000000000000000000000000000000..9929d6fa1fc3afb3690fa6aae344e3745dbd6281 --- /dev/null +++ b/bsp/stm32/stm32f767-st-nucleo/.config @@ -0,0 +1,529 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F7=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F767ZI=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_USB_TO_USART=y +# CONFIG_BSP_USING_ETH is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART3=y +# CONFIG_BSP_UART3_RX_USING_DMA is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32f767-st-nucleo/board/Kconfig b/bsp/stm32/stm32f767-st-nucleo/board/Kconfig index 849b397b3c1dba29991ede180854b5d8eae4ce4b..8e884601478daf598bc9b5be29610a1f5ec5642d 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f767-st-nucleo/board/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32F767ZI select SOC_SERIES_STM32F7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32f767-st-nucleo/rtconfig.h b/bsp/stm32/stm32f767-st-nucleo/rtconfig.h index 93fffb6a8fefe4a1eddec11c9688735fc5389555..e48e0d09451837cc3f7b6a8d15699b1ad37a7c5a 100644 --- a/bsp/stm32/stm32f767-st-nucleo/rtconfig.h +++ b/bsp/stm32/stm32f767-st-nucleo/rtconfig.h @@ -16,8 +16,10 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 #define RT_DEBUG -#define RT_DEBUG_COLOR /* Inter-Thread communication */ @@ -38,8 +40,10 @@ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart3" -#define RT_VER_NUM 0x40000 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE +#define RT_USING_CPU_FFS #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -84,11 +88,9 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* Using WiFi */ - - /* Using USB */ @@ -102,10 +104,10 @@ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -117,9 +119,6 @@ /* Utilities */ -/* ARM CMSIS */ - - /* RT-Thread online packages */ /* IoT - internet of things */ @@ -157,12 +156,13 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ -/* example package: hello */ +/* Privated Packages of RealThread */ + + +/* Network Utilities */ #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F7 diff --git a/bsp/stm32/stm32f769-st-disco/.config b/bsp/stm32/stm32f769-st-disco/.config index 9593efe39dc797a7f85be4bd00f31f3b38b1f7e5..671f310108e5117cc273397ab0c058bf91cc716e 100644 --- a/bsp/stm32/stm32f769-st-disco/.config +++ b/bsp/stm32/stm32f769-st-disco/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -65,11 +66,12 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x40003 -CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -121,6 +123,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -149,9 +152,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set # # Network @@ -176,6 +179,7 @@ CONFIG_RT_USING_LWIP=y CONFIG_RT_USING_LWIP202=y # CONFIG_RT_USING_LWIP212 is not set # CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 CONFIG_RT_LWIP_IGMP=y CONFIG_RT_LWIP_ICMP=y # CONFIG_RT_LWIP_SNMP is not set @@ -322,6 +326,9 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -347,6 +354,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -367,6 +375,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_BS8116A is not set # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -395,6 +404,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -445,6 +455,10 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_QLED is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -482,6 +496,48 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_MDNS is not set +# CONFIG_PKG_USING_UPNP is not set +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F7=y diff --git a/bsp/stm32/stm32f769-st-disco/board/Kconfig b/bsp/stm32/stm32f769-st-disco/board/Kconfig index 03b60cf1c0d7fb4ed79387a1f9eec6f1e2360364..57eb4c81d8b6533403a5440a3aa8749a82340fa1 100644 --- a/bsp/stm32/stm32f769-st-disco/board/Kconfig +++ b/bsp/stm32/stm32f769-st-disco/board/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32F769NI select SOC_SERIES_STM32F7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32f769-st-disco/rtconfig.h b/bsp/stm32/stm32f769-st-disco/rtconfig.h index 1639b90bd045c478b0600f77c41a60325c4fde15..b500f587f7a4ab7ce82cb119f2687523501a519d 100644 --- a/bsp/stm32/stm32f769-st-disco/rtconfig.h +++ b/bsp/stm32/stm32f769-st-disco/rtconfig.h @@ -40,8 +40,9 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x40003 -#define ARCH_ARM +#define RT_USING_CACHE #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -88,7 +89,7 @@ /* POSIX layer and C standard library */ -#define RT_LIBC_USING_TIME +#define RT_USING_LIBC /* Network */ @@ -103,6 +104,7 @@ #define RT_USING_LWIP #define RT_USING_LWIP202 +#define RT_LWIP_MEM_ALIGNMENT 4 #define RT_LWIP_IGMP #define RT_LWIP_ICMP #define RT_LWIP_DNS @@ -190,6 +192,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F7 diff --git a/bsp/stm32/stm32h743-atk-apollo/.config b/bsp/stm32/stm32h743-atk-apollo/.config index 294f481a7e1a81ab817ae562cd6bdd6124ac8992..261be9e1f350617ea7cbf10db21910b14053d94d 100644 --- a/bsp/stm32/stm32h743-atk-apollo/.config +++ b/bsp/stm32/stm32h743-atk-apollo/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -65,11 +66,12 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x40003 -CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -107,10 +109,6 @@ CONFIG_FINSH_ARG_MAX=10 # Device virtual file system # # CONFIG_RT_USING_DFS is not set -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set # # Device Drivers @@ -125,8 +123,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -152,9 +152,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set # # Network @@ -200,10 +200,15 @@ CONFIG_RT_LIBC_USING_TIME=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -230,6 +235,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -241,7 +248,10 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -252,6 +262,18 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_PROTOBUF_C is not set # CONFIG_PKG_USING_ONNX_PARSER is not set # CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -259,6 +281,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -275,6 +299,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -287,6 +312,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -298,6 +332,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -306,6 +341,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -313,6 +357,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -321,10 +366,16 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -332,8 +383,27 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set # CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -368,6 +438,49 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32H7=y @@ -397,7 +510,10 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_QSPI is not set # CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_WDT is not set # CONFIG_BSP_USING_CRC is not set # CONFIG_BSP_USING_RNG is not set diff --git a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig index e2d7618062e28bcd0510fe2a397de26508007f0e..a4344fc47bc92b14e141c4fb4d14269a28afcf8a 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32H743II select SOC_SERIES_STM32H7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32h743-atk-apollo/rtconfig.h b/bsp/stm32/stm32h743-atk-apollo/rtconfig.h index bc9a31c7ab7a3651107f18047ff8094ece8fc74f..c1cc134a463a0d50b6b014f37008776ce05a01e7 100644 --- a/bsp/stm32/stm32h743-atk-apollo/rtconfig.h +++ b/bsp/stm32/stm32h743-atk-apollo/rtconfig.h @@ -39,8 +39,9 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x40003 -#define ARCH_ARM +#define RT_USING_CACHE #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -87,7 +88,7 @@ /* POSIX layer and C standard library */ -#define RT_LIBC_USING_TIME +#define RT_USING_LIBC /* Network */ @@ -148,6 +149,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32H7 diff --git a/bsp/stm32/stm32h743-st-nucleo/.config b/bsp/stm32/stm32h743-st-nucleo/.config index b8dc6d8f710b36ae170446af4b430d414c7a67cd..7194cecf7ea404c9f7ff3119a48d96a903ebf6b5 100644 --- a/bsp/stm32/stm32h743-st-nucleo/.config +++ b/bsp/stm32/stm32h743-st-nucleo/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -64,12 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart3" -CONFIG_RT_VER_NUM=0x40002 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -121,8 +123,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -148,9 +152,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set # # Network @@ -196,10 +200,15 @@ CONFIG_RT_LIBC_USING_TIME=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -226,6 +235,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -238,8 +248,10 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -253,6 +265,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -260,6 +281,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -276,6 +299,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -290,6 +314,13 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -301,6 +332,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -309,6 +341,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -316,6 +357,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -324,6 +366,10 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set @@ -337,9 +383,27 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set # CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -376,6 +440,47 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32H7=y diff --git a/bsp/stm32/stm32h743-st-nucleo/board/Kconfig b/bsp/stm32/stm32h743-st-nucleo/board/Kconfig index a693c29f5a44b6b2df977d55ce2caa834a00605a..bde3b6ada4fa1cc9584160d7148f0d64184e9d48 100644 --- a/bsp/stm32/stm32h743-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32h743-st-nucleo/board/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32H743ZI select SOC_SERIES_STM32H7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32h743-st-nucleo/rtconfig.h b/bsp/stm32/stm32h743-st-nucleo/rtconfig.h index cedb0c06ce3a8b1e2e8bd6796e8464508d74b1a5..90d2ef7e77e51a4df1e4154f030ead7d838b26cb 100644 --- a/bsp/stm32/stm32h743-st-nucleo/rtconfig.h +++ b/bsp/stm32/stm32h743-st-nucleo/rtconfig.h @@ -38,9 +38,10 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart3" -#define RT_VER_NUM 0x40002 -#define ARCH_ARM +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -87,7 +88,7 @@ /* POSIX layer and C standard library */ -#define RT_LIBC_USING_TIME +#define RT_USING_LIBC /* Network */ @@ -148,6 +149,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32H7 diff --git a/bsp/stm32/stm32h747-st-discovery/.config b/bsp/stm32/stm32h747-st-discovery/.config index 79e85b0bf1e3211b4a9527e61747f476edd95bcc..56172a7a83a714ddab0929219a53f6794471fad0 100644 --- a/bsp/stm32/stm32h747-st-discovery/.config +++ b/bsp/stm32/stm32h747-st-discovery/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -65,11 +66,12 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x40003 -CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -121,8 +123,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -148,9 +152,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set # # Network @@ -196,10 +200,15 @@ CONFIG_RT_LIBC_USING_TIME=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -226,6 +235,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -237,8 +248,10 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -249,6 +262,18 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_PROTOBUF_C is not set # CONFIG_PKG_USING_ONNX_PARSER is not set # CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -256,6 +281,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -272,6 +299,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -284,6 +312,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -295,6 +332,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -303,6 +341,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -310,6 +357,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -318,10 +366,16 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -329,8 +383,27 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set # CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -365,6 +438,49 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32H7=y diff --git a/bsp/stm32/stm32h747-st-discovery/board/Kconfig b/bsp/stm32/stm32h747-st-discovery/board/Kconfig index e1f1d01abaa8e1b62d3cc805cb4b37bed52e0891..a1baef364baf7d0f31145b499d19e2e263a96134 100644 --- a/bsp/stm32/stm32h747-st-discovery/board/Kconfig +++ b/bsp/stm32/stm32h747-st-discovery/board/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32H747XI select SOC_SERIES_STM32H7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32h747-st-discovery/rtconfig.h b/bsp/stm32/stm32h747-st-discovery/rtconfig.h index 9838f7ab280272e6f76f2d78b5808710f4652cab..c0ac0199eac6e66e4839c102eb7eac25cd0332fb 100644 --- a/bsp/stm32/stm32h747-st-discovery/rtconfig.h +++ b/bsp/stm32/stm32h747-st-discovery/rtconfig.h @@ -39,8 +39,9 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x40003 -#define ARCH_ARM +#define RT_USING_CACHE #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -87,7 +88,7 @@ /* POSIX layer and C standard library */ -#define RT_LIBC_USING_TIME +#define RT_USING_LIBC /* Network */ @@ -148,6 +149,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32H7 diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/.config b/bsp/stm32/stm32h750-armfly-h7-tool/.config index 23b131643f0c5fe093f35e3403e05ced51a274f1..8c68c7a516bc2a3faf0980064061c10bcf74e177 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/.config +++ b/bsp/stm32/stm32h750-armfly-h7-tool/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -64,12 +65,13 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -121,8 +123,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -167,9 +171,9 @@ CONFIG_RT_HWCRYPTO_USING_CRC=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set # # Network @@ -215,10 +219,15 @@ CONFIG_RT_LIBC_USING_TIME=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -245,6 +254,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -257,8 +267,10 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -270,6 +282,17 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_ONNX_PARSER is not set # CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -277,6 +300,8 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -293,6 +318,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -305,6 +331,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -316,6 +351,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -324,6 +360,15 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -331,6 +376,7 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -339,10 +385,16 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -350,9 +402,27 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set # CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -387,6 +457,49 @@ CONFIG_RT_LIBC_USING_TIME=y # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32H7=y @@ -398,6 +511,10 @@ CONFIG_SOC_STM32H750IB=y # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_QSPI_FLASH is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_ESP32 is not set # # On-chip Peripheral Drivers @@ -405,6 +522,14 @@ CONFIG_SOC_STM32H750IB=y CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y +CONFIG_BSP_USING_UART4=y +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_QSPI_USING_DMA is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_USBD is not set CONFIG_BSP_USING_CRC=y CONFIG_BSP_USING_RNG=y CONFIG_BSP_USING_UDID=y diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/Kconfig b/bsp/stm32/stm32h750-armfly-h7-tool/board/Kconfig index 0f3d798f717683a60d337c22fcd134e8702ce509..65b3d92050d332b48959e9ecabe9bd77d3c1c396 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/board/Kconfig +++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32H750IB select SOC_SERIES_STM32H7 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN + select RT_USING_CACHE default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.h b/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.h index 4390e994d2d67dceb990a9fe12541cdf5bc93ab8..c2586f44d7642dde3f8118e4cbef434ec2461c8a 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.h +++ b/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.h @@ -38,9 +38,10 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 -#define ARCH_ARM +#define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M7 @@ -93,7 +94,7 @@ /* POSIX layer and C standard library */ -#define RT_LIBC_USING_TIME +#define RT_USING_LIBC /* Network */ @@ -154,6 +155,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32H7 @@ -163,11 +170,13 @@ /* Onboard Peripheral Drivers */ + /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART1 +#define BSP_USING_UART4 #define BSP_USING_CRC #define BSP_USING_RNG #define BSP_USING_UDID diff --git a/bsp/x86/.config b/bsp/x86/.config new file mode 100644 index 0000000000000000000000000000000000000000..fb4eb2d459125b2377ee4f4f179f0cee59a1fc94 --- /dev/null +++ b/bsp/x86/.config @@ -0,0 +1,724 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=20 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=16384 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=16384 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0x00000000 +CONFIG_PV_OFFSET=0 + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=3 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=3 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y +# CONFIG_RT_USING_MLIB is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_USING_POSIX_CLOCKTIME=y +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +CONFIG_SAL_USING_POSIX=y + +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +CONFIG_NETDEV_USING_IPV6=y +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=1 +CONFIG_NETDEV_IPV6_SCOPES=y + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP202 is not set +CONFIG_RT_USING_LWIP212=y +CONFIG_RT_USING_LWIP_IPV6=y +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8192 +CONFIG_RT_LWIP_TCP_WND=8192 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=8192 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_RT_USING_ARDUINO is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_USB_STACK is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +CONFIG_BOARD_x86=y +CONFIG_BSP_USING_DIRECT_UART=y +CONFIG_BSP_DRV_UART=y +CONFIG_RT_USING_UART0=y +# CONFIG_RT_USING_UART1 is not set +CONFIG_BSP_DRV_AHCI=y diff --git a/bsp/x86/.gitignore b/bsp/x86/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..108b9aba15717c648c3940e8eadc51e8910a1239 --- /dev/null +++ b/bsp/x86/.gitignore @@ -0,0 +1,31 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +*.iso +# grub efi +*.efi + +grub-2.04 +*.img \ No newline at end of file diff --git a/bsp/x86/Kconfig b/bsp/x86/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..03b2daa770b3dbd2856a2b152919f59060026639 --- /dev/null +++ b/bsp/x86/Kconfig @@ -0,0 +1,35 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config BOARD_x86 + bool + select ARCH_X86 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_CACHE + select BSP_USING_UART + select ARCH_MM_MMU + default y + +config RT_USING_USERSPACE + bool + default y + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/x86/Makefile b/bsp/x86/Makefile index eb4654193b5100b8550a5bd399908da140cb04a7..acbcaba2a951d71870c32557f2778c4a595b470b 100644 --- a/bsp/x86/Makefile +++ b/bsp/x86/Makefile @@ -1,46 +1,81 @@ +# tools +GRUB_DIR := grub-2.04 +OS_NAME := rtthread +QEMU := qemu-system-i386 +GDB := gdb +TRUNC := truncate +MCOPY := mcopy -CC = gcc -O0 -m32 -fno-builtin -fno-stack-protector -nostdinc -nostdlib -LD = ld -melf_i386 -nostdlib +# file name +DISK0 := disk0.img +DISK1 := disk1.img +SZ_DISK0 := 64M +SZ_DISK1 := 64M +MKFS := mkfs.fat +ROM_DIR := ../../../userapps/root -all: rtthread rtsym exe dll floppy.img - @mkdir -p tmp - @sudo mount -t vfat floppy.img tmp -o loop - @sudo cp -fv rtthread.elf tmp/boot/oskernel - @sudo rm tmp/bin/* -fr - @sudo cp out/*.mo tmp/bin/ -fv - @sudo umount tmp +RTTHREAD_ELF:= rtthread.elf -rtthread: - @scons +# config graphic window ? (y/n) +QEMU_WINDOW ?= n -rtsym: - @./src/extract.sh ./rtthread-ia32.map ./src/rt_thread_sym.h +# config netcard ? (y/n) +QEMU_NETCARD ?= y -obj: - mkdir -p obj +# netcard name: rtl8139/pcnet +QEMU_NETCARD_NAME ?=pcnet -out: - mkdir -p out +# netcard type: tap/user +QEMU_NET_MODE ?=user -dll: obj out - $(CC) -c -fPIC -Isrc src/hello.c -o out/hello.o - $(CC) -s -Wl,-shared,-melf_i386,--entry=main -o out/hello.mo out/hello.o +# qemu args +QEMU_ARGS := -m 256m \ + -rtc base=localtime \ + -boot d \ + -cdrom $(OS_NAME).iso + +ifeq ($(QEMU_WINDOW),y) + QEMU_ARGS += -serial stdio +else + QEMU_ARGS += -nographic +endif -disasm: obj out - $(CC) -shared -S -fPIC -Isrc src/hello.c -o obj/hello.s - cat obj/hello.s - objdump --disassemble out/hello.mo +ifeq ($(QEMU_NETCARD),y) + QEMU_ARGS += -net nic,model=$(QEMU_NETCARD_NAME) +ifeq ($(QEMU_NET_MODE),tap) + QEMU_ARGS += -net tap,ifname=tap0,script=no,downscript=no +else + QEMU_ARGS += -net user +endif -exe: obj out +endif +QEMU_ARGS +=-drive id=disk0,file=$(DISK0),format=raw,if=none \ + -drive id=disk1,file=$(DISK1),format=raw,if=none \ + -device ahci,id=ahci \ + -device ide-hd,drive=disk0,bus=ahci.0 \ + -device ide-hd,drive=disk1,bus=ahci.1 -clean: - scons -c clean - rm -fr build rtthread* out obj +all: makeiso makedisk + +makeiso: $(RTTHREAD_ELF) + @$(MAKE) -s -C $(GRUB_DIR) KERNEL=$(RTTHREAD_ELF) OS_NAME=$(OS_NAME) + +makedisk: + $(TRUNC) --size $(SZ_DISK0) $(DISK0) + $(TRUNC) --size $(SZ_DISK1) $(DISK1) + $(MKFS) -F32 $(DISK0) + -$(MCOPY) -i $(DISK0) $(ROM_DIR)/bin/*.elf :: -floppy.img: - wget https://github.com/bajdcc/tinix/raw/master/floppy.img +run: makedisk makeiso + $(QEMU) $(QEMU_ARGS) -# https://en.wikibooks.org/wiki/QEMU/Devices/Network -run: - qemu-system-i386 -fda floppy.img -boot a -m 64M -serial stdio -net nic,model=ne2k_pci +qemudbg: + $(QEMU) -S -gdb tcp::10001,ipv4 $(QEMU_ARGS) + +# 连接gdb server: target remote localhost:10001 +gdb: + $(GDB) $(RTTHREAD_ELF) + +clean: + @$(MAKE) -s -C $(GRUB_DIR) clean \ No newline at end of file diff --git a/bsp/x86/README.md b/bsp/x86/README.md new file mode 100644 index 0000000000000000000000000000000000000000..0c0aff4e4c314533dd36624617c0d9cc8b61dc4e --- /dev/null +++ b/bsp/x86/README.md @@ -0,0 +1,77 @@ +# RT-Thread Smart for x86 + +这是一份基础的RT-Thread Smart针对x86的版本、移植，主要是能够在qemu中执行。以下说明主要针对Linux的环境，如果是Windows环境，请使用Env工具，同时请自行处理生成iso的方法。 + +## 编译 + +编译RT-Thread Smart for x86版本，还需要一份支持musllib的工具链，可以通过以下地址获得： + +*[i386-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](http://117.143.63.254:9012/www/rt-smart/i386-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) + +下载后解压，然后在rtconfig.py中配置其中的EXEC_PATH变量 + +```python +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/home/jasonhu/Desktop/rtthread-smart/tools/gnu_gcc/i386-linux-musleabi_for_x86_64-pc-linux-gnu/bin' +``` + +然后在x86 bsp目录下执行scons命令来编译： + +```bash +scons +``` + +### 配置 + +RT-Thread Smart for x86的版本也支持menuconfig的配置方式，在Linux下可以使用`scons --menuconfig`的方式进行配置。 + +因为menuconfig是一份字符界面的配置（Kconfig），在ubuntu下需要安装ncurses5的库 + +```bash +sudo apt install libncurses5-dev +``` + +## 运行 + +在ubuntu下运行，请确保你安装了`qemu-system-i386`，`grub2` 以及 `xorriso`软件包： + +```bash +sudo apt install qemu-system-x86 grub2-common xorriso +``` + +然后执行`./run.sh`命令可以使用qemu来模拟执行(它也会生成可启动的iso文件) + +```bash +xorriso 1.5.0 : RockRidge filesystem manipulator, libburnia project. + +Drive current: -outdev 'stdio:bootable.iso' +Media current: stdio file, overwriteable +Media status : is blank +Media summary: 0 sessions, 0 data blocks, 0 data, 534m free +Added to ISO image: directory '/'='/tmp/grub.IcTOBu' +xorriso : UPDATE : 332 files added in 1 seconds +Added to ISO image: directory '/'='/home/jasonhu/Desktop/RTT/rtthread-smart/kernel/bsp/x86/root' +xorriso : UPDATE : 336 files added in 1 seconds +xorriso : NOTE : Copying to System Area: 512 bytes from file '/usr/lib/grub/i386-pc/boot_hybrid.img' +ISO image produced: 5679 sectors +Written to medium : 5679 sectors at LBA 0 +Writing to 'stdio:bootable.iso' completed successfully. + + \ | / +- RT - Thread Smart Operating System + / | \ 5.0.0 build Aug 23 2021 + 2006 - 2020 Copyright by rt-thread team +lwIP-2.1.2 initialized! +[E/DBG] [ahci] no AHCI controllers present! +[E/PCNET32] device not find on pci device. + +[E/RTL8139] device not find on pci device. + +[I/sal.skt] Socket Abstraction Layer initialize success. +Dir /mnt mount failed! +Hello rtthread-smart x86! +msh /> +``` + +在qemu下可以按Ctrl-A + X退出qemu。 diff --git a/bsp/x86/SConscript b/bsp/x86/SConscript index fe0ae941ae9a759ae478de901caec1c961e56af8..c7ef7659ecea92b1dd9b71a97736a8552ee02551 100644 --- a/bsp/x86/SConscript +++ b/bsp/x86/SConscript @@ -1,8 +1,8 @@ # for module compiling import os -Import('RTT_ROOT') +from building import * -cwd = str(Dir('#')) +cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) diff --git a/bsp/x86/applications/SConscript b/bsp/x86/applications/SConscript index 01eb940dfb35f92c503a78b0b49a4354590f9f3a..9ffdfd6d3ac13244a32fb825524e12e0ca88c585 100644 --- a/bsp/x86/applications/SConscript +++ b/bsp/x86/applications/SConscript @@ -1,10 +1,8 @@ -Import('RTT_ROOT') -Import('rtconfig') from building import * -cwd = os.path.join(str(Dir('#')), 'applications') +cwd = GetCurrentDir() src = Glob('*.c') -CPPPATH = [cwd, str(Dir('#'))] +CPPPATH = [cwd] group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/x86/applications/application.c b/bsp/x86/applications/application.c deleted file mode 100644 index 8928e6357ecead779bf3a87a1c0298062614793a..0000000000000000000000000000000000000000 --- a/bsp/x86/applications/application.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - */ - -#include - -#ifdef RT_USING_DFS -#include -#include -#include "floppy.h" -#ifdef RT_USING_MODULE -#include -#endif -extern int elm_init(void); -#endif - -/* components initialization for simulator */ -void components_init(void) -{ -#ifdef RT_USING_DFS - rt_floppy_init(); - /* initialize the device file system */ - dfs_init(); - -#ifdef RT_USING_DFS_ELMFAT - /* initialize the elm chan FatFS file system*/ - elm_init(); -#endif - -#ifdef RT_USING_MODULE - rt_system_dlmodule_init(); -#endif -#endif -} -void rt_init_thread_entry(void *parameter) -{ - components_init(); - - /* File system Initialization */ -#ifdef RT_USING_DFS - { - -#ifdef RT_USING_DFS_ELMFAT - /* mount sd card fatfs as root directory */ - if (dfs_mount("floppy", "/", "elm", 0, 0) == 0) - rt_kprintf("fatfs initialized!\n"); - else - rt_kprintf("fatfs initialization failed!\n"); -#endif - } -#endif -} - -int rt_application_init() -{ - rt_thread_t tid; - - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX / 3, 20); - - if (tid != RT_NULL) - rt_thread_startup(tid); - - return 0; -} diff --git a/bsp/x86/applications/main.c b/bsp/x86/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..3ab106ed6079c0a428d2afae6c43ff0edc135d7e --- /dev/null +++ b/bsp/x86/applications/main.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include +#include +#include + +int main(void) +{ + printf("Hello rtthread-smart x86!\n"); + return 0; +} diff --git a/bsp/x86/applications/mnt.c b/bsp/x86/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..d55681138f26a6ca086178328776df00b81922d1 --- /dev/null +++ b/bsp/x86/applications/mnt.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-23 JasonHu first version + */ + +#include + +#ifdef RT_USING_DFS +#include +#include + +int mnt_init(void) +{ + if (dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) != 0) + { + rt_kprintf("Dir / mount failed!\n"); + return -1; + } + + rt_thread_mdelay(200); + + if (dfs_mount("sd0", "/mnt", "elm", 0, NULL) != 0) + { + rt_kprintf("Dir /mnt mount failed!\n"); + return -1; + } + + rt_kprintf("file system initialization done!\n"); + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif diff --git a/bsp/x86/applications/romfs.c b/bsp/x86/applications/romfs.c new file mode 100644 index 0000000000000000000000000000000000000000..5b19a74c0eab59ae21a850d08959854cde6b82aa --- /dev/null +++ b/bsp/x86/applications/romfs.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-05 JasonHu first version + */ + +#include + +static const struct romfs_dirent _romfs_root[] = { + {ROMFS_DIRENT_DIR, "etc", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "mnt", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "bin", RT_NULL, 0} +}; + +const struct romfs_dirent romfs_root = { + ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0])}; + diff --git a/bsp/x86/applications/startup.c b/bsp/x86/applications/startup.c deleted file mode 100644 index 72a4eb0a9668c70f0225388572beae7b2e59b3a7..0000000000000000000000000000000000000000 --- a/bsp/x86/applications/startup.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.fayfayspace.org/license/LICENSE. - * - * Change Logs: - * Date Author Notes - * 2006-09-15 QiuYi the first version - * 2006-10-10 Bernard update to 0.2.2 version - */ - -#include -#include - -#include "board.h" - -extern void rt_hw_console_init(void); -extern void rt_hw_board_init(void); -extern int rt_application_init(void); -//extern void rt_hw_interrupt_init(void); -//extern void rt_system_timer_init(void); -//extern void rt_system_scheduler_init(void); -//extern void rt_thread_idle_init(void); - -#ifdef RT_USING_FINSH -extern int finsh_system_init(void); -extern void finsh_set_device(const char *device); -#endif - -extern unsigned char __bss_start[]; -extern unsigned char __bss_end[]; - -/** - * @addtogroup QEMU - */ - - /*@{*/ - -/* clear .bss */ -void rt_hw_clear_bss(void) -{ - unsigned char *dst; - dst = __bss_start; - while (dst < __bss_end) - *dst++ = 0; -} - -/** - * This function will startup RT-Thread RTOS - */ -void rtthread_startup(void) -{ - /* clear .bss */ - rt_hw_clear_bss(); - - /* init hardware interrupt */ - rt_hw_interrupt_init(); - - /* init the console */ - rt_hw_console_init(); - rt_console_set_device("console"); - - /* init board */ - rt_hw_board_init(); - - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); - - /* init kernel object */ - rt_system_object_init(); - - /* init timer system */ - rt_system_timer_init(); - - /* init memory system */ -#ifdef RT_USING_HEAP - /* RAM 16M */ - rt_system_heap_init((void *)&__bss_end, (void *)(1024UL*1024*8)); -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - - /* init application */ - rt_application_init(); - -#ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("console"); -#endif - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -/*@}*/ diff --git a/bsp/x86/drivers/Kconfig b/bsp/x86/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f74daba619077f4d28dbc59494a89487dd379fa9 --- /dev/null +++ b/bsp/x86/drivers/Kconfig @@ -0,0 +1,22 @@ +config BSP_USING_DIRECT_UART + bool "Using Direct UART without driver" + default y + +config BSP_DRV_UART + bool "Enabel UART driver" + select RT_USING_SERIAL + default y + +if BSP_DRV_UART + config RT_USING_UART0 + bool "Enabel UART 0" + default y + + config RT_USING_UART1 + bool "Enabel UART 1" + default n +endif + +config BSP_DRV_AHCI + bool "Enabel AHCI disk driver" + default y \ No newline at end of file diff --git a/bsp/x86/drivers/board.c b/bsp/x86/drivers/board.c index 211ae1832afc8e3641ab61f83b5ce4a37992e8b6..acb8048c98d44edefd7cb4419ceae6b784f4828d 100644 --- a/bsp/x86/drivers/board.c +++ b/bsp/x86/drivers/board.c @@ -1,74 +1,122 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.fayfayspace.org/license/LICENSE. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2006-09-15 QiuYi the first version - * 2006-10-10 Bernard add hardware related of finsh + * 2021-07-14 JasonHu first version */ -#include #include +#include +#include +#include +#include -#include +#include +#include +#include -/** - * @addtogroup QEMU - */ -/*@{*/ +#include "drv_uart.h" +#include "direct_uart.h" +#include "drv_timer.h" +#include "pci.h" -static void rt_timer_handler(int vector, void* param) -{ - rt_tick_increase(); -} +#ifdef RT_USING_USERSPACE +#include +#include +#include "lwp_arch.h" + +rt_mmu_info mmu_info; + +/* kernel mmu table */ +volatile rt_size_t g_mmu_table[ARCH_PAGE_SIZE / sizeof(rt_size_t)] __attribute__((aligned(ARCH_PAGE_SIZE))); -#ifdef RT_USING_HOOK -static void idle_hook(void) +static size_t page_region_init() { - asm volatile("sti; hlt": : :"memory"); + unsigned int memory_size = *((unsigned int *)0x000001000); + rt_kprintf("physic memory size: %x bytes, %d MB\n", memory_size, memory_size / (1024 * 1024)); + if (memory_size < HW_PHY_MEM_SIZE_MIN) + { + dbg_log(DBG_ERROR, "phyisc memory too small! only %d MB, must >= %d MB\n", + memory_size / (1024 * 1024), HW_PHY_MEM_SIZE_MIN / (1024 * 1024)); + for (;;) + { + } + } + if (memory_size > HW_PAGE_SIZE_MAX) + { + memory_size = HW_PAGE_SIZE_MAX; + } + return memory_size; } + #endif -/** - * This function will init QEMU - * - */ void rt_hw_board_init(void) { - /* initialize 8253 clock to interrupt 1000 times/sec */ - outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); - outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) % 256); - outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) / 256); +#ifdef BSP_USING_DIRECT_UART + /* init direct serial hardware */ + rt_hw_direct_uart_init(); +#endif /* RT_USING_DIRECT_UART */ - /* install interrupt handler */ - rt_hw_interrupt_install(INTTIMER0, rt_timer_handler, RT_NULL, "tick"); - rt_hw_interrupt_umask(INTTIMER0); +#ifdef RT_USING_USERSPACE + /* init page and mmu */ + rt_region_t init_page_region; + init_page_region.start = (size_t)HW_PAGE_START; + init_page_region.end = page_region_init(); + /* init no mapped area in kernel table, must in kernel space */ + RT_ASSERT(!rt_hw_mmu_map_init(&mmu_info, (void *)HW_KERNEL_DELAY_MAP_START, + HW_KERNEL_DELAY_MAP_SIZE, (rt_size_t *)g_mmu_table, 0)); -#ifdef RT_USING_HOOK - rt_thread_idle_sethook(idle_hook); + rt_page_init(init_page_region); + /* map kernel space, then can read/write this area directly. */ + rt_hw_mmu_kernel_map_init(&mmu_info, HW_KERNEL_START, HW_KERNEL_END); + switch_mmu((void *)g_mmu_table); + mmu_enable(); #endif -} -void restart(void) -{ - outb(KBSTATP, 0xFE); /* pulse reset low */ - while(1); -} + /* init cpu special */ + rt_hw_cpu_init(); -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(restart, reboot PC) + /* initalize interrupt */ + rt_hw_interrupt_init(); -void reboot(void) +#ifdef BSP_DRV_UART + /* init serial driver */ + rt_hw_uart_init(); +#endif /* BSP_DRV_UART */ + + /* init timer driver */ + rt_hw_timer_init(); + +#ifdef RT_USING_HEAP + rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) HW_HEAP_BEGIN, (rt_ubase_t) HW_HEAP_END); + /* initialize memory system */ + rt_system_heap_init((void *)HW_HEAP_BEGIN, (void *)HW_HEAP_END); +#endif + + /* init dma allocator */ + rt_hw_dma_init(HW_DMA_BEGIN, HW_DMA_BEGIN + HW_DMA_SIZE); + + /* init pci bus */ + rt_pci_init(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_CONSOLE */ + +} + +void primary_cpu_entry(void) { - restart(); + extern void entry(void); + rt_hw_interrupt_disable(); + entry(); } -FINSH_FUNCTION_EXPORT(reboot, reboot PC) -#endif -/*@}*/ diff --git a/bsp/x86/drivers/board.h b/bsp/x86/drivers/board.h index bc79f9ccfb42c20f53034ddad5fd68f2132fc5d1..ccd3a9b0143b28255ccf55fcc609b78cd7443d06 100644 --- a/bsp/x86/drivers/board.h +++ b/bsp/x86/drivers/board.h @@ -1,20 +1,87 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2006-10-09 Bernard first version + * 2021-07-14 JasonHu first version */ #ifndef __BOARD_H__ #define __BOARD_H__ +#include +#include +#include + +/* boot size */ +#define HW_KERNEL_BEGIN 0x00000000UL +#define HW_KERNEL_SIZE (8 * 1024 * 1024) + +/* DMA start at 8M (DMA must lower than 16 MB address) */ +#define HW_DMA_BEGIN (HW_KERNEL_BEGIN + HW_KERNEL_SIZE) +/* DMA 8 MB size */ +#define HW_DMA_SIZE (8 * 1024 * 1024) + +/* heap start at 16M */ +#define HW_HEAP_BEGIN (HW_DMA_BEGIN + HW_DMA_SIZE) +/* heap 16 MB size */ +#define HW_HEAP_SIZE (16 * 1024 * 1024) + +#define HW_KERNEL_DELAY_MAP_MB 128 + +#ifdef RT_USING_USERSPACE +#define HW_HEAP_END (void*)(KERNEL_VADDR_START + HW_HEAP_BEGIN + HW_HEAP_SIZE) + +#define HW_PAGE_START HW_HEAP_END +/* TODO: use dynamic memroy select size */ +#define HW_PAGE_SIZE_MIN ((64 - 32) * 1024 * 1024) +#define HW_PAGE_SIZE_MAX (((1024 - HW_KERNEL_DELAY_MAP_MB) - 32) * 1024 * 1024) + +#define HW_PAGE_SIZE_DEF ((256 - 32) * 1024 * 1024) + +/* this should at end of phy memory */ +#define HW_PAGE_END (void*)(HW_PAGE_START + HW_PAGE_SIZE_DEF) + +#define HW_PHY_MEM_SIZE_MIN (HW_KERNEL_SIZE + HW_DMA_SIZE + HW_HEAP_SIZE + HW_PAGE_SIZE_MIN) + +#else +#define HW_HEAP_END (void*)(HEAP_BEGIN + HW_HEAP_SIZE) +#endif + +/* start at 1G, end at 4G */ +#define HW_USER_START 0x40000000UL +#define HW_USER_END 0xFFFFF000UL +#define HW_USER_SIZE (HW_USER_END - HW_USER_START) + +/* + * Delay map, don't map when kernel do self map, only map when needed. + * This area was used ioremap. + */ +#define HW_KERNEL_DELAY_MAP_SIZE (HW_KERNEL_DELAY_MAP_MB * (1024 * 1024)) +#define HW_KERNEL_START (0) +#define HW_KERNEL_END (HW_USER_START - HW_KERNEL_DELAY_MAP_SIZE) +#define HW_KERNEL_DELAY_MAP_START HW_KERNEL_END + +/** + * Virtual memory layout: + * + * +------------+ <- 0xFFFFFFFF (4GB) + * | USER | + * +------------+ <- 0x40000000 (1GB) + * | DELAY MAP | + * +------------+ <- 0x38000000 (896MB) + * | PAGE | + * +------------+ <- 0x02000000 (32MB) + * | HEAP | + * +------------+ <- 0x01000000 (16MB) + * | DMA | + * +------------+ <- 0x00800000 (8MB) + * | KERNEL | + * +------------+ <- 0x00000000 + */ + void rt_hw_board_init(void); #endif diff --git a/bsp/x86/drivers/console.c b/bsp/x86/drivers/console.c deleted file mode 100644 index f5c4fe530bc014815ec6960b846c7cd40acd2628..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/console.c +++ /dev/null @@ -1,337 +0,0 @@ -/* - * File : console.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-09-15 QiuYi the first version - */ - -#include -#include - -#include - -static unsigned addr_6845; -static rt_uint16_t *crt_buf; -static rt_int16_t crt_pos; - -extern void init_keyboard(); -extern void rt_keyboard_isr(void); -extern rt_bool_t rt_keyboard_getc(char* c); - -extern void rt_serial_init(void); -extern char rt_serial_getc(void); -extern void rt_serial_putc(const char c); - -void rt_console_putc(int c); - -/** - * @addtogroup QEMU - */ -/*@{*/ - -/** - * This function initializes cga - * - */ -void rt_cga_init(void) -{ - rt_uint16_t volatile *cp; - rt_uint16_t was; - rt_uint32_t pos; - - cp = (rt_uint16_t *) (CGA_BUF); - was = *cp; - *cp = (rt_uint16_t) 0xA55A; - if (*cp != 0xA55A) - { - cp = (rt_uint16_t *) (MONO_BUF); - addr_6845 = MONO_BASE; - } - else - { - *cp = was; - addr_6845 = CGA_BASE; - } - - /* Extract cursor location */ - outb(addr_6845, 14); - pos = inb(addr_6845+1) << 8; - outb(addr_6845, 15); - pos |= inb(addr_6845+1); - - crt_buf = (rt_uint16_t *)cp; - crt_pos = pos; -} - -/** - * This function will write a character to cga - * - * @param c the char to write - */ -static void rt_cga_putc(int c) -{ - /* if no attribute given, then use black on white */ - if (!(c & ~0xff)) c |= 0x0700; - - switch (c & 0xff) - { - case '\b': - if (crt_pos > 0) - { - crt_pos--; - crt_buf[crt_pos] = (c&~0xff) | ' '; - } - break; - case '\n': - crt_pos += CRT_COLS; - /* cascade */ - case '\r': - crt_pos -= (crt_pos % CRT_COLS); - break; - case '\t': - rt_console_putc(' '); - rt_console_putc(' '); - rt_console_putc(' '); - rt_console_putc(' '); - rt_console_putc(' '); - break; - default: - crt_buf[crt_pos++] = c; /* write the character */ - break; - } - - if (crt_pos >= CRT_SIZE) - { - rt_int32_t i; - rt_memcpy(crt_buf, crt_buf + CRT_COLS, (CRT_SIZE - CRT_COLS) << 1); - for (i = CRT_SIZE - CRT_COLS; i < CRT_SIZE; i++) - crt_buf[i] = 0x0700 | ' '; - crt_pos -= CRT_COLS; - } - - outb(addr_6845, 14); - outb(addr_6845+1, crt_pos >> 8); - outb(addr_6845, 15); - outb(addr_6845+1, crt_pos); -} - -/** - * This function will write a character to serial an cga - * - * @param c the char to write - */ -void rt_console_putc(int c) -{ - rt_cga_putc(c); - rt_serial_putc(c); -} - -/* RT-Thread Device Interface */ -#define CONSOLE_RX_BUFFER_SIZE 64 -static struct rt_device console_device; -static rt_uint8_t rx_buffer[CONSOLE_RX_BUFFER_SIZE]; -static rt_uint32_t read_index, save_index; - -static rt_err_t rt_console_init (rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_console_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt_console_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_console_control(rt_device_t dev, int cmd, void *args) -{ - return RT_EOK; -} - -static rt_size_t rt_console_write(rt_device_t dev, rt_off_t pos, const void * buffer, rt_size_t size) -{ - rt_size_t i = size; - const char* str = buffer; - - while(i--) - { - rt_console_putc(*str++); - } - - return size; -} - -static rt_size_t rt_console_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr = buffer; - rt_err_t err_code = RT_EOK; - - /* interrupt mode Rx */ - while (size) - { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - if (read_index != save_index) - { - /* read a character */ - *ptr++ = rx_buffer[read_index]; - size--; - - /* move to next position */ - read_index ++; - if (read_index >= CONSOLE_RX_BUFFER_SIZE) - read_index = 0; - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static void rt_console_isr(int vector, void* param) -{ - char c; - rt_bool_t ret; - rt_base_t level; - - if(INTUART0_RX == vector) - { - c = rt_serial_getc(); - ret = RT_TRUE; - } - else - { - rt_keyboard_isr(); - - ret = rt_keyboard_getc(&c); - } - - if(ret == RT_FALSE) - { - /* do nothing */ - } - else - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* save character */ - rx_buffer[save_index] = c; - save_index ++; - if (save_index >= CONSOLE_RX_BUFFER_SIZE) - save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (save_index == read_index) - { - read_index ++; - if (read_index >= CONSOLE_RX_BUFFER_SIZE) - read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - - /* invoke callback */ - if (console_device.rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = read_index > save_index ? - CONSOLE_RX_BUFFER_SIZE - read_index + save_index : - save_index - read_index; - - if(rx_length > 0) - { - console_device.rx_indicate(&console_device, rx_length); - } - } - else - { - - } -} - -/** - * This function initializes console - * - */ -void rt_hw_console_init(void) -{ - rt_cga_init(); - rt_serial_init(); - init_keyboard(); - - /* install keyboard isr */ - rt_hw_interrupt_install(INTKEYBOARD, rt_console_isr, RT_NULL, "kbd"); - rt_hw_interrupt_umask(INTKEYBOARD); - - rt_hw_interrupt_install(INTUART0_RX, rt_console_isr, RT_NULL, "COM1"); - rt_hw_interrupt_umask(INTUART0_RX); - - console_device.type = RT_Device_Class_Char; - console_device.rx_indicate = RT_NULL; - console_device.tx_complete = RT_NULL; - console_device.init = rt_console_init; - console_device.open = rt_console_open; - console_device.close = rt_console_close; - console_device.read = rt_console_read; - console_device.write = rt_console_write; - console_device.control = rt_console_control; - console_device.user_data = RT_NULL; - - /* register a character device */ - rt_device_register(&console_device, - "console", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); -} - -/** - * This function is used to display a string on console, normally, it's - * invoked by rt_kprintf - * - * @param str the displayed string - * - * Modified: - * caoxl 2009-10-14 - * the name is change to rt_hw_console_output in the v0.3.0 - * - */ -void rt_hw_console_output(const char* str) -{ - while (*str) - { - rt_console_putc (*str++); - } -} - -/*@}*/ diff --git a/bsp/x86/drivers/direct_uart.c b/bsp/x86/drivers/direct_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..fa444d4f0df9c8d735b7d49c39b2334df1eb3540 --- /dev/null +++ b/bsp/x86/drivers/direct_uart.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-15 JasonHu first version + */ + +#include + +#ifdef BSP_USING_DIRECT_UART +#include +#include + +#include "board.h" + +/* I/O port base addr */ +#define COM1_BASE 0X3F8 + +#define MAX_BAUD_VALUE 115200 +#define DEFAULT_BAUD_VALUE 19200 +#define DEFAULT_DIVISOR_VALUE (MAX_BAUD_VALUE / DEFAULT_BAUD_VALUE) + +#define UART_SEND_TIMEOUT + +enum uart_fifo_control_register_bits +{ + FIFO_ENABLE = 1, /* Enable FIFOs */ + FIFO_CLEAR_RECEIVE = (1 << 1), /* Clear Receive FIFO */ + FIFO_CLEAR_TRANSMIT = (1 << 2), /* Clear Transmit FIFO */ + FIFO_DMA_MODE_SELECT = (1 << 3), /* DMA Mode Select */ + FIFO_RESERVED = (1 << 4), /* Reserved */ + FIFO_ENABLE_64 = (1 << 5), /* Enable 64 Byte FIFO(16750) */ + /* Interrupt Trigger Level/Trigger Level */ + FIFO_TRIGGER_1 = (0 << 6), /* 1 Byte */ + FIFO_TRIGGER_4 = (1 << 6), /* 4 Byte */ + FIFO_TRIGGER_8 = (1 << 7), /* 8 Byte */ + FIFO_TRIGGER_14 = (1 << 6) | (1 << 7), /* 14 Byte */ +}; + +enum uart_line_control_register_bits +{ + /* Word Length */ + LINE_WORD_LENGTH_5 = 0, /* 5 Bits */ + LINE_WORD_LENGTH_6 = 1, /* 6 Bits */ + LINE_WORD_LENGTH_7 = (1 << 1), /* 7 Bits */ + LINE_WORD_LENGTH_8 = ((1 << 1) | 1), /* 8 Bits */ + LINE_STOP_BIT_1 = (0 << 2), /* One Stop Bit */ + LINE_STOP_BIT_2 = (1 << 2), /* 1.5 Stop Bits or 2 Stop Bits */ + /* Parity Select */ + LINE_PARITY_NO = (0 << 3), /* No Parity */ + LINE_PARITY_ODD = (1 << 3), /* Odd Parity */ + LINE_PARITY_EVEN = (1 << 3) | (1 << 4), /* Even Parity */ + LINE_PARITY_MARK = (1 << 3) | (1 << 5), /* Mark */ + LINE_PARITY_SPACE = (1 << 3) | (1 << 4) | (1 << 5), /* Space */ + LINE_BREAK_ENABLE = (1 << 6), /* Set Break Enable */ + LINE_DLAB = (1 << 7), /* Divisor Latch Access Bit */ +}; + +enum uart_interrupt_enable_register_bits +{ + INTR_RECV_DATA_AVALIABLE = 1, /* Enable Received Data Available Interrupt */ + INTR_TRANSMIT_HOLDING = (1 << 1), /* Enable Transmitter Holding Register Empty Interrupt */ + INTR_STATUS_CHANGED = (1 << 2), /* Enable Receiver Line Status Interrupt */ + INTR_MODEM_STATUS = (1 << 3), /* Enable Modem Status Interrupt */ + INTR_SLEEP_MODE = (1 << 4), /* Enable Sleep Mode(16750) */ + INTR_LOW_POWER_MODE = (1 << 5), /* Enable Low Power Mode(16750) */ + INTR_RESERVED1 = (1 << 6), /* Reserved */ + INTR_RESERVED2 = (1 << 7), /* Reserved */ +}; + +enum uart_line_status_register_bits { + LINE_STATUS_DATA_READY = 1, /* Data Ready */ + LINE_STATUS_OVERRUN_ERROR = (1 << 1), /* Overrun Error */ + LINE_STATUS_PARITY_ERROR = (1 << 2), /* Parity Error */ + LINE_STATUS_FRAMING_ERROR = (1 << 3), /* Framing Error */ + LINE_STATUS_BREAK_INTERRUPT = (1 << 4), /* Break Interrupt */ + LINE_STATUS_EMPTY_TRANSMITTER_HOLDING = (1 << 5), /* Empty Transmitter Holding Register */ + LINE_STATUS_EMPTY_DATA_HOLDING = (1 << 6), /* Empty Data Holding Registers */ + LINE_STATUS_ERROR_RECEIVE_FIFO = (1 << 7), /* Error in Received FIFO */ +}; + +enum uart_intr_indenty_reg_bits { + INTR_STATUS_PENDING_FLAG = 1, /* Interrupt Pending Flag */ + /* 产生的什么中断 */ + INTR_STATUS_MODEM = (0 << 1), /* Transmitter Holding Register Empty Interrupt */ + INTR_STATUS_TRANSMITTER_HOLDING = (1 << 1), /* Received Data Available Interrupt */ + INTR_STATUS_RECEIVE_DATA = (1 << 2), /* Received Data Available Interrupt */ + INTR_STATUS_RECEIVE_LINE = (1 << 1) | (1 << 2), /* Receiver Line Status Interrupt */ + INTR_STATUS_TIME_OUT_PENDING = (1 << 2) | (1 << 3), /* Time-out Interrupt Pending (16550 & later) */ + INTR_STATUS_64BYTE_FIFO = (1 << 5), /* 64 Byte FIFO Enabled (16750 only) */ + INTR_STATUS_NO_FIFO = (0 << 6), /* No FIFO on chip */ + INTR_STATUS_RESERVED_CONDITION = (1 << 6), /* Reserved condition */ + INTR_STATUS_FIFO_NOT_FUNC = (1 << 7), /* FIFO enabled, but not functioning */ + INTR_STATUS_FIFO = (1 << 6) | (1 << 7), /* FIFO enabled */ +}; + +struct hw_uart +{ + rt_uint16_t iobase; + rt_uint16_t data_reg; + rt_uint16_t divisor_low_reg; + rt_uint16_t intr_enable_reg; + rt_uint16_t divisor_high_reg; + rt_uint16_t intr_indenty_reg; + rt_uint16_t fifo_reg; + rt_uint16_t line_ctrl_reg; + rt_uint16_t modem_ctrl_reg; + rt_uint16_t line_status_reg; + rt_uint16_t modem_status_reg; + rt_uint16_t scratch_reg; +}; +typedef struct hw_uart hw_uart_t; + +static hw_uart_t hw_uart; + +static int uart_send(hw_uart_t *uart, char data) +{ +#ifdef UART_SEND_TIMEOUT + int timeout = 0x100000; + while (!(inb(uart->line_status_reg) & LINE_STATUS_EMPTY_TRANSMITTER_HOLDING) && timeout--) + { + } +#else + while (!(inb(uart->line_status_reg) & LINE_STATUS_EMPTY_TRANSMITTER_HOLDING)) + { + } +#endif + outb(uart->data_reg, data); + return 0; +} + +void rt_hw_direct_uart_putchar(char ch) +{ + if(ch == '\n') { + uart_send(&hw_uart, '\r'); + } + uart_send(&hw_uart, ch); +} + +/** +* This function is used by rt_kprintf to display a string on console. +* +* @param str the displayed string +*/ +void rt_hw_console_output(const char *str) +{ + while (*str) { + rt_hw_direct_uart_putchar(*str++); + } +} + +void rt_hw_direct_uart_init(void) +{ + hw_uart_t *uart = &hw_uart; + rt_uint16_t iobase; + + iobase = COM1_BASE; + uart->iobase = iobase; + uart->data_reg = iobase + 0; + uart->divisor_low_reg = iobase + 0; + uart->intr_enable_reg = iobase + 1; + uart->divisor_high_reg = iobase + 1; + uart->intr_indenty_reg = iobase + 2; + uart->line_ctrl_reg = iobase + 3; + uart->modem_ctrl_reg = iobase + 4; + uart->line_status_reg = iobase + 5; + uart->modem_status_reg = iobase + 6; + uart->scratch_reg = iobase + 7; + + outb(uart->line_ctrl_reg, LINE_DLAB); + + outb(uart->divisor_low_reg, (DEFAULT_DIVISOR_VALUE) & 0xff); + outb(uart->divisor_high_reg, ((DEFAULT_DIVISOR_VALUE) >> 8) & 0xff); + + outb(uart->line_ctrl_reg, LINE_WORD_LENGTH_8 | + LINE_STOP_BIT_1 | LINE_PARITY_NO); + + /* close all intr */ + outb(uart->intr_enable_reg, 0); + + outb(uart->fifo_reg, FIFO_ENABLE | FIFO_CLEAR_TRANSMIT | + FIFO_CLEAR_RECEIVE | FIFO_ENABLE_64 | + FIFO_TRIGGER_14); + + outb(uart->modem_ctrl_reg, 0x00); + outb(uart->scratch_reg, 0x00); +} +#endif /* BSP_USING_DIRECT_UART */ diff --git a/bsp/x86/drivers/direct_uart.h b/bsp/x86/drivers/direct_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..71c30e73e7bdcae33015e248b489501292decd5d --- /dev/null +++ b/bsp/x86/drivers/direct_uart.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-15 JasonHu first version + */ + +#ifndef __DIRECT_UART_H__ +#define __DIRECT_UART_H__ + +/* direct means not use driver framework */ + +void rt_hw_direct_uart_init(void); + +#endif /* __DIRECT_UART_H__ */ diff --git a/bsp/x86/drivers/dma.h b/bsp/x86/drivers/dma.h deleted file mode 100644 index f1a8563cb1c435119229a7b02f5f3e6d731e1a7d..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/dma.h +++ /dev/null @@ -1,187 +0,0 @@ -#ifndef _DMA_H -#define _DMA_H - - -#define MAX_DMA_CHANNELS 8 - -/* 8237 DMA controllers */ -#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ -#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ - -/* DMA controller registers */ -#define DMA1_CMD_REG 0x08 /* command register (w) */ -#define DMA1_STAT_REG 0x08 /* status register (r) */ -#define DMA1_REQ_REG 0x09 /* request register (w) */ -#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ -#define DMA1_MODE_REG 0x0B /* mode register (w) */ -#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ -#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ -#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ -#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ -#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ - -#define DMA2_CMD_REG 0xD0 /* command register (w) */ -#define DMA2_STAT_REG 0xD0 /* status register (r) */ -#define DMA2_REQ_REG 0xD2 /* request register (w) */ -#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ -#define DMA2_MODE_REG 0xD6 /* mode register (w) */ -#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ -#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ -#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ -#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ -#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ - -#define DMA_ADDR_0 0x00 /* DMA address registers */ -#define DMA_ADDR_1 0x02 -#define DMA_ADDR_2 0x04 -#define DMA_ADDR_3 0x06 -#define DMA_ADDR_4 0xC0 -#define DMA_ADDR_5 0xC4 -#define DMA_ADDR_6 0xC8 -#define DMA_ADDR_7 0xCC - -#define DMA_CNT_0 0x01 /* DMA count registers */ -#define DMA_CNT_1 0x03 -#define DMA_CNT_2 0x05 -#define DMA_CNT_3 0x07 -#define DMA_CNT_4 0xC2 -#define DMA_CNT_5 0xC6 -#define DMA_CNT_6 0xCA -#define DMA_CNT_7 0xCE - -#define DMA_PAGE_0 0x87 /* DMA page registers */ -#define DMA_PAGE_1 0x83 -#define DMA_PAGE_2 0x81 -#define DMA_PAGE_3 0x82 -#define DMA_PAGE_5 0x8B -#define DMA_PAGE_6 0x89 -#define DMA_PAGE_7 0x8A - -#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ -#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ -#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ - -/* - * 启用指定的DMA通道 - */ -static __inline__ void EnableDma(unsigned int dmanr) -{ - if (dmanr<=3) - OUTB(dmanr, DMA1_MASK_REG); - else - OUTB(dmanr & 3, DMA2_MASK_REG); -} - -/* - * 禁用指定的DMA通道 - */ -static __inline__ void DisableDma(unsigned int dmanr) -{ - if (dmanr<=3) - OUTB(dmanr | 4, DMA1_MASK_REG); - else - OUTB((dmanr & 3) | 4, DMA2_MASK_REG); -} - -/* - * 清空DMA 晶体计数器 - */ -static __inline__ void ClearDmaFF(unsigned int dmanr) -{ - if (dmanr<=3) - OUTB(0, DMA1_CLEAR_FF_REG); - else - OUTB(0, DMA2_CLEAR_FF_REG); -} - -/* - * 清空DMA 晶体计数器 - */ -static __inline__ void SetDmaMode(unsigned int dmanr, char mode) -{ - if (dmanr<=3) - OUTB(mode | dmanr, DMA1_MODE_REG); - else - OUTB(mode | (dmanr&3), DMA2_MODE_REG); -} - -/* - * 设定DMA 页面寄存器 - */ -static __inline__ void SetDmaPage(unsigned int dmanr, char pagenr) -{ - switch(dmanr) { - case 0: - OUTB(pagenr, DMA_PAGE_0); - break; - case 1: - OUTB(pagenr, DMA_PAGE_1); - break; - case 2: - OUTB(pagenr, DMA_PAGE_2); - break; - case 3: - OUTB(pagenr, DMA_PAGE_3); - break; - case 5: - OUTB(pagenr & 0xfe, DMA_PAGE_5); - break; - case 6: - OUTB(pagenr & 0xfe, DMA_PAGE_6); - break; - case 7: - OUTB(pagenr & 0xfe, DMA_PAGE_7); - break; - } -} - - -/* - * 设定DMA 传输高速缓冲区地址 - */ -static __inline__ void SetDmaAddr(unsigned int dmanr, unsigned int a) -{ - SetDmaPage(dmanr, a>>16); - if (dmanr <= 3) { - OUTB( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - OUTB( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - } else { - OUTB( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - OUTB( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - } -} - - -/* - * 设定DMA 传输块数 - */ -static __inline__ void SetDmaCount(unsigned int dmanr, unsigned int count) -{ - count--; - if (dmanr <= 3) { - OUTB( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - OUTB( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - } else { - OUTB( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - OUTB( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - } -} - - -/* - * 获得DMA 传输剩余块数 - */ -static __inline__ int GetDmaResidue(unsigned int dmanr) -{ - unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE - : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; - - /* using short to get 16-bit wrap around */ - unsigned short count; - count = 1 + inb(io_port); - count += inb(io_port) << 8; - return (dmanr<=3)? count : (count<<1); -} - -#endif - diff --git a/bsp/x86/drivers/drv_ahci.c b/bsp/x86/drivers/drv_ahci.c new file mode 100644 index 0000000000000000000000000000000000000000..16a005bd2d30c73eb7e5c547979d78c17ddd3a15 --- /dev/null +++ b/bsp/x86/drivers/drv_ahci.c @@ -0,0 +1,852 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 JasonHu first version + */ + +#include + +#ifdef BSP_DRV_AHCI + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "drv_ahci.h" +#include "pci.h" + +#define DEV_NAME "sd" + +// #define RT_DRV_AHCI_DEBUG + +#ifdef RT_DRV_AHCI_DEBUG + #define dbgprint rt_kprintf +#else + #define dbgprint(...) +#endif + +/* memio info on the pci bar 5 */ +#define PCI_AHCI_MEMIO_BAR 5 + +#define LOWER32(a) (rt_uint32_t)((a) & 0xffffffff) +#define LOWER8(a) (rt_uint8_t)((a) & 0xff) +#define HIGHER8(a) (rt_uint8_t)(((a) >> 8) & 0xff) + +/* maxim ports we support */ +#define DRV_AHCI_PORT_NR 32 + +struct device_extension +{ + rt_uint64_t sector_count; /* sectors in this disk. */ + rt_uint8_t type; /* AHCI device type */ + rt_uint8_t port; /* port for each device. */ + rt_uint32_t slots; /* solts for device read/write transfer bits */ + struct rt_mutex lock; /* lock for disk read/write */ + void *fis_vaddr; + void *clb_vaddr; + rt_hw_dma_t clb_dma; + rt_hw_dma_t fis_dma; + void *cmd_hdrs[HBA_COMMAND_HEADER_NUM]; /* command header */ + rt_hw_dma_t cmd_hdrs_dmas[HBA_COMMAND_HEADER_NUM]; /* command header dma */ +}; +typedef struct device_extension rt_device_extension_t; + +static struct hba_memory *g_hba_base; /* hba memory io base addr */ + +static rt_err_t ahci_create_device(rt_device_extension_t *extension); + +static rt_uint32_t ahci_flush_commands(struct hba_port *port) +{ + /* the commands may not take effect until the command + * register is read again by software, because reasons. + */ + rt_hw_dsb(); + volatile rt_uint32_t c = port->command; + rt_hw_dmb(); + return c; +} + +static void ahci_stop_port_command_engine(struct hba_port *port) +{ + rt_hw_dsb(); + port->command &= ~HBA_PxCMD_ST; + rt_hw_dsb(); + port->command &= ~HBA_PxCMD_FRE; + rt_hw_dmb(); + while((port->command & HBA_PxCMD_CR) || (port->command & HBA_PxCMD_FR)) + { + rt_hw_cpu_pause(); + } +} + +static void ahci_start_port_command_engine(struct hba_port *port) +{ + rt_hw_dmb(); + while(port->command & HBA_PxCMD_CR) + { + rt_hw_cpu_pause(); + } + rt_hw_dsb(); + port->command |= HBA_PxCMD_FRE; + rt_hw_dsb(); + port->command |= HBA_PxCMD_ST; + ahci_flush_commands((struct hba_port *)port); +} + +static struct hba_command_header *ahci_initialize_command_header(rt_device_extension_t *dev, struct hba_memory *abar, + struct hba_port *port, int slot, int write, + int atapi, int prd_entries, int fis_len) +{ + struct hba_command_header *hdr = (struct hba_command_header *)dev->clb_vaddr; + hdr += slot; + hdr->write = write ? 1 : 0; + hdr->prdb_count = 0; + hdr->atapi=atapi ? 1 : 0; + hdr->fis_length = fis_len; + hdr->prdt_len = prd_entries; + hdr->prefetchable = 0; + hdr->bist = 0; + hdr->pmport = 0; + hdr->reset = 0; + return hdr; +} + +static struct fis_reg_host_to_device *ahci_initialize_fis_host_to_device(rt_device_extension_t *dev, struct hba_memory *abar, + struct hba_port *port, int slot, int cmdctl, int ata_command) +{ + struct hba_command_table *tbl = (struct hba_command_table *)(dev->cmd_hdrs[slot]); + struct fis_reg_host_to_device *fis = (struct fis_reg_host_to_device *)(tbl->command_fis); + + rt_memset(fis, 0, sizeof(*fis)); + fis->fis_type = FIS_TYPE_REG_H2D; + fis->command = ata_command; + fis->c = cmdctl ? 1 : 0; + return fis; +} + +static void ahci_send_command(struct hba_port *port, int slot) +{ + port->interrupt_status = ~0; + port->command_issue = (1 << slot); + ahci_flush_commands(port); +} + +static int ahci_write_prdt(rt_device_extension_t *dev, struct hba_memory *abar, struct hba_port *port, + int slot, int offset, int length, rt_ubase_t virt_buffer) +{ + int num_entries = ((length - 1) / PRDT_MAX_COUNT) + 1; + struct hba_command_table *tbl = (struct hba_command_table *)(dev->cmd_hdrs[slot]); + int i; + struct hba_prdt_entry *prd; + + for(i = 0; i < num_entries - 1; i++) + { + rt_ubase_t phys_buffer; + phys_buffer = rt_hw_vir2phy(virt_buffer); + prd = &tbl->prdt_entries[i + offset]; + prd->byte_count = PRDT_MAX_COUNT - 1; + prd->data_base_l = LOWER32(phys_buffer); + prd->data_base_h = 0; + prd->interrupt_on_complete = 0; + + length -= PRDT_MAX_COUNT; + virt_buffer += PRDT_MAX_COUNT; + } + + rt_ubase_t phys_buffer; + phys_buffer = rt_hw_vir2phy(virt_buffer); + prd = &tbl->prdt_entries[i + offset]; + prd->byte_count = length - 1; + prd->data_base_l = LOWER32(phys_buffer); + prd->data_base_h = 0; + prd->interrupt_on_complete = 0; + return num_entries; +} + +static void ahci_reset_device(struct hba_memory *abar, struct hba_port *port, rt_device_extension_t *dev) +{ + dbgprint("[ahci] device port %d: sending COMRESET and reinitializing\n", dev->port); + ahci_stop_port_command_engine(port); + port->sata_error = ~0; + /* power on, spin up */ + port->command |= 2; + port->command |= 4; + ahci_flush_commands(port); + rt_thread_mdelay(1); + + /* initialize state */ + port->interrupt_status = ~0; /* clear pending interrupts */ + port->interrupt_enable = AHCI_DEFAULT_INT; /* we want some interrupts */ + port->command &= ~((1 << 27) | (1 << 26)); /* clear some bits */ + port->sata_control |= 1; + rt_thread_mdelay(10); + port->sata_control |= (~1); + rt_thread_mdelay(10); + port->interrupt_status = ~0; /* clear pending interrupts */ + port->interrupt_enable = AHCI_DEFAULT_INT; /* we want some interrupts */ + ahci_start_port_command_engine(port); + dev->slots = 0; + port->sata_error = ~0; +} + +static rt_err_t ahci_port_dma_data_transfer(rt_device_extension_t *dev, struct hba_memory *abar, struct hba_port *port, + int slot, int write, rt_ubase_t virt_buffer, int sectors, rt_uint64_t lba) +{ + struct fis_reg_host_to_device *fis; + int timeout; + int fis_len = sizeof(struct fis_reg_host_to_device) / 4; + + int ne = ahci_write_prdt(dev, abar, port, slot, 0, ATA_SECTOR_SIZE * sectors, virt_buffer); + ahci_initialize_command_header(dev, abar, port, slot, write, 0, ne, fis_len); + fis = ahci_initialize_fis_host_to_device(dev, abar, port, slot, 1, write ? ATA_CMD_WRITE_DMA_EX : ATA_CMD_READ_DMA_EX); + + fis->device = 1 << 6; + fis->count_l = LOWER8(sectors); + fis->count_h = HIGHER8(sectors); + + fis->lba0 = (unsigned char)( lba & 0xFF); + fis->lba1 = (unsigned char)((lba >> 8) & 0xFF); + fis->lba2 = (unsigned char)((lba >> 16) & 0xFF); + fis->lba3 = (unsigned char)((lba >> 24) & 0xFF); + fis->lba4 = (unsigned char)((lba >> 32) & 0xFF); + fis->lba5 = (unsigned char)((lba >> 40) & 0xFF); + port->sata_error = ~0; + + timeout = ATA_TFD_TIMEOUT; + while ((port->task_file_data & (ATA_DEV_BUSY | ATA_DEV_DRQ)) && --timeout) + { + rt_thread_yield(); + } + if(!timeout) + { + goto port_hung; + } + + port->sata_error = ~0; + ahci_send_command(port, slot); + timeout = ATA_TFD_TIMEOUT; + while ((port->task_file_data & (ATA_DEV_BUSY | ATA_DEV_DRQ)) && --timeout) + { + rt_thread_yield(); + } + if(!timeout) + { + goto port_hung; + } + + timeout = AHCI_CMD_TIMEOUT; + while(--timeout) + { + if(!((port->sata_active | port->command_issue) & (1 << slot))) + break; + rt_thread_yield(); + } + if(!timeout) + { + goto port_hung; + } + if(port->sata_error) + { + dbg_log(DBG_ERROR, "[ahci] device %d: ahci error\n", dev->port); + goto error; + } + if(port->task_file_data & ATA_DEV_ERR) + { + dbg_log(DBG_ERROR, "[ahci] device %d: task file data error\n", dev->port); + goto error; + } + return RT_EOK; +port_hung: + dbg_log(DBG_ERROR, "[ahci] device %d: port hung\n", dev->port); +error: + dbg_log(DBG_ERROR, "[ahci] device %d: tfd=%x, serr=%x\n", + dev->port, port->task_file_data, port->sata_error); + ahci_reset_device(abar, port, dev); + return RT_ERROR; +} + +static rt_err_t ahci_device_identify(rt_device_extension_t *dev, struct hba_memory *abar, struct hba_port *port) +{ + int fis_len = sizeof(struct fis_reg_host_to_device) / 4; + rt_hw_dma_t dma; + dma.size = 0x1000; + dma.alignment = 0x1000; + RT_ASSERT(rt_hw_dma_alloc(&dma) == RT_EOK); + + ahci_write_prdt(dev, abar, port, 0, 0, 512, (rt_ubase_t)dma.vaddr); + ahci_initialize_command_header(dev, abar, port, 0, 0, 0, 1, fis_len); + ahci_initialize_fis_host_to_device(dev, abar, port, 0, 1, ATA_CMD_IDENTIFY); + + int timeout = ATA_TFD_TIMEOUT; + port->sata_error = ~0; + while ((port->task_file_data & (ATA_DEV_BUSY | ATA_DEV_DRQ)) && --timeout) + { + rt_hw_cpu_pause(); + } + if(!timeout ) + { + dbg_log(DBG_ERROR, "[ahci] device %d: identify 1: port hung\n", dev->port); + dbg_log(DBG_ERROR, "[ahci] device %d: identify 1: tfd=%x, serr=%x\n", + dev->port, port->task_file_data, port->sata_error); + rt_hw_dma_free(&dma); + return RT_ETIMEOUT; + } + + ahci_send_command(port, 0); + + timeout = AHCI_CMD_TIMEOUT; + while(--timeout) + { + if(!((port->sata_active | port->command_issue) & 1)) + break; + } + if(!timeout) + { + dbg_log(DBG_ERROR, "[ahci] device %d: identify 2: port hung\n", dev->port); + dbg_log(DBG_ERROR, "[ahci] device %d: identify 2: tfd=%x, serr=%x\n", + dev->port, port->task_file_data, port->sata_error); + rt_hw_dma_free(&dma); + return RT_ETIMEOUT; + } + + struct ata_identify *identify = (struct ata_identify *) dma.vaddr; + if (identify->lba48_addressable_sectors) + { + dev->sector_count = identify->lba48_addressable_sectors; + } + else + { + dev->sector_count = 0; + } + dbgprint("[ahci] device %d: num sectors=%d\n", dev->port, dev->sector_count); + + rt_hw_dma_free(&dma); + + if (!dev->sector_count) + { + dbg_log(DBG_ERROR, "[ahci] device %d invalid sectors ZERO.\n", dev->port); + return RT_EINVAL; + } + return RT_EOK; +} + +static rt_uint32_t ahci_check_type(volatile struct hba_port *port) +{ + port->command &= ~1; + while(port->command & (1 << 15)) + { + rt_hw_cpu_pause(); + } + + port->command &= ~(1 << 4); + while(port->command & (1 << 14)) + { + rt_hw_cpu_pause(); + } + + rt_hw_dsb(); + port->command |= 2; + rt_hw_dsb(); + rt_thread_mdelay(10); + + rt_uint32_t s = port->sata_status; + + uint8_t ipm, det; + ipm = (s >> 8) & 0x0F; + det = s & 0x0F; + if(ipm != HBA_PORT_IPM_ACTIVE || det != HBA_PORT_DET_PRESENT) + { + return AHCI_DEV_NULL; + } + + switch (port->signature) + { + case SATA_SIG_ATAPI: + return AHCI_DEV_SATAPI; + case SATA_SIG_SEMB: + return AHCI_DEV_SEMB; + case SATA_SIG_PM: + return AHCI_DEV_PM; + default: + return AHCI_DEV_SATA; + } + return AHCI_DEV_SATA; +} + +int ahci_initialize_device(rt_device_extension_t *dev, struct hba_memory *abar) +{ + struct hba_port *port = (struct hba_port *)&abar->ports[dev->port]; + ahci_stop_port_command_engine(port); + port->sata_error = ~0; + /* power on, spin up */ + port->command |= (2 | 4); + ahci_flush_commands(port); + rt_thread_mdelay(2); + + /* initialize state */ + port->interrupt_status = ~0; /* clear pending interrupts */ + port->interrupt_enable = AHCI_DEFAULT_INT; /* we want some interrupts */ + + port->command &= ~1; + while(port->command & (1 << 15)) + { + rt_hw_cpu_pause(); + } + + port->command &= ~((1 << 27) | (1 << 26) | 1); /* clear some bits */ + ahci_flush_commands(port); + + /* start reset sata */ + port->sata_control |= 1; + rt_thread_mdelay(20); + + /* close DET, after init sata device done. */ + port->sata_control &= (~1); + rt_thread_mdelay(10); + while(!(port->sata_status & 1)) + { + rt_hw_cpu_pause(); + } + + port->sata_error = ~0; + port->command |= (1 << 28); /* set interface to active */ + while((port->sata_status >> 8) != 1) + { + rt_hw_cpu_pause(); + } + + port->interrupt_status = ~0; /* clear pending interrupts */ + port->interrupt_enable = AHCI_DEFAULT_INT; /* we want some interrupts */ + + rt_ubase_t clb_phys, fis_phys; + dev->clb_dma.size = 0x2000; + dev->clb_dma.alignment = 0x1000; + dev->fis_dma.size = 0x1000; + dev->fis_dma.alignment = 0x1000; + + RT_ASSERT(rt_hw_dma_alloc(&dev->clb_dma) == RT_EOK); + RT_ASSERT(rt_hw_dma_alloc(&dev->fis_dma) == RT_EOK); + dev->clb_vaddr = (void *)dev->clb_dma.vaddr; + dev->fis_vaddr = (void *)dev->fis_dma.vaddr; + clb_phys = dev->clb_dma.paddr; + fis_phys = dev->fis_dma.paddr; + + dev->slots=0; + struct hba_command_header *hdr = (struct hba_command_header *)dev->clb_vaddr; + int i; + for(i = 0; i < HBA_COMMAND_HEADER_NUM; i++) + { + dev->cmd_hdrs_dmas[i].size = 0x1000; + dev->cmd_hdrs_dmas[i].alignment = 0x1000; + + RT_ASSERT(rt_hw_dma_alloc(&dev->cmd_hdrs_dmas[i]) == RT_EOK); + dev->cmd_hdrs[i] = (void *)dev->cmd_hdrs_dmas[i].vaddr; + rt_memset(hdr, 0, sizeof(*hdr)); + + hdr->command_table_base_l = LOWER32(dev->cmd_hdrs_dmas[i].paddr); + hdr->command_table_base_h = 0; + + hdr++; + } + + port->command_list_base_l = LOWER32(clb_phys); + port->command_list_base_h = 0; + + port->fis_base_l = LOWER32(fis_phys); + port->fis_base_h = 0; + ahci_start_port_command_engine(port); + + port->sata_error = ~0; + return ahci_device_identify(dev, abar, port); +} + +static rt_uint32_t ahci_probe_ports(struct hba_memory *abar) +{ + rt_uint32_t pi = abar->port_implemented; + dbgprint("[ahci] ports implemented: %x\n", pi); + int counts = 0; /* exist device count */ + int i = 0; + rt_device_extension_t *extension; + while (i < DRV_AHCI_PORT_NR) + { + if (pi & 1) + { + rt_uint32_t type = ahci_check_type(&abar->ports[i]); + if (type == AHCI_DEV_SATA) { /* SATA device */ + dbgprint("[ahci] detected SATA device on port %d\n", i); + + extension = rt_malloc(sizeof(rt_device_extension_t)); + if (extension == RT_NULL) + { + dbg_log(DBG_ERROR, "[ahci] port %d alloc memory for extension failed!\n", i); + return counts; + } + extension->type = type; + extension->port = i; + rt_mutex_init(&extension->lock, "ahci", RT_IPC_FLAG_PRIO); + if (ahci_initialize_device(extension, abar) == RT_EOK)\ + { + if (ahci_create_device(extension) == RT_EOK) { + counts++; + } + else + { + dbg_log(DBG_ERROR, "[ahci] failed to create device %d, disabling port!\n", i); + rt_free(extension); + } + } else { + dbg_log(DBG_ERROR, "[ahci] failed to initialize device %d, disabling port.\n", i); + } + } else if(type == AHCI_DEV_SATAPI) { /* SATAPI device */ + dbg_log(DBG_WARNING, "[ahci] not support SATAPI device on port %d now!\n", i); + } else if(type == AHCI_DEV_PM) { /* PM device */ + dbg_log(DBG_WARNING, "[ahci] not support Port multiplier on port %d now!\n", i); + } else if(type == AHCI_DEV_SEMB) { /* SEMB device */ + dbg_log(DBG_WARNING, "[ahci] not support Enclosure management bridge on port %d now!\n", i); + } + /* do not deal other type now. */ + } + i++; + pi >>= 1; + } + return counts; +} + +static int ahci_port_get_slot(rt_device_extension_t *dev) +{ + for(;;) + { + int i; + rt_mutex_take(&dev->lock, RT_WAITING_FOREVER); + for(i = 0; i < DRV_AHCI_PORT_NR; i++) + { + if(!(dev->slots & (1 << i))) + { + dev->slots |= (1 << i); + rt_mutex_release(&dev->lock); + return i; + } + } + rt_mutex_release(&dev->lock); + rt_thread_yield(); + } +} + +void ahci_port_put_slot(rt_device_extension_t *dev, int slot) +{ + rt_mutex_take(&dev->lock, RT_WAITING_FOREVER); + dev->slots &= ~(1 << slot); + rt_mutex_release(&dev->lock); +} + +/* since a DMA transfer must write to contiguous physical RAM, we need to allocate + * buffers that allow us to create PRDT entries that do not cross a page boundary. + * That means that each PRDT entry can transfer a maximum of PAGE_SIZE bytes (for + * 0x1000 page size, that's 8 sectors). Thus, we allocate a buffer that is page aligned, + * in a multiple of PAGE_SIZE, so that the PRDT will write to contiguous physical ram + * (the key here is that the buffer need not be contiguous across multiple PRDT entries). + */ +static rt_size_t ahci_rw_multiple_do(rt_device_extension_t *dev, int rw, rt_uint64_t blk, unsigned char *out_buffer, int count) +{ + rt_uint32_t length = count * ATA_SECTOR_SIZE; + rt_uint64_t end_blk = dev->sector_count; + if (blk >= end_blk) + { + dbg_log(DBG_ERROR, "ahci: lba %d out of range %d\n", blk, end_blk); + return 0; + } + + if((blk + count) > end_blk) + { + count = end_blk - blk; + } + if(!count) + { + return 0; + } + + int num_pages = ((ATA_SECTOR_SIZE * (count - 1)) / PAGE_SIZE) + 1; + RT_ASSERT((length <= (unsigned)num_pages * 0x1000)); + rt_hw_dma_t dma; + dma.size = 0x1000 * num_pages; + dma.alignment = 0x1000; + RT_ASSERT(rt_hw_dma_alloc(&dma) == RT_EOK); + + rt_size_t num_read_blocks = count; + struct hba_port *port = (struct hba_port *)&g_hba_base->ports[dev->port]; + if(rw == 1) + { + rt_memcpy((void *)dma.vaddr, out_buffer, length); + } + + int slot = ahci_port_get_slot(dev); + if(ahci_port_dma_data_transfer(dev, g_hba_base, port, slot, rw == 1 ? 1 : 0, (rt_ubase_t)dma.vaddr, count, blk) != RT_EOK) + { + num_read_blocks = 0; + } + + ahci_port_put_slot(dev, slot); + + if(rw == 0 && num_read_blocks) + { + rt_memcpy(out_buffer, (void *)dma.vaddr, length); + } + + rt_hw_dma_free(&dma); + return num_read_blocks; +} + +/* and then since there is a maximum transfer amount because of the page size + * limit, wrap the transfer function to allow for bigger transfers than that even. + */ +static rt_size_t ahci_rw_multiple(rt_device_extension_t *dev, int rw, rt_uint64_t blk, unsigned char *out_buffer, int count) +{ + int i = 0; + rt_size_t ret = 0; + int c = count; + for(i = 0; i < count; i += (PRDT_MAX_ENTRIES * PRDT_MAX_COUNT) / ATA_SECTOR_SIZE) + { + int n = (PRDT_MAX_ENTRIES * PRDT_MAX_COUNT) / ATA_SECTOR_SIZE; + if(n > c) + { + n = c; + } + ret += ahci_rw_multiple_do(dev, rw, blk+i, out_buffer + ret, n); + c -= n; + } + return ret; +} + +static rt_pci_device_t *ahci_get_pci_info(void) +{ + rt_pci_device_t *ahci = rt_pci_device_get(0x1, 0x6); + if(ahci == RT_NULL) + { + ahci = rt_pci_device_get(0x8086, 0x8c03); + } + if(ahci == RT_NULL) + { + ahci = rt_pci_device_get(0x8086, 0x2922); + } + if(ahci == RT_NULL) + { + return RT_NULL; + } + + dbgprint("[ahci] device vendorID %x deviceID %x class code %x\n", ahci->vendor_id, ahci->device_id, ahci->class_code); + + rt_pci_enable_bus_mastering(ahci); + + g_hba_base = rt_ioremap((void *) ahci->bars[PCI_AHCI_MEMIO_BAR].base_addr, ahci->bars[PCI_AHCI_MEMIO_BAR].length); + if (g_hba_base == RT_NULL) { + dbgprint("[ahci] device memio_remap on %x length %x failed!\n", ahci->bars[PCI_AHCI_MEMIO_BAR].base_addr, ahci->bars[PCI_AHCI_MEMIO_BAR].length); + return RT_NULL; + } + mmu_flush_tlb(); + + dbgprint("[ahci] mapping memory iobase from paddr %x to vaddr %x\n", ahci->bars[PCI_AHCI_MEMIO_BAR].base_addr, g_hba_base); + dbgprint("[ahci] using interrupt %d\n", ahci->irq_line); + return ahci; +} + +static rt_err_t rt_ahci_init(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_ahci_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_ahci_close(rt_device_t dev) +{ + return RT_EOK; +} + +/* + * position: block page address, not bytes address + * buffer: read buffer addr + * size : how many blocks + */ +static rt_size_t rt_ahci_read(rt_device_t device, rt_off_t position, void *buffer, rt_size_t size) +{ + return ahci_rw_multiple((rt_device_extension_t *)device->user_data, 0, position, (unsigned char *)buffer, size); +} + +/* + * position: block page address, not bytes address + * buffer: write buffer addr + * size : how many blocks + */ +static rt_size_t rt_ahci_write(rt_device_t device, rt_off_t position, const void *buffer, rt_size_t size) +{ + return ahci_rw_multiple((rt_device_extension_t *)device->user_data, 1, position, (unsigned char *)buffer, size); +} + +static rt_err_t rt_ahci_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev->user_data != NULL); + RT_ASSERT(args != RT_NULL); + + rt_device_extension_t *extension = (rt_device_extension_t *)dev->user_data; + rt_err_t err = RT_EOK; + switch(cmd) + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + { + struct rt_device_blk_geometry *geometry; + + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) + { + return -RT_ERROR; + } + geometry->bytes_per_sector = ATA_SECTOR_SIZE; + geometry->block_size = ATA_SECTOR_SIZE; + geometry->sector_count = extension->sector_count; + dbgprint("[ahci] getgeome: bytes_per_sector:%d, block_size:%d, sector_count:%d\n", + geometry->bytes_per_sector, geometry->block_size, geometry->sector_count); + break; + } + default: + err = RT_ERROR; + break; + } + return err; +} + +static void rt_hw_ahci_isr(int vector, void *param) +{ + int i; + for (i = 0; i < 32; i++) + { + if (g_hba_base->interrupt_status & (1 << i)) + { + dbgprint("[ahci] interrupt on port %d occured!\n", i); + g_hba_base->ports[i].interrupt_status = ~0; + g_hba_base->interrupt_status = (1 << i); + ahci_flush_commands((struct hba_port *)&g_hba_base->ports[i]); + } + } +} + +static void ahci_init_hba(struct hba_memory *abar) +{ + if(abar->ext_capabilities & 1) + { + /* request BIOS/OS ownership handoff */ + abar->bohc |= (1 << 1); + while((abar->bohc & 1) || !(abar->bohc & (1<<1))) + { + rt_hw_cpu_pause(); + } + } + /* enable the AHCI and reset it */ + abar->global_host_control |= HBA_GHC_AHCI_ENABLE; + abar->global_host_control |= HBA_GHC_RESET; + /* wait for reset to complete */ + while(abar->global_host_control & HBA_GHC_RESET) + { + rt_hw_cpu_pause(); + } + + /* enable the AHCI and interrupts */ + abar->global_host_control |= HBA_GHC_AHCI_ENABLE; + abar->global_host_control |= HBA_GHC_INTERRUPT_ENABLE; + rt_thread_mdelay(20); + dbgprint("[ahci] caps: %x %x ver:%x ctl: %x\n", abar->capability, abar->ext_capabilities, abar->version, abar->global_host_control); +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops ahci_ops = +{ + rt_ahci_init, + rt_ahci_open, + rt_ahci_close, + rt_ahci_read, + rt_ahci_write, + rt_ahci_control +}; +#endif + +static rt_err_t ahci_create_device(rt_device_extension_t *extension) +{ + static int ahci_next_device = 0; /* first is sd0 */ + rt_device_t device = rt_device_create(RT_Device_Class_Block, 0); + if (device == RT_NULL) + { + dbg_log(DBG_ERROR, "[ahci] create device failed!\n"); + return RT_ENOMEM; + } + device->user_data = (void *)extension; + +#ifdef RT_USING_DEVICE_OPS + device->ops = &ahci_ops; +#else + device->init = rt_ahci_init; + device->open = rt_ahci_open; + device->close = rt_ahci_close; + device->read = rt_ahci_read; + device->write = rt_ahci_write; + device->control = rt_ahci_control; +#endif + char devname[8] = {0}; + rt_sprintf(devname, "%s%c", DEV_NAME, '0' + ahci_next_device); + ahci_next_device++; + if (rt_device_register(device, devname, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE) != RT_EOK) + { + dbg_log(DBG_ERROR, "[ahci] register device failed!\n"); + rt_device_destroy(device); + return RT_ENOMEM; + } + return RT_EOK; +} + +static int rt_hw_ahci_init(void) +{ + /* 1. get pci info */ + rt_pci_device_t *ahci_pci = ahci_get_pci_info(); + if(ahci_pci == RT_NULL) + { + dbg_log(DBG_ERROR, "[ahci] no AHCI controllers present!\n"); + return RT_ERROR; + } + + /* 2. install intr */ + if (rt_hw_interrupt_install(ahci_pci->irq_line, rt_hw_ahci_isr, RT_NULL, "ahci") < 0) + { + dbg_log(DBG_ERROR, "[ahci] install IRQ failed!\n"); + rt_iounmap(g_hba_base); + return RT_ERROR; + } + rt_hw_interrupt_umask(ahci_pci->irq_line); + + /* 3. init ahci device */ + ahci_init_hba(g_hba_base); + if (!ahci_probe_ports(g_hba_base)) + { + dbg_log(DBG_ERROR, "[ahci] initializing ahci driver failed!.\n"); + rt_hw_interrupt_mask(ahci_pci->irq_line); + rt_iounmap(g_hba_base); + return RT_ERROR; + } + rt_kprintf("[ahci] disk driver init done!\n"); + return RT_EOK; +} + +#ifdef RT_USING_COMPONENTS_INIT +INIT_DEVICE_EXPORT(rt_hw_ahci_init); +#endif +#endif /* BSP_DRV_AHCI */ diff --git a/bsp/x86/drivers/drv_ahci.h b/bsp/x86/drivers/drv_ahci.h new file mode 100644 index 0000000000000000000000000000000000000000..f9e2bb35bf149337f92ed456ec5a3738c3b86ab4 --- /dev/null +++ b/bsp/x86/drivers/drv_ahci.h @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 JasonHu first version + */ + +#ifndef __DRV_AHCI_H__ +#define __DRV_AHCI_H__ + +#include + +enum AHCI_FIS_TYPE +{ + FIS_TYPE_REG_H2D = 0x27, // Register FIS - host to device + FIS_TYPE_REG_D2H = 0x34, // Register FIS - device to host + FIS_TYPE_DMA_ACT = 0x39, // DMA activate FIS - device to host + FIS_TYPE_DMA_SETUP = 0x41, // DMA setup FIS - bidirectional + FIS_TYPE_DATA = 0x46, // Data FIS - bidirectional + FIS_TYPE_BIST = 0x58, // BIST activate FIS - bidirectional + FIS_TYPE_PIO_SETUP = 0x5F, // PIO setup FIS - device to host + FIS_TYPE_DEV_BITS = 0xA1, // Set device bits FIS - device to host +}; + +struct fis_reg_host_to_device +{ + rt_uint8_t fis_type; + + rt_uint8_t pmport:4; + rt_uint8_t reserved0:3; + rt_uint8_t c:1; + + rt_uint8_t command; + rt_uint8_t feature_l; + + rt_uint8_t lba0; + rt_uint8_t lba1; + rt_uint8_t lba2; + rt_uint8_t device; + + rt_uint8_t lba3; + rt_uint8_t lba4; + rt_uint8_t lba5; + rt_uint8_t feature_h; + + rt_uint8_t count_l; + rt_uint8_t count_h; + rt_uint8_t icc; + rt_uint8_t control; + + rt_uint8_t reserved1[4]; +}__attribute__ ((packed)); + +struct fis_reg_device_to_host +{ + rt_uint8_t fis_type; + + rt_uint8_t pmport:4; + rt_uint8_t reserved0:2; + rt_uint8_t interrupt:1; + rt_uint8_t reserved1:1; + + rt_uint8_t status; + rt_uint8_t error; + + rt_uint8_t lba0; + rt_uint8_t lba1; + rt_uint8_t lba2; + rt_uint8_t device; + + rt_uint8_t lba3; + rt_uint8_t lba4; + rt_uint8_t lba5; + rt_uint8_t reserved2; + + rt_uint8_t count_l; + rt_uint8_t count_h; + rt_uint8_t reserved3[2]; + + rt_uint8_t reserved4[4]; +}__attribute__ ((packed)); + +struct fis_data +{ + rt_uint8_t fis_type; + rt_uint8_t pmport:4; + rt_uint8_t reserved0:4; + rt_uint8_t reserved1[2]; + + rt_uint32_t data[1]; +}__attribute__ ((packed)); + +struct fis_pio_setup +{ + rt_uint8_t fis_type; + + rt_uint8_t pmport:4; + rt_uint8_t reserved0:1; + rt_uint8_t direction:1; + rt_uint8_t interrupt:1; + rt_uint8_t reserved1:1; + + rt_uint8_t status; + rt_uint8_t error; + + rt_uint8_t lba0; + rt_uint8_t lba1; + rt_uint8_t lba2; + rt_uint8_t device; + + rt_uint8_t lba3; + rt_uint8_t lba4; + rt_uint8_t lba5; + rt_uint8_t reserved2; + + rt_uint8_t count_l; + rt_uint8_t count_h; + rt_uint8_t reserved3; + rt_uint8_t e_status; + + rt_uint16_t transfer_count; + rt_uint8_t reserved4[2]; +}__attribute__ ((packed)); + +struct fis_dma_setup +{ + rt_uint8_t fis_type; + + rt_uint8_t pmport:4; + rt_uint8_t reserved0:1; + rt_uint8_t direction:1; + rt_uint8_t interrupt:1; + rt_uint8_t auto_activate:1; + + rt_uint8_t reserved1[2]; + + rt_uint64_t dma_buffer_id; + + rt_uint32_t reserved2; + + rt_uint32_t dma_buffer_offset; + + rt_uint32_t transfer_count; + + rt_uint32_t reserved3; +}__attribute__ ((packed)); + +struct fis_dev_bits +{ + volatile rt_uint8_t fis_type; + + volatile rt_uint8_t pmport:4; + volatile rt_uint8_t reserved0:2; + volatile rt_uint8_t interrupt:1; + volatile rt_uint8_t notification:1; + + volatile rt_uint8_t status; + volatile rt_uint8_t error; + + volatile rt_uint32_t protocol; +}__attribute__ ((packed)); + +struct hba_port +{ + volatile rt_uint32_t command_list_base_l; + volatile rt_uint32_t command_list_base_h; + volatile rt_uint32_t fis_base_l; + volatile rt_uint32_t fis_base_h; + volatile rt_uint32_t interrupt_status; + volatile rt_uint32_t interrupt_enable; + volatile rt_uint32_t command; + volatile rt_uint32_t reserved0; + volatile rt_uint32_t task_file_data; + volatile rt_uint32_t signature; + volatile rt_uint32_t sata_status; + volatile rt_uint32_t sata_control; + volatile rt_uint32_t sata_error; + volatile rt_uint32_t sata_active; + volatile rt_uint32_t command_issue; + volatile rt_uint32_t sata_notification; + volatile rt_uint32_t fis_based_switch_control; + volatile rt_uint32_t reserved1[11]; + volatile rt_uint32_t vendor[4]; +}__attribute__ ((packed)); + +struct hba_memory +{ + volatile rt_uint32_t capability; + volatile rt_uint32_t global_host_control; + volatile rt_uint32_t interrupt_status; + volatile rt_uint32_t port_implemented; + volatile rt_uint32_t version; + volatile rt_uint32_t ccc_control; + volatile rt_uint32_t ccc_ports; + volatile rt_uint32_t em_location; + volatile rt_uint32_t em_control; + volatile rt_uint32_t ext_capabilities; + volatile rt_uint32_t bohc; + + volatile rt_uint8_t reserved[0xA0 - 0x2C]; + + volatile rt_uint8_t vendor[0x100 - 0xA0]; + + volatile struct hba_port ports[1]; +}__attribute__ ((packed)); + +struct hba_received_fis +{ + volatile struct fis_dma_setup fis_ds; + volatile rt_uint8_t pad0[4]; + + volatile struct fis_pio_setup fis_ps; + volatile rt_uint8_t pad1[12]; + + volatile struct fis_reg_device_to_host fis_r; + volatile rt_uint8_t pad2[4]; + + volatile struct fis_dev_bits fis_sdb; + volatile rt_uint8_t ufis[64]; + volatile rt_uint8_t reserved[0x100 - 0xA0]; +}__attribute__ ((packed)); + +struct hba_command_header +{ + rt_uint8_t fis_length:5; + rt_uint8_t atapi:1; + rt_uint8_t write:1; + rt_uint8_t prefetchable:1; + + rt_uint8_t reset:1; + rt_uint8_t bist:1; + rt_uint8_t clear_busy_upon_r_ok:1; + rt_uint8_t reserved0:1; + rt_uint8_t pmport:4; + + rt_uint16_t prdt_len; + + volatile rt_uint32_t prdb_count; + + rt_uint32_t command_table_base_l; + rt_uint32_t command_table_base_h; + + rt_uint32_t reserved1[4]; +}__attribute__ ((packed)); + +struct hba_prdt_entry +{ + rt_uint32_t data_base_l; + rt_uint32_t data_base_h; + rt_uint32_t reserved0; + + rt_uint32_t byte_count:22; + rt_uint32_t reserved1:9; + rt_uint32_t interrupt_on_complete:1; +}__attribute__ ((packed)); + +struct hba_command_table +{ + rt_uint8_t command_fis[64]; + rt_uint8_t acmd[16]; + rt_uint8_t reserved[48]; + struct hba_prdt_entry prdt_entries[1]; +}__attribute__ ((packed)); + +#define HBA_COMMAND_HEADER_NUM 32 + +struct ata_identify +{ + rt_uint16_t ata_device; + rt_uint16_t dont_care[48]; + rt_uint16_t cap0; + rt_uint16_t cap1; + rt_uint16_t obs[2]; + rt_uint16_t free_fall; + rt_uint16_t dont_care_2[8]; + rt_uint16_t dma_mode0; + rt_uint16_t pio_modes; + rt_uint16_t dont_care_3[4]; + rt_uint16_t additional_supported; + rt_uint16_t rsv1[6]; + rt_uint16_t serial_ata_cap0; + rt_uint16_t rsv2; + + rt_uint16_t serial_ata_features; + rt_uint16_t serial_ata_features_enabled; + + rt_uint16_t maj_ver; + rt_uint16_t min_ver; + + rt_uint16_t features0; + rt_uint16_t features1; + rt_uint16_t features2; + rt_uint16_t features3; + rt_uint16_t features4; + rt_uint16_t features5; + + rt_uint16_t udma_modes; + rt_uint16_t dont_care_4[11]; + rt_uint64_t lba48_addressable_sectors; + rt_uint16_t wqewqe[2]; + rt_uint16_t ss_1; + rt_uint16_t rrrrr[4]; + rt_uint32_t ss_2; + /* ...and more */ +}; + +#define HBA_PxCMD_ST (1 << 0) +#define HBA_PxCMD_FRE (1 << 4) +#define HBA_PxCMD_FR (1 << 14) +#define HBA_PxCMD_CR (1 << 15) + +#define HBA_GHC_AHCI_ENABLE (1 << 31) +#define HBA_GHC_INTERRUPT_ENABLE (1 << 1) +#define HBA_GHC_RESET (1 << 0) + +#define ATA_CMD_IDENTIFY 0xEC + +#define ATA_DEV_BUSY 0x80 +#define ATA_DEV_DRQ 0x08 +#define ATA_DEV_ERR 0x01 + +#define ATA_CMD_READ_DMA_EX 0x25 +#define ATA_CMD_WRITE_DMA_EX 0x35 + +#define PRDT_MAX_COUNT 0x1000 + +#define PRDT_MAX_ENTRIES 65535 + +#define ATA_TFD_TIMEOUT 1000000 +#define AHCI_CMD_TIMEOUT 1000000 + +#define ATA_SECTOR_SIZE 512 + +#define AHCI_DEFAULT_INT 0 + +#define SATA_SIG_ATA 0x00000101 // SATA drive +#define SATA_SIG_ATAPI 0xEB140101 // SATAPI drive +#define SATA_SIG_SEMB 0xC33C0101 // Enclosure management bridge +#define SATA_SIG_PM 0x96690101 // Port multiplier + +enum AHCI_DEVICE_TYPE +{ + AHCI_DEV_NULL = 0, + AHCI_DEV_SATA, + AHCI_DEV_SEMB, + AHCI_DEV_PM, + AHCI_DEV_SATAPI +}; + +#define HBA_PORT_IPM_ACTIVE 1 +#define HBA_PORT_DET_PRESENT 3 + +#endif /* __DRV_AHCI_H__ */ diff --git a/bsp/x86/drivers/drv_pcnet32.c b/bsp/x86/drivers/drv_pcnet32.c new file mode 100644 index 0000000000000000000000000000000000000000..8a05287a4ea909b9dedbfea5bf3fa2a9e165948a --- /dev/null +++ b/bsp/x86/drivers/drv_pcnet32.c @@ -0,0 +1,670 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-19 JasonHu first version + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DBG_LVL DBG_INFO +#define DBG_TAG "PCNET32" +#include + +#include "drv_pcnet32.h" + +#define DEV_NAME "e0" + +#define GET_PCNET32(eth) (struct eth_device_pcnet32 *)(eth) + +/** + * rx ring desc struct + */ +struct pcnet32_rx_desc +{ + rt_uint32_t base; /* buffer base addr */ + rt_uint16_t buf_length; /* two`s complement of length */ + rt_uint16_t status; /* desc status */ + rt_uint16_t msg_length; /* Message Byte Count is the length in bytes of the received message. */ + rt_uint16_t rpc_rcc; + rt_uint32_t reserved; +} __attribute__ ((packed)); + +/** + * tx ring desc struct + */ +struct pcnet32_tx_desc +{ + rt_uint32_t base; /* buffer base addr */ + rt_uint16_t buf_length; /* two`s complement of length */ + rt_uint16_t status; /* desc status */ + rt_uint32_t misc; + rt_uint32_t reserved; +} __attribute__ ((packed)); + +/** + * The PCNET32 32-Bit initialization block, described in databook. + * The Mode Register (CSR15) allows alteration of the chip's operating + * parameters. The Mode field of the Initialization Block is copied directly + * into CSR15. Normal operation is the result of configuring the Mode field + * with all bits zero. + */ +struct pcnet32_init_block +{ + rt_uint16_t mode; + rt_uint16_t tlen_rlen; + rt_uint8_t phys_addr[6]; + rt_uint16_t reserved; + rt_uint32_t filter[2]; + /* Receive and transmit ring base, along with extra bits. */ + rt_uint32_t rx_ring; + rt_uint32_t tx_ring; +} __attribute__ ((packed)); + +struct eth_device_pcnet32 +{ + /* inherit from Ethernet device */ + struct eth_device parent; + /* interface address info. */ + rt_uint8_t dev_addr[ETH_ALEN]; /* MAC address */ + + rt_pci_device_t *pci_dev; /* pci device info */ + + rt_uint32_t iobase; /* io port base */ + rt_uint32_t irqno; /* irq number */ + + rt_mq_t rx_mqueue; /* msg queue for rx */ + + struct pcnet32_init_block *init_block; + + rt_uint16_t rx_len_bits; + rt_uint16_t tx_len_bits; + + rt_ubase_t rx_ring_dma_addr; + rt_ubase_t tx_ring_dma_addr; + + rt_ubase_t init_block_dma_addr; + + rt_ubase_t rx_buffer_ptr; + rt_ubase_t tx_buffer_ptr; /* pointers to transmit/receive buffers */ + + rt_size_t rx_buffer_count; /* total number of receive buffers */ + rt_size_t tx_buffer_count; /* total number of transmit buffers */ + + rt_size_t buffer_size; /* length of each packet buffer */ + + rt_size_t de_size; /* length of descriptor entry */ + + struct pcnet32_rx_desc *rdes; /* pointer to ring buffer of receive des */ + struct pcnet32_tx_desc *tdes; /* pointer to ring buffer of transmit des */ + + rt_uint32_t rx_buffers; /* physical address of actual receive buffers (< 4 GiB) */ + rt_uint32_t tx_buffers; /* physical address of actual transmit buffers (< 4 GiB) */ +}; +static struct eth_device_pcnet32 eth_dev; +static rt_uint8_t rx_cache_send_buf[RX_MSG_SIZE] = {0}; /* buf for rx packet, put size and data into mq */ +static rt_uint8_t rx_cache_recv_buf[RX_MSG_SIZE] = {0}; /* buf for rx packet, get size and data from mq */ +static rt_uint8_t tx_cache_pbuf[TX_CACHE_BUF_SIZE] = {0}; /* buf for tx packet, get data from pbuf payload */ + +/** + * does the driver own the particular buffer? + */ +rt_inline rt_bool_t pcnet32_is_driver_own(struct eth_device_pcnet32 *dev, rt_bool_t is_tx, rt_uint32_t idx) +{ + return (rt_bool_t)(is_tx ? ((dev->tdes[idx].status & PCNET32_DESC_STATUS_OWN) == 0) : + ((dev->rdes[idx].status & PCNET32_DESC_STATUS_OWN) == 0)); +} + +/* + * get the next desc buffer index + */ +rt_inline rt_uint32_t pcnet32_get_next_desc(struct eth_device_pcnet32 *dev, rt_uint32_t cur_idx, rt_uint32_t buf_count) +{ + return (cur_idx + 1) % buf_count; +} + +static void pcnet32_init_rx_desc_entry(struct eth_device_pcnet32 *dev, rt_uint32_t idx) +{ + struct pcnet32_rx_desc *des = dev->rdes + idx; + rt_memset(des, 0, dev->de_size); + + des->base = dev->rx_buffers + idx * dev->buffer_size; + + /* next 2 bytes are 0xf000 OR'd with the first 12 bits of the 2s complement of the length */ + rt_uint16_t bcnt = (rt_uint16_t)(-dev->buffer_size); + bcnt &= 0x0fff; + bcnt |= 0xf000; /* high 4 bits fixed 1 */ + des->buf_length = bcnt; + + /* finally, set ownership bit - transmit buffers are owned by us, receive buffers by the card */ + des->status = PCNET32_DESC_STATUS_OWN; +} + +static void pcnet32_init_tx_desc_entry(struct eth_device_pcnet32 *dev, rt_uint32_t idx) +{ + struct pcnet32_tx_desc *des = dev->tdes + idx; + rt_memset(des, 0, dev->de_size); + + des->base = dev->tx_buffers + idx * dev->buffer_size; + + /* next 2 bytes are 0xf000 OR'd with the first 12 bits of the 2s complement of the length */ + rt_uint16_t bcnt = (rt_uint16_t)(-dev->buffer_size); + bcnt &= 0x0fff; + bcnt |= 0xf000; /* high 4 bits fixed 1 */ + des->buf_length = bcnt; +} + +static rt_uint16_t pcnet32_wio_read_mac(rt_uint32_t addr, int index) +{ + return inw(addr + index); +} + +/* + * write index to RAP, read data from RDP + */ +static rt_uint16_t pcnet32_wio_read_csr(rt_uint32_t addr, int index) +{ + outw(addr + PCNET32_WIO_RAP, index); + return inw(addr + PCNET32_WIO_RDP); +} + +/** + * write index to RAP, write data to RDP + */ +static void pcnet32_wio_write_csr(rt_uint32_t addr, int index, rt_uint16_t val) +{ + outw(addr + PCNET32_WIO_RAP, index); + outw(addr + PCNET32_WIO_RDP, val); +} + +static void pcnet32_wio_write_bcr(rt_uint32_t addr, int index, rt_uint16_t val) +{ + outw(addr + PCNET32_WIO_RAP, index); + outw(addr + PCNET32_WIO_BDP, val); +} + +/* + * Reset causes the device to cease operation and clear its internal logic. + */ +static void pcnet32_wio_reset(rt_uint32_t addr) +{ + inw(addr + PCNET32_WIO_RESET); +} + +static int pcnet32_get_pci(struct eth_device_pcnet32 *dev) +{ + /* get pci device */ + rt_pci_device_t *pci_dev = rt_pci_device_get(PCNET32_VENDOR_ID, PCNET32_DEVICE_ID); + if (pci_dev == RT_NULL) + { + LOG_E("device not find on pci device.\n"); + return -1; + } + dev->pci_dev = pci_dev; + dbg_log(DBG_LOG, "find device, vendor id: 0x%x, device id: 0x%x\n", + pci_dev->vendor_id, pci_dev->device_id); + + /* enable bus mastering */ + rt_pci_enable_bus_mastering(pci_dev); + + /* get io port address */ + dev->iobase = rt_pci_device_get_io_addr(pci_dev); + if (dev->iobase == 0) + { + LOG_E("invalid pci device io address.\n"); + return -1; + } + dbg_log(DBG_LOG, "io base address: 0x%x\n", dev->iobase); + /* get irq */ + dev->irqno = rt_pci_device_get_irq_line(pci_dev); + if (dev->irqno == 0xff) + { + LOG_E("invalid irqno.\n"); + return -1; + } + dbg_log(DBG_LOG, "irqno %d\n", dev->irqno); + return 0; +} + +static int pcnet32_transmit(struct eth_device_pcnet32 *dev, rt_uint8_t *buf, rt_size_t len) +{ + if(len > ETH_FRAME_LEN) + { + len = ETH_FRAME_LEN; + } + + rt_uint32_t tx_retry = PCNET32_TX_RETRY; + + while (tx_retry > 0) + { + /* the next available descriptor entry index is in tx_buffer_ptr */ + if(!pcnet32_is_driver_own(dev, RT_TRUE, dev->tx_buffer_ptr)) + { + /* try encourage the card to send all buffers. */ + pcnet32_wio_write_csr(dev->iobase, CSR0, pcnet32_wio_read_csr(dev->iobase, CSR0) | CSR0_TXPOLL); + } + else + { + break; + } + --tx_retry; + } + + if (!tx_retry) /* retry end, no entry available */ + { + dbg_log(DBG_ERROR, "transmit no available descriptor entry\n") + return -1; + } + + rt_memcpy((void *)(dev->tx_buffers + dev->tx_buffer_ptr * dev->buffer_size), buf, len); + + struct pcnet32_tx_desc *tdes = dev->tdes + dev->tx_buffer_ptr; + /** + * set the STP bit in the descriptor entry (signals this is the first + * frame in a split packet - we only support single frames) + */ + tdes->status |= PCNET32_DESC_STATUS_STP; + + /* similarly, set the ENP bit to state this is also the end of a packet */ + tdes->status |= PCNET32_DESC_STATUS_ENP; + + rt_uint16_t bcnt = (rt_uint16_t)(-len); + bcnt &= 0xfff; + bcnt |= 0xf000; /* high 4 bits fixed 1 */ + tdes->buf_length = bcnt; + + /* finally, flip the ownership bit back to the card */ + tdes->status |= PCNET32_DESC_STATUS_OWN; + + dev->tx_buffer_ptr = pcnet32_get_next_desc(dev, dev->tx_buffer_ptr, dev->tx_buffer_count); + return 0; +} + +static rt_err_t pcnet32_tx(rt_device_t device, struct pbuf *p) +{ + rt_err_t err = RT_EOK; + /* copy data from pbuf to tx cache */ + pbuf_copy_partial(p, (void *)&tx_cache_pbuf[0], p->tot_len, 0); + if (pcnet32_transmit(GET_PCNET32(device), tx_cache_pbuf, p->tot_len) < 0) + { + err = RT_ERROR; + } + return err; +} + +static struct pbuf *pcnet32_rx(rt_device_t device) +{ + struct eth_device_pcnet32 *dev = GET_PCNET32(device); + int recv_len = 0; + struct pbuf *pbuf = RT_NULL; + rt_err_t err; + + /* get data from rx queue. */ + err = rt_mq_recv_interruptible(dev->rx_mqueue, rx_cache_recv_buf, RX_MSG_SIZE, 0); + if (err != RT_EOK) + { + return pbuf; + } + /* get recv len from rx cache, 0~3: recv len, 3-n: frame data */ + recv_len = *(int *)rx_cache_recv_buf; + if (recv_len > 0) + { + pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); + rt_memcpy(pbuf->payload, (char *)rx_cache_recv_buf + 4, recv_len); + } + return pbuf; +} + +static rt_err_t pcnet32_control(rt_device_t device, int cmd, void *args) +{ + struct eth_device_pcnet32 *dev = GET_PCNET32(device); + switch(cmd) + { + case NIOCTL_GADDR: + /* get MAC address */ + if(args) + { + rt_memcpy(args, dev->dev_addr, ETH_ALEN); + } + else + { + return -RT_ERROR; + } + break; + default : + break; + } + return RT_EOK; +} + +static void pcnet32_rx_packet(struct eth_device_pcnet32 *dev) +{ + while (pcnet32_is_driver_own(dev, RT_FALSE, dev->rx_buffer_ptr)) + { + struct pcnet32_rx_desc *rdes = dev->rdes + dev->rx_buffer_ptr; + rt_uint32_t plen = rdes->msg_length; /* msg len no need to negate it unlike BCNT above */ + + void *pbuf = (void *)(dev->rx_buffers + dev->rx_buffer_ptr * dev->buffer_size); + dbg_log(DBG_LOG, "recv packet on ring %d: buf=%p, len=%d\n", dev->rx_buffer_ptr, pbuf, plen); + /* merge size and data into receive pkg */ + rt_memcpy(rx_cache_send_buf, &plen, 4); + rt_memcpy(&rx_cache_send_buf[4], pbuf, plen); + + rt_mq_send_interrupt(dev->rx_mqueue, rx_cache_send_buf, plen + 4); + eth_device_ready(&dev->parent); /* notify eth thread to read packet */ + + /* hand the buffer back to the card */ + rdes->status = PCNET32_DESC_STATUS_OWN; + + dev->rx_buffer_ptr = pcnet32_get_next_desc(dev, dev->rx_buffer_ptr, dev->rx_buffer_count); + } +} + +static void rt_hw_pcnet32_isr(int vector, void *param) +{ + struct eth_device_pcnet32 *dev = GET_PCNET32(param); + rt_uint32_t iobase = dev->iobase; + rt_uint32_t csr0 = pcnet32_wio_read_csr(iobase, 0); + + if (csr0 & CSR0_RINT) /* recv packet */ + { + dbg_log(DBG_LOG, "RX intr occur!\n"); + pcnet32_rx_packet(dev); + } + else if ((csr0 & CSR0_TINT)) /* packet transmitted */ + { + dbg_log(DBG_LOG, "TX intr occur!\n"); + } + else if ((csr0 & CSR0_IDON)) + { + dbg_log(DBG_INFO, "init done\n"); + } + else if ((csr0 & CSR0_MERR)) + { + dbg_log(DBG_WARNING, "memory error!\n"); + } + else if ((csr0 & CSR0_MISS)) + { + dbg_log(DBG_WARNING, "missed frame!\n"); + } + else if ((csr0 & CSR0_CERR)) + { + dbg_log(DBG_WARNING, "collision error!\n"); + } + else if ((csr0 & CSR0_BABL)) + { + dbg_log(DBG_WARNING, "transmitter time-out error!\n"); + } + else + { + dbg_log(DBG_WARNING, "unknown intr\n"); + } + /* ack pcnet32 interrupt as handled */ + pcnet32_wio_write_csr(iobase, 0, csr0); +} + +static rt_err_t pcnet32_alloc_ring_buffer(struct eth_device_pcnet32 *dev) +{ + dev->rdes = rt_malloc_align(dev->rx_buffer_count * dev->de_size, 16); + if (dev->rdes == RT_NULL) + { + dbg_log(DBG_ERROR, "alloc memory for rx ring failed!"); + return RT_ERROR; + } + dev->tdes = rt_malloc_align(dev->tx_buffer_count * dev->de_size, 16); + if (dev->tdes == RT_NULL) + { + dbg_log(DBG_ERROR, "alloc memory for tx ring failed!"); + rt_free_align(dev->rdes); + return RT_ERROR; + } + + dev->rx_buffers = (uint32_t)rt_malloc_align(dev->rx_buffer_count * dev->buffer_size, 16); + if (dev->rx_buffers == 0) + { + dbg_log(DBG_ERROR, "alloc memory for rx ring buffer failed!"); + rt_free_align(dev->rdes); + rt_free_align(dev->tdes); + return RT_ERROR; + } + + dev->tx_buffers = (uint32_t)rt_malloc_align(dev->tx_buffer_count * dev->buffer_size, 16); + if (dev->tx_buffers == 0) + { + dbg_log(DBG_ERROR, "alloc memory for tx ring buffer failed!"); + rt_free_align(dev->rdes); + rt_free_align(dev->tdes); + rt_free_align((void *)dev->rx_buffers); + return RT_ERROR; + } + dbg_log(DBG_LOG, "rdes:%p tdes:%p rbuf:%p tbuf:%p\n", dev->rdes, dev->tdes, dev->rx_buffers, dev->tx_buffers); + + int i = 0; + for (i = 0; i < dev->rx_buffer_count; i++) + { + pcnet32_init_rx_desc_entry(dev, i); + } + for (i = 0; i < dev->tx_buffer_count; i++) + { + pcnet32_init_tx_desc_entry(dev, i); + } + return RT_EOK; +} + +static void pcnet32_free_ring_buffer(struct eth_device_pcnet32 *dev) +{ + rt_free_align(dev->rdes); + rt_free_align(dev->tdes); + rt_free_align((void *)dev->rx_buffers); + rt_free_align((void *)dev->tx_buffers); +} + +static void pcnet32_print_init_block(struct eth_device_pcnet32 *dev) +{ + rt_uint32_t iobase = dev->iobase; + + struct pcnet32_init_block *init_block = dev->init_block; + dbg_log(DBG_LOG, "============\nprint init block\n"); + dbg_log(DBG_LOG, "mode: %x, tlen_rlen:%x\n", init_block->mode, init_block->tlen_rlen); + dbg_log(DBG_LOG, "mac: %x:%x:%x:%x:%x:%x\n", + init_block->phys_addr[0], + init_block->phys_addr[1], + init_block->phys_addr[2], + init_block->phys_addr[3], + init_block->phys_addr[4], + init_block->phys_addr[5]); + dbg_log(DBG_LOG, "filter0: %x, filter1: %x\n", init_block->filter[0], init_block->filter[1]); + dbg_log(DBG_LOG, "rx ring dma: %x, tx ring dma: %x\n", init_block->rx_ring, init_block->tx_ring); + dbg_log(DBG_LOG, "init block dma: %x\n", dev->init_block_dma_addr); + + int i = 0; + for (; i <= 46; i++) + { + dbg_log(DBG_LOG, "csr%d=%x\n", i, pcnet32_wio_read_csr(iobase, i)); + } +} + +static rt_err_t pcnet32_init(rt_device_t device) +{ + struct eth_device_pcnet32 *dev = GET_PCNET32(device); + rt_uint32_t iobase = dev->iobase; + + /* init buffer info */ + dev->rx_buffer_ptr = 0; + dev->tx_buffer_ptr = 0; + + dev->rx_buffer_count = PCNET32_RX_BUFFERS; + dev->tx_buffer_count = PCNET32_TX_BUFFERS; + + dev->buffer_size = ETH_FRAME_LEN; + dev->de_size = PCNET32_RING_DE_SIZE; + + if (pcnet32_alloc_ring_buffer(dev) != RT_EOK) + { + return RT_ERROR; + } + + dev->rx_ring_dma_addr = (rt_ubase_t)rt_hw_vir2phy(dev->rdes); + dev->tx_ring_dma_addr = (rt_ubase_t)rt_hw_vir2phy(dev->tdes); + + /* create msg queue for eth rx */ + dev->rx_mqueue = rt_mq_create("rx_mqueue", RX_MSG_SIZE, RX_MSG_CNT, 0); + if (dev->rx_mqueue == RT_NULL) + { + LOG_E("crete msg queue for rx buffer failed!\n"); + pcnet32_free_ring_buffer(dev); + return RT_ERROR; + } + + /* alloc init block, must 16 bit align */ + dev->init_block = rt_malloc_align(sizeof(struct pcnet32_init_block), 16); + if (dev->init_block == RT_NULL) + { + dbg_log(DBG_ERROR, "alloc memory for init block failed!"); + rt_mq_delete(dev->rx_mqueue); + pcnet32_free_ring_buffer(dev); + return RT_ERROR; + } + dev->init_block_dma_addr = (rt_ubase_t)rt_hw_vir2phy(dev->init_block); + + dbg_log(DBG_LOG, "init block addr:%p size:%d\n", dev->init_block, sizeof(struct pcnet32_init_block)); + + /* fill init block */ + dev->init_block->mode = 0; + dev->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 4); + dev->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); + dev->init_block->tlen_rlen = (dev->tx_len_bits << 8) | dev->rx_len_bits; + int i = 0; + for (i = 0; i < ETH_ALEN; i++) + { + dev->init_block->phys_addr[i] = dev->dev_addr[i]; + } + dev->init_block->filter[0] = 0x00000000; + dev->init_block->filter[1] = 0x00000000; + dev->init_block->rx_ring = dev->rx_ring_dma_addr; + dev->init_block->tx_ring = dev->tx_ring_dma_addr; + + /* register init block, CSR1 save low 16 bit, CSR1 save high 16 bit */ + pcnet32_wio_write_csr(iobase, CSR1, (dev->init_block_dma_addr & 0xffff)); + pcnet32_wio_write_csr(iobase, CSR2, (dev->init_block_dma_addr >> 16) & 0xffff); + + /* register intr */ + if (rt_hw_interrupt_install(dev->irqno, rt_hw_pcnet32_isr, (void *) dev, "pcnet32") < 0) + { + LOG_E("install IRQ failed!\n"); + rt_free_align(dev->init_block); + rt_mq_delete(dev->rx_mqueue); + pcnet32_free_ring_buffer(dev); + return RT_ERROR; + } + rt_hw_interrupt_umask(dev->irqno); + + /* Start init */ + pcnet32_wio_write_csr(iobase, CSR0, CSR0_INIT | CSR0_INTEN); + dbg_log(DBG_LOG, "card init done.\n"); + + /* add auto pad amd strip recv */ + rt_uint16_t csr4 = pcnet32_wio_read_csr(iobase, CSR4); + pcnet32_wio_write_csr(iobase, CSR4, csr4 | CSR4_ASTRP_RCV | CSR4_APAD_XMT); + + /* start work */ + pcnet32_wio_write_csr(iobase, CSR0, CSR0_START | CSR0_INTEN); + + pcnet32_print_init_block(dev); + + eth_device_linkchange(&dev->parent, RT_TRUE); + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops pcnet32_ops = +{ + pcnet32_init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + pcnet32_control +}; +#endif + +static rt_err_t pcnet32_init_hw(struct eth_device_pcnet32 *dev) +{ + rt_uint32_t iobase = dev->iobase; + + /* reset card to 16 bit io mode */ + pcnet32_wio_reset(iobase); + + /* use dealy to wait reset done, at least 1 microsecond */ + rt_thread_delay(1); + + /* switch to 32 bit soft-style mode, use 32 bit struct */ + pcnet32_wio_write_bcr(iobase, 20, 0x102); + + /* stop card work */ + pcnet32_wio_write_csr(iobase, 0, 0x4); + + /* read mac addr */ + rt_uint16_t mac0 = pcnet32_wio_read_mac(iobase, 0); + rt_uint16_t mac1 = pcnet32_wio_read_mac(iobase, 2); + rt_uint16_t mac2 = pcnet32_wio_read_mac(iobase, 4); + + dev->dev_addr[0] = mac0 & 0xff; + dev->dev_addr[1] = (mac0 >> 8) & 0xff; + dev->dev_addr[2] = mac1 & 0xff; + dev->dev_addr[3] = (mac1 >> 8) & 0xff; + dev->dev_addr[4] = mac2 & 0xff; + dev->dev_addr[5] = (mac2 >> 8) & 0xff; + + dbg_log(DBG_INFO, "MAC addr: %x:%x:%x:%x:%x:%x\n", + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); + return RT_EOK; +} + +static int rt_hw_pcnet32_init(void) +{ + rt_memset(ð_dev, 0x0, sizeof(eth_dev)); + + if (pcnet32_get_pci(ð_dev) < 0) + { + return -1; + } + + if (pcnet32_init_hw(ð_dev) != RT_EOK) + { + return -1; + } + + /* set device opts */ +#ifdef RT_USING_DEVICE_OPS + eth_dev.parent.parent.ops = &pcnet32_ops; +#else + eth_dev.parent.parent.init = pcnet32_init; + eth_dev.parent.parent.open = RT_NULL; + eth_dev.parent.parent.close = RT_NULL; + eth_dev.parent.parent.read = RT_NULL; + eth_dev.parent.parent.write = RT_NULL; + eth_dev.parent.parent.control = pcnet32_control; +#endif + eth_dev.parent.parent.user_data = RT_NULL; + eth_dev.parent.eth_rx = pcnet32_rx; + eth_dev.parent.eth_tx = pcnet32_tx; + + /* register ETH device */ + if (eth_device_init(&(eth_dev.parent), DEV_NAME) != RT_EOK) + { + return -1; + } + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_pcnet32_init); diff --git a/bsp/x86/drivers/drv_pcnet32.h b/bsp/x86/drivers/drv_pcnet32.h new file mode 100644 index 0000000000000000000000000000000000000000..a6ba7397e4b9dc32dcf0dac4b26fe07e86e6be83 --- /dev/null +++ b/bsp/x86/drivers/drv_pcnet32.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-19 JasonHu first version + */ + +#ifndef __DRV_PCNET32_H__ +#define __DRV_PCNET32_H__ + +#include + +#define ETH_ALEN 6 /* MAC addr */ +#define ETH_ZLEN 60 /* Minimum length of data without CRC check */ +#define ETH_DATA_LEN 1500 /* Maximum length of data in a frame */ +#define ETH_FRAME_LEN 1518 /* Maximum Ethernet data length */ + +#define RX_MSG_CNT 8 /* 4 msg queue */ +#define RX_MSG_SIZE (ETH_FRAME_LEN + 4) /* 4 save real msg size */ + +#define TX_CACHE_BUF_SIZE (2048) + +#define JUMP_TO(label) goto label + +#define PCNET32_VENDOR_ID 0x1022 +#define PCNET32_DEVICE_ID 0x2000 + +/* Offsets from base I/O address. */ +#define PCNET32_WIO_RDP 0x10 +#define PCNET32_WIO_RAP 0x12 +#define PCNET32_WIO_RESET 0x14 +#define PCNET32_WIO_BDP 0x16 + +#define CSR0 0 +#define CSR0_INIT 0x1 +#define CSR0_START 0x2 +#define CSR0_STOP 0x4 +#define CSR0_TXPOLL 0x8 +#define CSR0_INTEN 0x40 +#define CSR0_IDON 0x0100 +#define CSR0_NORMAL (CSR0_START | CSR0_INTEN) +#define CSR0_TINT 0x0200 /* Transmit Interrupt */ +#define CSR0_RINT 0x0400 /* Receive Interrupt */ +#define CSR0_MERR 0x0800 /* Memory Error */ +#define CSR0_MISS 0x1000 /* Missed Frame */ +#define CSR0_CERR 0x2000 /* Collision Error */ +#define CSR0_BABL 0x4000 /* Babble is a transmitter time-out error. */ + +/* Error is set by the ORing of BABL, CERR, MISS, and MERR. + * ERR remains set as long as any of the error flags are true. + */ +#define CSR0_ERR 0x8000 + +#define CSR1 1 +#define CSR2 2 +#define CSR3 3 /* Interrupt Masks and Deferral Control */ +#define CSR3_IDONM (1 << 8) /* Initialization Done Mask. */ +#define CSR4 4 /* Test and Features Control */ +#define CSR4_ASTRP_RCV (1 << 10) /* Auto Strip Receive */ +#define CSR4_APAD_XMT (1 << 11) /* Auto Pad Transmit */ + +#define CSR5 5 +#define CSR5_SUSPEND 0x0001 +#define CSR6 6 /* RX/TX Descriptor Table Length */ + +#define CSR15 15 /* Mode */ +#define CSR18 18 /* Current Receive Buffer Address Lower */ +#define CSR19 19 /* Current Receive Buffer Address Upper */ +#define CSR24 24 /* Base Address of Receive Descriptor Ring Lower */ +#define CSR25 25 /* Base Address of Receive Descriptor Ring Upper */ +#define CSR30 30 /* Base Address of Transmit Descriptor Ring Lower */ +#define CSR31 31 /* Base Address of Transmit Descriptor Ring Upper */ + +#define CSR58 58 /* Software Style */ +#define CSR58_PCNET_PCI_II 0x02 + +#define PCNET32_INIT_LOW 1 +#define PCNET32_INIT_HIGH 2 +#define PCNET32_MC_FILTER 8 /* broadcast filter */ + +#define CSR72 72 /* Receive Descriptor Ring Counter */ +#define CSR74 74 /* Transmit Descriptor Ring Counter */ + +#define BCR2 2 +#define BCR2_ASEL (1 << 1) + +#define PCNET32_TX_BUFFERS 8 +#define PCNET32_RX_BUFFERS 32 +#define PCNET32_LOG_TX_BUFFERS 3 /* 2^3 = 8 buffers */ +#define PCNET32_LOG_RX_BUFFERS 5 /* 2^5 = 32 buffers */ + +#define PCNET32_RING_DE_SIZE 16 + +#define PCNET32_TX_RETRY 10 /* tx retry counter when no available descriptor entry */ + +#define PCNET32_DESC_STATUS_OWN 0x8000 /* card own the desc */ + +/** + * End of Packet indicates that this is the last buffer used by + * the PCnet-PCI II controller for this frame. + */ +#define PCNET32_DESC_STATUS_ENP 0x0100 + +/** + * Start of Packet indicates that this + * is the first buffer used by the + * PCnet-PCI II controller for this + * frame. + */ +#define PCNET32_DESC_STATUS_STP 0x0200 + +#endif /* __DRV_PCNET32_H__ */ diff --git a/bsp/x86/drivers/drv_rtl8139.c b/bsp/x86/drivers/drv_rtl8139.c new file mode 100644 index 0000000000000000000000000000000000000000..16b81e4da45219f47c89ea588a7ee0bf798a1ad0 --- /dev/null +++ b/bsp/x86/drivers/drv_rtl8139.c @@ -0,0 +1,901 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-16 JasonHu first version + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DBG_LVL DBG_INFO +#define DBG_TAG "RTL8139" +#include + +#include "drv_rtl8139.h" + +#define DEV_NAME "e0" + +#define GET_RTL8139(eth) (struct eth_device_rtl8139 *)(eth) + +struct eth_device_rtl8139 +{ + /* inherit from Ethernet device */ + struct eth_device parent; + /* interface address info. */ + rt_uint8_t dev_addr[ETH_ALEN]; /* MAC address */ + + rt_pci_device_t *pci_dev; /* pci device info */ + + rt_uint32_t iobase; /* io port base */ + rt_uint32_t irqno; /* irq number */ + + card_chip_t chipset; + + rt_spinlock_t lock; /* lock for rx packet */ + + rt_uint8_t *rx_buffer; + rt_uint8_t *rx_ring; + rt_uint8_t current_rx; /* CAPR, Current Address of Packet Read */ + rt_uint32_t rx_flags; + rt_ubase_t rx_ring_dma; /* dma phy addr */ + rt_uint32_t rx_config; /* receive config */ + struct rtl8139_status rx_status; + + rt_uint8_t *tx_buffers; + rt_uint8_t *tx_buffer[NUM_TX_DESC]; /* tx buffer pointer array */ + rt_uint32_t current_tx; + rt_uint32_t dirty_tx; + rt_size_t tx_free_counts; + rt_uint32_t tx_flags; + rt_ubase_t tx_buffer_dma; /* dma phy addr */ + struct rtl8139_status tx_status; + + struct net_device_status stats; /* device stats */ + struct rtl_extra_status xstats; /* extra status */ + + rt_uint32_t dev_flags; /* flags of net device */ + rt_mq_t rx_mqueue; /* msg queue for rx */ + rt_uint8_t linked; /* eth device linked */ +}; + +static struct eth_device_rtl8139 eth_dev; +static rt_uint8_t rx_cache_send_buf[RX_MSG_SIZE] = {0}; /* buf for rx packet, put size and data into mq */ +static rt_uint8_t rx_cache_recv_buf[RX_MSG_SIZE] = {0}; /* buf for rx packet, get size and data from mq */ +static rt_uint8_t tx_cache_pbuf[TX_CACHE_BUF_SIZE] = {0}; /* buf for tx packet, get data from pbuf payload */ + +/* rx config */ +static const rt_uint32_t rtl8139_rx_config = RX_CFG_RCV_32K | RX_NO_WRAP | + (RX_FIFO_THRESH << RX_CFG_FIFO_SHIFT) | + (RX_DMA_BURST << RX_CFG_DMA_SHIFT); + +/* tx config */ +static const rt_uint32_t rtl8139_tx_config = TX_IFG96 | (TX_DMA_BURST << TX_DMA_SHIFT) | + (TX_RETRY << TX_RETRY_SHIFT); + +/* intr mask, 1: receive, 0: ignore */ +static const rt_uint16_t rtl8139_intr_mask = PCI_ERR | PCS_TIMEOUT | RX_UNDERRUN | RX_OVERFLOW | RX_FIFO_OVER | + TX_ERR | TX_OK | RX_ERR | RX_OK; + +static int rtl8139_next_desc(int current_desc) +{ + return (current_desc == NUM_TX_DESC - 1) ? 0 : (current_desc + 1); +} + +static int rtl8139_transmit(struct eth_device_rtl8139 *dev, rt_uint8_t *buf, rt_size_t len) +{ + rt_uint32_t entry; + rt_uint32_t length = len; + + entry = dev->current_tx; + + rt_base_t level = rt_hw_interrupt_disable(); + + if (dev->tx_free_counts > 0) + { + if (length < TX_BUF_SIZE) + { + if (length < ETH_ZLEN) + { + rt_memset(dev->tx_buffer[entry], 0, ETH_ZLEN); /* pad zero */ + } + rt_memcpy(dev->tx_buffer[entry], buf, length); + } + else + { + /* drop packet */ + dev->stats.tx_dropped++; + dbg_log(DBG_WARNING, "dropped a packed!\n"); + + rt_hw_interrupt_enable(level); + return 0; + } + /* + * Writing to tx_status triggers a DMA transfer of the data + * copied to dev->tx_buffer[entry] above. Use a memory barrier + * to make sure that the device sees the updated data. + */ + rt_hw_dsb(); + + outl(dev->iobase + TX_STATUS0 + (entry * 4), dev->tx_flags | ETH_MAX(length, (rt_uint32_t)ETH_ZLEN)); + inl(dev->iobase + TX_STATUS0 + (entry * 4)); // flush + + dev->current_tx = rtl8139_next_desc(dev->current_tx); + + --dev->tx_free_counts; + } else { + LOG_E("Stop Tx packet!\n"); + rt_hw_interrupt_enable(level); + return -1; + } + rt_hw_interrupt_enable(level); + return 0; +} + +/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ +static void rtl8139_init_ring(struct eth_device_rtl8139 *dev) +{ + dev->current_rx = 0; + dev->current_tx = 0; + dev->dirty_tx = 0; + + /* set free counts */ + dev->tx_free_counts = NUM_TX_DESC; + + int i = 0; + for (; i < NUM_TX_DESC; i++) + { + dev->tx_buffer[i] = (unsigned char *)&dev->tx_buffers[i * TX_BUF_SIZE]; + } +} + +static void rtl8139_chip_reset(struct eth_device_rtl8139 *dev) +{ + /* software reset, to clear the RX and TX buffers and set everything back to defaults. */ + outb(dev->iobase + CHIP_CMD, CMD_RESET); + + /* wait reset done */ + for (;;) + { + rt_hw_dmb(); + if ((inb(dev->iobase + CHIP_CMD) & CMD_RESET) == 0) + { + break; + } + rt_hw_cpu_pause(); + } +} + +static void rtl8139_set_rx_mode(struct eth_device_rtl8139 *dev) +{ + rt_base_t level = rt_hw_interrupt_disable(); + + int rx_mode = ACCEPT_BROADCAST | ACCEPT_MY_PHYS | ACCEPT_MULTICAST; + + rx_mode |= (ACCEPT_ERR | ACCEPT_RUNT); + + rt_uint32_t tmp; + tmp = rtl8139_rx_config | rx_mode; + if (dev->rx_config != tmp) + { + outl(dev->iobase + RX_CONFIG, tmp); + /* flush */ + inl(dev->iobase + RX_CONFIG); + dev->rx_config = tmp; + } + + /* filter packet */ + rt_uint32_t mac_filter[2]; + + mac_filter[0] = mac_filter[1] = 0; + + outl(dev->iobase + MAR0 + 0, mac_filter[0]); + inl(dev->iobase + MAR0 + 0); + + outl(dev->iobase + MAR0 + 4, mac_filter[1]); + inl(dev->iobase + MAR0 + 4); + + rt_hw_interrupt_enable(level); +} + +static void rtl8139_hardware_start(struct eth_device_rtl8139 *dev) +{ + /* Bring old chips out of low-power mode. */ + if (rtl_chip_info[dev->chipset].flags & HAS_HLT_CLK) + { + outb(dev->iobase + HLT_CTL, 'R'); + } + + rtl8139_chip_reset(dev); + + /* unlock Config[01234] and BMCR register writes */ + outb(dev->iobase + CFG9346, CFG9346_UNLOCK); + inb(dev->iobase + CFG9346); // flush + + /* Restore our rtl8139a of the MAC address. */ + outl(dev->iobase + MAC0, *(rt_uint32_t *)(dev->dev_addr + 0)); + inl(dev->iobase + MAC0); + + outw(dev->iobase + MAC0 + 4, *(uint16_t *)(dev->dev_addr + 4)); + inw(dev->iobase + MAC0 + 4); + + dev->current_rx = 0; + + /* init Rx ring buffer DMA address */ + outl(dev->iobase + RX_BUF, dev->rx_ring_dma); + inl(dev->iobase + RX_BUF); + + /* Must enable Tx/Rx before setting transfer thresholds! */ + outb(dev->iobase + CHIP_CMD, CMD_RX_ENABLE | CMD_TX_ENABLE); + + /* set receive config */ + dev->rx_config = rtl8139_rx_config | ACCEPT_BROADCAST | ACCEPT_MY_PHYS; + + outl(dev->iobase + RX_CONFIG, dev->rx_config); + outl(dev->iobase + TX_CONFIG, rtl8139_tx_config); + + if (dev->chipset >= CH_8139B) + { + /* Disable magic packet scanning, which is enabled + * when PM is enabled in Config1. It can be reenabled + * via ETHTOOL_SWOL if desired. + * clear MAGIC bit + */ + outb(dev->iobase + CONFIG3, inb(dev->iobase + CONFIG3) & ~CFG3_MAGIC); + } + + /* Lock Config[01234] and BMCR register writes */ + outb(dev->iobase + CFG9346, CFG9346_LOCK); + + /* init Tx buffer DMA addresses */ + int i = 0; + for (; i < NUM_TX_DESC; i++) + { + outl(dev->iobase + TX_ADDR0 + (i * 4), dev->tx_buffer_dma + (dev->tx_buffer[i] - dev->tx_buffers)); + /* flush */ + inl(dev->iobase + TX_ADDR0 + (i * 4)); + } + + outl(dev->iobase + RX_MISSED, 0); + + rtl8139_set_rx_mode(dev); + + /* no early-rx intr */ + outw(dev->iobase + MULTI_INTR, inw(dev->iobase + MULTI_INTR) & MULTI_INTR_CLEAR); + + /* make sure tx & rx enabled */ + uint8_t tmp = inb(dev->iobase + CHIP_CMD); + if (!(tmp & CMD_RX_ENABLE) || !(tmp & CMD_TX_ENABLE)) + { + outb(dev->iobase + CHIP_CMD, CMD_RX_ENABLE | CMD_TX_ENABLE); + } + + /* enable 8139 intr mask */ + outw(dev->iobase + INTR_MASK, rtl8139_intr_mask); +} + +static int rtl8139_tx_interrupt(struct eth_device_rtl8139 *dev) +{ + while (dev->tx_free_counts < NUM_TX_DESC) + { + int entry = dev->dirty_tx; + + /* read tx status */ + int tx_status = inl(dev->iobase + TX_STATUS0 + (entry * 4)); + + /* no tx intr, exit */ + if (!(tx_status & (TX_STAT_OK | TX_UNDERRUN | TX_ABORTED))) + { + dbg_log(DBG_ERROR, "tx status not we want!\n"); + break; + } + + /* NOTE: TxCarrierLost is always asserted at 100mbps. */ + if (tx_status & (TX_OUT_OF_WINDOW | TX_ABORTED)) + { + dbg_log(DBG_ERROR, "Transmit error, Tx status %x\n", tx_status); + dev->stats.tx_errors++; + if (tx_status & TX_ABORTED) + { + dev->stats.tx_aborted_errors++; + /* clear abort bit */ + outl(dev->iobase + TX_CONFIG, TX_CLEAR_ABT); + + /* set intr tx error */ + outw(dev->iobase + INTR_STATUS, TX_ERR); + + rt_hw_dsb(); + } + if (tx_status & TX_CARRIER_LOST) + { + dev->stats.tx_carrier_errors++; + } + + if (tx_status & TX_OUT_OF_WINDOW) + { + dev->stats.tx_window_errors++; + } + } + else + { + if (tx_status & TX_UNDERRUN) + { + /* Add 64 to the Tx FIFO threshold. */ + if (dev->tx_flags < 0x00300000) { + dev->tx_flags += 0x00020000; + } + dev->stats.tx_fifo_errors++; + } + dev->stats.collisions += (tx_status >> 24) & 15; + + dev->tx_status.packets++; + dev->tx_status.bytes += tx_status & 0x7ff; + } + + dev->dirty_tx = rtl8139_next_desc(dev->dirty_tx); + + if (dev->tx_free_counts == 0) + { + rt_hw_dmb(); + } + + dev->tx_free_counts++; + } + return 0; +} + +static void rtl8139_other_interrupt(struct eth_device_rtl8139 *dev, int status, int link_changed) +{ + /* Update the error count. */ + dev->stats.rx_missed_errors += inl(dev->iobase + RX_MISSED); + outl(dev->iobase + RX_MISSED, 0); + + if ((status & RX_UNDERRUN) && link_changed && (dev->dev_flags & HAS_LNK_CHNG)) + { + dev->linked = RT_FALSE; /* dev not linked */ + status &= ~RX_UNDERRUN; + } + + if (status & (RX_UNDERRUN | RX_ERR)) + { + dev->stats.rx_errors++; + } + + if (status & PCS_TIMEOUT) + { + dev->stats.rx_length_errors++; + } + + if (status & RX_UNDERRUN) + { + dev->stats.rx_fifo_errors++; + } + + if (status & PCI_ERR) /* error on pci */ + { + rt_uint32_t pci_cmd_status; + pci_cmd_status = rt_pci_device_read(dev->pci_dev, PCI_STATUS_COMMAND); + rt_pci_device_write(dev->pci_dev, PCI_STATUS_COMMAND, pci_cmd_status); + dbg_log(DBG_ERROR, "PCI Bus error %x\n", pci_cmd_status >> 16); + } +} + +static void rtl8139_rx_error(rt_uint32_t rx_status, struct eth_device_rtl8139 *dev) +{ + rt_uint8_t tmp; + + dev->stats.rx_errors++; + + /* rx error */ + if (!(rx_status & RX_STATUS_OK)) + { + /* frame error */ + if (rx_status & (RX_BAD_SYMBOL | RX_BAD_ALIGN)) + { + dev->stats.rx_frame_errors++; + } + + /* long */ + if (rx_status & (RX_RUNT | RX_TOO_LONG)) + { + dev->stats.rx_length_errors++; + } + + /* CRC check */ + if (rx_status & RX_CRC_ERR) + { + dev->stats.rx_crc_errors++; + } + } + else + { + /* receive ok, but lost */ + dev->xstats.rx_lost_in_ring++; + } + + /* reset receive */ + tmp = inb(dev->iobase + CHIP_CMD); + outb(dev->iobase + CHIP_CMD, tmp & ~CMD_RX_ENABLE); + outb(dev->iobase + CHIP_CMD, tmp); + outl(dev->iobase + RX_CONFIG, dev->rx_config); + dev->current_rx = 0; +} + +static void rtl8139_isr_ack(struct eth_device_rtl8139 *dev) +{ + rt_uint16_t status; + + status = inw(dev->iobase + INTR_STATUS) & RX_ACK_BITS; + + /* Clear out errors and receive interrupts */ + if (status != 0) + { + if (status & (RX_FIFO_OVER | RX_OVERFLOW)) + { + dev->stats.rx_errors++; + if (status & RX_FIFO_OVER) + { + dev->stats.rx_fifo_errors++; + } + } + /* write rx ack */ + outw(dev->iobase + INTR_STATUS, RX_ACK_BITS); + inw(dev->iobase + INTR_STATUS); // for flush + } +} + +static int rtl8139_rx_interrupt(struct eth_device_rtl8139 *dev) +{ + int received = 0; + rt_uint8_t *rx_ring = dev->rx_ring; + rt_uint32_t current_rx = dev->current_rx; + rt_uint32_t rx_size = 0; + + while (!(inb(dev->iobase + CHIP_CMD) & RX_BUFFER_EMPTY)) + { + rt_uint32_t ring_offset = current_rx % RX_BUF_LEN; + rt_uint32_t rx_status; + + rt_size_t pkt_size; + + rt_hw_dmb(); + + /* read size+status of next frame from DMA ring buffer */ + rx_status = *(rt_uint32_t *)(rx_ring + ring_offset); + + /* size on high 16 bit */ + rx_size = rx_status >> 16; + + if (!(dev->dev_flags & DEV_FLAGS_RXFCS)) { + pkt_size = rx_size - 4; + } else { + pkt_size = rx_size; + } + + /* Packet copy from FIFO still in progress. + * Theoretically, this should never happen + * since early_rx is disabled. + */ + if (rx_size == 0xfff0) + { + dbg_log(DBG_WARNING, "rx fifo copy in progress\n"); + dev->xstats.early_rx++; + break; + } + + /* If Rx err or invalid rx_size/rx_status received + * (which happens if we get lost in the ring), + * Rx process gets reset, so we abort any further + * Rx processing. + */ + if ((rx_size > (MAX_ETH_FRAME_SIZE + 4) || (rx_size < 8) || (!(rx_status & RX_STATUS_OK)))) + { + if ((dev->dev_flags & DEV_FLAGS_RXALL) && (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) && + (rx_size >= 8) && (!(rx_status & RX_STATUS_OK))) + { + dev->stats.rx_errors++; + if (rx_status & RX_CRC_ERR) + { + dev->stats.rx_crc_errors++; + JUMP_TO(keep_pkt); + } + + if (rx_status & RX_RUNT) + { + dev->stats.rx_length_errors++; + JUMP_TO(keep_pkt); + } + } + /* rx error handle */ + rtl8139_rx_error(rx_status, dev); + received = -1; + JUMP_TO(out); + } + +keep_pkt: + /* merge size and data into receive pkg */ + rt_memcpy(rx_cache_send_buf, &pkt_size, 4); + rt_memcpy(&rx_cache_send_buf[4], &rx_ring[ring_offset + 4], pkt_size); + + rt_mq_send_interrupt(dev->rx_mqueue, rx_cache_send_buf, pkt_size + 4); + eth_device_ready(&dev->parent); /* notify eth thread to read packet */ + + dev->rx_status.packets++; + dev->rx_status.bytes += pkt_size; + + received++; + + /* 4:for header length(length include 4 bytes CRC) + * 3:for dword alignment + */ + current_rx = (current_rx + rx_size + 4 + 3) & ~3; + outw(dev->iobase + RX_BUF_PTR, (rt_uint16_t)(current_rx - 16)); + + rtl8139_isr_ack(dev); + } + + if (!received || rx_size == 0xfff0) + { + rtl8139_isr_ack(dev); + } + + dev->current_rx = current_rx; +out: + return received; +} + +static void rt_hw_rtl8139_isr(int vector, void *param) +{ + struct eth_device_rtl8139 *dev = GET_RTL8139(param); + + rt_uint16_t status, ackstat; + + int link_changed = 0; /* avoid bogus "uninit" warning */ + + rt_spin_lock(&dev->lock); + + status = inw(dev->iobase + INTR_STATUS); + outw(dev->iobase + INTR_STATUS, status); + + if ((status & rtl8139_intr_mask) == 0) + { + dbg_log(DBG_LOG, "no interrupt occured on me!\n"); + rt_spin_unlock(&dev->lock); + return; + } + + /* check netif state whether running. */ + if (!dev->linked) + { + /* clear intr mask, don't receive intr forever */ + outw(dev->iobase + INTR_MASK, 0); + JUMP_TO(out); + } + + /* Acknowledge all of the current interrupt sources ASAP, but + an first get an additional status bit from CSCR. */ + if (status & RX_UNDERRUN) + { + link_changed = inw(dev->iobase + CSCR) & CSCR_LINK_CHANGE; + } + + ackstat = status & ~(RX_ACK_BITS | TX_ERR); + if (ackstat) + { + outw(dev->iobase + INTR_STATUS, ackstat); + } + + if (status & RX_ACK_BITS) + { + rtl8139_rx_interrupt(dev); + } + + /* Check uncommon events with one test. */ + if (status & (PCI_ERR | PCS_TIMEOUT | RX_UNDERRUN | RX_ERR)) + { + rtl8139_other_interrupt(dev, status, link_changed); + } + + /* handle receive */ + if (status & (TX_OK | TX_ERR)) + { + rtl8139_tx_interrupt(dev); + + if (status & TX_ERR) + { + outw(dev->iobase + INTR_STATUS, TX_ERR); + } + } +out: + rt_spin_unlock(&dev->lock); +} + +static rt_err_t rtl8139_init(rt_device_t device) +{ + struct eth_device_rtl8139 *dev = GET_RTL8139(device); + + /* alloc transmit buffer */ + dev->tx_buffers = (rt_uint8_t *) rt_malloc(TX_BUF_TOTAL_LEN); + if (dev->tx_buffers == RT_NULL) + { + LOG_E("alloc memory for rtl8139 tx buffer failed!\n"); + return -1; + } + + /* alloc receive buffer */ + dev->rx_ring = (rt_uint8_t *) rt_malloc(RX_BUF_TOTAL_LEN); + if (dev->rx_ring == RT_NULL) { + LOG_E("alloc memory for rtl8139 rx buffer failed!\n"); + rt_free(dev->tx_buffers); + return -1; + } + + /* create msg queue for eth rx */ + dev->rx_mqueue = rt_mq_create("rx_mqueue", RX_MSG_SIZE, RX_MSG_CNT, 0); + if (dev->rx_mqueue == RT_NULL) + { + LOG_E("crete msg queue for rx buffer failed!\n"); + rt_free(dev->tx_buffers); + rt_free(dev->rx_ring); + return -1; + } + + dev->tx_buffer_dma = (rt_ubase_t)rt_hw_vir2phy(dev->tx_buffers); + dev->rx_ring_dma = (rt_ubase_t)rt_hw_vir2phy(dev->rx_ring); + + dev->tx_flags = (TX_FIFO_THRESH << 11) & 0x003f0000; + + /* init tx and rx ring */ + rtl8139_init_ring(dev); + rtl8139_hardware_start(dev); + + dev->dev_flags = DEV_FLAGS_RXALL; + dev->linked = RT_TRUE; + + eth_device_linkchange(&dev->parent, RT_TRUE); + + if (rt_hw_interrupt_install(dev->irqno, rt_hw_rtl8139_isr, (void *) dev, "rtl8139") < 0) + { + LOG_E("install IRQ failed!\n"); + rt_free(dev->tx_buffers); + rt_free(dev->rx_ring); + rt_mq_delete(dev->rx_mqueue); + return RT_ERROR; + } + rt_hw_interrupt_umask(dev->irqno); + + dbg_log(DBG_INFO, "ethernet card init done.\n"); + + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops rtl8139_ops = +{ + rtl8139_init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + rtl8139_control +}; +#endif + +static int rtl8139_get_pci(struct eth_device_rtl8139 *dev) +{ + /* get pci device */ + rt_pci_device_t *pci_dev = rt_pci_device_get(RTL8139_VENDOR_ID, RTL8139_DEVICE_ID); + if (pci_dev == RT_NULL) + { + LOG_E("device not find on pci device.\n"); + return -1; + } + dev->pci_dev = pci_dev; + dbg_log(DBG_LOG, "find device, vendor id: 0x%x, device id: 0x%x\n", + pci_dev->vendor_id, pci_dev->device_id); + + /* enable bus mastering */ + rt_pci_enable_bus_mastering(pci_dev); + + /* get io port address */ + dev->iobase = rt_pci_device_get_io_addr(pci_dev); + if (dev->iobase == 0) + { + LOG_E("invalid pci device io address.\n"); + return -1; + } + dbg_log(DBG_LOG, "io base address: 0x%x\n", dev->iobase); + /* get irq */ + dev->irqno = rt_pci_device_get_irq_line(pci_dev); + if (dev->irqno == 0xff) + { + LOG_E("invalid irqno.\n"); + return -1; + } + dbg_log(DBG_LOG, "irqno %d\n", dev->irqno); + return 0; +} + +static int rtl8139_init_board(struct eth_device_rtl8139 *dev) +{ + /* check for missing/broken hardware */ + if (inl(dev->iobase + TX_CONFIG) == 0xFFFFFFFF) + { + dbg_log(DBG_ERROR, "chip not responding, ignoring board.\n"); + return -1; + } + + rt_uint32_t version = inl(dev->iobase + TX_CONFIG) & HW_REVID_MASK; + int i = 0; + for (; i < CHIP_INFO_NR; i++) + { + if (version == rtl_chip_info[i].version) { + dev->chipset = i; + JUMP_TO(chip_match); + } + } + + /* if unknown chip, assume array element #0, original RTL-8139 in this case */ + i = 0; + + dbg_log(DBG_LOG, "unknown chip version, assuming RTL-8139\n"); + dbg_log(DBG_LOG, "TxConfig = 0x%x\n", inl(dev->iobase + TX_CONFIG)); + dev->chipset = 0; + +chip_match: + dbg_log(DBG_LOG, "chipset id (%x) == index %d, '%s'\n", + version, i, rtl_chip_info[i].name); + /* start netcard */ + if (dev->chipset >= CH_8139B) + { + dbg_log(DBG_WARNING, "PCI PM wakeup, not support now!\n"); + } + else + { + rt_uint8_t tmp = inb(dev->iobase + CONFIG1); + tmp &= ~(CFG1_SLEEP | CFG1_PWRDN); + outb(dev->iobase + CONFIG1, tmp); + } + + /* reset chip */ + rtl8139_chip_reset(dev); + return 0; +} + +static int rtl8139_init_hw(struct eth_device_rtl8139 *dev) +{ + rt_pci_device_t *pci_dev = dev->pci_dev; + + /* check version */ + if (pci_dev->vendor_id == RTL8139_VENDOR_ID && pci_dev->device_id == RTL8139_DEVICE_ID && + pci_dev->revision_id >= 0x20) + { + dbg_log(DBG_LOG, "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n", + pci_dev->vendor_id, pci_dev->device_id, pci_dev->revision_id); + } + + if (rtl8139_init_board(dev) < 0) + { + return -1; + } + + /* get MAC from pci config */ + int i = 0; + for (; i < ETH_ALEN; i++) { + dev->dev_addr[i] = inb(dev->iobase + MAC0 + i); + } + dbg_log(DBG_INFO, "MAC addr: %x:%x:%x:%x:%x:%x\n", dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); + + rt_spin_lock_init(&dev->lock); + + /* Put the chip into low-power mode. */ + if (rtl_chip_info[dev->chipset].flags & HAS_HLT_CLK) + { + outb(dev->iobase + HLT_CTL, 'H'); /* 'R' would leave the clock running. */ + } + return 0; +} + +static rt_err_t rtl8139_tx(rt_device_t device, struct pbuf *p) +{ + rt_err_t err = RT_EOK; + /* copy data from pbuf to tx cache */ + pbuf_copy_partial(p, (void *)&tx_cache_pbuf[0], p->tot_len, 0); + if (rtl8139_transmit(GET_RTL8139(device), tx_cache_pbuf, p->tot_len) < 0) + { + err = RT_ERROR; + } + return err; +} + +static struct pbuf *rtl8139_rx(rt_device_t device) +{ + struct eth_device_rtl8139 *dev = GET_RTL8139(device); + int recv_len = 0; + struct pbuf *pbuf = RT_NULL; + rt_err_t err; + + /* get data from rx queue. */ + err = rt_mq_recv_interruptible(dev->rx_mqueue, rx_cache_recv_buf, RX_MSG_SIZE, 0); + if (err != RT_EOK) + { + return pbuf; + } + /* get recv len from rx cache, 0~3: recv len, 3-n: frame data */ + recv_len = *(int *)rx_cache_recv_buf; + if (recv_len > 0) + { + pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); + rt_memcpy(pbuf->payload, (char *)rx_cache_recv_buf + 4, recv_len); + } + return pbuf; +} + +static rt_err_t rtl8139_control(rt_device_t device, int cmd, void *args) +{ + struct eth_device_rtl8139 *dev = GET_RTL8139(device); + switch(cmd) + { + case NIOCTL_GADDR: + /* get MAC address */ + if(args) + { + rt_memcpy(args, dev->dev_addr, ETH_ALEN); + } + else + { + return -RT_ERROR; + } + break; + default : + break; + } + return RT_EOK; +} + +static int rt_hw_rtl8139_init(void) +{ + rt_memset(ð_dev, 0x0, sizeof(eth_dev)); + + if (rtl8139_get_pci(ð_dev) < 0) + { + return -1; + } + + if (rtl8139_init_hw(ð_dev) < 0) + { + return -1; + } + + /* set device opts */ +#ifdef RT_USING_DEVICE_OPS + eth_dev.parent.parent.ops = &rtl8139_ops; +#else + eth_dev.parent.parent.init = rtl8139_init; + eth_dev.parent.parent.open = RT_NULL; + eth_dev.parent.parent.close = RT_NULL; + eth_dev.parent.parent.read = RT_NULL; + eth_dev.parent.parent.write = RT_NULL; + eth_dev.parent.parent.control = rtl8139_control; +#endif + eth_dev.parent.parent.user_data = RT_NULL; + eth_dev.parent.eth_rx = rtl8139_rx; + eth_dev.parent.eth_tx = rtl8139_tx; + + /* register ETH device */ + if (eth_device_init(&(eth_dev.parent), DEV_NAME) != RT_EOK) + { + return -1; + } + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_rtl8139_init); diff --git a/bsp/x86/drivers/drv_rtl8139.h b/bsp/x86/drivers/drv_rtl8139.h new file mode 100644 index 0000000000000000000000000000000000000000..8e1ea5d3a566a92eeb81eedf3cca0e83dcbfe89e --- /dev/null +++ b/bsp/x86/drivers/drv_rtl8139.h @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-16 JasonHu first version + */ + +#ifndef __DRV_RTL8139_H__ +#define __DRV_RTL8139_H__ + +#include + +#define ETH_ALEN 6 /* MAC addr */ +#define ETH_ZLEN 60 /* Minimum length of data without CRC check */ +#define ETH_DATA_LEN 1500 /* Maximum length of data in a frame */ +#define ETH_FRAME_LEN 1514 /* Maximum Ethernet data length without CRC checksum */ + +#define ETH_MAX(a, b) ((a) > (b) ? (a) : (b)) + +#define RX_MSG_CNT 8 /* 4 msg queue */ +#define RX_MSG_SIZE (ETH_FRAME_LEN + 4) /* 4 save real msg size */ + +#define TX_CACHE_BUF_SIZE (2048) + +#define DEV_FLAGS_RXALL (1 << 0) /* receive all pkgs */ +#define DEV_FLAGS_RXFCS (1 << 1) /* receive no crc check */ + +/* pci device info */ +#define RTL8139_VENDOR_ID 0x10ec +#define RTL8139_DEVICE_ID 0x8139 + +#define RX_BUF_IDX 2 /* 32K ring */ + +#define RX_BUF_LEN (8192 << RX_BUF_IDX) +#define RX_BUF_PAD 16 /* pad 16 bytes */ +#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */ + +/* The total length of the receive buffer */ +#define RX_BUF_TOTAL_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD) + +/* Number of Tx descriptor registers. */ +#define NUM_TX_DESC 4 + +/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/ +#define MAX_ETH_FRAME_SIZE 1536 + +/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */ +#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE +#define TX_BUF_TOTAL_LEN (TX_BUF_SIZE * NUM_TX_DESC) + +/* PCI Tuning Parameters + Threshold is bytes transferred to chip before transmission starts. */ +#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ + +/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ +#define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ +#define RX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ +#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */ + +#define JUMP_TO(label) goto label + +enum +{ + HAS_MII_XCVR = 0x010000, + HAS_CHIP_XCVR = 0x020000, + HAS_LNK_CHNG = 0x040000, +}; + +#define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */ +#define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */ +#define RTL_MIN_IO_SIZE 0x80 +#define RTL8139B_IO_SIZE 256 +#define RTL8129_CAPS HAS_MII_XCVR +#define RTL8139_CAPS (HAS_CHIP_XCVR | HAS_LNK_CHNG) + +/* Symbolic offsets to registers. */ +enum rtl8139_registers +{ + MAC0 = 0, /* Ethernet hardware address. */ + MAR0 = 8, /* Multicast filter. */ + TX_STATUS0 = 0x10, /* Transmit status (Four 32bit registers). */ + TX_ADDR0 = 0x20, /* Tx descriptors (also four 32bit). */ + RX_BUF = 0x30, + CHIP_CMD = 0x37, + RX_BUF_PTR = 0x38, + RX_BUF_ADDR = 0x3A, + INTR_MASK = 0x3C, + INTR_STATUS = 0x3E, + TX_CONFIG = 0x40, + RX_CONFIG = 0x44, + TIMER = 0x48, /* A general-purpose counter. */ + RX_MISSED = 0x4C, /* 24 bits valid, write clears. */ + CFG9346 = 0x50, + CONFIG0 = 0x51, + CONFIG1 = 0x52, + TIMER_INT = 0x54, + MEDIA_STATUS = 0x58, + CONFIG3 = 0x59, + CONFIG4 = 0x5A, /* absent on RTL-8139A */ + HLT_CTL = 0x5B, + MULTI_INTR = 0x5C, + TX_SUMMARY = 0x60, + BASIC_MODE_CTRL = 0x62, + BASIC_MODE_STATUS = 0x64, + NWAY_ADVERT = 0x66, + NWAY_LPAR = 0x68, + NWAY_EXPANSION = 0x6A, + /* Undocumented registers, but required for proper operation. */ + FIFOTMS = 0x70, /* FIFO Control and test. */ + CSCR = 0x74, /* Chip Status and Configuration Register. */ + PARA78 = 0x78, + FLASH_REG = 0xD4, /* Communication with Flash ROM, four bytes. */ + PARA7C = 0x7c, /* Magic transceiver parameter register. */ + CONFIG5 = 0xD8, /* absent on RTL-8139A */ +}; + +enum clear_bit_masks +{ + MULTI_INTR_CLEAR = 0xF000, + CHIP_CMD_CLEAR = 0xE2, + CONFIG1_CLEAR = (1 << 7) | (1 << 6) | (1 << 3) | (1 << 2) | (1 << 1), +}; + +enum chip_cmd_bits +{ + CMD_RESET = 0x10, + CMD_RX_ENABLE = 0x08, + CMD_TX_ENABLE = 0x04, + RX_BUFFER_EMPTY = 0x01, +}; + +/* Interrupt register bits, using my own meaningful names. */ +enum intr_status_bits +{ + PCI_ERR = 0x8000, + PCS_TIMEOUT = 0x4000, + RX_FIFO_OVER = 0x40, + RX_UNDERRUN = 0x20, + RX_OVERFLOW = 0x10, + TX_ERR = 0x08, + TX_OK = 0x04, + RX_ERR = 0x02, + RX_OK = 0x01, + RX_ACK_BITS = RX_FIFO_OVER | RX_OVERFLOW | RX_OK, +}; + +enum tx_status_bits +{ + TX_HOST_OWNS = 0x2000, + TX_UNDERRUN = 0x4000, + TX_STAT_OK = 0x8000, + TX_OUT_OF_WINDOW = 0x20000000, + TX_ABORTED = 0x40000000, + TX_CARRIER_LOST = 0x80000000, +}; + +enum rx_status_bits +{ + RX_MULTICAST = 0x8000, + RX_PHYSICAL = 0x4000, + RX_BROADCAST = 0x2000, + RX_BAD_SYMBOL = 0x0020, + RX_RUNT = 0x0010, + RX_TOO_LONG = 0x0008, + RX_CRC_ERR = 0x0004, + RX_BAD_ALIGN = 0x0002, + RX_STATUS_OK = 0x0001, +}; + +/* Bits in rx_config. */ +enum rx_mode_bits +{ + ACCEPT_ERR = 0x20, + ACCEPT_RUNT = 0x10, + ACCEPT_BROADCAST = 0x08, + ACCEPT_MULTICAST = 0x04, + ACCEPT_MY_PHYS = 0x02, + ACCEPT_ALL_PHYS = 0x01, +}; + +/* Bits in TxConfig. */ +enum tx_config_bits +{ + /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ + TX_IFG_SHIFT = 24, + TX_IFG84 = (0 << TX_IFG_SHIFT), /* 8.4us / 840ns (10 / 100Mbps) */ + TX_IFG88 = (1 << TX_IFG_SHIFT), /* 8.8us / 880ns (10 / 100Mbps) */ + TX_IFG92 = (2 << TX_IFG_SHIFT), /* 9.2us / 920ns (10 / 100Mbps) */ + TX_IFG96 = (3 << TX_IFG_SHIFT), /* 9.6us / 960ns (10 / 100Mbps) */ + + TX_LOOP_BACK = (1 << 18) | (1 << 17), /* enable loopback test mode */ + TX_CRC = (1 << 16), /* DISABLE Tx pkt CRC append */ + TX_CLEAR_ABT = (1 << 0), /* Clear abort (WO) */ + TX_DMA_SHIFT = 8, /* DMA burst value (0-7) is shifted X many bits */ + TX_RETRY_SHIFT = 4, /* TXRR value (0-15) is shifted X many bits */ + + TX_VERSION_MASK = 0x7C800000, /* mask out version bits 30-26, 23 */ +}; + +/* Bits in Config1 */ +enum config1_bits +{ + CFG1_PM_ENABLE = 0x01, + CFG1_VPD_ENABLE = 0x02, + CFG1_PIO = 0x04, + CFG1_MMIO = 0x08, + CFG1_LWAKE = 0x10, /* not on 8139, 8139A */ + CFG1_DRIVER_LOAD = 0x20, + CFG1_LED0 = 0x40, + CFG1_LED1 = 0x80, + CFG1_SLEEP = (1 << 1), /* only on 8139, 8139A */ + CFG1_PWRDN = (1 << 0), /* only on 8139, 8139A */ +}; + +/* Bits in Config3 */ +enum config3_bits +{ + CFG3_FAST_ENABLE = (1 << 0), /* 1 = Fast Back to Back */ + CFG3_FUNCTION_ENABLE = (1 << 1), /* 1 = enable CardBus Function registers */ + CFG3_CLKRUN_ENABLE = (1 << 2), /* 1 = enable CLKRUN */ + CFG3_CARD_BUS_ENABLE = (1 << 3), /* 1 = enable CardBus registers */ + CFG3_LINK_UP = (1 << 4), /* 1 = wake up on link up */ + CFG3_MAGIC = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ + CFG3_PARM_ENABLE = (1 << 6), /* 0 = software can set twister parameters */ + CFG3_GNT = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ +}; + +/* Bits in Config4 */ +enum config4_bits +{ + CFG4_LWPTN = (1 << 2), /* not on 8139, 8139A */ +}; + +/* Bits in Config5 */ +enum config5_bits +{ + CFG5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ + CFG5_LAN_WAKE = (1 << 1), /* 1 = enable LANWake signal */ + CFG5_LDPS = (1 << 2), /* 0 = save power when link is down */ + CFG5_FIFO_ADDR_PTR = (1 << 3), /* Realtek internal SRAM testing */ + CFG5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ + CFG5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ + CFG5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ +}; + +enum rx_config_bits +{ + /* rx fifo threshold */ + RX_CFG_FIFO_SHIFT = 13, + RX_CFG_FIFO_NONE = (7 << RX_CFG_FIFO_SHIFT), + + /* Max DMA burst */ + RX_CFG_DMA_SHIFT = 8, + RX_CFG_DMA_UNLIMITED = (7 << RX_CFG_DMA_SHIFT), + + /* rx ring buffer length */ + RX_CFG_RCV_8K = 0, + RX_CFG_RCV_16K = (1 << 11), + RX_CFG_RCV_32K = (1 << 12), + RX_CFG_RCV_64K = (1 << 11) | (1 << 12), + + /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ + RX_NO_WRAP = (1 << 7), +}; + +/* Twister tuning parameters from RealTek. + Completely undocumented, but required to tune bad links on some boards. */ +enum cscr_bits +{ + CSCR_LINK_OK = 0x0400, + CSCR_LINK_CHANGE = 0x0800, + CSCR_LINK_STATUS = 0x0f000, + CSCR_LINK_DOWN_OFF_CMD = 0x003c0, + CSCR_LINK_DOWN_CMD = 0x0f3c0, +}; + +enum config9346_bits +{ + CFG9346_LOCK = 0x00, + CFG9346_UNLOCK = 0xC0, +}; + +typedef enum { + CH_8139 = 0, + CH_8139_K, + CH_8139A, + CH_8139A_G, + CH_8139B, + CH_8130, + CH_8139C, + CH_8100, + CH_8100B_8139D, + CH_8101, +} card_chip_t; + +enum chip_flags { + HAS_HLT_CLK = (1 << 0), + HAS_LWAKE = (1 << 1), +}; + +#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ + ((b30) << 30 | (b29) << 29 | (b28) << 28 | (b27) << 27 | (b26) << 26 | (b23) << 23 | (b22) << 22) +#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) + +#define CHIP_INFO_NR 10 + +/* directly indexed by chip_t, above */ +static const struct +{ + const char *name; + rt_uint32_t version; /* from RTL8139C/RTL8139D docs */ + rt_uint32_t flags; +} rtl_chip_info[CHIP_INFO_NR] = { + { "RTL-8139", + HW_REVID(1, 0, 0, 0, 0, 0, 0), + HAS_HLT_CLK, + }, + { "RTL-8139 rev K", + HW_REVID(1, 1, 0, 0, 0, 0, 0), + HAS_HLT_CLK, + }, + { "RTL-8139A", + HW_REVID(1, 1, 1, 0, 0, 0, 0), + HAS_HLT_CLK, /* XXX undocumented? */ + }, + { "RTL-8139A rev G", + HW_REVID(1, 1, 1, 0, 0, 1, 0), + HAS_HLT_CLK, /* XXX undocumented? */ + }, + { "RTL-8139B", + HW_REVID(1, 1, 1, 1, 0, 0, 0), + HAS_LWAKE, + }, + { "RTL-8130", + HW_REVID(1, 1, 1, 1, 1, 0, 0), + HAS_LWAKE, + }, + { "RTL-8139C", + HW_REVID(1, 1, 1, 0, 1, 0, 0), + HAS_LWAKE, + }, + { "RTL-8100", + HW_REVID(1, 1, 1, 1, 0, 1, 0), + HAS_LWAKE, + }, + { "RTL-8100B/8139D", + HW_REVID(1, 1, 1, 0, 1, 0, 1), + HAS_HLT_CLK /* XXX undocumented? */ | HAS_LWAKE, + }, + { "RTL-8101", + HW_REVID(1, 1, 1, 0, 1, 1, 1), + HAS_LWAKE, + } +}; + +struct rtl8139_status +{ + rt_ubase_t packets; + rt_ubase_t bytes; +}; + +struct net_device_status +{ + rt_ubase_t tx_errors; + rt_ubase_t tx_aborted_errors; + rt_ubase_t tx_carrier_errors; + rt_ubase_t tx_window_errors; + rt_ubase_t tx_fifo_errors; + rt_ubase_t tx_dropped; + + rt_ubase_t rx_errors; + rt_ubase_t rx_length_errors; + rt_ubase_t rx_missed_errors; + rt_ubase_t rx_fifo_errors; + rt_ubase_t rx_crc_errors; + rt_ubase_t rx_frame_errors; + rt_ubase_t rx_dropped; + + rt_ubase_t tx_packets; + rt_ubase_t tx_bytes; + + rt_ubase_t collisions; +}; + +struct rtl_extra_status +{ + rt_ubase_t early_rx; + rt_ubase_t tx_buf_mapped; + rt_ubase_t tx_timeouts; + rt_ubase_t rx_lost_in_ring; +}; + +#endif /* __DRV_RTL8139_H__ */ diff --git a/bsp/x86/drivers/drv_timer.c b/bsp/x86/drivers/drv_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..f83a8513c9a91dcd1cf40e6ab1ff949d441e3bb5 --- /dev/null +++ b/bsp/x86/drivers/drv_timer.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 JasonHu first version + */ + +#include +#include +#include + +#include "board.h" + +/* PIT （Programmable Interval Timer）8253/8254 可编程中断计时器 */ + +/* +Port 40h, 8253 Counter 0 Time of Day Clock (normally mode 3) +*/ +#define PIT_COUNTER0 0x40 + +/* +Port 41h, 8253 Counter 1 RAM Refresh Counter (normally mode 2) +*/ +#define PIT_COUNTER1 0x41 + +/* +Port 42h, 8253 Counter 2 Cassette and Speaker Functions +*/ +#define PIT_COUNTER2 0x42 + +/* +Programmable interrupt timer, control word register: +Port 43h, 8253 Mode Control Register, data format: + + |7|6|5|4|3|2|1|0| Mode Control Register + | | | | | | | `---- 0=16 binary counter, 1=4 decade BCD counter + | | | | `--------- counter mode bits + | | `------------ read/write/latch format bits + `--------------- counter select bits (also 8254 read back command) + +Read Back Command Format (8254 only) + + |7|6|5|4|3|2|1|0| Read Back Command (written to Mode Control Reg) + | | | | | | | `--- must be zero + | | | | | | `---- select counter 0 + | | | | | `----- select counter 1 + | | | | `------ select counter 2 + | | | `------- 0 = latch status of selected counters + | | `-------- 0 = latch count of selected counters + `----------- 11 = read back command + +Read Back Command Status (8254 only, read from counter register) + + |7|6|5|4|3|2|1|0| Read Back Command Status + | | | | | | | `--- 0=16 binary counter, 1=4 decade BCD counter + | | | | `-------- counter mode bits (see Mode Control Reg above) + | | `----------- read/write/latch format (see Mode Control Reg) + | `------------ 1=null count (no count set), 0=count available + `------------- state of OUT pin (1=high, 0=low) +*/ +#define PIT_CTRL 0x43 + +/* Mode Control Register */ +enum ctrl_mode_bits +{ + /* Bits 76 Counter Select Bits */ + PIT_MODE_COUNTER_0 = (0), /* 00 select counter 0 */ + PIT_MODE_COUNTER_1 = (1 << 6), /* 01 select counter 1 */ + PIT_MODE_COUNTER_2 = (1 << 7), /* 10 select counter 2 */ + PIT_MODE_READ_BACK = ((1 << 6) | (1 << 7)), /* 11 read back command (8254 only, illegal on 8253, see below) */ + /* Bits 54 Read/Write/Latch Format Bits */ + PIT_MODE_LPCV = (0), /* 00 latch present counter value */ + PIT_MODE_MSB = (1 << 4), /* 01 read/write of MSB only */ + PIT_MODE_LSB = (1 << 5), /* 10 read/write of LSB only */ + PIT_MODE_MSB_LSB = ((1 << 4) | (1 << 5)), /* 11 read/write LSB, followed by write of MSB */ + /* Bits 321 Counter Mode Bits */ + + /* + 000 mode 0, interrupt on terminal count; countdown, interrupt, + then wait for a new mode or count; loading a new count in the + middle of a count stops the countdown + */ + PIT_MODE_0 = (0), + /* + 001 mode 1, programmable one-shot; countdown with optional + restart; reloading the counter will not affect the countdown + until after the following trigger + */ + PIT_MODE_1 = (1 << 1), + /* + 010 mode 2, rate generator; generate one pulse after 'count' CLK + cycles; output remains high until after the new countdown has + begun; reloading the count mid-period does not take affect + until after the period + */ + PIT_MODE_2 = (1 << 2), + /* + 011 mode 3, square wave rate generator; generate one pulse after + 'count' CLK cycles; output remains high until 1/2 of the next + countdown; it does this by decrementing by 2 until zero, at + which time it lowers the output signal, reloads the counter + and counts down again until interrupting at 0; reloading the + count mid-period does not take affect until after the period + + */ + PIT_MODE_3 = ((1 << 1) | (1 << 2)), + /* + 100 mode 4, software triggered strobe; countdown with output high + until counter zero; at zero output goes low for one CLK + period; countdown is triggered by loading counter; reloading + counter takes effect on next CLK pulse + + */ + PIT_MODE_4 = (1 << 3), + /* + 101 mode 5, hardware triggered strobe; countdown after triggering + with output high until counter zero; at zero output goes low + for one CLK period + */ + PIT_MODE_5 = ((1 << 1) | (1 << 3)), + + /* Bits 0 Counter Mode Bits */ + PIT_MODE_BINARY = (0), /* 0 0= 16 binary counter */ + PIT_MODE_BCD = (1), /* 1 1= 4 decade BCD counter */ +}; + +#define TIMER_FREQ 1193180 /* clock frequency */ +#define COUNTER0_VALUE (TIMER_FREQ / RT_TICK_PER_SECOND) + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); +} + +int rt_hw_timer_init(void) +{ + outb(PIT_CTRL, PIT_MODE_2 | PIT_MODE_MSB_LSB | + PIT_MODE_COUNTER_0 | PIT_MODE_BINARY); + outb(PIT_COUNTER0, (rt_uint8_t) (COUNTER0_VALUE & 0xff)); + outb(PIT_COUNTER0, (rt_uint8_t) (COUNTER0_VALUE >> 8) & 0xff); + + rt_hw_interrupt_install(IRQ0_CLOCK, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ0_CLOCK); + return 0; +} diff --git a/bsp/x86/drivers/drv_timer.h b/bsp/x86/drivers/drv_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..ec052afcb21aa71a3c3b02d709d1fe78873f047e --- /dev/null +++ b/bsp/x86/drivers/drv_timer.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 JasonHu first version + */ + +#ifndef __DRV_TIMER_H__ +#define __DRV_TIMER_H__ + +int rt_hw_timer_init(void); + +#endif /* __DRV_TIMER_H__ */ diff --git a/bsp/x86/drivers/drv_uart.c b/bsp/x86/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..370f153b80570c90a65cf71b5e363c7002589faf --- /dev/null +++ b/bsp/x86/drivers/drv_uart.c @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-15 JasonHu first version + */ + +#include + +#ifdef BSP_DRV_UART +#include +#include +#include "drv_uart.h" +#include "board.h" + +struct hw_uart_device +{ + rt_uint32_t hw_base; + rt_uint32_t irqno; + + rt_uint16_t data_reg; + rt_uint16_t divisor_low_reg; + rt_uint16_t intr_enable_reg; + rt_uint16_t divisor_high_reg; + rt_uint16_t intr_indenty_reg; + rt_uint16_t fifo_reg; + rt_uint16_t line_ctrl_reg; + rt_uint16_t modem_ctrl_reg; + rt_uint16_t line_status_reg; + rt_uint16_t modem_status_reg; + rt_uint16_t scratch_reg; +}; + +/* I/O port base addr */ +#define SERIAL0_BASE 0X3F8 +#define SERIAL1_BASE 0X2F8 + +#define SERIAL0_IRQ 4 +#define SERIAL1_IRQ 3 + +#define MAX_BAUD_VALUE 115200 +#define DEFAULT_BAUD_VALUE 115200 +#define DEFAULT_DIVISOR_VALUE (MAX_BAUD_VALUE / DEFAULT_BAUD_VALUE) + +enum uart_fifo_control_register_bits +{ + FIFO_ENABLE = 1, /* Enable FIFOs */ + FIFO_CLEAR_RECEIVE = (1 << 1), /* Clear Receive FIFO */ + FIFO_CLEAR_TRANSMIT = (1 << 2), /* Clear Transmit FIFO */ + FIFO_DMA_MODE_SELECT = (1 << 3), /* DMA Mode Select */ + FIFO_RESERVED = (1 << 4), /* Reserved */ + FIFO_ENABLE_64 = (1 << 5), /* Enable 64 Byte FIFO(16750) */ + /* Interrupt Trigger Level/Trigger Level */ + FIFO_TRIGGER_1 = (0 << 6), /* 1 Byte */ + FIFO_TRIGGER_4 = (1 << 6), /* 4 Byte */ + FIFO_TRIGGER_8 = (1 << 7), /* 8 Byte */ + FIFO_TRIGGER_14 = (1 << 6) | (1 << 7), /* 14 Byte */ +}; + +enum uart_line_control_register_bits +{ + /* Word Length */ + LINE_WORD_LENGTH_5 = 0, /* 5 Bits */ + LINE_WORD_LENGTH_6 = 1, /* 6 Bits */ + LINE_WORD_LENGTH_7 = (1 << 1), /* 7 Bits */ + LINE_WORD_LENGTH_8 = ((1 << 1) | 1), /* 8 Bits */ + LINE_STOP_BIT_1 = (0 << 2), /* One Stop Bit */ + LINE_STOP_BIT_2 = (1 << 2), /* 1.5 Stop Bits or 2 Stop Bits */ + /* Parity Select */ + LINE_PARITY_NO = (0 << 3), /* No Parity */ + LINE_PARITY_ODD = (1 << 3), /* Odd Parity */ + LINE_PARITY_EVEN = (1 << 3) | (1 << 4), /* Even Parity */ + LINE_PARITY_MARK = (1 << 3) | (1 << 5), /* Mark */ + LINE_PARITY_SPACE = (1 << 3) | (1 << 4) | (1 << 5), /* Space */ + LINE_BREAK_ENABLE = (1 << 6), /* Set Break Enable */ + LINE_DLAB = (1 << 7), /* Divisor Latch Access Bit */ +}; +enum uart_interrupt_enable_register_bits +{ + INTR_RECV_DATA_AVALIABLE = 1, /* Enable Received Data Available Interrupt */ + INTR_TRANSMIT_HOLDING = (1 << 1), /* Enable Transmitter Holding Register Empty Interrupt */ + INTR_STATUS_CHANGED = (1 << 2), /* Enable Receiver Line Status Interrupt */ + INTR_MODEM_STATUS = (1 << 3), /* Enable Modem Status Interrupt */ + INTR_SLEEP_MODE = (1 << 4), /* Enable Sleep Mode(16750) */ + INTR_LOW_POWER_MODE = (1 << 5), /* Enable Low Power Mode(16750) */ + INTR_RESERVED1 = (1 << 6), /* Reserved */ + INTR_RESERVED2 = (1 << 7), /* Reserved */ +}; + +enum uart_line_status_register_bits +{ + LINE_STATUS_DATA_READY = 1, /* Data Ready */ + LINE_STATUS_OVERRUN_ERROR = (1 << 1), /* Overrun Error */ + LINE_STATUS_PARITY_ERROR = (1 << 2), /* Parity Error */ + LINE_STATUS_FRAMING_ERROR = (1 << 3), /* Framing Error */ + LINE_STATUS_BREAK_INTERRUPT = (1 << 4), /* Break Interrupt */ + LINE_STATUS_EMPTY_TRANSMITTER_HOLDING = (1 << 5), /* Empty Transmitter Holding Register */ + LINE_STATUS_EMPTY_DATA_HOLDING = (1 << 6), /* Empty Data Holding Registers */ + LINE_STATUS_ERROR_RECEIVE_FIFO = (1 << 7), /* Error in Received FIFO */ +}; + +enum uart_intr_indenty_reg_bits +{ + INTR_STATUS_PENDING_FLAG = 1, /* Interrupt Pending Flag */ + /* 产生的什么中断 */ + INTR_STATUS_MODEM = (0 << 1), /* Transmitter Holding Register Empty Interrupt */ + INTR_STATUS_TRANSMITTER_HOLDING = (1 << 1), /* Received Data Available Interrupt */ + INTR_STATUS_RECEIVE_DATA = (1 << 2), /* Received Data Available Interrupt */ + INTR_STATUS_RECEIVE_LINE = (1 << 1) | (1 << 2), /* Receiver Line Status Interrupt */ + INTR_STATUS_TIME_OUT_PENDING = (1 << 2) | (1 << 3), /* Time-out Interrupt Pending (16550 & later) */ + INTR_STATUS_64BYTE_FIFO = (1 << 5), /* 64 Byte FIFO Enabled (16750 only) */ + INTR_STATUS_NO_FIFO = (0 << 6), /* No FIFO on chip */ + INTR_STATUS_RESERVED_CONDITION = (1 << 6), /* Reserved condition */ + INTR_STATUS_FIFO_NOT_FUNC = (1 << 7), /* FIFO enabled, but not functioning */ + INTR_STATUS_FIFO = (1 << 6) | (1 << 7), /* FIFO enabled */ +}; + +enum uart_modem_control_register_bits +{ + MCR_DTR = 1, /* Programs -DTR. If set, -DTR is low and the DTR pin of the port goes 'high'. */ + MCR_RTS = (1 << 1), /* Programs -RTS. dito. */ + MCR_OUT1 = (1 << 2), /* Programs -OUT1. Normally not used in a PC, but used with some + multi-port serial adapters to enable or disable a port. Best + thing is to write a '1' to this bit. */ + MCR_OUT2 = (1 << 3), /* Programs -OUT2. If set to 1, interrupts generated by the UART + are transferred to the ICU (Interrupt Control Unit) while 0 + sets the interrupt output of the card to high impedance. + (This is PC-only). */ + MCR_LOOPBACK = (1 << 4), /* '1': local loopback. All outputs disabled. This is a means of + testing the chip: you 'receive' all the data you send. */ +}; + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + RT_ASSERT(serial != RT_NULL); + serial->config = *cfg; + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + rt_uint8_t val; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + val = inb(uart->intr_enable_reg); + outb(uart->intr_enable_reg, val & ~INTR_RECV_DATA_AVALIABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + val = inb(uart->intr_enable_reg); + outb(uart->intr_enable_reg, val | INTR_RECV_DATA_AVALIABLE); + break; + } + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + int timeout = 100000; + while (!(inb(uart->line_status_reg) & LINE_STATUS_EMPTY_TRANSMITTER_HOLDING) && timeout--) + { + } + outb(uart->data_reg, c); + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + int timeout = 100000; + while (!(inb(uart->line_status_reg) & LINE_STATUS_DATA_READY) && timeout--) + { + } + int data = -1; + if (timeout > 0) + { + data = inb(uart->data_reg); + } + return data; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +#ifdef RT_USING_UART0 +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + SERIAL0_BASE, + SERIAL0_IRQ, +}; +static struct rt_serial_device _serial0; +#endif /* RT_USING_UART0 */ + +#ifdef RT_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = +{ + SERIAL1_BASE, + SERIAL1_IRQ, +}; +static struct rt_serial_device _serial1; +#endif /* RT_USING_UART1 */ + +#if defined(RT_USING_UART0) || defined(RT_USING_UART1) +static void do_uart_init(char *name, struct hw_uart_device *uart, struct rt_serial_device *serial) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_uint32_t iobase = uart->hw_base; + + uart->data_reg = iobase + 0; + uart->divisor_low_reg = iobase + 0; + uart->intr_enable_reg = iobase + 1; + uart->divisor_high_reg = iobase + 1; + uart->intr_indenty_reg = iobase + 2; + uart->line_ctrl_reg = iobase + 3; + uart->modem_ctrl_reg = iobase + 4; + uart->line_status_reg = iobase + 5; + uart->modem_status_reg = iobase + 6; + uart->scratch_reg = iobase + 7; + + /* Setting can change the baud rate Baud */ + outb(uart->line_ctrl_reg, LINE_DLAB); + + /* Set Baud rate */ + outb(uart->divisor_low_reg, (MAX_BAUD_VALUE / config.baud_rate) & 0xff); + outb(uart->divisor_high_reg, ((MAX_BAUD_VALUE / config.baud_rate) >> 8) & 0xff); + + /* Set DLAB to 0, set the character width to 8, stop bit to 1, no parity, break signal Disabled */ + outb(uart->line_ctrl_reg, LINE_WORD_LENGTH_8 | + LINE_STOP_BIT_1 | LINE_PARITY_NO); + + /* enable recv intr */ + outb(uart->intr_enable_reg, INTR_RECV_DATA_AVALIABLE | + INTR_STATUS_CHANGED | INTR_LOW_POWER_MODE); + + /* + * Set FIFO, open FIFO, clear receive FIFO, clear transmit FIFO Open 64Byte FIFO, + * interrupt trigger level is 14Byte + */ + outb(uart->fifo_reg, FIFO_ENABLE | FIFO_CLEAR_TRANSMIT | + FIFO_CLEAR_RECEIVE | FIFO_ENABLE_64 | + FIFO_TRIGGER_14); + + /* IRQs enabled, RTS/DSR set */ + outb(uart->modem_ctrl_reg, MCR_DTR | MCR_RTS | MCR_OUT2); + outb(uart->scratch_reg, 0x00); + + serial->ops = &_uart_ops; + serial->config = config; + + /* register device */ + rt_hw_serial_register(serial, name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + uart); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, name); + rt_hw_interrupt_umask(uart->irqno); +} +#endif + +int rt_hw_uart_init(void) +{ +#ifdef RT_USING_UART0 + do_uart_init("uart0", &_uart0_device, &_serial0); +#endif /* RT_USING_UART0 */ + +#ifdef RT_USING_UART1 + do_uart_init("uart1", &_uart1_device, &_serial1); +#endif /* RT_USING_UART1 */ + return 0; +} +#endif /* BSP_DRV_UART */ diff --git a/bsp/x86/drivers/drv_uart.h b/bsp/x86/drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..b22beca5d2869d540e338f71cd95be7ca789f5c6 --- /dev/null +++ b/bsp/x86/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-15 JasonHu first version + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/x86/drivers/floppy.c b/bsp/x86/drivers/floppy.c deleted file mode 100644 index c7876a68f8a2a658fea989545b0013747a36689f..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/floppy.c +++ /dev/null @@ -1,360 +0,0 @@ - -#include -#include - -#include - -typedef rt_uint8_t u8; -typedef rt_uint16_t u16; -typedef rt_uint32_t u32; - -typedef rt_int8_t s8; -typedef rt_int16_t s16; -typedef rt_int32_t s32; - -#define OUTB(v,p) outb(p,v) - -#include "floppy.h" -#include "dma.h" - -#define NULL RT_NULL -#define SECTOR_SIZE 512 -#define panic(str,...) do { rt_kprintf("panic::" str,##__VA_ARGS__); while(1); } while(0) - -#define _local_irq_save(level) level = rt_hw_interrupt_disable() -#define _local_irq_restore(level) rt_hw_interrupt_enable(level) - -static u8 floppy_buffer[512]; /* 软盘高速缓冲区地址指针 */ - -#define MAX_REPLIES 7 -static u8 floppy_reply_buffer[MAX_REPLIES]; /* 软驱回应缓冲区 */ -#define ST0 (floppy_reply_buffer[0]) /* 软驱回应0号字节 */ -#define ST1 (floppy_reply_buffer[1]) /* 软驱回应1号字节 */ -#define ST2 (floppy_reply_buffer[2]) /* 软驱回应2号字节 */ -#define ST3 (floppy_reply_buffer[3]) /* 软驱回应3号字节 */ - - -static char *floppy_inc_name; /* 软驱型号名 */ -static char *floppy_type; -static u32 floppy_motor=0; /* 软驱马达状态字节 */ -static u32 floppy_size =0; -/**********************功能函数***************************/ -static void floppy_result(void); /* 获得软驱响应状态 */ -static u32 floppy_sendbyte(u32); /* 向软驱控制寄存器发送一个控制字节 */ -static u32 floppy_getbyte(void); /* 从软驱数据寄存器得到一个数据字节 */ -static u32 floppy_get_info(void); /* 得到软驱信息 */ -static void floppy_motorOn(void); /* 打开软驱马达 */ -static void floppy_motorOff(void); /* 关闭软驱马达 */ -static void floppy_setmode(void); /* 软驱模式设置 */ -static void block_to_hts(u32, u32*, u32*, u32*); /* 逻辑块转为磁盘头、磁道号和扇区号 */ -static void floppy_setupDMA(void); /* 设置软驱DMA通道 */ -static void floppy_read_cmd(u32 blk); /* 从软盘上读取指定的逻辑块到缓冲区 */ - - -void floppy_result(void) -{ - u8 stat, i,count; - i=0; - for(count=0; count<0xFF; count++) - { - stat = inb( FD_STATUS ) & (STATUS_READY|STATUS_DIR|STATUS_BUSY); //读取状态寄存器 - if (stat == STATUS_READY) - return; - if (stat == (STATUS_READY|STATUS_DIR|STATUS_BUSY)) - { - if(i>7) break; - floppy_reply_buffer[i++]=inb_p(FD_DATA); - } - } - - panic("Get floppy status times out !\n"); -} - -u32 floppy_sendbyte( u32 value ) -{ - u8 stat, i; - - for ( i = 0; i < 128; i++ ) { - stat = inb( FD_STATUS ) & (STATUS_READY|STATUS_DIR); //读取状态寄存器 - if ( stat == STATUS_READY ) - { - OUTB( value ,FD_DATA); //将参数写入数据寄存器 - return 1; - } - io_delay(); // 作一些延迟 - } - return 0; -} - - -u32 floppy_getbyte(void) -{ - u8 stat, i; - - for ( i = 0; i < 128; i++ ) { - stat = inb( FD_STATUS ) & (STATUS_READY|STATUS_DIR|STATUS_BUSY); //读取状态寄存器 - if (stat == STATUS_READY) - return -1; - if ( stat == 0xD0 ) - return inb(FD_DATA); - io_delay(); - } - return 0; -} - - -u32 floppy_get_info(void) -{ - u32 i; - u8 CmType, FdType; - - floppy_sendbyte(0x10); - i = floppy_getbyte(); - - switch (i) - { - case 0x80: floppy_inc_name = "NEC765A controller"; break; - case 0x90: floppy_inc_name = "NEC765B controller"; break; - default: floppy_inc_name = "Enhanced controller"; break; - } - - CmType = readcmos(0x10); //read floppy type from cmos - FdType = (CmType>>4) & 0x07; - - if ( FdType == 0 ) - panic("Floppy driver not found!"); - - switch( FdType ) - { - case 0x02: // 1.2MB - floppy_type = "1.2MB"; - floppy_size = 2458*512; - break; - - case 0x04: // 1.44MB 标准软盘 - floppy_type = "1.44MB"; - floppy_size = 2880*512; - break; - - case 0x05: // 2.88MB - floppy_type = "2.88MB"; - floppy_size = 2*2880*512; - break; - } - return 1; -} - - -void floppy_motorOn( void ) -{ - u32 eflags; - if (!floppy_motor) - { - _local_irq_save(eflags); - OUTB(28,FD_DOR); - floppy_motor = 1; - _local_irq_restore(eflags); - } - return; -} - - -void floppy_motorOff( void ) -{ - u32 eflags; - if (floppy_motor) - { - _local_irq_save(eflags); - OUTB(12,FD_DOR); - floppy_motor = 0; - _local_irq_restore(eflags); - - } - return; -} - - -void floppy_setmode(void) -{ - floppy_sendbyte (FD_SPECIFY); - floppy_sendbyte (0xcf); - floppy_sendbyte (0x06); - OUTB (0,FD_DCR); -} - - -void block_to_hts(u32 block, u32 *head, u32 *track, u32 *sector ) -{ - *head = ( block % ( 18 * 2 ) ) /18; - *track = block / ( 18 * 2 ); - *sector = block % 18 + 1; -} - - -void floppy_setupDMA(void) -{ - u32 eflags; - _local_irq_save(eflags); - DisableDma(2); - ClearDmaFF(2); - SetDmaMode(2,DMA_MODE_READ); - SetDmaAddr(2,(unsigned long)floppy_buffer); - SetDmaCount(2,512); - EnableDma(2); - _local_irq_restore(eflags); -} - - -void floppy_read_cmd(u32 blk) -{ - u32 head; - u32 track; - u32 sector; - - block_to_hts(blk,&head,&track,§or); - - floppy_motorOn(); - io_delay(); - - floppy_setupDMA(); - io_delay(); - - floppy_setmode(); - io_delay(); - floppy_sendbyte (FD_READ); //send read command - floppy_sendbyte (head*4 + 0); - floppy_sendbyte (track); /* Cylinder */ - floppy_sendbyte (head); /* Head */ - floppy_sendbyte (sector); /* Sector */ - floppy_sendbyte (2); /* 0=128, 1=256, 2=512, 3=1024, ... */ - floppy_sendbyte (18); - //floppy_sendbyte (sector+secs-1); /* Last sector in track:here are sectors count */ - floppy_sendbyte (0x1B); - floppy_sendbyte (0xff); - return; -} - -static struct rt_device devF; -static struct rt_mutex lock; -static struct rt_semaphore sem; - -/* RT-Thread device interface */ - -static rt_err_t rt_floppy_init_internal(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_floppy_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt_floppy_close(rt_device_t dev) -{ - return RT_EOK; -} - -/* position: block page address, not bytes address - * buffer: - * size : how many blocks - */ -static rt_size_t rt_floppy_read(rt_device_t device, rt_off_t position, void *buffer, rt_size_t size) -{ - rt_size_t doSize = size; - - rt_mutex_take(&lock, RT_WAITING_FOREVER); - while(size>0) - { - floppy_read_cmd(position); - - rt_sem_take(&sem, RT_WAITING_FOREVER); /* waiting isr sem forever */ - - floppy_result(); - io_delay(); - - if(ST1 != 0 || ST2 != 0) - { - panic("ST0 %d ST1 %d ST2 %d\n",ST0,ST1,ST2); - } - - rt_memcpy(buffer, floppy_buffer, 512); - - floppy_motorOff(); - io_delay(); - - position += 1; - size -= 1; - } - rt_mutex_release(&lock); - - return doSize; -} - -/* position: block page address, not bytes address - * buffer: - * size : how many blocks - */ -static rt_size_t rt_floppy_write(rt_device_t device, rt_off_t position, const void *buffer, rt_size_t size) -{ - rt_mutex_take(&lock, RT_WAITING_FOREVER); - panic("FIXME:I don't know how!\n"); - rt_mutex_release(&lock); - return size; -} - -static rt_err_t rt_floppy_control(rt_device_t dev, int cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) - { - struct rt_device_blk_geometry *geometry; - - geometry = (struct rt_device_blk_geometry *)args; - if (geometry == RT_NULL) return -RT_ERROR; - - geometry->bytes_per_sector = SECTOR_SIZE; - geometry->block_size = SECTOR_SIZE; - - geometry->sector_count = floppy_size / SECTOR_SIZE; - } - - return RT_EOK; -} - -static void rt_floppy_isr(int vector, void* param) -{ - (void)vector; - (void)param; - rt_sem_release(&sem); -} - -void rt_floppy_init(void) -{ - struct rt_device *device; - - rt_mutex_init(&lock,"fdlock", RT_IPC_FLAG_FIFO); - rt_sem_init(&sem, "fdsem", 0, RT_IPC_FLAG_FIFO); - - rt_hw_interrupt_install(FLOPPY_IRQ, rt_floppy_isr, RT_NULL, "floppy"); - rt_hw_interrupt_umask(FLOPPY_IRQ); - - floppy_get_info(); - rt_kprintf("Floppy Inc : %s Floppy Type : %s\n",floppy_inc_name,floppy_type); - - device = &(devF); - - device->type = RT_Device_Class_Block; - device->init = rt_floppy_init_internal; - device->open = rt_floppy_open; - device->close = rt_floppy_close; - device->read = rt_floppy_read; - device->write = rt_floppy_write; - device->control = rt_floppy_control; - device->user_data = NULL; - - rt_device_register(device, "floppy", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - -} diff --git a/bsp/x86/drivers/floppy.h b/bsp/x86/drivers/floppy.h deleted file mode 100644 index f619508c43b7b7a0f06a7cec10ea94bd5999bdba..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/floppy.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef _FLOPPY_H -#define _FLOPPY_H - -#define FD_STATUS 0x3f4 // 主状态寄存器端口。 -#define FD_DATA 0x3f5 // 数据端口。 -#define FD_DOR 0x3f2 // 数字输出寄存器（也称为数字控制寄存器）。 -#define FD_DIR 0x3f7 // 数字输入寄存器。 -#define FD_DCR 0x3f7 // 数据传输率控制寄存器。 - -/* 主状态寄存器各比特位的含义 */ - -#define STATUS_BUSYMASK 0x0F // 驱动器忙位（每位对应一个驱动器）。 -#define STATUS_BUSY 0x10 // 软盘控制器忙。 -#define STATUS_DMA 0x20 // 0 - 为DMA 数据传输模式，1 - 为非DMA 模式。 -#define STATUS_DIR 0x40 // 传输方向：0 - CPU .. fdc，1 - 相反。 -#define STATUS_READY 0x80 // 数据寄存器就绪位。 - - -/*状态字节0（ST0）各比特位的含义 */ - -#define ST0_DS 0x03 // 驱动器选择号（发生中断时驱动器号）。 -#define ST0_HA 0x04 // 磁头号。 -#define ST0_NR 0x08 // 磁盘驱动器未准备好。 -#define ST0_ECE 0x10 // 设备检测出错（零磁道校准出错）。 -#define ST0_SE 0x20 // 寻道或重新校正操作执行结束。 -#define ST0_INTR 0xC0 // 中断代码位（中断原因），00 - 命令正常结束； - // 01 - 命令异常结束；10 - 命令无效；11 - FDD 就绪状态改变。 - -/*状态字节1（ST1）各比特位的含义 */ - -#define ST1_MAM 0x01 // 未找到地址标志(ID AM)。 -#define ST1_WP 0x02 // 写保护。 -#define ST1_ND 0x04 // 未找到指定的扇区。 -#define ST1_OR 0x10 // 数据传输超时（DMA 控制器故障）。 -#define ST1_CRC 0x20 // CRC 检验出错。 -#define ST1_EOC 0x80 // 访问超过一个磁道上的最大扇区号。 - -/*状态字节2（ST2）各比特位的含义 */ - -#define ST2_MAM 0x01 // 未找到数据地址标志。 -#define ST2_BC 0x02 // 磁道坏。 -#define ST2_SNS 0x04 // 检索（扫描）条件不满足。 -#define ST2_SEH 0x08 // 检索条件满足。 -#define ST2_WC 0x10 // 磁道（柱面）号不符。 -#define ST2_CRC 0x20 // 数据场CRC 校验错。 -#define ST2_CM 0x40 // 读数据遇到删除标志。 - -/*状态字节3（ST3）各比特位的含义 */ - -#define ST3_HA 0x04 // 磁头号。 -#define ST3_TZ 0x10 // 零磁道信号。 -#define ST3_WP 0x40 // 写保护。 - - -/* 软盘命令码 */ - -#define FD_RECALIBRATE 0x07 // 重新校正(磁头退到零磁道)。 -#define FD_SEEK 0x0F // 磁头寻道。 -#define FD_READ 0xE6 // 读数据（MT 多磁道操作，MFM 格式，跳过删除数据）。 -#define FD_WRITE 0xC5 // 写数据（MT，MFM）。 -#define FD_SENSEI 0x08 // 检测中断状态。 -#define FD_SPECIFY 0x03 // 设定驱动器参数（步进速率、磁头卸载时间等）。 - - -/* DMA 命令 */ -#define DMA_READ 0x46 // DMA 读盘，DMA 方式字（送DMA 端口12，11）。 -#define DMA_WRITE 0x4A - -extern void rt_floppy_init(void); - -#endif diff --git a/bsp/x86/drivers/include/bsp.h b/bsp/x86/drivers/include/bsp.h deleted file mode 100644 index 724f518c6e67eaa43f3a451fcc2f94fa45c782f3..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/include/bsp.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * File : bsp.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-09-15 QiuYi the first version */ - -#ifndef __BSP_H_ -#define __BSP_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/*******************************************************************/ -/* Timer Register */ -/*******************************************************************/ -#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ -#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ -#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ -#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ -#define TIMER_SEL0 0x00 /* select counter 0 */ -#define TIMER_SEL1 0x40 /* select counter 1 */ -#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ -#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ -#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ -#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ -#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ -#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ -#define TIMER_LATCH 0x00 /* latch counter for reading */ -#define TIMER_LSB 0x10 /* r/w counter LSB */ -#define TIMER_MSB 0x20 /* r/w counter MSB */ -#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ -#define TIMER_BCD 0x01 /* count in BCD */ - -#define TIMER_FREQ 1193182 -#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x)) - -#define IO_TIMER1 0x040 /* 8253 Timer #1 */ - -/*******************************************************************/ -/* Interrupt Controller */ -/*******************************************************************/ -/* these are processor defined */ -#define T_DIVIDE 0 /* divide error */ -#define T_DEBUG 1 /* debug exception */ -#define T_NMI 2 /* non-maskable interrupt */ -#define T_BRKPT 3 /* breakpoint */ -#define T_OFLOW 4 /* overflow */ -#define T_BOUND 5 /* bounds check */ -#define T_ILLOP 6 /* illegal opcode */ -#define T_DEVICE 7 /* device not available */ -#define T_DBLFLT 8 /* double fault */ -/* 9 is reserved */ -#define T_TSS 10 /* invalid task switch segment */ -#define T_SEGNP 11 /* segment not present */ -#define T_STACK 12 /* stack exception */ -#define T_GPFLT 13 /* genernal protection fault */ -#define T_PGFLT 14 /* page fault */ -/* 15 is reserved */ -#define T_FPERR 16 /* floating point error */ -#define T_ALIGN 17 /* aligment check */ -#define T_MCHK 18 /* machine check */ -#define T_DEFAULT 500 /* catchall */ - -#define INTTIMER0 0 -#define INTKEYBOARD 1 -#define INTUART0_RX 4 -#define CLOCK_IRQ 0 -#define KEYBOARD_IRQ 1 -#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ -#define ETHER_IRQ 3 /* default ethernet interrupt vector */ -#define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */ -#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ -#define XT_WINI_IRQ 5 /* xt winchester */ -#define FLOPPY_IRQ 6 /* floppy disk */ -#define PRINTER_IRQ 7 -#define AT_WINI_IRQ 14 /* at winchester */ -/* I/O Addresses of the two 8259A programmable interrupt controllers */ -#define IO_PIC1 0x20 /* Master(IRQs 0-7) */ -#define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */ -#define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */ -#define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */ - -#define MAX_HANDLERS 16 /*max number of isr handler*/ - -/*******************************************************************/ -/* CRT Register */ -/*******************************************************************/ -#define MONO_BASE 0x3b4 -#define MONO_BUF 0xb0000 -#define CGA_BASE 0x3d4 -#define CGA_BUF 0xb8000 - -#define CRT_ROWS 25 -#define CRT_COLS 80 -#define CRT_SIZE (CRT_ROWS * CRT_COLS) - -/*******************************************************************/ -/* Keyboard Register */ -/*******************************************************************/ -#define KBSTATP 0x64 /* kbd controller status port(I) */ -#define KBS_DIB 0x01 /* kbd data in buffer */ -#define KBDATAP 0x60 /* kbd data port(I) */ -/* AT keyboard */ -/* 8042 ports */ -#define KB_DATA 0x60 /* I/O port for keyboard data - Read : Read Output Buffer - Write: Write Input Buffer(8042 Data&8048 Command) */ -#define KB_CMD 0x64 /* I/O port for keyboard command - Read : Read Status Register - Write: Write Input Buffer(8042 Command) */ -#define LED_CODE 0xED -#define KB_ACK 0xFA - -/*******************************************************************/ -/* Serial Register */ -/*******************************************************************/ -/*Serial I/O code */ -#define COM1 0x3F8 -#define COMSTATUS 5 -#define COMDATA 0x01 -#define COMREAD 0 -#define COMWRITE 0 - -/* Bits definition of the Line Status Register (LSR)*/ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* Transmitter Holding Register Empty */ -#define TEMT 0x40 /* Transmitter Empty */ -#define ERFIFO 0x80 /* Error receive Fifo */ - -#ifdef __cplusplus -} -#endif - -#endif /* __BSP_H_ */ diff --git a/bsp/x86/drivers/include/grub.h b/bsp/x86/drivers/include/grub.h deleted file mode 100644 index dcfa36b81987177cb097b6612d092c60760a4ddb..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/include/grub.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * File : grub.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-10-09 Bernard the grub related definitions - * (multiboot) - */ - -#ifndef __GRUB_H__ -#define __GRUB_H__ - -/* the magic number for the multiboot header. */ -#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 - -/* the flags for the multiboot header. */ -#define MULTIBOOT_HEADER_FLAGS 0x00000003 - -/* the magic number passed by a multiboot-compliant boot loader. */ -#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002 - -#ifndef __ASM__ -/* the multiboot header. */ -typedef struct multiboot_header -{ - unsigned long magic; - unsigned long flags; - unsigned long checksum; - unsigned long header_addr; - unsigned long load_addr; - unsigned long load_end_addr; - unsigned long bss_end_addr; - unsigned long entry_addr; -} multiboot_header_t; - -/* the section header table for elf. */ -typedef struct elf_section_header_table -{ - unsigned long num; - unsigned long size; - unsigned long addr; - unsigned long shndx; -} elf_section_header_table_t; - -/* the multiboot information. */ -typedef struct multiboot_info -{ - unsigned long flags; - unsigned long mem_lower; - unsigned long mem_upper; - unsigned long boot_device; - unsigned long cmdline; - unsigned long mods_count; - unsigned long mods_addr; - union - { - aout_symbol_table_t aout_sym; - elf_section_header_table_t elf_sec; - } u; - unsigned long mmap_length; - unsigned long mmap_addr; -} multiboot_info_t; - -/* the module structure. */ -typedef struct module -{ - unsigned long mod_start; - unsigned long mod_end; - unsigned long string; - unsigned long reserved; -} module_t; - -/* the memory map. be careful that the offset 0 is base_addr_low - but no size. */ -typedef struct memory_map -{ - unsigned long size; - unsigned long base_addr_low; - unsigned long base_addr_high; - unsigned long length_low; - unsigned long length_high; - unsigned long type; -} memory_map_t; - -#endif - -#endif diff --git a/bsp/x86/drivers/include/i386.h b/bsp/x86/drivers/include/i386.h deleted file mode 100644 index 68c854932be5f725ecbd5c478458a8cc6b7b9d42..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/include/i386.h +++ /dev/null @@ -1,147 +0,0 @@ -#ifndef __I386_H_ -#define __I386_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -static __inline unsigned char inb(int port) -{ - unsigned char data; - __asm __volatile("inb %w1,%0" : "=a" (data) : "d" (port)); - return data; -} -static __inline unsigned char inb_p(unsigned short port) -{ - unsigned char _v; - __asm__ __volatile__ ("inb %1, %0\n\t" - // "outb %0,$0x80\n\t" - // "outb %0,$0x80\n\t" - // "outb %0,$0x80\n\t" - "outb %0,$0x80" - :"=a" (_v) - :"d" ((unsigned short) port)); - return _v; -} - -static __inline unsigned short inw(int port) -{ - unsigned short data; - __asm __volatile("inw %w1,%0" : "=a" (data) : "d" (port)); - return data; -} - -static __inline unsigned int inl(int port) -{ - unsigned int data; - __asm __volatile("inl %w1,%0" : "=a" (data) : "d" (port)); - return data; -} - -static __inline void insl(int port, void *addr, int cnt) -{ - __asm __volatile("cld\n\trepne\n\tinsl" : - "=D" (addr), "=c" (cnt) : - "d" (port), "0" (addr), "1" (cnt) : - "memory", "cc"); -} - -static __inline void outb(int port, unsigned char data) -{ - __asm __volatile("outb %0,%w1" : : "a" (data), "d" (port)); -} - - -static __inline void outb_p(char value, unsigned short port) -{ - __asm__ __volatile__ ("outb %0,%1\n\t" - "outb %0,$0x80" - ::"a" ((char) value),"d" ((unsigned short) port)); -} - -static __inline void outw(int port, unsigned short data) -{ - __asm __volatile("outw %0,%w1" : : "a" (data), "d" (port)); -} - -static __inline unsigned char readcmos(int reg) -{ - outb(0x70,reg); - return (unsigned char) inb(0x71); -} - -#define io_delay() \ - __asm__ __volatile__ ("pushal \n\t"\ - "mov $0x3F6, %dx \n\t" \ - "inb %dx, %al \n\t" \ - "inb %dx, %al \n\t" \ - "inb %dx, %al \n\t" \ - "inb %dx, %al \n\t" \ - "popal") - -/* Gate descriptors are slightly different*/ -struct Gatedesc { - unsigned gd_off_15_0 : 16; // low 16 bits of offset in segment - unsigned gd_ss : 16; // segment selector - unsigned gd_args : 5; // # args, 0 for interrupt/trap gates - unsigned gd_rsv1 : 3; // reserved(should be zero I guess) - unsigned gd_type :4; // type(STS_{TG,IG32,TG32}) - unsigned gd_s : 1; // must be 0 (system) - unsigned gd_dpl : 2; // descriptor(meaning new) privilege level - unsigned gd_p : 1; // Present - unsigned gd_off_31_16 : 16; // high bits of offset in segment -}; - -/* Pseudo-descriptors used for LGDT, LLDT and LIDT instructions*/ -struct Pseudodesc { - rt_uint16_t pd__garbage; // LGDT supposed to be from address 4N+2 - rt_uint16_t pd_lim; // Limit - rt_uint32_t pd_base __attribute__ ((packed)); // Base address -}; - -#define SETGATE(gate, istrap, sel, off, dpl) \ -{ \ - (gate).gd_off_15_0 = (rt_uint32_t) (off) & 0xffff; \ - (gate).gd_ss = (sel); \ - (gate).gd_args = 0; \ - (gate).gd_rsv1 = 0; \ - (gate).gd_type = (istrap) ? STS_TG32 : STS_IG32; \ - (gate).gd_s = 0; \ - (gate).gd_dpl = dpl; \ - (gate).gd_p = 1; \ - (gate).gd_off_31_16 = (rt_uint32_t) (off) >> 16; \ -} - -/* Global descriptor numbers*/ -#define GD_KT 0x08 // kernel text -#define GD_KD 0x10 // kernel data -#define GD_UT 0x18 // user text -#define GD_UD 0x20 // user data - -/* Application segment type bits*/ -#define STA_X 0x8 // Executable segment -#define STA_E 0x4 // Expand down(non-executable segments) -#define STA_C 0x4 // Conforming code segment(executable only) -#define STA_W 0x2 // Writeable(non-executable segments) -#define STA_R 0x2 // Readable(executable segments) -#define STA_A 0x1 // Accessed - -/* System segment type bits*/ -#define STS_T16A 0x1 // Available 16-bit TSS -#define STS_LDT 0x2 // Local Descriptor Table -#define STS_T16B 0x3 // Busy 16-bit TSS -#define STS_CG16 0x4 // 16-bit Call Gate -#define STS_TG 0x5 // Task Gate / Coum Transmitions -#define STS_IG16 0x6 // 16-bit Interrupt Gate -#define STS_TG16 0x7 // 16-bit Trap Gate -#define STS_T32A 0x9 // Available 32-bit TSS -#define STS_T32B 0xb // Busy 32-bit TSS -#define STS_CG32 0xc // 32-bit Call Gate -#define STS_IG32 0xe // 32-bit Interrupt Gate -#define STS_TG32 0xf // 32-bit Trap Gate - -#ifdef __cplusplus - } -#endif - -#endif diff --git a/bsp/x86/drivers/keyboard.c b/bsp/x86/drivers/keyboard.c deleted file mode 100644 index 3716c367cced425b436f2453b5a4f76e9f9e081c..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/keyboard.c +++ /dev/null @@ -1,366 +0,0 @@ -/* - * File : keyboard.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-09-15 QiuYi the first version - * 2017-08-16 Parai the 2nd version - */ - -#include -#include - -#include -#include "keyboard.h" -#include "keymap.h" - -#define FALSE RT_FALSE -#define TRUE RT_TRUE -#define PRIVATE static -#define PUBLIC -#define t_bool rt_bool_t -#define t_8 rt_uint8_t -#define t_32 rt_uint32_t - -PRIVATE KB_INPUT kb_in; -PRIVATE t_bool code_with_E0 = FALSE; -PRIVATE t_bool shift_l; /* l shift state */ -PRIVATE t_bool shift_r; /* r shift state */ -PRIVATE t_bool alt_l; /* l alt state */ -PRIVATE t_bool alt_r; /* r left state */ -PRIVATE t_bool ctrl_l; /* l ctrl state */ -PRIVATE t_bool ctrl_r; /* l ctrl state */ -PRIVATE t_bool caps_lock; /* Caps Lock */ -PRIVATE t_bool num_lock; /* Num Lock */ -PRIVATE t_bool scroll_lock; /* Scroll Lock */ -PRIVATE int column = 0; /* keyrow[column] is one value of keymap */ - -PRIVATE t_8 get_byte_from_kb_buf(); -PRIVATE void set_leds(); -PRIVATE void kb_wait(); -PRIVATE void kb_ack(); - -PUBLIC void init_keyboard() -{ - kb_in.count = 0; - kb_in.p_head = kb_in.p_tail = kb_in.buf; - - caps_lock = 0; - num_lock = 1; - scroll_lock = 0; - - set_leds(); -} -PUBLIC rt_bool_t keyboard_read(rt_uint32_t *pkey) -{ - t_8 scan_code; - t_bool make; /* TRUE : make */ - /* FALSE: break */ - t_32 key = 0; - t_32* keyrow; - - if(kb_in.count > 0){ - code_with_E0 = FALSE; - scan_code = get_byte_from_kb_buf(); - - /* start scan */ - if (scan_code == 0xE1) { - int i; - static const t_8 pausebreak_scan_code[] = {0xE1, 0x1D, 0x45, 0xE1, 0x9D, 0xC5}; - t_bool is_pausebreak = TRUE; - for(i=1;i<6;i++){ - if (get_byte_from_kb_buf() != pausebreak_scan_code[i]) { - is_pausebreak = FALSE; - break; - } - } - if (is_pausebreak) { - key = PAUSEBREAK; - } - } - else if (scan_code == 0xE0) { - code_with_E0 = TRUE; - scan_code = get_byte_from_kb_buf(); - - /* PrintScreen pressed */ - if (scan_code == 0x2A) { - code_with_E0 = FALSE; - if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { - code_with_E0 = TRUE; - if ((scan_code = get_byte_from_kb_buf()) == 0x37) { - key = PRINTSCREEN; - make = TRUE; - } - } - } - /* PrintScreen released */ - else if (scan_code == 0xB7) { - code_with_E0 = FALSE; - if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { - code_with_E0 = TRUE; - if ((scan_code = get_byte_from_kb_buf()) == 0xAA) { - key = PRINTSCREEN; - make = FALSE; - } - } - } - } /* if is not PrintScreen, scan_code is the one after 0xE0 */ - if ((key != PAUSEBREAK) && (key != PRINTSCREEN)) { - /* is Make Code or Break Code */ - make = (scan_code & FLAG_BREAK ? FALSE : TRUE); - - keyrow = &keymap[(scan_code & 0x7F) * MAP_COLS]; - - column = 0; - - t_bool caps = shift_l || shift_r; - if (caps_lock) { - if ((keyrow[0] >= 'a') && (keyrow[0] <= 'z')){ - caps = !caps; - } - } - if (caps) { - column = 1; - } - - if (code_with_E0) { - column = 2; - } - - key = keyrow[column]; - - switch(key) { - case SHIFT_L: - shift_l = make; - break; - case SHIFT_R: - shift_r = make; - break; - case CTRL_L: - ctrl_l = make; - break; - case CTRL_R: - ctrl_r = make; - break; - case ALT_L: - alt_l = make; - break; - case ALT_R: - alt_l = make; - break; - case CAPS_LOCK: - if (make) { - caps_lock = !caps_lock; - set_leds(); - } - break; - case NUM_LOCK: - if (make) { - num_lock = !num_lock; - set_leds(); - } - break; - case SCROLL_LOCK: - if (make) { - scroll_lock = !scroll_lock; - set_leds(); - } - break; - default: - break; - } - } - - if(make){ /* ignore Break Code */ - t_bool pad = FALSE; - - /* handle the small pad first */ - if ((key >= PAD_SLASH) && (key <= PAD_9)) { - pad = TRUE; - switch(key) { /* '/', '*', '-', '+', and 'Enter' in num pad */ - case PAD_SLASH: - key = '/'; - break; - case PAD_STAR: - key = '*'; - break; - case PAD_MINUS: - key = '-'; - break; - case PAD_PLUS: - key = '+'; - break; - case PAD_ENTER: - key = ENTER; - break; - default: /* keys whose value depends on the NumLock */ - if (num_lock) { /* '0' ~ '9' and '.' in num pad */ - if ((key >= PAD_0) && (key <= PAD_9)) { - key = key - PAD_0 + '0'; - } - else if (key == PAD_DOT) { - key = '.'; - } - } - else{ - switch(key) { - case PAD_HOME: - key = HOME; - break; - case PAD_END: - key = END; - break; - case PAD_PAGEUP: - key = PAGEUP; - break; - case PAD_PAGEDOWN: - key = PAGEDOWN; - break; - case PAD_INS: - key = INSERT; - break; - case PAD_UP: - key = UP; - break; - case PAD_DOWN: - key = DOWN; - break; - case PAD_LEFT: - key = LEFT; - break; - case PAD_RIGHT: - key = RIGHT; - break; - case PAD_DOT: - key = DELETE; - break; - default: - break; - } - } - break; - } - } - key |= shift_l ? FLAG_SHIFT_L : 0; - key |= shift_r ? FLAG_SHIFT_R : 0; - key |= ctrl_l ? FLAG_CTRL_L : 0; - key |= ctrl_r ? FLAG_CTRL_R : 0; - key |= alt_l ? FLAG_ALT_L : 0; - key |= alt_r ? FLAG_ALT_R : 0; - key |= pad ? FLAG_PAD : 0; - - *pkey = key; - return TRUE; - } - } - - return FALSE; -} - -PRIVATE t_8 get_byte_from_kb_buf() -{ - t_8 scan_code; - - RT_ASSERT(kb_in.count>0); - scan_code = *(kb_in.p_tail); - kb_in.p_tail++; - if (kb_in.p_tail == kb_in.buf + KB_IN_BYTES) { - kb_in.p_tail = kb_in.buf; - } - kb_in.count--; - - return scan_code; -} - -PRIVATE void kb_wait() /* wait inpit cache of 8042 */ -{ - t_8 kb_stat; - - do { - kb_stat = inb(KB_CMD); - } while (kb_stat & 0x02); -} - -PRIVATE void kb_ack() -{ - t_8 kb_read; - - do { - kb_read = inb(KB_DATA); - } while (kb_read != KB_ACK); -} - -PRIVATE void set_leds() -{ - t_8 leds = (caps_lock << 2) | (num_lock << 1) | scroll_lock; - - kb_wait(); - outb(KB_DATA, LED_CODE); - kb_ack(); - - kb_wait(); - outb(KB_DATA, leds); - kb_ack(); -} - -/** - * @addtogroup QEMU - */ -/*@{*/ - -void rt_keyboard_isr(void) -{ - rt_uint8_t data; - - if ((inb(KBSTATP) & KBS_DIB) == 0) - return ; - - data = inb(KBDATAP); - - if (kb_in.count < KB_IN_BYTES) { - *(kb_in.p_head) = data; - kb_in.p_head++; - if (kb_in.p_head == kb_in.buf + KB_IN_BYTES) { - kb_in.p_head = kb_in.buf; - } - kb_in.count++; - } -} -/* generally, this should be called in task level for all key inpit support, -but here only support a key that is composed of 2 bytes */ -rt_bool_t rt_keyboard_getc(char* c) -{ - if(kb_in.count>=2) - { - rt_uint32_t key = 0; - rt_bool_t rv=keyboard_read(&key); - - switch(key) - { - case TAB: - *c = '\t'; - break; - case ENTER: - *c = '\n'; - break; - case BACKSPACE: - *c = '\b'; - break; - default: - *c = key; - break; - } - - return rv; - } - - return RT_FALSE; -} - -/*@}*/ diff --git a/bsp/x86/drivers/keyboard.h b/bsp/x86/drivers/keyboard.h deleted file mode 100644 index f3e849df96702fb389e0715faf6128017a2cb31e..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/keyboard.h +++ /dev/null @@ -1,132 +0,0 @@ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - keyboard.h -++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - Forrest Yu, 2005 -++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -#ifndef _TINIX_KEYBOARD_H_ -#define _TINIX_KEYBOARD_H_ - - -/************************************************************************/ -/* Macros Declaration */ -/************************************************************************/ -#define KB_IN_BYTES 32 /* size of keyboard input buffer */ -#define MAP_COLS 3 /* Number of columns in keymap */ -#define NR_SCAN_CODES 0x80 /* Number of scan codes (rows in keymap) */ - -#define FLAG_BREAK 0x0080 /* Break Code */ -#define FLAG_EXT 0x0100 /* Normal function keys */ -#define FLAG_SHIFT_L 0x0200 /* Shift key */ -#define FLAG_SHIFT_R 0x0400 /* Shift key */ -#define FLAG_CTRL_L 0x0800 /* Control key */ -#define FLAG_CTRL_R 0x1000 /* Control key */ -#define FLAG_ALT_L 0x2000 /* Alternate key */ -#define FLAG_ALT_R 0x4000 /* Alternate key */ -#define FLAG_PAD 0x8000 /* keys in num pad */ - -#define MASK_RAW 0x01FF /* raw key value = code passed to tty & MASK_RAW - the value can be found either in the keymap column 0 - or in the list below */ - -/* Special keys */ -#define ESC (0x01 + FLAG_EXT) /* Esc */ -#define TAB (0x02 + FLAG_EXT) /* Tab */ -#define ENTER (0x03 + FLAG_EXT) /* Enter */ -#define BACKSPACE (0x04 + FLAG_EXT) /* BackSpace */ - -#define GUI_L (0x05 + FLAG_EXT) /* L GUI */ -#define GUI_R (0x06 + FLAG_EXT) /* R GUI */ -#define APPS (0x07 + FLAG_EXT) /* APPS */ - -/* Shift, Ctrl, Alt */ -#define SHIFT_L (0x08 + FLAG_EXT) /* L Shift */ -#define SHIFT_R (0x09 + FLAG_EXT) /* R Shift */ -#define CTRL_L (0x0A + FLAG_EXT) /* L Ctrl */ -#define CTRL_R (0x0B + FLAG_EXT) /* R Ctrl */ -#define ALT_L (0x0C + FLAG_EXT) /* L Alt */ -#define ALT_R (0x0D + FLAG_EXT) /* R Alt */ - -/* Lock keys */ -#define CAPS_LOCK (0x0E + FLAG_EXT) /* Caps Lock */ -#define NUM_LOCK (0x0F + FLAG_EXT) /* Number Lock */ -#define SCROLL_LOCK (0x10 + FLAG_EXT) /* Scroll Lock */ - -/* Function keys */ -#define F1 (0x11 + FLAG_EXT) /* F1 */ -#define F2 (0x12 + FLAG_EXT) /* F2 */ -#define F3 (0x13 + FLAG_EXT) /* F3 */ -#define F4 (0x14 + FLAG_EXT) /* F4 */ -#define F5 (0x15 + FLAG_EXT) /* F5 */ -#define F6 (0x16 + FLAG_EXT) /* F6 */ -#define F7 (0x17 + FLAG_EXT) /* F7 */ -#define F8 (0x18 + FLAG_EXT) /* F8 */ -#define F9 (0x19 + FLAG_EXT) /* F9 */ -#define F10 (0x1A + FLAG_EXT) /* F10 */ -#define F11 (0x1B + FLAG_EXT) /* F11 */ -#define F12 (0x1C + FLAG_EXT) /* F12 */ - -/* Control Pad */ -#define PRINTSCREEN (0x1D + FLAG_EXT) /* Print Screen */ -#define PAUSEBREAK (0x1E + FLAG_EXT) /* Pause/Break */ -#define INSERT (0x1F + FLAG_EXT) /* Insert */ -#define DELETE (0x20 + FLAG_EXT) /* Delete */ -#define HOME (0x21 + FLAG_EXT) /* Home */ -#define END (0x22 + FLAG_EXT) /* End */ -#define PAGEUP (0x23 + FLAG_EXT) /* Page Up */ -#define PAGEDOWN (0x24 + FLAG_EXT) /* Page Down */ -#define UP (0x25 + FLAG_EXT) /* Up */ -#define DOWN (0x26 + FLAG_EXT) /* Down */ -#define LEFT (0x27 + FLAG_EXT) /* Left */ -#define RIGHT (0x28 + FLAG_EXT) /* Right */ - -/* ACPI keys */ -#define POWER (0x29 + FLAG_EXT) /* Power */ -#define SLEEP (0x2A + FLAG_EXT) /* Sleep */ -#define WAKE (0x2B + FLAG_EXT) /* Wake Up */ - -/* Num Pad */ -#define PAD_SLASH (0x2C + FLAG_EXT) /* / */ -#define PAD_STAR (0x2D + FLAG_EXT) /* * */ -#define PAD_MINUS (0x2E + FLAG_EXT) /* - */ -#define PAD_PLUS (0x2F + FLAG_EXT) /* + */ -#define PAD_ENTER (0x30 + FLAG_EXT) /* Enter */ -#define PAD_DOT (0x31 + FLAG_EXT) /* . */ -#define PAD_0 (0x32 + FLAG_EXT) /* 0 */ -#define PAD_1 (0x33 + FLAG_EXT) /* 1 */ -#define PAD_2 (0x34 + FLAG_EXT) /* 2 */ -#define PAD_3 (0x35 + FLAG_EXT) /* 3 */ -#define PAD_4 (0x36 + FLAG_EXT) /* 4 */ -#define PAD_5 (0x37 + FLAG_EXT) /* 5 */ -#define PAD_6 (0x38 + FLAG_EXT) /* 6 */ -#define PAD_7 (0x39 + FLAG_EXT) /* 7 */ -#define PAD_8 (0x3A + FLAG_EXT) /* 8 */ -#define PAD_9 (0x3B + FLAG_EXT) /* 9 */ -#define PAD_UP PAD_8 /* Up */ -#define PAD_DOWN PAD_2 /* Down */ -#define PAD_LEFT PAD_4 /* Left */ -#define PAD_RIGHT PAD_6 /* Right */ -#define PAD_HOME PAD_7 /* Home */ -#define PAD_END PAD_1 /* End */ -#define PAD_PAGEUP PAD_9 /* Page Up */ -#define PAD_PAGEDOWN PAD_3 /* Page Down */ -#define PAD_INS PAD_0 /* Ins */ -#define PAD_MID PAD_5 /* Middle key */ -#define PAD_DEL PAD_DOT /* Del */ - - -/************************************************************************/ -/* Stucture Definition */ -/************************************************************************/ -/* Keyboard structure, 1 per console. */ -typedef struct s_kb { - char* p_head; /* input cache pointer */ - char* p_tail; /* read cache pointer */ - int count; - char buf[KB_IN_BYTES]; -}KB_INPUT; - - - -#endif /* _TINIX_KEYBOARD_H_ */ diff --git a/bsp/x86/drivers/keymap.h b/bsp/x86/drivers/keymap.h deleted file mode 100644 index 3031438a1bea56c13c63e4d7a5457587be321295..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/keymap.h +++ /dev/null @@ -1,239 +0,0 @@ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - keymap.h -++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - Forrest Yu, 2005 -++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/********************************************************************/ -/* "scan code" <--> "key" map. */ -/* It should be and can only be included by keyboard.c! */ -/********************************************************************/ - -#ifndef _TINIX_KEYMAP_H_ -#define _TINIX_KEYMAP_H_ - - -/* Keymap for US MF-2 keyboard. */ - -rt_uint32_t keymap[NR_SCAN_CODES * MAP_COLS] = { - -/* scan-code !Shift Shift E0 XX */ -/* ==================================================================== */ -/* 0x00 - none */ 0, 0, 0, -/* 0x01 - ESC */ ESC, ESC, 0, -/* 0x02 - '1' */ '1', '!', 0, -/* 0x03 - '2' */ '2', '@', 0, -/* 0x04 - '3' */ '3', '#', 0, -/* 0x05 - '4' */ '4', '$', 0, -/* 0x06 - '5' */ '5', '%', 0, -/* 0x07 - '6' */ '6', '^', 0, -/* 0x08 - '7' */ '7', '&', 0, -/* 0x09 - '8' */ '8', '*', 0, -/* 0x0A - '9' */ '9', '(', 0, -/* 0x0B - '0' */ '0', ')', 0, -/* 0x0C - '-' */ '-', '_', 0, -/* 0x0D - '=' */ '=', '+', 0, -/* 0x0E - BS */ BACKSPACE, BACKSPACE, 0, -/* 0x0F - TAB */ TAB, TAB, 0, -/* 0x10 - 'q' */ 'q', 'Q', 0, -/* 0x11 - 'w' */ 'w', 'W', 0, -/* 0x12 - 'e' */ 'e', 'E', 0, -/* 0x13 - 'r' */ 'r', 'R', 0, -/* 0x14 - 't' */ 't', 'T', 0, -/* 0x15 - 'y' */ 'y', 'Y', 0, -/* 0x16 - 'u' */ 'u', 'U', 0, -/* 0x17 - 'i' */ 'i', 'I', 0, -/* 0x18 - 'o' */ 'o', 'O', 0, -/* 0x19 - 'p' */ 'p', 'P', 0, -/* 0x1A - '[' */ '[', '{', 0, -/* 0x1B - ']' */ ']', '}', 0, -/* 0x1C - CR/LF */ ENTER, ENTER, PAD_ENTER, -/* 0x1D - l. Ctrl */ CTRL_L, CTRL_L, CTRL_R, -/* 0x1E - 'a' */ 'a', 'A', 0, -/* 0x1F - 's' */ 's', 'S', 0, -/* 0x20 - 'd' */ 'd', 'D', 0, -/* 0x21 - 'f' */ 'f', 'F', 0, -/* 0x22 - 'g' */ 'g', 'G', 0, -/* 0x23 - 'h' */ 'h', 'H', 0, -/* 0x24 - 'j' */ 'j', 'J', 0, -/* 0x25 - 'k' */ 'k', 'K', 0, -/* 0x26 - 'l' */ 'l', 'L', 0, -/* 0x27 - ';' */ ';', ':', 0, -/* 0x28 - '\'' */ '\'', '"', 0, -/* 0x29 - '`' */ '`', '~', 0, -/* 0x2A - l. SHIFT */ SHIFT_L, SHIFT_L, 0, -/* 0x2B - '\' */ '\\', '|', 0, -/* 0x2C - 'z' */ 'z', 'Z', 0, -/* 0x2D - 'x' */ 'x', 'X', 0, -/* 0x2E - 'c' */ 'c', 'C', 0, -/* 0x2F - 'v' */ 'v', 'V', 0, -/* 0x30 - 'b' */ 'b', 'B', 0, -/* 0x31 - 'n' */ 'n', 'N', 0, -/* 0x32 - 'm' */ 'm', 'M', 0, -/* 0x33 - ',' */ ',', '<', 0, -/* 0x34 - '.' */ '.', '>', 0, -/* 0x35 - '/' */ '/', '?', PAD_SLASH, -/* 0x36 - r. SHIFT */ SHIFT_R, SHIFT_R, 0, -/* 0x37 - '*' */ '*', '*', 0, -/* 0x38 - ALT */ ALT_L, ALT_L, ALT_R, -/* 0x39 - ' ' */ ' ', ' ', 0, -/* 0x3A - CapsLock */ CAPS_LOCK, CAPS_LOCK, 0, -/* 0x3B - F1 */ F1, F1, 0, -/* 0x3C - F2 */ F2, F2, 0, -/* 0x3D - F3 */ F3, F3, 0, -/* 0x3E - F4 */ F4, F4, 0, -/* 0x3F - F5 */ F5, F5, 0, -/* 0x40 - F6 */ F6, F6, 0, -/* 0x41 - F7 */ F7, F7, 0, -/* 0x42 - F8 */ F8, F8, 0, -/* 0x43 - F9 */ F9, F9, 0, -/* 0x44 - F10 */ F10, F10, 0, -/* 0x45 - NumLock */ NUM_LOCK, NUM_LOCK, 0, -/* 0x46 - ScrLock */ SCROLL_LOCK, SCROLL_LOCK, 0, -/* 0x47 - Home */ PAD_HOME, '7', HOME, -/* 0x48 - CurUp */ PAD_UP, '8', UP, -/* 0x49 - PgUp */ PAD_PAGEUP, '9', PAGEUP, -/* 0x4A - '-' */ PAD_MINUS, '-', 0, -/* 0x4B - Left */ PAD_LEFT, '4', LEFT, -/* 0x4C - MID */ PAD_MID, '5', 0, -/* 0x4D - Right */ PAD_RIGHT, '6', RIGHT, -/* 0x4E - '+' */ PAD_PLUS, '+', 0, -/* 0x4F - End */ PAD_END, '1', END, -/* 0x50 - Down */ PAD_DOWN, '2', DOWN, -/* 0x51 - PgDown */ PAD_PAGEDOWN, '3', PAGEDOWN, -/* 0x52 - Insert */ PAD_INS, '0', INSERT, -/* 0x53 - Delete */ PAD_DOT, '.', DELETE, -/* 0x54 - Enter */ 0, 0, 0, -/* 0x55 - ??? */ 0, 0, 0, -/* 0x56 - ??? */ 0, 0, 0, -/* 0x57 - F11 */ F11, F11, 0, -/* 0x58 - F12 */ F12, F12, 0, -/* 0x59 - ??? */ 0, 0, 0, -/* 0x5A - ??? */ 0, 0, 0, -/* 0x5B - ??? */ 0, 0, GUI_L, -/* 0x5C - ??? */ 0, 0, GUI_R, -/* 0x5D - ??? */ 0, 0, APPS, -/* 0x5E - ??? */ 0, 0, 0, -/* 0x5F - ??? */ 0, 0, 0, -/* 0x60 - ??? */ 0, 0, 0, -/* 0x61 - ??? */ 0, 0, 0, -/* 0x62 - ??? */ 0, 0, 0, -/* 0x63 - ??? */ 0, 0, 0, -/* 0x64 - ??? */ 0, 0, 0, -/* 0x65 - ??? */ 0, 0, 0, -/* 0x66 - ??? */ 0, 0, 0, -/* 0x67 - ??? */ 0, 0, 0, -/* 0x68 - ??? */ 0, 0, 0, -/* 0x69 - ??? */ 0, 0, 0, -/* 0x6A - ??? */ 0, 0, 0, -/* 0x6B - ??? */ 0, 0, 0, -/* 0x6C - ??? */ 0, 0, 0, -/* 0x6D - ??? */ 0, 0, 0, -/* 0x6E - ??? */ 0, 0, 0, -/* 0x6F - ??? */ 0, 0, 0, -/* 0x70 - ??? */ 0, 0, 0, -/* 0x71 - ??? */ 0, 0, 0, -/* 0x72 - ??? */ 0, 0, 0, -/* 0x73 - ??? */ 0, 0, 0, -/* 0x74 - ??? */ 0, 0, 0, -/* 0x75 - ??? */ 0, 0, 0, -/* 0x76 - ??? */ 0, 0, 0, -/* 0x77 - ??? */ 0, 0, 0, -/* 0x78 - ??? */ 0, 0, 0, -/* 0x78 - ??? */ 0, 0, 0, -/* 0x7A - ??? */ 0, 0, 0, -/* 0x7B - ??? */ 0, 0, 0, -/* 0x7C - ??? */ 0, 0, 0, -/* 0x7D - ??? */ 0, 0, 0, -/* 0x7E - ??? */ 0, 0, 0, -/* 0x7F - ??? */ 0, 0, 0 -}; - -/*====================================================================================* - Appendix: Scan code set 1 - *====================================================================================* - -KEY MAKE BREAK ----- KEY MAKE BREAK ----- KEY MAKE BREAK --------------------------------------------------------------------------------------- -A 1E 9E 9 0A 8A [ 1A 9A -B 30 B0 ` 29 89 INSERT E0,52 E0,D2 -C 2E AE - 0C 8C HOME E0,47 E0,C7 -D 20 A0 = 0D 8D PG UP E0,49 E0,C9 -E 12 92 \ 2B AB DELETE E0,53 E0,D3 -F 21 A1 BKSP 0E 8E END E0,4F E0,CF -G 22 A2 SPACE 39 B9 PG DN E0,51 E0,D1 -H 23 A3 TAB 0F 8F U ARROW E0,48 E0,C8 -I 17 97 CAPS 3A BA L ARROW E0,4B E0,CB -J 24 A4 L SHFT 2A AA D ARROW E0,50 E0,D0 -K 25 A5 L CTRL 1D 9D R ARROW E0,4D E0,CD -L 26 A6 L GUI E0,5B E0,DB NUM 45 C5 -M 32 B2 L ALT 38 B8 KP / E0,35 E0,B5 -N 31 B1 R SHFT 36 B6 KP * 37 B7 -O 18 98 R CTRL E0,1D E0,9D KP - 4A CA -P 19 99 R GUI E0,5C E0,DC KP + 4E CE -Q 10 19 R ALT E0,38 E0,B8 KP EN E0,1C E0,9C -R 13 93 APPS E0,5D E0,DD KP . 53 D3 -S 1F 9F ENTER 1C 9C KP 0 52 D2 -T 14 94 ESC 01 81 KP 1 4F CF -U 16 96 F1 3B BB KP 2 50 D0 -V 2F AF F2 3C BC KP 3 51 D1 -W 11 91 F3 3D BD KP 4 4B CB -X 2D AD F4 3E BE KP 5 4C CC -Y 15 95 F5 3F BF KP 6 4D CD -Z 2C AC F6 40 C0 KP 7 47 C7 -0 0B 8B F7 41 C1 KP 8 48 C8 -1 02 82 F8 42 C2 KP 9 49 C9 -2 03 83 F9 43 C3 ] 1B 9B -3 04 84 F10 44 C4 ; 27 A7 -4 05 85 F11 57 D7 ' 28 A8 -5 06 86 F12 58 D8 , 33 B3 - -6 07 87 PRTSCRN E0,2A E0,B7 . 34 B4 - E0,37 E0,AA - -7 08 88 SCROLL 46 C6 / 35 B5 - -8 09 89 PAUSE E1,1D,45 -NONE- - E1,9D,C5 - - ------------------ -ACPI Scan Codes: -------------------------------------------- -Key Make Code Break Code -------------------------------------------- -Power E0, 5E E0, DE -Sleep E0, 5F E0, DF -Wake E0, 63 E0, E3 - - -------------------------------- -Windows Multimedia Scan Codes: -------------------------------------------- -Key Make Code Break Code -------------------------------------------- -Next Track E0, 19 E0, 99 -Previous Track E0, 10 E0, 90 -Stop E0, 24 E0, A4 -Play/Pause E0, 22 E0, A2 -Mute E0, 20 E0, A0 -Volume Up E0, 30 E0, B0 -Volume Down E0, 2E E0, AE -Media Select E0, 6D E0, ED -E-Mail E0, 6C E0, EC -Calculator E0, 21 E0, A1 -My Computer E0, 6B E0, EB -WWW Search E0, 65 E0, E5 -WWW Home E0, 32 E0, B2 -WWW Back E0, 6A E0, EA -WWW Forward E0, 69 E0, E9 -WWW Stop E0, 68 E0, E8 -WWW Refresh E0, 67 E0, E7 -WWW Favorites E0, 66 E0, E6 - -*=====================================================================================*/ - - - -#endif /* _TINIX_KEYMAP_H_ */ diff --git a/bsp/x86/drivers/pci.c b/bsp/x86/drivers/pci.c new file mode 100644 index 0000000000000000000000000000000000000000..16b561bf33bd20ed7b568d47a0dc853626797ab6 --- /dev/null +++ b/bsp/x86/drivers/pci.c @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 JasonHu first version + */ + +#include "pci.h" +#include "board.h" + +#include + +// #define RT_PCI_DEBUG + +#ifdef RT_PCI_DEBUG + #define dbgprint rt_kprintf +#else + #define dbgprint(...) +#endif + +static rt_list_t g_pci_device_list_head; + +static void pci_device_bar_init(rt_pci_device_bar_t *bar, rt_uint32_t addr_reg_val, rt_uint32_t len_reg_val) +{ + if (addr_reg_val == 0xffffffff) { + addr_reg_val = 0; + } + /*we judge type by addr register bit 0, if 1, type is io, if 0, type is memory*/ + if (addr_reg_val & 1) { + bar->type = PCI_BAR_TYPE_IO; + bar->base_addr = addr_reg_val & PCI_BASE_ADDR_IO_MASK; + bar->length = ~(len_reg_val & PCI_BASE_ADDR_IO_MASK) + 1; + } else { + bar->type = PCI_BAR_TYPE_MEM; + bar->base_addr = addr_reg_val & PCI_BASE_ADDR_MEM_MASK; + bar->length = ~(len_reg_val & PCI_BASE_ADDR_MEM_MASK) + 1; + } +} + +void rt_pci_device_bar_dump(rt_pci_device_bar_t *bar) +{ + rt_kprintf(" type: %s, ", bar->type == PCI_BAR_TYPE_IO ? "io base address" : "mem base address"); + rt_kprintf(" base address: %x, ", bar->base_addr); + rt_kprintf(" len: %x\n", bar->length); +} + +static void pci_device_init(rt_pci_device_t *device, rt_uint8_t bus, rt_uint8_t dev, rt_uint8_t function, + rt_uint16_t vendor_id, rt_uint16_t device_id, rt_uint32_t class_code, + rt_uint8_t revision_id, rt_uint8_t multi_function) +{ + device->bus = bus; + device->dev = dev; + device->function = function; + + device->vendor_id = vendor_id; + device->device_id = device_id; + device->multi_function = multi_function; + device->class_code = class_code; + device->revision_id = revision_id; + int i; + for (i = 0; i < PCI_MAX_BAR_NR; i++) + { + device->bars[i].type = PCI_BAR_TYPE_INVALID; + } + device->irq_line = -1; +} + +static rt_uint32_t pci_read_config(rt_uint32_t bus, rt_uint32_t device, rt_uint32_t function, rt_uint32_t addr) +{ + rt_uint32_t reg = 0x80000000; + reg |= (bus & 0xFF) << 16; + reg |= (device & 0x1F) << 11; + reg |= (function & 0x7) << 8; + reg |= (addr & 0xFF) & 0xFC; /*bit 0 and 1 always 0*/ + outl(PCI_CONFIG_ADDR, reg); + return inl(PCI_CONFIG_DATA); +} + +static void pci_write_config(rt_uint32_t bus, rt_uint32_t device, rt_uint32_t function, rt_uint32_t addr, rt_uint32_t val) +{ + rt_uint32_t reg = 0x80000000; + reg |= (bus & 0xFF) << 16; + reg |= (device & 0x1F) << 11; + reg |= (function & 0x7) << 8; + reg |= (addr & 0xFF) & 0xFC; /*bit 0 and 1 always 0*/ + outl(PCI_CONFIG_ADDR, reg); + outl(PCI_CONFIG_DATA, val); +} + +static rt_pci_device_t *pci_create_device() +{ + rt_pci_device_t *device = rt_malloc(sizeof(rt_pci_device_t)); + if (device == RT_NULL) + { + return RT_NULL; + } + rt_list_insert_after(&g_pci_device_list_head, &device->list); + return device; +} + +void rt_pci_device_dump(rt_pci_device_t *device) +{ + rt_kprintf("vendor id: 0x%x\n", device->vendor_id); + rt_kprintf("device id: 0x%x\n", device->device_id); + rt_kprintf("class code: 0x%x\n", device->class_code); + rt_kprintf("revision id: 0x%x\n", device->revision_id); + rt_kprintf("multi function: %d\n", device->multi_function); + rt_kprintf("card bus CIS pointer: %x\n", device->card_bus_pointer); + rt_kprintf("subsystem vendor id: %x\n", device->subsystem_vendor_id); + rt_kprintf("subsystem device id: %x\n", device->subsystem_device_id); + rt_kprintf("expansion ROM base address: %x\n", device->expansion_rom_base_addr); + rt_kprintf("capability list pointer: %x\n", device->capability_list); + rt_kprintf("irq line: %d\n", device->irq_line); + rt_kprintf("irq pin: %d\n", device->irq_pin); + rt_kprintf("min Gnt: %d\n", device->min_gnt); + rt_kprintf("max Lat: %d\n", device->max_lat); + int i; + for (i = 0; i < PCI_MAX_BAR_NR; i++) + { + if (device->bars[i].type != PCI_BAR_TYPE_INVALID) + { + rt_kprintf("bar %d:\n", i); + rt_pci_device_bar_dump(&device->bars[i]); + } + } + rt_kprintf("\n"); +} + +static void pci_scan_device(rt_uint8_t bus, rt_uint8_t device, rt_uint8_t function) +{ + rt_uint32_t val = pci_read_config(bus, device, function, PCI_DEVICE_VENDER); + rt_uint32_t vendor_id = val & 0xffff; + rt_uint32_t device_id = val >> 16; + /*if vendor id is 0xffff, it means that this bus , device not exist!*/ + if (vendor_id == 0xffff) + { + return; + } + + rt_pci_device_t *pci_dev = pci_create_device(); + if (pci_dev == RT_NULL) + { + return; + } + + val = pci_read_config(bus, device, function, PCI_BIST_HEADER_TYPE); + rt_uint8_t header_type = ((val >> 16)); + val = pci_read_config(bus, device, function, PCI_STATUS_COMMAND); + + pci_dev->command = val & 0xffff; + pci_dev->status = (val >> 16) & 0xffff; + + val = pci_read_config(bus, device, function, PCI_CLASS_CODE_REVISION_ID); + rt_uint32_t classcode = val >> 8; + rt_uint8_t revision_id = val & 0xff; + + pci_device_init(pci_dev, bus, device, function, vendor_id, device_id, classcode, revision_id, (header_type & 0x80)); + + int bar, reg; + for (bar = 0; bar < PCI_MAX_BAR_NR; bar++) + { + reg = PCI_BASS_ADDRESS0 + (bar*4); + val = pci_read_config(bus, device, function, reg); + /*set 0xffffffff to bass address[0~5], so that if we pci_read_config again, it's addr len*/ + pci_write_config(bus, device, function, reg, 0xffffffff); + + /*pci_read_config bass address[0~5] to get addr len*/ + rt_uint32_t len = pci_read_config(bus, device, function, reg); + /*pci_write_config the io/mem address back to confige space*/ + pci_write_config(bus, device, function, reg, val); + + if (len != 0 && len != 0xffffffff) + { + pci_device_bar_init(&pci_dev->bars[bar], val, len); + } + } + + val = pci_read_config(bus, device, function, PCI_CARD_BUS_POINTER); + pci_dev->card_bus_pointer = val; + + val = pci_read_config(bus, device, function, PCI_SUBSYSTEM_ID); + pci_dev->subsystem_vendor_id = val & 0xffff; + pci_dev->subsystem_device_id = (val >> 16) & 0xffff; + + val = pci_read_config(bus, device, function, PCI_EXPANSION_ROM_BASE_ADDR); + pci_dev->expansion_rom_base_addr = val; + + val = pci_read_config(bus, device, function, PCI_CAPABILITY_LIST); + pci_dev->capability_list = val; + + val = pci_read_config(bus, device, function, PCI_IRQ_PIN_IRQ_LINE); + if ((val & 0xff) > 0 && (val & 0xff) < 32) + { + int irq = val & 0xff; + pci_dev->irq_line = irq; + pci_dev->irq_pin = (val >> 8)& 0xff; + } + pci_dev->min_gnt = (val >> 16) & 0xff; + pci_dev->max_lat = (val >> 24) & 0xff; +} + +static void rt_pci_scan_all_buses() +{ + rt_uint32_t bus; + rt_uint8_t device, function; + for (bus = 0; bus < PCI_MAX_BUS_NR; bus++) + { + for (device = 0; device < PCI_MAX_DEV_NR; device++) + { + for (function = 0; function < PCI_MAX_FUN_NR; function++) + { + pci_scan_device(bus, device, function); + } + } + } +} + +rt_pci_device_t *rt_pci_device_get(rt_uint32_t vendor_id, rt_uint32_t device_id) +{ + rt_pci_device_t* device; + + rt_list_for_each_entry(device, &g_pci_device_list_head, list) + { + if (device->vendor_id == vendor_id && device->device_id == device_id) + { + return device; + } + } + return RT_NULL; +} + +rt_pci_device_t *rt_pci_device_get_by_class_code(rt_uint32_t class, rt_uint32_t sub_class) +{ + rt_pci_device_t* device; + rt_uint32_t class_code = ((class & 0xff) << 16) | ((sub_class & 0xff) << 8); + + rt_list_for_each_entry(device, &g_pci_device_list_head, list) + { + if ((device->class_code & 0xffff00) == class_code) + { + return device; + } + } + return RT_NULL; +} + +void rt_pci_enable_bus_mastering(rt_pci_device_t *device) +{ + rt_uint32_t val = pci_read_config(device->bus, device->dev, device->function, PCI_STATUS_COMMAND); + dbgprint("PCI enable bus mastering: before command: %x\n", val); + val |= 0x04; + pci_write_config(device->bus, device->dev, device->function, PCI_STATUS_COMMAND, val); + val = pci_read_config(device->bus, device->dev, device->function, PCI_STATUS_COMMAND); + dbgprint("PCI enable bus mastering: after command: %x\n", val); +} + +rt_uint32_t rt_pci_device_read(rt_pci_device_t *device, rt_uint32_t reg) +{ + return pci_read_config(device->bus, device->dev, device->function, reg); +} + +void rt_pci_device_write(rt_pci_device_t *device, rt_uint32_t reg, rt_uint32_t value) +{ + pci_write_config(device->bus, device->dev, device->function, reg, value); +} + +rt_uint32_t rt_pci_device_get_io_addr(rt_pci_device_t *device) +{ + int i; + for (i = 0; i < PCI_MAX_BAR_NR; i++) + { + if (device->bars[i].type == PCI_BAR_TYPE_IO) + { + return device->bars[i].base_addr; + } + } + return 0; +} + +rt_uint32_t rt_pci_device_get_mem_addr(rt_pci_device_t *device) +{ + int i; + for (i = 0; i < PCI_MAX_BAR_NR; i++) + { + if (device->bars[i].type == PCI_BAR_TYPE_MEM) + { + return device->bars[i].base_addr; + } + } + return 0; +} + +rt_uint32_t rt_pci_device_get_mem_len(rt_pci_device_t *device) +{ + int i; + for(i = 0; i < PCI_MAX_BAR_NR; i++) + { + if(device->bars[i].type == PCI_BAR_TYPE_MEM) + { + return device->bars[i].length; + } + } + return 0; +} + +rt_uint32_t rt_pci_device_get_irq_line(rt_pci_device_t *device) +{ + return device->irq_line; +} + +static rt_uint32_t pic_get_connected_counts() +{ + rt_uint32_t n = 0; + rt_pci_device_t *device; + rt_list_for_each_entry(device, &g_pci_device_list_head, list) + { + n++; + } + return n; +} + +#ifdef RT_USING_FINSH +static void rt_pci_device_list(rt_pci_device_t *device) +{ + rt_kprintf("device bus: %d, device: %d function: %d\n", device->bus, device->dev, device->function); + rt_kprintf(" vendor id: 0x%x\n", device->vendor_id); + rt_kprintf(" device id: 0x%x\n", device->device_id); + rt_kprintf(" class code: 0x%x\n", device->class_code); + rt_kprintf(" irq line: %d\n", device->irq_line); + int i; + for (i = 0; i < PCI_MAX_BAR_NR; i++) + { + if (device->bars[i].type != PCI_BAR_TYPE_INVALID) + { + rt_kprintf(" bar %d:\n", i); + rt_pci_device_bar_dump(&device->bars[i]); + } + } + rt_kprintf("\n"); +} + +static void list_pci_device() +{ + rt_kprintf("list pci device:\n"); + rt_pci_device_t *device; + rt_list_for_each_entry(device, &g_pci_device_list_head, list) + { + rt_pci_device_list(device); + } +} +#endif /* RT_USING_FINSH */ + +void rt_pci_init(void) +{ + rt_list_init(&g_pci_device_list_head); + rt_pci_scan_all_buses(); + rt_kprintf("PCI device: device found %d.\n", pic_get_connected_counts()); +} + +#ifdef RT_USING_FINSH +#include +MSH_CMD_EXPORT(list_pci_device, list PCI device on computer) +#endif /* RT_USING_FINSH */ diff --git a/bsp/x86/drivers/pci.h b/bsp/x86/drivers/pci.h new file mode 100644 index 0000000000000000000000000000000000000000..a1ec6d28db0d909fe6a94afa1b64b17a10ddd291 --- /dev/null +++ b/bsp/x86/drivers/pci.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 JasonHu first version + */ + +#ifndef __PCI_H__ +#define __PCI_H__ + +#include + +#define PCI_CONFIG_ADDR 0xCF8 /* PCI configuration space address port */ +#define PCI_CONFIG_DATA 0xCFC /* PCI configuration space data port */ + +#define PCI_DEVICE_VENDER 0x00 +#define PCI_STATUS_COMMAND 0x04 +#define PCI_CLASS_CODE_REVISION_ID 0x08 +#define PCI_BIST_HEADER_TYPE 0x0C +#define PCI_BASS_ADDRESS0 0x10 +#define PCI_BASS_ADDRESS1 0x14 +#define PCI_BASS_ADDRESS2 0x18 +#define PCI_BASS_ADDRESS3 0x1C +#define PCI_BASS_ADDRESS4 0x20 +#define PCI_BASS_ADDRESS5 0x24 +#define PCI_CARD_BUS_POINTER 0x28 +#define PCI_SUBSYSTEM_ID 0x2C +#define PCI_EXPANSION_ROM_BASE_ADDR 0x30 +#define PCI_CAPABILITY_LIST 0x34 +#define PCI_RESERVED 0x38 +#define PCI_IRQ_PIN_IRQ_LINE 0x3C + +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ +#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ +#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ +#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ + +#define PCI_BASE_ADDR_MEM_MASK (~0x0FUL) +#define PCI_BASE_ADDR_IO_MASK (~0x03UL) + +#define PCI_BAR_TYPE_INVALID 0 +#define PCI_BAR_TYPE_MEM 1 +#define PCI_BAR_TYPE_IO 2 + +#define PCI_MAX_BAR_NR 6 /* Each device has up to 6 address information */ +#define PCI_MAX_BUS_NR 256 /* PCI has a total of 256 buses */ +#define PCI_MAX_DEV_NR 32 /* There are a total of 32 devices on each PCI bus */ +#define PCI_MAX_FUN_NR 8 /* PCI devices have a total of 8 function numbers */ + +#ifndef PCI_ANY_ID +#define PCI_ANY_ID (~0) +#endif + +struct rt_pci_device_id +{ + rt_uint32_t vendor, device; /* vendor and device id or PCI_ANY_ID */ + rt_uint32_t subvendor, subdevice; /* subsystem's id or PCI_ANY_ID */ + rt_uint32_t class_value, class_mask; +}; +typedef struct rt_pci_device_id rt_pci_device_id_t; + +struct rt_pci_device_bar +{ + rt_uint32_t type; /* Type of address bar (IO address/MEM address) */ + rt_uint32_t base_addr; + rt_uint32_t length; /* Length of address */ +}; +typedef struct rt_pci_device_bar rt_pci_device_bar_t; + +struct rt_pci_device +{ + rt_list_t list; /* list for all pci device */ + rt_uint8_t bus; /* bus number */ + rt_uint8_t dev; /* device number */ + rt_uint8_t function; /* Function number */ + + rt_uint16_t vendor_id; /* Configuration space:Vendor ID */ + rt_uint16_t device_id; /* Configuration space:Device ID */ + rt_uint16_t command; /* Configuration space:Command */ + rt_uint16_t status; /* Configuration space:Status */ + + rt_uint32_t class_code; /* Configuration space:Class Code */ + rt_uint8_t revision_id; /* Configuration space:Revision ID */ + rt_uint8_t multi_function; + rt_uint32_t card_bus_pointer; + rt_uint16_t subsystem_vendor_id; + rt_uint16_t subsystem_device_id; + rt_uint32_t expansion_rom_base_addr; + rt_uint32_t capability_list; + + rt_uint8_t irq_line; /*Configuration space:IRQ line*/ + rt_uint8_t irq_pin; /*Configuration space:IRQ pin*/ + rt_uint8_t min_gnt; + rt_uint8_t max_lat; + rt_pci_device_bar_t bars[PCI_MAX_BAR_NR]; +}; +typedef struct rt_pci_device rt_pci_device_t; + +rt_uint32_t rt_pci_device_get_io_addr(rt_pci_device_t *device); +rt_uint32_t rt_pci_device_get_mem_addr(rt_pci_device_t *device); +rt_uint32_t rt_pci_device_get_mem_len(rt_pci_device_t *device); +rt_uint32_t rt_pci_device_get_irq_line(rt_pci_device_t *device); + +void rt_pci_enable_bus_mastering(rt_pci_device_t *device); + +rt_pci_device_t* rt_pci_device_get(rt_uint32_t vendor_id, rt_uint32_t device_id); +rt_pci_device_t* rt_pci_device_get_by_class_code(rt_uint32_t class_value, rt_uint32_t sub_class); + +void rt_pci_device_bar_dump(rt_pci_device_bar_t *bar); +void rt_pci_device_dump(rt_pci_device_t *device); + +rt_uint32_t rt_pci_device_read(rt_pci_device_t *device, rt_uint32_t reg); +void rt_pci_device_write(rt_pci_device_t *device, rt_uint32_t reg, rt_uint32_t value); + +void rt_pci_init(void); + +#endif /* __PCI_H__ */ diff --git a/bsp/x86/drivers/serial.c b/bsp/x86/drivers/serial.c deleted file mode 100644 index 51b7a0d96df1cf13301406dd393c85c8e532dcf6..0000000000000000000000000000000000000000 --- a/bsp/x86/drivers/serial.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-09-15 QiuYi the first version - * 2006-10-10 Bernard use keyboard instead of serial - */ - -#include -#include - -#include - -/** - * @addtogroup QEMU - */ -/*@{*/ - -/** - * This function initializes serial - */ -void rt_serial_init(void) -{ - outb(COM1+3,0x80); /* set DLAB of line control reg */ - outb(COM1,0x0c); /* LS of divisor (48 -> 2400 bps */ - outb(COM1+1,0x00); /* MS of divisor */ - outb(COM1+3,0x03); /* reset DLAB */ - outb(COM1+4,0x0b); /* set DTR,RTS, OUT_2 */ - outb(COM1+1,0x0d); /* enable all intrs but writes */ - inb(COM1); /* read data port to reset things (?) */ -} - -/** - * This function read a character from serial without interrupt enable mode - * - * @return the read char - */ -char rt_serial_getc(void) -{ - - while(!(inb(COM1+COMSTATUS) & COMDATA)); - - return inb(COM1+COMREAD); - -} - -/** - * This function will write a character to serial without interrupt enable mode - * - * @param c the char to write - */ -void rt_serial_putc(const char c) -{ - int val; - - while(1) - { - if ((val = inb(COM1+COMSTATUS)) & THRE) - break; - } - - outb(COM1+COMWRITE, c&0xff); -} - -/*@}*/ diff --git a/bsp/x86/get_grub.sh b/bsp/x86/get_grub.sh new file mode 100644 index 0000000000000000000000000000000000000000..6024ffd282c8169490c9640760b23bec2138730b --- /dev/null +++ b/bsp/x86/get_grub.sh @@ -0,0 +1,6 @@ +# 1. download +git clone https://gitee.com/hzc1998/grub2for-rt-smartx86 +# 2. unzip +unzip grub2for-rt-smartx86/grub-2.04-for-rt-smartx86.zip +# 3. remove hub +rm -rf grub2for-rt-smartx86 \ No newline at end of file diff --git a/bsp/x86/link.lds b/bsp/x86/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..b58d26401586f91fd2259f07334c383f3720c571 --- /dev/null +++ b/bsp/x86/link.lds @@ -0,0 +1,106 @@ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) +SECTIONS +{ + . = 0x00100000; + + . = ALIGN(4); + __text_start = .; + .text : + { + _stext = .; + *(.init) + *(.text) + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + _etext = .; /* define a global symbols at end of code */ + } =0 + __text_end = .; + + . = ALIGN(4); + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(4); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _end = .; +} diff --git a/bsp/x86/memlayout.md b/bsp/x86/memlayout.md new file mode 100644 index 0000000000000000000000000000000000000000..930e6a6e8f21568fa9f5fc3987d06e1898c999cf --- /dev/null +++ b/bsp/x86/memlayout.md @@ -0,0 +1,52 @@ +# 物理内存分布图 +``` + +---------------------+-------------------------------------------+ + | Address | details | + +---------------------+-------------------------------------------+ + | 0x00~0x400 | int vectors | + +---------------------+-------------------------------------------+ + | 0x400~0x500 | ROM BIOS parameter area | + +---------------------+-------------------------------------------+ + | 0x1000~0x1100 | ards | + +---------------------+-------------------------------------------+ + | 0x9d000~0x9f000 | kernel statck | + +---------------------+-------------------------------------------+ + | 0x9fc00~0xa0000 | extended BIOS data area (EBDA) | + +---------------------+-------------------------------------------+ + | 0xa0000~0xc0000 | display adapter reserved | + +---------------------+-------------------------------------------+ + | 0xc0000~0xe0000 | Reserved for ROM expansion | + +---------------------+-------------------------------------------+ + | 0xe0000~0xf0000 | Expansion of system ROM | + +---------------------+-------------------------------------------+ + | 0xf0000~0x100000 | System ROM | + +---------------------+-------------------------------------------+ + | 0x100000~0x3F0000 | kernel | + +---------------------+-------------------------------------------+ + | 0x3F0000~0x3F0800 | GDT | + +---------------------+-------------------------------------------+ + | 0x3F0800~0x3F1000 | IDT | + +-----------------------------------------------------------------+ + | 0x3F1000~0x3F2000 | GRUB MODULE INFO | + +---------------------+-------------------------------------------+ + | 0x3F2000~0x3F3000 | KERNEL PAGE DIR TABLE | + +---------------------+-------------------------------------------+ + | 0x3F3000~0x3F4000 | KERNEL PAGE TABLE | + +---------------------+-------------------------------------------+ + | 0x3F3000~0x800000 | KERNEL PAGE TABLE STATIC(1G) | + +---------------------+-------------------------------------------+ + | 0x800000~0x1000000 | DMA device special addr | + +---------------------+-------------------------------------------+ + | 0x1000000~0xffffffff| avaliable memory | + +---------------------+-------------------------------------------+ +``` +# 虚拟内存分布图 +``` + +-------------------------+---------------------------------------+ + | Address | details | + +-------------------------+---------------------------------------+ + | 0x0~0x3FFFFFFF | kernel space | + +-------------------------+---------------------------------------+ + | 0x40000000~0xFFFFFFFF | user space | + +---------------------+-------------------------------------------+ +``` \ No newline at end of file diff --git a/bsp/x86/root/boot/grub/grub.cfg b/bsp/x86/root/boot/grub/grub.cfg new file mode 100644 index 0000000000000000000000000000000000000000..a45e439ddf2b8c7f6f656042f8b1d0b2ff78bcc5 --- /dev/null +++ b/bsp/x86/root/boot/grub/grub.cfg @@ -0,0 +1,7 @@ +set timeout=0 +set default=0 + +menuentry "boot RT-Thread Smart" { + multiboot2 /rtthread.elf + boot +} diff --git a/bsp/x86/rtconfig.h b/bsp/x86/rtconfig.h index c4cdac1fdca971e331a25795c97a11164d0c2c6a..b132ea0564578430b79b38c0f04328b357fc21a5 100644 --- a/bsp/x86/rtconfig.h +++ b/bsp/x86/rtconfig.h @@ -1,180 +1,275 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 8 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 1000 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -#define RT_DEBUG -#define RT_DEBUG_COLOR -#define RT_DEBUG_MODULE 0 +/* RT-Thread Kernel */ +#define RT_NAME_MAX 20 +#define RT_USING_SMART +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 16384 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 16384 +#define RT_DEBUG -/* Using Software Timer */ -/* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +/* Inter-Thread communication */ -/* SECTION: IPC */ -/* Using Semaphore*/ #define RT_USING_SEMAPHORE - -/* Using Mutex */ #define RT_USING_MUTEX - -/* Using Event */ #define RT_USING_EVENT - -/* Using MailBox */ #define RT_USING_MAILBOX - -/* Using Message Queue */ #define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -#define RT_USING_MEMPOOL +/* Memory Management */ -/* Using Dynamic Heap Management */ +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM #define RT_USING_HEAP -/* Using Small MM */ -#define RT_USING_SMALL_MEM +/* Kernel Device Object */ -/* SECTION: Device System */ -/* Using Device System */ #define RT_USING_DEVICE - -/* SECTION: Console options */ #define RT_USING_CONSOLE -/* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50000 +#define RT_USING_CACHE +#define ARCH_MM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0x00000000 +#define PV_OFFSET 0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 -#define IDLE_THREAD_STACK_SIZE 1024 /* idle stack 1K */ +/* C++ features */ + + +/* Command shell */ -/* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH +#define RT_USING_MSH #define FINSH_USING_MSH -#define FINSH_USING_MSH_ONLY -/* Using symbol table */ +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 3 +#define DFS_FILESYSTEM_TYPES_MAX 3 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT -// #define RT_USING_LIBC -// #define RT_USING_PTHREADS - -/* SECTION: device filesystem */ - #define RT_USING_DFS +/* elm-chan's FatFs, Generic FAT Filesystem Module */ -#define RT_USING_DFS_ELMFAT +#define RT_DFS_ELM_CODE_PAGE 437 #define RT_DFS_ELM_WORD_ACCESS -/* Reentrancy (thread safe) of the FatFs module. */ +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_DFS_ELM_REENTRANT -/* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 -/* Maximum sector size to be handled. */ -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 - -/* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 - #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_TTY + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_MUSL +#define RT_USING_POSIX +#define RT_USING_POSIX_CLOCKTIME + +/* Network */ + +/* Socket abstraction layer */ + +#define RT_USING_SAL + +/* protocol stack implement */ -/* SECTION: lwip, a lighwight TCP/IP protocol stack */ -//#define RT_USING_LWIP -/* Enable ICMP protocol*/ +#define SAL_USING_LWIP +#define SAL_USING_POSIX + +/* Network interface device */ + +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_USING_IPV6 +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 1 +#define NETDEV_IPV6_SCOPES + +/* light weight TCP/IP stack */ + +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_IPV6 +#define RT_LWIP_MEM_ALIGNMENT 4 +#define RT_LWIP_IGMP #define RT_LWIP_ICMP -/* Enable UDP protocol*/ +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP -/* Enable TCP protocol*/ #define RT_LWIP_TCP -/* Enable DNS */ -#define RT_LWIP_DNS +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8192 +#define RT_LWIP_TCP_WND 8192 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 8192 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 8192 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define BOARD_x86 +#define BSP_USING_DIRECT_UART +#define BSP_DRV_UART +#define RT_USING_UART0 +#define BSP_DRV_AHCI -/* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 - -/* Using DHCP */ -/* #define RT_LWIP_DHCP */ - -/* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 - -/* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 - -/* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 - -/* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 - -/* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 - -/* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 -/* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 - -/* SECTION: RT-Thread/GUI */ -/* #define RT_USING_RTGUI */ - -/* name length of RTGUI object */ -#define RTGUI_NAME_MAX 12 -/* support 16 weight font */ -#define RTGUI_USING_FONT16 -/* support Chinese font */ -#define RTGUI_USING_FONTHZ -/* use DFS as file interface */ -#define RTGUI_USING_DFS_FILERW -/* use font file as Chinese font */ -#define RTGUI_USING_HZ_FILE -/* use Chinese bitmap font */ -#define RTGUI_USING_HZ_BMP -/* use small size in RTGUI */ -#define RTGUI_USING_SMALL_SIZE -/* use mouse cursor */ -/* #define RTGUI_USING_MOUSE_CURSOR */ -/* default font size in RTGUI */ -#define RTGUI_DEFAULT_FONT_SIZE 16 - -/* image support */ -/* #define RTGUI_IMAGE_XPM */ -/* #define RTGUI_IMAGE_BMP */ - -// #define RT_USING_MODULE #endif diff --git a/bsp/x86/rtconfig.py b/bsp/x86/rtconfig.py index b833f4de49f8625cb4e1d5918d05704e52ac49f8..a4b6dc98851de369dac1797451d94712383d58db 100644 --- a/bsp/x86/rtconfig.py +++ b/bsp/x86/rtconfig.py @@ -1,10 +1,12 @@ import os # toolchains options -ARCH='ia32' -CPU='' +ARCH='x86' +CPU='i386' CROSS_TOOL='gcc' +RTT_ROOT = os.getenv('RTT_ROOT') or os.path.join(os.getcwd(), '..', '..') + if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') @@ -13,7 +15,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_IA32_ELF/bin' + EXEC_PATH = '/home/jasonhu/Desktop/rtthread-smart/tools/gnu_gcc/i386-linux-musleabi_for_x86_64-pc-linux-gnu/bin' elif CROSS_TOOL == 'keil': print('================ERROR============================') print('Not support keil yet!') @@ -29,23 +31,37 @@ if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') BUILD = 'debug' +LIBC_MODE = 'release' # 'debug' or 'release', if debug, use libc in components, or not use libc with toolchain if PLATFORM == 'gcc': # toolchains - PREFIX = '' - CC = PREFIX + 'gcc -m32 -fno-builtin -fno-stack-protector -nostdinc' - AS = PREFIX + 'gcc -m32' + PREFIX = 'i386-unknown-linux-musl-' + + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' AR = PREFIX + 'ar' - LINK = PREFIX + 'ld -melf_i386' + LINK = PREFIX + 'gcc' TARGET_EXT = 'elf' SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' DEVICE = '' - CFLAGS = DEVICE + ' -Wall' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Map rtthread-ia32.map -T x86_ram.lds -nostdlib' + + if LIBC_MODE == 'debug': + EXT_CFLAGS = ' -nostdinc -nostdlib -fno-builtin -fno-stack-protector' + else: + EXT_CFLAGS = '' + + CFLAGS = DEVICE + ' -Wall' + EXT_CFLAGS + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -I.' + + if LIBC_MODE == 'debug': + EXT_LFLAGS = ' -nostdlib' + else: + EXT_LFLAGS = '' + + LFLAGS = DEVICE + ' -static -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref -n -T link.lds' + EXT_LFLAGS CPATH = '' LPATH = '' @@ -55,5 +71,5 @@ if PLATFORM == 'gcc': AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' \ No newline at end of file diff --git a/bsp/x86/run.sh b/bsp/x86/run.sh new file mode 100644 index 0000000000000000000000000000000000000000..9086c35333babbe894283d88d69d0a80f3a59665 --- /dev/null +++ b/bsp/x86/run.sh @@ -0,0 +1,4 @@ +cp rtthread.elf root +grub-mkrescue -o bootable.iso root + +qemu-system-i386 -cdrom bootable.iso -boot d -nographic -net nic,model=pcnet -net user diff --git a/bsp/x86/src/extract.sh b/bsp/x86/src/extract.sh deleted file mode 100755 index 89f8baef7a10543839633101b7229115e707e2ea..0000000000000000000000000000000000000000 --- a/bsp/x86/src/extract.sh +++ /dev/null @@ -1,28 +0,0 @@ -#! /bin/sh - - -imap=$1 -iout=$2 - -echo "!!! extract symbol from $imap to $iout !!!" - -symlist="rt_kprintf \ -rt_kputs \ -rt_vsprintf \ -rt_sprintf \ -rt_snprintf \ -rt_thread_create \ -" - -echo "#ifndef RT_THREAD_SYM_H_H" > $iout -echo "#define RT_THREAD_SYM_H_H" >> $iout - -for sym in $symlist -do -dlim=`echo $sym | cut -b 1` -addr=`cat $imap | grep $sym | head -n 1 | cut -d $dlim -f 1` - -echo "#define __abs_$sym $addr" >> $iout -done - -echo "#endif /* RT_THREAD_SYM_H_H */" >> $iout diff --git a/bsp/x86/src/hello.c b/bsp/x86/src/hello.c deleted file mode 100644 index a075f18ef1c829e1ae6ae671843040579eca6d5f..0000000000000000000000000000000000000000 --- a/bsp/x86/src/hello.c +++ /dev/null @@ -1,36 +0,0 @@ - -#include -const char* g_str = "Hello World!"; - -static int a = 1234; -int b = 5678; - -extern void rt_kprintf(const char* fmt,...); - -int add(int a, int b) -{ - return a+b; -} - -int main(int argc, char* argv[]) -{ - int i; - char str[32] = "Hello World\n"; - - for(i=0; i - -typedef unsigned int size_t; - -typedef int (*sprintf_fcn_t)(char *buf ,const char *format, ...); -typedef int (*snprintf_fcn_t)(char *buf, size_t size, const char *format, ...); -typedef void (*puts_fcn_t)(const char *str); -typedef void (*printf_fcn_t)(const char *fmt, ...); - -#define printf ((printf_fcn_t)__abs_rt_kprintf) -#define puts ((printf_fcn_t)__abs_rt_kputs) -#define sprintf ((printf_fcn_t)__abs_rt_sprintf) -#define snprintf ((printf_fcn_t)__abs_rt_snprintf) - -#endif diff --git a/bsp/x86/x86_ram.lds b/bsp/x86/x86_ram.lds deleted file mode 100644 index afac69f04b8b5964202af8c783c56af65be65d19..0000000000000000000000000000000000000000 --- a/bsp/x86/x86_ram.lds +++ /dev/null @@ -1,55 +0,0 @@ -OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) -ENTRY(_start) -SECTIONS -{ - . = 0x00100000; - - . = ALIGN(4); - .text : - { - *(.init) - *(.text) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)); - __rtmsymtab_end = .; - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - __bss_end = .; - - /* stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } - - _end = .; -} diff --git a/bsp/zynq7000/rtconfig.h b/bsp/zynq7000/rtconfig.h index b09fc1ab26fdcf6dd91095c93016b218621391eb..b5660064105eaef51ba187fbed26d5016e4af5f0 100644 --- a/bsp/zynq7000/rtconfig.h +++ b/bsp/zynq7000/rtconfig.h @@ -67,6 +67,8 @@ // #define RT_USING_SLAB //
+#define RT_USING_CACHE + //
#define RT_USING_DEVICE // diff --git a/components/dfs/Kconfig b/components/dfs/Kconfig index c93fd02e66f87b468504bb9363f635d7c54dc8e2..657c8a25c42b24be2efe7588ada2debbf7860966 100644 --- a/components/dfs/Kconfig +++ b/components/dfs/Kconfig @@ -108,9 +108,14 @@ if RT_USING_DFS default y config RT_USING_DFS_ROMFS - bool "Enable ReadOnly file system on flash" + bool "Enable readonly file system on flash" default n + config RT_USING_DFS_CROMFS + bool "Enable readonly compressed file system on flash" + default n + select PKG_USING_ZLIB + config RT_USING_DFS_RAMFS bool "Enable RAM file system" select RT_USING_MEMHEAP diff --git a/components/libc/termios/SConscript b/components/dfs/filesystems/cromfs/SConscript similarity index 42% rename from components/libc/termios/SConscript rename to components/dfs/filesystems/cromfs/SConscript index 381eb5ad8bba4e86e55f5800e6ed258dadaf9348..1bc4d444cebfdc49a9f40f58fb3591b2364011d4 100644 --- a/components/libc/termios/SConscript +++ b/components/dfs/filesystems/cromfs/SConscript @@ -3,11 +3,9 @@ from building import * cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') +src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('libc', src, - depend = ['RT_USING_LIBC', 'RT_USING_POSIX', 'RT_USING_POSIX_TERMIOS'], - CPPPATH = CPPPATH) +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS','RT_USING_DFS_CROMFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/cromfs/dfs_cromfs.c b/components/dfs/filesystems/cromfs/dfs_cromfs.c new file mode 100644 index 0000000000000000000000000000000000000000..68ae2384a4c393b1d38382671c0d2346f3883baa --- /dev/null +++ b/components/dfs/filesystems/cromfs/dfs_cromfs.c @@ -0,0 +1,1170 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/08/21 ShaoJinchun first version + */ + +#include +#include +#include +#include + +#include "dfs_cromfs.h" + +#include + +#include "zlib.h" + +/**********************************/ + +#define CROMFS_PATITION_HEAD_SIZE 256 +#define CROMFS_DIRENT_CACHE_SIZE 8 + +#define CROMFS_MAGIC "CROMFSMG" + +#define CROMFS_CT_ASSERT(name, x) \ + struct assert_##name {char ary[2 * (x) - 1];} + +#define CROMFS_POS_ROOT (0x0UL) +#define CROMFS_POS_ERROR (0x1UL) + +typedef struct +{ + uint8_t magic[8]; /* CROMFS_MAGIC */ + uint32_t version; + uint32_t partition_attr; /* expand, now reserved 0 */ + uint32_t partition_size; /* with partition head */ + uint32_t root_dir_pos; /* root dir pos */ + uint32_t root_dir_size; +} partition_head_data; + +typedef struct +{ + partition_head_data head; + uint8_t padding[CROMFS_PATITION_HEAD_SIZE - sizeof(partition_head_data)]; +} partition_head; + +#define CROMFS_DIRENT_ATTR_DIR 0x1UL +#define CROMFS_DIRENT_ATTR_FILE 0x0UL + +typedef struct +{ + uint16_t attr; /* dir or file add other */ + uint16_t name_size; /* name real size */ + uint32_t file_size; /* file data size */ + uint32_t file_origin_size; /* file size before compress */ + uint32_t parition_pos; /* offset of data */ + uint8_t name[0]; /* name data */ +} cromfs_dirent; + +#define CROMFS_ALIGN_SIZE_BIT 4 +#define CROMFS_ALIGN_SIZE (1UL << CROMFS_ALIGN_SIZE_BIT) /* must be same as sizeof cromfs_dirent */ +#define CROMFS_ALIGN_SIZE_MASK (CROMFS_ALIGN_SIZE - 1) + +CROMFS_CT_ASSERT(align_size, CROMFS_ALIGN_SIZE == sizeof(cromfs_dirent)); + +typedef union +{ + cromfs_dirent dirent; + uint8_t name[CROMFS_ALIGN_SIZE]; +} cromfs_dirent_item; + +/**********************************/ + +typedef struct +{ + rt_list_t list; + uint32_t partition_pos; + uint32_t size; + uint8_t *buff; +} cromfs_dirent_cache; + +typedef struct st_cromfs_info +{ + rt_device_t device; + uint32_t partition_size; + uint32_t bytes_per_sector; + uint32_t (*read_bytes)(struct st_cromfs_info *ci, uint32_t pos, void *buf, uint32_t size); + partition_head_data part_info; + struct rt_mutex lock; + struct cromfs_avl_struct *cromfs_avl_root; + rt_list_t cromfs_dirent_cache_head; + int cromfs_dirent_cache_nr; +} cromfs_info; + +typedef struct +{ + uint32_t ref; + uint32_t partition_pos; + cromfs_info *ci; + uint32_t size; + uint8_t *buff; + uint32_t partition_size; + int data_valid; +} file_info; + +/**********************************/ + +#define avl_key_t uint32_t +#define AVL_EMPTY (struct cromfs_avl_struct *)0 +#define avl_maxheight 32 +#define heightof(tree) ((tree) == AVL_EMPTY ? 0 : (tree)->avl_height) + +struct cromfs_avl_struct +{ + struct cromfs_avl_struct *avl_left; + struct cromfs_avl_struct *avl_right; + int avl_height; + avl_key_t avl_key; + file_info *fi; +}; + +static void cromfs_avl_remove(struct cromfs_avl_struct *node_to_delete, struct cromfs_avl_struct **ptree); +static void cromfs_avl_insert(struct cromfs_avl_struct *new_node, struct cromfs_avl_struct **ptree); +static struct cromfs_avl_struct* cromfs_avl_find(avl_key_t key, struct cromfs_avl_struct *ptree); + +static void cromfs_avl_rebalance(struct cromfs_avl_struct ***nodeplaces_ptr, int count) +{ + for (;count > 0; count--) + { + struct cromfs_avl_struct **nodeplace = *--nodeplaces_ptr; + struct cromfs_avl_struct *node = *nodeplace; + struct cromfs_avl_struct *nodeleft = node->avl_left; + struct cromfs_avl_struct *noderight = node->avl_right; + int heightleft = heightof(nodeleft); + int heightright = heightof(noderight); + if (heightright + 1 < heightleft) + { + struct cromfs_avl_struct * nodeleftleft = nodeleft->avl_left; + struct cromfs_avl_struct * nodeleftright = nodeleft->avl_right; + int heightleftright = heightof(nodeleftright); + if (heightof(nodeleftleft) >= heightleftright) + { + node->avl_left = nodeleftright; + nodeleft->avl_right = node; + nodeleft->avl_height = 1 + (node->avl_height = 1 + heightleftright); + *nodeplace = nodeleft; + } + else + { + nodeleft->avl_right = nodeleftright->avl_left; + node->avl_left = nodeleftright->avl_right; + nodeleftright->avl_left = nodeleft; + nodeleftright->avl_right = node; + nodeleft->avl_height = node->avl_height = heightleftright; + nodeleftright->avl_height = heightleft; + *nodeplace = nodeleftright; + } + } + else if (heightleft + 1 < heightright) + { + struct cromfs_avl_struct *noderightright = noderight->avl_right; + struct cromfs_avl_struct *noderightleft = noderight->avl_left; + int heightrightleft = heightof(noderightleft); + if (heightof(noderightright) >= heightrightleft) + { + node->avl_right = noderightleft; + noderight->avl_left = node; + noderight->avl_height = 1 + (node->avl_height = 1 + heightrightleft); + *nodeplace = noderight; + } + else + { + noderight->avl_left = noderightleft->avl_right; + node->avl_right = noderightleft->avl_left; + noderightleft->avl_right = noderight; + noderightleft->avl_left = node; + noderight->avl_height = node->avl_height = heightrightleft; + noderightleft->avl_height = heightright; + *nodeplace = noderightleft; + } + } + else { + int height = (heightleftavl_height) + { + break; + } + node->avl_height = height; + } + } +} + +static void cromfs_avl_remove(struct cromfs_avl_struct *node_to_delete, struct cromfs_avl_struct **ptree) +{ + avl_key_t key = node_to_delete->avl_key; + struct cromfs_avl_struct **nodeplace = ptree; + struct cromfs_avl_struct **stack[avl_maxheight]; + uint32_t stack_count = 0; + struct cromfs_avl_struct ***stack_ptr = &stack[0]; /* = &stack[stackcount] */ + struct cromfs_avl_struct **nodeplace_to_delete; + for (;;) + { + struct cromfs_avl_struct *node = *nodeplace; + if (node == AVL_EMPTY) + { + return; + } + *stack_ptr++ = nodeplace; + stack_count++; + if (key == node->avl_key) + { + break; + } + if (key < node->avl_key) + { + nodeplace = &node->avl_left; + } + else + { + nodeplace = &node->avl_right; + } + } + nodeplace_to_delete = nodeplace; + if (node_to_delete->avl_left == AVL_EMPTY) + { + *nodeplace_to_delete = node_to_delete->avl_right; + stack_ptr--; + stack_count--; + } + else + { + struct cromfs_avl_struct *** stack_ptr_to_delete = stack_ptr; + struct cromfs_avl_struct ** nodeplace = &node_to_delete->avl_left; + struct cromfs_avl_struct * node; + for (;;) + { + node = *nodeplace; + if (node->avl_right == AVL_EMPTY) + { + break; + } + *stack_ptr++ = nodeplace; + stack_count++; + nodeplace = &node->avl_right; + } + *nodeplace = node->avl_left; + node->avl_left = node_to_delete->avl_left; + node->avl_right = node_to_delete->avl_right; + node->avl_height = node_to_delete->avl_height; + *nodeplace_to_delete = node; + *stack_ptr_to_delete = &node->avl_left; + } + cromfs_avl_rebalance(stack_ptr,stack_count); +} + +static void cromfs_avl_insert(struct cromfs_avl_struct *new_node, struct cromfs_avl_struct **ptree) +{ + avl_key_t key = new_node->avl_key; + struct cromfs_avl_struct **nodeplace = ptree; + struct cromfs_avl_struct **stack[avl_maxheight]; + int stack_count = 0; + struct cromfs_avl_struct ***stack_ptr = &stack[0]; /* = &stack[stackcount] */ + for (;;) + { + struct cromfs_avl_struct * node = *nodeplace; + if (node == AVL_EMPTY) + { + break; + } + *stack_ptr++ = nodeplace; + stack_count++; + if (key < node->avl_key) + { + nodeplace = &node->avl_left; + } + else + { + nodeplace = &node->avl_right; + } + } + new_node->avl_left = AVL_EMPTY; + new_node->avl_right = AVL_EMPTY; + new_node->avl_height = 1; + *nodeplace = new_node; + cromfs_avl_rebalance(stack_ptr,stack_count); +} + +static struct cromfs_avl_struct* cromfs_avl_find(avl_key_t key, struct cromfs_avl_struct* ptree) +{ + for (;;) + { + if (ptree == AVL_EMPTY) + { + return (struct cromfs_avl_struct *)0; + } + if (key == ptree->avl_key) + { + break; + } + if (key < ptree->avl_key) + { + ptree = ptree->avl_left; + } + else + { + ptree = ptree->avl_right; + } + } + return ptree; +} + +/**********************************/ + +static uint32_t cromfs_read_bytes(cromfs_info *ci, uint32_t pos, void *buf, uint32_t size) +{ + if (pos >= ci->partition_size || pos + size > ci->partition_size) + { + return 0; + } + return ci->read_bytes(ci, pos, buf, size); +} + +static uint32_t cromfs_noblk_read_bytes(cromfs_info *ci, uint32_t pos, void *buf, uint32_t size) +{ + uint32_t ret = 0; + + ret = rt_device_read(ci->device, pos, buf, size); + if (ret != size) + { + return 0; + } + else + { + return ret; + } +} + +static uint32_t cromfs_blk_read_bytes(cromfs_info *ci, uint32_t pos, void *buf, uint32_t size) +{ + uint32_t ret = 0; + uint32_t size_bak = size; + uint32_t start_blk = 0; + uint32_t end_blk = 0; + uint32_t off_s = 0; + uint32_t sector_nr = 0; + uint8_t *block_buff = NULL; + uint32_t ret_len = 0; + + if (!size || !buf) + { + return 0; + } + block_buff = (uint8_t *)malloc(2 * ci->bytes_per_sector); + if (!block_buff) + { + return 0; + } + start_blk = pos / ci->bytes_per_sector; + off_s = pos % ci->bytes_per_sector; + end_blk = (pos + size - 1) / ci->bytes_per_sector; + + sector_nr = end_blk - start_blk; + if (sector_nr < 2) + { + ret_len = rt_device_read(ci->device, start_blk, block_buff, sector_nr + 1); + if (ret_len != sector_nr + 1) + { + goto end; + } + memcpy(buf, block_buff + off_s, size); + } + else + { + ret_len = rt_device_read(ci->device, start_blk, block_buff, 1); + if (ret_len != 1) + { + goto end; + } + memcpy(buf, block_buff + off_s, ci->bytes_per_sector - off_s); + off_s = (ci->bytes_per_sector - off_s); + size -= off_s; + sector_nr--; + start_blk++; + if (sector_nr) + { + ret_len = rt_device_read(ci->device, start_blk, (char*)buf + off_s, sector_nr); + if (ret_len != sector_nr) + { + goto end; + } + start_blk += sector_nr; + off_s += (sector_nr * ci->bytes_per_sector); + size -= (sector_nr * ci->bytes_per_sector); + } + ret_len = rt_device_read(ci->device, start_blk, block_buff, 1); + if (ret_len != 1) + { + goto end; + } + memcpy((char*)buf + off_s, block_buff, size); + } + ret = size_bak; +end: + free(block_buff); + return ret; +} + +/**********************************/ + +static uint8_t *cromfs_dirent_cache_get(cromfs_info *ci, uint32_t pos, uint32_t size) +{ + rt_list_t *l = NULL; + cromfs_dirent_cache *dir = NULL; + uint32_t len = 0; + + /* find */ + for (l = ci->cromfs_dirent_cache_head.next; l != &ci->cromfs_dirent_cache_head; l = l->next) + { + dir = (cromfs_dirent_cache *)l; + if (dir->partition_pos == pos) + { + RT_ASSERT(dir->size == size); + rt_list_remove(l); + rt_list_insert_after(&ci->cromfs_dirent_cache_head, l); + return dir->buff; + } + } + /* not found */ + if (ci->cromfs_dirent_cache_nr >= CROMFS_DIRENT_CACHE_SIZE) + { + l = ci->cromfs_dirent_cache_head.prev; + dir = (cromfs_dirent_cache *)l; + rt_list_remove(l); + free(dir->buff); + free(dir); + ci->cromfs_dirent_cache_nr--; + } + dir = (cromfs_dirent_cache *)malloc(sizeof *dir); + if (!dir) + { + return NULL; + } + dir->buff = (uint8_t *)malloc(size); + if (!dir->buff) + { + free(dir); + return NULL; + } + len = cromfs_read_bytes(ci, pos, dir->buff, size); + if (len != size) + { + free(dir->buff); + free(dir); + return NULL; + } + rt_list_insert_after(&ci->cromfs_dirent_cache_head, (rt_list_t *)dir); + ci->cromfs_dirent_cache_nr++; + dir->partition_pos = pos; + dir->size = size; + return dir->buff; +} + +static void cromfs_dirent_cache_destroy(cromfs_info *ci) +{ + rt_list_t *l = NULL; + cromfs_dirent_cache *dir = NULL; + + while ((l = ci->cromfs_dirent_cache_head.next) != &ci->cromfs_dirent_cache_head) + { + rt_list_remove(l); + dir = (cromfs_dirent_cache *)l; + free(dir->buff); + free(dir); + ci->cromfs_dirent_cache_nr--; + } +} + +/**********************************/ + +static int dfs_cromfs_mount(struct dfs_filesystem *fs, unsigned long rwflag, const void *data) +{ + struct rt_device_blk_geometry geometry; + uint32_t len = 0; + cromfs_info *ci = NULL; + + ci = (cromfs_info *)malloc(sizeof *ci); + if (!ci) + { + return -ENOMEM; + } + + memset(ci, 0, sizeof *ci); + ci->device = fs->dev_id; + ci->partition_size = UINT32_MAX; + if (ci->device->type == RT_Device_Class_Block) + { + rt_device_control(ci->device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry); + ci->bytes_per_sector = geometry.bytes_per_sector; + ci->read_bytes = cromfs_blk_read_bytes; + } + else + { + ci->read_bytes = cromfs_noblk_read_bytes; + } + + len = cromfs_read_bytes(ci, 0, &ci->part_info, sizeof ci->part_info); + if (len != sizeof ci->part_info || + memcmp(ci->part_info.magic, CROMFS_MAGIC, sizeof ci->part_info.magic) != 0) + { + free(ci); + return -RT_ERROR; + } + ci->partition_size = ci->part_info.partition_size; + fs->data = ci; + + rt_mutex_init(&ci->lock, "crom", RT_IPC_FLAG_FIFO); + ci->cromfs_avl_root = NULL; + + rt_list_init(&ci->cromfs_dirent_cache_head); + ci->cromfs_dirent_cache_nr = 0; + + return RT_EOK; +} + +static int dfs_cromfs_unmount(struct dfs_filesystem *fs) +{ + rt_err_t result = RT_EOK; + cromfs_info *ci = NULL; + + ci = (cromfs_info *)fs->data; + + result = rt_mutex_take(&ci->lock, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + return -RT_ERROR; + } + + cromfs_dirent_cache_destroy(ci); + + while (ci->cromfs_avl_root) + { + struct cromfs_avl_struct *node; + file_info *fi = NULL; + + node = ci->cromfs_avl_root; + fi = node->fi; + cromfs_avl_remove(node, &ci->cromfs_avl_root); + free(node); + if (fi->buff) + { + free(fi->buff); + } + free(fi); + } + + rt_mutex_detach(&ci->lock); + + free(ci); + + return RT_EOK; +} + +static int dfs_cromfs_ioctl(struct dfs_fd *file, int cmd, void *args) +{ + return -EIO; +} + +static uint32_t cromfs_lookup(cromfs_info *ci, const char *path, int* is_dir, uint32_t *size, uint32_t *osize) +{ + uint32_t cur_size = 0, cur_pos = 0, cur_osize = 0; + const char *subpath = NULL, *subpath_end = NULL; + void *di_mem = NULL; + int isdir = 0; + + if (path[0] == '\0') + { + return CROMFS_POS_ERROR; + } + + cur_size = ci->part_info.root_dir_size; + cur_osize = 0; + cur_pos = ci->part_info.root_dir_pos; + isdir = 1; + + subpath_end = path; + while (1) + { + cromfs_dirent_item *di_iter = NULL; + int found = 0; + + /* skip /// */ + while (*subpath_end && *subpath_end == '/') + { + subpath_end++; + } + subpath = subpath_end; + while ((*subpath_end != '/') && *subpath_end) + { + subpath_end++; + } + if (*subpath == '\0') + { + break; + } + + /* if not dir or empty dir, error */ + if (!isdir || !cur_size) + { + return CROMFS_POS_ERROR; + } + + /* find subpath */ + di_mem = cromfs_dirent_cache_get(ci, cur_pos, cur_size); + if (!di_mem) + { + return CROMFS_POS_ERROR; + } + + found = 0; + di_iter = (cromfs_dirent_item *)di_mem; + while (1) + { + uint32_t name_len = subpath_end - subpath; + uint32_t name_block = 0; + + if (di_iter->dirent.name_size == name_len) + { + if (memcmp(di_iter->dirent.name, subpath, name_len) == 0) + { + found = 1; + cur_size = di_iter->dirent.file_size; + cur_osize = di_iter->dirent.file_origin_size; + cur_pos = di_iter->dirent.parition_pos; + if (di_iter->dirent.attr == CROMFS_DIRENT_ATTR_DIR) + { + isdir = 1; + } + else + { + isdir = 0; + } + break; + } + } + name_block = (di_iter->dirent.name_size + CROMFS_ALIGN_SIZE_MASK) >> CROMFS_ALIGN_SIZE_BIT; + di_iter += (1 + name_block); + if ((uint32_t)di_iter - (uint32_t)di_mem >= cur_size) + { + break; + } + } + if (!found) + { + return CROMFS_POS_ERROR; + } + } + *size = cur_size; + *osize = cur_osize; + *is_dir = isdir; + return cur_pos; +} + +static uint32_t dfs_cromfs_lookup(cromfs_info *ci, const char *path, int* is_dir, uint32_t *size, uint32_t *osize) +{ + rt_err_t result = RT_EOK; + uint32_t ret = 0; + + result = rt_mutex_take(&ci->lock, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + return CROMFS_POS_ERROR; + } + ret = cromfs_lookup(ci, path, is_dir, size, osize); + rt_mutex_release(&ci->lock); + return ret; +} + +static int fill_file_data(file_info *fi) +{ + int ret = -1; + cromfs_info *ci = NULL; + void *compressed_file_buff = NULL; + uint32_t size = 0, osize = 0; + + if (!fi->data_valid) + { + RT_ASSERT(fi->buff != NULL); + + ci = fi->ci; + osize = fi->size; + size = fi->partition_size; + + compressed_file_buff = (void *)malloc(size); + if (!compressed_file_buff) + { + goto end; + } + if (cromfs_read_bytes(ci, fi->partition_pos, compressed_file_buff, size) != size) + { + goto end; + } + if (uncompress((uint8_t *)fi->buff, (uLongf *)&osize, (uint8_t *)compressed_file_buff, size) != Z_OK) + { + goto end; + } + fi->data_valid = 1; + } + ret = 0; +end: + if (compressed_file_buff) + { + free(compressed_file_buff); + } + return ret; +} + +static int dfs_cromfs_read(struct dfs_fd *file, void *buf, size_t count) +{ + rt_err_t result = RT_EOK; + struct dfs_filesystem *fs = NULL; + file_info *fi = NULL; + cromfs_info *ci = NULL; + uint32_t length = 0; + + fs = (struct dfs_filesystem *)file->fnode->fs; + ci = (cromfs_info *)fs->data; + fi = (file_info *)file->fnode->data; + + if (count < file->fnode->size - file->pos) + { + length = count; + } + else + { + length = file->fnode->size - file->pos; + } + + if (length > 0) + { + RT_ASSERT(fi->size != 0); + + if (fi->buff) + { + int fill_ret = 0; + + result = rt_mutex_take(&ci->lock, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + return 0; + } + fill_ret = fill_file_data(fi); + rt_mutex_release(&ci->lock); + if (fill_ret < 0) + { + return 0; + } + + memcpy(buf, fi->buff + file->pos, length); + } + else + { + void *di_mem = NULL; + + result = rt_mutex_take(&ci->lock, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + return 0; + } + di_mem = cromfs_dirent_cache_get(ci, fi->partition_pos, fi->size); + if (di_mem) + { + memcpy(buf, (char*)di_mem + file->pos, length); + } + rt_mutex_release(&ci->lock); + if (!di_mem) + { + return 0; + } + } + /* update file current position */ + file->pos += length; + } + + return length; +} + +static int dfs_cromfs_lseek(struct dfs_fd *file, off_t offset) +{ + if (offset <= file->fnode->size) + { + file->pos = offset; + return file->pos; + } + return -EIO; +} + +static file_info *get_file_info(cromfs_info *ci, uint32_t partition_pos, int inc_ref) +{ + struct cromfs_avl_struct* node = cromfs_avl_find(partition_pos, ci->cromfs_avl_root); + + if (node) + { + if (inc_ref) + { + node->fi->ref++; + } + return node->fi; + } + return NULL; +} + +static file_info *inset_file_info(cromfs_info *ci, uint32_t partition_pos, int is_dir, uint32_t size, uint32_t osize) +{ + file_info *fi = NULL; + void *file_buff = NULL; + struct cromfs_avl_struct *node = NULL; + + fi = (file_info *)malloc(sizeof *fi); + if (!fi) + { + goto err; + } + fi->partition_pos = partition_pos; + fi->ci = ci; + if (is_dir) + { + fi->size = size; + } + else + { + fi->size = osize; + fi->partition_size = size; + fi->data_valid = 0; + if (osize) + { + file_buff = (void *)malloc(osize); + if (!file_buff) + { + goto err; + } + } + } + fi->buff = file_buff; + fi->ref = 1; + + node = (struct cromfs_avl_struct *)malloc(sizeof *node); + if (!node) + { + goto err; + } + node->avl_key = partition_pos; + node->fi = fi; + cromfs_avl_insert(node, &ci->cromfs_avl_root); + return fi; +err: + if (file_buff) + { + free(file_buff); + } + if (fi) + { + free(fi); + } + return NULL; +} + +static void deref_file_info(cromfs_info *ci, uint32_t partition_pos) +{ + struct cromfs_avl_struct* node = cromfs_avl_find(partition_pos, ci->cromfs_avl_root); + file_info *fi = NULL; + + if (node) + { + node->fi->ref--; + if (node->fi->ref == 0) + { + fi = node->fi; + cromfs_avl_remove(node, &ci->cromfs_avl_root); + free(node); + if (fi->buff) + { + free(fi->buff); + } + free(fi); + } + } +} + +static int dfs_cromfs_close(struct dfs_fd *file) +{ + file_info *fi = NULL; + struct dfs_filesystem *fs = NULL; + cromfs_info *ci = NULL; + rt_err_t result = 0; + + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + return 0; + } + + fi = (file_info *)file->fnode->data; + fs = (struct dfs_filesystem *)file->fnode->fs; + ci = (cromfs_info *)fs->data; + + result = rt_mutex_take(&ci->lock, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + return -RT_ERROR; + } + deref_file_info(ci, fi->partition_pos); + rt_mutex_release(&ci->lock); + file->fnode->data = NULL; + return RT_EOK; +} + +static int dfs_cromfs_open(struct dfs_fd *file) +{ + int ret = 0; + struct dfs_filesystem *fs = NULL; + file_info *fi = NULL; + cromfs_info *ci = NULL; + uint32_t file_pos = 0; + uint32_t size = 0, osize = 0; + int is_dir = 0; + rt_err_t result = RT_EOK; + + if (file->flags & (O_CREAT | O_WRONLY | O_APPEND | O_TRUNC | O_RDWR)) + { + return -EINVAL; + } + + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + if (file->fnode->type == FT_DIRECTORY + && !(file->flags & O_DIRECTORY)) + { + return -ENOENT; + } + file->pos = 0; + return 0; + } + + fs = file->fnode->fs; + ci = (cromfs_info *)fs->data; + + file_pos = dfs_cromfs_lookup(ci, file->fnode->path, &is_dir, &size, &osize); + if (file_pos == CROMFS_POS_ERROR) + { + ret = -ENOENT; + goto end; + } + + /* entry is a directory file type */ + if (is_dir) + { + if (!(file->flags & O_DIRECTORY)) + { + ret = -ENOENT; + goto end; + } + file->fnode->type = FT_DIRECTORY; + } + else + { + /* entry is a file, but open it as a directory */ + if (file->flags & O_DIRECTORY) + { + ret = -ENOENT; + goto end; + } + file->fnode->type = FT_REGULAR; + } + + result = rt_mutex_take(&ci->lock, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + ret = -EINTR; + goto end; + } + + fi = get_file_info(ci, file_pos, 1); + if (!fi) + { + fi = inset_file_info(ci, file_pos, is_dir, size, osize); + } + rt_mutex_release(&ci->lock); + if (!fi) + { + ret = -ENOENT; + goto end; + } + + file->fnode->data = fi; + if (is_dir) + { + file->fnode->size = size; + } + else + { + file->fnode->size = osize; + } + file->pos = 0; + + ret = RT_EOK; +end: + return ret; +} + +static int dfs_cromfs_stat(struct dfs_filesystem *fs, const char *path, struct stat *st) +{ + uint32_t size = 0, osize = 0; + int is_dir = 0; + cromfs_info *ci = NULL; + uint32_t file_pos = 0; + + ci = (cromfs_info *)fs->data; + + file_pos = dfs_cromfs_lookup(ci, path, &is_dir, &size, &osize); + if (file_pos == CROMFS_POS_ERROR) + { + return -ENOENT; + } + + st->st_dev = 0; + st->st_mode = S_IFREG | S_IRUSR | S_IRGRP | S_IROTH | + S_IWUSR | S_IWGRP | S_IWOTH; + + if (is_dir) + { + st->st_mode &= ~S_IFREG; + st->st_mode |= S_IFDIR | S_IXUSR | S_IXGRP | S_IXOTH; + st->st_size = size; + } + else + { + st->st_size = osize; + } + + st->st_mtime = 0; + + return RT_EOK; +} + +static int dfs_cromfs_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t count) +{ + uint32_t index = 0; + uint8_t *name = NULL; + struct dirent *d = NULL; + file_info *fi = NULL; + cromfs_info *ci = NULL; + cromfs_dirent_item *dirent = NULL, *sub_dirent = NULL; + void *di_mem = NULL; + rt_err_t result = RT_EOK; + + fi = (file_info *)file->fnode->data; + ci = fi->ci; + + RT_ASSERT(fi->buff == NULL); + + if (!fi->size) + { + return -EINVAL; + } + + dirent = (cromfs_dirent_item *)malloc(fi->size); + if (!dirent) + { + return -ENOMEM; + } + + result = rt_mutex_take(&ci->lock, RT_WAITING_FOREVER); + if (result != RT_EOK) + { + free(dirent); + return -EINTR; + } + di_mem = cromfs_dirent_cache_get(ci, fi->partition_pos, fi->size); + if (di_mem) + { + memcpy(dirent, di_mem, fi->size); + } + rt_mutex_release(&ci->lock); + if (!di_mem) + { + free(dirent); + return -ENOMEM; + } + + /* make integer count */ + count = (count / sizeof(struct dirent)); + if (count == 0) + { + free(dirent); + return -EINVAL; + } + + for (index = 0; index < count && file->pos < file->fnode->size; index++) + { + uint32_t name_size = 0; + + d = dirp + index; + sub_dirent = &dirent[file->pos >> CROMFS_ALIGN_SIZE_BIT]; + name = sub_dirent->dirent.name; + + /* fill dirent */ + if (sub_dirent->dirent.attr == CROMFS_DIRENT_ATTR_DIR) + { + d->d_type = DT_DIR; + } + else + { + d->d_type = DT_REG; + } + + d->d_namlen = sub_dirent->dirent.name_size; + d->d_reclen = (rt_uint16_t)sizeof(struct dirent); + memcpy(d->d_name, (char *)name, sub_dirent->dirent.name_size); + d->d_name[sub_dirent->dirent.name_size] = '\0'; + + name_size = (sub_dirent->dirent.name_size + CROMFS_ALIGN_SIZE_MASK) & ~CROMFS_ALIGN_SIZE_MASK; + /* move to next position */ + file->pos += (name_size + sizeof *sub_dirent); + } + + free(dirent); + + return index * sizeof(struct dirent); +} + +static const struct dfs_file_ops _crom_fops = +{ + dfs_cromfs_open, + dfs_cromfs_close, + dfs_cromfs_ioctl, + dfs_cromfs_read, + NULL, + NULL, + dfs_cromfs_lseek, + dfs_cromfs_getdents, +}; + +static const struct dfs_filesystem_ops _cromfs = +{ + "crom", + DFS_FS_FLAG_DEFAULT, + &_crom_fops, + + dfs_cromfs_mount, + dfs_cromfs_unmount, + NULL, + NULL, + + NULL, + dfs_cromfs_stat, + NULL, +}; + +int dfs_cromfs_init(void) +{ + /* register crom file system */ + dfs_register(&_cromfs); + return 0; +} +INIT_COMPONENT_EXPORT(dfs_cromfs_init); diff --git a/components/dfs/filesystems/cromfs/dfs_cromfs.h b/components/dfs/filesystems/cromfs/dfs_cromfs.h new file mode 100644 index 0000000000000000000000000000000000000000..97339bc510c014c4d26fd98a6d331305fda7ffc7 --- /dev/null +++ b/components/dfs/filesystems/cromfs/dfs_cromfs.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/08/21 ShaoJinchun firset version + */ + +#ifndef __DFS_CROMFS_H__ +#define __DFS_CROMFS_H__ + +int dfs_cromfs_init(void); + +#endif /*__DFS_CROMFS_H__*/ diff --git a/components/dfs/filesystems/devfs/devfs.c b/components/dfs/filesystems/devfs/devfs.c index 7637074dbba40e8ac94c74b30414b0cc49273b66..bf3a27fe87d7e6fad406f4506cd8712686032964 100644 --- a/components/dfs/filesystems/devfs/devfs.c +++ b/components/dfs/filesystems/devfs/devfs.c @@ -7,7 +7,7 @@ * Date Author Notes * 2018-02-11 Bernard Ignore O_CREAT flag in open. */ - +#include #include #include @@ -37,7 +37,7 @@ int dfs_device_fs_ioctl(struct dfs_fd *file, int cmd, void *args) RT_ASSERT(file != RT_NULL); /* get device handler */ - dev_id = (rt_device_t)file->data; + dev_id = (rt_device_t)file->fnode->data; RT_ASSERT(dev_id != RT_NULL); /* close device handler */ @@ -56,7 +56,7 @@ int dfs_device_fs_read(struct dfs_fd *file, void *buf, size_t count) RT_ASSERT(file != RT_NULL); /* get device handler */ - dev_id = (rt_device_t)file->data; + dev_id = (rt_device_t)file->fnode->data; RT_ASSERT(dev_id != RT_NULL); /* read device data */ @@ -74,7 +74,7 @@ int dfs_device_fs_write(struct dfs_fd *file, const void *buf, size_t count) RT_ASSERT(file != RT_NULL); /* get device handler */ - dev_id = (rt_device_t)file->data; + dev_id = (rt_device_t)file->fnode->data; RT_ASSERT(dev_id != RT_NULL); /* read device data */ @@ -90,12 +90,18 @@ int dfs_device_fs_close(struct dfs_fd *file) rt_device_t dev_id; RT_ASSERT(file != RT_NULL); + RT_ASSERT(file->fnode->ref_count > 0); + + if (file->fnode->ref_count > 1) + { + return 0; + } - if (file->type == FT_DIRECTORY) + if (file->fnode->type == FT_DIRECTORY) { struct device_dirent *root_dirent; - root_dirent = (struct device_dirent *)file->data; + root_dirent = (struct device_dirent *)file->fnode->data; RT_ASSERT(root_dirent != RT_NULL); /* release dirent */ @@ -104,14 +110,14 @@ int dfs_device_fs_close(struct dfs_fd *file) } /* get device handler */ - dev_id = (rt_device_t)file->data; + dev_id = (rt_device_t)file->fnode->data; RT_ASSERT(dev_id != RT_NULL); /* close device handler */ result = rt_device_close(dev_id); if (result == RT_EOK) { - file->data = RT_NULL; + file->fnode->data = RT_NULL; return RT_EOK; } @@ -123,9 +129,16 @@ int dfs_device_fs_open(struct dfs_fd *file) { rt_err_t result; rt_device_t device; + rt_base_t level; + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + file->pos = 0; + return 0; + } /* open root directory */ - if ((file->path[0] == '/') && (file->path[1] == '\0') && + if ((file->fnode->path[0] == '/') && (file->fnode->path[1] == '\0') && (file->flags & O_DIRECTORY)) { struct rt_object *object; @@ -134,8 +147,8 @@ int dfs_device_fs_open(struct dfs_fd *file) struct device_dirent *root_dirent; rt_uint32_t count = 0; - /* lock scheduler */ - rt_enter_critical(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); /* traverse device object */ information = rt_object_get_information(RT_Object_Class_Device); @@ -161,32 +174,34 @@ int dfs_device_fs_open(struct dfs_fd *file) count ++; } } - rt_exit_critical(); + rt_hw_interrupt_enable(level); /* set data */ - file->data = root_dirent; + file->fnode->data = root_dirent; return RT_EOK; } - device = rt_device_find(&file->path[1]); + device = rt_device_find(&file->fnode->path[1]); if (device == RT_NULL) + { return -ENODEV; + } #ifdef RT_USING_POSIX if (device->fops) { /* use device fops */ - file->fops = device->fops; - file->data = (void *)device; + file->fnode->fops = device->fops; + file->fnode->data = (void *)device; /* use fops */ - if (file->fops->open) + if (file->fnode->fops->open) { - result = file->fops->open(file); + result = file->fnode->fops->open(file); if (result == RT_EOK || result == -RT_ENOSYS) { - file->type = FT_DEVICE; + file->fnode->type = FT_DEVICE; return 0; } } @@ -197,13 +212,13 @@ int dfs_device_fs_open(struct dfs_fd *file) result = rt_device_open(device, RT_DEVICE_OFLAG_RDWR); if (result == RT_EOK || result == -RT_ENOSYS) { - file->data = device; - file->type = FT_DEVICE; + file->fnode->data = device; + file->fnode->type = FT_DEVICE; return RT_EOK; } } - file->data = RT_NULL; + file->fnode->data = RT_NULL; /* open device failed. */ return -EIO; } @@ -263,7 +278,7 @@ int dfs_device_fs_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t co struct dirent *d; struct device_dirent *root_dirent; - root_dirent = (struct device_dirent *)file->data; + root_dirent = (struct device_dirent *)file->fnode->data; RT_ASSERT(root_dirent != RT_NULL); /* make integer count */ diff --git a/components/dfs/filesystems/elmfat/dfs_elm.c b/components/dfs/filesystems/elmfat/dfs_elm.c index b4c4c627aa3db27455dbb8b2e5f56e520b566da8..c7f19293bfe1fadea228f214f1d041cf5cb5a4d4 100644 --- a/components/dfs/filesystems/elmfat/dfs_elm.c +++ b/components/dfs/filesystems/elmfat/dfs_elm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -86,10 +86,12 @@ static int get_disk(rt_device_t id) { int index; - for (index = 0; index < _VOLUMES; index ++) + for (index = 0; index < _VOLUMES; index++) { if (disk[index] == id) + { return index; + } } return -1; @@ -106,7 +108,9 @@ int dfs_elm_mount(struct dfs_filesystem *fs, unsigned long rwflag, const void *d /* get an empty position */ index = get_disk(RT_NULL); if (index == -1) + { return -ENOENT; + } logic_nbr[0] = '0' + index; /* save device */ @@ -148,7 +152,9 @@ int dfs_elm_mount(struct dfs_filesystem *fs, unsigned long rwflag, const void *d /* open the root directory to test whether the fatfs is valid */ result = f_opendir(dir, drive); if (result != FR_OK) + { goto __err; + } /* mount succeed! */ fs->data = fat; @@ -177,12 +183,16 @@ int dfs_elm_unmount(struct dfs_filesystem *fs) /* find the device index and then umount it */ index = get_disk(fs->dev_id); if (index == -1) /* not found */ + { return -ENOENT; + } logic_nbr[0] = '0' + index; result = f_mount(RT_NULL, logic_nbr, (BYTE)1); if (result != FR_OK) + { return elm_result_to_dfs(result); + } fs->data = RT_NULL; disk[index] = RT_NULL; @@ -191,7 +201,7 @@ int dfs_elm_unmount(struct dfs_filesystem *fs) return RT_EOK; } -int dfs_elm_mkfs(rt_device_t dev_id) +int dfs_elm_mkfs(rt_device_t dev_id, const char *fs_name) { #define FSM_STATUS_INIT 0 #define FSM_STATUS_USE_TEMP_DRIVER 1 @@ -304,7 +314,9 @@ int dfs_elm_statfs(struct dfs_filesystem *fs, struct statfs *buf) rt_snprintf(driver, sizeof(driver), "%d:", f->drv); res = f_getfree(driver, &fre_clust, &f); if (res) + { return elm_result_to_dfs(res); + } /* Get total sectors and free sectors */ tot_sect = (f->n_fatent - 2) * f->csize; @@ -330,23 +342,41 @@ int dfs_elm_open(struct dfs_fd *file) #if (_VOLUMES > 1) int vol; - struct dfs_filesystem *fs = (struct dfs_filesystem *)file->data; + struct dfs_filesystem *fs = file->fnode->fs; extern int elm_get_vol(FATFS * fat); + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + if (file->fnode->type == FT_DIRECTORY + && !(file->flags & O_DIRECTORY)) + { + return -ENOENT; + } + file->pos = 0; + return 0; + } + if (fs == NULL) + { return -ENOENT; + } /* add path for ELM FatFS driver support */ vol = elm_get_vol((FATFS *)fs->data); if (vol < 0) + { return -ENOENT; + } drivers_fn = (char *)rt_malloc(256); if (drivers_fn == RT_NULL) + { return -ENOMEM; + } - rt_snprintf(drivers_fn, 256, "%d:%s", vol, file->path); + rt_snprintf(drivers_fn, 256, "%d:%s", vol, file->fnode->path); #else - drivers_fn = file->path; + drivers_fn = file->fnode->path; #endif if (file->flags & O_DIRECTORY) @@ -386,6 +416,7 @@ int dfs_elm_open(struct dfs_fd *file) } file->data = dir; + file->fnode->type = FT_DIRECTORY; return RT_EOK; } else @@ -393,18 +424,28 @@ int dfs_elm_open(struct dfs_fd *file) mode = FA_READ; if (file->flags & O_WRONLY) + { mode |= FA_WRITE; + } if ((file->flags & O_ACCMODE) & O_RDWR) + { mode |= FA_WRITE; + } /* Opens the file, if it is existing. If not, a new file is created. */ if (file->flags & O_CREAT) + { mode |= FA_OPEN_ALWAYS; + } /* Creates a new file. If the file is existing, it is truncated and overwritten. */ if (file->flags & O_TRUNC) + { mode |= FA_CREATE_ALWAYS; + } /* Creates a new file. The function fails if the file is already existing. */ if (file->flags & O_EXCL) + { mode |= FA_CREATE_NEW; + } /* allocate a fd */ fd = (FIL *)rt_malloc(sizeof(FIL)); @@ -423,7 +464,8 @@ int dfs_elm_open(struct dfs_fd *file) if (result == FR_OK) { file->pos = fd->fptr; - file->size = f_size(fd); + file->fnode->size = f_size(fd); + file->fnode->type = FT_REGULAR; file->data = fd; if (file->flags & O_APPEND) @@ -448,10 +490,15 @@ int dfs_elm_close(struct dfs_fd *file) { FRESULT result; + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + return 0; + } result = FR_OK; - if (file->type == FT_DIRECTORY) + if (file->fnode->type == FT_DIRECTORY) { - DIR *dir; + DIR *dir = RT_NULL; dir = (DIR *)(file->data); RT_ASSERT(dir != RT_NULL); @@ -459,9 +506,9 @@ int dfs_elm_close(struct dfs_fd *file) /* release memory */ rt_free(dir); } - else if (file->type == FT_REGULAR) + else if (file->fnode->type == FT_REGULAR) { - FIL *fd; + FIL *fd = RT_NULL; fd = (FIL *)(file->data); RT_ASSERT(fd != RT_NULL); @@ -504,6 +551,10 @@ int dfs_elm_ioctl(struct dfs_fd *file, int cmd, void *args) fd->fptr = fptr; return elm_result_to_dfs(result); } + case F_GETLK: + return 0; + case F_SETLK: + return 0; } return -ENOSYS; } @@ -514,7 +565,7 @@ int dfs_elm_read(struct dfs_fd *file, void *buf, size_t len) FRESULT result; UINT byte_read; - if (file->type == FT_DIRECTORY) + if (file->fnode->type == FT_DIRECTORY) { return -EISDIR; } @@ -526,7 +577,9 @@ int dfs_elm_read(struct dfs_fd *file, void *buf, size_t len) /* update position */ file->pos = fd->fptr; if (result == FR_OK) + { return byte_read; + } return elm_result_to_dfs(result); } @@ -537,7 +590,7 @@ int dfs_elm_write(struct dfs_fd *file, const void *buf, size_t len) FRESULT result; UINT byte_write; - if (file->type == FT_DIRECTORY) + if (file->fnode->type == FT_DIRECTORY) { return -EISDIR; } @@ -548,9 +601,11 @@ int dfs_elm_write(struct dfs_fd *file, const void *buf, size_t len) result = f_write(fd, buf, len, &byte_write); /* update position and file size */ file->pos = fd->fptr; - file->size = f_size(fd); + file->fnode->size = f_size(fd); if (result == FR_OK) + { return byte_write; + } return elm_result_to_dfs(result); } @@ -567,10 +622,10 @@ int dfs_elm_flush(struct dfs_fd *file) return elm_result_to_dfs(result); } -int dfs_elm_lseek(struct dfs_fd *file, rt_off_t offset) +int dfs_elm_lseek(struct dfs_fd *file, off_t offset) { FRESULT result = FR_OK; - if (file->type == FT_REGULAR) + if (file->fnode->type == FT_REGULAR) { FIL *fd; @@ -586,10 +641,10 @@ int dfs_elm_lseek(struct dfs_fd *file, rt_off_t offset) return fd->fptr; } } - else if (file->type == FT_DIRECTORY) + else if (file->fnode->type == FT_DIRECTORY) { /* which is a directory */ - DIR *dir; + DIR *dir = RT_NULL; dir = (DIR *)(file->data); RT_ASSERT(dir != RT_NULL); @@ -620,7 +675,9 @@ int dfs_elm_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t count) /* make integer count */ count = (count / sizeof(struct dirent)) * sizeof(struct dirent); if (count == 0) + { return -EINVAL; + } index = 0; while (1) @@ -631,7 +688,9 @@ int dfs_elm_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t count) result = f_readdir(dir, &fno); if (result != FR_OK || fno.fname[0] == 0) + { break; + } #if _USE_LFN fn = *fno.fname ? fno.fname : fno.altname; @@ -641,21 +700,29 @@ int dfs_elm_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t count) d->d_type = DT_UNKNOWN; if (fno.fattrib & AM_DIR) + { d->d_type = DT_DIR; + } else + { d->d_type = DT_REG; + } d->d_namlen = (rt_uint8_t)rt_strlen(fn); d->d_reclen = (rt_uint16_t)sizeof(struct dirent); rt_strncpy(d->d_name, fn, rt_strlen(fn) + 1); - index ++; + index++; if (index * sizeof(struct dirent) >= count) + { break; + } } if (index == 0) + { return elm_result_to_dfs(result); + } file->pos += index * sizeof(struct dirent); @@ -674,10 +741,14 @@ int dfs_elm_unlink(struct dfs_filesystem *fs, const char *path) /* add path for ELM FatFS driver support */ vol = elm_get_vol((FATFS *)fs->data); if (vol < 0) + { return -ENOENT; + } drivers_fn = (char *)rt_malloc(256); if (drivers_fn == RT_NULL) + { return -ENOMEM; + } rt_snprintf(drivers_fn, 256, "%d:%s", vol, path); #else @@ -705,11 +776,15 @@ int dfs_elm_rename(struct dfs_filesystem *fs, const char *oldpath, const char *n /* add path for ELM FatFS driver support */ vol = elm_get_vol((FATFS *)fs->data); if (vol < 0) + { return -ENOENT; + } drivers_oldfn = (char *)rt_malloc(256); if (drivers_oldfn == RT_NULL) + { return -ENOMEM; + } drivers_newfn = newpath; rt_snprintf(drivers_oldfn, 256, "%d:%s", vol, oldpath); @@ -740,10 +815,14 @@ int dfs_elm_stat(struct dfs_filesystem *fs, const char *path, struct stat *st) /* add path for ELM FatFS driver support */ vol = elm_get_vol((FATFS *)fs->data); if (vol < 0) + { return -ENOENT; + } drivers_fn = (char *)rt_malloc(256); if (drivers_fn == RT_NULL) + { return -ENOMEM; + } rt_snprintf(drivers_fn, 256, "%d:%s", vol, path); #else @@ -768,7 +847,9 @@ int dfs_elm_stat(struct dfs_filesystem *fs, const char *path, struct stat *st) st->st_mode |= S_IFDIR | S_IXUSR | S_IXGRP | S_IXOTH; } if (file_info.fattrib & AM_RDO) + { st->st_mode &= ~(S_IWUSR | S_IWGRP | S_IWOTH); + } st->st_size = file_info.fsize; @@ -898,7 +979,9 @@ DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff) rt_device_t device = disk[drv]; if (device == RT_NULL) + { return RES_ERROR; + } if (ctrl == GET_SECTOR_COUNT) { @@ -909,7 +992,9 @@ DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff) *(DWORD *)buff = geometry.sector_count; if (geometry.sector_count == 0) + { return RES_ERROR; + } } else if (ctrl == GET_SECTOR_SIZE) { @@ -993,7 +1078,9 @@ int ff_cre_syncobj(BYTE drv, _SYNC_t *m) int ff_del_syncobj(_SYNC_t m) { if (m != RT_NULL) + { rt_mutex_delete(m); + } return RT_TRUE; } @@ -1001,7 +1088,9 @@ int ff_del_syncobj(_SYNC_t m) int ff_req_grant(_SYNC_t m) { if (rt_mutex_take(m, _FS_TIMEOUT) == RT_EOK) + { return RT_TRUE; + } return RT_FALSE; } diff --git a/components/dfs/filesystems/jffs2/dfs_jffs2.c b/components/dfs/filesystems/jffs2/dfs_jffs2.c index c082c21d7351ebd61455ffc6fc369f643dfb82cb..2f1944eb8fe67d8e4626d4e315247d7e0c151ad0 100644 --- a/components/dfs/filesystems/jffs2/dfs_jffs2.c +++ b/components/dfs/filesystems/jffs2/dfs_jffs2.c @@ -102,14 +102,20 @@ static int dfs_jffs2_mount(struct dfs_filesystem* fs, for (index = 0; index < DEVICE_PART_MAX; index ++) { if (device_partition[index].dev == RT_NULL) + { break; + } } if (index == DEVICE_PART_MAX) + { return -ENOSPC; + } mte = rt_malloc(sizeof(struct cyg_mtab_entry)); if (mte == RT_NULL) + { return -ENOMEM; + } mte->name = fs->path; mte->fsname = "jffs2"; @@ -176,7 +182,7 @@ static int dfs_jffs2_unmount(struct dfs_filesystem* fs) return -ENOENT; } -static int dfs_jffs2_mkfs(rt_device_t dev_id) +static int dfs_jffs2_mkfs(rt_device_t dev_id, const char *fs_name) { /* just erase all blocks on this nand partition */ return -ENOSYS; @@ -192,7 +198,9 @@ static int dfs_jffs2_statfs(struct dfs_filesystem* fs, result = _find_fs(&mte, fs->dev_id); if (result) + { return -ENOENT; + } RT_ASSERT(mte->data != 0); @@ -215,20 +223,38 @@ static int dfs_jffs2_open(struct dfs_fd* file) struct dfs_filesystem *fs; struct cyg_mtab_entry * mte; + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + if (file->fnode->type == FT_DIRECTORY + && !(file->flags & O_DIRECTORY)) + { + return -ENOENT; + } + file->pos = 0; + return 0; + } + oflag = file->flags; - fs = (struct dfs_filesystem *)file->data; + fs = file->fnode->fs; RT_ASSERT(fs != RT_NULL); jffs2_file = rt_malloc(sizeof(cyg_file)); if (jffs2_file == RT_NULL) + { return -ENOMEM; + } /* just escape '/' provided by dfs code */ - name = file->path; + name = file->fnode->path; if ((name[0] == '/') && (name[1] == 0)) + { name = jffs2_root_path; + } else /* name[0] still will be '/' */ - name ++; + { + name++; + } result = _find_fs(&mte, fs->dev_id); if (result) @@ -267,7 +293,8 @@ static int dfs_jffs2_open(struct dfs_fd* file) jffs2_file->f_offset = 2; #endif /* save this pointer, it will be used by dfs_jffs2_getdents*/ - file->data = jffs2_file; + file->fnode->data = jffs2_file; + file->fnode->type = FT_DIRECTORY; return 0; } /* regular file operations */ @@ -292,17 +319,18 @@ static int dfs_jffs2_open(struct dfs_fd* file) /* save this pointer, it will be used when calling read(), write(), flush(), lessk(), and will be rt_free when calling close()*/ - file->data = jffs2_file; + file->fnode->data = jffs2_file; file->pos = jffs2_file->f_offset; - file->size = 0; - jffs2_file_lseek(jffs2_file, (off_t *)(&(file->size)), SEEK_END); + file->fnode->size = 0; + file->fnode->type = FT_REGULAR; + jffs2_file_lseek(jffs2_file, (off_t *)(&(file->fnode->size)), SEEK_END); jffs2_file->f_offset = (off_t)file->pos; rt_mutex_release(&jffs2_lock); if (oflag & O_APPEND) { - file->pos = file->size; - jffs2_file->f_offset = file->size; + file->pos = file->fnode->size; + jffs2_file->f_offset = file->fnode->size; } return 0; @@ -313,8 +341,14 @@ static int dfs_jffs2_close(struct dfs_fd* file) int result; cyg_file * jffs2_file; - RT_ASSERT(file->data != NULL); - jffs2_file = (cyg_file *)(file->data); + RT_ASSERT(file->fnode->data != NULL); + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + return 0; + } + + jffs2_file = (cyg_file *)(file->fnode->data); if (file->flags & O_DIRECTORY) /* operations about dir */ { @@ -322,7 +356,9 @@ static int dfs_jffs2_close(struct dfs_fd* file) result = jffs2_dir_colse(jffs2_file); rt_mutex_release(&jffs2_lock); if (result) + { return jffs2_result_to_dfs(result); + } rt_free(jffs2_file); return 0; @@ -332,7 +368,9 @@ static int dfs_jffs2_close(struct dfs_fd* file) result = jffs2_file_colse(jffs2_file); rt_mutex_release(&jffs2_lock); if (result) + { return jffs2_result_to_dfs(result); + } /* release memory */ rt_free(jffs2_file); @@ -352,8 +390,8 @@ static int dfs_jffs2_read(struct dfs_fd* file, void* buf, size_t len) int char_read; int result; - RT_ASSERT(file->data != NULL); - jffs2_file = (cyg_file *)(file->data); + RT_ASSERT(file->fnode->data != NULL); + jffs2_file = (cyg_file *)(file->fnode->data); uio_s.uio_iov = &iovec; uio_s.uio_iov->iov_base = buf; uio_s.uio_iov->iov_len = len; @@ -366,7 +404,9 @@ static int dfs_jffs2_read(struct dfs_fd* file, void* buf, size_t len) result = jffs2_file_read(jffs2_file, &uio_s); rt_mutex_release(&jffs2_lock); if (result) + { return jffs2_result_to_dfs(result); + } /* update position */ file->pos = jffs2_file->f_offset; @@ -384,8 +424,8 @@ static int dfs_jffs2_write(struct dfs_fd* file, int char_write; int result; - RT_ASSERT(file->data != NULL); - jffs2_file = (cyg_file *)(file->data); + RT_ASSERT(file->fnode->data != NULL); + jffs2_file = (cyg_file *)(file->fnode->data); uio_s.uio_iov = &iovec; uio_s.uio_iov->iov_base = (void *)buf; uio_s.uio_iov->iov_len = len; @@ -398,7 +438,9 @@ static int dfs_jffs2_write(struct dfs_fd* file, result = jffs2_file_write(jffs2_file, &uio_s); rt_mutex_release(&jffs2_lock); if (result) + { return jffs2_result_to_dfs(result); + } /* update position */ file->pos = jffs2_file->f_offset; @@ -414,20 +456,22 @@ static int dfs_jffs2_flush(struct dfs_fd* file) /* fixme warning: the offset is rt_off_t, so maybe the size of a file is must <= 2G*/ static int dfs_jffs2_lseek(struct dfs_fd* file, - rt_off_t offset) + off_t offset) { cyg_file * jffs2_file; int result; - RT_ASSERT(file->data != NULL); - jffs2_file = (cyg_file *)(file->data); + RT_ASSERT(file->fnode->data != NULL); + jffs2_file = (cyg_file *)(file->fnode->data); /* set offset as current offset */ rt_mutex_take(&jffs2_lock, RT_WAITING_FOREVER); result = jffs2_file_lseek(jffs2_file, &offset, SEEK_SET); rt_mutex_release(&jffs2_lock); if (result) + { return jffs2_result_to_dfs(result); + } /* update file position */ file->pos = offset; return offset; @@ -451,8 +495,8 @@ static int dfs_jffs2_getdents(struct dfs_fd* file, #endif int result; - RT_ASSERT(file->data != RT_NULL); - jffs2_file = (cyg_file*)(file->data); + RT_ASSERT(file->fnode->data != RT_NULL); + jffs2_file = (cyg_file*)(file->fnode->data); mte = jffs2_file->f_mte; //set jffs2_d @@ -479,7 +523,9 @@ static int dfs_jffs2_getdents(struct dfs_fd* file, rt_mutex_release(&jffs2_lock); /* if met a error or all entry are read over, break while*/ if (result || jffs2_d.d_name[0] == 0) + { break; + } #if defined (CYGPKG_FS_JFFS2_RET_DIRENT_DTYPE) switch(jffs2_d.d_type & JFFS2_S_IFMT) @@ -494,20 +540,28 @@ static int dfs_jffs2_getdents(struct dfs_fd* file, return -ENOMEM; /* make a right entry */ - if ((file->path[0] == '/') ) + if (file->fnode->path[0] == '/') { - if (file->path[1] == 0) + if (file->fnode->path[1] == 0) + { strcpy(fullname, jffs2_d.d_name); + } else - rt_sprintf(fullname, "%s/%s", file->path+1, jffs2_d.d_name); + { + rt_sprintf(fullname, "%s/%s", file->fnode->path+1, jffs2_d.d_name); + } } else - rt_sprintf(fullname, "%s/%s", file->path, jffs2_d.d_name); + { + rt_sprintf(fullname, "%s/%s", file->fnode->path, jffs2_d.d_name); + } rt_mutex_take(&jffs2_lock, RT_WAITING_FOREVER); result = jffs2_porting_stat(mte, mte->root, fullname, (void *)&s); rt_mutex_release(&jffs2_lock); if (result) + { return jffs2_result_to_dfs(result); + } rt_free(fullname); /* convert to dfs stat structure */ @@ -523,12 +577,16 @@ static int dfs_jffs2_getdents(struct dfs_fd* file, d->d_reclen = (rt_uint16_t)sizeof(struct dirent); rt_strncpy(d->d_name, jffs2_d.d_name, d->d_namlen + 1); - index ++; + index++; if (index * sizeof(struct dirent) >= count) + { break; + } } if (result) + { return jffs2_result_to_dfs(result); + } return index * sizeof(struct dirent); } @@ -540,11 +598,15 @@ static int dfs_jffs2_unlink(struct dfs_filesystem* fs, const char* path) result = _find_fs(&mte, fs->dev_id); if (result) + { return -ENOENT; + } /* deal path */ if (path[0] == '/') + { path++; + } /* judge file type, dir is to be delete by rmdir, others by unlink */ rt_mutex_take(&jffs2_lock, RT_WAITING_FOREVER); @@ -570,7 +632,9 @@ static int dfs_jffs2_unlink(struct dfs_filesystem* fs, const char* path) } rt_mutex_release(&jffs2_lock); if (result) + { return jffs2_result_to_dfs(result); + } return 0; } @@ -583,17 +647,25 @@ static int dfs_jffs2_rename(struct dfs_filesystem* fs, result = _find_fs(&mte, fs->dev_id); if (result) + { return -ENOENT; + } if (*oldpath == '/') + { oldpath += 1; + } if (*newpath == '/') + { newpath += 1; + } rt_mutex_take(&jffs2_lock, RT_WAITING_FOREVER); result = jffs2_rename(mte, mte->root, oldpath, mte->root, newpath); rt_mutex_release(&jffs2_lock); if (result) + { return jffs2_result_to_dfs(result); + } return 0; } @@ -607,18 +679,24 @@ static int dfs_jffs2_stat(struct dfs_filesystem* fs, const char *path, struct st RT_ASSERT(!((path[0] == '/') && (path[1] == 0))); if (path[0] == '/') + { path++; + } result = _find_fs(&mte, fs->dev_id); if (result) + { return -ENOENT; + } rt_mutex_take(&jffs2_lock, RT_WAITING_FOREVER); result = jffs2_porting_stat(mte, mte->root, path, (void *)&s); rt_mutex_release(&jffs2_lock); if (result) + { return jffs2_result_to_dfs(result); + } /* convert to dfs stat structure */ switch(s.st_mode & JFFS2_S_IFMT) { diff --git a/components/dfs/filesystems/jffs2/include/port/sys/stat.h b/components/dfs/filesystems/jffs2/include/port/sys/stat.h index 43958a752f57f20a3161cc568fd923ea193d3d62..10a0c9820870fa4113690eb22a727e55ee3e5509 100644 --- a/components/dfs/filesystems/jffs2/include/port/sys/stat.h +++ b/components/dfs/filesystems/jffs2/include/port/sys/stat.h @@ -82,11 +82,15 @@ typedef unsigned int mode_t; #endif */ +/* typedef unsigned short nlink_t; typedef long off_t; +*/ +/* typedef unsigned short gid_t; typedef unsigned short uid_t; +*/ typedef int pid_t; // diff --git a/components/dfs/filesystems/jffs2/porting.h b/components/dfs/filesystems/jffs2/porting.h index 2671f46dded4b0bf76e7aff4b48f69e3dc1b988f..3354cc1d7d981b2928e209ec59c04176bd912eb9 100644 --- a/components/dfs/filesystems/jffs2/porting.h +++ b/components/dfs/filesystems/jffs2/porting.h @@ -22,9 +22,9 @@ struct jffs2_stat { unsigned short st_uid; /* User ID of the file owner */ unsigned short st_gid; /* Group ID of the file's group */ long st_size; /* File size (regular files only) */ - long st_atime; /* Last access time */ - long st_mtime; /* Last data modification time */ - long st_ctime; /* Last file status change time */ + struct timespec st_atim; /* Last access time */ + struct timespec st_mtim; /* Last data modification time */ + struct timespec st_ctim; /* Last file status change time */ }; struct jffs2_dirent diff --git a/components/dfs/filesystems/nfs/dfs_nfs.c b/components/dfs/filesystems/nfs/dfs_nfs.c index e60f6f98c092becd5f4c8f54bbe07512d6108c17..fc296b6eb1714502fe41bd5f4afb40ff286b76c4 100644 --- a/components/dfs/filesystems/nfs/dfs_nfs.c +++ b/components/dfs/filesystems/nfs/dfs_nfs.c @@ -559,12 +559,11 @@ int nfs_read(struct dfs_fd *file, void *buf, size_t count) nfs_file *fd; nfs_filesystem *nfs; - if (file->type == FT_DIRECTORY) + if (file->fnode->type == FT_DIRECTORY) return -EISDIR; - - RT_ASSERT(file->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->data)); + RT_ASSERT(file->fnode->data != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); nfs = (struct nfs_filesystem *)(dfs_nfs->data); fd = (nfs_file *)(nfs->data); RT_ASSERT(fd != NULL); @@ -629,11 +628,11 @@ int nfs_write(struct dfs_fd *file, const void *buf, size_t count) nfs_file *fd; nfs_filesystem *nfs; - if (file->type == FT_DIRECTORY) + if (file->fnode->type == FT_DIRECTORY) return -EISDIR; - RT_ASSERT(file->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->data)); + RT_ASSERT(file->fnode->data != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); nfs = (struct nfs_filesystem *)(dfs_nfs->data); fd = (nfs_file *)(nfs->data); RT_ASSERT(fd != NULL); @@ -676,11 +675,10 @@ int nfs_write(struct dfs_fd *file, const void *buf, size_t count) file->pos = fd->offset; /* update file size */ if (fd->size < fd->offset) fd->size = fd->offset; - file->size = fd->size; + file->fnode->size = fd->size; } xdr_free((xdrproc_t)xdr_WRITE3res, (char *)&res); - } - while (count > 0); + } while (count > 0); xdr_free((xdrproc_t)xdr_WRITE3res, (char *)&res); @@ -692,11 +690,11 @@ int nfs_lseek(struct dfs_fd *file, off_t offset) nfs_file *fd; nfs_filesystem *nfs; - if (file->type == FT_DIRECTORY) + if (file->fnode->type == FT_DIRECTORY) return -EISDIR; - RT_ASSERT(file->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->data)); + RT_ASSERT(file->fnode->data != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); nfs = (struct nfs_filesystem *)(dfs_nfs->data); fd = (nfs_file *)(nfs->data); RT_ASSERT(fd != NULL); @@ -714,11 +712,18 @@ int nfs_lseek(struct dfs_fd *file, off_t offset) int nfs_close(struct dfs_fd *file) { nfs_filesystem *nfs; - RT_ASSERT(file->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->data)); + RT_ASSERT(file->fnode->data != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); + + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + return 0; + } + nfs = (struct nfs_filesystem *)(dfs_nfs->data); - if (file->type == FT_DIRECTORY) + if (file->fnode->type == FT_DIRECTORY) { struct nfs_dir *dir; @@ -727,7 +732,7 @@ int nfs_close(struct dfs_fd *file) xdr_free((xdrproc_t)xdr_READDIR3res, (char *)&dir->res); rt_free(dir); } - else if (file->type == FT_REGULAR) + else if (file->fnode->type == FT_REGULAR) { struct nfs_file *fd; @@ -744,24 +749,42 @@ int nfs_close(struct dfs_fd *file) int nfs_open(struct dfs_fd *file) { nfs_filesystem *nfs; - RT_ASSERT(file->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->data)); + RT_ASSERT(file->fnode->data != NULL); + struct dfs_filesystem *dfs_nfs = file->fnode->fs; nfs = (struct nfs_filesystem *)(dfs_nfs->data); RT_ASSERT(nfs != NULL); + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + if (file->fnode->type == FT_DIRECTORY + && !(file->flags & O_DIRECTORY)) + { + return -ENOENT; + } + file->pos = 0; + return 0; + } + if (file->flags & O_DIRECTORY) { nfs_dir *dir; if (file->flags & O_CREAT) { - if (nfs_mkdir(nfs, file->path, 0755) < 0) + if (nfs_mkdir(nfs, file->fnode->path, 0755) < 0) + { return -EAGAIN; + } } /* open directory */ - dir = nfs_opendir(nfs, file->path); - if (dir == NULL) return -ENOENT; + dir = nfs_opendir(nfs, file->fnode->path); + if (dir == NULL) + { + return -ENOENT; + } + file->fnode->type = FT_DIRECTORY; nfs->data = dir; } else @@ -772,8 +795,10 @@ int nfs_open(struct dfs_fd *file) /* create file */ if (file->flags & O_CREAT) { - if (nfs_create(nfs, file->path, 0664) < 0) + if (nfs_create(nfs, file->fnode->path, 0664) < 0) + { return -EAGAIN; + } } /* open file (get file handle ) */ @@ -781,7 +806,7 @@ int nfs_open(struct dfs_fd *file) if (fp == NULL) return -ENOMEM; - handle = get_handle(nfs, file->path); + handle = get_handle(nfs, file->fnode->path); if (handle == NULL) { rt_free(fp); @@ -805,7 +830,8 @@ int nfs_open(struct dfs_fd *file) /* set private file */ nfs->data = fp; - file->size = fp->size; + file->fnode->size = fp->size; + file->fnode->type = FT_REGULAR; } return 0; @@ -1085,9 +1111,8 @@ int nfs_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t count) nfs_filesystem *nfs; char *name; - - RT_ASSERT(file->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->data)); + RT_ASSERT(file->fnode->data != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); nfs = (struct nfs_filesystem *)(dfs_nfs->data); dir = (nfs_dir *)(nfs->data); RT_ASSERT(dir != NULL); diff --git a/components/dfs/filesystems/nfs/rpc/types.h b/components/dfs/filesystems/nfs/rpc/types.h index 254fcd339c266b8996b628fa3956db7204a5441f..5c02c07e34002843893d75ef6a5af9e017d37564 100644 --- a/components/dfs/filesystems/nfs/rpc/types.h +++ b/components/dfs/filesystems/nfs/rpc/types.h @@ -63,11 +63,11 @@ typedef unsigned long long uint64_t; typedef int bool_t; typedef int enum_t; -#ifndef RT_USING_NEWLIB +#if !defined(RT_USING_NEWLIB) && !defined(RT_USING_MUSL) typedef unsigned long dev_t; #endif -#if !defined(RT_USING_NEWLIB) && !defined(RT_USING_MINILIBC) +#if !defined(RT_USING_NEWLIB) && !defined(RT_USING_MINILIBC) && !defined(RT_USING_MUSL) typedef rt_int32_t ssize_t; #endif diff --git a/components/dfs/filesystems/ramfs/dfs_ramfs.c b/components/dfs/filesystems/ramfs/dfs_ramfs.c index aa85081e1e9754b39490ca27b4b59b59fe658481..e08a26381689478fd5b70055ad055c2fe4c713a2 100644 --- a/components/dfs/filesystems/ramfs/dfs_ramfs.c +++ b/components/dfs/filesystems/ramfs/dfs_ramfs.c @@ -97,13 +97,13 @@ int dfs_ramfs_read(struct dfs_fd *file, void *buf, size_t count) rt_size_t length; struct ramfs_dirent *dirent; - dirent = (struct ramfs_dirent *)file->data; + dirent = (struct ramfs_dirent *)file->fnode->data; RT_ASSERT(dirent != NULL); - if (count < file->size - file->pos) + if (count < file->fnode->size - file->pos) length = count; else - length = file->size - file->pos; + length = file->fnode->size - file->pos; if (length > 0) memcpy(buf, &(dirent->data[file->pos]), length); @@ -119,13 +119,13 @@ int dfs_ramfs_write(struct dfs_fd *fd, const void *buf, size_t count) struct ramfs_dirent *dirent; struct dfs_ramfs *ramfs; - dirent = (struct ramfs_dirent *)fd->data; + dirent = (struct ramfs_dirent *)fd->fnode->data; RT_ASSERT(dirent != NULL); ramfs = dirent->fs; RT_ASSERT(ramfs != NULL); - if (count + fd->pos > fd->size) + if (count + fd->pos > fd->fnode->size) { rt_uint8_t *ptr; ptr = rt_memheap_realloc(&(ramfs->memheap), dirent->data, fd->pos + count); @@ -139,7 +139,7 @@ int dfs_ramfs_write(struct dfs_fd *fd, const void *buf, size_t count) /* update dirent and file size */ dirent->data = ptr; dirent->size = fd->pos + count; - fd->size = dirent->size; + fd->fnode->size = dirent->size; } if (count > 0) @@ -153,7 +153,7 @@ int dfs_ramfs_write(struct dfs_fd *fd, const void *buf, size_t count) int dfs_ramfs_lseek(struct dfs_fd *file, off_t offset) { - if (offset <= (off_t)file->size) + if (offset <= (off_t)file->fnode->size) { file->pos = offset; @@ -165,7 +165,13 @@ int dfs_ramfs_lseek(struct dfs_fd *file, off_t offset) int dfs_ramfs_close(struct dfs_fd *file) { - file->data = NULL; + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + return 0; + } + + file->fnode->data = NULL; return RT_EOK; } @@ -177,7 +183,19 @@ int dfs_ramfs_open(struct dfs_fd *file) struct ramfs_dirent *dirent; struct dfs_filesystem *fs; - fs = (struct dfs_filesystem *)file->data; + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + if (file->fnode->type == FT_DIRECTORY + && !(file->flags & O_DIRECTORY)) + { + return -ENOENT; + } + file->pos = 0; + return 0; + } + + fs = file->fnode->fs; ramfs = (struct dfs_ramfs *)fs->data; RT_ASSERT(ramfs != NULL); @@ -190,7 +208,7 @@ int dfs_ramfs_open(struct dfs_fd *file) } /* open directory */ - dirent = dfs_ramfs_lookup(ramfs, file->path, &size); + dirent = dfs_ramfs_lookup(ramfs, file->fnode->path, &size); if (dirent == NULL) return -ENOENT; if (dirent == &(ramfs->root)) /* it's root directory */ @@ -200,10 +218,11 @@ int dfs_ramfs_open(struct dfs_fd *file) return -ENOENT; } } + file->fnode->type = FT_DIRECTORY; } else { - dirent = dfs_ramfs_lookup(ramfs, file->path, &size); + dirent = dfs_ramfs_lookup(ramfs, file->fnode->path, &size); if (dirent == &(ramfs->root)) /* it's root directory */ { return -ENOENT; @@ -225,15 +244,18 @@ int dfs_ramfs_open(struct dfs_fd *file) } /* remove '/' separator */ - name_ptr = file->path; + name_ptr = file->fnode->path; while (*name_ptr == '/' && *name_ptr) - name_ptr ++; + { + name_ptr++; + } strncpy(dirent->name, name_ptr, RAMFS_NAME_MAX); rt_list_init(&(dirent->list)); dirent->data = NULL; dirent->size = 0; dirent->fs = ramfs; + file->fnode->type = FT_DIRECTORY; /* add to the root directory */ rt_list_insert_after(&(ramfs->root.list), &(dirent->list)); @@ -256,12 +278,16 @@ int dfs_ramfs_open(struct dfs_fd *file) } } - file->data = dirent; - file->size = dirent->size; + file->fnode->data = dirent; + file->fnode->size = dirent->size; if (file->flags & O_APPEND) - file->pos = file->size; + { + file->pos = file->fnode->size; + } else + { file->pos = 0; + } return 0; } @@ -299,7 +325,7 @@ int dfs_ramfs_getdents(struct dfs_fd *file, struct ramfs_dirent *dirent; struct dfs_ramfs *ramfs; - dirent = (struct ramfs_dirent *)file->data; + dirent = (struct ramfs_dirent *)file->fnode->data; ramfs = dirent->fs; RT_ASSERT(ramfs != RT_NULL); diff --git a/components/dfs/filesystems/romfs/dfs_romfs.c b/components/dfs/filesystems/romfs/dfs_romfs.c index dcc34e58307e54906ec4c8614dda664ac735413a..086267ecef4a559835c96db97b5a492e3f28c6b8 100644 --- a/components/dfs/filesystems/romfs/dfs_romfs.c +++ b/components/dfs/filesystems/romfs/dfs_romfs.c @@ -34,7 +34,28 @@ int dfs_romfs_unmount(struct dfs_filesystem *fs) int dfs_romfs_ioctl(struct dfs_fd *file, int cmd, void *args) { - return -EIO; + int ret = RT_EOK; + struct romfs_dirent *dirent; + + dirent = (struct romfs_dirent *)file->fnode->data; + RT_ASSERT(dirent != NULL); + + switch (cmd) + { + case RT_FIOGETADDR: + { + *(rt_ubase_t*)args = (rt_ubase_t)dirent->data; + break; + } + case RT_FIOFTRUNCATE: + { + break; + } + default: + ret = -RT_EINVAL; + break; + } + return ret; } rt_inline int check_dirent(struct romfs_dirent *dirent) @@ -112,9 +133,6 @@ struct romfs_dirent *dfs_romfs_lookup(struct romfs_dirent *root_dirent, const ch else { /* return file dirent */ - if (subpath != NULL) - break; /* not the end of path */ - return &dirent[index]; } } @@ -133,7 +151,7 @@ int dfs_romfs_read(struct dfs_fd *file, void *buf, size_t count) rt_size_t length; struct romfs_dirent *dirent; - dirent = (struct romfs_dirent *)file->data; + dirent = (struct romfs_dirent *)file->fnode->data; RT_ASSERT(dirent != NULL); if (check_dirent(dirent) != 0) @@ -141,10 +159,10 @@ int dfs_romfs_read(struct dfs_fd *file, void *buf, size_t count) return -EIO; } - if (count < file->size - file->pos) + if (count < file->fnode->size - file->pos) length = count; else - length = file->size - file->pos; + length = file->fnode->size - file->pos; if (length > 0) memcpy(buf, &(dirent->data[file->pos]), length); @@ -157,7 +175,7 @@ int dfs_romfs_read(struct dfs_fd *file, void *buf, size_t count) int dfs_romfs_lseek(struct dfs_fd *file, off_t offset) { - if (offset <= file->size) + if (offset <= file->fnode->size) { file->pos = offset; return file->pos; @@ -168,7 +186,12 @@ int dfs_romfs_lseek(struct dfs_fd *file, off_t offset) int dfs_romfs_close(struct dfs_fd *file) { - file->data = NULL; + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + return RT_EOK; + } + file->fnode->data = NULL; return RT_EOK; } @@ -179,34 +202,63 @@ int dfs_romfs_open(struct dfs_fd *file) struct romfs_dirent *root_dirent; struct dfs_filesystem *fs; - fs = (struct dfs_filesystem *)file->data; + if (file->flags & (O_CREAT | O_WRONLY | O_APPEND | O_TRUNC | O_RDWR)) + { + return -EINVAL; + } + + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + if (file->fnode->type == FT_DIRECTORY + && !(file->flags & O_DIRECTORY)) + { + return -ENOENT; + } + file->pos = 0; + return 0; + } + + fs = file->fnode->fs; root_dirent = (struct romfs_dirent *)fs->data; if (check_dirent(root_dirent) != 0) + { return -EIO; + } if (file->flags & (O_CREAT | O_WRONLY | O_APPEND | O_TRUNC | O_RDWR)) + { return -EINVAL; + } - dirent = dfs_romfs_lookup(root_dirent, file->path, &size); + dirent = dfs_romfs_lookup(root_dirent, file->fnode->path, &size); if (dirent == NULL) + { return -ENOENT; + } /* entry is a directory file type */ if (dirent->type == ROMFS_DIRENT_DIR) { if (!(file->flags & O_DIRECTORY)) + { return -ENOENT; + } + file->fnode->type = FT_DIRECTORY; } else { /* entry is a file, but open it as a directory */ if (file->flags & O_DIRECTORY) + { return -ENOENT; + } + file->fnode->type = FT_REGULAR; } - file->data = dirent; - file->size = size; + file->fnode->data = dirent; + file->fnode->size = size; file->pos = 0; return RT_EOK; @@ -222,7 +274,9 @@ int dfs_romfs_stat(struct dfs_filesystem *fs, const char *path, struct stat *st) dirent = dfs_romfs_lookup(root_dirent, path, &size); if (dirent == NULL) + { return -ENOENT; + } st->st_dev = 0; st->st_mode = S_IFREG | S_IRUSR | S_IRGRP | S_IROTH | @@ -247,9 +301,11 @@ int dfs_romfs_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t count) struct dirent *d; struct romfs_dirent *dirent, *sub_dirent; - dirent = (struct romfs_dirent *)file->data; + dirent = (struct romfs_dirent *)file->fnode->data; if (check_dirent(dirent) != 0) + { return -EIO; + } RT_ASSERT(dirent->type == ROMFS_DIRENT_DIR); /* enter directory */ @@ -258,10 +314,12 @@ int dfs_romfs_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t count) /* make integer count */ count = (count / sizeof(struct dirent)); if (count == 0) + { return -EINVAL; + } index = 0; - for (index = 0; index < count && file->pos < file->size; index ++) + for (index = 0; index < count && file->pos < file->fnode->size; index++) { d = dirp + index; diff --git a/components/dfs/filesystems/uffs/dfs_uffs.c b/components/dfs/filesystems/uffs/dfs_uffs.c index fb8caf9dd768deb77fa6c05333aca344ec4ad8bc..b7b999b8468e5ff1d2ecc85908aa58805e9db95c 100644 --- a/components/dfs/filesystems/uffs/dfs_uffs.c +++ b/components/dfs/filesystems/uffs/dfs_uffs.c @@ -206,7 +206,7 @@ static int dfs_uffs_unmount(struct dfs_filesystem *fs) return -ENOENT; } -static int dfs_uffs_mkfs(rt_device_t dev_id) +static int dfs_uffs_mkfs(rt_device_t dev_id, const char *fs_name) { rt_base_t index; rt_uint32_t block; @@ -281,6 +281,18 @@ static int dfs_uffs_open(struct dfs_fd *file) int oflag, mode; char *file_path; + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + if (file->fnode->type == FT_DIRECTORY + && !(file->flags & O_DIRECTORY)) + { + return -ENOENT; + } + file->pos = 0; + return 0; + } + oflag = file->flags; if (oflag & O_DIRECTORY) /* operations about dir */ { @@ -288,7 +300,7 @@ static int dfs_uffs_open(struct dfs_fd *file) if (oflag & O_CREAT) /* create a dir*/ { - if (uffs_mkdir(file->path) < 0) + if (uffs_mkdir(file->fnode->path) < 0) return uffs_result_to_dfs(uffs_get_error()); } /* open dir */ @@ -296,8 +308,8 @@ static int dfs_uffs_open(struct dfs_fd *file) if (file_path == RT_NULL) return -ENOMEM; - if (file->path[0] == '/' && !(file->path[1] == 0)) - rt_snprintf(file_path, FILE_PATH_MAX, "%s/", file->path); + if (file->fnode->path[0] == '/' && !(file->fnode->path[1] == 0)) + rt_snprintf(file_path, FILE_PATH_MAX, "%s/", file->fnode->path); else { file_path[0] = '/'; @@ -312,7 +324,8 @@ static int dfs_uffs_open(struct dfs_fd *file) return uffs_result_to_dfs(uffs_get_error()); } /* save this pointer,will used by dfs_uffs_getdents*/ - file->data = dir; + file->fnode->data = dir; + file->fnode->type = FT_DIRECTORY; rt_free(file_path); return RT_EOK; } @@ -330,7 +343,7 @@ static int dfs_uffs_open(struct dfs_fd *file) /* Creates a new file. The function fails if the file is already existing. */ if (oflag & O_EXCL) mode |= UO_EXCL; - fd = uffs_open(file->path, mode); + fd = uffs_open(file->fnode->path, mode); if (fd < 0) { return uffs_result_to_dfs(uffs_get_error()); @@ -339,9 +352,9 @@ static int dfs_uffs_open(struct dfs_fd *file) /* save this pointer, it will be used when calling read(), write(), * flush(), seek(), and will be free when calling close()*/ - file->data = (void *)fd; + file->fnode->data = (void *)fd; file->pos = uffs_seek(fd, 0, USEEK_CUR); - file->size = uffs_seek(fd, 0, USEEK_END); + file->fnode->size = uffs_seek(fd, 0, USEEK_END); uffs_seek(fd, file->pos, USEEK_SET); if (oflag & O_APPEND) @@ -356,17 +369,23 @@ static int dfs_uffs_close(struct dfs_fd *file) int oflag; int fd; + RT_ASSERT(file->fnode->ref_count > 0); + if (file->fnode->ref_count > 1) + { + return 0; + } + oflag = file->flags; if (oflag & O_DIRECTORY) { /* operations about dir */ - if (uffs_closedir((uffs_DIR *)(file->data)) < 0) + if (uffs_closedir((uffs_DIR *)(file->fnode->data)) < 0) return uffs_result_to_dfs(uffs_get_error()); return 0; } /* regular file operations */ - fd = (int)(file->data); + fd = (int)(file->fnode->data); if (uffs_close(fd) == 0) return 0; @@ -384,7 +403,7 @@ static int dfs_uffs_read(struct dfs_fd *file, void *buf, size_t len) int fd; int char_read; - fd = (int)(file->data); + fd = (int)(file->fnode->data); char_read = uffs_read(fd, buf, len); if (char_read < 0) return uffs_result_to_dfs(uffs_get_error()); @@ -401,7 +420,7 @@ static int dfs_uffs_write(struct dfs_fd *file, int fd; int char_write; - fd = (int)(file->data); + fd = (int)(file->fnode->data); char_write = uffs_write(fd, buf, len); if (char_write < 0) @@ -417,7 +436,7 @@ static int dfs_uffs_flush(struct dfs_fd *file) int fd; int result; - fd = (int)(file->data); + fd = (int)(file->fnode->data); result = uffs_flush(fd); if (result < 0) @@ -445,19 +464,19 @@ static int dfs_uffs_seek(struct dfs_fd *file, int result; /* set offset as current offset */ - if (file->type == FT_DIRECTORY) + if (file->fnode->type == FT_DIRECTORY) { - uffs_rewinddir((uffs_DIR *)(file->data)); - result = uffs_seekdir((uffs_DIR *)(file->data), offset / sizeof(struct dirent)); + uffs_rewinddir((uffs_DIR *)(file->fnode->data)); + result = uffs_seekdir((uffs_DIR *)(file->fnode->data), offset / sizeof(struct dirent)); if (result >= 0) { file->pos = offset; return offset; } } - else if (file->type == FT_REGULAR) + else if (file->fnode->type == FT_REGULAR) { - result = uffs_seek((int)(file->data), offset, USEEK_SET); + result = uffs_seek((int)(file->fnode->data), offset, USEEK_SET); if (result >= 0) return offset; } @@ -477,7 +496,7 @@ static int dfs_uffs_getdents( uffs_DIR *dir; struct uffs_dirent *uffs_d; - dir = (uffs_DIR *)(file->data); + dir = (uffs_DIR *)(file->fnode->data); RT_ASSERT(dir != RT_NULL); /* round count, count is always 1 */ @@ -504,8 +523,8 @@ static int dfs_uffs_getdents( return (uffs_result_to_dfs(uffs_get_error())); } - if (file->path[0] == '/' && !(file->path[1] == 0)) - rt_snprintf(file_path, FILE_PATH_MAX, "%s/%s", file->path, uffs_d->d_name); + if (file->fnode->path[0] == '/' && !(file->fnode->path[1] == 0)) + rt_snprintf(file_path, FILE_PATH_MAX, "%s/%s", file->fnode->path, uffs_d->d_name); else rt_strncpy(file_path, uffs_d->d_name, FILE_PATH_MAX); diff --git a/components/dfs/filesystems/uffs/src/inc/uffs/uffs_fd.h b/components/dfs/filesystems/uffs/src/inc/uffs/uffs_fd.h index c5d81590747ad4d5d7c0238b565ba0e0cf97c2fa..4d6d596bc5236b28b9de50865e1c0790cef38ead 100644 --- a/components/dfs/filesystems/uffs/src/inc/uffs/uffs_fd.h +++ b/components/dfs/filesystems/uffs/src/inc/uffs/uffs_fd.h @@ -97,9 +97,9 @@ struct uffs_stat { long st_size; /* total size, in bytes */ int st_blksize; /* blocksize for filesystem I/O */ int st_blocks; /* number of blocks allocated */ - unsigned int st_atime; /* time of last access */ - unsigned int st_mtime; /* time of last modification */ - unsigned int st_ctime; /* time of last status change */ + struct timespec st_atim; /* time of last access */ + struct timespec st_mtim; /* time of last modification */ + struct timespec st_ctim; /* time of last status change */ }; /* POSIX complaint file system APIs */ diff --git a/components/dfs/include/dfs.h b/components/dfs/include/dfs.h index 1158df93cbb6253db2845a60620df142a995de53..5763a9c63007eb52994ef9c09a1fd8b06dd64d2a 100644 --- a/components/dfs/include/dfs.h +++ b/components/dfs/include/dfs.h @@ -31,8 +31,8 @@ /* * skip stdin/stdout/stderr normally */ -#ifndef DFS_FD_OFFSET -#define DFS_FD_OFFSET 3 +#ifndef DFS_STDIO_OFFSET +#define DFS_STDIO_OFFSET 3 #endif #ifndef DFS_PATH_MAX @@ -97,13 +97,26 @@ const char *dfs_subdir(const char *directory, const char *filename); void dfs_lock(void); void dfs_unlock(void); +void dfs_fd_lock(void); +void dfs_fd_unlock(void); + +void dfs_fm_lock(void); +void dfs_fm_unlock(void); + /* FD APIs */ +int fdt_fd_new(struct dfs_fdtable *fdt); +struct dfs_fd *fdt_fd_get(struct dfs_fdtable* fdt, int fd); +void fdt_fd_release(struct dfs_fdtable* fdt, int fd); int fd_new(void); +int fd_associate(struct dfs_fdtable *fdt, int fd, struct dfs_fd *file); struct dfs_fd *fd_get(int fd); -void fd_put(struct dfs_fd *fd); -int fd_is_open(const char *pathname); +int fd_get_fd_index(struct dfs_fd *file); +void fd_release(int fd); + +void fd_init(struct dfs_fd *fd); struct dfs_fdtable *dfs_fdtable_get(void); +struct dfs_fdtable *dfs_fdtable_get_global(void); #ifdef __cplusplus } diff --git a/components/dfs/include/dfs_file.h b/components/dfs/include/dfs_file.h index 2dfacd653e6791736503ebda72a9c49c58538977..8106ace88547764be240c9d64c2fb71c385e01cc 100644 --- a/components/dfs/include/dfs_file.h +++ b/components/dfs/include/dfs_file.h @@ -36,24 +36,36 @@ struct dfs_file_ops /* file descriptor */ #define DFS_FD_MAGIC 0xfdfd -struct dfs_fd + +struct dfs_fnode { - uint16_t magic; /* file descriptor magic number */ uint16_t type; /* Type (regular or socket) */ char *path; /* Name (below mount point) */ + char *fullpath; /* Full path is hash key */ int ref_count; /* Descriptor reference count */ + rt_list_t list; /* The node of fnode hash table */ struct dfs_filesystem *fs; const struct dfs_file_ops *fops; + uint32_t flags; /* self flags, is dir etc.. */ - uint32_t flags; /* Descriptor flags */ size_t size; /* Size in bytes */ - off_t pos; /* Current file position */ - void *data; /* Specific file system data */ }; +struct dfs_fd +{ + uint16_t magic; /* file descriptor magic number */ + uint32_t flags; /* Descriptor flags */ + int ref_count; /* Descriptor reference count */ + off_t pos; /* Current file position */ + struct dfs_fnode *fnode; /* file node struct */ + void *data; /* Specific fd data */ +}; + +void dfs_fnode_mgr_init(void); +int dfs_file_is_open(const char *pathname); int dfs_file_open(struct dfs_fd *fd, const char *path, int flags); int dfs_file_close(struct dfs_fd *fd); int dfs_file_ioctl(struct dfs_fd *fd, int cmd, void *args); @@ -69,7 +81,8 @@ int dfs_file_rename(const char *oldpath, const char *newpath); int dfs_file_ftruncate(struct dfs_fd *fd, off_t length); /* 0x5254 is just a magic number to make these relatively unique ("RT") */ -#define RT_FIOFTRUNCATE 0x52540000U +#define RT_FIOFTRUNCATE 0x52540000U +#define RT_FIOGETADDR 0x52540001U #ifdef __cplusplus } diff --git a/components/dfs/include/dfs_fs.h b/components/dfs/include/dfs_fs.h index a35a513044a2d09ac0295d67a5d9ac480662ff76..8749a793ab1c1ac0eece8115561e7ebba5b72e9a 100644 --- a/components/dfs/include/dfs_fs.h +++ b/components/dfs/include/dfs_fs.h @@ -35,7 +35,7 @@ struct dfs_filesystem_ops int (*unmount) (struct dfs_filesystem *fs); /* make a file system */ - int (*mkfs) (rt_device_t devid); + int (*mkfs) (rt_device_t dev_id, const char *fs_name); int (*statfs) (struct dfs_filesystem *fs, struct statfs *buf); int (*unlink) (struct dfs_filesystem *fs, const char *pathname); diff --git a/components/dfs/src/dfs.c b/components/dfs/src/dfs.c index 7ace0bc1600ac3b02f1cf59600060ceb2b4ccca3..bfe9942f4790f9331d0169c7c272a4b08985e9c3 100644 --- a/components/dfs/src/dfs.c +++ b/components/dfs/src/dfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,20 +14,18 @@ #include #include #include "dfs_private.h" + #ifdef RT_USING_LWP #include #endif -#if defined(RT_USING_DFS_DEVFS) && defined(RT_USING_POSIX) -#include -#endif - /* Global variables */ const struct dfs_filesystem_ops *filesystem_operation_table[DFS_FILESYSTEM_TYPES_MAX]; struct dfs_filesystem filesystem_table[DFS_FILESYSTEMS_MAX]; /* device filesystem lock */ static struct rt_mutex fslock; +static struct rt_mutex fdlock; #ifdef DFS_USING_WORKDIR char working_directory[DFS_PATH_MAX] = {"/"}; @@ -55,6 +53,9 @@ int dfs_init(void) return 0; } + /* init fnode hash table */ + dfs_fnode_mgr_init(); + /* clear filesystem operations table */ memset((void *)filesystem_operation_table, 0, sizeof(filesystem_operation_table)); /* clear filesystem table */ @@ -64,6 +65,7 @@ int dfs_init(void) /* create device filesystem lock */ rt_mutex_init(&fslock, "fslock", RT_IPC_FLAG_FIFO); + rt_mutex_init(&fdlock, "fdlock", RT_IPC_FLAG_FIFO); #ifdef DFS_USING_WORKDIR /* set current working directory */ @@ -108,6 +110,21 @@ void dfs_lock(void) } } +void dfs_fd_lock(void) +{ + rt_err_t result = -RT_EBUSY; + + while (result == -RT_EBUSY) + { + result = rt_mutex_take(&fdlock, RT_WAITING_FOREVER); + } + + if (result != RT_EOK) + { + RT_ASSERT(0); + } +} + /** * this function will lock device file system. * @@ -118,51 +135,95 @@ void dfs_unlock(void) rt_mutex_release(&fslock); } -static int fd_alloc(struct dfs_fdtable *fdt, int startfd) +void dfs_fd_unlock(void) { - int idx; + rt_mutex_release(&fdlock); +} - /* find an empty fd entry */ - for (idx = startfd; idx < (int)fdt->maxfd; idx++) +static int fd_slot_expand(struct dfs_fdtable *fdt, int fd) +{ + int nr; + int index; + struct dfs_fd **fds = NULL; + + if (fd < fdt->maxfd) { - if (fdt->fds[idx] == RT_NULL) - break; - if (fdt->fds[idx]->ref_count == 0) - break; + return fd; + } + if (fd >= DFS_FD_MAX) + { + return -1; } - /* allocate a larger FD container */ - if (idx == fdt->maxfd && fdt->maxfd < DFS_FD_MAX) + nr = ((fd + 4) & ~3); + if (nr > DFS_FD_MAX) + { + nr = DFS_FD_MAX; + } + fds = (struct dfs_fd **)rt_realloc(fdt->fds, nr * sizeof(struct dfs_fd *)); + if (!fds) { - int cnt, index; - struct dfs_fd **fds; + return -1; + } + + /* clean the new allocated fds */ + for (index = fdt->maxfd; index < nr; index++) + { + fds[index] = NULL; + } + fdt->fds = fds; + fdt->maxfd = nr; - /* increase the number of FD with 4 step length */ - cnt = fdt->maxfd + 4; - cnt = cnt > DFS_FD_MAX ? DFS_FD_MAX : cnt; + return fd; +} - fds = (struct dfs_fd **)rt_realloc(fdt->fds, cnt * sizeof(struct dfs_fd *)); - if (fds == NULL) goto __exit; /* return fdt->maxfd */ +static int fd_slot_alloc(struct dfs_fdtable *fdt, int startfd) +{ + int idx; - /* clean the new allocated fds */ - for (index = fdt->maxfd; index < cnt; index ++) + /* find an empty fd slot */ + for (idx = startfd; idx < (int)fdt->maxfd; idx++) + { + if (fdt->fds[idx] == RT_NULL) { - fds[index] = NULL; + return idx; } + } - fdt->fds = fds; - fdt->maxfd = cnt; + idx = fdt->maxfd; + if (idx < startfd) + { + idx = startfd; + } + if (fd_slot_expand(fdt, idx) < 0) + { + return -1; } + return idx; +} + +static int fd_alloc(struct dfs_fdtable *fdt, int startfd) +{ + int idx; + struct dfs_fd *fd = NULL; + + idx = fd_slot_alloc(fdt, startfd); /* allocate 'struct dfs_fd' */ - if (idx < (int)fdt->maxfd && fdt->fds[idx] == RT_NULL) + if (idx < 0) { - fdt->fds[idx] = (struct dfs_fd *)rt_calloc(1, sizeof(struct dfs_fd)); - if (fdt->fds[idx] == RT_NULL) - idx = fdt->maxfd; + return -1; } + fd = (struct dfs_fd *)rt_calloc(1, sizeof(struct dfs_fd)); + if (!fd) + { + return -1; + } + fd->ref_count = 1; + fd->magic = DFS_FD_MAGIC; + fd->fnode = NULL; + fdt->fds[idx] = fd; -__exit: return idx; } @@ -172,34 +233,32 @@ __exit: * * @return -1 on failed or the allocated file descriptor. */ -int fd_new(void) +int fdt_fd_new(struct dfs_fdtable *fdt) { - struct dfs_fd *d; int idx; - struct dfs_fdtable *fdt; - fdt = dfs_fdtable_get(); /* lock filesystem */ - dfs_lock(); + dfs_fd_lock(); /* find an empty fd entry */ - idx = fd_alloc(fdt, 0); + idx = fd_alloc(fdt, DFS_STDIO_OFFSET); /* can't find an empty fd entry */ - if (idx == fdt->maxfd) + if (idx < 0) { - idx = -(1 + DFS_FD_OFFSET); LOG_E("DFS fd new is failed! Could not found an empty fd entry."); - goto __result; } - d = fdt->fds[idx]; - d->ref_count = 1; - d->magic = DFS_FD_MAGIC; + dfs_fd_unlock(); + return idx; +} + +int fd_new(void) +{ + struct dfs_fdtable *fdt = NULL; -__result: - dfs_unlock(); - return idx + DFS_FD_OFFSET; + fdt = dfs_fdtable_get(); + return fdt_fd_new(fdt); } /** @@ -211,130 +270,252 @@ __result: * @return NULL on on this file descriptor or the file descriptor structure * pointer. */ -struct dfs_fd *fd_get(int fd) + +struct dfs_fd *fdt_fd_get(struct dfs_fdtable* fdt, int fd) { struct dfs_fd *d; - struct dfs_fdtable *fdt; - -#if defined(RT_USING_DFS_DEVFS) && defined(RT_USING_POSIX) - if ((0 <= fd) && (fd <= 2)) - fd = libc_stdio_get_console(); -#endif - fdt = dfs_fdtable_get(); - fd = fd - DFS_FD_OFFSET; if (fd < 0 || fd >= (int)fdt->maxfd) + { return NULL; + } - dfs_lock(); + dfs_fd_lock(); d = fdt->fds[fd]; /* check dfs_fd valid or not */ if ((d == NULL) || (d->magic != DFS_FD_MAGIC)) { - dfs_unlock(); + dfs_fd_unlock(); return NULL; } - /* increase the reference count */ - d->ref_count ++; - dfs_unlock(); + dfs_fd_unlock(); return d; } +struct dfs_fd *fd_get(int fd) +{ + struct dfs_fdtable *fdt; + + fdt = dfs_fdtable_get(); + return fdt_fd_get(fdt, fd); +} + /** * @ingroup Fd * * This function will put the file descriptor. */ -void fd_put(struct dfs_fd *fd) +void fdt_fd_release(struct dfs_fdtable* fdt, int fd) { - RT_ASSERT(fd != NULL); + struct dfs_fd *fd_slot = NULL; - dfs_lock(); + RT_ASSERT(fdt != NULL); - fd->ref_count --; + dfs_fd_lock(); - /* clear this fd entry */ - if (fd->ref_count == 0) + if ((fd < 0) || (fd >= fdt->maxfd)) { - int index; - struct dfs_fdtable *fdt; + dfs_fd_unlock(); + return; + } + + fd_slot = fdt->fds[fd]; + if (fd_slot == NULL) + { + dfs_fd_unlock(); + return; + } + fdt->fds[fd] = NULL; - fdt = dfs_fdtable_get(); - for (index = 0; index < (int)fdt->maxfd; index ++) + /* check fd */ + RT_ASSERT(fd_slot->magic == DFS_FD_MAGIC); + + fd_slot->ref_count--; + + /* clear this fd entry */ + if (fd_slot->ref_count == 0) + { + struct dfs_fnode *fnode = fd_slot->fnode; + if (fnode) { - if (fdt->fds[index] == fd) - { - rt_free(fd); - fdt->fds[index] = 0; - break; - } + fnode->ref_count--; } + rt_free(fd_slot); } - dfs_unlock(); + dfs_fd_unlock(); } -/** - * @ingroup Fd - * - * This function will return whether this file has been opend. - * - * @param pathname the file path name. - * - * @return 0 on file has been open successfully, -1 on open failed. - */ -int fd_is_open(const char *pathname) +void fd_release(int fd) { - char *fullpath; - unsigned int index; - struct dfs_filesystem *fs; - struct dfs_fd *fd; struct dfs_fdtable *fdt; fdt = dfs_fdtable_get(); - fullpath = dfs_normalize_path(NULL, pathname); - if (fullpath != NULL) + fdt_fd_release(fdt, fd); +} + +int sys_dup(int oldfd) +{ + int newfd = -1; + struct dfs_fdtable *fdt = NULL; + + dfs_fd_lock(); + /* check old fd */ + fdt = dfs_fdtable_get(); + if ((oldfd < 0) || (oldfd >= fdt->maxfd)) + { + goto exit; + } + if (!fdt->fds[oldfd]) + { + goto exit; + } + /* get a new fd */ + newfd = fd_slot_alloc(fdt, DFS_STDIO_OFFSET); + if (newfd >= 0) + { + fdt->fds[newfd] = fdt->fds[oldfd]; + /* inc ref_count */ + fdt->fds[newfd]->ref_count++; + } +exit: + dfs_fd_unlock(); + return newfd; +} + +int sys_dup2(int oldfd, int newfd) +{ + struct dfs_fdtable *fdt = NULL; + int ret = 0; + int retfd = -1; + + dfs_fd_lock(); + /* check old fd */ + fdt = dfs_fdtable_get(); + if ((oldfd < 0) || (oldfd >= fdt->maxfd)) + { + goto exit; + } + if (!fdt->fds[oldfd]) { - char *mountpath; - fs = dfs_filesystem_lookup(fullpath); - if (fs == NULL) + goto exit; + } + if (newfd < 0) + { + goto exit; + } + if (newfd >= fdt->maxfd) + { + newfd = fd_slot_expand(fdt, newfd); + if (newfd < 0) { - /* can't find mounted file system */ - rt_free(fullpath); + goto exit; + } + } + if (fdt->fds[newfd] == fdt->fds[oldfd]) + { + /* ok, return newfd */ + retfd = newfd; + goto exit; + } - return -1; + if (fdt->fds[newfd]) + { + ret = dfs_file_close(fdt->fds[newfd]); + if (ret < 0) + { + goto exit; } + fd_release(newfd); + } - /* get file path name under mounted file system */ - if (fs->path[0] == '/' && fs->path[1] == '\0') - mountpath = fullpath; - else - mountpath = fullpath + strlen(fs->path); + fdt->fds[newfd] = fdt->fds[oldfd]; + /* inc ref_count */ + fdt->fds[newfd]->ref_count++; + retfd = newfd; +exit: + dfs_fd_unlock(); + return retfd; +} - dfs_lock(); +static int fd_get_fd_index_form_fdt(struct dfs_fdtable *fdt, struct dfs_fd *file) +{ + int fd = -1; - for (index = 0; index < fdt->maxfd; index++) - { - fd = fdt->fds[index]; - if (fd == NULL || fd->fops == NULL || fd->path == NULL) continue; + if (file == RT_NULL) + { + return -1; + } - if (fd->fs == fs && strcmp(fd->path, mountpath) == 0) - { - /* found file in file descriptor table */ - rt_free(fullpath); - dfs_unlock(); + dfs_fd_lock(); - return 0; - } + for(int index = 0; index < (int)fdt->maxfd; index++) + { + if(fdt->fds[index] == file) + { + fd = index; + break; } - dfs_unlock(); + } + + dfs_fd_unlock(); + + return fd; +} + +int fd_get_fd_index(struct dfs_fd *file) +{ + struct dfs_fdtable *fdt; + + fdt = dfs_fdtable_get(); + return fd_get_fd_index_form_fdt(fdt, file); +} + +int fd_associate(struct dfs_fdtable *fdt, int fd, struct dfs_fd *file) +{ + int retfd = -1; - rt_free(fullpath); + if (!file) + { + return retfd; + } + if (!fdt) + { + return retfd; + } + + dfs_fd_lock(); + /* check old fd */ + if ((fd < 0) || (fd >= fdt->maxfd)) + { + goto exit; + } + + if (fdt->fds[fd]) + { + goto exit; } + /* inc ref_count */ + file->ref_count++; + fdt->fds[fd] = file; + retfd = fd; +exit: + dfs_fd_unlock(); + return retfd; +} - return -1; +void fd_init(struct dfs_fd *fd) +{ + if (fd) + { + fd->magic = DFS_FD_MAGIC; + fd->ref_count = 1; + fd->pos = 0; + fd->fnode = NULL; + fd->data = NULL; + } } /** @@ -355,7 +536,7 @@ const char *dfs_subdir(const char *directory, const char *filename) dir = filename + strlen(directory); if ((*dir != '/') && (dir != filename)) { - dir --; + dir--; } return dir; @@ -381,7 +562,13 @@ char *dfs_normalize_path(const char *directory, const char *filename) #ifdef DFS_USING_WORKDIR if (directory == NULL) /* shall use working directory */ + { +#ifdef RT_USING_LWP + directory = lwp_getcwd(); +#else directory = &working_directory[0]; +#endif + } #else if ((directory == NULL) && (filename[0] != '/')) { @@ -420,14 +607,14 @@ char *dfs_normalize_path(const char *directory, const char *filename) if (c == '.') { - if (!src[1]) src ++; /* '.' and ends */ + if (!src[1]) src++; /* '.' and ends */ else if (src[1] == '/') { /* './' case */ src += 2; while ((*src == '/') && (*src != '\0')) - src ++; + src++; continue; } else if (src[1] == '.') @@ -444,7 +631,7 @@ char *dfs_normalize_path(const char *directory, const char *filename) src += 3; while ((*src == '/') && (*src != '\0')) - src ++; + src++; goto up_one; } } @@ -452,15 +639,15 @@ char *dfs_normalize_path(const char *directory, const char *filename) /* copy up the next '/' and erase all '/' */ while ((c = *src++) != '\0' && c != '/') - *dst ++ = c; + *dst++ = c; if (c == '/') { - *dst ++ = '/'; + *dst++ = '/'; while (c == '/') c = *src++; - src --; + src--; } else if (!c) break; @@ -468,20 +655,20 @@ char *dfs_normalize_path(const char *directory, const char *filename) continue; up_one: - dst --; + dst--; if (dst < dst0) { rt_free(fullpath); return NULL; } while (dst0 < dst && dst[-1] != '/') - dst --; + dst--; } *dst = '\0'; /* remove '/' in the end of path if exist */ - dst --; + dst--; if ((dst != fullpath) && (*dst == '/')) *dst = '\0'; @@ -517,6 +704,27 @@ struct dfs_fdtable *dfs_fdtable_get(void) return fdt; } +#ifdef RT_USING_LWP +struct dfs_fdtable *dfs_fdtable_get_pid(int pid) +{ + struct rt_lwp *lwp = RT_NULL; + struct dfs_fdtable *fdt = RT_NULL; + + lwp = lwp_from_pid(pid); + if (lwp) + { + fdt = &lwp->fdt; + } + + return fdt; +} +#endif + +struct dfs_fdtable *dfs_fdtable_get_global(void) +{ + return &_fdtab; +} + #ifdef RT_USING_FINSH #include int list_fd(void) @@ -531,24 +739,24 @@ int list_fd(void) rt_kprintf("fd type ref magic path\n"); rt_kprintf("-- ------ --- ----- ------\n"); - for (index = 0; index < (int)fd_table->maxfd; index ++) + for (index = 0; index < (int)fd_table->maxfd; index++) { struct dfs_fd *fd = fd_table->fds[index]; - if (fd && fd->fops) + if (fd && fd->fnode->fops) { - rt_kprintf("%2d ", index + DFS_FD_OFFSET); - if (fd->type == FT_DIRECTORY) rt_kprintf("%-7.7s ", "dir"); - else if (fd->type == FT_REGULAR) rt_kprintf("%-7.7s ", "file"); - else if (fd->type == FT_SOCKET) rt_kprintf("%-7.7s ", "socket"); - else if (fd->type == FT_USER) rt_kprintf("%-7.7s ", "user"); - else if (fd->type == FT_DEVICE) rt_kprintf("%-7.7s ", "device"); + rt_kprintf("%2d ", index); + if (fd->fnode->type == FT_DIRECTORY) rt_kprintf("%-7.7s ", "dir"); + else if (fd->fnode->type == FT_REGULAR) rt_kprintf("%-7.7s ", "file"); + else if (fd->fnode->type == FT_SOCKET) rt_kprintf("%-7.7s ", "socket"); + else if (fd->fnode->type == FT_USER) rt_kprintf("%-7.7s ", "user"); + else if (fd->fnode->type == FT_DEVICE) rt_kprintf("%-7.7s ", "device"); else rt_kprintf("%-8.8s ", "unknown"); - rt_kprintf("%3d ", fd->ref_count); + rt_kprintf("%3d ", fd->fnode->ref_count); rt_kprintf("%04x ", fd->magic); - if (fd->path) + if (fd->fnode->path) { - rt_kprintf("%s\n", fd->path); + rt_kprintf("%s\n", fd->fnode->path); } else { @@ -561,6 +769,194 @@ int list_fd(void) return 0; } MSH_CMD_EXPORT(list_fd, list file descriptor); + +#ifdef RT_USING_LWP +static int lsofp(int pid) +{ + int index; + struct dfs_fdtable *fd_table = RT_NULL; + + if (pid == (-1)) + { + fd_table = dfs_fdtable_get(); + if (!fd_table) return -1; + } + else + { + fd_table = dfs_fdtable_get_pid(pid); + if (!fd_table) + { + rt_kprintf("PID %s is not a applet(lwp)\n", pid); + return -1; + } + } + + rt_kprintf("--- -- ------ ------ ----- ---------- ---------- ---------- ------\n"); + + rt_enter_critical(); + for (index = 0; index < (int)fd_table->maxfd; index++) + { + struct dfs_fd *fd = fd_table->fds[index]; + + if (fd && fd->fnode->fops) + { + if(pid == (-1)) + { + rt_kprintf(" K "); + } + else + { + rt_kprintf("%3d ", pid); + } + + rt_kprintf("%2d ", index); + if (fd->fnode->type == FT_DIRECTORY) rt_kprintf("%-7.7s ", "dir"); + else if (fd->fnode->type == FT_REGULAR) rt_kprintf("%-7.7s ", "file"); + else if (fd->fnode->type == FT_SOCKET) rt_kprintf("%-7.7s ", "socket"); + else if (fd->fnode->type == FT_USER) rt_kprintf("%-7.7s ", "user"); + else if (fd->fnode->type == FT_DEVICE) rt_kprintf("%-7.7s ", "device"); + else rt_kprintf("%-8.8s ", "unknown"); + rt_kprintf("%6d ", fd->fnode->ref_count); + rt_kprintf("%04x 0x%.8x ", fd->magic, (int)(size_t)fd->fnode); + + if(fd->fnode == RT_NULL) + { + rt_kprintf("0x%.8x 0x%.8x ", (int)0x00000000, (int)(size_t)fd); + } + else + { + rt_kprintf("0x%.8x 0x%.8x ", (int)(size_t)(fd->fnode->data), (int)(size_t)fd); + } + + if (fd->fnode->path) + { + rt_kprintf("%s \n", fd->fnode->path); + } + else + { + rt_kprintf("\n"); + } + } + } + rt_exit_critical(); + + return 0; +} + +int lsof(int argc, char *argv[]) +{ + rt_kprintf("PID fd type fd-ref magic fnode fnode/data addr path \n"); + + if (argc == 1) + { + struct rt_list_node *node, *list; + struct lwp_avl_struct *pids = lwp_get_pid_ary(); + + lsofp(-1); + + for (int index = 0; index < RT_LWP_MAX_NR; index++) + { + struct rt_lwp *lwp = (struct rt_lwp *)pids[index].data; + + if (lwp) + { + list = &lwp->t_grp; + for (node = list->next; node != list; node = node->next) + { + lsofp(lwp_to_pid(lwp)); + } + } + } + } + else if (argc == 3) + { + if (argv[1][0] == '-' && argv[1][1] == 'p') + { + int pid = atoi(argv[2]); + lsofp(pid); + } + } + + return 0; +} +MSH_CMD_EXPORT(lsof, list open files); +#endif /* RT_USING_LWP */ + +/* + * If no argument is specified, display the mount history; + * If there are 3 arguments, mount the filesystem. + * The order of the arguments is: + * argv[1]: device name + * argv[2]: mountpoint path + * argv[3]: filesystem type + */ +int mount(int argc, char *argv[]) +{ + if (argc == 1) /* display the mount history */ + { + struct dfs_filesystem *iter; + + rt_kprintf("filesystem device mountpoint\n"); + rt_kprintf("---------- ------ ----------\n"); + for (iter = &filesystem_table[0]; + iter < &filesystem_table[DFS_FILESYSTEMS_MAX]; iter++) + { + if ((iter != NULL) && (iter->path != NULL)) + { + rt_kprintf("%-10s %-6s %-s\n", + iter->ops->name, iter->dev_id->parent.name, iter->path); + } + } + return 0; + } + else if (argc == 4) + { /* mount a filesystem to the specified directory */ + char *device = argv[1]; + char *path = argv[2]; + char *fstype = argv[3]; + + rt_kprintf("mount device %s(%s) onto %s ... ", device, fstype, path); + if (dfs_mount(device, path, fstype, 0, 0) == 0) + { + rt_kprintf("succeed!\n"); + return 0; + } + else + { + rt_kprintf("failed!\n"); + return -1; + } + } + else + { + rt_kprintf("Usage: mount .\n"); + return -1; + } +} +MSH_CMD_EXPORT(mount, mount); + +/* unmount the filesystem from the specified mountpoint */ +int unmount(int argc, char *argv[]) +{ + if (argc != 2) + { + rt_kprintf("Usage: unmount .\n"); + return -1; + } + + char *path = argv[1]; + + rt_kprintf("unmount %s ... ", path); + if (dfs_unmount(path) < 0) + { + rt_kprintf("failed!\n"); + return -1; + } else { + rt_kprintf("succeed!\n"); + return 0; + } +} +MSH_CMD_EXPORT(unmount, unmount the mountpoint); + #endif /*@}*/ - diff --git a/components/dfs/src/dfs_file.c b/components/dfs/src/dfs_file.c index fd205f2f3a10914d05a138e7fc83d3e0a46df70d..ccfe5429c581b4556f1a4dcf8e781b01e6421be2 100644 --- a/components/dfs/src/dfs_file.c +++ b/components/dfs/src/dfs_file.c @@ -15,12 +15,111 @@ #include #include +#define DFS_FNODE_HASH_NR 128 + +struct dfs_fnode_mgr +{ + struct rt_mutex lock; + rt_list_t head[DFS_FNODE_HASH_NR]; +}; + +static struct dfs_fnode_mgr dfs_fm; + +void dfs_fm_lock(void) +{ + rt_mutex_take(&dfs_fm.lock, RT_WAITING_FOREVER); +} + +void dfs_fm_unlock(void) +{ + rt_mutex_release(&dfs_fm.lock); +} + +void dfs_fnode_mgr_init(void) +{ + int i = 0; + + rt_mutex_init(&dfs_fm.lock, "dfs_mgr", RT_IPC_FLAG_PRIO); + for (i = 0; i < DFS_FNODE_HASH_NR; i++) + { + rt_list_init(&dfs_fm.head[i]); + } +} + +/* BKDR Hash Function */ +static unsigned int bkdr_hash(const char *str) +{ + unsigned int seed = 131; // 31 131 1313 13131 131313 etc.. + unsigned int hash = 0; + + while (*str) + { + hash = hash * seed + (*str++); + } + + return (hash % DFS_FNODE_HASH_NR); +} + +static struct dfs_fnode *dfs_fnode_find(const char *path, rt_list_t **hash_head) +{ + struct dfs_fnode *fnode = NULL; + int hash = bkdr_hash(path); + rt_list_t *hh; + + hh = dfs_fm.head[hash].next; + + if (hash_head) + { + *hash_head = &dfs_fm.head[hash]; + } + + while (hh != &dfs_fm.head[hash]) + { + fnode = rt_container_of(hh, struct dfs_fnode, list); + if (rt_strcmp(path, fnode->fullpath) == 0) + { + /* found */ + return fnode; + } + hh = hh->next; + } + return NULL; +} + /** * @addtogroup FileApi */ /*@{*/ +/** + * This function will return whether this file has been opend. + * + * @param pathname the file path name. + * + * @return 0 on file has been open successfully, -1 on open failed. + */ +int dfs_file_is_open(const char *pathname) +{ + char *fullpath = NULL; + struct dfs_fnode *fnode = NULL; + int ret = 0; + + fullpath = dfs_normalize_path(NULL, pathname); + + dfs_fm_lock(); + fnode = dfs_fnode_find(fullpath, NULL); + if (fnode) + { + ret = 1; + } + dfs_fm_unlock(); + + rt_free(fullpath); + return ret; +} + + /** * this function will open a file which specified by path with specified flags. * @@ -35,6 +134,8 @@ int dfs_file_open(struct dfs_fd *fd, const char *path, int flags) struct dfs_filesystem *fs; char *fullpath; int result; + struct dfs_fnode *fnode = NULL; + rt_list_t *hash_head; /* parameter check */ if (fd == NULL) @@ -49,56 +150,101 @@ int dfs_file_open(struct dfs_fd *fd, const char *path, int flags) LOG_D("open file:%s", fullpath); - /* find filesystem */ - fs = dfs_filesystem_lookup(fullpath); - if (fs == NULL) + dfs_fm_lock(); + /* fnode find */ + fnode = dfs_fnode_find(fullpath, &hash_head); + if (fnode) { + fnode->ref_count++; + fd->pos = 0; + fd->fnode = fnode; + dfs_fm_unlock(); rt_free(fullpath); /* release path */ - - return -ENOENT; } + else + { + /* find filesystem */ + fs = dfs_filesystem_lookup(fullpath); + if (fs == NULL) + { + dfs_fm_unlock(); + rt_free(fullpath); /* release path */ + return -ENOENT; + } - LOG_D("open in filesystem:%s", fs->ops->name); - fd->fs = fs; /* set file system */ - fd->fops = fs->ops->fops; /* set file ops */ + fnode = rt_calloc(1, sizeof(struct dfs_fnode)); + if (!fnode) + { + dfs_fm_unlock(); + rt_free(fullpath); /* release path */ + return -ENOMEM; + } + fnode->ref_count = 1; - /* initialize the fd item */ - fd->type = FT_REGULAR; - fd->flags = flags; - fd->size = 0; - fd->pos = 0; - fd->data = fs; + LOG_D("open in filesystem:%s", fs->ops->name); + fnode->fs = fs; /* set file system */ + fnode->fops = fs->ops->fops; /* set file ops */ - if (!(fs->ops->flags & DFS_FS_FLAG_FULLPATH)) - { - if (dfs_subdir(fs->path, fullpath) == NULL) - fd->path = rt_strdup("/"); + /* initialize the fd item */ + fnode->type = FT_REGULAR; + fnode->flags = 0; + + if (!(fs->ops->flags & DFS_FS_FLAG_FULLPATH)) + { + if (dfs_subdir(fs->path, fullpath) == NULL) + fnode->path = rt_strdup("/"); + else + fnode->path = rt_strdup(dfs_subdir(fs->path, fullpath)); + LOG_D("Actual file path: %s", fnode->path); + } else - fd->path = rt_strdup(dfs_subdir(fs->path, fullpath)); - rt_free(fullpath); - LOG_D("Actual file path: %s", fd->path); - } - else - { - fd->path = fullpath; - } + { + fnode->path = fullpath; + } + fnode->fullpath = fullpath; - /* specific file system open routine */ - if (fd->fops->open == NULL) - { - /* clear fd */ - rt_free(fd->path); - fd->path = NULL; + /* specific file system open routine */ + if (fnode->fops->open == NULL) + { + dfs_fm_unlock(); + /* clear fd */ + if (fnode->path != fnode->fullpath) + { + rt_free(fnode->fullpath); + } + rt_free(fnode->path); + rt_free(fnode); - return -ENOSYS; + return -ENOSYS; + } + + fd->pos = 0; + fd->fnode = fnode; + + /* insert fnode to hash */ + rt_list_insert_after(hash_head, &fnode->list); } - if ((result = fd->fops->open(fd)) < 0) + fd->flags = flags; + + if ((result = fnode->fops->open(fd)) < 0) { - /* clear fd */ - rt_free(fd->path); - fd->path = NULL; + fnode->ref_count--; + if (fnode->ref_count == 0) + { + /* remove from hash */ + rt_list_remove(&fnode->list); + /* clear fd */ + if (fnode->path != fnode->fullpath) + { + rt_free(fnode->fullpath); + } + rt_free(fnode->path); + fd->fnode = NULL; + rt_free(fnode); + } + dfs_fm_unlock(); LOG_D("%s open failed", fullpath); return result; @@ -107,9 +253,10 @@ int dfs_file_open(struct dfs_fd *fd, const char *path, int flags) fd->flags |= DFS_F_OPEN; if (flags & O_DIRECTORY) { - fd->type = FT_DIRECTORY; + fd->fnode->type = FT_DIRECTORY; fd->flags |= DFS_F_DIRECTORY; } + dfs_fm_unlock(); LOG_D("open successful"); return 0; @@ -124,20 +271,52 @@ int dfs_file_open(struct dfs_fd *fd, const char *path, int flags) */ int dfs_file_close(struct dfs_fd *fd) { + struct dfs_fnode *fnode = NULL; int result = 0; if (fd == NULL) + { return -ENXIO; + } - if (fd->fops->close != NULL) - result = fd->fops->close(fd); + if (fd->ref_count == 1) + { + dfs_fm_lock(); + fnode = fd->fnode; - /* close fd error, return */ - if (result < 0) - return result; + if (fnode->ref_count <= 0) + { + dfs_fm_unlock(); + return -ENXIO; + } + + if (fnode->fops->close != NULL) + { + result = fnode->fops->close(fd); + } - rt_free(fd->path); - fd->path = NULL; + /* close fd error, return */ + if (result < 0) + { + dfs_fm_unlock(); + return result; + } + + if (fnode->ref_count == 1) + { + /* remove from hash */ + rt_list_remove(&fnode->list); + fd->fnode = NULL; + + if (fnode->path != fnode->fullpath) + { + rt_free(fnode->fullpath); + } + rt_free(fnode->path); + rt_free(fnode); + } + dfs_fm_unlock(); + } return result; } @@ -154,10 +333,12 @@ int dfs_file_close(struct dfs_fd *fd) int dfs_file_ioctl(struct dfs_fd *fd, int cmd, void *args) { if (fd == NULL) + { return -EINVAL; + } /* regular file system fd */ - if (fd->type == FT_REGULAR || fd->type == FT_DEVICE) + if (fd->fnode->type == FT_REGULAR || fd->fnode->type == FT_DEVICE) { switch (cmd) { @@ -176,8 +357,10 @@ int dfs_file_ioctl(struct dfs_fd *fd, int cmd, void *args) } } - if (fd->fops->ioctl != NULL) - return fd->fops->ioctl(fd, cmd, args); + if (fd->fnode->fops->ioctl != NULL) + { + return fd->fnode->fops->ioctl(fd, cmd, args); + } return -ENOSYS; } @@ -197,13 +380,19 @@ int dfs_file_read(struct dfs_fd *fd, void *buf, size_t len) int result = 0; if (fd == NULL) + { return -EINVAL; + } - if (fd->fops->read == NULL) + if (fd->fnode->fops->read == NULL) + { return -ENOSYS; + } - if ((result = fd->fops->read(fd, buf, len)) < 0) + if ((result = fd->fnode->fops->read(fd, buf, len)) < 0) + { fd->flags |= DFS_F_EOF; + } return result; } @@ -220,11 +409,20 @@ int dfs_file_read(struct dfs_fd *fd, void *buf, size_t len) int dfs_file_getdents(struct dfs_fd *fd, struct dirent *dirp, size_t nbytes) { /* parameter check */ - if (fd == NULL || fd->type != FT_DIRECTORY) + if (fd == NULL) + { + return -EINVAL; + } + + if (fd->fnode->type != FT_DIRECTORY) + { return -EINVAL; + } - if (fd->fops->getdents != NULL) - return fd->fops->getdents(fd, dirp, nbytes); + if (fd->fnode->fops->getdents != NULL) + { + return fd->fnode->fops->getdents(fd, dirp, nbytes); + } return -ENOSYS; } @@ -249,17 +447,17 @@ int dfs_file_unlink(const char *path) return -EINVAL; } - /* get filesystem */ - if ((fs = dfs_filesystem_lookup(fullpath)) == NULL) + /* Check whether file is already open */ + if (dfs_file_is_open(fullpath)) { - result = -ENOENT; + result = -EBUSY; goto __exit; } - /* Check whether file is already open */ - if (fd_is_open(fullpath) == 0) + /* get filesystem */ + if ((fs = dfs_filesystem_lookup(fullpath)) == NULL) { - result = -EBUSY; + result = -ENOENT; goto __exit; } @@ -294,12 +492,16 @@ __exit: int dfs_file_write(struct dfs_fd *fd, const void *buf, size_t len) { if (fd == NULL) + { return -EINVAL; + } - if (fd->fops->write == NULL) + if (fd->fnode->fops->write == NULL) + { return -ENOSYS; + } - return fd->fops->write(fd, buf, len); + return fd->fnode->fops->write(fd, buf, len); } /** @@ -314,10 +516,10 @@ int dfs_file_flush(struct dfs_fd *fd) if (fd == NULL) return -EINVAL; - if (fd->fops->flush == NULL) + if (fd->fnode->fops->flush == NULL) return -ENOSYS; - return fd->fops->flush(fd); + return fd->fnode->fops->flush(fd); } /** @@ -335,10 +537,10 @@ int dfs_file_lseek(struct dfs_fd *fd, off_t offset) if (fd == NULL) return -EINVAL; - if (fd->fops->lseek == NULL) + if (fd->fnode->fops->lseek == NULL) return -ENOSYS; - result = fd->fops->lseek(fd, offset); + result = fd->fnode->fops->lseek(fd, offset); /* update current position */ if (result >= 0) @@ -425,11 +627,10 @@ int dfs_file_stat(const char *path, struct stat *buf) */ int dfs_file_rename(const char *oldpath, const char *newpath) { - int result; - struct dfs_filesystem *oldfs, *newfs; - char *oldfullpath, *newfullpath; + int result = RT_EOK; + struct dfs_filesystem *oldfs = NULL, *newfs = NULL; + char *oldfullpath = NULL, *newfullpath = NULL; - result = RT_EOK; newfullpath = NULL; oldfullpath = NULL; @@ -440,6 +641,12 @@ int dfs_file_rename(const char *oldpath, const char *newpath) goto __exit; } + if (dfs_file_is_open((const char *)oldfullpath)) + { + result = -EBUSY; + goto __exit; + } + newfullpath = dfs_normalize_path(NULL, newpath); if (newfullpath == NULL) { @@ -473,8 +680,14 @@ int dfs_file_rename(const char *oldpath, const char *newpath) } __exit: - rt_free(oldfullpath); - rt_free(newfullpath); + if (oldfullpath) + { + rt_free(oldfullpath); + } + if (newfullpath) + { + rt_free(newfullpath); + } /* not at same file system, return EXDEV */ return result; @@ -494,17 +707,17 @@ int dfs_file_ftruncate(struct dfs_fd *fd, off_t length) int result; /* fd is null or not a regular file system fd, or length is invalid */ - if (fd == NULL || fd->type != FT_REGULAR || length < 0) + if (fd == NULL || fd->fnode->type != FT_REGULAR || length < 0) return -EINVAL; - if (fd->fops->ioctl == NULL) + if (fd->fnode->fops->ioctl == NULL) return -ENOSYS; - result = fd->fops->ioctl(fd, RT_FIOFTRUNCATE, (void*)&length); + result = fd->fnode->fops->ioctl(fd, RT_FIOFTRUNCATE, (void*)&length); /* update current size */ if (result == 0) - fd->size = length; + fd->fnode->size = length; return result; } @@ -512,10 +725,10 @@ int dfs_file_ftruncate(struct dfs_fd *fd, off_t length) #ifdef RT_USING_FINSH #include -static struct dfs_fd fd; -static struct dirent dirent; void ls(const char *pathname) { + struct dfs_fd fd; + struct dirent dirent; struct stat stat; int length; char *fullpath, *path; @@ -537,6 +750,7 @@ void ls(const char *pathname) path = (char *)pathname; } + fd_init(&fd); /* list directory */ if (dfs_file_open(&fd, path, O_DIRECTORY) == 0) { @@ -570,8 +784,7 @@ void ls(const char *pathname) rt_kprintf("BAD file: %s\n", dirent.d_name); rt_free(fullpath); } - } - while (length > 0); + } while (length > 0); dfs_file_close(&fd); } @@ -595,9 +808,11 @@ FINSH_FUNCTION_EXPORT(rm, remove files or directories); void cat(const char *filename) { - uint32_t length; + struct dfs_fd fd; + uint32_t length = 0; char buffer[81]; + fd_init(&fd); if (dfs_file_open(&fd, filename, O_RDONLY) < 0) { rt_kprintf("Open %s failed\n", filename); @@ -607,14 +822,13 @@ void cat(const char *filename) do { - memset(buffer, 0, sizeof(buffer)); length = dfs_file_read(&fd, buffer, sizeof(buffer) - 1); if (length > 0) { + buffer[length] = '\0'; rt_kprintf("%s", buffer); } - } - while (length > 0); + } while (length > 0); dfs_file_close(&fd); } @@ -623,6 +837,7 @@ FINSH_FUNCTION_EXPORT(cat, print file); #define BUF_SZ 4096 static void copyfile(const char *src, const char *dst) { + struct dfs_fd fd; struct dfs_fd src_fd; rt_uint8_t *block_ptr; rt_int32_t read_bytes; @@ -635,6 +850,7 @@ static void copyfile(const char *src, const char *dst) return; } + fd_init(&src_fd); if (dfs_file_open(&src_fd, src, O_RDONLY) < 0) { rt_free(block_ptr); @@ -642,6 +858,7 @@ static void copyfile(const char *src, const char *dst) return; } + fd_init(&fd); if (dfs_file_open(&fd, dst, O_WRONLY | O_CREAT) < 0) { rt_free(block_ptr); @@ -667,8 +884,7 @@ static void copyfile(const char *src, const char *dst) break; } } - } - while (read_bytes > 0); + } while (read_bytes > 0); dfs_file_close(&src_fd); dfs_file_close(&fd); @@ -733,8 +949,7 @@ static void copydir(const char *src, const char *dst) rt_free(src_entry_full); rt_free(dst_entry_full); } - } - while (length > 0); + } while (length > 0); dfs_file_close(&cpfd); } diff --git a/components/dfs/src/dfs_fs.c b/components/dfs/src/dfs_fs.c index c21b914727cda5eb811069225bad2e13d2d0210a..6013cc55b03d607379e9c0d6a68b800afebf4859 100644 --- a/components/dfs/src/dfs_fs.c +++ b/components/dfs/src/dfs_fs.c @@ -241,7 +241,7 @@ int dfs_mount(const char *device_name, for (ops = &filesystem_operation_table[0]; ops < &filesystem_operation_table[DFS_FILESYSTEM_TYPES_MAX]; ops++) - if ((*ops != NULL) && (strcmp((*ops)->name, filesystemtype) == 0)) + if ((*ops != NULL) && (strncmp((*ops)->name, filesystemtype, strlen((*ops)->name)) == 0)) break; dfs_unlock(); @@ -273,6 +273,7 @@ int dfs_mount(const char *device_name, { struct dfs_fd fd; + fd_init(&fd); if (dfs_file_open(&fd, fullpath, O_RDONLY | O_DIRECTORY) < 0) { rt_free(fullpath); @@ -312,6 +313,9 @@ int dfs_mount(const char *device_name, fs->path = fullpath; fs->ops = *ops; fs->dev_id = dev_id; + /* For UFS, record the real filesystem name */ + fs->data = (void *) filesystemtype; + /* release filesystem_table lock */ dfs_unlock(); @@ -447,7 +451,8 @@ int dfs_mkfs(const char *fs_name, const char *device_name) for (index = 0; index < DFS_FILESYSTEM_TYPES_MAX; index ++) { if (filesystem_operation_table[index] != NULL && - strcmp(filesystem_operation_table[index]->name, fs_name) == 0) + strncmp(filesystem_operation_table[index]->name, fs_name, + strlen(filesystem_operation_table[index]->name)) == 0) break; } dfs_unlock(); @@ -463,7 +468,7 @@ int dfs_mkfs(const char *fs_name, const char *device_name) return -1; } - return ops->mkfs(dev_id); + return ops->mkfs(dev_id, fs_name); } LOG_E("File system (%s) was not found.", fs_name); @@ -490,6 +495,7 @@ int dfs_statfs(const char *path, struct statfs *buffer) return fs->ops->statfs(fs, buffer); } + rt_set_errno(-ENOSYS); return -1; } @@ -625,7 +631,10 @@ int df(const char *path) result = dfs_statfs(path ? path : NULL, &buffer); if (result != 0) { - rt_kprintf("dfs_statfs failed.\n"); + if (rt_get_errno() == -ENOSYS) + rt_kprintf("The function is not implemented.\n"); + else + rt_kprintf("statfs failed: errno=%d.\n", rt_get_errno()); return -1; } diff --git a/components/dfs/src/dfs_posix.c b/components/dfs/src/dfs_posix.c index fc603df4379bbf016188b5f04866e0174869bacd..96d8ecc3c9ef73a3cb63c446b1fb86f6d2d7181e 100644 --- a/components/dfs/src/dfs_posix.c +++ b/components/dfs/src/dfs_posix.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,12 +7,17 @@ * Date Author Notes * 2009-05-27 Yi.qiu The first version * 2018-02-07 Bernard Change the 3rd parameter of open/fcntl/ioctl to '...' + * 2021-08-26 linzhenxing add setcwd and modify getcwd\chdir */ #include #include #include "dfs_private.h" +#ifdef RT_USING_LWP +#include +#endif + /** * @addtogroup FsPosixApi */ @@ -47,17 +52,13 @@ int open(const char *file, int flags, ...) if (result < 0) { /* release the ref-count of fd */ - fd_put(d); - fd_put(d); + fd_release(fd); rt_set_errno(result); return -1; } - /* release the ref-count of fd */ - fd_put(d); - return fd; } RTM_EXPORT(open); @@ -84,7 +85,6 @@ int close(int fd) } result = dfs_file_close(d); - fd_put(d); if (result < 0) { @@ -93,7 +93,7 @@ int close(int fd) return -1; } - fd_put(d); + fd_release(fd); return 0; } @@ -131,15 +131,11 @@ int read(int fd, void *buf, size_t len) result = dfs_file_read(d, buf, len); if (result < 0) { - fd_put(d); rt_set_errno(result); return -1; } - /* release the ref-count of fd */ - fd_put(d); - return result; } RTM_EXPORT(read); @@ -175,15 +171,11 @@ int write(int fd, const void *buf, size_t len) result = dfs_file_write(d, buf, len); if (result < 0) { - fd_put(d); rt_set_errno(result); return -1; } - /* release the ref-count of fd */ - fd_put(d); - return result; } RTM_EXPORT(write); @@ -221,11 +213,10 @@ off_t lseek(int fd, off_t offset, int whence) break; case SEEK_END: - offset += d->size; + offset += d->fnode->size; break; default: - fd_put(d); rt_set_errno(-EINVAL); return -1; @@ -233,7 +224,6 @@ off_t lseek(int fd, off_t offset, int whence) if (offset < 0) { - fd_put(d); rt_set_errno(-EINVAL); return -1; @@ -241,15 +231,11 @@ off_t lseek(int fd, off_t offset, int whence) result = dfs_file_lseek(d, offset); if (result < 0) { - fd_put(d); rt_set_errno(result); return -1; } - /* release the ref-count of fd */ - fd_put(d); - return offset; } RTM_EXPORT(lseek); @@ -356,17 +342,15 @@ int fstat(int fildes, struct stat *buf) buf->st_mode = S_IFREG | S_IRUSR | S_IRGRP | S_IROTH | S_IWUSR | S_IWGRP | S_IWOTH; - if (d->type == FT_DIRECTORY) + if (d->fnode->type == FT_DIRECTORY) { buf->st_mode &= ~S_IFREG; buf->st_mode |= S_IFDIR | S_IXUSR | S_IXGRP | S_IXOTH; } - buf->st_size = d->size; + buf->st_size = d->fnode->size; buf->st_mtime = 0; - fd_put(d); - return RT_EOK; } RTM_EXPORT(fstat); @@ -397,7 +381,6 @@ int fsync(int fildes) ret = dfs_file_flush(d); - fd_put(d); return ret; } RTM_EXPORT(fsync); @@ -431,7 +414,6 @@ int fcntl(int fildes, int cmd, ...) va_end(ap); ret = dfs_file_ioctl(d, cmd, arg); - fd_put(d); } else ret = -EBADF; @@ -496,7 +478,6 @@ int ftruncate(int fd, off_t length) if (length < 0) { - fd_put(d); rt_set_errno(-EINVAL); return -1; @@ -504,15 +485,11 @@ int ftruncate(int fd, off_t length) result = dfs_file_ftruncate(d, length); if (result < 0) { - fd_put(d); rt_set_errno(result); return -1; } - /* release the ref-count of fd */ - fd_put(d); - return 0; } RTM_EXPORT(ftruncate); @@ -570,16 +547,14 @@ int mkdir(const char *path, mode_t mode) if (result < 0) { - fd_put(d); - fd_put(d); + fd_release(fd); rt_set_errno(result); return -1; } dfs_file_close(d); - fd_put(d); - fd_put(d); + fd_release(fd); return 0; } @@ -646,7 +621,7 @@ DIR *opendir(const char *name) if (t == NULL) { dfs_file_close(d); - fd_put(d); + fd_release(fd); } else { @@ -654,14 +629,12 @@ DIR *opendir(const char *name) t->fd = fd; } - fd_put(d); return t; } /* open failed */ - fd_put(d); - fd_put(d); + fd_release(fd); rt_set_errno(result); return NULL; @@ -704,7 +677,6 @@ struct dirent *readdir(DIR *d) sizeof(d->buf) - 1); if (result <= 0) { - fd_put(fd); rt_set_errno(result); return NULL; @@ -714,8 +686,6 @@ struct dirent *readdir(DIR *d) d->cur = 0; /* current entry index */ } - fd_put(fd); - return (struct dirent *)(d->buf + d->cur); } RTM_EXPORT(readdir); @@ -742,7 +712,6 @@ long telldir(DIR *d) } result = fd->pos - d->num + d->cur; - fd_put(fd); return result; } @@ -770,7 +739,6 @@ void seekdir(DIR *d, off_t offset) /* seek to the offset position of directory */ if (dfs_file_lseek(fd, offset) >= 0) d->num = d->cur = 0; - fd_put(fd); } RTM_EXPORT(seekdir); @@ -795,7 +763,6 @@ void rewinddir(DIR *d) /* seek to the beginning of directory */ if (dfs_file_lseek(fd, 0) >= 0) d->num = d->cur = 0; - fd_put(fd); } RTM_EXPORT(rewinddir); @@ -821,9 +788,8 @@ int closedir(DIR *d) } result = dfs_file_close(fd); - fd_put(fd); + fd_release(d->fd); - fd_put(fd); rt_free(d); if (result < 0) @@ -854,7 +820,9 @@ int chdir(const char *path) if (path == NULL) { dfs_lock(); +#ifdef DFS_USING_WORKDIR rt_kprintf("%s\n", working_directory); +#endif dfs_unlock(); return 0; @@ -888,9 +856,12 @@ int chdir(const char *path) /* close directory stream */ closedir(d); - +#ifdef RT_USING_LWP /* copy full path to working directory */ - strncpy(working_directory, fullpath, DFS_PATH_MAX); + lwp_setcwd(fullpath); +#else + rt_strncpy(working_directory, fullpath, DFS_PATH_MAX); +#endif /* release normalize directory path name */ rt_free(fullpath); @@ -923,6 +894,31 @@ int access(const char *path, int amode) /* ignore R_OK,W_OK,X_OK condition */ return 0; } +/** + * this function is a POSIX compliant version, which will set current + * working directory. + * + * @param buf the current directory. + * + * @return null. + */ +void setcwd(char *buf) +{ +#ifdef DFS_USING_WORKDIR + dfs_lock(); +#ifdef RT_USING_LWP + lwp_setcwd(buf); +#else + rt_strncpy(working_directory, buf, DFS_PATH_MAX); +#endif + dfs_unlock(); +#else + rt_kprintf(NO_WORKING_DIR); +#endif + + return ; +} +RTM_EXPORT(setcwd); /** * this function is a POSIX compliant version, which will return current @@ -936,8 +932,22 @@ int access(const char *path, int amode) char *getcwd(char *buf, size_t size) { #ifdef DFS_USING_WORKDIR + char *dir_buf = RT_NULL; + dfs_lock(); - strncpy(buf, working_directory, size); + +#ifdef RT_USING_LWP + dir_buf = lwp_getcwd(); +#else + dir_buf = &working_directory[0]; +#endif + + /* copy to buf parameter */ + if (buf) + { + rt_strncpy(buf, dir_buf, size); + } + dfs_unlock(); #else rt_kprintf(NO_WORKING_DIR); diff --git a/components/dfs/src/poll.c b/components/dfs/src/poll.c index fc48eca758d9e1c1d34c58d13683582db202398c..a2f3cb8074b823bc5406f4df703da9539034c17c 100644 --- a/components/dfs/src/poll.c +++ b/components/dfs/src/poll.c @@ -95,20 +95,22 @@ static int poll_wait_timeout(struct rt_poll_table *pt, int msec) if (timeout != 0 && !pt->triggered) { - rt_thread_suspend(thread); - if (timeout > 0) + if (rt_thread_suspend_with_flag(thread, RT_INTERRUPTIBLE) == RT_EOK) { - rt_timer_control(&(thread->thread_timer), - RT_TIMER_CTRL_SET_TIME, - &timeout); - rt_timer_start(&(thread->thread_timer)); - } + if (timeout > 0) + { + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &timeout); + rt_timer_start(&(thread->thread_timer)); + } - rt_hw_interrupt_enable(level); + rt_hw_interrupt_enable(level); - rt_schedule(); + rt_schedule(); - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); + } } ret = !pt->triggered; @@ -132,23 +134,21 @@ static int do_pollfd(struct pollfd *pollfd, rt_pollreq_t *req) if (f) { mask = POLLMASK_DEFAULT; - if (f->fops->poll) + if (f->fnode->fops->poll) { req->_key = pollfd->events | POLLERR | POLLHUP; - mask = f->fops->poll(f, req); + mask = f->fnode->fops->poll(f, req); /* dealwith the device return error -1*/ if (mask < 0) - { - fd_put(f); + { pollfd->revents = 0; return mask; } } /* Mask out unneeded events. */ mask &= pollfd->events | POLLERR | POLLHUP; - fd_put(f); } } pollfd->revents = mask; diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index db4455160e3633292ffa405f07fe4fb0c58f620d..8e6a17eef57d656896db942c46e373f868b0e8a0 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -4,11 +4,15 @@ config RT_USING_DEVICE_IPC bool "Using device drivers IPC" default y +config RT_UNAMED_PIPE_NUMBER + int "The number of unamed pipe" + default 64 + if RT_USING_DEVICE_IPC config RT_PIPE_BUFSZ int "Set pipe buffer size" default 512 - + config RT_USING_SYSTEM_WORKQUEUE bool "Using system default workqueue" default n @@ -41,6 +45,16 @@ if RT_USING_SERIAL endif +config RT_USING_TTY + bool "Using TTY SYSTEM" + default y + +if RT_USING_TTY + config RT_TTY_DEBUG + bool "Using TTY DEBUG" + default n +endif + config RT_USING_CAN bool "Using CAN device drivers" default n @@ -118,7 +132,19 @@ config RT_USING_ADC config RT_USING_DAC bool "Using DAC device drivers" default n - + +config RT_USING_NULL + bool "Using NULL device drivers" + default n + +config RT_USING_ZERO + bool "Using ZERO device drivers" + default n + +config RT_USING_RANDOM + bool "Using RANDOM device drivers" + default n + config RT_USING_PWM bool "Using PWM device drivers" default n @@ -202,7 +228,7 @@ config RT_USING_SPI bool "Using SPI Bus/Device device drivers" default n - if RT_USING_SPI + if RT_USING_SPI config RT_USING_QSPI bool "Enable QSPI mode" default n @@ -226,7 +252,7 @@ config RT_USING_SPI config RT_SFUD_USING_FLASH_INFO_TABLE bool "Using defined supported flash chip information table" default y - + config RT_SFUD_USING_QSPI bool "Using QSPI mode support" select RT_USING_QSPI @@ -262,7 +288,7 @@ config RT_USING_WDT config RT_USING_AUDIO bool "Using Audio device drivers" default n - + if RT_USING_AUDIO config RT_AUDIO_REPLAY_MP_BLOCK_SIZE int "Replay memory pool block size" diff --git a/components/drivers/audio/audio_pipe.c b/components/drivers/audio/audio_pipe.c index d7c37009b6c3005aba1738ddf0f3b4a93d34f100..4fd8b0edfe776af2f3f2e0edc72018f679a6cc35 100644 --- a/components/drivers/audio/audio_pipe.c +++ b/components/drivers/audio/audio_pipe.c @@ -72,7 +72,7 @@ static rt_size_t rt_pipe_read(rt_device_t dev, read_nbytes = rt_ringbuffer_get(&(pipe->ringbuffer), (rt_uint8_t *)buffer, size); if (read_nbytes == 0) { - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); /* waiting on suspended read list */ rt_list_insert_before(&(pipe->suspended_read_list), &(thread->tlist)); @@ -160,7 +160,7 @@ static rt_size_t rt_pipe_write(rt_device_t dev, if (write_nbytes == 0) { /* pipe full, waiting on suspended write list */ - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); /* waiting on suspended read list */ rt_list_insert_before(&(pipe->suspended_write_list), &(thread->tlist)); diff --git a/components/drivers/include/drivers/mmcsd_host.h b/components/drivers/include/drivers/mmcsd_host.h index 1253062aefe3cea1f479211cbdc229abc157c18c..1550c4b3c7b46e5e0c31a7df735caba59aceab19 100644 --- a/components/drivers/include/drivers/mmcsd_host.h +++ b/components/drivers/include/drivers/mmcsd_host.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #ifndef __HOST_H__ @@ -18,33 +18,33 @@ extern "C" { #endif struct rt_mmcsd_io_cfg { - rt_uint32_t clock; /* clock rate */ - rt_uint16_t vdd; + rt_uint32_t clock; /* clock rate */ + rt_uint16_t vdd; /* vdd stores the bit number of the selected voltage range from below. */ - rt_uint8_t bus_mode; /* command output mode */ + rt_uint8_t bus_mode; /* command output mode */ -#define MMCSD_BUSMODE_OPENDRAIN 1 -#define MMCSD_BUSMODE_PUSHPULL 2 +#define MMCSD_BUSMODE_OPENDRAIN 1 +#define MMCSD_BUSMODE_PUSHPULL 2 - rt_uint8_t chip_select; /* SPI chip select */ + rt_uint8_t chip_select; /* SPI chip select */ -#define MMCSD_CS_IGNORE 0 -#define MMCSD_CS_HIGH 1 -#define MMCSD_CS_LOW 2 +#define MMCSD_CS_IGNORE 0 +#define MMCSD_CS_HIGH 1 +#define MMCSD_CS_LOW 2 - rt_uint8_t power_mode; /* power supply mode */ + rt_uint8_t power_mode; /* power supply mode */ -#define MMCSD_POWER_OFF 0 -#define MMCSD_POWER_UP 1 -#define MMCSD_POWER_ON 2 +#define MMCSD_POWER_OFF 0 +#define MMCSD_POWER_UP 1 +#define MMCSD_POWER_ON 2 - rt_uint8_t bus_width; /* data bus width */ + rt_uint8_t bus_width; /* data bus width */ -#define MMCSD_BUS_WIDTH_1 0 -#define MMCSD_BUS_WIDTH_4 2 -#define MMCSD_BUS_WIDTH_8 3 +#define MMCSD_BUS_WIDTH_1 0 +#define MMCSD_BUS_WIDTH_4 2 +#define MMCSD_BUS_WIDTH_8 3 }; @@ -52,71 +52,72 @@ struct rt_mmcsd_host; struct rt_mmcsd_req; struct rt_mmcsd_host_ops { - void (*request)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req); - void (*set_iocfg)(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); - rt_int32_t (*get_card_status)(struct rt_mmcsd_host *host); - void (*enable_sdio_irq)(struct rt_mmcsd_host *host, rt_int32_t en); + void (*request)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req); + void (*set_iocfg)(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); + rt_int32_t (*get_card_status)(struct rt_mmcsd_host *host); + void (*enable_sdio_irq)(struct rt_mmcsd_host *host, rt_int32_t en); }; struct rt_mmcsd_host { - struct rt_mmcsd_card *card; - const struct rt_mmcsd_host_ops *ops; - rt_uint32_t freq_min; - rt_uint32_t freq_max; - struct rt_mmcsd_io_cfg io_cfg; - rt_uint32_t valid_ocr; /* current valid OCR */ -#define VDD_165_195 (1 << 7) /* VDD voltage 1.65 - 1.95 */ -#define VDD_20_21 (1 << 8) /* VDD voltage 2.0 ~ 2.1 */ -#define VDD_21_22 (1 << 9) /* VDD voltage 2.1 ~ 2.2 */ -#define VDD_22_23 (1 << 10) /* VDD voltage 2.2 ~ 2.3 */ -#define VDD_23_24 (1 << 11) /* VDD voltage 2.3 ~ 2.4 */ -#define VDD_24_25 (1 << 12) /* VDD voltage 2.4 ~ 2.5 */ -#define VDD_25_26 (1 << 13) /* VDD voltage 2.5 ~ 2.6 */ -#define VDD_26_27 (1 << 14) /* VDD voltage 2.6 ~ 2.7 */ -#define VDD_27_28 (1 << 15) /* VDD voltage 2.7 ~ 2.8 */ -#define VDD_28_29 (1 << 16) /* VDD voltage 2.8 ~ 2.9 */ -#define VDD_29_30 (1 << 17) /* VDD voltage 2.9 ~ 3.0 */ -#define VDD_30_31 (1 << 18) /* VDD voltage 3.0 ~ 3.1 */ -#define VDD_31_32 (1 << 19) /* VDD voltage 3.1 ~ 3.2 */ -#define VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */ -#define VDD_33_34 (1 << 21) /* VDD voltage 3.3 ~ 3.4 */ -#define VDD_34_35 (1 << 22) /* VDD voltage 3.4 ~ 3.5 */ -#define VDD_35_36 (1 << 23) /* VDD voltage 3.5 ~ 3.6 */ - rt_uint32_t flags; /* define device capabilities */ -#define MMCSD_BUSWIDTH_4 (1 << 0) -#define MMCSD_BUSWIDTH_8 (1 << 1) -#define MMCSD_MUTBLKWRITE (1 << 2) -#define MMCSD_HOST_IS_SPI (1 << 3) -#define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI) -#define MMCSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */ -#define MMCSD_SUP_HIGHSPEED (1 << 5) /* support high speed */ - - rt_uint32_t max_seg_size; /* maximum size of one dma segment */ - rt_uint32_t max_dma_segs; /* maximum number of dma segments in one request */ - rt_uint32_t max_blk_size; /* maximum block size */ - rt_uint32_t max_blk_count; /* maximum block count */ - - rt_uint32_t spi_use_crc; - struct rt_mutex bus_lock; - struct rt_semaphore sem_ack; - - rt_uint32_t sdio_irq_num; - struct rt_semaphore *sdio_irq_sem; - struct rt_thread *sdio_irq_thread; - - void *private_data; + char name[RT_NAME_MAX]; + struct rt_mmcsd_card *card; + const struct rt_mmcsd_host_ops *ops; + rt_uint32_t freq_min; + rt_uint32_t freq_max; + struct rt_mmcsd_io_cfg io_cfg; + rt_uint32_t valid_ocr; /* current valid OCR */ +#define VDD_165_195 (1 << 7) /* VDD voltage 1.65 - 1.95 */ +#define VDD_20_21 (1 << 8) /* VDD voltage 2.0 ~ 2.1 */ +#define VDD_21_22 (1 << 9) /* VDD voltage 2.1 ~ 2.2 */ +#define VDD_22_23 (1 << 10) /* VDD voltage 2.2 ~ 2.3 */ +#define VDD_23_24 (1 << 11) /* VDD voltage 2.3 ~ 2.4 */ +#define VDD_24_25 (1 << 12) /* VDD voltage 2.4 ~ 2.5 */ +#define VDD_25_26 (1 << 13) /* VDD voltage 2.5 ~ 2.6 */ +#define VDD_26_27 (1 << 14) /* VDD voltage 2.6 ~ 2.7 */ +#define VDD_27_28 (1 << 15) /* VDD voltage 2.7 ~ 2.8 */ +#define VDD_28_29 (1 << 16) /* VDD voltage 2.8 ~ 2.9 */ +#define VDD_29_30 (1 << 17) /* VDD voltage 2.9 ~ 3.0 */ +#define VDD_30_31 (1 << 18) /* VDD voltage 3.0 ~ 3.1 */ +#define VDD_31_32 (1 << 19) /* VDD voltage 3.1 ~ 3.2 */ +#define VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */ +#define VDD_33_34 (1 << 21) /* VDD voltage 3.3 ~ 3.4 */ +#define VDD_34_35 (1 << 22) /* VDD voltage 3.4 ~ 3.5 */ +#define VDD_35_36 (1 << 23) /* VDD voltage 3.5 ~ 3.6 */ + rt_uint32_t flags; /* define device capabilities */ +#define MMCSD_BUSWIDTH_4 (1 << 0) +#define MMCSD_BUSWIDTH_8 (1 << 1) +#define MMCSD_MUTBLKWRITE (1 << 2) +#define MMCSD_HOST_IS_SPI (1 << 3) +#define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI) +#define MMCSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */ +#define MMCSD_SUP_HIGHSPEED (1 << 5) /* support high speed */ + + rt_uint32_t max_seg_size; /* maximum size of one dma segment */ + rt_uint32_t max_dma_segs; /* maximum number of dma segments in one request */ + rt_uint32_t max_blk_size; /* maximum block size */ + rt_uint32_t max_blk_count; /* maximum block count */ + + rt_uint32_t spi_use_crc; + struct rt_mutex bus_lock; + struct rt_semaphore sem_ack; + + rt_uint32_t sdio_irq_num; + struct rt_semaphore *sdio_irq_sem; + struct rt_thread *sdio_irq_thread; + + void *private_data; }; rt_inline void mmcsd_delay_ms(rt_uint32_t ms) { - if (ms < 1000 / RT_TICK_PER_SECOND) - { - rt_thread_delay(1); - } - else - { - rt_thread_delay(ms/(1000 / RT_TICK_PER_SECOND)); - } + if (ms < 1000 / RT_TICK_PER_SECOND) + { + rt_thread_delay(1); + } + else + { + rt_thread_delay(ms/(1000 / RT_TICK_PER_SECOND)); + } } #ifdef __cplusplus diff --git a/components/drivers/include/drivers/serial.h b/components/drivers/include/drivers/serial.h index 45095af63f36f5749154fa1055731975804db884..901a8666e416a3d96368815206d891673c112e1e 100644 --- a/components/drivers/include/drivers/serial.h +++ b/components/drivers/include/drivers/serial.h @@ -144,6 +144,8 @@ struct rt_serial_device void *serial_rx; void *serial_tx; + + struct rt_device_notify rx_notify; }; typedef struct rt_serial_device rt_serial_t; diff --git a/components/drivers/include/ipc/pipe.h b/components/drivers/include/ipc/pipe.h index 93ba95cd2c1234cb68df4b16b0bbe8e618f45b94..338063ace81a029ec0a4709caf9f77d25454c341 100644 --- a/components/drivers/include/ipc/pipe.h +++ b/components/drivers/include/ipc/pipe.h @@ -25,14 +25,14 @@ struct rt_pipe_device { struct rt_device parent; rt_bool_t is_named; +#ifdef RT_USING_POSIX + int pipeno; /* for unamed pipe */ +#endif /* ring buffer in pipe device */ struct rt_ringbuffer *fifo; rt_uint16_t bufsz; - rt_uint8_t readers; - rt_uint8_t writers; - rt_wqueue_t reader_queue; rt_wqueue_t writer_queue; diff --git a/components/drivers/include/ipc/waitqueue.h b/components/drivers/include/ipc/waitqueue.h index e26ec1e896078620c4f1cf192b1650d035201ba2..a64b973a9e4f7572c578258763d5526a94515ebb 100644 --- a/components/drivers/include/ipc/waitqueue.h +++ b/components/drivers/include/ipc/waitqueue.h @@ -43,6 +43,8 @@ rt_inline void rt_wqueue_init(rt_wqueue_t *queue) void rt_wqueue_add(rt_wqueue_t *queue, struct rt_wqueue_node *node); void rt_wqueue_remove(struct rt_wqueue_node *node); int rt_wqueue_wait(rt_wqueue_t *queue, int condition, int timeout); +int rt_wqueue_wait_killable(rt_wqueue_t *queue, int condition, int timeout); +int rt_wqueue_wait_interruptible(rt_wqueue_t *queue, int condition, int timeout); void rt_wqueue_wakeup(rt_wqueue_t *queue, void *key); #define DEFINE_WAIT_FUNC(name, function) \ diff --git a/components/drivers/misc/SConscript b/components/drivers/misc/SConscript index 72058eeeca4c26200c3e42e43166fba838162397..927e662b19a7b9bbf5b4410df7f1806976087cf9 100644 --- a/components/drivers/misc/SConscript +++ b/components/drivers/misc/SConscript @@ -1,28 +1,37 @@ from building import * cwd = GetCurrentDir() -src = [] +src = [] CPPPATH = [cwd + '/../include'] group = [] if GetDepend(['RT_USING_PIN']): src = src + ['pin.c'] - + if GetDepend(['RT_USING_ADC']): src = src + ['adc.c'] - + if GetDepend(['RT_USING_DAC']): src = src + ['dac.c'] if GetDepend(['RT_USING_PWM']): src = src + ['rt_drv_pwm.c'] - + if GetDepend(['RT_USING_PULSE_ENCODER']): src = src + ['pulse_encoder.c'] if GetDepend(['RT_USING_INPUT_CAPTURE']): src = src + ['rt_inputcapture.c'] +if GetDepend(['RT_USING_NULL']): + src = src + ['rt_null.c'] + +if GetDepend(['RT_USING_ZERO']): + src = src + ['rt_zero.c'] + +if GetDepend(['RT_USING_RANDOM']): + src = src + ['rt_random.c'] + if len(src): group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) diff --git a/components/drivers/misc/rt_null.c b/components/drivers/misc/rt_null.c new file mode 100644 index 0000000000000000000000000000000000000000..3e4cf6f3da6594956160928cca50d7412758cd7c --- /dev/null +++ b/components/drivers/misc/rt_null.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2011-2020, Shanghai Real-Thread Electronic Technology Co.,Ltd + * + * Change Logs: + * Date Author Notes + * 2020-12-03 quanzhao the first version + */ + +#include +#include +#include + +static struct rt_device null_dev; + +static rt_size_t null_read (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + return 0; +} + +static rt_size_t null_write (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + return size; +} + +static rt_err_t null_control (rt_device_t dev, int cmd, void *args) +{ + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops null_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + null_read, + null_write, + null_control +}; +#endif + +int null_device_init(void) +{ + static rt_bool_t init_ok = RT_FALSE; + + if (init_ok) + { + return 0; + } + RT_ASSERT(!rt_device_find("null")); + null_dev.type = RT_Device_Class_Miscellaneous; + +#ifdef RT_USING_DEVICE_OPS + null_dev.ops = &null_ops; +#else + null_dev.init = RT_NULL; + null_dev.open = RT_NULL; + null_dev.close = RT_NULL; + null_dev.read = null_read; + null_dev.write = null_write; + null_dev.control = null_control; +#endif + + /* no private */ + null_dev.user_data = RT_NULL; + + rt_device_register(&null_dev, "null", RT_DEVICE_FLAG_RDWR); + + init_ok = RT_TRUE; + + return 0; +} +INIT_DEVICE_EXPORT(null_device_init); + diff --git a/components/drivers/misc/rt_random.c b/components/drivers/misc/rt_random.c new file mode 100644 index 0000000000000000000000000000000000000000..1ea0480b7c008a069f311ba6b03541906c18018e --- /dev/null +++ b/components/drivers/misc/rt_random.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2011-2020, Shanghai Real-Thread Electronic Technology Co.,Ltd + * + * Change Logs: + * Date Author Notes + * 2020-12-18 quanzhao the first version + */ + +#include +#include +#include + +static struct rt_device random_dev; +static unsigned long seed; + +static rt_uint16_t calc_random(void) +{ + seed = 214013L * seed + 2531011L; + return (seed >> 16) & 0x7FFF; /* return bits 16~30 */ +} + +static rt_size_t random_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_uint16_t rand = calc_random(); + ssize_t ret = sizeof(rand); + rt_memcpy(buffer, &rand, ret); + return ret; +} + +static rt_size_t random_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + ssize_t ret = sizeof(seed); + rt_memcpy(&seed, buffer, ret); + return ret; +} + +static rt_err_t random_control(rt_device_t dev, int cmd, void *args) +{ + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops random_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + random_read, + random_write, + random_control +}; +#endif + +int random_device_init(void) +{ + static rt_bool_t init_ok = RT_FALSE; + + if (init_ok) + { + return 0; + } + RT_ASSERT(!rt_device_find("random")); + random_dev.type = RT_Device_Class_Miscellaneous; + +#ifdef RT_USING_DEVICE_OPS + random_dev.ops = &random_ops; +#else + random_dev.init = RT_NULL; + random_dev.open = RT_NULL; + random_dev.close = RT_NULL; + random_dev.read = random_read; + random_dev.write = random_write; + random_dev.control = random_control; +#endif + + /* no private */ + random_dev.user_data = RT_NULL; + + rt_device_register(&random_dev, "random", RT_DEVICE_FLAG_RDWR); + + init_ok = RT_TRUE; + + return 0; +} +INIT_DEVICE_EXPORT(random_device_init); + +static struct rt_device urandom_dev; +static unsigned long useed; + +static rt_uint16_t calc_urandom(void) +{ + useed = 214013L * useed + 2531011L; + return (useed >> 16) & 0x7FFF; /* return bits 16~30 */ +} + +static rt_size_t random_uread(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_uint16_t rand = calc_urandom(); + ssize_t ret = sizeof(rand); + rt_memcpy(buffer, &rand, ret); + return ret; +} + +static rt_size_t random_uwrite(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + ssize_t ret = sizeof(useed); + rt_memcpy(&useed, buffer, ret); + return ret; +} + +static rt_err_t random_ucontrol(rt_device_t dev, int cmd, void *args) +{ + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops urandom_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + random_uread, + random_uwrite, + random_ucontrol +}; +#endif + +int urandom_device_init(void) +{ + static rt_bool_t init_ok = RT_FALSE; + + if (init_ok) + { + return 0; + } + RT_ASSERT(!rt_device_find("urandom")); + urandom_dev.type = RT_Device_Class_Miscellaneous; + +#ifdef RT_USING_DEVICE_OPS + urandom_dev.ops = &urandom_ops; +#else + urandom_dev.init = RT_NULL; + urandom_dev.open = RT_NULL; + urandom_dev.close = RT_NULL; + urandom_dev.read = random_uread; + urandom_dev.write = random_uwrite; + urandom_dev.control = random_ucontrol; +#endif + + /* no private */ + urandom_dev.user_data = RT_NULL; + + rt_device_register(&urandom_dev, "urandom", RT_DEVICE_FLAG_RDWR); + + init_ok = RT_TRUE; + + return 0; +} +INIT_DEVICE_EXPORT(urandom_device_init); diff --git a/components/drivers/misc/rt_zero.c b/components/drivers/misc/rt_zero.c new file mode 100644 index 0000000000000000000000000000000000000000..f2657a2360b43842bedfc7836e016566a07714a6 --- /dev/null +++ b/components/drivers/misc/rt_zero.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2011-2020, Shanghai Real-Thread Electronic Technology Co.,Ltd + * + * Change Logs: + * Date Author Notes + * 2020-12-03 quanzhao the first version + */ + +#include +#include +#include + +static struct rt_device zero_dev; + +static rt_size_t zero_read (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_memset(buffer, 0, size); + return size; +} + +static rt_size_t zero_write (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + return size; +} + +static rt_err_t zero_control (rt_device_t dev, int cmd, void *args) +{ + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops zero_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + zero_read, + zero_write, + zero_control +}; +#endif + +int zero_device_init(void) +{ + static rt_bool_t init_ok = RT_FALSE; + + if (init_ok) + { + return 0; + } + RT_ASSERT(!rt_device_find("zero")); + zero_dev.type = RT_Device_Class_Miscellaneous; + +#ifdef RT_USING_DEVICE_OPS + zero_dev.ops = &zero_ops; +#else + zero_dev.init = RT_NULL; + zero_dev.open = RT_NULL; + zero_dev.close = RT_NULL; + zero_dev.read = zero_read; + zero_dev.write = zero_write; + zero_dev.control = zero_control; +#endif + + /* no private */ + zero_dev.user_data = RT_NULL; + + rt_device_register(&zero_dev, "zero", RT_DEVICE_FLAG_RDWR); + + init_ok = RT_TRUE; + + return 0; +} +INIT_DEVICE_EXPORT(zero_device_init); + diff --git a/components/drivers/mtd/mtd_nand.c b/components/drivers/mtd/mtd_nand.c index ae5aa9c17285dd8e175ed6e5c413ebada98635d9..c5e6a8766ecceeea167d0fcfa718191ee2761756 100644 --- a/components/drivers/mtd/mtd_nand.c +++ b/components/drivers/mtd/mtd_nand.c @@ -11,7 +11,7 @@ /* * COPYRIGHT (C) 2012, Shanghai Real Thread */ - +#include #include #ifdef RT_USING_MTD_NAND diff --git a/components/drivers/mtd/mtd_nor.c b/components/drivers/mtd/mtd_nor.c index b941f9236d5e1df0e1d30ce7eb348d6de9645b0e..d28482e3c9204a33f2849b1c4190d21cbb706839 100644 --- a/components/drivers/mtd/mtd_nor.c +++ b/components/drivers/mtd/mtd_nor.c @@ -35,7 +35,9 @@ static rt_size_t _mtd_read(rt_device_t dev, void *buffer, rt_size_t size) { - return size; + struct rt_mtd_nor_device *device = (struct rt_mtd_nor_device *)dev; + + return device->ops->read(device, pos + device->block_start, buffer, size); } static rt_size_t _mtd_write(rt_device_t dev, @@ -43,7 +45,9 @@ static rt_size_t _mtd_write(rt_device_t dev, const void *buffer, rt_size_t size) { - return size; + struct rt_mtd_nor_device *device = (struct rt_mtd_nor_device *)dev; + + return device->ops->write(device, pos + device->block_start, buffer, size); } static rt_err_t _mtd_control(rt_device_t dev, int cmd, void *args) diff --git a/components/drivers/rtc/rtc.c b/components/drivers/rtc/rtc.c index 682515ce98a3d853e39a00c1b0e55987674d4f6b..361488f991ee16bea11beef56abb61ad02b2659e 100644 --- a/components/drivers/rtc/rtc.c +++ b/components/drivers/rtc/rtc.c @@ -186,7 +186,7 @@ FINSH_FUNCTION_EXPORT(list_date, show date and time.) FINSH_FUNCTION_EXPORT(set_date, set date. e.g: set_date(2010,2,28)) FINSH_FUNCTION_EXPORT(set_time, set time. e.g: set_time(23,59,59)) -#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) +#if defined(RT_USING_FINSH) static void date(uint8_t argc, char **argv) { if (argc == 1) @@ -247,7 +247,7 @@ static void date(uint8_t argc, char **argv) } } MSH_CMD_EXPORT(date, get date and time or set [year month day hour min sec]); -#endif /* defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) */ +#endif /* defined(RT_USING_FINSH) */ #endif /* RT_USING_FINSH */ diff --git a/components/drivers/sdio/block_dev.c b/components/drivers/sdio/block_dev.c index 602acb9aa77a6a917ea4b2d862a8d48eb633b4ab..c7be39209f43f83b128320d492bcbd362ce5bd72 100644 --- a/components/drivers/sdio/block_dev.c +++ b/components/drivers/sdio/block_dev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -76,7 +76,7 @@ rt_int32_t mmcsd_num_wr_blocks(struct rt_mmcsd_card *card) timeout_us += data.timeout_clks * 1000 / (card->host->io_cfg.clock / 1000); - if (timeout_us > 100000) + if (timeout_us > 100000) { data.timeout_ns = 100000000; data.timeout_clks = 0; @@ -119,9 +119,9 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, rt_memset(&data, 0, sizeof(struct rt_mmcsd_data)); req.cmd = &cmd; req.data = &data; - + cmd.arg = sector; - if (!(card->flags & CARD_FLAG_SDHC)) + if (!(card->flags & CARD_FLAG_SDHC)) { cmd.arg <<= 9; } @@ -130,7 +130,7 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, data.blksize = SECTOR_SIZE; data.blks = blks; - if (blks > 1) + if (blks > 1) { if (!controller_is_spi(card->host) || !dir) { @@ -149,7 +149,7 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, w_cmd = WRITE_BLOCK; } - if (!dir) + if (!dir) { cmd.cmd_code = r_cmd; data.flags |= DATA_DIR_READ; @@ -164,9 +164,9 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, data.buf = buf; mmcsd_send_request(host, &req); - if (!controller_is_spi(card->host) && dir != 0) + if (!controller_is_spi(card->host) && dir != 0) { - do + do { rt_int32_t err; @@ -174,7 +174,7 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, cmd.arg = card->rca << 16; cmd.flags = RESP_R1 | CMD_AC; err = mmcsd_send_cmd(card->host, &cmd, 5); - if (err) + if (err) { LOG_E("error %d requesting status", err); break; @@ -190,7 +190,7 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, mmcsd_host_unlock(host); - if (cmd.err || data.err || stop.err) + if (cmd.err || data.err || stop.err) { LOG_E("mmcsd request blocks error"); LOG_E("%d,%d,%d, 0x%08x,0x%08x", @@ -264,7 +264,7 @@ static rt_size_t rt_mmcsd_read(rt_device_t dev, rt_sem_release(part->lock); /* the length of reading must align to SECTOR SIZE */ - if (err) + if (err) { rt_set_errno(-EIO); return 0; @@ -305,7 +305,7 @@ static rt_size_t rt_mmcsd_write(rt_device_t dev, rt_sem_release(part->lock); /* the length of reading must align to SECTOR SIZE */ - if (err) + if (err) { rt_set_errno(-EIO); @@ -330,7 +330,7 @@ static rt_int32_t mmcsd_set_blksize(struct rt_mmcsd_card *card) err = mmcsd_send_cmd(card->host, &cmd, 5); mmcsd_host_unlock(card->host); - if (err) + if (err) { LOG_E("MMCSD: unable to set block size to %d: %d", cmd.arg, err); @@ -341,7 +341,7 @@ static rt_int32_t mmcsd_set_blksize(struct rt_mmcsd_card *card) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops mmcsd_blk_ops = +const static struct rt_device_ops mmcsd_blk_ops = { rt_mmcsd_init, rt_mmcsd_open, @@ -357,12 +357,12 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) rt_int32_t err = 0; rt_uint8_t i, status; rt_uint8_t *sector; - char dname[4]; - char sname[8]; + char dname[10]; + char sname[16]; struct mmcsd_blk_device *blk_dev = RT_NULL; err = mmcsd_set_blksize(card); - if(err) + if(err) { return err; } @@ -381,28 +381,68 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) status = rt_mmcsd_req_blk(card, 0, sector, 1, 0); if (status == RT_EOK) { + blk_dev = rt_calloc(1, sizeof(struct mmcsd_blk_device)); + if (!blk_dev) + { + LOG_E("mmcsd:malloc memory failed!"); + return -1; + } + + blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * + card->host->max_seg_size) >> 9, + (card->host->max_blk_count * + card->host->max_blk_size) >> 9); + blk_dev->part.offset = 0; + blk_dev->part.size = 0; + rt_snprintf(sname, sizeof(sname)-1, "sem_%s%d", card->host->name,0); + blk_dev->part.lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO); + /* register mmcsd device */ + blk_dev->dev.type = RT_Device_Class_Block; +#ifdef RT_USING_DEVICE_OPS + blk_dev->dev.ops = &mmcsd_blk_ops; +#else + blk_dev->dev.init = rt_mmcsd_init; + blk_dev->dev.open = rt_mmcsd_open; + blk_dev->dev.close = rt_mmcsd_close; + blk_dev->dev.read = rt_mmcsd_read; + blk_dev->dev.write = rt_mmcsd_write; + blk_dev->dev.control = rt_mmcsd_control; +#endif + blk_dev->card = card; + + blk_dev->geometry.bytes_per_sector = 1<<9; + blk_dev->geometry.block_size = card->card_blksize; + blk_dev->geometry.sector_count = + card->card_capacity * (1024 / 512); + + blk_dev->dev.user_data = blk_dev; + + rt_device_register(&(blk_dev->dev), card->host->name, + RT_DEVICE_FLAG_RDWR); + rt_list_insert_after(&blk_devices, &blk_dev->list); + for (i = 0; i < RT_MMCSD_MAX_PARTITION; i++) { blk_dev = rt_calloc(1, sizeof(struct mmcsd_blk_device)); - if (!blk_dev) + if (!blk_dev) { LOG_E("mmcsd:malloc memory failed!"); break; } - blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * - card->host->max_seg_size) >> 9, - (card->host->max_blk_count * + blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * + card->host->max_seg_size) >> 9, + (card->host->max_blk_count * card->host->max_blk_size) >> 9); /* get the first partition */ status = dfs_filesystem_get_partition(&blk_dev->part, sector, i); if (status == RT_EOK) { - rt_snprintf(dname, 4, "sd%d", i); - rt_snprintf(sname, 8, "sem_sd%d", i); + rt_snprintf(dname, sizeof(dname)-1, "%s%d", card->host->name,i); + rt_snprintf(sname, sizeof(sname)-1, "sem_%s%d", card->host->name,i+1); blk_dev->part.lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO); - + /* register mmcsd device */ blk_dev->dev.type = RT_Device_Class_Block; #ifdef RT_USING_DEVICE_OPS @@ -415,66 +455,31 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) blk_dev->dev.write = rt_mmcsd_write; blk_dev->dev.control = rt_mmcsd_control; #endif - blk_dev->dev.user_data = blk_dev; - blk_dev->card = card; - + blk_dev->geometry.bytes_per_sector = 1<<9; blk_dev->geometry.block_size = card->card_blksize; blk_dev->geometry.sector_count = blk_dev->part.size; - - rt_device_register(&blk_dev->dev, dname, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + blk_dev->dev.user_data = blk_dev; + + rt_device_register(&(blk_dev->dev), dname, + RT_DEVICE_FLAG_RDWR); rt_list_insert_after(&blk_devices, &blk_dev->list); } else { - if (i == 0) - { - /* there is no partition table */ - blk_dev->part.offset = 0; - blk_dev->part.size = 0; - blk_dev->part.lock = rt_sem_create("sem_sd0", 1, RT_IPC_FLAG_FIFO); - - /* register mmcsd device */ - blk_dev->dev.type = RT_Device_Class_Block; -#ifdef RT_USING_DEVICE_OPS - blk_dev->dev.ops = &mmcsd_blk_ops; -#else - blk_dev->dev.init = rt_mmcsd_init; - blk_dev->dev.open = rt_mmcsd_open; - blk_dev->dev.close = rt_mmcsd_close; - blk_dev->dev.read = rt_mmcsd_read; - blk_dev->dev.write = rt_mmcsd_write; - blk_dev->dev.control = rt_mmcsd_control; -#endif - blk_dev->dev.user_data = blk_dev; - - blk_dev->card = card; - - blk_dev->geometry.bytes_per_sector = 1<<9; - blk_dev->geometry.block_size = card->card_blksize; - blk_dev->geometry.sector_count = - card->card_capacity * (1024 / 512); - - rt_device_register(&blk_dev->dev, "sd0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - rt_list_insert_after(&blk_devices, &blk_dev->list); - } - else - { - rt_free(blk_dev); - blk_dev = RT_NULL; - break; - } + rt_free(blk_dev); + blk_dev = RT_NULL; + break; } #ifdef RT_USING_DFS_MNTTABLE if (blk_dev) { - LOG_I("try to mount file system!"); - /* try to mount file system on this block device */ - dfs_mount_device(&(blk_dev->dev)); + LOG_I("try to mount file system!"); + /* try to mount file system on this block device */ + dfs_mount_device(&(blk_dev->dev)); } #endif } @@ -484,10 +489,10 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) LOG_E("read mmcsd first sector failed"); err = -RT_ERROR; } - + /* release sector buffer */ rt_free(sector); - + return err; } @@ -499,15 +504,15 @@ void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card) for (l = (&blk_devices)->next, n = l->next; l != &blk_devices; l = n) { blk_dev = (struct mmcsd_blk_device *)rt_list_entry(l, struct mmcsd_blk_device, list); - if (blk_dev->card == card) + if (blk_dev->card == card) { - /* unmount file system */ - const char * mounted_path = dfs_filesystem_get_mounted_path(&(blk_dev->dev)); - if (mounted_path) - { + /* unmount file system */ + const char * mounted_path = dfs_filesystem_get_mounted_path(&(blk_dev->dev)); + if (mounted_path) + { dfs_unmount(mounted_path); LOG_D("unmount file system %s for device %s.\r\n", mounted_path, blk_dev->dev.parent.name); - } + } rt_sem_delete(blk_dev->part.lock); rt_device_unregister(&blk_dev->dev); rt_list_remove(&blk_dev->list); diff --git a/components/drivers/sdio/mmc.c b/components/drivers/sdio/mmc.c index c1c56d37fd45406293cad199d665ecd967b24a38..0a41eee594f7e801e01f55f7379012ee3bfd19aa 100644 --- a/components/drivers/sdio/mmc.c +++ b/components/drivers/sdio/mmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -45,9 +45,9 @@ static const rt_uint8_t tacc_value[] = rt_inline rt_uint32_t GET_BITS(rt_uint32_t *resp, rt_uint32_t start, rt_uint32_t size) -{ +{ const rt_int32_t __size = size; - const rt_uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; + const rt_uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; const rt_int32_t __off = 3 - ((start) / 32); const rt_int32_t __shft = (start) & 31; rt_uint32_t __res; @@ -67,7 +67,7 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) rt_uint32_t a, b; struct rt_mmcsd_csd *csd = &card->csd; rt_uint32_t *resp = card->resp_csd; - + /* * We only understand CSD structure v1.1 and v1.2. * v1.2 has extra information in bits 15, 11 and 10. @@ -76,10 +76,10 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) csd->csd_structure = GET_BITS(resp, 126, 2); if (csd->csd_structure == 0) { LOG_E("unrecognised CSD structure version %d!", csd->csd_structure); - + return -RT_ERROR; } - + csd->taac = GET_BITS(resp, 112, 8); csd->nsac = GET_BITS(resp, 104, 8); csd->tran_speed = GET_BITS(resp, 96, 8); @@ -95,7 +95,7 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) csd->wr_blk_len = GET_BITS(resp, 22, 4); csd->wr_blk_partial = GET_BITS(resp, 21, 1); csd->csd_crc = GET_BITS(resp, 1, 7); - + card->card_blksize = 1 << csd->rd_blk_len; card->tacc_clks = csd->nsac * 100; card->tacc_ns = (tacc_uint[csd->taac&0x07] * tacc_value[(csd->taac&0x78)>>3] + 9) / 10; @@ -106,7 +106,7 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) card->erase_size = (a + 1) * (b + 1); card->erase_size <<= csd->wr_blk_len - 9; } - + return 0; } @@ -119,12 +119,11 @@ static int mmc_get_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t **new_ext_csd) struct rt_mmcsd_req req; struct rt_mmcsd_cmd cmd; struct rt_mmcsd_data data; - + *new_ext_csd = RT_NULL; - - if (GET_BITS(card->resp_cid, 122, 4) < 4) + if (GET_BITS(card->resp_csd, 122, 4) < 4) return 0; - + /* * As the ext_csd is so large and mostly unused, we don't store the * raw block in mmc_card. @@ -134,29 +133,29 @@ static int mmc_get_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t **new_ext_csd) LOG_E("alloc memory failed when get ext csd!"); return -RT_ENOMEM; } - + rt_memset(&req, 0, sizeof(struct rt_mmcsd_req)); rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); rt_memset(&data, 0, sizeof(struct rt_mmcsd_data)); - + req.cmd = &cmd; req.data = &data; - + cmd.cmd_code = SEND_EXT_CSD; cmd.arg = 0; - + /* NOTE HACK: the RESP_SPI_R1 is always correct here, but we * rely on callers to never use this with "native" calls for reading * CSD or CID. Native versions of those commands use the R2 type, * not R1 plus a data block. */ cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC; - + data.blksize = 512; data.blks = 1; data.flags = DATA_DIR_READ; data.buf = ext_csd; - + /* * Some cards require longer data read timeout than indicated in CSD. * Address this by setting the read timeout to a "reasonably high" @@ -165,14 +164,14 @@ static int mmc_get_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t **new_ext_csd) */ data.timeout_ns = 300000000; data.timeout_clks = 0; - + mmcsd_send_request(card->host, &req); - + if (cmd.err) return cmd.err; if (data.err) return data.err; - + *new_ext_csd = ext_csd; return 0; } @@ -192,13 +191,13 @@ static int mmc_parse_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) card->flags |= CARD_FLAG_HIGHSPEED; card->hs_max_data_rate = 52000000; - + card_capacity = *((rt_uint32_t *)&ext_csd[EXT_CSD_SEC_CNT]); card_capacity *= card->card_blksize; card_capacity >>= 10; /* unit:KB */ card->card_capacity = card_capacity; LOG_I("emmc card capacity %d KB.", card->card_capacity); - + return 0; } @@ -211,41 +210,41 @@ static int mmc_parse_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) * * Modifies the EXT_CSD register for selected card. */ -static int mmc_switch(struct rt_mmcsd_card *card, rt_uint8_t set, +static int mmc_switch(struct rt_mmcsd_card *card, rt_uint8_t set, rt_uint8_t index, rt_uint8_t value) { int err; struct rt_mmcsd_host *host = card->host; struct rt_mmcsd_cmd cmd = {0}; - + cmd.cmd_code = SWITCH; cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | (index << 16) | (value << 8) | set; - cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_AC; - + cmd.flags = RESP_R1B | CMD_AC; + err = mmcsd_send_cmd(host, &cmd, 3); if (err) return err; - + return 0; } -static int mmc_compare_ext_csds(struct rt_mmcsd_card *card, +static int mmc_compare_ext_csds(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd, rt_uint32_t bus_width) { rt_uint8_t *bw_ext_csd; int err; - + if (bus_width == MMCSD_BUS_WIDTH_1) return 0; - + err = mmc_get_ext_csd(card, &bw_ext_csd); - + if (err || bw_ext_csd == RT_NULL) { err = -RT_ERROR; goto out; } - + /* only compare read only fields */ err = !((ext_csd[EXT_CSD_PARTITION_SUPPORT] == bw_ext_csd[EXT_CSD_PARTITION_SUPPORT]) && (ext_csd[EXT_CSD_ERASED_MEM_CONT] == bw_ext_csd[EXT_CSD_ERASED_MEM_CONT]) && @@ -273,10 +272,10 @@ static int mmc_compare_ext_csds(struct rt_mmcsd_card *card, (ext_csd[EXT_CSD_PWR_CL_DDR_52_195] == bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_195]) && (ext_csd[EXT_CSD_PWR_CL_DDR_52_360] == bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_360]) && (ext_csd[EXT_CSD_PWR_CL_DDR_200_360] == bw_ext_csd[EXT_CSD_PWR_CL_DDR_200_360])); - + if (err) err = -RT_ERROR; - + out: rt_free(bw_ext_csd); return err; @@ -302,10 +301,10 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) struct rt_mmcsd_host *host = card->host; unsigned idx, bus_width = 0; int err = 0; - - if (GET_BITS(card->resp_cid, 122, 4) < 4) + + if (GET_BITS(card->resp_csd, 122, 4) < 4) return 0; - + /* * Unlike SD, MMC cards dont have a configuration register to notify * supported bus width. So bus test command should be run to identify @@ -323,21 +322,25 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) * set by drivers. */ if ((!(host->flags & MMCSD_BUSWIDTH_8) && - ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8) || + ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8) || (!(host->flags & MMCSD_BUSWIDTH_4) && - (ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_4 || - ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8))) - continue; + (ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_4 || + ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8))) + continue; err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, ext_csd_bits[idx]); if (err) continue; - + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_HS_TIMING, + 1); + + if (err) + continue; bus_width = bus_widths[idx]; mmcsd_set_bus_width(host, bus_width); - mmcsd_delay_ms(20); //delay 10ms err = mmc_compare_ext_csds(card, ext_csd, bus_width); if (!err) { err = bus_width; @@ -358,10 +361,10 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) } } } - + return err; } -rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, +rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr, rt_uint32_t *rocr) { struct rt_mmcsd_cmd cmd; @@ -369,20 +372,20 @@ rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, rt_err_t err = RT_EOK; rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); - + cmd.cmd_code = SEND_OP_COND; cmd.arg = controller_is_spi(host) ? 0 : ocr; cmd.flags = RESP_SPI_R1 | RESP_R3 | CMD_BCR; - + for (i = 100; i; i--) { err = mmcsd_send_cmd(host, &cmd, 3); if (err) break; - + /* if we're just probing, do a single pass */ if (ocr == 0) break; - + /* otherwise wait until reset completes */ if (controller_is_spi(host)) { if (!(cmd.resp[0] & R1_SPI_IDLE)) @@ -391,15 +394,15 @@ rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, if (cmd.resp[0] & CARD_BUSY) break; } - + err = -RT_ETIMEOUT; - + mmcsd_delay_ms(10); //delay 10ms } - + if (rocr && !controller_is_spi(host)) *rocr = cmd.resp[0]; - + return err; } @@ -407,17 +410,17 @@ static rt_err_t mmc_set_card_addr(struct rt_mmcsd_host *host, rt_uint32_t rca) { rt_err_t err; struct rt_mmcsd_cmd cmd; - + rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd)); - + cmd.cmd_code = SET_RELATIVE_ADDR; cmd.arg = rca << 16; cmd.flags = RESP_R1 | CMD_AC; - + err = mmcsd_send_cmd(host, &cmd, 3); if (err) return err; - + return 0; } @@ -432,19 +435,19 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, struct rt_mmcsd_card *card = RT_NULL; mmcsd_go_idle(host); - + /* The extra bit indicates that we support high capacity */ err = mmc_send_op_cond(host, ocr | (1 << 30), &rocr); if (err) goto err; - - if (controller_is_spi(host)) + + if (controller_is_spi(host)) { err = mmcsd_spi_use_crc(host, 1); if (err) goto err1; } - + if (controller_is_spi(host)) err = mmcsd_get_cid(host, resp); else @@ -453,7 +456,7 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, goto err; card = rt_malloc(sizeof(struct rt_mmcsd_card)); - if (!card) + if (!card) { LOG_E("malloc card failed!"); err = -RT_ENOMEM; @@ -469,7 +472,7 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, /* * For native busses: get card RCA and quit open drain mode. */ - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { err = mmc_set_card_addr(host, card->rca); if (err) @@ -486,24 +489,24 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, if (err) goto err1; - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { err = mmcsd_select_card(card); if (err) goto err1; } - + /* * Fetch and process extended CSD. */ - + err = mmc_get_ext_csd(card, &ext_csd); if (err) goto err1; err = mmc_parse_ext_csd(card, ext_csd); if (err) goto err1; - + /* If doing byte addressing, check if required to do sector * addressing. Handle the case of <2GB cards needing sector * addressing. See section 8.1 JEDEC Standard JED84-A441; @@ -511,18 +514,17 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, */ if (!(card->flags & CARD_FLAG_SDHC) && (rocr & (1<<30))) card->flags |= CARD_FLAG_SDHC; - + /* set bus speed */ - if (card->flags & CARD_FLAG_HIGHSPEED) + if (card->flags & CARD_FLAG_HIGHSPEED) max_data_rate = card->hs_max_data_rate; else max_data_rate = card->max_data_rate; - mmcsd_set_clock(host, max_data_rate); - - /*switch bus width*/ + /*switch bus width and bus mode*/ mmc_select_bus_width(card, ext_csd); - + + mmcsd_set_clock(host, max_data_rate); host->card = card; rt_free(ext_csd); diff --git a/components/drivers/sdio/mmcsd_core.c b/components/drivers/sdio/mmcsd_core.c index 99bc6ce744fece3782bfb19f1b5a39ece5959cc5..a78c78f93d4886be65ef708371d2047c38437826 100644 --- a/components/drivers/sdio/mmcsd_core.c +++ b/components/drivers/sdio/mmcsd_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,6 +13,7 @@ #include #include #include +#include #define DBG_TAG "SDIO" #ifdef RT_SDIO_DEBUG @@ -63,7 +64,7 @@ void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) req->cmd->err = 0; req->cmd->mrq = req; if (req->data) - { + { req->cmd->data = req->data; req->data->err = 0; req->data->mrq = req; @@ -72,12 +73,12 @@ void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) req->data->stop = req->stop; req->stop->err = 0; req->stop->mrq = req; - } + } } host->ops->request(host, req); rt_sem_take(&host->sem_ack, RT_WAITING_FOREVER); - + } while(req->cmd->err && (req->cmd->retries > 0)); @@ -122,7 +123,7 @@ rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host) mmcsd_delay_ms(1); - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { mmcsd_set_chip_select(host, MMCSD_CS_IGNORE); mmcsd_delay_ms(1); @@ -179,7 +180,7 @@ rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid) struct rt_mmcsd_data data; rt_uint32_t *buf = RT_NULL; - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { if (!host->card) return -RT_ERROR; @@ -198,7 +199,7 @@ rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid) } buf = (rt_uint32_t *)rt_malloc(16); - if (!buf) + if (!buf) { LOG_E("allocate memory failed!"); @@ -274,7 +275,7 @@ rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd) } buf = (rt_uint32_t*)rt_malloc(16); - if (!buf) + if (!buf) { LOG_E("allocate memory failed!"); @@ -336,12 +337,12 @@ static rt_int32_t _mmcsd_select_card(struct rt_mmcsd_host *host, cmd.cmd_code = SELECT_CARD; - if (card) + if (card) { cmd.arg = card->rca << 16; cmd.flags = RESP_R1 | CMD_AC; - } - else + } + else { cmd.arg = 0; cmd.flags = RESP_NONE | CMD_AC; @@ -442,7 +443,7 @@ void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, { rt_uint32_t mult; - if (card->card_type == CARD_TYPE_SDIO) + if (card->card_type == CARD_TYPE_SDIO) { data->timeout_ns = 1000000000; /* SDIO card 1s */ data->timeout_clks = 0; @@ -468,7 +469,7 @@ void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, /* * SD cards also have an upper limit on the timeout. */ - if (card->card_type == CARD_TYPE_SD) + if (card->card_type == CARD_TYPE_SD) { rt_uint32_t timeout_us, limit_us; @@ -488,21 +489,21 @@ void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, /* * SDHC cards always use these fixed values. */ - if (timeout_us > limit_us || card->flags & CARD_FLAG_SDHC) + if (timeout_us > limit_us || card->flags & CARD_FLAG_SDHC) { data->timeout_ns = limit_us * 1000; /* SDHC card fixed 250ms */ data->timeout_clks = 0; } } - if (controller_is_spi(card->host)) + if (controller_is_spi(card->host)) { - if (data->flags & DATA_DIR_WRITE) + if (data->flags & DATA_DIR_WRITE) { if (data->timeout_ns < 1000000000) data->timeout_ns = 1000000000; /* 1s */ - } - else + } + else { if (data->timeout_ns < 100000000) data->timeout_ns = 100000000; /* 100ms */ @@ -522,7 +523,7 @@ rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr) ocr &= host->valid_ocr; bit = __rt_ffs(ocr); - if (bit) + if (bit) { bit -= 1; @@ -530,8 +531,8 @@ rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr) host->io_cfg.vdd = bit; mmcsd_set_iocfg(host); - } - else + } + else { LOG_W("host doesn't support card's voltages!"); ocr = 0; @@ -549,7 +550,7 @@ static void mmcsd_power_up(struct rt_mmcsd_host *host) { host->io_cfg.chip_select = MMCSD_CS_HIGH; host->io_cfg.bus_mode = MMCSD_BUSMODE_PUSHPULL; - } + } else { host->io_cfg.chip_select = MMCSD_CS_IGNORE; @@ -580,7 +581,7 @@ static void mmcsd_power_off(struct rt_mmcsd_host *host) { host->io_cfg.clock = 0; host->io_cfg.vdd = 0; - if (!controller_is_spi(host)) + if (!controller_is_spi(host)) { host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN; host->io_cfg.chip_select = MMCSD_CS_IGNORE; @@ -619,7 +620,7 @@ void mmcsd_detect(void *param) rt_uint32_t ocr; rt_int32_t err; - while (1) + while (1) { if (rt_mb_recv(&mmcsd_detect_mb, (rt_ubase_t *)&host, RT_WAITING_FOREVER) == RT_EOK) { @@ -644,7 +645,7 @@ void mmcsd_detect(void *param) * detect SD card */ err = mmcsd_send_app_op_cond(host, 0, &ocr); - if (!err) + if (!err) { if (init_sd(host, ocr)) mmcsd_power_off(host); @@ -652,12 +653,12 @@ void mmcsd_detect(void *param) rt_mb_send(&mmcsd_hotpluge_mb, (rt_ubase_t)host); continue; } - + /* * detect mmc card */ err = mmc_send_op_cond(host, 0, &ocr); - if (!err) + if (!err) { if (init_mmc(host, ocr)) mmcsd_power_off(host); @@ -669,21 +670,21 @@ void mmcsd_detect(void *param) } else { - /* card removed */ - mmcsd_host_lock(host); - if (host->card->sdio_function_num != 0) - { - LOG_W("unsupport sdio card plug out!"); - } - else - { - rt_mmcsd_blk_remove(host->card); - rt_free(host->card); - - host->card = RT_NULL; - } - mmcsd_host_unlock(host); - rt_mb_send(&mmcsd_hotpluge_mb, (rt_ubase_t)host); + /* card removed */ + mmcsd_host_lock(host); + if (host->card->sdio_function_num != 0) + { + LOG_W("unsupport sdio card plug out!"); + } + else + { + rt_mmcsd_blk_remove(host->card); + rt_free(host->card); + + host->card = RT_NULL; + } + mmcsd_host_unlock(host); + rt_mb_send(&mmcsd_hotpluge_mb, (rt_ubase_t)host); } } } @@ -694,7 +695,7 @@ struct rt_mmcsd_host *mmcsd_alloc_host(void) struct rt_mmcsd_host *host; host = rt_malloc(sizeof(struct rt_mmcsd_host)); - if (!host) + if (!host) { LOG_E("alloc host failed"); @@ -702,7 +703,7 @@ struct rt_mmcsd_host *mmcsd_alloc_host(void) } rt_memset(host, 0, sizeof(struct rt_mmcsd_host)); - + strncpy(host->name, "sd", sizeof(host->name)-1); host->max_seg_size = 65535; host->max_dma_segs = 1; host->max_blk_size = 512; @@ -736,16 +737,16 @@ int rt_mmcsd_core_init(void) &mmcsd_hotpluge_mb_pool[0], sizeof(mmcsd_hotpluge_mb_pool) / sizeof(mmcsd_hotpluge_mb_pool[0]), RT_IPC_FLAG_FIFO); RT_ASSERT(ret == RT_EOK); - ret = rt_thread_init(&mmcsd_detect_thread, "mmcsd_detect", mmcsd_detect, RT_NULL, + ret = rt_thread_init(&mmcsd_detect_thread, "mmcsd_detect", mmcsd_detect, RT_NULL, &mmcsd_stack[0], RT_MMCSD_STACK_SIZE, RT_MMCSD_THREAD_PREORITY, 20); - if (ret == RT_EOK) + if (ret == RT_EOK) { rt_thread_startup(&mmcsd_detect_thread); } rt_sdio_init(); - return 0; + return 0; } INIT_PREV_EXPORT(rt_mmcsd_core_init); diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c index 2511f18102aaac4d3220e227ab55c2e50219c8b1..eaab5868885414e0d85dbb090b4b52cce58058c9 100644 --- a/components/drivers/serial/serial.c +++ b/components/drivers/serial/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,10 +38,6 @@ #include #include -#ifdef RT_USING_POSIX_TERMIOS -#include -#endif - /* it's possible the 'getc/putc' is defined by stdio.h in gcc/newlib. */ #ifdef getc #undef getc @@ -65,7 +61,7 @@ static int serial_fops_open(struct dfs_fd *fd) rt_uint16_t flags = 0; rt_device_t device; - device = (rt_device_t)fd->data; + device = (rt_device_t)fd->fnode->data; RT_ASSERT(device != RT_NULL); switch (fd->flags & O_ACCMODE) @@ -88,9 +84,14 @@ static int serial_fops_open(struct dfs_fd *fd) } if ((fd->flags & O_ACCMODE) != O_WRONLY) + { rt_device_set_rx_indicate(device, serial_fops_rx_ind); + } ret = rt_device_open(device, flags); - if (ret == RT_EOK) return 0; + if (ret == RT_EOK) + { + return 0; + } return ret; } @@ -99,7 +100,7 @@ static int serial_fops_close(struct dfs_fd *fd) { rt_device_t device; - device = (rt_device_t)fd->data; + device = (rt_device_t)fd->fnode->data; rt_device_set_rx_indicate(device, RT_NULL); rt_device_close(device); @@ -111,7 +112,7 @@ static int serial_fops_ioctl(struct dfs_fd *fd, int cmd, void *args) { rt_device_t device; - device = (rt_device_t)fd->data; + device = (rt_device_t)fd->fnode->data; switch (cmd) { case FIONREAD: @@ -127,8 +128,9 @@ static int serial_fops_read(struct dfs_fd *fd, void *buf, size_t count) { int size = 0; rt_device_t device; + int wait_ret; - device = (rt_device_t)fd->data; + device = (rt_device_t)fd->fnode->data; do { @@ -137,14 +139,21 @@ static int serial_fops_read(struct dfs_fd *fd, void *buf, size_t count) { if (fd->flags & O_NONBLOCK) { - size = -EAGAIN; break; } - rt_wqueue_wait(&(device->wait_queue), 0, RT_WAITING_FOREVER); + wait_ret = rt_wqueue_wait_interruptible(&(device->wait_queue), 0, RT_WAITING_FOREVER); + if (wait_ret != RT_EOK) + { + break; + } } }while (size <= 0); + if (size < 0) + { + size = 0; + } return size; } @@ -152,7 +161,7 @@ static int serial_fops_write(struct dfs_fd *fd, const void *buf, size_t count) { rt_device_t device; - device = (rt_device_t)fd->data; + device = (rt_device_t)fd->fnode->data; return rt_device_write(device, -1, buf, count); } @@ -163,7 +172,7 @@ static int serial_fops_poll(struct dfs_fd *fd, struct rt_pollreq *req) rt_device_t device; struct rt_serial_device *serial; - device = (rt_device_t)fd->data; + device = (rt_device_t)fd->fnode->data; RT_ASSERT(device != RT_NULL); serial = (struct rt_serial_device *)device; @@ -456,7 +465,7 @@ static void rt_dma_recv_update_put_index(struct rt_serial_device *serial, rt_siz rx_fifo->is_full = RT_TRUE; } } - + if(rx_fifo->is_full == RT_TRUE) { _serial_check_buffer_size(); @@ -575,6 +584,8 @@ static rt_err_t rt_serial_init(struct rt_device *dev) serial->serial_rx = RT_NULL; serial->serial_tx = RT_NULL; + rt_memset(&serial->rx_notify, 0, sizeof(struct rt_device_notify)); + /* apply configuration */ if (serial->ops->configure) result = serial->ops->configure(serial, &serial->config); @@ -611,7 +622,7 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) /* initialize the Rx/Tx structure according to open flag */ if (serial->serial_rx == RT_NULL) - { + { if (oflag & RT_DEVICE_FLAG_INT_RX) { struct rt_serial_rx_fifo* rx_fifo; @@ -630,7 +641,7 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) /* configure low level device */ serial->ops->control(serial, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_RX); } -#ifdef RT_SERIAL_USING_DMA +#ifdef RT_SERIAL_USING_DMA else if (oflag & RT_DEVICE_FLAG_DMA_RX) { if (serial->config.bufsz == 0) { @@ -667,10 +678,14 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) else { if (oflag & RT_DEVICE_FLAG_INT_RX) + { dev->open_flag |= RT_DEVICE_FLAG_INT_RX; + } #ifdef RT_SERIAL_USING_DMA else if (oflag & RT_DEVICE_FLAG_DMA_RX) + { dev->open_flag |= RT_DEVICE_FLAG_DMA_RX; + } #endif /* RT_SERIAL_USING_DMA */ } @@ -715,11 +730,15 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) else { if (oflag & RT_DEVICE_FLAG_INT_TX) + { dev->open_flag |= RT_DEVICE_FLAG_INT_TX; + } #ifdef RT_SERIAL_USING_DMA else if (oflag & RT_DEVICE_FLAG_DMA_TX) + { dev->open_flag |= RT_DEVICE_FLAG_DMA_TX; -#endif /* RT_SERIAL_USING_DMA */ + } +#endif /* RT_SERIAL_USING_DMA */ } /* set stream flag */ @@ -777,7 +796,7 @@ static rt_err_t rt_serial_close(struct rt_device *dev) serial->ops->control(serial, RT_DEVICE_CTRL_CLR_INT, (void *) RT_DEVICE_FLAG_DMA_RX); } #endif /* RT_SERIAL_USING_DMA */ - + if (dev->open_flag & RT_DEVICE_FLAG_INT_TX) { struct rt_serial_tx_fifo* tx_fifo; @@ -838,7 +857,7 @@ static rt_size_t rt_serial_read(struct rt_device *dev, { return _serial_dma_rx(serial, (rt_uint8_t *)buffer, size); } -#endif /* RT_SERIAL_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ return _serial_poll_rx(serial, (rt_uint8_t *)buffer, size); } @@ -859,7 +878,7 @@ static rt_size_t rt_serial_write(struct rt_device *dev, { return _serial_int_tx(serial, (const rt_uint8_t *)buffer, size); } -#ifdef RT_SERIAL_USING_DMA +#ifdef RT_SERIAL_USING_DMA else if (dev->open_flag & RT_DEVICE_FLAG_DMA_TX) { return _serial_dma_tx(serial, (const rt_uint8_t *)buffer, size); @@ -871,103 +890,6 @@ static rt_size_t rt_serial_write(struct rt_device *dev, } } -#ifdef RT_USING_POSIX_TERMIOS -struct speed_baudrate_item -{ - speed_t speed; - int baudrate; -}; - -const static struct speed_baudrate_item _tbl[] = -{ - {B2400, BAUD_RATE_2400}, - {B4800, BAUD_RATE_4800}, - {B9600, BAUD_RATE_9600}, - {B19200, BAUD_RATE_19200}, - {B38400, BAUD_RATE_38400}, - {B57600, BAUD_RATE_57600}, - {B115200, BAUD_RATE_115200}, - {B230400, BAUD_RATE_230400}, - {B460800, BAUD_RATE_460800}, - {B921600, BAUD_RATE_921600}, - {B2000000, BAUD_RATE_2000000}, - {B3000000, BAUD_RATE_3000000}, -}; - -static speed_t _get_speed(int baudrate) -{ - int index; - - for (index = 0; index < sizeof(_tbl)/sizeof(_tbl[0]); index ++) - { - if (_tbl[index].baudrate == baudrate) - return _tbl[index].speed; - } - - return B0; -} - -static int _get_baudrate(speed_t speed) -{ - int index; - - for (index = 0; index < sizeof(_tbl)/sizeof(_tbl[0]); index ++) - { - if (_tbl[index].speed == speed) - return _tbl[index].baudrate; - } - - return 0; -} - -static void _tc_flush(struct rt_serial_device *serial, int queue) -{ - rt_base_t level; - int ch = -1; - struct rt_serial_rx_fifo *rx_fifo = RT_NULL; - struct rt_device *device = RT_NULL; - - RT_ASSERT(serial != RT_NULL); - - device = &(serial->parent); - rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx; - - switch(queue) - { - case TCIFLUSH: - case TCIOFLUSH: - - RT_ASSERT(rx_fifo != RT_NULL); - - if((device->open_flag & RT_DEVICE_FLAG_INT_RX) || (device->open_flag & RT_DEVICE_FLAG_DMA_RX)) - { - RT_ASSERT(RT_NULL != rx_fifo); - level = rt_hw_interrupt_disable(); - rt_memset(rx_fifo->buffer, 0, serial->config.bufsz); - rx_fifo->put_index = 0; - rx_fifo->get_index = 0; - rx_fifo->is_full = RT_FALSE; - rt_hw_interrupt_enable(level); - } - else - { - while (1) - { - ch = serial->ops->getc(serial); - if (ch == -1) break; - } - } - - break; - - case TCOFLUSH: - break; - } - -} - -#endif - static rt_err_t rt_serial_control(struct rt_device *dev, int cmd, void *args) @@ -1010,98 +932,19 @@ static rt_err_t rt_serial_control(struct rt_device *dev, break; -#ifdef RT_USING_POSIX_TERMIOS - case TCGETA: + case RT_DEVICE_CTRL_NOTIFY_SET: + if (args) { - struct termios *tio = (struct termios*)args; - if (tio == RT_NULL) return -RT_EINVAL; - - tio->c_iflag = 0; - tio->c_oflag = 0; - tio->c_lflag = 0; - - /* update oflag for console device */ - if (rt_console_get_device() == dev) - tio->c_oflag = OPOST | ONLCR; - - /* set cflag */ - tio->c_cflag = 0; - if (serial->config.data_bits == DATA_BITS_5) - tio->c_cflag = CS5; - else if (serial->config.data_bits == DATA_BITS_6) - tio->c_cflag = CS6; - else if (serial->config.data_bits == DATA_BITS_7) - tio->c_cflag = CS7; - else if (serial->config.data_bits == DATA_BITS_8) - tio->c_cflag = CS8; - - if (serial->config.stop_bits == STOP_BITS_2) - tio->c_cflag |= CSTOPB; - - if (serial->config.parity == PARITY_EVEN) - tio->c_cflag |= PARENB; - else if (serial->config.parity == PARITY_ODD) - tio->c_cflag |= (PARODD | PARENB); - - cfsetospeed(tio, _get_speed(serial->config.baud_rate)); + rt_memcpy(&serial->rx_notify, args, sizeof(struct rt_device_notify)); } break; - case TCSETAW: - case TCSETAF: - case TCSETA: - { - int baudrate; - struct serial_configure config; - - struct termios *tio = (struct termios*)args; - if (tio == RT_NULL) return -RT_EINVAL; - - config = serial->config; - - baudrate = _get_baudrate(cfgetospeed(tio)); - config.baud_rate = baudrate; - - switch (tio->c_cflag & CSIZE) - { - case CS5: - config.data_bits = DATA_BITS_5; - break; - case CS6: - config.data_bits = DATA_BITS_6; - break; - case CS7: - config.data_bits = DATA_BITS_7; - break; - default: - config.data_bits = DATA_BITS_8; - break; - } - - if (tio->c_cflag & CSTOPB) config.stop_bits = STOP_BITS_2; - else config.stop_bits = STOP_BITS_1; - - if (tio->c_cflag & PARENB) - { - if (tio->c_cflag & PARODD) config.parity = PARITY_ODD; - else config.parity = PARITY_EVEN; - } - else config.parity = PARITY_NONE; - - serial->ops->configure(serial, &config); - } - break; - case TCFLSH: + case RT_DEVICE_CTRL_CONSOLE_OFLAG: + if (args) { - int queue = (int)args; - - _tc_flush(serial, queue); + *(rt_uint16_t*)args = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM; } - - break; - case TCXONC: break; -#endif #ifdef RT_USING_POSIX case FIONREAD: { @@ -1126,7 +969,7 @@ static rt_err_t rt_serial_control(struct rt_device *dev, } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops serial_ops = +const static struct rt_device_ops serial_ops = { rt_serial_init, rt_serial_open, @@ -1236,6 +1079,12 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) serial->parent.rx_indicate(&serial->parent, rx_length); } } + + if (serial->rx_notify.notify) + { + serial->rx_notify.notify(serial->rx_notify.dev); + } + break; } case RT_SERIAL_EVENT_TX_DONE: @@ -1315,3 +1164,4 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) #endif /* RT_SERIAL_USING_DMA */ } } + diff --git a/components/drivers/spi/spi_flash_sfud.c b/components/drivers/spi/spi_flash_sfud.c index 2333c9ccb3848456a2e2523b082dc6a95d6e0072..684d52050118d62e2c7e1e102a6d7cc8bc59aadc 100644 --- a/components/drivers/spi/spi_flash_sfud.c +++ b/components/drivers/spi/spi_flash_sfud.c @@ -9,6 +9,7 @@ */ #include +#include #include #include "spi_flash.h" #include "spi_flash_sfud.h" diff --git a/components/drivers/src/completion.c b/components/drivers/src/completion.c index 9e461e49ce51e31f1437f02398076f9e83e590f1..24b85e198e4bd1919509677f99fe22be654efc1c 100644 --- a/components/drivers/src/completion.c +++ b/components/drivers/src/completion.c @@ -55,7 +55,7 @@ rt_err_t rt_completion_wait(struct rt_completion *completion, thread->error = RT_EOK; /* suspend thread */ - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); /* add to suspended list */ rt_list_insert_before(&(completion->suspended_list), &(thread->tlist)); diff --git a/components/drivers/src/dataqueue.c b/components/drivers/src/dataqueue.c index bfe8e1257394da38b000e7758ecfc94c30e39f91..3f481a308ec986f85ec08a1de97fbb0470f74c49 100644 --- a/components/drivers/src/dataqueue.c +++ b/components/drivers/src/dataqueue.c @@ -62,7 +62,7 @@ rt_err_t rt_data_queue_push(struct rt_data_queue *queue, rt_ubase_t level; rt_thread_t thread; rt_err_t result; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); @@ -85,9 +85,9 @@ rt_err_t rt_data_queue_push(struct rt_data_queue *queue, /* reset thread error number */ thread->error = RT_EOK; - + /* suspend thread on the push list */ - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); rt_list_insert_before(&(queue->suspended_push_list), &(thread->tlist)); /* start timer */ if (timeout > 0) @@ -155,13 +155,13 @@ RTM_EXPORT(rt_data_queue_push); rt_err_t rt_data_queue_pop(struct rt_data_queue *queue, const void** data_ptr, - rt_size_t *size, + rt_size_t *size, rt_int32_t timeout) { rt_ubase_t level; rt_thread_t thread; rt_err_t result; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); RT_ASSERT(data_ptr != RT_NULL); @@ -185,9 +185,9 @@ rt_err_t rt_data_queue_pop(struct rt_data_queue *queue, /* reset thread error number */ thread->error = RT_EOK; - + /* suspend thread on the pop list */ - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); rt_list_insert_before(&(queue->suspended_pop_list), &(thread->tlist)); /* start timer */ if (timeout > 0) @@ -269,11 +269,11 @@ rt_err_t rt_data_queue_peak(struct rt_data_queue *queue, rt_size_t *size) { rt_ubase_t level; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); - if (queue->is_empty) + if (queue->is_empty) { return -RT_EEMPTY; } @@ -293,7 +293,7 @@ void rt_data_queue_reset(struct rt_data_queue *queue) { rt_ubase_t level; struct rt_thread *thread; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); @@ -303,9 +303,9 @@ void rt_data_queue_reset(struct rt_data_queue *queue) queue->put_index = 0; queue->is_empty = 1; queue->is_full = 0; - + rt_hw_interrupt_enable(level); - + rt_enter_critical(); /* wakeup all suspend threads */ @@ -375,7 +375,7 @@ rt_err_t rt_data_queue_deinit(struct rt_data_queue *queue) level = rt_hw_interrupt_disable(); queue->magic = 0; rt_hw_interrupt_enable(level); - + rt_free(queue->queue); return RT_EOK; @@ -386,7 +386,7 @@ rt_uint16_t rt_data_queue_len(struct rt_data_queue *queue) { rt_ubase_t level; rt_int16_t len; - + RT_ASSERT(queue != RT_NULL); RT_ASSERT(queue->magic == DATAQUEUE_MAGIC); @@ -405,7 +405,7 @@ rt_uint16_t rt_data_queue_len(struct rt_data_queue *queue) { len = queue->size + queue->put_index - queue->get_index; } - + rt_hw_interrupt_enable(level); return len; diff --git a/components/drivers/src/pipe.c b/components/drivers/src/pipe.c index 2a7e143f6cdf8e7cbc0783dba4046d3cb6bf5f0b..284104511bd1bade226db82cd59355c30d8aaf86 100644 --- a/components/drivers/src/pipe.c +++ b/components/drivers/src/pipe.c @@ -16,20 +16,43 @@ #include #include #include +#include + +/* check RT_UNAMED_PIPE_NUMBER */ + +#ifndef RT_UNAMED_PIPE_NUMBER +#define RT_UNAMED_PIPE_NUMBER 64 +#endif + +#define BITS(x) _BITS(x) +#define _BITS(x) (sizeof(#x) - 1) + +struct check_rt_unamed_pipe_number +{ + /* -4 for "pipe" prefix */ + /* -1 for '\0' postfix */ + char _check[RT_NAME_MAX - 4 - 1 - BITS(RT_UNAMED_PIPE_NUMBER)]; +}; + +/* check end */ + +static void *resoure_id[RT_UNAMED_PIPE_NUMBER]; +static resource_id_t id_mgr = RESOURCE_ID_INIT(RT_UNAMED_PIPE_NUMBER, resoure_id); static int pipe_fops_open(struct dfs_fd *fd) { int rc = 0; - rt_device_t device; rt_pipe_t *pipe; - pipe = (rt_pipe_t *)fd->data; - if (!pipe) return -1; + pipe = (rt_pipe_t *)fd->fnode->data; + if (!pipe) + { + return -1; + } - device = &(pipe->parent); - rt_mutex_take(&(pipe->lock), RT_WAITING_FOREVER); + rt_mutex_take(&pipe->lock, RT_WAITING_FOREVER); - if (device->ref_count == 0) + if (fd->fnode->ref_count == 1) { pipe->fifo = rt_ringbuffer_create(pipe->bufsz); if (pipe->fifo == RT_NULL) @@ -39,23 +62,8 @@ static int pipe_fops_open(struct dfs_fd *fd) } } - switch (fd->flags & O_ACCMODE) - { - case O_RDONLY: - pipe->readers ++; - break; - case O_WRONLY: - pipe->writers ++; - break; - case O_RDWR: - pipe->readers ++; - pipe->writers ++; - break; - } - device->ref_count ++; - __exit: - rt_mutex_release(&(pipe->lock)); + rt_mutex_release(&pipe->lock); return rc; } @@ -65,47 +73,27 @@ static int pipe_fops_close(struct dfs_fd *fd) rt_device_t device; rt_pipe_t *pipe; - pipe = (rt_pipe_t *)fd->data; - if (!pipe) return -1; - - device = &(pipe->parent); - rt_mutex_take(&(pipe->lock), RT_WAITING_FOREVER); - - switch (fd->flags & O_ACCMODE) - { - case O_RDONLY: - pipe->readers --; - break; - case O_WRONLY: - pipe->writers --; - break; - case O_RDWR: - pipe->readers --; - pipe->writers --; - break; - } - - if (pipe->writers == 0) + pipe = (rt_pipe_t *)fd->fnode->data; + if (!pipe) { - rt_wqueue_wakeup(&(pipe->reader_queue), (void*)(POLLIN | POLLERR | POLLHUP)); + return -1; } - if (pipe->readers == 0) - { - rt_wqueue_wakeup(&(pipe->writer_queue), (void*)(POLLOUT | POLLERR | POLLHUP)); - } + device = &pipe->parent; + rt_mutex_take(&pipe->lock, RT_WAITING_FOREVER); - if (device->ref_count == 1) + if (fd->fnode->ref_count == 1) { if (pipe->fifo != RT_NULL) + { rt_ringbuffer_destroy(pipe->fifo); + } pipe->fifo = RT_NULL; } - device->ref_count --; - rt_mutex_release(&(pipe->lock)); + rt_mutex_release(&pipe->lock); - if (device->ref_count == 0 && pipe->is_named == RT_FALSE) + if (fd->fnode->ref_count == 1 && pipe->is_named == RT_FALSE) { /* delete the unamed pipe */ rt_pipe_delete(device->parent.name); @@ -119,7 +107,7 @@ static int pipe_fops_ioctl(struct dfs_fd *fd, int cmd, void *args) rt_pipe_t *pipe; int ret = 0; - pipe = (rt_pipe_t *)fd->data; + pipe = (rt_pipe_t *)fd->fnode->data; switch (cmd) { @@ -142,21 +130,13 @@ static int pipe_fops_read(struct dfs_fd *fd, void *buf, size_t count) int len = 0; rt_pipe_t *pipe; - pipe = (rt_pipe_t *)fd->data; + pipe = (rt_pipe_t *)fd->fnode->data; /* no process has the pipe open for writing, return end-of-file */ - if (pipe->writers == 0) - return 0; - - rt_mutex_take(&(pipe->lock), RT_WAITING_FOREVER); + rt_mutex_take(&pipe->lock, RT_WAITING_FOREVER); while (1) { - if (pipe->writers == 0) - { - goto out; - } - len = rt_ringbuffer_get(pipe->fifo, buf, count); if (len > 0) @@ -172,14 +152,14 @@ static int pipe_fops_read(struct dfs_fd *fd, void *buf, size_t count) } rt_mutex_release(&pipe->lock); - rt_wqueue_wakeup(&(pipe->writer_queue), (void*)POLLOUT); - rt_wqueue_wait(&(pipe->reader_queue), 0, -1); - rt_mutex_take(&(pipe->lock), RT_WAITING_FOREVER); + rt_wqueue_wakeup(&pipe->writer_queue, (void*)POLLOUT); + rt_wqueue_wait(&pipe->reader_queue, 0, -1); + rt_mutex_take(&pipe->lock, RT_WAITING_FOREVER); } } /* wakeup writer */ - rt_wqueue_wakeup(&(pipe->writer_queue), (void*)POLLOUT); + rt_wqueue_wakeup(&pipe->writer_queue, (void*)POLLOUT); out: rt_mutex_release(&pipe->lock); @@ -194,29 +174,18 @@ static int pipe_fops_write(struct dfs_fd *fd, const void *buf, size_t count) int ret = 0; uint8_t *pbuf; - pipe = (rt_pipe_t *)fd->data; - - if (pipe->readers == 0) - { - ret = -EPIPE; - goto out; - } + pipe = (rt_pipe_t *)fd->fnode->data; if (count == 0) + { return 0; + } pbuf = (uint8_t*)buf; rt_mutex_take(&pipe->lock, -1); while (1) { - if (pipe->readers == 0) - { - if (ret == 0) - ret = -EPIPE; - break; - } - len = rt_ringbuffer_put(pipe->fifo, pbuf, count - ret); ret += len; pbuf += len; @@ -240,19 +209,18 @@ static int pipe_fops_write(struct dfs_fd *fd, const void *buf, size_t count) } rt_mutex_release(&pipe->lock); - rt_wqueue_wakeup(&(pipe->reader_queue), (void*)POLLIN); + rt_wqueue_wakeup(&pipe->reader_queue, (void*)POLLIN); /* pipe full, waiting on suspended write list */ - rt_wqueue_wait(&(pipe->writer_queue), 0, -1); + rt_wqueue_wait(&pipe->writer_queue, 0, -1); rt_mutex_take(&pipe->lock, -1); } rt_mutex_release(&pipe->lock); if (wakeup) { - rt_wqueue_wakeup(&(pipe->reader_queue), (void*)POLLIN); + rt_wqueue_wakeup(&pipe->reader_queue, (void*)POLLIN); } -out: return ret; } @@ -261,10 +229,10 @@ static int pipe_fops_poll(struct dfs_fd *fd, rt_pollreq_t *req) int mask = 0; rt_pipe_t *pipe; int mode = 0; - pipe = (rt_pipe_t *)fd->data; + pipe = (rt_pipe_t *)fd->fnode->data; - rt_poll_add(&(pipe->reader_queue), req); - rt_poll_add(&(pipe->writer_queue), req); + rt_poll_add(&pipe->reader_queue, req); + rt_poll_add(&pipe->writer_queue, req); switch (fd->flags & O_ACCMODE) { @@ -285,10 +253,6 @@ static int pipe_fops_poll(struct dfs_fd *fd, rt_pollreq_t *req) { mask |= POLLIN; } - if (pipe->writers == 0) - { - mask |= POLLHUP; - } } if (mode & 2) @@ -297,10 +261,6 @@ static int pipe_fops_poll(struct dfs_fd *fd, rt_pollreq_t *req) { mask |= POLLOUT; } - if (pipe->readers == 0) - { - mask |= POLLERR; - } } return mask; @@ -330,8 +290,8 @@ rt_err_t rt_pipe_open (rt_device_t device, rt_uint16_t oflag) ret = -RT_EINVAL; goto __exit; } - - rt_mutex_take(&(pipe->lock), RT_WAITING_FOREVER); + + rt_mutex_take(&pipe->lock, RT_WAITING_FOREVER); if (pipe->fifo == RT_NULL) { @@ -342,7 +302,7 @@ rt_err_t rt_pipe_open (rt_device_t device, rt_uint16_t oflag) } } - rt_mutex_release(&(pipe->lock)); + rt_mutex_release(&pipe->lock); __exit: return ret; @@ -352,16 +312,16 @@ rt_err_t rt_pipe_close (rt_device_t device) { rt_pipe_t *pipe = (rt_pipe_t *)device; - if (device == RT_NULL) return -RT_EINVAL; - rt_mutex_take(&(pipe->lock), RT_WAITING_FOREVER); - - if (device->ref_count == 1) + if (device == RT_NULL) { - rt_ringbuffer_destroy(pipe->fifo); - pipe->fifo = RT_NULL; + return -RT_EINVAL; } + rt_mutex_take(&pipe->lock, RT_WAITING_FOREVER); - rt_mutex_release(&(pipe->lock)); + rt_ringbuffer_destroy(pipe->fifo); + pipe->fifo = RT_NULL; + + rt_mutex_release(&pipe->lock); return RT_EOK; } @@ -377,15 +337,21 @@ rt_size_t rt_pipe_read (rt_device_t device, rt_off_t pos, void *buffer, rt_siz rt_set_errno(-EINVAL); return 0; } - if (count == 0) return 0; + if (count == 0) + { + return 0; + } pbuf = (uint8_t*)buffer; - rt_mutex_take(&(pipe->lock), RT_WAITING_FOREVER); + rt_mutex_take(&pipe->lock, RT_WAITING_FOREVER); while (read_bytes < count) { int len = rt_ringbuffer_get(pipe->fifo, &pbuf[read_bytes], count - read_bytes); - if (len <= 0) break; + if (len <= 0) + { + break; + } read_bytes += len; } @@ -405,7 +371,10 @@ rt_size_t rt_pipe_write (rt_device_t device, rt_off_t pos, const void *buffer, rt_set_errno(-EINVAL); return 0; } - if (count == 0) return 0; + if (count == 0) + { + return 0; + } pbuf = (uint8_t*)buffer; rt_mutex_take(&pipe->lock, -1); @@ -413,7 +382,10 @@ rt_size_t rt_pipe_write (rt_device_t device, rt_off_t pos, const void *buffer, while (write_bytes < count) { int len = rt_ringbuffer_put(pipe->fifo, &pbuf[write_bytes], count - write_bytes); - if (len <= 0) break; + if (len <= 0) + { + break; + } write_bytes += len; } @@ -449,14 +421,17 @@ rt_pipe_t *rt_pipe_create(const char *name, int bufsz) rt_memset(pipe, 0, sizeof(rt_pipe_t)); pipe->is_named = RT_TRUE; /* initialize as a named pipe */ - rt_mutex_init(&(pipe->lock), name, RT_IPC_FLAG_FIFO); - rt_wqueue_init(&(pipe->reader_queue)); - rt_wqueue_init(&(pipe->writer_queue)); +#ifdef RT_USING_POSIX + pipe->pipeno = -1; +#endif + rt_mutex_init(&pipe->lock, name, RT_IPC_FLAG_FIFO); + rt_wqueue_init(&pipe->reader_queue); + rt_wqueue_init(&pipe->writer_queue); RT_ASSERT(bufsz < 0xFFFF); pipe->bufsz = bufsz; - dev = &(pipe->parent); + dev = &pipe->parent; dev->type = RT_Device_Class_Pipe; #ifdef RT_USING_DEVICE_OPS dev->ops = &pipe_ops; @@ -472,8 +447,12 @@ rt_pipe_t *rt_pipe_create(const char *name, int bufsz) dev->rx_indicate = RT_NULL; dev->tx_complete = RT_NULL; - if (rt_device_register(&(pipe->parent), name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE) != 0) + if (rt_device_register(&pipe->parent, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE) != 0) { + rt_mutex_detach(&pipe->lock); +#ifdef RT_USING_POSIX + resource_id_put(&id_mgr, pipe->pipeno); +#endif rt_free(pipe); return RT_NULL; } @@ -496,18 +475,16 @@ int rt_pipe_delete(const char *name) { rt_pipe_t *pipe; - if (device->ref_count != 0) - { - return -RT_EBUSY; - } - pipe = (rt_pipe_t *)device; - rt_mutex_detach(&(pipe->lock)); + rt_mutex_detach(&pipe->lock); +#ifdef RT_USING_POSIX + resource_id_put(&id_mgr, pipe->pipeno); +#endif rt_device_unregister(device); /* close fifo ringbuffer */ - if (pipe->fifo) + if (pipe->fifo) { rt_ringbuffer_destroy(pipe->fifo); pipe->fifo = RT_NULL; @@ -533,17 +510,24 @@ int pipe(int fildes[2]) rt_pipe_t *pipe; char dname[8]; char dev_name[32]; - static int pipeno = 0; + int pipeno = 0; - rt_snprintf(dname, sizeof(dname), "pipe%d", pipeno++); + pipeno = resource_id_get(&id_mgr); + if (pipeno == -1) + { + return -1; + } + rt_snprintf(dname, sizeof(dname), "pipe%d", pipeno); pipe = rt_pipe_create(dname, PIPE_BUFSZ); if (pipe == RT_NULL) { + resource_id_put(&id_mgr, pipeno); return -1; } pipe->is_named = RT_FALSE; /* unamed pipe */ + pipe->pipeno = pipeno; rt_snprintf(dev_name, sizeof(dev_name), "/dev/%s", dname); fildes[0] = open(dev_name, O_RDONLY, 0); if (fildes[0] < 0) @@ -564,7 +548,7 @@ int pipe(int fildes[2]) int mkfifo(const char *path, mode_t mode) { rt_pipe_t *pipe; - + pipe = rt_pipe_create(path, PIPE_BUFSZ); if (pipe == RT_NULL) { diff --git a/components/drivers/src/ringblk_buf.c b/components/drivers/src/ringblk_buf.c index 7d83149c5ebe5ff45e2d0dea9d6d5c0c8b76f1d2..1557f2bbcfd2977d1d9e9f65c7afcc6235ab385d 100644 --- a/components/drivers/src/ringblk_buf.c +++ b/components/drivers/src/ringblk_buf.c @@ -6,11 +6,13 @@ * Change Logs: * Date Author Notes * 2018-08-25 armink the first version + * 2021-02-19 lizhirui repaired compilation error in riscv64-unknown-elf that is NULL undeclared */ #include #include #include +#include /** * ring block buffer object initialization diff --git a/components/drivers/src/waitqueue.c b/components/drivers/src/waitqueue.c index 02240edbdfdfa79ac55c1394cc31991b9597195d..0acd360fb2ecb50aea804078f32500a94f46366c 100644 --- a/components/drivers/src/waitqueue.c +++ b/components/drivers/src/waitqueue.c @@ -74,13 +74,14 @@ void rt_wqueue_wakeup(rt_wqueue_t *queue, void *key) rt_schedule(); } -int rt_wqueue_wait(rt_wqueue_t *queue, int condition, int msec) +static int _rt_wqueue_wait(rt_wqueue_t *queue, int condition, int msec, int suspend_flag) { int tick; rt_thread_t tid = rt_thread_self(); rt_timer_t tmr = &(tid->thread_timer); struct rt_wqueue_node __wait; rt_base_t level; + rt_err_t ret; /* current context checking */ RT_DEBUG_NOT_IN_INTERRUPT; @@ -102,8 +103,14 @@ int rt_wqueue_wait(rt_wqueue_t *queue, int condition, int msec) goto __exit_wakeup; } + ret = rt_thread_suspend_with_flag(tid, suspend_flag); + if (ret != RT_EOK) + { + rt_hw_interrupt_enable(level); + /* suspend failed */ + return -RT_EINTR; + } rt_wqueue_add(queue, &__wait); - rt_thread_suspend(tid); /* start timer */ if (tick != RT_WAITING_FOREVER) @@ -128,3 +135,18 @@ __exit_wakeup: return 0; } + +int rt_wqueue_wait(rt_wqueue_t *queue, int condition, int msec) +{ + return _rt_wqueue_wait(queue, condition, msec, RT_UNINTERRUPTIBLE); +} + +int rt_wqueue_wait_killable(rt_wqueue_t *queue, int condition, int msec) +{ + return _rt_wqueue_wait(queue, condition, msec, RT_KILLABLE); +} + +int rt_wqueue_wait_interruptible(rt_wqueue_t *queue, int condition, int msec) +{ + return _rt_wqueue_wait(queue, condition, msec, RT_INTERRUPTIBLE); +} diff --git a/components/drivers/src/workqueue.c b/components/drivers/src/workqueue.c index 2e0280df3a747ca4c09950676781527dc6f29295..564dde78f29d5d243281512e0642d72b250cb02a 100644 --- a/components/drivers/src/workqueue.c +++ b/components/drivers/src/workqueue.c @@ -61,7 +61,7 @@ static void _workqueue_thread_entry(void *parameter) if (rt_list_isempty(&(queue->work_list))) { /* no software timer exist, suspend self. */ - rt_thread_suspend(rt_thread_self()); + rt_thread_suspend_with_flag(rt_thread_self(), RT_UNINTERRUPTIBLE); rt_schedule(); } diff --git a/components/drivers/touch/touch.h b/components/drivers/touch/touch.h index c33fe175201dca7eb5a2d63c4853e0cddcb0577f..f9a3abb23f1719b2cb87e285bc4335796e9672b1 100644 --- a/components/drivers/touch/touch.h +++ b/components/drivers/touch/touch.h @@ -13,6 +13,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { diff --git a/components/drivers/tty/SConscript b/components/drivers/tty/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..3c561f4e46165e19cb3ebbc29e06e56a3c11857c --- /dev/null +++ b/components/drivers/tty/SConscript @@ -0,0 +1,10 @@ +from building import * + +# The set of source files associated with this SConscript file. +src = Glob('*.c') +cwd = GetCurrentDir() +CPPPATH = [cwd + "/include"] + +group = DefineGroup('tty', src, depend = ['RT_USING_LWP', 'RT_USING_TTY'], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/drivers/tty/console.c b/components/drivers/tty/console.c new file mode 100644 index 0000000000000000000000000000000000000000..58368ec61a4b491d904b0ee58b1077bcefe4736d --- /dev/null +++ b/components/drivers/tty/console.c @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021.12.07 linzhenxing first version + */ +#include +#include +#include +#include + +#define DBG_TAG "CONSOLE" +#ifdef RT_TTY_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* RT_TTY_DEBUG */ +#include + +static struct tty_struct console_driver; + +static void console_rx_notify(struct rt_device *dev) +{ + struct tty_struct *console = NULL; + int len = 0; + int lens = 0; + char ch = 0; + char buf[1024] = {0}; + + console = (struct tty_struct *)dev; + RT_ASSERT(console != RT_NULL); + + while (1) + { + len = rt_device_read(console->driver, -1, &ch, 1); + if (len == 0) + { + break; + } + lens += len; + buf[lens-1] = ch; + if (lens > 1024) + { + break; + } + } + + if (console->ldisc->ops->receive_buf) + { + console->ldisc->ops->receive_buf((struct tty_struct *)console, buf, lens); + } +} + +struct tty_struct *console_tty_get(void) +{ + return &console_driver; +} + +static void iodev_close(struct tty_struct *console) +{ + struct rt_device_notify rx_notify; + + rx_notify.notify = RT_NULL; + rx_notify.dev = RT_NULL; + + /* clear notify */ + rt_device_control(console->driver, RT_DEVICE_CTRL_NOTIFY_SET, &rx_notify); + rt_device_close(console->driver); +} + +static rt_err_t iodev_open(struct tty_struct *console) +{ + rt_err_t ret = RT_EOK; + struct rt_device_notify rx_notify; + rt_uint16_t oflags = 0; + + rt_device_control(console->driver, RT_DEVICE_CTRL_CONSOLE_OFLAG, &oflags); + + ret = rt_device_open(console->driver, oflags); + if (ret != RT_EOK) + { + return RT_ERROR; + } + + rx_notify.notify = console_rx_notify; + rx_notify.dev = (struct rt_device *)console; + rt_device_control(console->driver, RT_DEVICE_CTRL_NOTIFY_SET, &rx_notify); + return RT_EOK; +} + +struct rt_device *console_get_iodev(void) +{ + rt_base_t level = 0; + struct rt_device *iodev = RT_NULL; + + level = rt_hw_interrupt_disable(); + iodev = console_driver.driver; + rt_hw_interrupt_enable(level); + return iodev; +} + +struct rt_device *console_set_iodev(struct rt_device *iodev) +{ + rt_base_t level = 0; + struct rt_device *io_before = RT_NULL; + struct tty_struct *console = RT_NULL; + + RT_ASSERT(iodev != RT_NULL); + + console = &console_driver; + + level = rt_hw_interrupt_disable(); + + RT_ASSERT(console->init_flag >= TTY_INIT_FLAG_REGED); + + io_before = console->driver; + + if (iodev == io_before) + { + goto exit; + } + + if (console->init_flag >= TTY_INIT_FLAG_INITED) + { + /* close old device */ + iodev_close(console); + } + + console->driver = iodev; + + if (console->init_flag >= TTY_INIT_FLAG_INITED) + { + rt_err_t ret; + /* open new device */ + ret = iodev_open(console); + RT_ASSERT(ret == RT_EOK); + } + +exit: + rt_hw_interrupt_enable(level); + return io_before; +} + +/* RT-Thread Device Interface */ +/* + * This function initializes console device. + */ +static rt_err_t rt_console_init(struct rt_device *dev) +{ + rt_base_t level = 0; + rt_err_t result = RT_EOK; + struct tty_struct *console = RT_NULL; + + RT_ASSERT(dev != RT_NULL); + + console = (struct tty_struct *)dev; + + level = rt_hw_interrupt_disable(); + + RT_ASSERT(console->init_flag == TTY_INIT_FLAG_REGED); + + result = iodev_open(console); + if (result != RT_EOK) + { + goto exit; + } + + console->init_flag = TTY_INIT_FLAG_INITED; +exit: + rt_hw_interrupt_enable(level); + return result; +} + +static rt_err_t rt_console_open(struct rt_device *dev, rt_uint16_t oflag) +{ + rt_err_t result = RT_EOK; + struct tty_struct *console = RT_NULL; + + RT_ASSERT(dev != RT_NULL); + console = (struct tty_struct *)dev; + RT_ASSERT(console != RT_NULL); + RT_ASSERT(console->init_flag == TTY_INIT_FLAG_INITED); + return result; +} + +static rt_err_t rt_console_close(struct rt_device *dev) +{ + rt_err_t result = RT_EOK; + struct tty_struct *console = RT_NULL; + + console = (struct tty_struct *)dev; + RT_ASSERT(console != RT_NULL); + RT_ASSERT(console->init_flag == TTY_INIT_FLAG_INITED); + return result; +} + +static rt_size_t rt_console_read(struct rt_device *dev, + rt_off_t pos, + void *buffer, + rt_size_t size) +{ + rt_size_t len = 0; + return len; +} + +static rt_size_t rt_console_write(struct rt_device *dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + rt_base_t level = 0; + rt_size_t len = 0; + struct tty_struct *console = RT_NULL; + + console = (struct tty_struct *)dev; + RT_ASSERT(console != RT_NULL); + RT_ASSERT(console->init_flag == TTY_INIT_FLAG_INITED); + + level = rt_hw_interrupt_disable(); + len = rt_device_write((struct rt_device *)console->driver, -1, buffer, size); + rt_hw_interrupt_enable(level); + + return len; +} + +static rt_err_t rt_console_control(rt_device_t dev, int cmd, void *args) +{ + rt_base_t level = 0; + rt_size_t len = 0; + struct tty_struct *console = RT_NULL; + + console = (struct tty_struct *)dev; + RT_ASSERT(console != RT_NULL); + RT_ASSERT(console->init_flag == TTY_INIT_FLAG_INITED); + + level = rt_hw_interrupt_disable(); + len = rt_device_control((struct rt_device *)console->driver, cmd, args); + rt_hw_interrupt_enable(level); + + return len; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops console_ops = +{ + rt_console_init, + rt_console_open, + rt_console_close, + rt_console_read, + rt_console_write, + rt_console_control, +}; +#endif +/* + * console register + */ + static struct dfs_file_ops con_fops; +rt_err_t console_register(const char *name, struct rt_device *iodev) +{ + rt_base_t level = 0; + rt_err_t ret = RT_EOK; + struct rt_device *device = RT_NULL; + struct tty_struct *console = &console_driver; + + level = rt_hw_interrupt_disable(); + RT_ASSERT(console->init_flag == TTY_INIT_FLAG_NONE); + RT_ASSERT(iodev != RT_NULL); + + device = &(console->parent); + + device->type = RT_Device_Class_Char; + +#ifdef RT_USING_DEVICE_OPS + device->ops = &console_ops; +#else + device->init = rt_console_init; + device->open = rt_console_open; + device->close = rt_console_close; + device->read = rt_console_read; + device->write = rt_console_write; + device->control = rt_console_control; +#endif + + + /* register a character device */ + ret = rt_device_register(device, name, 0); + if (ret != RT_EOK) + { + LOG_E("console driver register fail\n"); + goto exit; + } + +#ifdef RT_USING_POSIX + /* set fops */ + console_set_fops(&con_fops); + device->fops = &con_fops; +#endif + console->type = TTY_DRIVER_TYPE_CONSOLE; + console->subtype = SERIAL_TYPE_NORMAL; + console->driver = iodev; + + console->pgrp = -1; + console->session = -1; + console->foreground = RT_NULL; + rt_wqueue_init(&console->wait_queue); + + tty_ldisc_init(console); + +extern struct termios tty_std_termios; + console->init_termios = tty_std_termios; + console->init_termios.c_cflag = + B9600 | CS8 | CREAD | HUPCL; /* is normally B9600 default... */ + console->init_termios.__c_ispeed = 9600; + console->init_termios.__c_ospeed = 9600; + + console_ldata_init(console); + console->init_flag = TTY_INIT_FLAG_REGED; +exit: + rt_hw_interrupt_enable(level); + return ret; +} diff --git a/components/drivers/tty/include/console.h b/components/drivers/tty/include/console.h new file mode 100644 index 0000000000000000000000000000000000000000..779d816d4b14fc050bb510a5e708f7a8dc0239ba --- /dev/null +++ b/components/drivers/tty/include/console.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021.12.07 linzhenxing first version + */ +#ifndef __CONSOLE_ +#define __CONSOLE_ +#include +#include "tty.h" + +struct tty_struct *console_tty_get(void); +struct rt_device *console_get_iodev(void); +struct rt_device *console_set_iodev(struct rt_device *iodev); +rt_err_t console_register(const char *name, struct rt_device *iodev); +#endif diff --git a/components/libc/termios/posix_termios.h b/components/drivers/tty/include/posix_termios.h similarity index 67% rename from components/libc/termios/posix_termios.h rename to components/drivers/tty/include/posix_termios.h index c61191b7dcf5d6b0980e6f502f4f7520487d01ff..6f4caa230c31e529f8fc6701c2c7f067972beb37 100644 --- a/components/libc/termios/posix_termios.h +++ b/components/drivers/tty/include/posix_termios.h @@ -1,14 +1,15 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017/08/30 Bernard The first version + * 2021/12/10 linzhenxing put tty system */ -#ifndef TERMIOS_H__ -#define TERMIOS_H__ +#ifndef KTERMIOS_H__ +#define KTERMIOS_H__ #include #include @@ -34,6 +35,7 @@ struct termios { speed_t __c_ospeed; }; +/* c_cc characters */ #define VINTR 0 #define VQUIT 1 #define VERASE 2 @@ -52,6 +54,7 @@ struct termios { #define VLNEXT 15 #define VEOL2 16 +/* c_iflag bits */ #define IGNBRK 0000001 #define BRKINT 0000002 #define IGNPAR 0000004 @@ -68,38 +71,44 @@ struct termios { #define IMAXBEL 0020000 #define IUTF8 0040000 +/* c_oflag bits */ #define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 +#define ONLCR 0000002 +#define OLCUC 0000004 + #define OCRNL 0000010 #define ONOCR 0000020 #define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 +#define OFILL 00000100 +#define OFDEL 00000200 +#define NLDLY 00001400 +#define NL0 00000000 +#define NL1 00000400 +#define NL2 00001000 +#define NL3 00001400 +#define TABDLY 00006000 +#define TAB0 00000000 +#define TAB1 00002000 +#define TAB2 00004000 +#define TAB3 00006000 +#define CRDLY 00030000 +#define KCR0 00000000 +#define KCR1 00010000 +#define KCR2 00020000 +#define KCR3 00030000 +#define FFDLY 00040000 +#define FF0 00000000 +#define FF1 00040000 +#define BSDLY 00100000 +#define BS0 00000000 +#define BS1 00100000 +#define VTDLY 00200000 +#define VT0 00000000 +#define VT1 00200000 +#define XTABS 01000000 + +/* c_cflag bit meaning */ #define B0 0000000 #define B50 0000001 #define B75 0000002 @@ -145,15 +154,23 @@ struct termios { #define HUPCL 0002000 #define CLOCAL 0004000 -#define ISIG 0000001 -#define ICANON 0000002 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define IEXTEN 0100000 +/* c_lflag bits */ +#define ISIG 0000001 +#define ICANON 0000002 +#define XCASE 0000004 +#define ECHO 0000010 +#define ECHOE 0000020 +#define ECHOK 0000040 +#define ECHONL 0000100 +#define NOFLSH 0000200 +#define TOSTOP 0000400 +#define ECHOCTL 0001000 +#define ECHOPRT 0002000 +#define ECHOKE 0004000 +#define FLUSHO 0010000 +#define PENDIN 0040000 +#define IEXTEN 0100000 +#define EXTPROC 0200000 #define TCOOFF 0 #define TCOON 1 @@ -184,7 +201,13 @@ struct termios { #define PENDIN 0040000 #define EXTPROC 0200000 -#define XTABS 0014000 +/* intr=^C quit=^| erase=del kill=^U + eof=^D vtime=\0 vmin=\1 sxtc=\0 + start=^Q stop=^S susp=^Z eol=\0 + reprint=^R discard=^U werase=^W lnext=^V + eol2=\0 +*/ +#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" speed_t cfgetospeed (const struct termios *); speed_t cfgetispeed (const struct termios *); diff --git a/components/drivers/tty/include/tty.h b/components/drivers/tty/include/tty.h new file mode 100644 index 0000000000000000000000000000000000000000..681c472808cc301d15ceccb73fb193f2cecf4816 --- /dev/null +++ b/components/drivers/tty/include/tty.h @@ -0,0 +1,477 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021.12.07 linzhenxing first version + */ +#ifndef __TTY_H__ +#define __TTY_H__ +#include +#include +#include +#ifdef RT_USING_LWP +#include +#endif +#if defined(RT_USING_POSIX) +#include +#include +#endif + +#define current lwp_self() +#define __DISABLED_CHAR '\0' + +/* + * When a break, frame error, or parity error happens, these codes are + * stuffed into the flags buffer. + */ +#define TTY_NORMAL 0 +#define TTY_BREAK 1 +#define TTY_FRAME 2 +#define TTY_PARITY 3 +#define TTY_OVERRUN 4 + +#define INTR_CHAR(tty) ((tty)->init_termios.c_cc[VINTR]) +#define QUIT_CHAR(tty) ((tty)->init_termios.c_cc[VQUIT]) +#define ERASE_CHAR(tty) ((tty)->init_termios.c_cc[VERASE]) +#define KILL_CHAR(tty) ((tty)->init_termios.c_cc[VKILL]) +#define EOF_CHAR(tty) ((tty)->init_termios.c_cc[VEOF]) +#define TIME_CHAR(tty) ((tty)->init_termios.c_cc[VTIME]) +#define MIN_CHAR(tty) ((tty)->init_termios.c_cc[VMIN]) +#define SWTC_CHAR(tty) ((tty)->init_termios.c_cc[VSWTC]) +#define START_CHAR(tty) ((tty)->init_termios.c_cc[VSTART]) +#define STOP_CHAR(tty) ((tty)->init_termios.c_cc[VSTOP]) +#define SUSP_CHAR(tty) ((tty)->init_termios.c_cc[VSUSP]) +#define EOL_CHAR(tty) ((tty)->init_termios.c_cc[VEOL]) +#define REPRINT_CHAR(tty) ((tty)->init_termios.c_cc[VREPRINT]) +#define DISCARD_CHAR(tty) ((tty)->init_termios.c_cc[VDISCARD]) +#define WERASE_CHAR(tty) ((tty)->init_termios.c_cc[VWERASE]) +#define LNEXT_CHAR(tty) ((tty)->init_termios.c_cc[VLNEXT]) +#define EOL2_CHAR(tty) ((tty)->init_termios.c_cc[VEOL2]) + +#define _I_FLAG(tty,f) ((tty)->init_termios.c_iflag & (f)) +#define _O_FLAG(tty,f) ((tty)->init_termios.c_oflag & (f)) +#define _C_FLAG(tty,f) ((tty)->init_termios.c_cflag & (f)) +#define _L_FLAG(tty,f) ((tty)->init_termios.c_lflag & (f)) + +#define I_IGNBRK(tty) _I_FLAG((tty),IGNBRK) +#define I_BRKINT(tty) _I_FLAG((tty),BRKINT) +#define I_IGNPAR(tty) _I_FLAG((tty),IGNPAR) +#define I_PARMRK(tty) _I_FLAG((tty),PARMRK) +#define I_INPCK(tty) _I_FLAG((tty),INPCK) +#define I_ISTRIP(tty) _I_FLAG((tty),ISTRIP) +#define I_INLCR(tty) _I_FLAG((tty),INLCR) +#define I_IGNCR(tty) _I_FLAG((tty),IGNCR) +#define I_ICRNL(tty) _I_FLAG((tty),ICRNL) +#define I_IUCLC(tty) _I_FLAG((tty),IUCLC) +#define I_IXON(tty) _I_FLAG((tty),IXON) +#define I_IXANY(tty) _I_FLAG((tty),IXANY) +#define I_IXOFF(tty) _I_FLAG((tty),IXOFF) +#define I_IMAXBEL(tty) _I_FLAG((tty),IMAXBEL) +#define I_IUTF8(tty) _I_FLAG((tty), IUTF8) + +#define O_OPOST(tty) _O_FLAG((tty),OPOST) +#define O_OLCUC(tty) _O_FLAG((tty),OLCUC) +#define O_ONLCR(tty) _O_FLAG((tty),ONLCR) +#define O_OCRNL(tty) _O_FLAG((tty),OCRNL) +#define O_ONOCR(tty) _O_FLAG((tty),ONOCR) +#define O_ONLRET(tty) _O_FLAG((tty),ONLRET) +#define O_OFILL(tty) _O_FLAG((tty),OFILL) +#define O_OFDEL(tty) _O_FLAG((tty),OFDEL) +#define O_NLDLY(tty) _O_FLAG((tty),NLDLY) +#define O_CRDLY(tty) _O_FLAG((tty),CRDLY) +#define O_TABDLY(tty) _O_FLAG((tty),TABDLY) +#define O_BSDLY(tty) _O_FLAG((tty),BSDLY) +#define O_VTDLY(tty) _O_FLAG((tty),VTDLY) +#define O_FFDLY(tty) _O_FLAG((tty),FFDLY) + +#define C_BAUD(tty) _C_FLAG((tty),CBAUD) +#define C_CSIZE(tty) _C_FLAG((tty),CSIZE) +#define C_CSTOPB(tty) _C_FLAG((tty),CSTOPB) +#define C_CREAD(tty) _C_FLAG((tty),CREAD) +#define C_PARENB(tty) _C_FLAG((tty),PARENB) +#define C_PARODD(tty) _C_FLAG((tty),PARODD) +#define C_HUPCL(tty) _C_FLAG((tty),HUPCL) +#define C_CLOCAL(tty) _C_FLAG((tty),CLOCAL) +#define C_CIBAUD(tty) _C_FLAG((tty),CIBAUD) +#define C_CRTSCTS(tty) _C_FLAG((tty),CRTSCTS) + +#define L_ISIG(tty) _L_FLAG((tty),ISIG) +#define L_ICANON(tty) _L_FLAG((tty),ICANON) +#define L_XCASE(tty) _L_FLAG((tty),XCASE) +#define L_ECHO(tty) _L_FLAG((tty),ECHO) +#define L_ECHOE(tty) _L_FLAG((tty),ECHOE) +#define L_ECHOK(tty) _L_FLAG((tty),ECHOK) +#define L_ECHONL(tty) _L_FLAG((tty),ECHONL) +#define L_NOFLSH(tty) _L_FLAG((tty),NOFLSH) +#define L_TOSTOP(tty) _L_FLAG((tty),TOSTOP) +#define L_ECHOCTL(tty) _L_FLAG((tty),ECHOCTL) +#define L_ECHOPRT(tty) _L_FLAG((tty),ECHOPRT) +#define L_ECHOKE(tty) _L_FLAG((tty),ECHOKE) +#define L_FLUSHO(tty) _L_FLAG((tty),FLUSHO) +#define L_PENDIN(tty) _L_FLAG((tty),PENDIN) +#define L_IEXTEN(tty) _L_FLAG((tty),IEXTEN) +#define L_EXTPROC(tty) _L_FLAG((tty), EXTPROC) + +/* + * Where all of the state associated with a tty is kept while the tty + * is open. Since the termios state should be kept even if the tty + * has been closed --- for things like the baud rate, etc --- it is + * not stored here, but rather a pointer to the real state is stored + * here. Possible the winsize structure should have the same + * treatment, but (1) the default 80x24 is usually right and (2) it's + * most often used by a windowing system, which will set the correct + * size each time the window is created or resized anyway. + * - TYT, 9/14/92 + */ +struct tty_struct +{ + struct rt_device parent; + int type; + int subtype; + int init_flag; + int index; //for pty + int pts_lock; //for pty + + struct tty_struct *other_struct; //for pty + + struct winsize winsize; + struct termios init_termios; + struct rt_mutex mutex; + + pid_t pgrp; + pid_t session; + struct rt_lwp *foreground; + + struct tty_ldisc *ldisc; + void *disc_data; + struct rt_device *driver; + + struct rt_wqueue wait_queue; + +#define RT_TTY_BUF 1024 + rt_list_t tty_drivers; +}; + +enum +{ + TTY_INIT_FLAG_NONE = 0, + TTY_INIT_FLAG_ALLOCED, + TTY_INIT_FLAG_REGED, + TTY_INIT_FLAG_INITED, +}; + +#define TTY_DRIVER_TYPE_SYSTEM 0x0001 +#define TTY_DRIVER_TYPE_CONSOLE 0x0002 +#define TTY_DRIVER_TYPE_SERIAL 0x0003 +#define TTY_DRIVER_TYPE_PTY 0x0004 +#define TTY_DRIVER_TYPE_SCC 0x0005 /* scc driver */ +#define TTY_DRIVER_TYPE_SYSCONS 0x0006 + +/* tty magic number */ +#define TTY_MAGIC 0x5401 + +/* + * These bits are used in the flags field of the tty structure. + * + * So that interrupts won't be able to mess up the queues, + * copy_to_cooked must be atomic with respect to itself, as must + * tty->write. Thus, you must use the inline functions set_bit() and + * clear_bit() to make things atomic. + */ +#define TTY_THROTTLED 0 +#define TTY_IO_ERROR 1 +#define TTY_OTHER_CLOSED 2 +#define TTY_EXCLUSIVE 3 +#define TTY_DEBUG 4 +#define TTY_DO_WRITE_WAKEUP 5 +#define TTY_PUSH 6 +#define TTY_CLOSING 7 +#define TTY_DONT_FLIP 8 +#define TTY_HW_COOK_OUT 14 +#define TTY_HW_COOK_IN 15 +#define TTY_PTY_LOCK 16 +#define TTY_NO_WRITE_SPLIT 17 + +/* + * These bits are used in the flags field of the tty structure. + * + * So that interrupts won't be able to mess up the queues, + * copy_to_cooked must be atomic with respect to itself, as must + * tty->write. Thus, you must use the inline functions set_bit() and + * clear_bit() to make things atomic. + */ +#define TTY_THROTTLED 0 +#define TTY_IO_ERROR 1 +#define TTY_OTHER_CLOSED 2 +#define TTY_EXCLUSIVE 3 +#define TTY_DEBUG 4 +#define TTY_DO_WRITE_WAKEUP 5 +#define TTY_PUSH 6 +#define TTY_CLOSING 7 +#define TTY_DONT_FLIP 8 +#define TTY_HW_COOK_OUT 14 +#define TTY_HW_COOK_IN 15 +#define TTY_PTY_LOCK 16 +#define TTY_NO_WRITE_SPLIT 17 + +#define NR_LDISCS 30 + +/* line disciplines */ +#define N_TTY 0 +#define N_SLIP 1 +#define N_MOUSE 2 +#define N_PPP 3 +#define N_STRIP 4 +#define N_AX25 5 +#define N_X25 6 /* X.25 async */ +#define N_6PACK 7 +#define N_MASC 8 /* Reserved for Mobitex module */ +#define N_R3964 9 /* Reserved for Simatic R3964 module */ +#define N_PROFIBUS_FDL 10 /* Reserved for Profibus */ +#define N_IRDA 11 /* Linux IrDa - http://irda.sourceforge.net/ */ +#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data */ + /* cards about SMS messages */ +#define N_HDLC 13 /* synchronous HDLC */ +#define N_SYNC_PPP 14 /* synchronous PPP */ +#define N_HCI 15 /* Bluetooth HCI UART */ +#define N_GIGASET_M101 16 /* Siemens Gigaset M101 serial DECT adapter */ +#define N_SLCAN 17 /* Serial / USB serial CAN Adaptors */ +#define N_PPS 18 /* Pulse per Second */ +#define N_V253 19 /* Codec control over voice modem */ +#define N_CAIF 20 /* CAIF protocol for talking to modems */ +#define N_GSM0710 21 /* GSM 0710 Mux */ +#define N_TI_WL 22 /* for TI's WL BT, FM, GPS combo chips */ +#define N_TRACESINK 23 /* Trace data routing for MIPI P1149.7 */ +#define N_TRACEROUTER 24 /* Trace data routing for MIPI P1149.7 */ +#define N_NCI 25 /* NFC NCI UART */ + +/* Used for packet mode */ +#define TIOCPKT_DATA 0 +#define TIOCPKT_FLUSHREAD 1 +#define TIOCPKT_FLUSHWRITE 2 +#define TIOCPKT_STOP 4 +#define TIOCPKT_START 8 +#define TIOCPKT_NOSTOP 16 +#define TIOCPKT_DOSTOP 32 + +/* tty driver types */ +#define TTY_DRIVER_TYPE_SYSTEM 0x0001 +#define TTY_DRIVER_TYPE_CONSOLE 0x0002 +#define TTY_DRIVER_TYPE_SERIAL 0x0003 +#define TTY_DRIVER_TYPE_PTY 0x0004 +#define TTY_DRIVER_TYPE_SCC 0x0005 /* scc driver */ +#define TTY_DRIVER_TYPE_SYSCONS 0x0006 + +/* pty subtypes */ +#define PTY_TYPE_MASTER 0x0001 +#define PTY_TYPE_SLAVE 0x0002 + +/* serial subtype definitions */ +#define SERIAL_TYPE_NORMAL 1 + +#define max(a, b) ({\ + typeof(a) _a = a;\ + typeof(b) _b = b;\ + _a > _b ? _a : _b; }) + +#define min(a, b) ({\ + typeof(a) _a = a;\ + typeof(b) _b = b;\ + _a < _b ? _a : _b; }) + +void tty_set_fops(struct dfs_file_ops *fops); +void console_set_fops(struct dfs_file_ops *fops); +void mutex_lock(rt_mutex_t mutex); +void mutex_unlock(rt_mutex_t mutex); +int __tty_check_change(struct tty_struct *tty, int sig); +int tty_check_change(struct tty_struct *tty); + +rt_inline struct rt_wqueue *wait_queue_get(struct rt_lwp *lwp, struct tty_struct *tty) +{ + if (lwp == RT_NULL) + { + return &tty->wait_queue; + } + return &lwp->wait_queue; +} + +rt_inline struct rt_wqueue *wait_queue_current_get(struct rt_lwp *lwp, struct tty_struct *tty) +{ + return wait_queue_get(lwp, tty); +} + +rt_inline void tty_wakeup_check(struct tty_struct *tty) +{ + struct rt_wqueue *wq = NULL; + + wq = wait_queue_current_get(tty->foreground, tty); + rt_wqueue_wakeup(wq, (void*)POLLIN); +} + +rt_inline int set_bit(int nr,int *addr) +{ + int mask, retval, level; + + addr += nr >> 5; + mask = 1 << (nr & 0x1f); + level = rt_hw_interrupt_disable(); + retval = (mask & *addr) != 0; + *addr |= mask; + rt_hw_interrupt_enable(level); + return retval; +} + +rt_inline int clear_bit(int nr, int *addr) +{ + int mask, retval, level; + + addr += nr >> 5; + mask = 1 << (nr & 0x1f); + level = rt_hw_interrupt_disable(); + retval = (mask & *addr) != 0; + *addr &= ~mask; + rt_hw_interrupt_enable(level); + return retval; +} + +rt_inline int test_bit(int nr, int *addr) +{ + int mask; + + addr += nr >> 5; + mask = 1 << (nr & 0x1f); + return ((mask & *addr) != 0); +} + +rt_inline int test_and_clear_bit(int nr, volatile void *addr) +{ + int mask, retval, level; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + level = rt_hw_interrupt_disable(); + retval = (mask & *a) != 0; + *a &= ~mask; + rt_hw_interrupt_enable(level); + + return retval; +} + +rt_inline unsigned long __ffs(unsigned long word) +{ + int num = 0; + +#if BITS_PER_LONG == 64 + if ((word & 0xffffffff) == 0) + { + num += 32; + word >>= 32; + } +#endif + if ((word & 0xffff) == 0) + { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) + { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) + { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) + { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + { + num += 1; + } + + return num; +} +#define BITS_PER_LONG 32 +#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) + +/* + * Find the next set bit in a memory region. + */ +rt_inline unsigned long find_next_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + const unsigned long *p = addr + BITOP_WORD(offset); + unsigned long result = offset & ~(BITS_PER_LONG-1); + unsigned long tmp; + + if (offset >= size) + { + return size; + } + + size -= result; + offset %= BITS_PER_LONG; + if (offset) + { + tmp = *(p++); + tmp &= (~0UL << offset); + if (size < BITS_PER_LONG) + { + goto found_first; + } + + if (tmp) + { + goto found_middle; + } + + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + + while (size & ~(BITS_PER_LONG-1)) + { + if ((tmp = *(p++))) + { + goto found_middle; + } + + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + + if (!size) + { + return result; + } + + tmp = *p; + +found_first: + tmp &= (~0UL >> (BITS_PER_LONG - size)); + if (tmp == 0UL) /* Are any bits set? */ + { + return result + size; /* Nope. */ + } + +found_middle: + return result + __ffs(tmp); +} + +/*create by tty_ioctl.c*/ +int n_tty_ioctl_extend(struct tty_struct *tty, int cmd, void *arg); + +/*create by n_tty.c*/ +void console_ldata_init(struct tty_struct *tty); +int n_tty_receive_buf(struct tty_struct *tty, char *cp, int count); +void n_tty_init(void); + +#endif /*__TTY_H__*/ diff --git a/components/drivers/tty/include/tty_ldisc.h b/components/drivers/tty/include/tty_ldisc.h new file mode 100644 index 0000000000000000000000000000000000000000..6accb118ea4f254a1bd27cf23ea5ca8a4c853e6c --- /dev/null +++ b/components/drivers/tty/include/tty_ldisc.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021.12.07 linzhenxing first version + */ +#ifndef __TTY_LDISC_ +#define __TTY_LDISC_ +#include +#include +#include +#include +#if defined(RT_USING_POSIX) +#include +#endif +struct tty_struct; + +struct tty_ldisc_ops +{ + char *name; + int num; + + int (*open) (struct dfs_fd *fd); + int (*close) (struct tty_struct *tty); + int (*ioctl) (struct dfs_fd *fd, int cmd, void *args); + int (*read) (struct dfs_fd *fd, void *buf, size_t count); + int (*write) (struct dfs_fd *fd, const void *buf, size_t count); + int (*flush) (struct dfs_fd *fd); + int (*lseek) (struct dfs_fd *fd, off_t offset); + int (*getdents) (struct dfs_fd *fd, struct dirent *dirp, uint32_t count); + + int (*poll) (struct dfs_fd *fd, struct rt_pollreq *req); + void (*set_termios) (struct tty_struct *tty, struct termios *old); + int (*receive_buf) (struct tty_struct *tty,char *cp, int count); + + int refcount; +}; + +struct tty_ldisc +{ + struct tty_ldisc_ops *ops; + struct tty_struct *tty; +}; + +#define TTY_LDISC_MAGIC 0x5403 + +int tty_register_ldisc(int disc, struct tty_ldisc_ops *new_ldisc); +void tty_ldisc_kill(struct tty_struct *tty); +void tty_ldisc_init(struct tty_struct *tty); +void tty_ldisc_release(struct tty_struct *tty); +void n_tty_init(void); + +#endif // __TTY_LDISC_ diff --git a/components/drivers/tty/n_tty.c b/components/drivers/tty/n_tty.c new file mode 100644 index 0000000000000000000000000000000000000000..f44f0cdf8fe551e35d2fd2e9b4d4f5f93492dec2 --- /dev/null +++ b/components/drivers/tty/n_tty.c @@ -0,0 +1,2039 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021.12.07 linzhenxing first version + */ +#include +#include +#include +#if defined(RT_USING_POSIX) +#include +#endif + +#define DBG_TAG "N_TTY" +#ifdef RT_TTY_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* RT_TTY_DEBUG */ +#include + +/* number of characters left in xmit buffer before select has we have room */ +#define WAKEUP_CHARS 256 + +/* + * This defines the low- and high-watermarks for throttling and + * unthrottling the TTY driver. These watermarks are used for + * controlling the space in the read buffer. + */ +#define TTY_THRESHOLD_THROTTLE 128 /* now based on remaining room */ +#define TTY_THRESHOLD_UNTHROTTLE 128 + +/* + * Special byte codes used in the echo buffer to represent operations + * or special handling of characters. Bytes in the echo buffer that + * are not part of such special blocks are treated as normal character + * codes. + */ +#define ECHO_OP_START 0xff +#define ECHO_OP_MOVE_BACK_COL 0x80 +#define ECHO_OP_SET_CANON_COL 0x81 +#define ECHO_OP_ERASE_TAB 0x82 + +#define ECHO_COMMIT_WATERMARK 256 +#define ECHO_BLOCK 256 +#define ECHO_DISCARD_WATERMARK RT_TTY_BUF - (ECHO_BLOCK + 32) + +void mutex_lock(rt_mutex_t mutex) +{ + rt_err_t result = -RT_EBUSY; + + while (result == -RT_EBUSY) + { + result = rt_mutex_take(mutex, RT_WAITING_FOREVER); + } + + if (result != RT_EOK) + { + RT_ASSERT(0); + } + return; +} + +void mutex_unlock(rt_mutex_t mutex) +{ + rt_mutex_release(mutex); + return; +} +struct n_tty_data +{ + /* producer-published */ + size_t read_head; + size_t commit_head; + size_t canon_head; + size_t echo_head; + size_t echo_commit; + size_t echo_mark; + unsigned long char_map[256]; + + /* non-atomic */ + rt_bool_t no_room; + /* must hold exclusive termios_rwsem to reset these */ + unsigned char lnext:1, erasing:1, raw:1, real_raw:1, icanon:1; + unsigned char push:1; + + /* shared by producer and consumer */ + char read_buf[RT_TTY_BUF]; + unsigned long read_flags[RT_TTY_BUF]; + unsigned char echo_buf[RT_TTY_BUF]; + + /* consumer-published */ + size_t read_tail; + size_t line_start; + + /* protected by output lock */ + unsigned int column; + unsigned int canon_column; + size_t echo_tail; + + rt_mutex_t atomic_read_lock; + rt_mutex_t output_lock; +}; + +static inline size_t read_cnt(struct n_tty_data *ldata) +{ + return ldata->read_head - ldata->read_tail; +} + +static inline char read_buf(struct n_tty_data *ldata, size_t i) +{ + return ldata->read_buf[i & (RT_TTY_BUF - 1)]; +} + +static inline char *read_buf_addr(struct n_tty_data *ldata, size_t i) +{ + return &ldata->read_buf[i & (RT_TTY_BUF - 1)]; +} + +static inline unsigned char echo_buf(struct n_tty_data *ldata, size_t i) +{ + return ldata->echo_buf[i & (RT_TTY_BUF - 1)]; +} + +static inline unsigned char *echo_buf_addr(struct n_tty_data *ldata, size_t i) +{ + return &ldata->echo_buf[i & (RT_TTY_BUF - 1)]; +} + +/** + * put_tty_queue - add character to tty + * @c: character + * @ldata: n_tty data + * + * Add a character to the tty read_buf queue. + * + * n_tty_receive_buf()/producer path: + * caller holds non-exclusive termios_rwsem + */ + +static inline void put_tty_queue(unsigned char c, struct n_tty_data *ldata) +{ + *read_buf_addr(ldata, ldata->read_head) = c; + ldata->read_head++; +} + +/** + * reset_buffer_flags - reset buffer state + * @tty: terminal to reset + * + * Reset the read buffer counters and clear the flags. + * Called from n_tty_open() and n_tty_flush_buffer(). + * + * Locking: caller holds exclusive termios_rwsem + * (or locking is not required) + */ + +static void reset_buffer_flags(struct n_tty_data *ldata) +{ + ldata->read_head = ldata->canon_head = ldata->read_tail = 0; + ldata->echo_head = ldata->echo_tail = ldata->echo_commit = 0; + ldata->commit_head = 0; + ldata->echo_mark = 0; + ldata->line_start = 0; + + ldata->erasing = 0; + rt_memset(ldata->read_flags, 0, RT_TTY_BUF); + ldata->push = 0; +} + +/** + * add_echo_byte - add a byte to the echo buffer + * @c: unicode byte to echo + * @ldata: n_tty data + * + * Add a character or operation byte to the echo buffer. + */ + +static inline void add_echo_byte(unsigned char c, struct n_tty_data *ldata) +{ + *echo_buf_addr(ldata, ldata->echo_head++) = c; +} + +/** + * echo_move_back_col - add operation to move back a column + * @ldata: n_tty data + * + * Add an operation to the echo buffer to move back one column. + */ + +static void echo_move_back_col(struct n_tty_data *ldata) +{ + add_echo_byte(ECHO_OP_START, ldata); + add_echo_byte(ECHO_OP_MOVE_BACK_COL, ldata); +} + +/** + * echo_set_canon_col - add operation to set the canon column + * @ldata: n_tty data + * + * Add an operation to the echo buffer to set the canon column + * to the current column. + */ + +static void echo_set_canon_col(struct n_tty_data *ldata) +{ + add_echo_byte(ECHO_OP_START, ldata); + add_echo_byte(ECHO_OP_SET_CANON_COL, ldata); +} + +/** + * echo_erase_tab - add operation to erase a tab + * @num_chars: number of character columns already used + * @after_tab: true if num_chars starts after a previous tab + * @ldata: n_tty data + * + * Add an operation to the echo buffer to erase a tab. + * + * Called by the eraser function, which knows how many character + * columns have been used since either a previous tab or the start + * of input. This information will be used later, along with + * canon column (if applicable), to go back the correct number + * of columns. + */ + +static void echo_erase_tab(unsigned int num_chars, int after_tab, + struct n_tty_data *ldata) +{ + add_echo_byte(ECHO_OP_START, ldata); + add_echo_byte(ECHO_OP_ERASE_TAB, ldata); + + /* We only need to know this modulo 8 (tab spacing) */ + num_chars &= 7; + + /* Set the high bit as a flag if num_chars is after a previous tab */ + if (after_tab) + { + num_chars |= 0x80; + } + + add_echo_byte(num_chars, ldata); +} + +/** + * echo_char_raw - echo a character raw + * @c: unicode byte to echo + * @tty: terminal device + * + * Echo user input back onto the screen. This must be called only when + * L_ECHO(tty) is true. Called from the driver receive_buf path. + * + * This variant does not treat control characters specially. + */ + +static void echo_char_raw(unsigned char c, struct n_tty_data *ldata) +{ + if (c == ECHO_OP_START) + { + add_echo_byte(ECHO_OP_START, ldata); + add_echo_byte(ECHO_OP_START, ldata); + } + else + { + add_echo_byte(c, ldata); + } +} + +/** + * echo_char - echo a character + * @c: unicode byte to echo + * @tty: terminal device + * + * Echo user input back onto the screen. This must be called only when + * L_ECHO(tty) is true. Called from the driver receive_buf path. + * + * This variant tags control characters to be echoed as "^X" + * (where X is the letter representing the control char). + */ + +static void echo_char(unsigned char c, struct tty_struct *tty) +{ + struct n_tty_data *ldata = tty->disc_data; + + if (c == ECHO_OP_START) + { + add_echo_byte(ECHO_OP_START, ldata); + add_echo_byte(ECHO_OP_START, ldata); + } + else + { + if (L_ECHOCTL(tty) && iscntrl(c) && c != '\t') + { + add_echo_byte(ECHO_OP_START, ldata); + } + add_echo_byte(c, ldata); + } +} + +/** + * finish_erasing - complete erase + * @ldata: n_tty data + */ + +static inline void finish_erasing(struct n_tty_data *ldata) +{ + if (ldata->erasing) + { + echo_char_raw('/', ldata); + ldata->erasing = 0; + } +} + +/** + * is_utf8_continuation - utf8 multibyte check + * @c: byte to check + * + * Returns true if the utf8 character 'c' is a multibyte continuation + * character. We use this to correctly compute the on screen size + * of the character when printing + */ + +static inline int is_utf8_continuation(unsigned char c) +{ + return (c & 0xc0) == 0x80; +} + +/** + * is_continuation - multibyte check + * @c: byte to check + * + * Returns true if the utf8 character 'c' is a multibyte continuation + * character and the terminal is in unicode mode. + */ + +static inline int is_continuation(unsigned char c, struct tty_struct *tty) +{ + return I_IUTF8(tty) && is_utf8_continuation(c); +} + +/** + * eraser - handle erase function + * @c: character input + * @tty: terminal device + * + * Perform erase and necessary output when an erase character is + * present in the stream from the driver layer. Handles the complexities + * of UTF-8 multibyte symbols. + * + * n_tty_receive_buf()/producer path: + * caller holds non-exclusive termios_rwsem + */ + +static void eraser(unsigned char c, struct tty_struct *tty) +{ + struct n_tty_data *ldata = tty->disc_data; + enum { KERASE, WERASE, KILL } kill_type; + size_t head = 0; + size_t cnt = 0; + int seen_alnums = 0; + + if (ldata->read_head == ldata->canon_head) + { + /* process_output('\a', tty); */ /* what do you think? */ + return; + } + + if (c == ERASE_CHAR(tty)) + { + kill_type = KERASE; + } + else if (c == WERASE_CHAR(tty)) + { + kill_type = WERASE; + } + else + { + if (!L_ECHO(tty)) + { + ldata->read_head = ldata->canon_head; + return; + } + + if (!L_ECHOK(tty) || !L_ECHOKE(tty) || !L_ECHOE(tty)) + { + ldata->read_head = ldata->canon_head; + finish_erasing(ldata); + echo_char(KILL_CHAR(tty), tty); + /* Add a newline if ECHOK is on and ECHOKE is off. */ + if (L_ECHOK(tty)) + { + echo_char_raw('\n', ldata); + } + return; + } + kill_type = KILL; + } + + seen_alnums = 0; + while (ldata->read_head != ldata->canon_head) + { + head = ldata->read_head; + + /* erase a single possibly multibyte character */ + do + { + head--; + c = read_buf(ldata, head); + } while (is_continuation(c, tty) && head != ldata->canon_head); + + /* do not partially erase */ + if (is_continuation(c, tty)) + { + break; + } + + if (kill_type == WERASE) + { + /* Equivalent to BSD's ALTWERASE. */ + if (isalnum(c) || c == '_') + { + seen_alnums++; + } + else if (seen_alnums) + { + break; + } + } + cnt = ldata->read_head - head; + ldata->read_head = head; + if (L_ECHO(tty)) + { + if (L_ECHOPRT(tty)) + { + if (!ldata->erasing) + { + echo_char_raw('\\', ldata); + ldata->erasing = 1; + } + /* if cnt > 1, output a multi-byte character */ + echo_char(c, tty); + while (--cnt > 0) + { + head++; + echo_char_raw(read_buf(ldata, head), ldata); + echo_move_back_col(ldata); + } + } + else if (kill_type == KERASE && !L_ECHOE(tty)) + { + echo_char(ERASE_CHAR(tty), tty); + } + else if (c == '\t') + { + unsigned int num_chars = 0; + int after_tab = 0; + size_t tail = ldata->read_head; + + /* + * Count the columns used for characters + * since the start of input or after a + * previous tab. + * This info is used to go back the correct + * number of columns. + */ + while (tail != ldata->canon_head) + { + tail--; + c = read_buf(ldata, tail); + if (c == '\t') + { + after_tab = 1; + break; + } + else if (iscntrl(c)) + { + if (L_ECHOCTL(tty)) + { + num_chars += 2; + } + } + else if (!is_continuation(c, tty)) + { + num_chars++; + } + } + echo_erase_tab(num_chars, after_tab, ldata); + } + else + { + if (iscntrl(c) && L_ECHOCTL(tty)) + { + echo_char_raw('\b', ldata); + echo_char_raw(' ', ldata); + echo_char_raw('\b', ldata); + } + if (!iscntrl(c) || L_ECHOCTL(tty)) + { + echo_char_raw('\b', ldata); + echo_char_raw(' ', ldata); + echo_char_raw('\b', ldata); + } + } + } + if (kill_type == KERASE) + { + break; + } + } + if (ldata->read_head == ldata->canon_head && L_ECHO(tty)) + { + finish_erasing(ldata); + } +} + +/** + * isig - handle the ISIG optio + * @sig: signal + * @tty: terminal + * + * Called when a signal is being sent due to terminal input. + * Called from the driver receive_buf path so serialized. + * + * Performs input and output flush if !NOFLSH. In this context, the echo + * buffer is 'output'. The signal is processed first to alert any current + * readers or writers to discontinue and exit their i/o loops. + * + * Locking: ctrl_lock + */ + +static void __isig(int sig, struct tty_struct *tty) +{ + struct rt_lwp *lwp = tty->foreground; + if (lwp) + { + lwp_kill(lwp_to_pid(lwp), sig); + } +} + +static void isig(int sig, struct tty_struct *tty) +{ + struct n_tty_data *ldata = tty->disc_data; + + if (L_NOFLSH(tty)) + { + /* signal only */ + __isig(sig, tty); + + } + else + { /* signal and flush */ + __isig(sig, tty); + + /* clear echo buffer */ + ldata->echo_head = ldata->echo_tail = 0; + ldata->echo_mark = ldata->echo_commit = 0; + + /* clear input buffer */ + reset_buffer_flags(tty->disc_data); + } +} + +/** + * do_output_char - output one character + * @c: character (or partial unicode symbol) + * @tty: terminal device + * @space: space available in tty driver write buffer + * + * This is a helper function that handles one output character + * (including special characters like TAB, CR, LF, etc.), + * doing OPOST processing and putting the results in the + * tty driver's write buffer. + * + * Note that Linux currently ignores TABDLY, CRDLY, VTDLY, FFDLY + * and NLDLY. They simply aren't relevant in the world today. + * If you ever need them, add them here. + * + * Returns the number of bytes of buffer space used or -1 if + * no space left. + * + * Locking: should be called under the output_lock to protect + * the column state and space left in the buffer + */ + +static int do_output_char(unsigned char c, struct tty_struct *tty) +{ + struct n_tty_data *ldata = tty->disc_data; + int spaces = 0; + char *ch = RT_NULL; + + switch (c) + { + case '\n': + if (O_ONLRET(tty)) + { + ldata->column = 0; + } + + if (O_ONLCR(tty)) + { + ldata->canon_column = ldata->column = 0; + ch = "\r\n"; + rt_device_write((rt_device_t)tty, -1, ch, 2); + return 2; + } + ldata->canon_column = ldata->column; + break; + case '\r': + if (O_ONOCR(tty) && ldata->column == 0) + { + return 0; + } + + if (O_OCRNL(tty)) + { + c = '\n'; + if (O_ONLRET(tty)) + { + ldata->canon_column = ldata->column = 0; + } + break; + } + ldata->canon_column = ldata->column = 0; + break; + case '\t': + spaces = 8 - (ldata->column & 7); + if (O_TABDLY(tty) == XTABS) + { + ldata->column += spaces; + ch = " "; + rt_device_write((rt_device_t)tty, -1, &ch, spaces); + return spaces; + } + ldata->column += spaces; + break; + case '\b': + if (ldata->column > 0) + { + ldata->column--; + } + ch = "\b \b"; + rt_device_write((rt_device_t)tty, -1, ch, strlen(ch)); + return 1; + default: + if (!iscntrl(c)) + { + if (O_OLCUC(tty)) + { + c = toupper(c); + } + + if (!is_continuation(c, tty)) + { + ldata->column++; + } + } + break; + } + + rt_device_write((rt_device_t)tty, -1, &c, 1); + return 1; +} + +/** + * process_output - output post processor + * @c: character (or partial unicode symbol) + * @tty: terminal device + * + * Output one character with OPOST processing. + * Returns -1 when the output device is full and the character + * must be retried. + * + * Locking: output_lock to protect column state and space left + * (also, this is called from n_tty_write under the + * tty layer write lock) + */ + +static int process_output(unsigned char c, struct tty_struct *tty) +{ + int retval = 0; + int level = 0; + + level = rt_hw_interrupt_disable(); + retval = do_output_char(c, tty); + rt_hw_interrupt_enable(level); + if (retval < 0) + { + return -1; + } + else + { + return 0; + } +} + +/** + * process_output_block - block post processor + * @tty: terminal device + * @buf: character buffer + * @nr: number of bytes to output + * + * Output a block of characters with OPOST processing. + * Returns the number of characters output. + * + * This path is used to speed up block console writes, among other + * things when processing blocks of output data. It handles only + * the simple cases normally found and helps to generate blocks of + * symbols for the console driver and thus improve performance. + * + * Locking: output_lock to protect column state and space left + * (also, this is called from n_tty_write under the + * tty layer write lock) + */ + +static ssize_t process_output_block(struct tty_struct *tty, + const char *buf, unsigned int nr) +{ + struct n_tty_data *ldata = tty->disc_data; + int i = 0; + ssize_t size = 0; + const char *cp = RT_NULL; + int level = 0; + + level = rt_hw_interrupt_disable(); + + for (i = 0, cp = buf; i < nr; i++, cp++) + { + char c = *cp; + + switch (c) + { + case '\n': + if (O_ONLRET(tty)) + { + ldata->column = 0; + } + + if (O_ONLCR(tty)) + { + goto break_out; + } + ldata->canon_column = ldata->column; + break; + case '\r': + if (O_ONOCR(tty) && ldata->column == 0) + { + goto break_out; + } + + if (O_OCRNL(tty)) + { + goto break_out; + } + + ldata->canon_column = ldata->column = 0; + break; + case '\t': + goto break_out; + case '\b': + if (ldata->column > 0) + { + ldata->column--; + } + break; + default: + if (!iscntrl(c)) + { + if (O_OLCUC(tty)) + { + goto break_out; + } + + if (!is_continuation(c, tty)) + { + ldata->column++; + } + } + break; + } + } +break_out: + size = rt_device_write((rt_device_t)tty, -1, buf, i); + rt_hw_interrupt_enable(level); + return size; +} + +static size_t __process_echoes(struct tty_struct *tty) +{ + struct n_tty_data *ldata = tty->disc_data; + size_t tail = 0; + unsigned char c = 0; + char ch = 0; + + tail = ldata->echo_tail; + while (ldata->echo_commit != tail) + { + c = echo_buf(ldata, tail); + if (c == ECHO_OP_START) + { + unsigned char op = 0; + + /* + * If the buffer byte is the start of a multi-byte + * operation, get the next byte, which is either the + * op code or a control character value. + */ + op = echo_buf(ldata, tail + 1); + + switch (op) + { + unsigned char num_chars = 0, num_bs = 0; + + case ECHO_OP_ERASE_TAB: + num_chars = echo_buf(ldata, tail + 2); + + /* + * Determine how many columns to go back + * in order to erase the tab. + * This depends on the number of columns + * used by other characters within the tab + * area. If this (modulo 8) count is from + * the start of input rather than from a + * previous tab, we offset by canon column. + * Otherwise, tab spacing is normal. + */ + if (!(num_chars & 0x80)) + { + num_chars += ldata->canon_column; + } + num_bs = 8 - (num_chars & 7); + + while (num_bs--) + { + ch = '\b'; + rt_device_write((rt_device_t)tty, -1, &ch, 1); + if (ldata->column > 0) + { + ldata->column--; + } + } + tail += 3; + break; + + case ECHO_OP_SET_CANON_COL: + ldata->canon_column = ldata->column; + tail += 2; + break; + + case ECHO_OP_MOVE_BACK_COL: + if (ldata->column > 0) + { + ldata->column--; + } + tail += 2; + break; + + case ECHO_OP_START: + ch = ECHO_OP_START; + rt_device_write((rt_device_t)tty, -1, &ch, 1); + ldata->column++; + tail += 2; + break; + + default: + /* + * If the op is not a special byte code, + * it is a ctrl char tagged to be echoed + * as "^X" (where X is the letter + * representing the control char). + * Note that we must ensure there is + * enough space for the whole ctrl pair. + * + */ + ch = '^'; + rt_device_write((rt_device_t)tty, -1, &ch, 1); + ch = op ^ 0100; + rt_device_write((rt_device_t)tty, -1, &ch, 1); + ldata->column += 2; + tail += 2; + } + } + else + { + if (O_OPOST(tty)) + { + int retval = do_output_char(c, tty); + if (retval < 0) + { + break; + } + } + else + { + rt_device_write((rt_device_t)tty, -1, &c, 1); + } + tail += 1; + } + } + + /* If the echo buffer is nearly full (so that the possibility exists + * of echo overrun before the next commit), then discard enough + * data at the tail to prevent a subsequent overrun */ + while (ldata->echo_commit - tail >= ECHO_DISCARD_WATERMARK) + { + if (echo_buf(ldata, tail) == ECHO_OP_START) + { + if (echo_buf(ldata, tail + 1) == ECHO_OP_ERASE_TAB) + { + tail += 3; + } + else + { + tail += 2; + } + } + else + { + tail++; + } + } + + ldata->echo_tail = tail; + return 0; +} + +static void commit_echoes(struct tty_struct *tty) +{ + struct n_tty_data *ldata = tty->disc_data; + size_t nr = 0, old = 0; + size_t head = 0; + int level = 0; + + head = ldata->echo_head; + ldata->echo_mark = head; + old = ldata->echo_commit - ldata->echo_tail; + + /* Process committed echoes if the accumulated # of bytes + * is over the threshold (and try again each time another + * block is accumulated) */ + nr = head - ldata->echo_tail; + if (nr < ECHO_COMMIT_WATERMARK || (nr % ECHO_BLOCK > old % ECHO_BLOCK)) + { + return; + } + + level = rt_hw_interrupt_disable(); + ldata->echo_commit = head; + __process_echoes(tty); + rt_hw_interrupt_enable(level); +} + +static void process_echoes(struct tty_struct *tty) +{ + struct n_tty_data *ldata = tty->disc_data; + int level = 0; + if (ldata->echo_mark == ldata->echo_tail) + { + return; + } + + level = rt_hw_interrupt_disable(); + ldata->echo_commit = ldata->echo_mark; + __process_echoes(tty); + rt_hw_interrupt_enable(level); +} + +/* NB: echo_mark and echo_head should be equivalent here */ +static void flush_echoes(struct tty_struct *tty) +{ + struct n_tty_data *ldata = tty->disc_data; + int level = 0; + + if ((!L_ECHO(tty) && !L_ECHONL(tty)) || + ldata->echo_commit == ldata->echo_head) + { + return; + } + + level = rt_hw_interrupt_disable(); + ldata->echo_commit = ldata->echo_head; + __process_echoes(tty); + rt_hw_interrupt_enable(level); +} +/** + * n_tty_set_termios - termios data changed + * @tty: terminal + * @old: previous data + * + * Called by the tty layer when the user changes termios flags so + * that the line discipline can plan ahead. This function cannot sleep + * and is protected from re-entry by the tty layer. The user is + * guaranteed that this function will not be re-entered or in progress + * when the ldisc is closed. + * + * Locking: Caller holds tty->termios_rwsem + */ + +static void n_tty_set_termios(struct tty_struct *tty, struct termios *old) +{ + struct n_tty_data *ldata = tty->disc_data; + + if (!old || (old->c_lflag ^ tty->init_termios.c_lflag) & (ICANON | EXTPROC)) + { + rt_memset(ldata->read_flags, 0, RT_TTY_BUF); + ldata->line_start = ldata->read_tail; + if (!L_ICANON(tty) || !read_cnt(ldata)) + { + ldata->canon_head = ldata->read_tail; + ldata->push = 0; + } + else + { + set_bit((ldata->read_head - 1) & (RT_TTY_BUF - 1),(int *)ldata->read_flags); + ldata->canon_head = ldata->read_head; + ldata->push = 1; + } + ldata->commit_head = ldata->read_head; + ldata->erasing = 0; + ldata->lnext = 0; + } + + ldata->icanon = (L_ICANON(tty) != 0); + + if (I_ISTRIP(tty) || I_IUCLC(tty) || I_IGNCR(tty) || + I_ICRNL(tty) || I_INLCR(tty) || L_ICANON(tty) || + I_IXON(tty) || L_ISIG(tty) || L_ECHO(tty) || + I_PARMRK(tty)) + { + rt_memset(ldata->char_map, 0, 256); + if (I_IGNCR(tty) || I_ICRNL(tty)) + { + set_bit('\r', (int *)ldata->char_map); + } + + if (I_INLCR(tty)) + { + set_bit('\n', (int *)ldata->char_map); + } + + if (L_ICANON(tty)) + { + set_bit(ERASE_CHAR(tty), (int *)ldata->char_map); + set_bit(KILL_CHAR(tty),(int *) ldata->char_map); + set_bit(EOF_CHAR(tty), (int *)ldata->char_map); + set_bit('\n',(int *) ldata->char_map); + set_bit(EOL_CHAR(tty),(int *) ldata->char_map); + if (L_IEXTEN(tty)) + { + set_bit(WERASE_CHAR(tty), (int *)ldata->char_map); + set_bit(LNEXT_CHAR(tty), (int *)ldata->char_map); + set_bit(EOL2_CHAR(tty), (int *)ldata->char_map); + if (L_ECHO(tty)) + { + set_bit(REPRINT_CHAR(tty), + (int *)ldata->char_map); + } + } + } + if (I_IXON(tty)) + { + set_bit(START_CHAR(tty), (int *)ldata->char_map); + set_bit(STOP_CHAR(tty), (int *)ldata->char_map); + } + if (L_ISIG(tty)) + { + set_bit(INTR_CHAR(tty), (int *)ldata->char_map); + set_bit(QUIT_CHAR(tty), (int *)ldata->char_map); + set_bit(SUSP_CHAR(tty), (int *)ldata->char_map); + } + clear_bit(__DISABLED_CHAR, (int *)ldata->char_map); + ldata->raw = 0; + ldata->real_raw = 0; + } + else + { + ldata->raw = 1; + if ((I_IGNBRK(tty) || (!I_BRKINT(tty) && !I_PARMRK(tty))) && + (I_IGNPAR(tty) || !I_INPCK(tty))/* && + (tty->driver->flags & TTY_DRIVER_REAL_RAW)*/) + { + ldata->real_raw = 1; + } + else + { + ldata->real_raw = 0; + } + } +} + +void console_ldata_init(struct tty_struct *tty) +{ + struct n_tty_data *ldata = RT_NULL; + + ldata = rt_malloc(sizeof(struct n_tty_data)); + if (ldata == RT_NULL) + { + LOG_E("console_ldata_init ldata malloc fail"); + return; + } + tty->disc_data = ldata; + reset_buffer_flags(ldata); + ldata->column = 0; + ldata->canon_column = 0; + ldata->no_room = 0; + ldata->lnext = 0; + n_tty_set_termios(tty, RT_NULL); + return; +} + +static int n_tty_open(struct dfs_fd *fd) +{ + int ret = 0; + struct n_tty_data *ldata = RT_NULL; + struct tty_struct *tty = (struct tty_struct*)fd->fnode->data; + + ldata = rt_malloc(sizeof(struct n_tty_data)); + if (ldata == RT_NULL) + { + LOG_E("n_tty_open ldata malloc fail"); + return -1; + } + + ldata->atomic_read_lock = rt_mutex_create("atomic_read_lock",RT_IPC_FLAG_FIFO); + ldata->output_lock = rt_mutex_create("output_lock",RT_IPC_FLAG_FIFO); + tty->disc_data = ldata; + reset_buffer_flags(ldata); + ldata->column = 0; + ldata->canon_column = 0; + ldata->lnext = 0; + n_tty_set_termios(tty, RT_NULL); + return ret; +} + +static inline int input_available_p(struct tty_struct *tty, int poll) +{ + struct n_tty_data *ldata = tty->disc_data; + int amt = poll && !TIME_CHAR(tty) && MIN_CHAR(tty) ? MIN_CHAR(tty) : 1; + + if (ldata->icanon && !L_EXTPROC(tty)) + { + return ldata->canon_head != ldata->read_tail; + } + else + { + return ldata->commit_head - ldata->read_tail >= amt; + } +} + +/** + * copy_from_read_buf - copy read data directly + * @tty: terminal device + * @b: user data + * @nr: size of data + * + * Helper function to speed up n_tty_read. It is only called when + * ICANON is off; it copies characters straight from the tty queue to + * user space directly. It can be profitably called twice; once to + * drain the space from the tail pointer to the (physical) end of the + * buffer, and once to drain the space from the (physical) beginning of + * the buffer to head pointer. + * + * Called under the ldata->atomic_read_lock sem + * + * n_tty_read()/consumer path: + * caller holds non-exclusive termios_rwsem + * read_tail published + */ + +static int copy_from_read_buf(struct tty_struct *tty,char *b,size_t nr) +{ + struct n_tty_data *ldata = tty->disc_data; + size_t n = 0; + rt_bool_t is_eof = 0; + size_t head = ldata->commit_head; + size_t tail = ldata->read_tail & (RT_TTY_BUF - 1); + + n = min(head - ldata->read_tail, RT_TTY_BUF - tail); + n = min(nr, n); + if (n) + { + const char *from = read_buf_addr(ldata, tail); + rt_memcpy(b, from, n); + is_eof = n == 1 && *from == EOF_CHAR(tty); + ldata->read_tail += n; + /* Turn single EOF into zero-length read */ + if (L_EXTPROC(tty) && ldata->icanon && is_eof && + (head == ldata->read_tail)) + { + n = 0; + } + + } + return n; +} + +/** + * canon_copy_from_read_buf - copy read data in canonical mode + * @tty: terminal device + * @b: user data + * @nr: size of data + * + * Helper function for n_tty_read. It is only called when ICANON is on; + * it copies one line of input up to and including the line-delimiting + * character into the user-space buffer. + * + * NB: When termios is changed from non-canonical to canonical mode and + * the read buffer contains data, n_tty_set_termios() simulates an EOF + * push (as if C-d were input) _without_ the DISABLED_CHAR in the buffer. + * This causes data already processed as input to be immediately available + * as input although a newline has not been received. + * + * Called under the atomic_read_lock mutex + * + * n_tty_read()/consumer path: + * caller holds non-exclusive termios_rwsem + * read_tail published + */ + +static int canon_copy_from_read_buf(struct tty_struct *tty, char *b, size_t nr) +{ + struct n_tty_data *ldata = tty->disc_data; + size_t n = 0, size = 0, more = 0, c = 0; + size_t eol = 0; + size_t tail = 0; + int found = 0; + + /* N.B. avoid overrun if nr == 0 */ + if (nr == 0) + { + return 0; + } + + n = min(nr + 1, ldata->canon_head - ldata->read_tail); + + tail = ldata->read_tail & (RT_TTY_BUF - 1); + size = min(tail + n, RT_TTY_BUF); + + eol = find_next_bit(ldata->read_flags, size, tail); + more = n - (size - tail); + if (eol == RT_TTY_BUF && more) + { + /* scan wrapped without finding set bit */ + eol = find_next_bit(ldata->read_flags, more, 0); + found = eol != more; + } + else + { + found = eol != size; + } + + n = eol - tail; + if (n > RT_TTY_BUF) + { + n += RT_TTY_BUF; + } + c = n + found; + + if (!found || read_buf(ldata, eol) != __DISABLED_CHAR) + { + c = min(nr, c); + n = c; + } + + size_t buf_size = RT_TTY_BUF - tail; + const void *from = read_buf_addr(ldata, tail); + if (n > buf_size) + { + rt_memcpy(b, from, buf_size); + b += buf_size; + n -= buf_size; + from = ldata->read_buf; + } + rt_memcpy(b, from, n); + + if (found) + { + clear_bit(eol, (int *)ldata->read_flags); + } + ldata->read_tail = ldata->read_tail + c; + + if (found) + { + if (!ldata->push) + { + ldata->line_start = ldata->read_tail; + } + else + { + ldata->push = 0; + } + } + return n; +} + + +static int n_tty_close(struct tty_struct *tty) +{ + int ret = 0; + struct n_tty_data *ldata = RT_NULL; + struct tty_struct *o_tty = RT_NULL; + + RT_ASSERT(tty != RT_NULL); + if (tty->type == TTY_DRIVER_TYPE_PTY && tty->subtype == PTY_TYPE_MASTER) + { + o_tty = tty->other_struct; + } + else + { + o_tty = tty; + } + + ldata = o_tty->disc_data; + rt_free(ldata); + o_tty->disc_data = RT_NULL; + return ret; +} + +static int n_tty_ioctl(struct dfs_fd *fd, int cmd, void *args) +{ + int ret = 0; + struct tty_struct *real_tty = RT_NULL; + struct tty_struct *tty = RT_NULL; + + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + if (tty->type == TTY_DRIVER_TYPE_PTY && tty->subtype == PTY_TYPE_MASTER) + { + real_tty = tty->other_struct; + } + else + { + real_tty = tty; + } + + switch(cmd) + { + + default: + ret = n_tty_ioctl_extend(real_tty, cmd, args); + if (ret != -ENOIOCTLCMD) + { + return ret; + } + } + + ret = rt_device_control((rt_device_t)real_tty, cmd, args); + if (ret != -ENOIOCTLCMD) + { + return ret; + } + return ret; +} + +static void +n_tty_receive_signal_char(struct tty_struct *tty, int signal, unsigned char c) +{ + isig(signal, tty); + if (L_ECHO(tty)) + { + echo_char(c, tty); + commit_echoes(tty); + } + else + { + process_echoes(tty); + } + return; +} + +/** + * n_tty_receive_char - perform processing + * @tty: terminal device + * @c: character + * + * Process an individual character of input received from the driver. + * This is serialized with respect to itself by the rules for the + * driver above. + * + * n_tty_receive_buf()/producer path: + * caller holds non-exclusive termios_rwsem + * publishes canon_head if canonical mode is active + * + * Returns 1 if LNEXT was received, else returns 0 + */ + +static int n_tty_receive_char_special(struct tty_struct *tty, unsigned char c) +{ + struct n_tty_data *ldata = tty->disc_data; + + if (I_IXON(tty)) + { + if (c == START_CHAR(tty)) /*ctrl + p realize missing*/ + { + process_echoes(tty); + return 0; + } + if (c == STOP_CHAR(tty)) /*ctrl + s realize missing*/ + { + return 0; + } + } + + if (L_ISIG(tty)) + { + if (c == INTR_CHAR(tty)) /*ctrl + c realize missing*/ + { + n_tty_receive_signal_char(tty, SIGINT, c); + return 0; + } + else if (c == QUIT_CHAR(tty)) /*ctrl + d realize missing*/ + { + n_tty_receive_signal_char(tty, SIGQUIT, c); + return 0; + } + else if (c == SUSP_CHAR(tty)) /*ctrl + z realize missing*/ + { + n_tty_receive_signal_char(tty, SIGTSTP, c); + return 0; + } + } + + if (c == '\r') + { + if (I_IGNCR(tty)) + { + return 0; + } + + if (I_ICRNL(tty)) + { + c = '\n'; + } + } + else if (c == '\n' && I_INLCR(tty)) + { + c = '\r'; + } + + if (ldata->icanon) + { + if (c == ERASE_CHAR(tty) || c == KILL_CHAR(tty) || + (c == WERASE_CHAR(tty) && L_IEXTEN(tty))) + { + eraser(c, tty); + commit_echoes(tty); + return 0; + } + if (c == LNEXT_CHAR(tty) && L_IEXTEN(tty)) + { + ldata->lnext = 1; + if (L_ECHO(tty)) + { + finish_erasing(ldata); + if (L_ECHOCTL(tty)) + { + echo_char_raw('^', ldata); + echo_char_raw('\b', ldata); + commit_echoes(tty); + } + } + return 1; + } + if (c == REPRINT_CHAR(tty) && L_ECHO(tty) && L_IEXTEN(tty)) + { + size_t tail = ldata->canon_head; + + finish_erasing(ldata); + echo_char(c, tty); + echo_char_raw('\n', ldata); + while (tail != ldata->read_head) + { + echo_char(read_buf(ldata, tail), tty); + tail++; + } + commit_echoes(tty); + return 0; + } + if (c == '\n') + { + if (L_ECHO(tty) || L_ECHONL(tty)) + { + echo_char_raw('\n', ldata); + commit_echoes(tty); + } + goto handle_newline; + } + if (c == EOF_CHAR(tty)) + { + c = __DISABLED_CHAR; + goto handle_newline; + } + if ((c == EOL_CHAR(tty)) || + (c == EOL2_CHAR(tty) && L_IEXTEN(tty))) + { + /* + * XXX are EOL_CHAR and EOL2_CHAR echoed?!? + */ + if (L_ECHO(tty)) + { + /* Record the column of first canon char. */ + if (ldata->canon_head == ldata->read_head) + { + echo_set_canon_col(ldata); + } + + echo_char(c, tty); + commit_echoes(tty); + } + /* + * XXX does PARMRK doubling happen for + * EOL_CHAR and EOL2_CHAR? + */ + if (c == (unsigned char) '\377' && I_PARMRK(tty)) + { + put_tty_queue(c, ldata); + } + +handle_newline: + set_bit(ldata->read_head & (RT_TTY_BUF - 1), (int *)ldata->read_flags); + put_tty_queue(c, ldata); + ldata->canon_head = ldata->read_head; + tty_wakeup_check(tty); + return 0; + } + } + + if (L_ECHO(tty)) + { + finish_erasing(ldata); + if (c == '\n') + { + echo_char_raw('\n', ldata); + } + else + { + /* Record the column of first canon char. */ + if (ldata->canon_head == ldata->read_head) + { + echo_set_canon_col(ldata); + } + echo_char(c, tty); + } + commit_echoes(tty); + } + + /* PARMRK doubling check */ + if (c == (unsigned char) '\377' && I_PARMRK(tty)) + { + put_tty_queue(c, ldata); + } + + put_tty_queue(c, ldata); + return 0; +} + +static inline void n_tty_receive_char_inline(struct tty_struct *tty, unsigned char c) +{ + struct n_tty_data *ldata = tty->disc_data; + + if (L_ECHO(tty)) + { + finish_erasing(ldata); + /* Record the column of first canon char. */ + if (ldata->canon_head == ldata->read_head) + { + echo_set_canon_col(ldata); + } + + echo_char(c, tty); + commit_echoes(tty); + } + /* PARMRK doubling check */ + if (c == (unsigned char) '\377' && I_PARMRK(tty)) + { + put_tty_queue(c, ldata); + } + + put_tty_queue(c, ldata); +} + +static void n_tty_receive_char(struct tty_struct *tty, unsigned char c) +{ + n_tty_receive_char_inline(tty, c); +} + +static void n_tty_receive_char_lnext(struct tty_struct *tty, unsigned char c, char flag) +{ + struct n_tty_data *ldata = tty->disc_data; + + ldata->lnext = 0; + if (flag == TTY_NORMAL) + { + if (I_ISTRIP(tty)) + { + c &= 0x7f; + } + + if (I_IUCLC(tty) && L_IEXTEN(tty)) + { + c = tolower(c); + } + + n_tty_receive_char(tty, c); + } + else + { + //n_tty_receive_char_flagged(tty, c, flag); + } + +} + +static void n_tty_receive_buf_real_raw(struct tty_struct *tty, char *cp, int count) +{ + struct n_tty_data *ldata = tty->disc_data; + size_t n = 0, head = 0; + + head = ldata->read_head & (RT_TTY_BUF - 1); + n = min(count, RT_TTY_BUF - head); + rt_memcpy(read_buf_addr(ldata, head), cp, n); + ldata->read_head += n; + cp += n; + count -= n; + + head = ldata->read_head & (RT_TTY_BUF - 1); + n = min(count, RT_TTY_BUF - head); + rt_memcpy(read_buf_addr(ldata, head), cp, n); + ldata->read_head += n; +} + +static void n_tty_receive_buf_raw(struct tty_struct *tty, char *cp, int count) +{ + struct n_tty_data *ldata = tty->disc_data; + char flag = TTY_NORMAL; + + while (count--) + { + if (flag == TTY_NORMAL) + { + put_tty_queue(*cp++, ldata); + } + } +} + +static void n_tty_receive_buf_standard(struct tty_struct *tty, char *cp, int count) +{ + struct n_tty_data *ldata = tty->disc_data; + char flag = TTY_NORMAL; + + while (count--) + { + char c = *cp++; + + if (I_ISTRIP(tty)) + { + c &= 0x7f; + } + + if (I_IUCLC(tty) && L_IEXTEN(tty)) + { + c = tolower(c); + } + + if (L_EXTPROC(tty)) + { + put_tty_queue(c, ldata); + continue; + } + + if (!test_bit(c, (int *)ldata->char_map)) + { + n_tty_receive_char_inline(tty, c); + } + else if (n_tty_receive_char_special(tty, c) && count) + { + n_tty_receive_char_lnext(tty, *cp++, flag); + count--; + } + } +} + +static inline void n_tty_receive_char_fast(struct tty_struct *tty, unsigned char c) +{ + struct n_tty_data *ldata = tty->disc_data; + + if (L_ECHO(tty)) + { + finish_erasing(ldata); + /* Record the column of first canon char. */ + if (ldata->canon_head == ldata->read_head) + { + echo_set_canon_col(ldata); + } + + echo_char(c, tty); + commit_echoes(tty); + } + put_tty_queue(c, ldata); +} + +static void n_tty_receive_buf_fast(struct tty_struct *tty, char *cp, int count) +{ + struct n_tty_data *ldata = tty->disc_data; + char flag = TTY_NORMAL; + + while (count--) + { + unsigned char c = *cp++; + + if (!test_bit(c, (int *)ldata->char_map)) + { + n_tty_receive_char_fast(tty, c); + } + else if (n_tty_receive_char_special(tty, c) && count) + { + n_tty_receive_char_lnext(tty, *cp++, flag); + count--; + } + } +} + +static void __receive_buf(struct tty_struct *tty, char *cp, int count) +{ + struct n_tty_data *ldata = tty->disc_data; + rt_bool_t preops = I_ISTRIP(tty) || (I_IUCLC(tty) && L_IEXTEN(tty)); + + if (ldata->real_raw) + { + n_tty_receive_buf_real_raw(tty, cp, count); + } + + else if (ldata->raw || (L_EXTPROC(tty) && !preops)) + { + n_tty_receive_buf_raw(tty, cp, count); + } + else + { + if (!preops && !I_PARMRK(tty)) + { + n_tty_receive_buf_fast(tty, cp, count); + } + else + { + n_tty_receive_buf_standard(tty, cp, count); + } + flush_echoes(tty); + } + + if (ldata->icanon && !L_EXTPROC(tty)) + return; + + /* publish read_head to consumer */ + ldata->commit_head = ldata->read_head; + + if (read_cnt(ldata)) + { + tty_wakeup_check(tty); + } +} + +int n_tty_receive_buf(struct tty_struct *tty,char *cp, int count) +{ + int size = 0; + struct n_tty_data *ldata = tty->disc_data; + int room = 0, n = 0, rcvd = 0, overflow = 0; + + size = count; + while(1) + { + size_t tail = ldata->read_tail; + + room = RT_TTY_BUF - (ldata->read_head - tail); + + if (I_PARMRK(tty)) + { + room = (room +2)/3; + } + room--; + if (room <= 0) + { + overflow = ldata->icanon && ldata->canon_head == tail; + if (overflow && room < 0) + { + ldata->read_head--; + } + + room = overflow; + } + else + { + overflow = 0; + } + + n = min(size, room); + + if (!n) + { + break; + } + + if (!overflow) + { + __receive_buf(tty, cp, n); + } + + cp += n; + size -= n; + rcvd += n; + } + return count - size; +} + +/** + * job_control - check job control + * @tty: tty + * @file: file handle + * + * Perform job control management checks on this file/tty descriptor + * and if appropriate send any needed signals and return a negative + * error code if action should be taken. + * + * Locking: redirected write test is safe + * current->signal->tty check is safe + * ctrl_lock to safely reference tty->pgrp + */ + +static int job_control(struct tty_struct *tty) +{ + return __tty_check_change(tty, SIGTTIN); +} + +static int n_tty_read(struct dfs_fd *fd, void *buf, size_t count) +{ + int level = 0; + char *b = (char *)buf; + struct tty_struct *tty = RT_NULL; + struct rt_lwp *lwp = RT_NULL; + struct rt_wqueue *wq = RT_NULL; + int wait_ret = 0; + int retval = 0; + int c = 0; + + level = rt_hw_interrupt_disable(); + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + c = job_control(tty); + if (c < 0) + { + return c; + } + + struct n_tty_data *ldata = tty->disc_data; + + lwp = (struct rt_lwp *)(rt_thread_self()->lwp); + wq = wait_queue_get(lwp, tty); + + while(count) + { + if ((!input_available_p(tty, 0))) + { + if (fd->flags & O_NONBLOCK) + { + retval = -EAGAIN; + break; + } + + wait_ret = rt_wqueue_wait_interruptible(wq, 0, RT_WAITING_FOREVER); + if (wait_ret != 0) + { + break; + } + } + + if (ldata->icanon && !L_EXTPROC(tty)) + { + retval = canon_copy_from_read_buf(tty, b, count); + } + else + { + retval = copy_from_read_buf(tty, b, count); + } + + if (retval >= 1) + { + break; + } + } + rt_hw_interrupt_enable(level); + return retval; +} + +static int n_tty_write(struct dfs_fd *fd, const void *buf, size_t count) +{ + int retval = 0; + char *b = (char *)buf; + int c = 0; + struct tty_struct *tty = RT_NULL; + + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + retval = tty_check_change(tty); + if (retval) + { + return retval; + } + + process_echoes(tty); + retval = count; + while(1) + { + if (O_OPOST(tty)) + { + while (count > 0) + { + ssize_t num = process_output_block(tty, b, count); + if (num < 0) + { + if (num == -EAGAIN) + { + break; + } + + retval = num; + goto break_out; + } + b += num; + count -= num; + if (count == 0) + { + break; + } + + c = *b; + if (process_output(c, tty) < 0) + { + break; + } + + b++; + count--; + } + retval -= count; + } + else + { + int level = 0; + while (count > 0) + { + level = rt_hw_interrupt_disable(); + c = rt_device_write((rt_device_t)tty, -1, b, count); + rt_hw_interrupt_enable(level); + if (c < 0) + { + retval = c; + goto break_out; + } + b += c; + count -= c; + } + retval -= count; + } + + if (!count) + { + break; + } + if (fd->flags & O_NONBLOCK) + { + break; + } + } +break_out: + return retval; +} + +static int n_tty_flush(struct dfs_fd *fd) +{ + return 0; +} + +static int n_tty_lseek(struct dfs_fd *fd, off_t offset) +{ + return 0; +} + +static int n_tty_getdents(struct dfs_fd *fd, struct dirent *dirp, uint32_t count) +{ + return 0; +} + +static int n_tty_poll(struct dfs_fd *fd, struct rt_pollreq *req) +{ + rt_base_t level = 0; + int mask = POLLOUT; + struct tty_struct *tty = RT_NULL; + struct rt_wqueue *wq = RT_NULL; + struct rt_lwp *lwp = RT_NULL; + + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + + RT_ASSERT(tty->init_flag == TTY_INIT_FLAG_INITED); + + lwp = (struct rt_lwp *)(rt_thread_self()->lwp); + wq = wait_queue_get(lwp, tty); + rt_poll_add(wq, req); + level = rt_hw_interrupt_disable(); + + if (input_available_p(tty, 1)) + { + mask |= POLLIN; + } + + rt_hw_interrupt_enable(level); + + return mask; +} + +static struct tty_ldisc_ops n_tty_ops = { + "n_tty", + 0, + n_tty_open, + n_tty_close, + n_tty_ioctl, + n_tty_read, + n_tty_write, + n_tty_flush, + n_tty_lseek, + n_tty_getdents, + n_tty_poll, + n_tty_set_termios, + n_tty_receive_buf, + 0, +}; + +void n_tty_init(void) +{ + tty_register_ldisc(N_TTY, &n_tty_ops); +} diff --git a/components/libc/termios/posix_termios.c b/components/drivers/tty/posix_termios.c similarity index 84% rename from components/libc/termios/posix_termios.c rename to components/drivers/tty/posix_termios.c index 9c736c3184bed6f03c31c62fb02142abb0dbc3cb..801ace68a26244321e529ac3768cf979e429c9e6 100644 --- a/components/libc/termios/posix_termios.c +++ b/components/drivers/tty/posix_termios.c @@ -1,23 +1,24 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017/08/30 Bernard The first version + * 2021/12/10 linzhenxing put tty system */ #include #include #include #include -#include +#include int tcgetattr(int fd, struct termios *tio) { /* Get the current serial port settings. */ - if (ioctl(fd, TCGETA, tio)) + if (ioctl(fd, TCGETS, tio)) return -1; return 0; @@ -29,19 +30,19 @@ int tcsetattr(int fd, int act, const struct termios *tio) { case TCSANOW: /* make the change immediately */ - return (ioctl(fd, TCSETA, (void*)tio)); + return (ioctl(fd, TCSETS, (void*)tio)); case TCSADRAIN: /* * Don't make the change until all currently written data * has been transmitted. */ - return (ioctl(fd, TCSETAW, (void*)tio)); + return (ioctl(fd, TCSETSW, (void*)tio)); case TCSAFLUSH: /* Don't make the change until all currently written data * has been transmitted, at which point any received but * unread data is also discarded. */ - return (ioctl(fd, TCSETAF, (void*)tio)); + return (ioctl(fd, TCSETSF, (void*)tio)); default: errno = EINVAL; return (-1); @@ -95,12 +96,12 @@ int tcsendbreak(int fd, int dur) int tcflush(int fd, int queue) { - return ioctl(fd, TCFLSH, (void*)queue); + return ioctl(fd, TCFLSH, (void*)(size_t)queue); } int tcflow(int fd, int action) { - return ioctl(fd, TCXONC, (void*)action); + return ioctl(fd, TCXONC, (void*)(size_t)action); } /** diff --git a/components/drivers/tty/pty.c b/components/drivers/tty/pty.c new file mode 100644 index 0000000000000000000000000000000000000000..2c147b21c20ccc5650f19b1830e8ff167c36884b --- /dev/null +++ b/components/drivers/tty/pty.c @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021.12.07 linzhenxing first version + */ +#include +#include +#include + +#define DBG_TAG "PTY" +#ifdef RT_TTY_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* RT_TTY_DEBUG */ +#include + +#define PTY_PTS_SIZE 10 +static struct tty_struct ptm_driver; +static struct tty_struct pts_drivers[PTY_PTS_SIZE]; +static int pts_index = 0; + +static int pts_register(struct tty_struct *ptm_drv, struct tty_struct *pts_drv, int pts_index); + +/* check free pts device */ +static struct tty_struct *find_freepts(void) +{ + for(int i = 0; i < PTY_PTS_SIZE; i++) + { + if (pts_drivers[i].init_flag == TTY_INIT_FLAG_NONE) + { + pts_drivers[i].init_flag = TTY_INIT_FLAG_ALLOCED; + return &pts_drivers[i]; + } + } + return RT_NULL; +} + +/* Set the lock flag on a pty */ +static int pty_set_lock(struct tty_struct *tty, int *arg) +{ + int val = *arg; + + if (val) + { + tty->pts_lock = val; + } + else + { + tty->pts_lock = val; + } + return 0; +} + +static int pty_get_lock(struct tty_struct *tty, int *arg) +{ + *arg = tty->pts_lock; + return 0; +} + +static int pty_get_index(struct tty_struct *tty, int *arg) +{ + *arg = tty->index; + return 0; +} +/* RT-Thread Device Interface */ +/* + * This function initializes console device. + */ +static rt_err_t pty_device_init(struct rt_device *dev) +{ + rt_err_t result = RT_EOK; + int level = 0; + struct tty_struct *tty = RT_NULL; + RT_ASSERT(dev != RT_NULL); + + tty = (struct tty_struct *)dev; + level = rt_hw_interrupt_disable(); + RT_ASSERT(tty->init_flag == TTY_INIT_FLAG_REGED); + tty->init_flag = TTY_INIT_FLAG_INITED; + rt_hw_interrupt_enable(level); + return result; +} + +static rt_err_t pty_device_open(struct rt_device *dev, rt_uint16_t oflag) +{ + rt_err_t result = RT_EOK; + return result; +} + +static rt_err_t pty_device_close(struct rt_device *dev) +{ + rt_err_t result = RT_EOK; + struct tty_struct *tty = (struct tty_struct*)dev; + //struct tty_struct *to = RT_NULL; + + if (tty->subtype == PTY_TYPE_MASTER) + { + // to = tty->other_struct; + // to->init_flag = TTY_INIT_FLAG_NONE; + // to->other_struct = RT_NULL; + // to->foreground = RT_NULL; + // to->index = -1; + // tty_ldisc_kill(to); + // tty->other_struct = RT_NULL; + } + else + { + // to = tty->other_struct; + // to->other_struct = RT_NULL; + // tty->init_flag = TTY_INIT_FLAG_NONE; + // tty->other_struct = RT_NULL; + // tty->foreground = RT_NULL; + // tty->index = -1; + // tty->other_struct = RT_NULL; + // tty_ldisc_kill(tty); + } + + return result; +} + +static rt_size_t pty_device_read(struct rt_device *dev, + rt_off_t pos, + void *buffer, + rt_size_t size) +{ + rt_size_t len = 0; + + return len; +} + +static rt_size_t pty_device_write(struct rt_device *dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + rt_base_t level = 0; + rt_size_t len = 0; + struct tty_struct *tty = RT_NULL; + struct tty_struct *to = RT_NULL; + + tty = (struct tty_struct *)dev; + RT_ASSERT(tty != RT_NULL); + RT_ASSERT(tty->init_flag == TTY_INIT_FLAG_INITED); + to = tty->other_struct; + level = rt_hw_interrupt_disable(); + + if (to->ldisc->ops->receive_buf) + { + len = to->ldisc->ops->receive_buf(to, (char *)buffer, size); + } + rt_hw_interrupt_enable(level); + + return len; +} + +static rt_err_t pty_device_control(rt_device_t dev, int cmd, void *args) +{ + struct tty_struct *tty = (struct tty_struct *)dev; + + switch (cmd) + { + case TIOCSPTLCK: /* Set PT Lock (disallow slave open) */ + return pty_set_lock(tty, (int *)args); + case TIOCGPTLCK: /* Get PT Lock status */ + return pty_get_lock(tty, (int *)args); + case TIOCGPTN: /* Get PT Number */ + return pty_get_index(tty, (int *)args); + } + + return -ENOIOCTLCMD; +} + +static int ptmx_open(struct dfs_fd *fd) +{ + int ret = 0; + struct tty_struct *tty = RT_NULL; + struct tty_struct *pts_drv = RT_NULL; + struct tty_ldisc *ld = RT_NULL; + struct rt_lwp *lwp = RT_NULL; + struct rt_wqueue *wq = RT_NULL; + + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + + pts_drv = find_freepts(); + if (pts_drv == RT_NULL) + { + LOG_E("free pts driver find fail\n"); + return -1; + } + ret = pts_register(tty, pts_drv, pts_index); + if (ret < 0) + { + LOG_E("pts register fail\n"); + rt_free(pts_drv); + return -1; + } + pts_index++; + lwp = (struct rt_lwp *)(rt_thread_self()->lwp); + wq = wait_queue_get(lwp, tty); + pts_drv->wait_queue = *wq; + tty->other_struct = pts_drv; + ld = tty->ldisc; + if (ld->ops->open) + { + ret = ld->ops->open(fd); + } + + return ret; +} +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops pty_device_ops = +{ + pty_device_init, + pty_device_open, + pty_device_close, + pty_device_read, + pty_device_write, + pty_device_control, +}; +#endif /* RT_USING_DEVICE_OPS */ +static struct dfs_file_ops pts_fops; +static struct dfs_file_ops ptmx_fops; +static int pts_register(struct tty_struct *ptm_drv, struct tty_struct *pts_drv, int pts_index) +{ + rt_err_t ret = RT_EOK; + rt_base_t level = 0; + struct rt_device *device = RT_NULL; + char name[20]; + + RT_ASSERT(ptm_drv!=RT_NULL); + level = rt_hw_interrupt_disable(); + + if (pts_drv->init_flag != TTY_INIT_FLAG_ALLOCED) + { + LOG_E("pts%d has been registered\n", pts_index); + ret = (-RT_EBUSY); + goto _exit; + } + + device = &pts_drv->parent; + device->type = RT_Device_Class_Char; +#ifdef RT_USING_DEVICE_OPS + device->ops = &pty_device_ops; +#else + device->init = pty_device_init; + device->open = pty_device_open; + device->close = pty_device_close; + device->read = pty_device_read; + device->write = pty_device_write; + device->control = pty_device_control; +#endif /* RT_USING_DEVICE_OPS */ + + rt_snprintf(name, sizeof(name), "pts%d", pts_index); + ret = rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); + if (ret != RT_EOK) + { + LOG_E("pts%d register failed\n", pts_index); + ret = -RT_EIO; + goto _exit; + } + +#ifdef RT_USING_POSIX + /* set fops */ + tty_set_fops(&pts_fops); + device->fops = &pts_fops; +#endif + + pts_drv->type = TTY_DRIVER_TYPE_PTY; + pts_drv->subtype = PTY_TYPE_SLAVE; + + pts_drv->pgrp = -1; + pts_drv->session = -1; + pts_drv->foreground = RT_NULL; + pts_drv->index = pts_index; + pts_drv->pts_lock = 1; + rt_wqueue_init(&pts_drv->wait_queue); + + tty_ldisc_init(pts_drv); + +extern struct termios tty_std_termios; + pts_drv->init_termios = tty_std_termios; + pts_drv->init_termios.c_cflag = B38400 | CS8 | CREAD; + pts_drv->init_termios.c_lflag |= ICANON; + pts_drv->init_termios.__c_ispeed = 38400; + pts_drv->init_termios.__c_ospeed = 38400; + + pts_drv->other_struct = ptm_drv; + + pts_drv->init_flag = TTY_INIT_FLAG_REGED; +_exit: + rt_hw_interrupt_enable(level); + + return ret; +} + +static int ptmx_register(void) +{ + rt_base_t level = 0; + rt_err_t ret = RT_EOK; + struct rt_device *device = RT_NULL; + struct tty_struct *ptm_drv = &ptm_driver; + + level = rt_hw_interrupt_disable(); + RT_ASSERT(ptm_drv->init_flag == TTY_INIT_FLAG_NONE); + + level = rt_hw_interrupt_disable(); + device = &(ptm_drv->parent); + + device->type = RT_Device_Class_Char; + +#ifdef RT_USING_DEVICE_OPS + device->ops = &pty_device_ops; +#else + device->init = pty_device_init; + device->open = pty_device_open; + device->close = pty_device_close; + device->read = pty_device_read; + device->write = pty_device_write; + device->control = pty_device_control; +#endif /* RT_USING_DEVICE_OPS */ + + ret = rt_device_register(device, "ptmx", RT_DEVICE_FLAG_RDWR); + if (ret != RT_EOK) + { + LOG_E("ptmx register fail\n"); + ret = -RT_EIO; + goto _exit; + } + +#ifdef RT_USING_POSIX + /* set fops */ + tty_set_fops(&ptmx_fops); + ptmx_fops.open = ptmx_open; + device->fops = &ptmx_fops; +#endif + + ptm_drv->type = TTY_DRIVER_TYPE_PTY; + ptm_drv->subtype = PTY_TYPE_MASTER; + + ptm_drv->pgrp = -1; + ptm_drv->session = -1; + ptm_drv->foreground = RT_NULL; + rt_wqueue_init(&ptm_drv->wait_queue); + + tty_ldisc_init(ptm_drv); + +extern struct termios tty_std_termios; + ptm_drv->init_termios.c_iflag = 0; + ptm_drv->init_termios.c_oflag = 0; + ptm_drv->init_termios.c_cflag = B38400 | CS8 | CREAD; + ptm_drv->init_termios.c_lflag = 0; + ptm_drv->init_termios.__c_ispeed = 38400; + ptm_drv->init_termios.__c_ospeed = 38400; + + ptm_drv->init_flag = TTY_INIT_FLAG_REGED; + +_exit: + rt_hw_interrupt_enable(level); + + return ret; +} +INIT_DEVICE_EXPORT(ptmx_register); diff --git a/components/drivers/tty/tty.c b/components/drivers/tty/tty.c new file mode 100644 index 0000000000000000000000000000000000000000..b88a4b700f62cb71bbe08a00d1162b51befcdd23 --- /dev/null +++ b/components/drivers/tty/tty.c @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021.12.07 linzhenxing first version + */ +#include +#include +#include +#include +#include +#include +#include + +#if defined(RT_USING_POSIX) +#include +#endif + +#define DBG_TAG "TTY" +#ifdef RT_TTY_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* RT_TTY_DEBUG */ +#include + +struct termios tty_std_termios = { /* for the benefit of tty drivers */ + .c_iflag = IMAXBEL | IUCLC | INLCR | ICRNL | IGNPAR, + .c_oflag = OPOST, + .c_cflag = B38400 | CS8 | CREAD | HUPCL, + .c_lflag = ISIG | ECHOE | TOSTOP | NOFLSH, + RT_NULL,/* .c_line = N_TTY, */ + .c_cc = INIT_C_CC, + .__c_ispeed = 38400, + .__c_ospeed = 38400 +}; + +rt_inline int tty_sigismember(lwp_sigset_t *set, int _sig) +{ + unsigned long sig = _sig - 1; + + if (_LWP_NSIG_WORDS == 1) + { + return 1 & (set->sig[0] >> sig); + } + else + { + return 1 & (set->sig[sig / _LWP_NSIG_BPW] >> (sig % _LWP_NSIG_BPW)); + } +} + +static int is_ignored(int sig) +{ + return (tty_sigismember(¤t->signal, sig) || + current->signal_handler[sig-1] == SIG_IGN); +} + +/** + * tty_check_change - check for POSIX terminal changes + * @tty: tty to check + * + * If we try to write to, or set the state of, a terminal and we're + * not in the foreground, send a SIGTTOU. If the signal is blocked or + * ignored, go ahead and perform the operation. (POSIX 7.2) + * + * Locking: ctrl_lock + */ + +int __tty_check_change(struct tty_struct *tty, int sig) +{ + pid_t pgrp = 0, tty_pgrp = 0; + struct rt_lwp *lwp = tty->foreground; + int ret = 0; + int level = 0; + + level = rt_hw_interrupt_disable(); + if (current == RT_NULL) + { + return 0; + } + + if (current->tty != tty) + { + return 0; + } + + pgrp = current->__pgrp; + tty_pgrp = tty->pgrp; + + if (tty_pgrp && pgrp != tty->pgrp) + { + if (is_ignored(sig)) + { + if (sig == SIGTTIN) + { + ret = -EIO; + } + } + else + { + if (lwp) + { + lwp_kill(lwp_to_pid(lwp), sig); + } + } + } + rt_hw_interrupt_enable(level); + + if (!tty_pgrp) + { + LOG_D(tty, "sig=%d, tty->pgrp == -1!\n", sig); + } + return ret; +} + +int tty_check_change(struct tty_struct *tty) +{ + return __tty_check_change(tty, SIGTTOU); +} + +static int tty_open(struct dfs_fd *fd) +{ + int ret = 0; + int noctty = 0; + struct tty_struct *tty = RT_NULL; + struct tty_ldisc *ld = RT_NULL; + + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + ld = tty->ldisc; + if (ld->ops->open) + { + ret = ld->ops->open(fd); + } + noctty = (fd->flags & O_NOCTTY); + + rt_device_t device = (rt_device_t)fd->fnode->data; + if (fd->fnode->ref_count == 1) + { + ret = rt_device_open(device, fd->flags); + } + if (current == RT_NULL) //kernel mode not lwp + { + return ret; + } + + if (!noctty && + current->leader && + !current->tty && + tty->session == -1) + { + current->tty = tty; + current->tty_old_pgrp = 0; + tty->session = current->session; + tty->pgrp = current->__pgrp; + tty->foreground = current; + } + + return ret; +} + +static int tty_close(struct dfs_fd *fd) +{ + int ret = 0; + struct tty_struct *tty = RT_NULL; + struct tty_ldisc *ld = RT_NULL; + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + ld = tty->ldisc; + if (ld->ops->close) + { + //ld->ops->close(tty); + } + if (fd->fnode->ref_count == 1) + { + ret = rt_device_close((rt_device_t)tty); + } + return ret; +} + +static int tiocsctty(struct tty_struct *tty, int arg) +{ + if (current->leader && + (current->session == tty->session)) + { + return 0; + } + + /* + * The process must be a session leader and + * not have a controlling tty already. + */ + if (!current->leader || current->tty) + { + return -EPERM; + } + + if (tty->session > 0) + { + LOG_E("this tty have control process\n"); + + } + current->tty = tty; + current->tty_old_pgrp = 0; + tty->session = current->session; + tty->pgrp = current->__pgrp; + tty->foreground = current; + if (tty->type == TTY_DRIVER_TYPE_PTY) + { + tty->other_struct->foreground = current; + } + return 0; +} + +static int tty_ioctl(struct dfs_fd *fd, int cmd, void *args) +{ + int ret = 0; + struct tty_struct *tty = RT_NULL; + struct tty_struct *real_tty = RT_NULL; + struct tty_ldisc *ld = RT_NULL; + + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + + if (tty->type == TTY_DRIVER_TYPE_PTY && tty->subtype == PTY_TYPE_MASTER) + { + real_tty = tty->other_struct; + } + else + { + real_tty = tty; + } + switch (cmd) + { + case TIOCSCTTY: + return tiocsctty(real_tty, 1); + } + ld = tty->ldisc; + if (ld->ops->ioctl) + { + ret = ld->ops->ioctl(fd, cmd, args); + } + return ret; +} + +static int tty_read(struct dfs_fd *fd, void *buf, size_t count) +{ + int ret = 0; + struct tty_struct *tty = RT_NULL; + struct tty_ldisc *ld = RT_NULL; + + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + ld = tty->ldisc; + if (ld->ops->read) + { + ret = ld->ops->read(fd, buf, count); + } + return ret; +} + +static int tty_write(struct dfs_fd *fd, const void *buf, size_t count) +{ + int ret = 0; + struct tty_struct *tty = RT_NULL; + struct tty_ldisc *ld = RT_NULL; + + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + ld = tty->ldisc; + if (ld->ops->write) + { + ret = ld->ops->write(fd, buf, count); + } + return ret; +} + +static int tty_poll(struct dfs_fd *fd, struct rt_pollreq *req) +{ + int ret = 0; + struct tty_struct *tty = RT_NULL; + struct tty_ldisc *ld = RT_NULL; + + tty = (struct tty_struct *)fd->fnode->data; + RT_ASSERT(tty != RT_NULL); + ld = tty->ldisc; + if (ld->ops->poll) + { + ret = ld->ops->poll(fd, req); + } + return ret; +} + +static const struct dfs_file_ops tty_fops = +{ + tty_open, + tty_close, + tty_ioctl, + tty_read, + tty_write, + RT_NULL, /* flush */ + RT_NULL, /* lseek */ + RT_NULL, /* getdents */ + tty_poll, +}; +static const struct dfs_file_ops console_fops = +{ + tty_open, + tty_close, + tty_ioctl, + tty_read, + tty_write, + RT_NULL, /* flush */ + RT_NULL, /* lseek */ + RT_NULL, /* getdents */ + tty_poll, +}; + +void console_init() +{ + n_tty_init(); +} + +void tty_set_fops(struct dfs_file_ops *fops) +{ + *fops = tty_fops; +} + +void console_set_fops(struct dfs_file_ops *fops) +{ + *fops = console_fops; +} diff --git a/components/drivers/tty/tty_ioctl.c b/components/drivers/tty/tty_ioctl.c new file mode 100644 index 0000000000000000000000000000000000000000..894353ed845f52d4e0c4c36e10bf5c1dd22c92ad --- /dev/null +++ b/components/drivers/tty/tty_ioctl.c @@ -0,0 +1,108 @@ +#include +#include +#include +#if defined(RT_USING_POSIX) +#include +#endif + +#define DBG_TAG "TTY_IOCTL" +#ifdef RT_TTY_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* RT_TTY_DEBUG */ +#include + +/* + * Internal flag options for termios setting behavior + */ +#define TERMIOS_FLUSH 1 +#define TERMIOS_WAIT 2 +#define TERMIOS_TERMIO 4 +#define TERMIOS_OLD 8 + +/** + * set_termios - set termios values for a tty + * @tty: terminal device + * @arg: user data + * @opt: option information + * + * Helper function to prepare termios data and run necessary other + * functions before using tty_set_termios to do the actual changes. + * + * Locking: + * Called functions take ldisc and termios_rwsem locks + */ + +static int set_termios(struct tty_struct *tty, void *arg, int opt) +{ + struct termios old_termios = tty->init_termios; + struct tty_ldisc *ld = RT_NULL; + struct termios *new_termios = (struct termios *)arg; + int level = 0; + int retval = tty_check_change(tty); + + if (retval) + { + return retval; + } + + level = rt_hw_interrupt_disable(); + tty->init_termios = *new_termios; + rt_hw_interrupt_enable(level); + ld = tty->ldisc; + if (ld != NULL) + { + if (ld->ops->set_termios) + { + ld->ops->set_termios(tty, &old_termios); + } + } + return 0; +} + +int n_tty_ioctl_extend(struct tty_struct *tty, int cmd, void *args) +{ + int ret = 0; + void *p = (void *)args; + struct tty_struct *real_tty = RT_NULL; + + if (tty->type == TTY_DRIVER_TYPE_PTY && tty->subtype == PTY_TYPE_MASTER) + { + real_tty = tty->other_struct; + } + else + { + real_tty = tty; + } + + switch(cmd) + { + case TCGETS: + { + struct termios *tio = (struct termios *)p; + if (tio == RT_NULL) + { + return -RT_EINVAL; + } + + rt_memcpy(tio, &real_tty->init_termios, sizeof(real_tty->init_termios)); + return ret; + } + case TCSETSF: + { + return set_termios(real_tty, p, TERMIOS_FLUSH | TERMIOS_WAIT | TERMIOS_OLD); + } + case TCSETSW: + { + return set_termios(real_tty, p, TERMIOS_WAIT | TERMIOS_OLD); + } + case TCSETS: + { + return set_termios(real_tty, p, TERMIOS_OLD); + } + default: + break; + } + return -ENOIOCTLCMD; +} diff --git a/components/drivers/tty/tty_ldisc.c b/components/drivers/tty/tty_ldisc.c new file mode 100644 index 0000000000000000000000000000000000000000..f736812414dba60f3e2a9ee2011015a104d636eb --- /dev/null +++ b/components/drivers/tty/tty_ldisc.c @@ -0,0 +1,181 @@ +#include +#include + +#define DBG_TAG "TTY_LDISC" +#ifdef RT_TTY_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* RT_TTY_DEBUG */ +#include + +static struct tty_ldisc_ops *tty_ldiscs[NR_LDISCS]; + +static struct tty_ldisc_ops *get_ldops(int disc) +{ + struct tty_ldisc_ops *ldops = RT_NULL; + int level = 0; + level = rt_hw_interrupt_disable(); + ldops = tty_ldiscs[disc]; + if (ldops) + { + ldops->refcount++; + } + rt_hw_interrupt_enable(level); + return ldops; +} + +static void put_ldops(struct tty_ldisc_ops *ldops) +{ + int level = 0; + + level = rt_hw_interrupt_disable(); + ldops->refcount--; + rt_hw_interrupt_enable(level); +} +static struct tty_ldisc *tty_ldisc_get(struct tty_struct *tty, int disc) +{ + struct tty_ldisc *ld = RT_NULL; + struct tty_ldisc_ops *ldops = RT_NULL; + + if (disc < N_TTY || disc >= NR_LDISCS) + { + return RT_NULL; + } + + ldops = get_ldops(disc); + if (ldops == RT_NULL) + { + LOG_E("tty ldisc get error\n"); + return RT_NULL; + } + + ld = rt_malloc(sizeof(struct tty_ldisc)); + if (ld == RT_NULL) + { + ldops->refcount--; + return RT_NULL; + } + + ld->ops = ldops; + ld->tty = tty; + + return ld; +} + +/** + * tty_ldisc_put - release the ldisc + * + * Complement of tty_ldisc_get(). + */ +static void tty_ldisc_put(struct tty_ldisc *ld) +{ + if (ld == RT_NULL) + { + return; + } + + put_ldops(ld->ops); + rt_free(ld); +} + +/** + * tty_ldisc_close - close a line discipline + * @tty: tty we are opening the ldisc on + * @ld: discipline to close + * + * A helper close method. Also a convenient debugging and check + * point. + */ + +static void tty_ldisc_close(struct tty_struct *tty, struct tty_ldisc *ld) +{ + if (ld->ops->close) + { + ld->ops->close(tty); + } +} + +/** + * tty_ldisc_kill - teardown ldisc + * @tty: tty being released + * + * Perform final close of the ldisc and reset tty->ldisc + */ +void tty_ldisc_kill(struct tty_struct *tty) +{ + if (!tty->ldisc) + { + return; + } + + /* + * Now kill off the ldisc + */ + tty_ldisc_close(tty, tty->ldisc); + tty_ldisc_put(tty->ldisc); + /* Force an oops if we mess this up */ + tty->ldisc = NULL; +} + +int tty_register_ldisc(int disc, struct tty_ldisc_ops *new_ldisc) +{ + int ret = 0; + int level = 0; + + if (disc < N_TTY || disc >= NR_LDISCS) + { + return -EINVAL; + } + + level = rt_hw_interrupt_disable(); + tty_ldiscs[disc] = new_ldisc; + new_ldisc->num = disc; + new_ldisc->refcount = 0; + rt_hw_interrupt_enable(level); + + return ret; +} + +/** + * tty_ldisc_release - release line discipline + * @tty: tty being shut down (or one end of pty pair) + * + * Called during the final close of a tty or a pty pair in order to shut + * down the line discpline layer. On exit, each tty's ldisc is NULL. + */ + +void tty_ldisc_release(struct tty_struct *tty) +{ + int level = 0; + struct tty_struct *o_tty = tty->other_struct; + + /* + * Shutdown this line discipline. As this is the final close, + * it does not race with the set_ldisc code path. + */ + + level = rt_hw_interrupt_disable(); + tty_ldisc_kill(tty); + if (o_tty) + { + tty_ldisc_kill(o_tty); + } + rt_hw_interrupt_enable(level); + +} + +/** + * tty_ldisc_init - ldisc setup for new tty + * @tty: tty being allocated + * + * Set up the line discipline objects for a newly allocated tty. Note that + * the tty structure is not completely set up when this call is made. + */ + +void tty_ldisc_init(struct tty_struct *tty) +{ + struct tty_ldisc *ld = tty_ldisc_get(tty, N_TTY); + RT_ASSERT(ld != RT_NULL); + tty->ldisc = ld; +} diff --git a/components/drivers/wlan/wlan_cmd.c b/components/drivers/wlan/wlan_cmd.c index fead6a8bf233e5406037c67c829443eebdee2114..87ecba15df037b825beb735994c5fbe164755ad5 100644 --- a/components/drivers/wlan/wlan_cmd.c +++ b/components/drivers/wlan/wlan_cmd.c @@ -586,7 +586,7 @@ static int wifi_msh(int argc, char *argv[]) return 0; } -#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) +#if defined(RT_USING_FINSH) FINSH_FUNCTION_EXPORT_ALIAS(wifi_msh, __cmd_wifi, wifi command.); #endif diff --git a/components/finsh/Kconfig b/components/finsh/Kconfig index 8722fcd79a20aa1a58f9f6ca371392b7510d79bb..6f42aa704f5dc45da208d4dabc0e36247ca57b0f 100644 --- a/components/finsh/Kconfig +++ b/components/finsh/Kconfig @@ -1,13 +1,22 @@ menu "Command shell" config RT_USING_FINSH - bool "finsh shell" + bool + default n + +config RT_USING_MSH + bool "msh shell" + select RT_USING_FINSH default y -if RT_USING_FINSH +if RT_USING_MSH + +config FINSH_USING_MSH + bool + default y config FINSH_THREAD_NAME - string "The finsh thread name" + string "The msh thread name" default "tshell" config FINSH_USING_HISTORY bool "Enable command history feature" @@ -31,11 +40,11 @@ config FINSH_ECHO_DISABLE_DEFAULT default n config FINSH_THREAD_PRIORITY - int "The priority level value of finsh thread" + int "The priority level value of thread" default 20 config FINSH_THREAD_STACK_SIZE - int "The stack size for finsh thread" + int "The stack size for thread" default 4096 config FINSH_CMD_SIZE @@ -58,23 +67,9 @@ config FINSH_PASSWORD_MAX default RT_NAME_MAX endif -config FINSH_USING_MSH - bool "Using module shell" - default y - -if FINSH_USING_MSH -config FINSH_USING_MSH_DEFAULT - bool "Using module shell in default" - default y - -config FINSH_USING_MSH_ONLY - bool "Only using module shell" - default n - config FINSH_ARG_MAX - int "The command arg num for shell" + int "The number of arguments for a shell command" default 10 -endif endif diff --git a/components/finsh/SConscript b/components/finsh/SConscript index be04c566164570dceefd5bccc2754ce0e26ea7dc..a2f025b3a618573f4d6711448676375c41adf9b6 100644 --- a/components/finsh/SConscript +++ b/components/finsh/SConscript @@ -1,39 +1,18 @@ -Import('rtconfig') from building import * cwd = GetCurrentDir() src = Split(''' shell.c cmd.c +msh.c ''') -fsh_src = Split(''' -finsh_compiler.c -finsh_error.c -finsh_heap.c -finsh_init.c -finsh_node.c -finsh_ops.c -finsh_parser.c -finsh_var.c -finsh_vm.c -finsh_token.c -''') - -msh_src = Glob('msh.c') if GetDepend('RT_USING_DFS'): - msh_src += ['msh_file.c'] - -if not GetDepend('FINSH_USING_SYMTAB'): - src += ['symbol.c'] -if GetDepend('FINSH_USING_MSH'): - src = src + msh_src -if not GetDepend('FINSH_USING_MSH_ONLY'): - src = src + fsh_src + src += ['msh_file.c'] CPPPATH = [cwd] -group = DefineGroup('finsh', src, depend = ['RT_USING_FINSH'], CPPPATH = CPPPATH) +group = DefineGroup('msh', src, depend = ['RT_USING_FINSH'], CPPPATH = CPPPATH) Return('group') diff --git a/components/finsh/cmd.c b/components/finsh/cmd.c index afbda59e908aa320b33a06124ed21d18e22a08ec..2d136814e838f227103521b0d4a0cf40b15e3704 100644 --- a/components/finsh/cmd.c +++ b/components/finsh/cmd.c @@ -27,17 +27,17 @@ * 2012-10-22 Bernard add MS VC++ patch. * 2016-06-02 armink beautify the list_thread command * 2018-11-22 Jesven list_thread add smp support - * 2018-12-27 Jesven Fix the problem that disable interrupt too long in list_thread + * 2018-12-27 Jesven Fix the problem that disable interrupt too long in list_thread * Provide protection for the "first layer of objects" when list_* - * 2020-04-07 chenhui add clear + * 2020-04-07 chenhui add clear */ #include #include +#include #ifdef RT_USING_FINSH - -#include "finsh.h" +#include #define LIST_FIND_OBJ_NR 8 @@ -47,7 +47,7 @@ long hello(void) return 0; } -FINSH_FUNCTION_EXPORT(hello, say hello world); +MSH_CMD_EXPORT(hello, say hello world); static long clear(void) { @@ -55,8 +55,7 @@ static long clear(void) return 0; } -FINSH_FUNCTION_EXPORT(clear,clear the terminal screen); -MSH_CMD_EXPORT(clear,clear the terminal screen); +MSH_CMD_EXPORT(clear, clear the terminal screen); extern void rt_show_version(void); long version(void) @@ -65,7 +64,6 @@ long version(void) return 0; } -FINSH_FUNCTION_EXPORT(version, show RT-Thread version information); MSH_CMD_EXPORT(version, show RT-Thread version information); rt_inline void object_split(int len) @@ -156,7 +154,7 @@ static rt_list_t *list_get_next(rt_list_t *current, list_get_next_t *arg) break; } } - + rt_hw_interrupt_enable(level); arg->nr_out = nr; return node; @@ -202,7 +200,7 @@ long list_thread(void) continue; } /* copy info */ - memcpy(&thread_info, obj, sizeof thread_info); + rt_memcpy(&thread_info, obj, sizeof thread_info); rt_hw_interrupt_enable(level); thread = (struct rt_thread*)obj; @@ -221,7 +219,7 @@ long list_thread(void) #endif /*RT_USING_SMP*/ stat = (thread->stat & RT_THREAD_STAT_MASK); if (stat == RT_THREAD_READY) rt_kprintf(" ready "); - else if (stat == RT_THREAD_SUSPEND) rt_kprintf(" suspend"); + else if ((stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) rt_kprintf(" suspend"); else if (stat == RT_THREAD_INIT) rt_kprintf(" init "); else if (stat == RT_THREAD_CLOSE) rt_kprintf(" close "); else if (stat == RT_THREAD_RUNNING) rt_kprintf(" running"); @@ -256,7 +254,6 @@ long list_thread(void) return 0; } -FINSH_FUNCTION_EXPORT(list_thread, list thread); MSH_CMD_EXPORT(list_thread, list thread); static void show_wait_queue(struct rt_list_node *list) @@ -267,7 +264,7 @@ static void show_wait_queue(struct rt_list_node *list) for (node = list->next; node != list; node = node->next) { thread = rt_list_entry(node, struct rt_thread, tlist); - rt_kprintf("%s", thread->name); + rt_kprintf("%.*s", RT_NAME_MAX, thread->name); if (node->next != list) rt_kprintf("/"); @@ -337,7 +334,6 @@ long list_sem(void) return 0; } -FINSH_FUNCTION_EXPORT(list_sem, list semaphore in system); MSH_CMD_EXPORT(list_sem, list semaphore in system); #endif @@ -402,7 +398,6 @@ long list_event(void) return 0; } -FINSH_FUNCTION_EXPORT(list_event, list event in system); MSH_CMD_EXPORT(list_event, list event in system); #endif @@ -460,7 +455,6 @@ long list_mutex(void) return 0; } -FINSH_FUNCTION_EXPORT(list_mutex, list mutex in system); MSH_CMD_EXPORT(list_mutex, list mutex in system); #endif @@ -531,7 +525,6 @@ long list_mailbox(void) return 0; } -FINSH_FUNCTION_EXPORT(list_mailbox, list mail box in system); MSH_CMD_EXPORT(list_mailbox, list mail box in system); #endif @@ -598,7 +591,6 @@ long list_msgqueue(void) return 0; } -FINSH_FUNCTION_EXPORT(list_msgqueue, list message queue in system); MSH_CMD_EXPORT(list_msgqueue, list message queue in system); #endif @@ -655,7 +647,6 @@ long list_memheap(void) return 0; } -FINSH_FUNCTION_EXPORT(list_memheap, list memory heap in system); MSH_CMD_EXPORT(list_memheap, list memory heap in system); #endif @@ -735,7 +726,6 @@ long list_mempool(void) return 0; } -FINSH_FUNCTION_EXPORT(list_mempool, list memory pool in system) MSH_CMD_EXPORT(list_mempool, list memory pool in system); #endif @@ -794,7 +784,6 @@ long list_timer(void) return 0; } -FINSH_FUNCTION_EXPORT(list_timer, list timer in system); MSH_CMD_EXPORT(list_timer, list timer in system); #ifdef RT_USING_DEVICE @@ -877,17 +866,11 @@ long list_device(void) return 0; } -FINSH_FUNCTION_EXPORT(list_device, list device in system); MSH_CMD_EXPORT(list_device, list device in system); #endif long list(void) { -#ifndef FINSH_USING_MSH_ONLY - struct finsh_syscall_item *syscall_item; - struct finsh_sysvar_item *sysvar_item; -#endif - rt_kprintf("--Function List:\n"); { struct finsh_syscall *index; @@ -906,247 +889,8 @@ long list(void) } } -#ifndef FINSH_USING_MSH_ONLY - /* list syscall list */ - syscall_item = global_syscall_list; - while (syscall_item != NULL) - { - rt_kprintf("[l] %s\n", syscall_item->syscall.name); - syscall_item = syscall_item->next; - } - - rt_kprintf("--Variable List:\n"); - { - struct finsh_sysvar *index; - for (index = _sysvar_table_begin; - index < _sysvar_table_end; - FINSH_NEXT_SYSVAR(index)) - { -#ifdef FINSH_USING_DESCRIPTION - rt_kprintf("%-16s -- %s\n", index->name, index->desc); -#else - rt_kprintf("%s\n", index->name); -#endif - } - } - - sysvar_item = global_sysvar_list; - while (sysvar_item != NULL) - { - rt_kprintf("[l] %s\n", sysvar_item->sysvar.name); - sysvar_item = sysvar_item->next; - } -#endif - return 0; } -FINSH_FUNCTION_EXPORT(list, list all symbol in system) - -#ifndef FINSH_USING_MSH_ONLY -static int str_is_prefix(const char *prefix, const char *str) -{ - while ((*prefix) && (*prefix == *str)) - { - prefix ++; - str ++; - } - - if (*prefix == 0) - return 0; - - return -1; -} - -static int str_common(const char *str1, const char *str2) -{ - const char *str = str1; - - while ((*str != 0) && (*str2 != 0) && (*str == *str2)) - { - str ++; - str2 ++; - } - - return (str - str1); -} - -void list_prefix(char *prefix) -{ - struct finsh_syscall_item *syscall_item; - struct finsh_sysvar_item *sysvar_item; - rt_uint16_t func_cnt, var_cnt; - int length, min_length; - const char *name_ptr; - - func_cnt = 0; - var_cnt = 0; - min_length = 0; - name_ptr = RT_NULL; - - /* checks in system function call */ - { - struct finsh_syscall *index; - for (index = _syscall_table_begin; - index < _syscall_table_end; - FINSH_NEXT_SYSCALL(index)) - { - /* skip internal command */ - if (str_is_prefix("__", index->name) == 0) continue; - - if (str_is_prefix(prefix, index->name) == 0) - { - if (func_cnt == 0) - { - rt_kprintf("--function:\n"); - - if (*prefix != 0) - { - /* set name_ptr */ - name_ptr = index->name; - - /* set initial length */ - min_length = strlen(name_ptr); - } - } - - func_cnt ++; - - if (*prefix != 0) - { - length = str_common(name_ptr, index->name); - if (length < min_length) - min_length = length; - } - -#ifdef FINSH_USING_DESCRIPTION - rt_kprintf("%-16s -- %s\n", index->name, index->desc); -#else - rt_kprintf("%s\n", index->name); -#endif - } - } - } - - /* checks in dynamic system function call */ - syscall_item = global_syscall_list; - while (syscall_item != NULL) - { - if (str_is_prefix(prefix, syscall_item->syscall.name) == 0) - { - if (func_cnt == 0) - { - rt_kprintf("--function:\n"); - if (*prefix != 0 && name_ptr == NULL) - { - /* set name_ptr */ - name_ptr = syscall_item->syscall.name; - - /* set initial length */ - min_length = strlen(name_ptr); - } - } - - func_cnt ++; - - if (*prefix != 0) - { - length = str_common(name_ptr, syscall_item->syscall.name); - if (length < min_length) - min_length = length; - } - - rt_kprintf("[l] %s\n", syscall_item->syscall.name); - } - syscall_item = syscall_item->next; - } - - /* checks in system variable */ - { - struct finsh_sysvar *index; - for (index = _sysvar_table_begin; - index < _sysvar_table_end; - FINSH_NEXT_SYSVAR(index)) - { - if (str_is_prefix(prefix, index->name) == 0) - { - if (var_cnt == 0) - { - rt_kprintf("--variable:\n"); - - if (*prefix != 0 && name_ptr == NULL) - { - /* set name_ptr */ - name_ptr = index->name; - - /* set initial length */ - min_length = strlen(name_ptr); - - } - } - - var_cnt ++; - - if (*prefix != 0) - { - length = str_common(name_ptr, index->name); - if (length < min_length) - min_length = length; - } - -#ifdef FINSH_USING_DESCRIPTION - rt_kprintf("%-16s -- %s\n", index->name, index->desc); -#else - rt_kprintf("%s\n", index->name); -#endif - } - } - } - - /* checks in dynamic system variable */ - sysvar_item = global_sysvar_list; - while (sysvar_item != NULL) - { - if (str_is_prefix(prefix, sysvar_item->sysvar.name) == 0) - { - if (var_cnt == 0) - { - rt_kprintf("--variable:\n"); - if (*prefix != 0 && name_ptr == NULL) - { - /* set name_ptr */ - name_ptr = sysvar_item->sysvar.name; - - /* set initial length */ - min_length = strlen(name_ptr); - } - } - - var_cnt ++; - - if (*prefix != 0) - { - length = str_common(name_ptr, sysvar_item->sysvar.name); - if (length < min_length) - min_length = length; - } - - rt_kprintf("[v] %s\n", sysvar_item->sysvar.name); - } - sysvar_item = sysvar_item->next; - } - - /* only one matched */ - if (name_ptr != NULL) - { - rt_strncpy(prefix, name_ptr, min_length); - } -} -#endif - -#if defined(FINSH_USING_SYMTAB) && !defined(FINSH_USING_MSH_ONLY) -static int dummy = 0; -FINSH_VAR_EXPORT(dummy, finsh_type_int, dummy variable for finsh) -#endif +MSH_CMD_EXPORT(list, list all symbol in system) #endif /* RT_USING_FINSH */ - diff --git a/components/finsh/finsh.h b/components/finsh/finsh.h index 7276ea7ce13915379cb6c648173dfa4bc1c8dca1..13924fb22990e6f6d732c57cc9d3d994be4cd0fa 100644 --- a/components/finsh/finsh.h +++ b/components/finsh/finsh.h @@ -11,73 +11,137 @@ #define __FINSH_H__ #include -#include "finsh_api.h" -/* -- the beginning of option -- */ -#define FINSH_NAME_MAX 16 /* max length of identifier */ -#define FINSH_NODE_MAX 16 /* max number of node */ - -#define FINSH_HEAP_MAX 128 /* max length of heap */ -#define FINSH_STRING_MAX 128 /* max length of string */ -#define FINSH_VARIABLE_MAX 8 /* max number of variable */ - -#define FINSH_STACK_MAX 64 /* max stack size */ -#define FINSH_TEXT_MAX 128 /* max text segment size */ - -#define HEAP_ALIGNMENT 4 /* heap alignment */ +#if defined(_MSC_VER) +#pragma section("FSymTab$f",read) +#endif -#define FINSH_GET16(x) (*(x)) | (*((x)+1) << 8) -#define FINSH_GET32(x) (rt_ubase_t)(*(x)) | ((rt_ubase_t)*((x)+1) << 8) | \ - ((rt_ubase_t)*((x)+2) << 16) | ((rt_ubase_t)*((x)+3) << 24) +typedef long (*syscall_func)(void); -#define FINSH_SET16(x, v) \ - do \ - { \ - *(x) = (v) & 0x00ff; \ - (*((x)+1)) = (v) >> 8; \ - } while ( 0 ) +#ifdef FINSH_USING_SYMTAB -#define FINSH_SET32(x, v) \ - do \ - { \ - *(x) = (rt_uint32_t)(v) & 0x000000ff; \ - (*((x)+1)) = ((rt_uint32_t)(v) >> 8) & 0x000000ff; \ - (*((x)+2)) = ((rt_uint32_t)(v) >> 16) & 0x000000ff; \ - (*((x)+3)) = ((rt_uint32_t)(v) >> 24); \ - } while ( 0 ) +#ifdef __TI_COMPILER_VERSION__ +#define __TI_FINSH_EXPORT_FUNCTION(f) PRAGMA(DATA_SECTION(f,"FSymTab")) +#endif -/* -- the end of option -- */ + #ifdef FINSH_USING_DESCRIPTION + #ifdef _MSC_VER + #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ + const char __fsym_##cmd##_name[] = #cmd; \ + const char __fsym_##cmd##_desc[] = #desc; \ + __declspec(allocate("FSymTab$f")) \ + const struct finsh_syscall __fsym_##cmd = \ + { \ + __fsym_##cmd##_name, \ + __fsym_##cmd##_desc, \ + (syscall_func)&name \ + }; + #pragma comment(linker, "/merge:FSymTab=mytext") + + #elif defined(__TI_COMPILER_VERSION__) + #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ + __TI_FINSH_EXPORT_FUNCTION(__fsym_##cmd); \ + const char __fsym_##cmd##_name[] = #cmd; \ + const char __fsym_##cmd##_desc[] = #desc; \ + const struct finsh_syscall __fsym_##cmd = \ + { \ + __fsym_##cmd##_name, \ + __fsym_##cmd##_desc, \ + (syscall_func)&name \ + }; + + #else + #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ + const char __fsym_##cmd##_name[] SECTION(".rodata.name") = #cmd; \ + const char __fsym_##cmd##_desc[] SECTION(".rodata.name") = #desc; \ + RT_USED const struct finsh_syscall __fsym_##cmd SECTION("FSymTab")= \ + { \ + __fsym_##cmd##_name, \ + __fsym_##cmd##_desc, \ + (syscall_func)&name \ + }; + + #endif + #else + #ifdef _MSC_VER + #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ + const char __fsym_##cmd##_name[] = #cmd; \ + __declspec(allocate("FSymTab$f")) \ + const struct finsh_syscall __fsym_##cmd = \ + { \ + __fsym_##cmd##_name, \ + (syscall_func)&name \ + }; + #pragma comment(linker, "/merge:FSymTab=mytext") + + #elif defined(__TI_COMPILER_VERSION__) + #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ + __TI_FINSH_EXPORT_FUNCTION(__fsym_##cmd); \ + const char __fsym_##cmd##_name[] = #cmd; \ + const struct finsh_syscall __fsym_##cmd = \ + { \ + __fsym_##cmd##_name, \ + (syscall_func)&name \ + }; + + #else + #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ + const char __fsym_##cmd##_name[] = #cmd; \ + RT_USED const struct finsh_syscall __fsym_##cmd SECTION("FSymTab")= \ + { \ + __fsym_##cmd##_name, \ + (syscall_func)&name \ + }; + + #endif + #endif /* end of FINSH_USING_DESCRIPTION */ +#endif /* end of FINSH_USING_SYMTAB */ -/* std header file */ -#include -#include -#include -#include -#include +/** + * @ingroup finsh + * + * This macro exports a system function to finsh shell. + * + * @param name the name of function. + * @param desc the description of function, which will show in help. + */ +#define FINSH_FUNCTION_EXPORT(name, desc) \ + FINSH_FUNCTION_EXPORT_CMD(name, name, desc) -#define FINSH_VERSION_MAJOR 1 -#define FINSH_VERSION_MINOR 0 +/** + * @ingroup finsh + * + * This macro exports a system function with an alias name to finsh shell. + * + * @param name the name of function. + * @param alias the alias name of function. + * @param desc the description of function, which will show in help. + */ +#define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc) \ + FINSH_FUNCTION_EXPORT_CMD(name, alias, desc) /** - * @addtogroup finsh + * @ingroup finsh + * + * This macro exports a command to module shell. + * + * @param command the name of command. + * @param desc the description of command, which will show in help. */ -/*@{*/ -#define FINSH_ERROR_OK 0 /**< No error */ -#define FINSH_ERROR_INVALID_TOKEN 1 /**< Invalid token */ -#define FINSH_ERROR_EXPECT_TYPE 2 /**< Expect a type */ -#define FINSH_ERROR_UNKNOWN_TYPE 3 /**< Unknown type */ -#define FINSH_ERROR_VARIABLE_EXIST 4 /**< Variable exist */ -#define FINSH_ERROR_EXPECT_OPERATOR 5 /**< Expect a operator */ -#define FINSH_ERROR_MEMORY_FULL 6 /**< Memory full */ -#define FINSH_ERROR_UNKNOWN_OP 7 /**< Unknown operator */ -#define FINSH_ERROR_UNKNOWN_NODE 8 /**< Unknown node */ -#define FINSH_ERROR_EXPECT_CHAR 9 /**< Expect a character */ -#define FINSH_ERROR_UNEXPECT_END 10 /**< Unexpect end */ -#define FINSH_ERROR_UNKNOWN_TOKEN 11 /**< Unknown token */ -#define FINSH_ERROR_NO_FLOAT 12 /**< Float not supported */ -#define FINSH_ERROR_UNKNOWN_SYMBOL 13 /**< Unknown symbol */ -#define FINSH_ERROR_NULL_NODE 14 /**< Null node */ -/*@}*/ +#define MSH_CMD_EXPORT(command, desc) \ + FINSH_FUNCTION_EXPORT_CMD(command, __cmd_##command, desc) +#define MSH_CMD_EXPORT_ALIAS(command, alias, desc) \ + FINSH_FUNCTION_EXPORT_ALIAS(command, __cmd_##alias, desc) + +/* system call table */ +struct finsh_syscall +{ + const char* name; /* the name of system call */ +#if defined(FINSH_USING_DESCRIPTION) && defined(FINSH_USING_SYMTAB) + const char* desc; /* description of system call */ +#endif + syscall_func func; /* the function address of system call */ +}; /* system call item */ struct finsh_syscall_item @@ -85,165 +149,22 @@ struct finsh_syscall_item struct finsh_syscall_item* next; /* next item */ struct finsh_syscall syscall; /* syscall */ }; -extern struct finsh_syscall_item *global_syscall_list; -/* system variable table */ -struct finsh_sysvar -{ - const char* name; /* the name of variable */ -#if defined(FINSH_USING_DESCRIPTION) && defined(FINSH_USING_SYMTAB) - const char* desc; /* description of system variable */ -#endif - uint8_t type; /* the type of variable */ - void* var ; /* the address of variable */ -}; +extern struct finsh_syscall_item *global_syscall_list; +extern struct finsh_syscall *_syscall_table_begin, *_syscall_table_end; #if defined(_MSC_VER) || (defined(__GNUC__) && defined(__x86_64__)) struct finsh_syscall* finsh_syscall_next(struct finsh_syscall* call); -struct finsh_sysvar* finsh_sysvar_next(struct finsh_sysvar* call); #define FINSH_NEXT_SYSCALL(index) index=finsh_syscall_next(index) -#define FINSH_NEXT_SYSVAR(index) index=finsh_sysvar_next(index) #else #define FINSH_NEXT_SYSCALL(index) index++ -#define FINSH_NEXT_SYSVAR(index) index++ #endif -/* system variable item */ -struct finsh_sysvar_item -{ - struct finsh_sysvar_item *next; /* next item */ - struct finsh_sysvar sysvar; /* system variable */ -}; -extern struct finsh_sysvar *_sysvar_table_begin, *_sysvar_table_end; -extern struct finsh_sysvar_item* global_sysvar_list; - -/* find out system variable, which should be implemented in user program */ -struct finsh_sysvar* finsh_sysvar_lookup(const char* name); - +/* find out system call, which should be implemented in user program */ +struct finsh_syscall* finsh_syscall_lookup(const char* name); -struct finsh_token -{ - char eof; - char replay; - - int position; - uint8_t current_token; - - union { - char char_value; - int int_value; - long long_value; - } value; - uint8_t string[FINSH_STRING_MAX]; - - uint8_t* line; -}; - -#define FINSH_IDTYPE_VAR 0x01 -#define FINSH_IDTYPE_SYSVAR 0x02 -#define FINSH_IDTYPE_SYSCALL 0x04 -#define FINSH_IDTYPE_ADDRESS 0x08 -struct finsh_node -{ - uint8_t node_type; /* node node_type */ - uint8_t data_type; /* node data node_type */ - uint8_t idtype; /* id node information */ - - union { /* value node */ - char char_value; - short short_value; - int int_value; - long long_value; - void* ptr; - } value; - union - { - /* point to variable identifier or function identifier */ - struct finsh_var *var; - struct finsh_sysvar *sysvar; - struct finsh_syscall*syscall; - }id; - - /* sibling and child node */ - struct finsh_node *sibling, *child; -}; - -struct finsh_parser -{ - uint8_t* parser_string; - - struct finsh_token token; - struct finsh_node* root; -}; - -/** - * @ingroup finsh - * - * The basic data type in finsh shell - */ -enum finsh_type { - finsh_type_unknown = 0, /**< unknown data type */ - finsh_type_void, /**< void */ - finsh_type_voidp, /**< void pointer */ - finsh_type_char, /**< char */ - finsh_type_uchar, /**< unsigned char */ - finsh_type_charp, /**< char pointer */ - finsh_type_short, /**< short */ - finsh_type_ushort, /**< unsigned short */ - finsh_type_shortp, /**< short pointer */ - finsh_type_int, /**< int */ - finsh_type_uint, /**< unsigned int */ - finsh_type_intp, /**< int pointer */ - finsh_type_long, /**< long */ - finsh_type_ulong, /**< unsigned long */ - finsh_type_longp /**< long pointer */ -}; - -/* init finsh environment */ -int finsh_init(struct finsh_parser* parser); -/* flush finsh node, text segment */ -int finsh_flush(struct finsh_parser* parser); -/* reset all of finsh */ -int finsh_reset(struct finsh_parser* parser); #ifdef RT_USING_DEVICE void finsh_set_device(const char* device_name); #endif -/* run finsh parser to generate abstract synatx tree */ -void finsh_parser_run (struct finsh_parser* parser, const unsigned char* string); -/* run compiler to compile abstract syntax tree */ -int finsh_compiler_run(struct finsh_node* node); -/* run finsh virtual machine */ -void finsh_vm_run(void); - -/* get variable value */ -struct finsh_var* finsh_var_lookup(const char* name); -/* get bottom value of stack */ -long finsh_stack_bottom(void); - -/* get error number of finsh */ -uint8_t finsh_errno(void); -/* get error string */ -const char* finsh_error_string(uint8_t type); - -#ifdef RT_USING_HEAP -/** - * @ingroup finsh - * - * This function appends a system call to finsh runtime environment - * @param name the name of system call - * @param func the function pointer of system call - */ -void finsh_syscall_append(const char* name, syscall_func func); - -/** - * @ingroup finsh - * - * This function appends a system variable to finsh runtime environment - * @param name the name of system variable - * @param type the data type of system variable - * @param addr the address of system variable - */ -void finsh_sysvar_append(const char* name, uint8_t type, void* addr); -#endif #endif diff --git a/components/finsh/finsh_api.h b/components/finsh/finsh_api.h deleted file mode 100644 index c601415d824b46c329322a602f38555876a1320d..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_api.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#ifndef FINSH_API_H__ -#define FINSH_API_H__ - -#if defined(_MSC_VER) -#pragma section("FSymTab$f",read) -#pragma section("VSymTab",read) -#endif - -typedef long (*syscall_func)(void); - -/* system call table */ -struct finsh_syscall -{ - const char* name; /* the name of system call */ -#if defined(FINSH_USING_DESCRIPTION) && defined(FINSH_USING_SYMTAB) - const char* desc; /* description of system call */ -#endif - syscall_func func; /* the function address of system call */ -}; -extern struct finsh_syscall *_syscall_table_begin, *_syscall_table_end; - -/* find out system call, which should be implemented in user program */ -struct finsh_syscall* finsh_syscall_lookup(const char* name); - -#ifdef FINSH_USING_SYMTAB - -#ifdef __TI_COMPILER_VERSION__ -#define __TI_FINSH_EXPORT_FUNCTION(f) PRAGMA(DATA_SECTION(f,"FSymTab")) -#define __TI_FINSH_EXPORT_VAR(v) PRAGMA(DATA_SECTION(v,"VSymTab")) -#endif - - #ifdef FINSH_USING_DESCRIPTION - #ifdef _MSC_VER - #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ - const char __fsym_##cmd##_name[] = #cmd; \ - const char __fsym_##cmd##_desc[] = #desc; \ - __declspec(allocate("FSymTab$f")) \ - const struct finsh_syscall __fsym_##cmd = \ - { \ - __fsym_##cmd##_name, \ - __fsym_##cmd##_desc, \ - (syscall_func)&name \ - }; - #pragma comment(linker, "/merge:FSymTab=mytext") - - #define FINSH_VAR_EXPORT(name, type, desc) \ - const char __vsym_##name##_name[] = #name; \ - const char __vsym_##name##_desc[] = #desc; \ - __declspec(allocate("VSymTab")) \ - const struct finsh_sysvar __vsym_##name = \ - { \ - __vsym_##name##_name, \ - __vsym_##name##_desc, \ - type, \ - (void*)&name \ - }; - - #elif defined(__TI_COMPILER_VERSION__) - #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ - __TI_FINSH_EXPORT_FUNCTION(__fsym_##cmd); \ - const char __fsym_##cmd##_name[] = #cmd; \ - const char __fsym_##cmd##_desc[] = #desc; \ - const struct finsh_syscall __fsym_##cmd = \ - { \ - __fsym_##cmd##_name, \ - __fsym_##cmd##_desc, \ - (syscall_func)&name \ - }; - - #define FINSH_VAR_EXPORT(name, type, desc) \ - __TI_FINSH_EXPORT_VAR(__vsym_##name); \ - const char __vsym_##name##_name[] = #name; \ - const char __vsym_##name##_desc[] = #desc; \ - const struct finsh_sysvar __vsym_##name = \ - { \ - __vsym_##name##_name, \ - __vsym_##name##_desc, \ - type, \ - (void*)&name \ - }; - - #else - #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ - const char __fsym_##cmd##_name[] SECTION(".rodata.name") = #cmd; \ - const char __fsym_##cmd##_desc[] SECTION(".rodata.name") = #desc; \ - RT_USED const struct finsh_syscall __fsym_##cmd SECTION("FSymTab")= \ - { \ - __fsym_##cmd##_name, \ - __fsym_##cmd##_desc, \ - (syscall_func)&name \ - }; - - #define FINSH_VAR_EXPORT(name, type, desc) \ - const char __vsym_##name##_name[] SECTION(".rodata.name") = #name; \ - const char __vsym_##name##_desc[] SECTION(".rodata.name") = #desc; \ - RT_USED const struct finsh_sysvar __vsym_##name SECTION("VSymTab")= \ - { \ - __vsym_##name##_name, \ - __vsym_##name##_desc, \ - type, \ - (void*)&name \ - }; - - #endif - #else - #ifdef _MSC_VER - #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ - const char __fsym_##cmd##_name[] = #cmd; \ - __declspec(allocate("FSymTab$f")) \ - const struct finsh_syscall __fsym_##cmd = \ - { \ - __fsym_##cmd##_name, \ - (syscall_func)&name \ - }; - #pragma comment(linker, "/merge:FSymTab=mytext") - - #define FINSH_VAR_EXPORT(name, type, desc) \ - const char __vsym_##name##_name[] = #name; \ - __declspec(allocate("VSymTab")) const struct finsh_sysvar __vsym_##name = \ - { \ - __vsym_##name##_name, \ - type, \ - (void*)&name \ - }; - - #elif defined(__TI_COMPILER_VERSION__) - #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ - __TI_FINSH_EXPORT_FUNCTION(__fsym_##cmd); \ - const char __fsym_##cmd##_name[] = #cmd; \ - const struct finsh_syscall __fsym_##cmd = \ - { \ - __fsym_##cmd##_name, \ - (syscall_func)&name \ - }; - - #define FINSH_VAR_EXPORT(name, type, desc) \ - __TI_FINSH_EXPORT_VAR(__vsym_##name); \ - const char __vsym_##name##_name[] = #name; \ - const struct finsh_sysvar __vsym_##name = \ - { \ - __vsym_##name##_name, \ - type, \ - (void*)&name \ - }; - - #else - #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ - const char __fsym_##cmd##_name[] = #cmd; \ - RT_USED const struct finsh_syscall __fsym_##cmd SECTION("FSymTab")= \ - { \ - __fsym_##cmd##_name, \ - (syscall_func)&name \ - }; - - #define FINSH_VAR_EXPORT(name, type, desc) \ - const char __vsym_##name##_name[] = #name; \ - RT_USED const struct finsh_sysvar __vsym_##name SECTION("VSymTab")= \ - { \ - __vsym_##name##_name, \ - type, \ - (void*)&name \ - }; - - #endif - #endif /* end of FINSH_USING_DESCRIPTION */ -#endif /* end of FINSH_USING_SYMTAB */ - -/** - * @ingroup finsh - * - * This macro exports a system function to finsh shell. - * - * @param name the name of function. - * @param desc the description of function, which will show in help. - */ -#define FINSH_FUNCTION_EXPORT(name, desc) \ - FINSH_FUNCTION_EXPORT_CMD(name, name, desc) - -/** - * @ingroup finsh - * - * This macro exports a system function with an alias name to finsh shell. - * - * @param name the name of function. - * @param alias the alias name of function. - * @param desc the description of function, which will show in help. - */ -#define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc) \ - FINSH_FUNCTION_EXPORT_CMD(name, alias, desc) - -/** - * @ingroup finsh - * - * This macro exports a command to module shell. - * - * @param command the name of command. - * @param desc the description of command, which will show in help. - */ -#ifdef FINSH_USING_MSH -#define MSH_CMD_EXPORT(command, desc) \ - FINSH_FUNCTION_EXPORT_CMD(command, __cmd_##command, desc) -#define MSH_CMD_EXPORT_ALIAS(command, alias, desc) \ - FINSH_FUNCTION_EXPORT_ALIAS(command, __cmd_##alias, desc) -#else -#define MSH_CMD_EXPORT(command, desc) -#define MSH_CMD_EXPORT_ALIAS(command, alias, desc) -#endif - -#endif diff --git a/components/finsh/finsh_compiler.c b/components/finsh/finsh_compiler.c deleted file mode 100644 index f81409bf9a24bd5399df55bfe41865faa502bf0b..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_compiler.c +++ /dev/null @@ -1,918 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#include - -#include "finsh_node.h" -#include "finsh_error.h" -#include "finsh_var.h" -#include "finsh_ops.h" - -union finsh_value* finsh_compile_sp; /* stack pointer */ -uint8_t* finsh_compile_pc; /* PC */ - -#define finsh_code_byte(x) do { *finsh_compile_pc = (x); finsh_compile_pc ++; } while(0) -#define finsh_code_word(x) do { FINSH_SET16(finsh_compile_pc, x); finsh_compile_pc +=2; } while(0) -#define finsh_code_dword(x) do { FINSH_SET32(finsh_compile_pc, x); finsh_compile_pc +=4; } while(0) - -static int finsh_compile(struct finsh_node* node) -{ - if (node != NULL) - { - /* compile child node */ - if (finsh_node_child(node) != NULL) - finsh_compile(finsh_node_child(node)); - - /* compile current node */ - switch (node->node_type) - { - case FINSH_NODE_ID: - { - /* identifier::syscall */ - if (node->idtype & FINSH_IDTYPE_SYSCALL) - { - /* load address */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword((long)node->id.syscall->func); - } - /* identifier::sysvar */ - else if (node->idtype & FINSH_IDTYPE_SYSVAR) - { - struct finsh_sysvar* sysvar; - - sysvar = node->id.sysvar; - if (sysvar != NULL) - { - switch (sysvar->type) - { - case finsh_type_char: - case finsh_type_uchar: - if (node->idtype & FINSH_IDTYPE_ADDRESS) - { - /* load address */ - finsh_code_byte(FINSH_OP_LD_DWORD); - } - else - { - /* load value */ - finsh_code_byte(FINSH_OP_LD_VALUE_BYTE); - } - - finsh_code_dword((long)(sysvar->var)); - break; - - case finsh_type_short: - case finsh_type_ushort: - if (node->idtype & FINSH_IDTYPE_ADDRESS) - { - /* load address */ - finsh_code_byte(FINSH_OP_LD_DWORD); - } - else - { - /* load value */ - finsh_code_byte(FINSH_OP_LD_VALUE_WORD); - } - - finsh_code_dword((long)(sysvar->var)); - break; - - case finsh_type_int: - case finsh_type_uint: - case finsh_type_long: - case finsh_type_ulong: - case finsh_type_charp: - case finsh_type_shortp: - case finsh_type_intp: - case finsh_type_longp: - if (node->idtype & FINSH_IDTYPE_ADDRESS) - { - /* load address */ - finsh_code_byte(FINSH_OP_LD_DWORD); - } - else - { - /* load value */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD); - } - - finsh_code_dword((long)(sysvar->var)); - break; - } - } - } - /* identifier::var */ - else - { - struct finsh_var* var; - - var = node->id.var; - if (var != NULL) - { - switch (var->type) - { - case finsh_type_char: - case finsh_type_uchar: - if (node->idtype & FINSH_IDTYPE_ADDRESS) - { - /* load address */ - finsh_code_byte(FINSH_OP_LD_DWORD); - } - else - { - /* load value */ - finsh_code_byte(FINSH_OP_LD_VALUE_BYTE); - } - - finsh_code_dword((long)&(var->value.char_value)); - break; - - case finsh_type_short: - case finsh_type_ushort: - if (node->idtype & FINSH_IDTYPE_ADDRESS) - { - /* load address */ - finsh_code_byte(FINSH_OP_LD_DWORD); - } - else - { - /* load value */ - finsh_code_byte(FINSH_OP_LD_VALUE_WORD); - } - - finsh_code_dword((long)&(var->value.short_value)); - break; - - case finsh_type_int: - case finsh_type_uint: - case finsh_type_long: - case finsh_type_ulong: - case finsh_type_charp: - case finsh_type_shortp: - case finsh_type_intp: - case finsh_type_longp: - if (node->idtype & FINSH_IDTYPE_ADDRESS) - { - /* load address */ - finsh_code_byte(FINSH_OP_LD_DWORD); - } - else - { - /* load value */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD); - } - - finsh_code_dword((long)&(var->value.long_value)); - break; - } - } - } - } - break; - - /* load const */ - case FINSH_NODE_VALUE_CHAR: - finsh_code_byte(FINSH_OP_LD_BYTE); - finsh_code_byte(node->value.char_value); - break; - - case FINSH_NODE_VALUE_INT: - case FINSH_NODE_VALUE_LONG: - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword(node->value.long_value); - break; - - case FINSH_NODE_VALUE_NULL: - case FINSH_NODE_VALUE_STRING: - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword((rt_ubase_t)node->value.ptr); - break; - - /* arithmetic operation */ - case FINSH_NODE_SYS_ADD: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_ADD_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_ADD_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_ADD_DWORD); - break; - - case FINSH_NODE_SYS_SUB: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_SUB_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_SUB_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_SUB_DWORD); - break; - - case FINSH_NODE_SYS_MUL: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_MUL_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_MUL_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_MUL_DWORD); - break; - - case FINSH_NODE_SYS_DIV: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_DIV_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_DIV_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_DIV_DWORD); - break; - - case FINSH_NODE_SYS_MOD: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_MOD_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_MOD_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_MOD_DWORD); - break; - - /* bit operation */ - case FINSH_NODE_SYS_AND: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_AND_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_AND_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_AND_DWORD); - break; - - case FINSH_NODE_SYS_OR: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_OR_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_OR_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_OR_DWORD); - break; - - case FINSH_NODE_SYS_XOR: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_XOR_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_XOR_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_XOR_DWORD); - break; - - case FINSH_NODE_SYS_BITWISE: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_BITWISE_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_BITWISE_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_BITWISE_DWORD); - break; - - case FINSH_NODE_SYS_SHL: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_SHL_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_SHL_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_SHL_DWORD); - break; - - case FINSH_NODE_SYS_SHR: - if (node->data_type == FINSH_DATA_TYPE_BYTE) finsh_code_byte(FINSH_OP_SHR_BYTE); - else if (node->data_type == FINSH_DATA_TYPE_WORD) finsh_code_byte(FINSH_OP_SHR_WORD); - else if (node->data_type == FINSH_DATA_TYPE_DWORD) finsh_code_byte(FINSH_OP_SHR_DWORD); - break; - - /* syscall */ - case FINSH_NODE_SYS_FUNC: - { - int parameters; - struct finsh_node* sibling; - - parameters = 0; - if (finsh_node_child(node) != NULL) - { - sibling = finsh_node_sibling(finsh_node_child(node)); - while (sibling != NULL) - { - parameters ++; - sibling = finsh_node_sibling(sibling); - } - - /* load address of function */ - // finsh_code_dword((long)&(node->var->value.ptr)); - - /* syscall parameters */ - finsh_code_byte(FINSH_OP_SYSCALL); - finsh_code_byte(parameters); - } - } - break; - - /* assign expression */ - case FINSH_NODE_SYS_ASSIGN: - if (finsh_node_child(node) && finsh_node_child(node)->node_type == FINSH_NODE_ID) - { - switch (finsh_node_child(node)->data_type) - { - case FINSH_DATA_TYPE_BYTE: - finsh_code_byte(FINSH_OP_ST_BYTE); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_BYTE_STACK); - break; - - case FINSH_DATA_TYPE_WORD: - finsh_code_byte(FINSH_OP_ST_WORD); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_WORD_STACK); - break; - - case FINSH_DATA_TYPE_DWORD: - finsh_code_byte(FINSH_OP_ST_DWORD); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD_STACK); - break; - - default: - finsh_error_set(FINSH_ERROR_UNKNOWN_TYPE); - } - } - else if (finsh_node_child(node)->node_type == FINSH_NODE_SYS_GETVALUE) - { - switch ((finsh_node_child(node)->data_type) & 0x0F) - { - case FINSH_DATA_TYPE_BYTE: - finsh_code_byte(FINSH_OP_ST_BYTE); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_BYTE_STACK); - break; - - case FINSH_DATA_TYPE_WORD: - finsh_code_byte(FINSH_OP_ST_WORD); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_WORD_STACK); - break; - - case FINSH_DATA_TYPE_DWORD: - finsh_code_byte(FINSH_OP_ST_DWORD); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD_STACK); - break; - - default: - finsh_error_set(FINSH_ERROR_UNKNOWN_TYPE); - } - } - break; - - /* pre-increase */ - case FINSH_NODE_SYS_PREINC: - if (finsh_node_child(node) && finsh_node_child(node)->node_type == FINSH_NODE_ID) - { - struct finsh_var* var; - var = finsh_node_child(node)->id.var; - - /* ld_dword &id */ - // finsh_code_byte(FINSH_OP_LD_DWORD); - - switch (node->data_type) - { - case FINSH_DATA_TYPE_BYTE: - /* address */ - // finsh_code_dword((long)&(var->value.char_value)); - - /* ld_value_byte &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_BYTE); - finsh_code_dword((long)&(var->value.char_value)); - - /* ld_byte 1 */ - finsh_code_byte(FINSH_OP_LD_BYTE); - finsh_code_byte(1); - - /* add_byte */ - finsh_code_byte(FINSH_OP_ADD_BYTE); - /* st_byte */ - finsh_code_byte(FINSH_OP_ST_BYTE); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD_STACK); - - break; - - case FINSH_DATA_TYPE_WORD: - /* address */ - // finsh_code_dword((long)&(var->value.short_value)); - - /* ld_value_word &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_WORD); - finsh_code_dword((long)&(var->value.short_value)); - - /* ld_word 1 */ - finsh_code_byte(FINSH_OP_LD_WORD); - finsh_code_word(1); - - /* add_word */ - finsh_code_byte(FINSH_OP_ADD_WORD); - /* st_word */ - finsh_code_byte(FINSH_OP_ST_WORD); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD_STACK); - - break; - - case FINSH_DATA_TYPE_DWORD: - /* address */ - // finsh_code_dword((long)&(var->value.long_value)); - - /* ld_dword &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD); - finsh_code_dword((long)&(var->value.long_value)); - - /* ld_dword 1 */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword(1); - - /* add_dword */ - finsh_code_byte(FINSH_OP_ADD_DWORD); - /* st_dword */ - finsh_code_byte(FINSH_OP_ST_DWORD); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD_STACK); - - break; - } - } - break; - - /* pre-decrease */ - case FINSH_NODE_SYS_PREDEC: - if (finsh_node_child(node) && finsh_node_child(node)->node_type == FINSH_NODE_ID) - { - struct finsh_var* var; - var = finsh_node_child(node)->id.var; - - /* ld_dword &id */ - // finsh_code_byte(FINSH_OP_LD_DWORD); - - switch (node->data_type) - { - case FINSH_DATA_TYPE_BYTE: - /* address */ - // finsh_code_dword((long)&(var->value.char_value)); - - /* ld_value_byte &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_BYTE); - finsh_code_dword((long)&(var->value.char_value)); - - /* ld_byte 1 */ - finsh_code_byte(FINSH_OP_LD_BYTE); - finsh_code_byte(1); - - /* add_byte */ - finsh_code_byte(FINSH_OP_SUB_BYTE); - /* st_byte */ - finsh_code_byte(FINSH_OP_ST_BYTE); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD_STACK); - - break; - - case FINSH_DATA_TYPE_WORD: - /* address */ - // finsh_code_dword((long)&(var->value.short_value)); - - /* ld_value_word &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_WORD); - finsh_code_dword((long)&(var->value.short_value)); - - /* ld_word 1 */ - finsh_code_byte(FINSH_OP_LD_WORD); - finsh_code_word(1); - - /* add_word */ - finsh_code_byte(FINSH_OP_SUB_WORD); - /* st_word */ - finsh_code_byte(FINSH_OP_ST_WORD); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD_STACK); - - break; - - case FINSH_DATA_TYPE_DWORD: - /* address */ - // finsh_code_dword((long)&(var->value.long_value)); - - /* ld_dword &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD); - finsh_code_dword((long)&(var->value.long_value)); - - /* ld_dword 1 */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword(1); - - /* add_dword */ - finsh_code_byte(FINSH_OP_SUB_DWORD); - /* st_dword */ - finsh_code_byte(FINSH_OP_ST_DWORD); - - /* load value again */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD_STACK); - - break; - } - } - break; - - /* increase */ - case FINSH_NODE_SYS_INC: - if (finsh_node_child(node) && finsh_node_child(node)->node_type == FINSH_NODE_ID) - { - struct finsh_var* var; - var = finsh_node_child(node)->id.var; - - switch (node->data_type) - { - case FINSH_DATA_TYPE_BYTE: - /* ld_value_byte &id */ - // finsh_code_byte(FINSH_OP_LD_VALUE_BYTE); - // finsh_code_dword((long)&(var->value.char_value)); - - /* ld_dword &id */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword((long)&(var->value.char_value)); - - /* ld_value_byte &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_BYTE); - finsh_code_dword((long)&(var->value.char_value)); - - /* ld_byte 1 */ - finsh_code_byte(FINSH_OP_LD_BYTE); - finsh_code_byte(1); - - /* add_byte */ - finsh_code_byte(FINSH_OP_ADD_BYTE); - /* get byte */ - finsh_code_byte(FINSH_OP_ST_BYTE); - - /* pop */ - finsh_code_byte(FINSH_OP_POP); - break; - - case FINSH_DATA_TYPE_WORD: - /* ld_value_word &id */ - // finsh_code_byte(FINSH_OP_LD_VALUE_WORD); - // finsh_code_dword((long)&(var->value.short_value)); - - /* ld_dword &id */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword((long)&(var->value.short_value)); - - /* ld_value_word &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_WORD); - finsh_code_dword((long)&(var->value.short_value)); - - /* ld_word 1 */ - finsh_code_byte(FINSH_OP_LD_WORD); - finsh_code_word(1); - - /* add_byte */ - finsh_code_byte(FINSH_OP_ADD_WORD); - /* get byte */ - finsh_code_byte(FINSH_OP_ST_WORD); - - /* pop */ - finsh_code_byte(FINSH_OP_POP); - break; - - case FINSH_DATA_TYPE_DWORD: - /* ld_value_dword &id */ - // finsh_code_byte(FINSH_OP_LD_VALUE_DWORD); - // finsh_code_dword((long)&(var->value.long_value)); - - /* ld_dword &id */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword((long)&(var->value.long_value)); - - /* ld_value_dword &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD); - finsh_code_dword((long)&(var->value.long_value)); - - /* ld_dword 1 */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword(1); - - /* add_byte */ - finsh_code_byte(FINSH_OP_ADD_DWORD); - /* get byte */ - finsh_code_byte(FINSH_OP_ST_DWORD); - - /* pop */ - finsh_code_byte(FINSH_OP_POP); - break; - } - } - break; - - /* decrease */ - case FINSH_NODE_SYS_DEC: - if (finsh_node_child(node) && finsh_node_child(node)->node_type == FINSH_NODE_ID) - { - struct finsh_var* var; - var = finsh_node_child(node)->id.var; - - switch (node->data_type) - { - case FINSH_DATA_TYPE_BYTE: - /* ld_value_byte &id */ - // finsh_code_byte(FINSH_OP_LD_VALUE_BYTE); - // finsh_code_dword((long)&(var->value.char_value)); - - /* ld_dword &id */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword((long)&(var->value.char_value)); - - /* ld_value_byte &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_BYTE); - finsh_code_dword((long)&(var->value.char_value)); - - /* ld_byte 1 */ - finsh_code_byte(FINSH_OP_LD_BYTE); - finsh_code_byte(1); - - /* add_byte */ - finsh_code_byte(FINSH_OP_SUB_BYTE); - /* get byte */ - finsh_code_byte(FINSH_OP_ST_BYTE); - - /* pop */ - finsh_code_byte(FINSH_OP_POP); - break; - - case FINSH_DATA_TYPE_WORD: - /* ld_value_word &id */ - // finsh_code_byte(FINSH_OP_LD_VALUE_WORD); - // finsh_code_dword((long)&(var->value.short_value)); - - /* ld_dword &id */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword((long)&(var->value.short_value)); - - /* ld_value_word &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_WORD); - finsh_code_dword((long)&(var->value.short_value)); - - /* ld_word 1 */ - finsh_code_byte(FINSH_OP_LD_WORD); - finsh_code_word(1); - - /* add_byte */ - finsh_code_byte(FINSH_OP_SUB_WORD); - /* get byte */ - finsh_code_byte(FINSH_OP_ST_WORD); - - /* pop */ - finsh_code_byte(FINSH_OP_POP); - break; - - case FINSH_DATA_TYPE_DWORD: - /* ld_value_dword &id */ - // finsh_code_byte(FINSH_OP_LD_VALUE_DWORD); - // finsh_code_dword((long)&(var->value.long_value)); - - /* ld_dword &id */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword((long)&(var->value.long_value)); - - /* ld_value_dword &id */ - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD); - finsh_code_dword((long)&(var->value.long_value)); - - /* ld_dword 1 */ - finsh_code_byte(FINSH_OP_LD_DWORD); - finsh_code_dword(1); - - /* add_byte */ - finsh_code_byte(FINSH_OP_SUB_DWORD); - /* get byte */ - finsh_code_byte(FINSH_OP_ST_DWORD); - - /* pop */ - finsh_code_byte(FINSH_OP_POP); - break; - } - } - break; - - case FINSH_NODE_SYS_NULL: - finsh_code_dword(0); - break; - - case FINSH_NODE_SYS_GETVALUE: - if (node->idtype & FINSH_IDTYPE_ADDRESS) - { - /* nothing will be generated */ - } - else - { - switch (node->data_type) - { - case FINSH_DATA_TYPE_BYTE: - finsh_code_byte(FINSH_OP_LD_VALUE_BYTE_STACK); - break; - case FINSH_DATA_TYPE_WORD: - finsh_code_byte(FINSH_OP_LD_VALUE_WORD_STACK); - break; - case FINSH_DATA_TYPE_DWORD: - finsh_code_byte(FINSH_OP_LD_VALUE_DWORD_STACK); - break; - default: - break; - } - } - break; - - case FINSH_NODE_SYS_GETADDR: - /* nothing will be generated */ - break; - - default: - finsh_error_set(FINSH_ERROR_UNKNOWN_NODE); - break; - } - - /* compile sibling node */ - if (finsh_node_sibling(node) != NULL) - finsh_compile(finsh_node_sibling(node)); - } - - return 0; -} - -static int finsh_type_check(struct finsh_node* node, uint8_t is_addr) -{ - if (node != NULL) - { - /* address & value */ - if (node->node_type == FINSH_NODE_SYS_ASSIGN || - node->node_type == FINSH_NODE_SYS_PREINC || - node->node_type == FINSH_NODE_SYS_PREDEC || - node->node_type == FINSH_NODE_SYS_GETADDR) - { - /* address */ - finsh_type_check(finsh_node_child(node), FINSH_IDTYPE_ADDRESS); - } - else if (node->node_type == FINSH_NODE_SYS_GETVALUE && is_addr) - { - /* change the attribute of getvalue in left expr */ - finsh_type_check(finsh_node_child(node), 0); - } - else - { - /* transfer 'av' to child node */ - finsh_type_check(finsh_node_child(node), is_addr); - } - - /* always does not load address in sibling */ - finsh_type_check(finsh_node_sibling(node), FINSH_NODE_VALUE); - - /** set attribute of current node */ - - /* make sure the current node is address or value */ - if (node->idtype != FINSH_IDTYPE_SYSCALL) node->idtype |= is_addr; - - if (finsh_node_child(node) != NULL) - { - node->data_type = finsh_node_child(node)->data_type; - return 0; - } - - if (node->node_type == FINSH_NODE_ID) - { - if (node->idtype & FINSH_IDTYPE_VAR) - { - struct finsh_var* var; - - var = node->id.var; - if (var != NULL) - { - switch (var->type) - { - case finsh_type_void: - node->data_type = FINSH_DATA_TYPE_VOID; - break; - - case finsh_type_char: - case finsh_type_uchar: - node->data_type = FINSH_DATA_TYPE_BYTE; - break; - - case finsh_type_short: - case finsh_type_ushort: - node->data_type = FINSH_DATA_TYPE_WORD; - break; - - case finsh_type_int: - case finsh_type_uint: - case finsh_type_long: - case finsh_type_ulong: - node->data_type = FINSH_DATA_TYPE_DWORD; - break; - - case finsh_type_charp: - case finsh_type_voidp: - case finsh_type_shortp: - case finsh_type_intp: - case finsh_type_longp: - node->data_type = FINSH_DATA_TYPE_DWORD; - break; - - default: - finsh_error_set(FINSH_ERROR_UNKNOWN_TYPE); - break; - } - } - } - else if (node->idtype & FINSH_IDTYPE_SYSVAR) - { - struct finsh_sysvar *sysvar; - - sysvar = node->id.sysvar; - if (sysvar != NULL) - { - switch (sysvar->type) - { - case finsh_type_void: - node->data_type = FINSH_DATA_TYPE_VOID; - break; - - case finsh_type_char: - case finsh_type_uchar: - node->data_type = FINSH_DATA_TYPE_BYTE; - break; - - case finsh_type_short: - case finsh_type_ushort: - node->data_type = FINSH_DATA_TYPE_WORD; - break; - - case finsh_type_int: - case finsh_type_uint: - case finsh_type_long: - case finsh_type_ulong: - node->data_type = FINSH_DATA_TYPE_DWORD; - break; - - case finsh_type_charp: - case finsh_type_voidp: - case finsh_type_shortp: - case finsh_type_intp: - case finsh_type_longp: - node->data_type = FINSH_DATA_TYPE_DWORD; - break; - - default: - finsh_error_set(FINSH_ERROR_UNKNOWN_TYPE); - break; - } - } - } - } - else if (node->node_type == FINSH_NODE_VALUE_CHAR) - { - node->data_type = FINSH_DATA_TYPE_BYTE; - } - else if (node->node_type == FINSH_NODE_VALUE_INT || - node->node_type == FINSH_NODE_VALUE_LONG || - node->node_type == FINSH_NODE_VALUE_STRING || - node->node_type == FINSH_NODE_VALUE_NULL) - { - node->data_type = FINSH_DATA_TYPE_DWORD; - } - } - return 0; -} - -int finsh_compiler_run(struct finsh_node* node) -{ - struct finsh_node* sibling; - - /* type check */ - finsh_type_check(node, FINSH_NODE_VALUE); - - /* clean text segment and vm stack */ - memset(&text_segment[0], 0, sizeof(text_segment)); - memset(&finsh_vm_stack[0], 0, sizeof(finsh_vm_stack)); - - /* reset compile stack pointer and pc */ - finsh_compile_sp = &finsh_vm_stack[0]; - finsh_compile_pc = &text_segment[0]; - - /* compile node */ - sibling = node; - while (sibling != NULL) - { - struct finsh_node* current_node; - current_node = sibling; - - /* get sibling node */ - sibling = current_node->sibling; - - /* clean sibling node */ - current_node->sibling = NULL; - finsh_compile(current_node); - - /* pop current value */ - if (sibling != NULL) finsh_code_byte(FINSH_OP_POP); - } - - return 0; -} diff --git a/components/finsh/finsh_error.c b/components/finsh/finsh_error.c deleted file mode 100644 index bdd0108f98264f84e45aab2475f0a36e6a3e9c5f..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_error.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#include "finsh_error.h" - -uint8_t global_errno; - -static const char * finsh_error_string_table[] = -{ - "No error", - "Invalid token", - "Expect a type", - "Unknown type", - "Variable exist", - "Expect a operater", - "Memory full", - "Unknown operator", - "Unknown node", - "Expect a character", - "Unexpect end", - "Unknown token", - "Float not supported", - "Unknown symbol", - "Null node" -}; - -int finsh_error_init() -{ - global_errno = FINSH_ERROR_OK; - - return 0; -} - -int finsh_error_set(uint8_t type) -{ - global_errno = type; - - return 0; -} - -uint8_t finsh_errno() -{ - return global_errno; -} - -const char* finsh_error_string(uint8_t type) -{ - return finsh_error_string_table[type]; -} diff --git a/components/finsh/finsh_heap.c b/components/finsh/finsh_heap.c deleted file mode 100644 index 0d185db47469bd700030691178d708559d5e537a..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_heap.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#include - -#include "finsh_var.h" - -ALIGN(RT_ALIGN_SIZE) -uint8_t finsh_heap[FINSH_HEAP_MAX]; -struct finsh_block_header -{ - uint32_t length; - struct finsh_block_header* next; -}; -#define BLOCK_HEADER(x) (struct finsh_block_header*)(x) -#define finsh_block_get_header(data) (struct finsh_block_header*)((uint8_t*)data - sizeof(struct finsh_block_header)) -#define finsh_block_get_data(header) (uint8_t*)((struct finsh_block_header*)header + 1) -#define HEAP_ALIGN_SIZE(size) (((size) + HEAP_ALIGNMENT - 1) & ~(HEAP_ALIGNMENT-1)) - -static struct finsh_block_header* free_list; -static struct finsh_block_header* allocate_list; - -static void finsh_heap_gc(void); - -static void finsh_block_insert(struct finsh_block_header** list, struct finsh_block_header* header); -static void finsh_block_remove(struct finsh_block_header** list, struct finsh_block_header* header); -static void finsh_block_split(struct finsh_block_header* header, size_t size); -static void finsh_block_merge(struct finsh_block_header** list, struct finsh_block_header* header); - -int finsh_heap_init(void) -{ - /* clear heap to zero */ - memset(&finsh_heap[0], 0, sizeof(finsh_heap)); - - /* init free and alloc list */ - free_list = BLOCK_HEADER(&finsh_heap[0]); - free_list->length = FINSH_HEAP_MAX - sizeof(struct finsh_block_header); - free_list->next = NULL; - - allocate_list = NULL; - - return 0; -} - -/** - * allocate a block from heap - */ -void* finsh_heap_allocate(size_t size) -{ - struct finsh_block_header* header; - - size = HEAP_ALIGN_SIZE(size); - - /* find the first fit block */ - for (header = free_list; - ((header != NULL) && (header->length <= size + sizeof(struct finsh_block_header))); - header = header->next) ; - - if (header == NULL) - { - finsh_heap_gc(); - - /* find the first fit block */ - for (header = free_list; - ((header != NULL) && (header->length < size + sizeof(struct finsh_block_header))); - header = header->next) ; - - /* there is no memory */ - if (header == NULL) return NULL; - } - - /* split block */ - finsh_block_split(header, size); - - /* remove from free list */ - finsh_block_remove(&free_list, header); - header->next = NULL; - - /* insert to allocate list */ - finsh_block_insert(&allocate_list, header); - - memset(finsh_block_get_data(header), 0, size); - - return finsh_block_get_data(header); -} - -/** - * release the allocated block - */ -void finsh_heap_free(void*ptr) -{ - struct finsh_block_header* header; - - /* get block header */ - header = finsh_block_get_header(ptr); - - /* remove from allocate list */ - finsh_block_remove(&allocate_list, header); - - /* insert to free list */ - finsh_block_insert(&free_list, header); - finsh_block_merge(&free_list, header); -} - -/** - * garbage collector - */ -static void finsh_heap_gc(void) -{ - int i; - struct finsh_block_header *header, *temp; - - temp = NULL; - - /* find the first fit block */ - for (header = allocate_list; header != NULL; ) - { - for (i = 0; i < FINSH_VARIABLE_MAX; i ++) - { - if (global_variable[i].type != finsh_type_unknown) - { - if (global_variable[i].value.ptr == finsh_block_get_data(header)) - break; - } - } - - temp = header; - header = header->next; - - /* this block is an unused block, release it */ - if (i == FINSH_VARIABLE_MAX) - { - finsh_heap_free(finsh_block_get_data(temp)); - } - } -} - -/** - * insert a block to list - */ -void finsh_block_insert(struct finsh_block_header** list, struct finsh_block_header* header) -{ - struct finsh_block_header* node; - - if (*list == NULL) - { - *list = header; - return; - } - - /* find out insert point */ - node = *list; - - if (node > header) - { - /* insert node in the header of list */ - header->next = node; - *list = header; - - return; - } - else - { - for (node = *list; node; node = node->next) - { - if (node->next > header) break; - - if (node->next == NULL) break; - } - } - - /* insert node */ - if (node->next != NULL) header->next = node->next; - node->next = header; -} - -/** - * remove block from list - */ -void finsh_block_remove(struct finsh_block_header** list, struct finsh_block_header* header) -{ - struct finsh_block_header* node; - - node = *list; - if (node == header) - { - /* remove list header */ - *list = header->next; - header->next = NULL; - - return; - } - - for (node = *list; node != NULL; node = node->next) - { - if (node->next == header) - { - node->next = header->next; - break; - } - } -} - -/** - * split block - */ -void finsh_block_split(struct finsh_block_header* header, size_t size) -{ - struct finsh_block_header* next; - - /* - * split header into two node: - * header->next->... - */ - next = BLOCK_HEADER((uint8_t*)header + sizeof(struct finsh_block_header) + size); - next->length = header->length - sizeof(struct finsh_block_header) - size; - header->length = size; - next->next = header->next; - - header->next = next; -} - -void finsh_block_merge(struct finsh_block_header** list, struct finsh_block_header* header) -{ - struct finsh_block_header* prev_node; - struct finsh_block_header* next_node; - - next_node = header->next; - - if (*list == header) prev_node = NULL; - else - { - /* find out the previous header */ - for (prev_node = *list; prev_node; prev_node =prev_node->next) - { - if (prev_node->next == header) - break; - } - } - - /* try merge node */ - - /* merge to previous node */ - if (prev_node != NULL && - ((uint8_t*)prev_node + prev_node->length + sizeof(struct finsh_block_header) - == (uint8_t*)header)) - { - /* is it close to next node? */ - if ((next_node != NULL) && - ((uint8_t*)header + header->length + sizeof(struct finsh_block_header) - == (uint8_t*)next_node)) - { - /* merge three node */ - prev_node->length += header->length + next_node->length + - 2 * sizeof(struct finsh_block_header); - - prev_node->next = next_node->next; - } - else - { - prev_node->length += header->length + sizeof(struct finsh_block_header); - prev_node->next = header->next; - } - } - else /* merge to last node */ - if ( (next_node != NULL) && - ((uint8_t*)header + header->length + sizeof(struct finsh_block_header) - == (uint8_t*)next_node)) - { - header->length += next_node->length + sizeof(struct finsh_block_header); - header->next = next_node->next; - } -} diff --git a/components/finsh/finsh_init.c b/components/finsh/finsh_init.c deleted file mode 100644 index 72f5aa5e9ad5bb5f082f4f86e473de7f0b541c7f..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_init.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#include - -#include "finsh_node.h" -#include "finsh_vm.h" -#include "finsh_parser.h" -#include "finsh_var.h" -#include "finsh_error.h" -#include "finsh_heap.h" - -int finsh_init(struct finsh_parser* parser) -{ - finsh_parser_init(parser); - - /* finsh init */ - finsh_node_init(); - finsh_var_init(); - finsh_error_init(); - finsh_heap_init(); - - return 0; -} - -long finsh_stack_bottom() -{ - return finsh_vm_stack[0].long_value; -} - -int finsh_flush(struct finsh_parser* parser) -{ - finsh_parser_init(parser); - - /* finsh init */ - finsh_node_init(); - finsh_error_init(); - - return 0; -} - -int finsh_reset(struct finsh_parser* parser) -{ - /* finsh init */ - finsh_node_init(); - finsh_var_init(); - finsh_error_init(); - finsh_heap_init(); - - return 0; -} diff --git a/components/finsh/finsh_node.c b/components/finsh/finsh_node.c deleted file mode 100644 index 0de82c189d4cdeebe0118f6921229e2a227e5bb7..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_node.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#include - -#include "finsh_node.h" -#include "finsh_error.h" -#include "finsh_var.h" -#include "finsh_heap.h" - -struct finsh_node global_node_table[FINSH_NODE_MAX]; - -int finsh_node_init() -{ - memset(global_node_table, 0, sizeof(global_node_table)); - - return 0; -} - -struct finsh_node* finsh_node_allocate(uint8_t type) -{ - int i; - - /* find an empty entry */ - for (i = 0; i < FINSH_NODE_MAX; i ++) - { - if (global_node_table[i].node_type == FINSH_NODE_UNKNOWN) break; - } - - if (i == FINSH_NODE_MAX) return NULL; - - /* fill type field */ - global_node_table[i].node_type = type; - - /* return this allocated node */ - return &global_node_table[i]; -} - -struct finsh_node* finsh_node_new_id(char* id) -{ - struct finsh_node* node; - void* symbol; - unsigned char type; - - symbol = NULL; - type = 0; - node = NULL; - - /* lookup variable firstly */ - symbol = (void*)finsh_var_lookup(id); - if (symbol == NULL) - { - /* then lookup system variable */ - symbol = (void*)finsh_sysvar_lookup(id); - if (symbol == NULL) - { - /* then lookup system call */ - symbol = (void*)finsh_syscall_lookup(id); - if (symbol != NULL) type = FINSH_IDTYPE_SYSCALL; - } - else type = FINSH_IDTYPE_SYSVAR; - } - else type = FINSH_IDTYPE_VAR; - - if (symbol != NULL) - { - /* allocate a new node */ - node = finsh_node_allocate(FINSH_NODE_ID); - - /* allocate node error */ - if (node == NULL) - { - finsh_error_set(FINSH_ERROR_MEMORY_FULL); - return NULL; - } - - /* fill node value according type */ - switch (type) - { - case FINSH_IDTYPE_VAR: - node->id.var = (struct finsh_var*)symbol; - break; - - case FINSH_IDTYPE_SYSVAR: - node->id.sysvar = (struct finsh_sysvar*)symbol; - break; - - case FINSH_IDTYPE_SYSCALL: - node->id.syscall = (struct finsh_syscall*)symbol; - break; - } - /* fill identifier type */ - node->idtype = type; - } - else finsh_error_set(FINSH_ERROR_UNKNOWN_SYMBOL); - - return node; -} - -struct finsh_node* finsh_node_new_char(char c) -{ - struct finsh_node* node; - - node = finsh_node_allocate(FINSH_NODE_VALUE_CHAR); - if (node == NULL) - { - finsh_error_set(FINSH_ERROR_MEMORY_FULL); - return NULL; - } - - node->value.char_value = c; - return node; -} - -struct finsh_node* finsh_node_new_int(int i) -{ - struct finsh_node* node; - - node = finsh_node_allocate(FINSH_NODE_VALUE_INT); - if (node == NULL) - { - finsh_error_set(FINSH_ERROR_MEMORY_FULL); - return NULL; - } - - node->value.int_value = i; - return node; -} - -struct finsh_node* finsh_node_new_long(long l) -{ - struct finsh_node* node; - - node = finsh_node_allocate(FINSH_NODE_VALUE_LONG); - if (node == NULL) - { - finsh_error_set(FINSH_ERROR_MEMORY_FULL); - return NULL; - } - - node->value.long_value = l; - return node; -} - -struct finsh_node* finsh_node_new_string(char* s) -{ - struct finsh_node* node; - - node = finsh_node_allocate(FINSH_NODE_VALUE_STRING); - if (node == NULL) - { - finsh_error_set(FINSH_ERROR_MEMORY_FULL); - return NULL; - } - - /* make string */ - node->value.ptr = finsh_heap_allocate(strlen(s) + 1); - strncpy(node->value.ptr, s, strlen(s)); - ((uint8_t*)node->value.ptr)[strlen(s)] = '\0'; - - return node; -} - -struct finsh_node* finsh_node_new_ptr(void* ptr) -{ - struct finsh_node* node; - - node = finsh_node_allocate(FINSH_NODE_VALUE_NULL); - if (node == NULL) - { - finsh_error_set(FINSH_ERROR_MEMORY_FULL); - return NULL; - } - - node->value.ptr = ptr; - return node; -} diff --git a/components/finsh/finsh_node.h b/components/finsh/finsh_node.h deleted file mode 100644 index c7ce099636d316cc551f3ce2d01b8cb20a485588..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_node.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#ifndef __FINSH_NODE_H__ -#define __FINSH_NODE_H__ - -#include - -#define FINSH_NODE_UNKNOWN 0 -#define FINSH_NODE_ID 1 - -#define FINSH_NODE_VALUE_CHAR 2 -#define FINSH_NODE_VALUE_INT 3 -#define FINSH_NODE_VALUE_LONG 4 -#define FINSH_NODE_VALUE_STRING 5 -#define FINSH_NODE_VALUE_NULL 6 - -#define FINSH_NODE_SYS_ADD 7 -#define FINSH_NODE_SYS_SUB 8 -#define FINSH_NODE_SYS_MUL 9 -#define FINSH_NODE_SYS_DIV 10 -#define FINSH_NODE_SYS_MOD 11 -#define FINSH_NODE_SYS_AND 12 -#define FINSH_NODE_SYS_OR 13 -#define FINSH_NODE_SYS_XOR 14 -#define FINSH_NODE_SYS_BITWISE 15 -#define FINSH_NODE_SYS_SHL 16 -#define FINSH_NODE_SYS_SHR 17 -#define FINSH_NODE_SYS_FUNC 18 -#define FINSH_NODE_SYS_ASSIGN 19 -#define FINSH_NODE_SYS_CAST 20 -#define FINSH_NODE_SYS_PREINC 21 -#define FINSH_NODE_SYS_PREDEC 22 -#define FINSH_NODE_SYS_INC 23 -#define FINSH_NODE_SYS_DEC 24 -#define FINSH_NODE_SYS_GETVALUE 25 -#define FINSH_NODE_SYS_GETADDR 26 -#define FINSH_NODE_SYS_NULL 27 - -#define FINSH_DATA_TYPE_VOID 0x00 -#define FINSH_DATA_TYPE_BYTE 0x01 -#define FINSH_DATA_TYPE_WORD 0x02 -#define FINSH_DATA_TYPE_DWORD 0x03 -#define FINSH_DATA_TYPE_PTR 0x10 - -#define FINSH_NODE_VALUE 0 -#define FINSH_NODE_ADDRESS 1 -#define FINSH_NODE_FUNCTION 2 - -int finsh_node_init(void); - -struct finsh_node* finsh_node_allocate(uint8_t type); -struct finsh_node* finsh_node_new_id(char* id); -struct finsh_node* finsh_node_new_char(char c); -struct finsh_node* finsh_node_new_int(int i); -struct finsh_node* finsh_node_new_long(long l); -struct finsh_node* finsh_node_new_string(char* s); -struct finsh_node* finsh_node_new_ptr(void* ptr); - -#define finsh_node_sibling(node) ((node)->sibling) -#define finsh_node_child(node) ((node)->child) - -#endif diff --git a/components/finsh/finsh_ops.c b/components/finsh/finsh_ops.c deleted file mode 100644 index 2eafb50c699cd72deab192fbda180c193e45427c..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_ops.c +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#include "finsh_ops.h" -#include "finsh_vm.h" - -#define OP_BIN_BYTE(x) do {\ - (finsh_sp - 2)->char_value = (finsh_sp - 2)->char_value x (finsh_sp - 1)->char_value; \ - finsh_sp--; \ - }while (0) - -#define OP_BIN_WORD(x) do {\ - (finsh_sp - 2)->short_value = (finsh_sp - 2)->short_value x (finsh_sp - 1)->short_value; \ - finsh_sp--; \ - }while (0) - -#define OP_BIN_DWORD(x) do {\ - (finsh_sp - 2)->long_value = (finsh_sp - 2)->long_value x (finsh_sp - 1)->long_value; \ - finsh_sp--; \ - }while (0) - -/* --- noop --- */ -void OP_no_op() -{ - /* none */ - return ; -} - -/* --- add --- */ -void OP_add_byte() -{ - OP_BIN_BYTE(+); - - return ; -} - -void OP_add_word() -{ - OP_BIN_WORD(+); - - return ; -} - -void OP_add_dword() -{ - OP_BIN_DWORD(+); - - return ; -} - -/* --- sub --- */ -void OP_sub_byte() -{ - OP_BIN_BYTE(-); - - return ; -} - -void OP_sub_word() -{ - OP_BIN_WORD(-); - - return ; -} - -void OP_sub_dword() -{ - OP_BIN_DWORD(-); - - return ; -} - -/* --- div --- */ -void OP_div_byte() -{ - OP_BIN_BYTE(/); - - return ; -} - -void OP_div_word() -{ - OP_BIN_WORD(/); - - return ; -} - -void OP_div_dword() -{ - OP_BIN_DWORD(/); - - return ; -} - -/* --- mod --- */ -void OP_mod_byte() -{ - OP_BIN_BYTE(%); - - return ; -} - -void OP_mod_word() -{ - OP_BIN_WORD(%); - - return ; -} - -void OP_mod_dword() -{ - OP_BIN_DWORD(%); - - return ; -} - -/* --- mul --- */ -void OP_mul_byte() -{ - OP_BIN_BYTE(*); - - return ; -} - -void OP_mul_word() -{ - OP_BIN_WORD(*); - - return ; -} - -void OP_mul_dword() -{ - OP_BIN_DWORD(*); - - return ; -} - -/* --- and --- */ -void OP_and_byte() -{ - OP_BIN_BYTE(&); - - return ; -} - -void OP_and_word() -{ - OP_BIN_WORD(&); - - return ; -} - -void OP_and_dword() -{ - OP_BIN_DWORD(&); - - return ; -} - -/* --- or --- */ -void OP_or_byte() -{ - OP_BIN_BYTE(|); - - return ; -} - -void OP_or_word() -{ - OP_BIN_WORD(|); - - return ; -} - -void OP_or_dword() -{ - OP_BIN_DWORD(|); - - return ; -} - -/* --- xor --- */ -void OP_xor_byte() -{ - OP_BIN_BYTE(^); - - return ; -} - -void OP_xor_word() -{ - OP_BIN_WORD(^); - - return ; -} - -void OP_xor_dword() -{ - OP_BIN_DWORD(^); - - return ; -} - -/* --- bw --- */ -void OP_bw_byte() -{ - (finsh_sp - 1)->char_value = ~ ((finsh_sp - 1)->char_value); - - return ; -} - -void OP_bw_word() -{ - (finsh_sp - 1)->short_value = ~ ((finsh_sp - 1)->short_value); - - return ; -} - -void OP_bw_dword() -{ - (finsh_sp - 1)->long_value = ~ ((finsh_sp - 1)->long_value); - - return ; -} - -/* --- shl --- */ -void OP_shl_byte() -{ - OP_BIN_BYTE(<<); - - return ; -} - -void OP_shl_word() -{ - OP_BIN_WORD(<<); - - return ; -} - -void OP_shl_dword() -{ - OP_BIN_DWORD(<<); - - return ; -} - -/* --- shr --- */ -void OP_shr_byte() -{ - OP_BIN_BYTE(>>); - - return ; -} - -void OP_shr_word() -{ - OP_BIN_WORD(>>); - - return ; -} - -void OP_shr_dword() -{ - OP_BIN_DWORD(>>); - - return ; -} - -/* --- ld --- */ -void OP_ld_byte() -{ - finsh_sp->char_value = *finsh_pc; - - finsh_sp++; - finsh_pc++; - - return ; -} - -void OP_ld_word() -{ - finsh_sp->short_value = FINSH_GET16(finsh_pc); - - finsh_sp ++; - finsh_pc += 2; - - return ; -} - -void OP_ld_dword() -{ - finsh_sp->long_value = FINSH_GET32(finsh_pc); - - finsh_sp ++; - finsh_pc += 4; - - return ; -} - -void OP_ld_value_byte() -{ - char* c; - - c = (char*) (FINSH_GET32(finsh_pc)); - - finsh_sp->char_value = *c; - - finsh_sp ++; - finsh_pc += 4; - - return; -} - -void OP_ld_value_byte_stack() -{ - char* c; - - c = (char *)(finsh_sp - 1)->long_value; - (finsh_sp - 1)->char_value = *c; - - return; -} - -void OP_ld_value_word() -{ - short* s; - - s = (short*) (FINSH_GET32(finsh_pc)); - - finsh_sp->short_value = *s; - - finsh_sp ++; - finsh_pc += 4; - - return; -} - -void OP_ld_value_word_stack() -{ - short* s; - - s = (short *)(finsh_sp - 1)->long_value; - (finsh_sp - 1)->short_value = *s; - - return; -} - -void OP_ld_value_dword() -{ - long* l; - - l = (long*) (FINSH_GET32(finsh_pc)); - - finsh_sp->long_value = *l; - - finsh_sp ++; - finsh_pc += 4; - - return; -} - -void OP_ld_value_dword_stack() -{ - long* l; - - l = (long *)(finsh_sp - 1)->long_value; - (finsh_sp - 1)->long_value = *l; - - return; -} - -/* --- st --- */ -/* - * 2006-4-16 bernard - * fixed the sp move bug - */ -void OP_st_byte() -{ - *(char*)((finsh_sp - 2)->long_value) = (finsh_sp - 1)->char_value; - finsh_sp --; - - return ; -} - -/* - * 2006-4-16 bernard - * fixed the sp move bug - */ -void OP_st_word() -{ - *(short*)((finsh_sp - 2)->long_value) = (finsh_sp - 1)->short_value; - finsh_sp --; - - return ; -} - -/* - * 2006-4-16 bernard - * fixed the sp move bug - */ -void OP_st_dword() -{ - *(long*)((finsh_sp - 2)->long_value) = (finsh_sp - 1)->long_value; - finsh_sp --; - - return ; -} - -/* --- pop --- */ -void OP_pop() -{ - finsh_sp --; - return ; -} - -/* --- call --- */ -void OP_call() -{ - /* the max number of arg*/ - unsigned long parameterv[16]; - unsigned int parameters, i; - - typedef unsigned long var_t; - typedef var_t (*op_func)(); - op_func f; - var_t r; - - parameters = *finsh_pc ++; - - i = 0; finsh_sp --; - while (i < parameters) - { - parameterv[parameters - 1 - i] = finsh_sp->long_value; - finsh_sp --; - i++; - } - - f = (op_func)(finsh_sp->long_value); - switch (parameters) - { - case 0: - r = f(0); - break; - - case 1: - r = f(parameterv[0]); - break; - - case 2: - r = f(parameterv[0], parameterv[1]); - break; - - case 3: - r = f(parameterv[0], parameterv[1], parameterv[2]); - break; - - case 4: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3]); - break; - - case 5: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4]); - break; - - case 6: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5]); - break; - - case 7: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6]); - break; - - case 8: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6], parameterv[7]); - break; - - case 9: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6], parameterv[7], - parameterv[8]); - break; - - case 10: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6], parameterv[7], - parameterv[8], parameterv[9]); - break; - - case 11: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6], parameterv[7], - parameterv[8], parameterv[9], parameterv[10]); - break; - - case 12: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6], parameterv[7], - parameterv[8], parameterv[9], parameterv[10], parameterv[11]); - break; - - case 13: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6], parameterv[7], - parameterv[8], parameterv[9], parameterv[10], parameterv[11], - parameterv[12]); - break; - - case 14: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6], parameterv[7], - parameterv[8], parameterv[9], parameterv[10], parameterv[11], - parameterv[12], parameterv[13]); - break; - - case 15: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6], parameterv[7], - parameterv[8], parameterv[9], parameterv[10], parameterv[11], - parameterv[12], parameterv[13], parameterv[14]); - break; - - case 16: - r = f(parameterv[0], parameterv[1], parameterv[2], parameterv[3], - parameterv[4], parameterv[5], parameterv[6], parameterv[7], - parameterv[8], parameterv[9], parameterv[10], parameterv[11], - parameterv[12], parameterv[13], parameterv[14], parameterv[15]); - break; - - default: - r = 0; - break; - } - - finsh_sp->long_value = r; - finsh_sp ++; - - return ; -} - -const op_func op_table[] = -{ - /* 00 */ OP_no_op, - /* 01 */ OP_add_byte, - /* 02 */ OP_add_word, - /* 03 */ OP_add_dword, - /* 04 */ OP_sub_byte, - /* 05 */ OP_sub_word, - /* 06 */ OP_sub_dword, - /* 07 */ OP_div_byte, - /* 08 */ OP_div_word, - /* 09 */ OP_div_dword, - /* 10 */ OP_mod_byte, - /* 11 */ OP_mod_word, - /* 12 */ OP_mod_dword, - /* 13 */ OP_mul_byte, - /* 14 */ OP_mul_word, - /* 15 */ OP_mul_dword, - /* 16 */ OP_and_byte, - /* 17 */ OP_and_word, - /* 18 */ OP_and_dword, - /* 19 */ OP_or_byte, - /* 20 */ OP_or_word, - /* 21 */ OP_or_dword, - /* 22 */ OP_xor_byte, - /* 23 */ OP_xor_word, - /* 24 */ OP_xor_dword, - /* 25 */ OP_bw_byte, - /* 26 */ OP_bw_word, - /* 27 */ OP_bw_dword, - /* 28 */ OP_shl_byte, - /* 29 */ OP_shl_word, - /* 30 */ OP_shl_dword, - /* 31 */ OP_shr_byte, - /* 32 */ OP_shr_word, - /* 33 */ OP_shr_dword, - /* 34 */ OP_ld_byte, - /* 35 */ OP_ld_word, - /* 36 */ OP_ld_dword, - /* 37 */ OP_ld_value_byte, - /* 38 */ OP_ld_value_word, - /* 39 */ OP_ld_value_dword, - /* 40 */ OP_st_byte, - /* 41 */ OP_st_word, - /* 42 */ OP_st_dword, - /* 43 */ OP_pop, - /* 44 */ OP_call, - /* 45 */ OP_ld_value_byte_stack, - /* 46 */ OP_ld_value_word_stack, - /* 47 */ OP_ld_value_dword_stack, - NULL -}; diff --git a/components/finsh/finsh_ops.h b/components/finsh/finsh_ops.h deleted file mode 100644 index 95a8b001fbf2269defa427689069cd66b3cddb3b..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_ops.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#ifndef __FINSH_OP_H__ -#define __FINSH_OP_H__ - -#include "finsh_vm.h" - -/* - * FinC VM specification - * Memory - * .VAR - * - * .STACK - * - * .HEAP - * - * .TEXT - * OP [op1] - */ - -#define FINSH_OP_NOOP 0x00 - -/* add @ r1 = r2 + r3 */ -#define FINSH_OP_ADD_BYTE 0x01 -#define FINSH_OP_ADD_WORD 0x02 -#define FINSH_OP_ADD_DWORD 0x03 - -/* sub @ r1 = r2 - r3 */ -#define FINSH_OP_SUB_BYTE 0x04 -#define FINSH_OP_SUB_WORD 0x05 -#define FINSH_OP_SUB_DWORD 0x06 - -/* div @ r1 = r2 / r3 */ -#define FINSH_OP_DIV_BYTE 0x07 -#define FINSH_OP_DIV_WORD 0x08 -#define FINSH_OP_DIV_DWORD 0x09 - -/* mod @ r1 = r2 % r3 */ -#define FINSH_OP_MOD_BYTE 0x0A -#define FINSH_OP_MOD_WORD 0x0B -#define FINSH_OP_MOD_DWORD 0x0C - -/* mul @ r1 = r2 * r3 */ -#define FINSH_OP_MUL_BYTE 0x0D -#define FINSH_OP_MUL_WORD 0x0E -#define FINSH_OP_MUL_DWORD 0x0F - -/* and @ r1 = r2 & r3 */ -#define FINSH_OP_AND_BYTE 0x10 -#define FINSH_OP_AND_WORD 0x11 -#define FINSH_OP_AND_DWORD 0x12 - -/* or @ r1 = r2 | r3 */ -#define FINSH_OP_OR_BYTE 0x13 -#define FINSH_OP_OR_WORD 0x14 -#define FINSH_OP_OR_DWORD 0x15 - -/* xor @ r1 = r2 ^ r3 */ -#define FINSH_OP_XOR_BYTE 0x16 -#define FINSH_OP_XOR_WORD 0x17 -#define FINSH_OP_XOR_DWORD 0x18 - -/* bw @ r1 = ~r2 */ -#define FINSH_OP_BITWISE_BYTE 0x19 -#define FINSH_OP_BITWISE_WORD 0x1A -#define FINSH_OP_BITWISE_DWORD 0x1B - -/* shl @ r1 = r2 << r3 */ -#define FINSH_OP_SHL_BYTE 0x1C -#define FINSH_OP_SHL_WORD 0x1D -#define FINSH_OP_SHL_DWORD 0x1E - -/* shr @ r1 = r2 >> r3 */ -#define FINSH_OP_SHR_BYTE 0x1F -#define FINSH_OP_SHR_WORD 0x20 -#define FINSH_OP_SHR_DWORD 0x21 - -/* ld @ r1 = [r2] */ -#define FINSH_OP_LD_BYTE 0x22 -#define FINSH_OP_LD_WORD 0x23 -#define FINSH_OP_LD_DWORD 0x24 - -#define FINSH_OP_LD_VALUE_BYTE 0x25 -#define FINSH_OP_LD_VALUE_WORD 0x26 -#define FINSH_OP_LD_VALUE_DWORD 0x27 - -/* st @ [r2] = r1 */ -#define FINSH_OP_ST_BYTE 0x28 -#define FINSH_OP_ST_WORD 0x29 -#define FINSH_OP_ST_DWORD 0x2A - -/* pop */ -#define FINSH_OP_POP 0x2B - -/* call r1 @ [r1](stack) */ -#define FINSH_OP_SYSCALL 0x2C - -/* load value from stack */ -#define FINSH_OP_LD_VALUE_BYTE_STACK 0x2D -#define FINSH_OP_LD_VALUE_WORD_STACK 0x2E -#define FINSH_OP_LD_VALUE_DWORD_STACK 0x2F - -/* halt */ -#define FINSH_OP_HALT 0xFF - -typedef void (*op_func)(); -extern const op_func op_table[]; - -#endif diff --git a/components/finsh/finsh_parser.c b/components/finsh/finsh_parser.c deleted file mode 100644 index 0e7617003c379eb3a05dce18a25e35f16f4febd0..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_parser.c +++ /dev/null @@ -1,986 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - * 2013-10-09 Bernard fix the command line too long issue. - */ -#include - -#include "finsh_token.h" -#include "finsh_node.h" -#include "finsh_error.h" -#include "finsh_parser.h" -#include "finsh_var.h" - -/* - * the structure of abstract syntax tree: - * root____________ - * | \ - * child__ sibling__ - * | \ | \ - * child sibling child sibling - * ... - */ -static enum finsh_type proc_type(struct finsh_parser* self); -static int proc_identifier(struct finsh_parser* self, char* id); -static struct finsh_node* proc_variable_decl(struct finsh_parser* self); -static struct finsh_node* proc_expr(struct finsh_parser* self); -static struct finsh_node* proc_assign_expr(struct finsh_parser* self); -static struct finsh_node* proc_inclusive_or_expr(struct finsh_parser* self); -static struct finsh_node* proc_exclusive_or_expr(struct finsh_parser* self); -static struct finsh_node* proc_and_expr(struct finsh_parser* self); -static struct finsh_node* proc_shift_expr(struct finsh_parser* self); -static struct finsh_node* proc_additive_expr(struct finsh_parser* self); -static struct finsh_node* proc_multiplicative_expr(struct finsh_parser* self); -static struct finsh_node* proc_cast_expr(struct finsh_parser* self); -static struct finsh_node* proc_unary_expr(struct finsh_parser* self); -static struct finsh_node* proc_postfix_expr(struct finsh_parser* self); -static struct finsh_node* proc_primary_expr(struct finsh_parser* self); -static struct finsh_node* proc_param_list(struct finsh_parser* self); -static struct finsh_node* proc_expr_statement(struct finsh_parser* self); -static struct finsh_node* make_sys_node(uint8_t type, struct finsh_node* node1, - struct finsh_node* node2); - -/* check token */ -#define check_token(token, lex, type) if ( (token) != (type) ) \ - { \ - finsh_error_set(FINSH_ERROR_INVALID_TOKEN); \ - finsh_token_replay(lex); \ - } - -/* is the token a data type? */ -#define is_base_type(token) ((token) == finsh_token_type_void \ - || (token) == finsh_token_type_char \ - || (token) == finsh_token_type_short \ - || (token) == finsh_token_type_int \ - || (token) == finsh_token_type_long) - -/* get the next token */ -#define next_token(token, lex) (token) = finsh_token_token(lex) - -/* match a specified token */ -#define match_token(token, lex, type) next_token(token, lex); \ - check_token(token, lex, type) - -/* -process for function and variable declaration. -decl_variable -> type declaration_list ';' -declarator_list -> declarator_list ',' declarator - | declarator -declarator -> identifier - | identifier ASSIGN expr_assign -*/ -static struct finsh_node* proc_variable_decl(struct finsh_parser* self) -{ - enum finsh_token_type token; - enum finsh_type type; - char id[FINSH_NAME_MAX + 1]; - - struct finsh_node *node; - struct finsh_node *end; - struct finsh_node *assign; - - node = NULL; - end = NULL; - - /* get type */ - type = proc_type(self); - - /*process id.*/ - if (proc_identifier(self, id) == 0) - { - /* if add variable failed */ - if (finsh_var_insert(id, type) < 0) - { - finsh_error_set(FINSH_ERROR_VARIABLE_EXIST); - } - } - - next_token(token, &(self->token)); - switch ( token ) - { - case finsh_token_type_comma:/*',', it's a variable_list declaration.*/ - if (proc_identifier(self, id) == 0) - { - /* if add variable failed */ - if (finsh_var_insert(id, type) < 0) - { - finsh_error_set(FINSH_ERROR_VARIABLE_EXIST); - } - } - - next_token(token, &(self->token)); - if ( token == finsh_token_type_assign ) - { - /* get the right side of assign expression */ - assign = proc_assign_expr(self); - - if (assign != NULL) - { - struct finsh_node* idnode; - - idnode = finsh_node_new_id(id); - end = make_sys_node(FINSH_NODE_SYS_ASSIGN, idnode, assign); - node = end; - - next_token(token, &(self->token)); - } - } - - while ( token == finsh_token_type_comma ) - { - if (proc_identifier(self, id) == 0) - { - /* if add variable failed */ - if (finsh_var_insert(id, type) < 0) - { - finsh_error_set(FINSH_ERROR_VARIABLE_EXIST); - } - } - - next_token(token, &(self->token)); - if ( token == finsh_token_type_assign ) - { - /* get the right side of assign expression */ - assign = proc_assign_expr(self); - - if (assign != NULL) - { - struct finsh_node* idnode; - - idnode = finsh_node_new_id(id); - - /* make assign expression node */ - if (node != NULL) - { - finsh_node_sibling(end) = make_sys_node(FINSH_NODE_SYS_ASSIGN, idnode, assign); - end = finsh_node_sibling(end); - } - else - { - end = make_sys_node(FINSH_NODE_SYS_ASSIGN, idnode, assign); - node = end; - } - - next_token(token, &(self->token)); - } - } - } - - check_token(token, &(self->token), finsh_token_type_semicolon); - return node; - - case finsh_token_type_assign:/*'=', it's a variable with assign declaration.*/ - { - struct finsh_node *idnode; - - assign = proc_assign_expr(self); - if (assign != NULL) - { - idnode = finsh_node_new_id(id); - - /* make assign expression node */ - end = make_sys_node(FINSH_NODE_SYS_ASSIGN, idnode, assign); - node = end; - - next_token(token, &(self->token)); - } - - while ( token == finsh_token_type_comma ) - { - if (proc_identifier(self, id) == 0) - { - /* if add variable failed */ - if (finsh_var_insert(id, type) < 0) - { - finsh_error_set(FINSH_ERROR_VARIABLE_EXIST); - } - } - - next_token(token, &(self->token)); - if (token == finsh_token_type_assign) - { - /* get the right side of assign expression */ - assign = proc_assign_expr(self); - - if (assign != NULL) - { - idnode = finsh_node_new_id(id); - - /* make assign expression node */ - if (node != NULL) - { - finsh_node_sibling(end) = make_sys_node(FINSH_NODE_SYS_ASSIGN, idnode, assign); - end = finsh_node_sibling(end); - } - else - { - end = make_sys_node(FINSH_NODE_SYS_ASSIGN, idnode, assign); - node = end; - } - - next_token(token, &(self->token)); - } - } - } - - check_token(token, &(self->token), finsh_token_type_semicolon); - return node; - } - - case finsh_token_type_semicolon:/*';', it's a variable declaration.*/ - return node; - - default: - finsh_error_set(FINSH_ERROR_EXPECT_TYPE); - - return NULL; - } -} - -/* -type -> type_prefix type_basic | type_basic -type_prefix -> UNSIGNED -type_basic -> VOID - | CHAR - | SHORT - | INT - | STRING -*/ -static enum finsh_type proc_type(struct finsh_parser* self) -{ - enum finsh_type type; - enum finsh_token_type token; - - /* set init type */ - type = finsh_type_unknown; - - next_token(token, &(self->token)); - if ( is_base_type(token) ) /* base_type */ - { - switch (token) - { - case finsh_token_type_void: - type = finsh_type_void; - break; - - case finsh_token_type_char: - type = finsh_type_char; - break; - - case finsh_token_type_short: - type = finsh_type_short; - break; - - case finsh_token_type_int: - type = finsh_type_int; - break; - - case finsh_token_type_long: - type = finsh_type_long; - break; - - default: - goto __return; - } - } - else if ( token == finsh_token_type_unsigned ) /* unsigned base_type */ - { - next_token(token, &(self->token)); - if ( is_base_type(token) ) - { - switch (token) - { - case finsh_token_type_char: - type = finsh_type_uchar; - break; - - case finsh_token_type_short: - type = finsh_type_ushort; - break; - - case finsh_token_type_int: - type = finsh_type_uint; - break; - - case finsh_token_type_long: - type = finsh_type_ulong; - break; - - default: - goto __return; - } - } - else - { - finsh_token_replay(&(self->token)); - finsh_error_set(FINSH_ERROR_EXPECT_TYPE); - } - } - else - { - goto __return; - } - - /* parse for pointer */ - next_token(token, &(self->token)); - if (token == finsh_token_type_mul) - { - switch (type) - { - case finsh_type_void: - type = finsh_type_voidp; - break; - - case finsh_type_char: - case finsh_type_uchar: - type = finsh_type_charp; - break; - - case finsh_type_short: - case finsh_type_ushort: - type = finsh_type_shortp; - break; - - case finsh_type_int: - case finsh_type_uint: - type = finsh_type_intp; - break; - - case finsh_type_long: - case finsh_type_ulong: - type = finsh_type_longp; - break; - - default: - type = finsh_type_voidp; - break; - } - } - else finsh_token_replay(&(self->token)); - - return type; - -__return: - finsh_token_replay(&(self->token)); - finsh_error_set(FINSH_ERROR_UNKNOWN_TYPE); - - return type; -} - -/* -identifier -> IDENTIFIER -*/ -static int proc_identifier(struct finsh_parser* self, char* id) -{ - enum finsh_token_type token; - - match_token(token, &(self->token), finsh_token_type_identifier); - - strncpy(id, (char*)self->token.string, FINSH_NAME_MAX); - - return 0; -} - -/* -statement_expr -> ';' - | expr ';' -*/ -static struct finsh_node* proc_expr_statement(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* expr; - - expr = NULL; - next_token(token, &(self->token)); - if ( token != finsh_token_type_semicolon ) - { - finsh_token_replay(&(self->token)); - expr = proc_expr(self); - - match_token(token, &(self->token), finsh_token_type_semicolon); - } - - return expr; -} - -/* -expr -> expr_assign -*/ -static struct finsh_node* proc_expr(struct finsh_parser* self) -{ - return proc_assign_expr(self); -} - -/* -expr_assign -> expr_inclusive_or - | expr_unary ASSIGN expr_assign -*/ -static struct finsh_node* proc_assign_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* or; - struct finsh_node* assign; - - or = proc_inclusive_or_expr(self); - - next_token(token, &(self->token)); - - if (token == finsh_token_type_assign) - { - assign = proc_assign_expr(self); - - return make_sys_node(FINSH_NODE_SYS_ASSIGN, or, assign); - } - else finsh_token_replay(&(self->token)); - - return or; -} - -/* -expr_inclusive_or -> expr_exclusive_or - | expr_inclusive_or '|' expr_exclusive_or -*/ -static struct finsh_node* proc_inclusive_or_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* xor; - struct finsh_node* xor_new; - - xor = proc_exclusive_or_expr(self); - - next_token(token, &(self->token)); - while ( token == finsh_token_type_or ) - { - xor_new = proc_exclusive_or_expr(self); - - if (xor_new == NULL) finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - else xor = make_sys_node(FINSH_NODE_SYS_OR, xor, xor_new); - - next_token(token, &(self->token)); - } - - finsh_token_replay(&(self->token)); - return xor; -} - -/* -expr_exclusive_or -> expr_and - | expr_exclusive '^' expr_and -*/ -static struct finsh_node* proc_exclusive_or_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* and; - struct finsh_node* and_new; - - and = proc_and_expr(self); - next_token(token, &(self->token)); - while ( token == finsh_token_type_xor ) - { - and_new = proc_and_expr(self); - if (and_new == NULL) finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - else and = make_sys_node(FINSH_NODE_SYS_XOR, and, and_new); - - next_token(token, &(self->token)); - } - - finsh_token_replay(&(self->token)); - return and; -} - -/* -expr_and -> expr_shift - | expr_and '&' expr_shift -*/ -static struct finsh_node* proc_and_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* shift; - struct finsh_node* shift_new; - - shift = proc_shift_expr(self); - - next_token(token, &(self->token)); - while ( token == finsh_token_type_and ) - { - shift_new = proc_shift_expr(self); - - if (shift_new == NULL) finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - else shift = make_sys_node(FINSH_NODE_SYS_AND, shift, shift_new); - - next_token(token, &(self->token)); - } - - finsh_token_replay(&(self->token)); - return shift; -} - -/* -expr_shift -> expr_additive - | expr_shift '<<' expr_additive - | expr_shift '>>' expr_additive -*/ -static struct finsh_node* proc_shift_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* add; - struct finsh_node* add_new; - - add = proc_additive_expr(self); - - next_token(token, &(self->token)); - while ( token == finsh_token_type_shl || token == finsh_token_type_shr) - { - add_new = proc_additive_expr(self); - if (add_new == NULL) finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - else - { - switch (token) - { - case finsh_token_type_shl: - add = make_sys_node(FINSH_NODE_SYS_SHL, add, add_new); - break; - case finsh_token_type_shr: - add = make_sys_node(FINSH_NODE_SYS_SHR, add, add_new); - break; - default: - finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - break; - } - } - next_token(token, &(self->token)); - } - - finsh_token_replay(&(self->token)); - return add; -} - -/* -expr_additive -> expr_multiplicative - | expr_additive SUB expr_multiplicative - | expr_additive ADD expr_multiplicative -*/ -static struct finsh_node* proc_additive_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* mul; - struct finsh_node* mul_new; - - mul = proc_multiplicative_expr(self); - - next_token(token, &(self->token)); - while ( token == finsh_token_type_sub || token == finsh_token_type_add ) - { - mul_new = proc_multiplicative_expr(self); - if (mul_new == NULL) finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - else - { - switch (token) - { - case finsh_token_type_sub: - mul = make_sys_node(FINSH_NODE_SYS_SUB, mul, mul_new); - break; - case finsh_token_type_add: - mul = make_sys_node(FINSH_NODE_SYS_ADD, mul, mul_new); - break; - default: - finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - break; - } - } - next_token(token, &(self->token)); - } - - finsh_token_replay(&(self->token)); - return mul; -} - -/* -expr_multiplicative -> expr_cast - | expr_multiplicative '*' expr_cast - | expr_multiplicative '/' expr_cast - | expr_multiplicative '%' expr_cast -*/ -static struct finsh_node* proc_multiplicative_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* cast; - struct finsh_node* cast_new; - - cast = proc_cast_expr(self); - next_token(token, &(self->token)); - while (token == finsh_token_type_mul || - token == finsh_token_type_div || - token == finsh_token_type_mod ) - { - cast_new = proc_cast_expr(self); - if (cast_new == NULL) finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - else - { - switch (token) - { - case finsh_token_type_mul: - cast = make_sys_node(FINSH_NODE_SYS_MUL, cast, cast_new); - break; - - case finsh_token_type_div: - cast = make_sys_node(FINSH_NODE_SYS_DIV, cast, cast_new); - break; - - case finsh_token_type_mod: - cast = make_sys_node(FINSH_NODE_SYS_MOD, cast, cast_new); - break; - - default: - finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - break; - } - } - next_token(token, &(self->token)); - } - - finsh_token_replay(&(self->token)); - return cast; -} - -/* -20060313, add recast parse -expr_cast -> expr_unary - | '(' type ')' expr_cast -*/ -static struct finsh_node* proc_cast_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - enum finsh_type type; - struct finsh_node* cast; - - next_token(token, &(self->token)); - if (token == finsh_token_type_left_paren) - { - type = proc_type(self); - match_token(token, &(self->token), finsh_token_type_right_paren); - - cast = proc_cast_expr(self); - if (cast != NULL) - { - cast->data_type = type; - return cast; - } - } - - finsh_token_replay(&(self->token)); - return proc_unary_expr(self); -} - -/* -20050921, add '*' and '&' -expr_unary -> expr_postfix - | ADD expr_cast - | INC expr_cast - | SUB expr_cast - | DEC expr_cast - | '~' expr_cast - | '*' expr_cast - | '&' expr_cast -*/ -static struct finsh_node* proc_unary_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node *cast; - - next_token(token, &(self->token)); - switch (token) - { - case finsh_token_type_add: /* + */ - cast = proc_cast_expr(self); - return cast; - - case finsh_token_type_inc: /* ++ */ - cast = proc_cast_expr(self); - return make_sys_node(FINSH_NODE_SYS_PREINC, cast, NULL); - - case finsh_token_type_sub: /* - */ - cast = proc_cast_expr(self); - return make_sys_node(FINSH_NODE_SYS_SUB, finsh_node_new_long(0), cast); - - case finsh_token_type_dec: /* -- */ - cast = proc_cast_expr(self); - return make_sys_node(FINSH_NODE_SYS_PREDEC, cast, NULL); - - case finsh_token_type_bitwise: /* ~ */ - cast = proc_cast_expr(self); - return make_sys_node(FINSH_NODE_SYS_BITWISE, cast, NULL); - - case finsh_token_type_mul: /* * */ - cast = proc_cast_expr(self); - return make_sys_node(FINSH_NODE_SYS_GETVALUE, cast, NULL); - - case finsh_token_type_and: /* & */ - cast = proc_cast_expr(self); - return make_sys_node(FINSH_NODE_SYS_GETADDR, cast, NULL); - - default: - finsh_token_replay(&(self->token)); - return proc_postfix_expr(self); - } -} - -/* -expr_postfix -> expr_primary - | expr_postfix INC - | expr_postfix DEC - | expr_postfix '(' param_list ')' -*/ -static struct finsh_node* proc_postfix_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* postfix; - - postfix = proc_primary_expr(self); - - next_token(token, &(self->token)); - while ( token == finsh_token_type_inc || - token == finsh_token_type_dec || - token == finsh_token_type_left_paren ) - { - switch (token) - { - case finsh_token_type_inc :/* '++' */ - postfix = make_sys_node(FINSH_NODE_SYS_INC, postfix, NULL); - break; - - case finsh_token_type_dec :/* '--' */ - postfix = make_sys_node(FINSH_NODE_SYS_DEC, postfix, NULL); - break; - - case finsh_token_type_left_paren :/* '(' */ - { - struct finsh_node* param_list; - - param_list = NULL; - next_token(token, &(self->token)); - if (token != finsh_token_type_right_paren) - { - finsh_token_replay(&(self->token)); - param_list = proc_param_list(self); - - match_token(token, &(self->token), finsh_token_type_right_paren); - } - - postfix = make_sys_node(FINSH_NODE_SYS_FUNC, postfix, param_list); - } - break; - - default: - break; - } - - next_token(token, &(self->token)); - } - - finsh_token_replay(&(self->token)); - return postfix; -} - -/* -expr_primary -> literal - | '(' expr ')' - | identifier -*/ -static struct finsh_node* proc_primary_expr(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node* expr; - - next_token(token, &(self->token)); - switch ( token ) - { - case finsh_token_type_identifier: - { - char id[FINSH_NAME_MAX + 1]; - - finsh_token_replay(&(self->token)); - proc_identifier(self, id); - return finsh_node_new_id(id); - } - - case finsh_token_type_left_paren: - expr = proc_expr(self); - match_token(token, &(self->token), finsh_token_type_right_paren); - return expr; - - case finsh_token_type_value_int: - return finsh_node_new_int(self->token.value.int_value); - - case finsh_token_type_value_long: - return finsh_node_new_long(self->token.value.long_value); - - case finsh_token_type_value_char: - return finsh_node_new_char(self->token.value.char_value); - - case finsh_token_type_value_string: - return finsh_node_new_string((char*)self->token.string); - - case finsh_token_type_value_null: - return finsh_node_new_ptr(NULL); - - default: - finsh_error_set(FINSH_ERROR_INVALID_TOKEN); - break; - } - - return NULL; -} - -/* -param_list -> empty - | expr_assign - | param_list ',' expr_assign -*/ -static struct finsh_node* proc_param_list(struct finsh_parser* self) -{ - enum finsh_token_type token; - struct finsh_node *node, *assign; - - assign = proc_assign_expr(self); - if (assign == NULL) return NULL; - node = assign; - - next_token(token, &(self->token)); - while (token == finsh_token_type_comma ) - { - finsh_node_sibling(assign) = proc_assign_expr(self); - - if (finsh_node_sibling(assign) != NULL) assign = finsh_node_sibling(assign); - else finsh_error_set(FINSH_ERROR_EXPECT_OPERATOR); - - next_token(token, &(self->token)); - } - - finsh_token_replay(&(self->token)); - - return node; -} - -/* -make a new node as following tree: -new_node -| -node1__ - \ - node2 -*/ -static struct finsh_node* make_sys_node(uint8_t type, struct finsh_node* node1, struct finsh_node* node2) -{ - struct finsh_node* node; - - node = finsh_node_allocate(type); - - if ((node1 != NULL) && (node != NULL)) - { - finsh_node_child(node) = node1; - finsh_node_sibling(node1) = node2; - } - else finsh_error_set(FINSH_ERROR_NULL_NODE); - - return node; -} - -/* -start -> statement_expr | decl_variable -*/ -void finsh_parser_run(struct finsh_parser* self, const uint8_t* string) -{ - enum finsh_token_type token; - struct finsh_node *node; - - node = NULL; - - /* init parser */ - self->parser_string = (uint8_t*)string; - - /* init token */ - finsh_token_init(&(self->token), self->parser_string); - - /* get next token */ - next_token(token, &(self->token)); - while (token != finsh_token_type_eof && token != finsh_token_type_bad) - { - switch (token) - { - case finsh_token_type_identifier: - /* process expr_statement */ - finsh_token_replay(&(self->token)); - - if (self->root != NULL) - { - finsh_node_sibling(node) = proc_expr_statement(self); - if (finsh_node_sibling(node) != NULL) - node = finsh_node_sibling(node); - } - else - { - node = proc_expr_statement(self); - self->root = node; - } - break; - - default: - if (is_base_type(token) || token == finsh_token_type_unsigned) - { - /* variable decl */ - finsh_token_replay(&(self->token)); - - if (self->root != NULL) - { - finsh_node_sibling(node) = proc_variable_decl(self); - if (finsh_node_sibling(node) != NULL) - node = finsh_node_sibling(node); - } - else - { - node = proc_variable_decl(self); - self->root = node; - } - } - else - { - /* process expr_statement */ - finsh_token_replay(&(self->token)); - - if (self->root != NULL) - { - finsh_node_sibling(node) = proc_expr_statement(self); - if (finsh_node_sibling(node) != NULL) - node = finsh_node_sibling(node); - else next_token(token, &(self->token)); - } - else - { - node = proc_expr_statement(self); - self->root = node; - } - } - - break; - } - - /* no root found, break out */ - if (self->root == NULL) break; - - /* get next token */ - next_token(token, &(self->token)); - } -} - -int finsh_parser_init(struct finsh_parser* self) -{ - memset(self, 0, sizeof(struct finsh_parser)); - - return 0; -} diff --git a/components/finsh/finsh_token.c b/components/finsh/finsh_token.c deleted file mode 100644 index 5fb593d81677922dc524a74339bdf937fd9d5024..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_token.c +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - * 2013-04-03 Bernard strip more characters. - */ -#include -#include - -#include "finsh_token.h" -#include "finsh_error.h" - -#define is_alpha(ch) ((ch | 0x20) - 'a') < 26u -#define is_digit(ch) ((ch) >= '0' && (ch) <= '9') -#define is_xdigit(ch) (((ch) >= '0' && (ch) <= '9') || (((ch | 0x20) - 'a') < 6u)) -#define is_separator(ch) !(((ch) >= 'a' && (ch) <= 'z') \ - || ((ch) >= 'A' && (ch) <= 'Z') || ((ch) >= '0' && (ch) <= '9') || ((ch) == '_')) -#define is_eof(self) (self)->eof - -struct name_table -{ - char* name; - enum finsh_token_type type; -}; - -/* keyword */ -static const struct name_table finsh_name_table[] = -{ - {"void", finsh_token_type_void}, - {"char", finsh_token_type_char}, - {"short", finsh_token_type_short}, - {"int", finsh_token_type_int}, - {"long", finsh_token_type_long}, - {"unsigned", finsh_token_type_unsigned}, - - {"NULL", finsh_token_type_value_null}, - {"null", finsh_token_type_value_null} -}; - -static char token_next_char(struct finsh_token* self); -static void token_prev_char(struct finsh_token* self); -static long token_spec_number(char* string, int length, int b); -static void token_run(struct finsh_token* self); -static int token_match_name(struct finsh_token* self, const char* str); -static void token_proc_number(struct finsh_token* self); -static uint8_t* token_proc_string(struct finsh_token* self); -static void token_trim_space(struct finsh_token* self); -static char token_proc_char(struct finsh_token* self); -static int token_proc_escape(struct finsh_token* self); - -void finsh_token_init(struct finsh_token* self, uint8_t* line) -{ - memset(self, 0, sizeof(struct finsh_token)); - - self->line = line; -} - -enum finsh_token_type finsh_token_token(struct finsh_token* self) -{ - if ( self->replay ) self->replay = 0; - else token_run(self); - - return (enum finsh_token_type)self->current_token; -} - -void finsh_token_get_token(struct finsh_token* self, uint8_t* token) -{ - strncpy((char*)token, (char*)self->string, FINSH_NAME_MAX); -} - -int token_get_string(struct finsh_token* self, uint8_t* str) -{ - unsigned char *p=str; - char ch; - - ch = token_next_char(self); - if (is_eof(self)) return -1; - - str[0] = '\0'; - - if ( is_digit(ch) )/*the first character of identifier is not a digit.*/ - { - token_prev_char(self); - return -1; - } - - while (!is_separator(ch) && !is_eof(self)) - { - *p++ = ch; - - ch = token_next_char(self); - } - self->eof = 0; - - token_prev_char(self); - *p = '\0'; - - return 0; -} - -/* -get next character. -*/ -static char token_next_char(struct finsh_token* self) -{ - if (self->eof) return '\0'; - - if (self->position == (int)strlen((char*)self->line) || self->line[self->position] =='\n') - { - self->eof = 1; - self->position = 0; - return '\0'; - } - - return self->line[self->position++]; -} - -static void token_prev_char(struct finsh_token* self) -{ - if ( self->eof ) return; - - if ( self->position == 0 ) return; - else self->position--; -} - -static void token_run(struct finsh_token* self) -{ - char ch; - - token_trim_space(self); /* first trim space and tab. */ - token_get_string(self, &(self->string[0])); - - if ( is_eof(self) ) /*if it is eof, break;*/ - { - self->current_token = finsh_token_type_eof; - return ; - } - - if (self->string[0] != '\0') /*It is a key word or a identifier.*/ - { - if ( !token_match_name(self, (char*)self->string) ) - { - self->current_token = finsh_token_type_identifier; - } - } - else/*It is a operator character.*/ - { - ch = token_next_char(self); - - switch ( ch ) - { - case '(': - self->current_token = finsh_token_type_left_paren; - break; - - case ')': - self->current_token = finsh_token_type_right_paren; - break; - - case ',': - self->current_token = finsh_token_type_comma; - break; - - case ';': - self->current_token = finsh_token_type_semicolon; - break; - - case '&': - self->current_token = finsh_token_type_and; - break; - - case '*': - self->current_token = finsh_token_type_mul; - break; - - case '+': - ch = token_next_char(self); - - if ( ch == '+' ) - { - self->current_token = finsh_token_type_inc; - } - else - { - token_prev_char(self); - self->current_token = finsh_token_type_add; - } - break; - - case '-': - ch = token_next_char(self); - - if ( ch == '-' ) - { - self->current_token = finsh_token_type_dec; - } - else - { - token_prev_char(self); - self->current_token = finsh_token_type_sub; - } - break; - - case '/': - ch = token_next_char(self); - if (ch == '/') - { - /* line comments, set to end of file */ - self->current_token = finsh_token_type_eof; - } - else - { - token_prev_char(self); - self->current_token = finsh_token_type_div; - } - break; - - case '<': - ch = token_next_char(self); - - if ( ch == '<' ) - { - self->current_token = finsh_token_type_shl; - } - else - { - token_prev_char(self); - self->current_token = finsh_token_type_bad; - } - break; - - case '>': - ch = token_next_char(self); - - if ( ch == '>' ) - { - self->current_token = finsh_token_type_shr; - } - else - { - token_prev_char(self); - self->current_token = finsh_token_type_bad; - } - break; - - case '|': - self->current_token = finsh_token_type_or; - break; - - case '%': - self->current_token = finsh_token_type_mod; - break; - - case '~': - self->current_token = finsh_token_type_bitwise; - break; - - case '^': - self->current_token = finsh_token_type_xor; - break; - - case '=': - self->current_token = finsh_token_type_assign; - break; - - case '\'': - self->value.char_value = token_proc_char(self); - self->current_token = finsh_token_type_value_char; - break; - - case '"': - token_proc_string(self); - self->current_token = finsh_token_type_value_string; - break; - - default: - if ( is_digit(ch) ) - { - token_prev_char(self); - token_proc_number(self); - break; - } - - finsh_error_set(FINSH_ERROR_UNKNOWN_TOKEN); - self->current_token = finsh_token_type_bad; - - break; - } - } -} - -static int token_match_name(struct finsh_token* self, const char* str) -{ - int i; - - for (i = 0; i < sizeof(finsh_name_table)/sizeof(struct name_table); i++) - { - if ( strcmp(finsh_name_table[i].name, str)==0 ) - { - self->current_token = finsh_name_table[i].type; - return 1; - } - } - - return 0; -} - -static void token_trim_space(struct finsh_token* self) -{ - char ch; - while ( (ch = token_next_char(self)) ==' ' || - ch == '\t' || - ch == '\r'); - - token_prev_char(self); -} - -static char token_proc_char(struct finsh_token* self) -{ - char ch; - char buf[4], *p; - - p = buf; - ch = token_next_char(self); - - if ( ch == '\\' ) - { - ch = token_next_char(self); - switch ( ch ) - { - case 'n': ch = '\n'; break; - case 't': ch = '\t'; break; - case 'v': ch = '\v'; break; - case 'b': ch = '\b'; break; - case 'r': ch = '\r'; break; - case '\\': ch = '\\'; break; - case '\'': ch = '\''; break; - default : - while ( is_digit(ch) )/*for '\113' char*/ - { - ch = token_next_char(self); - *p++ = ch; - } - - token_prev_char(self); - *p = '\0'; - ch = atoi(p); - break; - } - } - - if ( token_next_char(self) != '\'' ) - { - token_prev_char(self); - finsh_error_set(FINSH_ERROR_EXPECT_CHAR); - return ch; - } - - return ch; -} - -static uint8_t* token_proc_string(struct finsh_token* self) -{ - uint8_t* p; - - for ( p = &self->string[0]; p - &(self->string[0]) < FINSH_STRING_MAX; ) - { - char ch = token_next_char(self); - - if ( is_eof(self) ) - { - finsh_error_set(FINSH_ERROR_UNEXPECT_END); - return NULL;; - } - if ( ch == '\\' ) - { - ch = token_proc_escape(self); - } - else if ( ch == '"' )/*end of string.*/ - { - *p = '\0'; - return self->string; - } - - *p++ = ch; - } - - return NULL; -} - -static int token_proc_escape(struct finsh_token* self) -{ - char ch; - int result=0; - - ch = token_next_char(self); - switch (ch) - { - case 'n': - result = '\n'; - break; - case 't': - result = '\t'; - break; - case 'v': - result = '\v'; - break; - case 'b': - result = '\b'; - break; - case 'r': - result = '\r'; - break; - case 'f': - result = '\f'; - break; - case 'a': - result = '\007'; - break; - case '"': - result = '"'; - break; - case 'x': - case 'X': - result = 0; - ch = token_next_char(self); - while (is_xdigit(ch)) - { - result = result * 16 + ((ch < 'A') ? (ch - '0') : (ch | 0x20) - 'a' + 10); - ch = token_next_char(self); - } - token_prev_char(self); - break; - default: - if ( (ch - '0') < 8u) - { - result = 0; - while ( (ch - '0') < 8u ) - { - result = result*8 + ch - '0'; - ch = token_next_char(self); - } - - token_prev_char(self); - } - break; - } - - return result; -} - -/* -(0|0x|0X|0b|0B)number+(l|L) -*/ -static void token_proc_number(struct finsh_token* self) -{ - char ch; - char *p, buf[128]; - long value; - - value = 0; - p = buf; - - ch = token_next_char(self); - if ( ch == '0' ) - { - int b; - ch = token_next_char(self); - if ( ch == 'x' || ch == 'X' )/*it's a hex number*/ - { - b = 16; - ch = token_next_char(self); - while ( is_digit(ch) || is_alpha(ch) ) - { - *p++ = ch; - ch = token_next_char(self); - } - - *p = '\0'; - } - else if ( ch == 'b' || ch == 'B' ) - { - b = 2; - ch = token_next_char(self); - while ( (ch=='0')||(ch=='1') ) - { - *p++ = ch; - ch = token_next_char(self); - } - - *p = '\0'; - } - else if ( '0' <= ch && ch <= '7' ) - { - b = 8; - while ( '0' <= ch && ch <= '7' ) - { - *p++ = ch; - ch = token_next_char(self); - } - - *p = '\0'; - } - else - { - token_prev_char(self); - - /* made as 0 value */ - self->value.int_value = 0; - self->current_token = finsh_token_type_value_int; - return; - } - - self->value.int_value = token_spec_number(buf, strlen(buf), b); - self->current_token = finsh_token_type_value_int; - } - else - { - while ( is_digit(ch) ) - { - value = value*10 + ( ch - '0' ); - ch = token_next_char(self); - } - - self->value.int_value = value; - self->current_token = finsh_token_type_value_int; - } - - switch ( ch ) - { - case 'l': - case 'L': - self->current_token = finsh_token_type_value_long; - break; - - default: - token_prev_char(self); - break; - } -} - -/*use 64 bit number*/ -#define BN_SIZE 2 - -static long token_spec_number(char* string, int length, int b) -{ - char* p; - int t; - int i, j, shift=1; - unsigned int bn[BN_SIZE], v; - long d; - - p = string; - i = 0; - - switch ( b ) - { - case 16: shift = 4; - break; - case 8: shift = 3; - break; - case 2: shift = 1; - break; - default: break; - } - - for ( j=0; j='a' && t <='f' ) - { - t = t - 'a' +10; - } - else if ( t >='A' && t <='F' ) - { - t = t - 'A' +10; - } - else t = t - '0'; - - for ( j=0; j> (32 - shift); - } - i++; - } - - d = (long)bn[0]; - - return d; -} diff --git a/components/finsh/finsh_token.h b/components/finsh/finsh_token.h deleted file mode 100644 index 0ce98c0f14fc1021bc7478517745daba335d9e3c..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_token.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#ifndef __FINSH_TOKEN_H__ -#define __FINSH_TOKEN_H__ - -#include - -enum finsh_token_type -{ - finsh_token_type_left_paren = 1, /* ( */ - finsh_token_type_right_paren , /* ) */ - finsh_token_type_comma , /* , */ - finsh_token_type_semicolon , /* ; */ - finsh_token_type_mul , /* * */ - finsh_token_type_add , /* + */ - finsh_token_type_inc , /* ++ */ - finsh_token_type_sub , /* - */ - finsh_token_type_dec , /* -- */ - finsh_token_type_div , /* / */ - finsh_token_type_mod , /* % */ - finsh_token_type_assign , /* = */ - finsh_token_type_and, /* & */ - finsh_token_type_or, /* | */ - finsh_token_type_xor, /* ^ */ - finsh_token_type_bitwise, /* ~ */ - finsh_token_type_shl, /* << */ - finsh_token_type_shr, /* >> */ - finsh_token_type_comments, /* // */ - /*-- data type --*/ - finsh_token_type_void, /* void */ - finsh_token_type_char, /* char */ - finsh_token_type_short, /* short */ - finsh_token_type_int, /* int */ - finsh_token_type_long, /* long */ - finsh_token_type_unsigned, /* unsigned */ - /* data value type */ - finsh_token_type_value_char, /* v:char */ - finsh_token_type_value_int, /* v:int */ - finsh_token_type_value_long, /* v:long */ - finsh_token_type_value_string, /* v:string */ - finsh_token_type_value_null, /* NULL */ - /*-- others --*/ - finsh_token_type_identifier, /* ID */ - finsh_token_type_bad, /* bad token */ - finsh_token_type_eof -}; - -#define finsh_token_position(self) (self)->position -#define finsh_token_replay(self) (self)->replay = 1 - -void finsh_token_init(struct finsh_token* self, uint8_t* script); - -enum finsh_token_type finsh_token_token(struct finsh_token* self); -void finsh_token_get_token(struct finsh_token* self, uint8_t* token); - -#endif diff --git a/components/finsh/finsh_var.c b/components/finsh/finsh_var.c deleted file mode 100644 index 6a27bf1fabdf4352384a5250aa9d8958592ece50..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_var.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - * 2012-04-27 Bernard fixed finsh_var_delete issue which - * is found by Grissiom. - */ -#include -#include "finsh_var.h" - -struct finsh_var global_variable[FINSH_VARIABLE_MAX]; -struct finsh_sysvar_item* global_sysvar_list; - -int finsh_var_init() -{ - memset(global_variable, 0, sizeof(global_variable)); - - return 0; -} - -int finsh_var_insert(const char* name, int type) -{ - int i, empty; - - empty = -1; - for (i = 0; i < FINSH_VARIABLE_MAX; i ++) - { - /* there is a same name variable exist. */ - if (strncmp(global_variable[i].name, name, FINSH_NAME_MAX) == 0) - return -1; - - if (global_variable[i].type == finsh_type_unknown && empty == -1) - { - empty = i; - } - } - - /* there is no empty entry */ - if (empty == -1) return -1; - - /* insert entry */ - strncpy(global_variable[empty].name, name, FINSH_NAME_MAX); - global_variable[empty].type = type; - - /* return the offset */ - return empty; -} - -int finsh_var_delete(const char* name) -{ - int i; - - for (i = 0; i < FINSH_VARIABLE_MAX; i ++) - { - if (strncmp(global_variable[i].name, name, FINSH_NAME_MAX) == 0) - break; - } - - /* can't find variable */ - if (i == FINSH_VARIABLE_MAX) return -1; - - memset(&global_variable[i], 0, sizeof(struct finsh_var)); - - return 0; -} - -struct finsh_var* finsh_var_lookup(const char* name) -{ - int i; - - for (i = 0; i < FINSH_VARIABLE_MAX; i ++) - { - if (strncmp(global_variable[i].name, name, FINSH_NAME_MAX) == 0) - break; - } - - /* can't find variable */ - if (i == FINSH_VARIABLE_MAX) return NULL; - - return &global_variable[i]; -} - -#ifdef RT_USING_HEAP -void finsh_sysvar_append(const char* name, uint8_t type, void* var_addr) -{ - /* create a sysvar */ - struct finsh_sysvar_item* item; - - item = (struct finsh_sysvar_item*) rt_malloc (sizeof(struct finsh_sysvar_item)); - if (item != NULL) - { - item->next = NULL; - item->sysvar.name = rt_strdup(name); - item->sysvar.type = type; - item->sysvar.var = var_addr; - - if (global_sysvar_list == NULL) - { - global_sysvar_list = item; - } - else - { - item->next = global_sysvar_list; - global_sysvar_list = item; - } - } -} -#endif - -struct finsh_sysvar* finsh_sysvar_lookup(const char* name) -{ - struct finsh_sysvar* index; - struct finsh_sysvar_item* item; - - for (index = _sysvar_table_begin; - index < _sysvar_table_end; - FINSH_NEXT_SYSVAR(index)) - { - if (strcmp(index->name, name) == 0) - return index; - } - - /* find in sysvar list */ - item = global_sysvar_list; - while (item != NULL) - { - if (strncmp(item->sysvar.name, name, strlen(name)) == 0) - { - return &(item->sysvar); - } - - /* move to next item */ - item = item->next; - } - - /* can't find variable */ - return NULL; -} diff --git a/components/finsh/finsh_var.h b/components/finsh/finsh_var.h deleted file mode 100644 index 8d7ee6a201a8185141d59e7d7b869e0c1ca13b5d..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_var.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#ifndef __FINSH_VAR_H__ -#define __FINSH_VAR_H__ - -#include - -/* - * The variable in finsh is put in data segment as a global variable. - * The 'finsh_var' structure presents the structure of variable in data segment. - */ -struct finsh_var -{ - char name[FINSH_NAME_MAX + 1]; /* the name of variable */ - - uint8_t type; /* the type of variable */ - - /* variable value */ - union { - char char_value; - short short_value; - int int_value; - long long_value; - void* ptr; - }value; -}; -extern struct finsh_var global_variable[]; - -int finsh_var_init(void); -int finsh_var_insert(const char* name, int type); -int finsh_var_delete(const char* name); -struct finsh_var* finsh_var_lookup(const char* name); - -#endif diff --git a/components/finsh/finsh_vm.c b/components/finsh/finsh_vm.c deleted file mode 100644 index 7c564070841976e424770d73dc9bc6616043a259..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_vm.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#include - -#include "finsh_vm.h" -#include "finsh_ops.h" -#include "finsh_var.h" - -/* stack */ -union finsh_value finsh_vm_stack[FINSH_STACK_MAX]; -/* text segment */ -uint8_t text_segment[FINSH_TEXT_MAX]; - -union finsh_value* finsh_sp; /* stack pointer */ -uint8_t* finsh_pc; /* PC */ - -/* syscall list, for dynamic system call register */ -struct finsh_syscall_item* global_syscall_list = NULL; - -// #define FINSH_VM_DISASSEMBLE -void finsh_vm_run() -{ - uint8_t op; - - /* if you want to disassemble the byte code, please define FINSH_VM_DISASSEMBLE */ -#ifdef FINSH_VM_DISASSEMBLE - void finsh_disassemble(); - finsh_disassemble(); -#endif - - /* set sp(stack pointer) to the beginning of stack */ - finsh_sp = &finsh_vm_stack[0]; - - /* set pc to the beginning of text segment */ - finsh_pc = &text_segment[0]; - - while ((finsh_pc - &text_segment[0] >= 0) && - (finsh_pc - &text_segment[0] < FINSH_TEXT_MAX)) - { - /* get op */ - op = *finsh_pc++; - - /* call op function */ - op_table[op](); - } -} - -#ifdef RT_USING_HEAP -void finsh_syscall_append(const char* name, syscall_func func) -{ - /* create the syscall */ - struct finsh_syscall_item* item; - - item = (struct finsh_syscall_item*)rt_malloc(sizeof(struct finsh_syscall_item)); - if (item != RT_NULL) - { - item->next = NULL; - item->syscall.name = rt_strdup(name); - item->syscall.func = func; - - if (global_syscall_list == NULL) - { - global_syscall_list = item; - } - else - { - item->next = global_syscall_list; - global_syscall_list = item; - } - } -} -#endif - -struct finsh_syscall* finsh_syscall_lookup(const char* name) -{ - struct finsh_syscall* index; - struct finsh_syscall_item* item; - - for (index = _syscall_table_begin; index < _syscall_table_end; FINSH_NEXT_SYSCALL(index)) - { - if (strcmp(index->name, name) == 0) - return index; - } - - /* find on syscall list */ - item = global_syscall_list; - while (item != NULL) - { - if (strncmp(item->syscall.name, name, strlen(name)) == 0) - { - return &(item->syscall); - } - - item = item->next; - } - - return NULL; -} - -#ifdef FINSH_VM_DISASSEMBLE -void finsh_disassemble() -{ - uint8_t *pc, op; - - pc = &text_segment[0]; - while (*pc != 0) - { - op = *pc; - switch (op) - { - case FINSH_OP_ADD_BYTE: - pc ++; - rt_kprintf("addb\n"); - break; - - case FINSH_OP_SUB_BYTE: - pc ++; - rt_kprintf("subb\n"); - break; - - case FINSH_OP_DIV_BYTE: - pc ++; - rt_kprintf("divb\n"); - break; - - case FINSH_OP_MOD_BYTE: - pc ++; - rt_kprintf("modb\n"); - break; - - case FINSH_OP_MUL_BYTE: - pc ++; - rt_kprintf("mulb\n"); - break; - - case FINSH_OP_AND_BYTE: - pc ++; - rt_kprintf("andb\n"); - break; - - case FINSH_OP_OR_BYTE: - pc ++; - rt_kprintf("orb\n"); - break; - - case FINSH_OP_XOR_BYTE: - pc ++; - rt_kprintf("xorb\n"); - break; - - case FINSH_OP_BITWISE_BYTE: - pc ++; - rt_kprintf("bwb\n"); - break; - - case FINSH_OP_SHL_BYTE: - pc ++; - rt_kprintf("shlb\n"); - break; - - case FINSH_OP_SHR_BYTE: - pc ++; - rt_kprintf("shrb\n"); - break; - - case FINSH_OP_LD_BYTE: - pc ++; - rt_kprintf("ldb %d\n", *pc++); - break; - - case FINSH_OP_LD_VALUE_BYTE: - pc ++; - rt_kprintf("ldb [0x%x]\n", FINSH_GET32(pc)); - pc += 4; - break; - - case FINSH_OP_ST_BYTE: - pc ++; - rt_kprintf("stb\n"); - break; - - case FINSH_OP_ADD_WORD: - pc ++; - rt_kprintf("addw\n"); - break; - - case FINSH_OP_SUB_WORD: - pc ++; - rt_kprintf("subw\n"); - break; - - case FINSH_OP_DIV_WORD: - pc ++; - rt_kprintf("divw\n"); - break; - - case FINSH_OP_MOD_WORD: - pc ++; - rt_kprintf("modw\n"); - break; - - case FINSH_OP_MUL_WORD: - pc ++; - rt_kprintf("mulw\n"); - break; - - case FINSH_OP_AND_WORD: - pc ++; - rt_kprintf("andw\n"); - break; - - case FINSH_OP_OR_WORD: - pc ++; - rt_kprintf("orw\n"); - break; - - case FINSH_OP_XOR_WORD: - pc ++; - rt_kprintf("xorw\n"); - break; - - case FINSH_OP_BITWISE_WORD: - pc ++; - rt_kprintf("bww\n"); - break; - - case FINSH_OP_SHL_WORD: - pc ++; - rt_kprintf("shlw\n"); - break; - - case FINSH_OP_SHR_WORD: - pc ++; - rt_kprintf("shrw\n"); - break; - - case FINSH_OP_LD_WORD: - pc ++; - rt_kprintf("ldw %d\n", FINSH_GET16(pc)); - pc += 2; - break; - - case FINSH_OP_LD_VALUE_WORD: - pc ++; - rt_kprintf("ldw [0x%x]\n", FINSH_GET32(pc)); - pc += 4; - break; - - case FINSH_OP_ST_WORD: - pc ++; - rt_kprintf("stw\n"); - break; - - case FINSH_OP_ADD_DWORD: - pc ++; - rt_kprintf("addd\n"); - break; - - case FINSH_OP_SUB_DWORD: - pc ++; - rt_kprintf("subd\n"); - break; - - case FINSH_OP_DIV_DWORD: - pc ++; - rt_kprintf("divd\n"); - break; - - case FINSH_OP_MOD_DWORD: - pc ++; - rt_kprintf("modd\n"); - break; - - case FINSH_OP_MUL_DWORD: - pc ++; - rt_kprintf("muld\n"); - break; - - case FINSH_OP_AND_DWORD: - pc ++; - rt_kprintf("andd\n"); - break; - - case FINSH_OP_OR_DWORD: - pc ++; - rt_kprintf("ord\n"); - break; - - case FINSH_OP_XOR_DWORD: - pc ++; - rt_kprintf("xord\n"); - break; - - case FINSH_OP_BITWISE_DWORD: - pc ++; - rt_kprintf("bwd\n"); - break; - - case FINSH_OP_SHL_DWORD: - pc ++; - rt_kprintf("shld\n"); - break; - - case FINSH_OP_SHR_DWORD: - pc ++; - rt_kprintf("shrd\n"); - break; - - case FINSH_OP_LD_DWORD: - pc ++; - rt_kprintf("ldd 0x%x\n", FINSH_GET32(pc)); - pc += 4; - break; - - case FINSH_OP_LD_VALUE_DWORD: - pc ++; - rt_kprintf("ldd [0x%x]\n", FINSH_GET32(pc)); - pc += 4; - break; - - case FINSH_OP_ST_DWORD: - pc ++; - rt_kprintf("std\n"); - break; - - case FINSH_OP_POP: - rt_kprintf("pop\n"); - pc ++; - break; - - case FINSH_OP_SYSCALL: - pc ++; - rt_kprintf("syscall %d\n", *pc++); - break; - - case FINSH_OP_LD_VALUE_BYTE_STACK: - pc ++; - rt_kprintf("ldb [sp]\n"); - break; - - case FINSH_OP_LD_VALUE_WORD_STACK: - pc ++; - rt_kprintf("ldw [sp]\n"); - break; - - case FINSH_OP_LD_VALUE_DWORD_STACK: - pc ++; - rt_kprintf("ldd [sp]\n"); - break; - - default: - return; - } - } -} -#endif diff --git a/components/finsh/finsh_vm.h b/components/finsh/finsh_vm.h deleted file mode 100644 index fc515418e4775a2147361f2cf69383a35a521475..0000000000000000000000000000000000000000 --- a/components/finsh/finsh_vm.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ -#ifndef __FINSH_VM_H__ -#define __FINSH_VM_H__ - -#include - -#include "finsh_var.h" - -union finsh_value { - char char_value; - short short_value; - long long_value; - void* ptr; -}; - -extern union finsh_value* finsh_sp; /* stack pointer */ -extern uint8_t* finsh_pc; /* PC */ - -/* stack */ -extern union finsh_value finsh_vm_stack[FINSH_STACK_MAX]; -/* text segment */ -extern uint8_t text_segment[FINSH_TEXT_MAX]; - -void finsh_vm_run(void); -//void finsh_disassemble(void); - -#endif diff --git a/components/finsh/msh.c b/components/finsh/msh.c index 79f1e3c87f9d5b0fe7e25368acbd65eb3812e107..7a4a3a887f8242ec2bcc708a65ba5bdae2e11c99 100644 --- a/components/finsh/msh.c +++ b/components/finsh/msh.c @@ -11,11 +11,15 @@ */ #include -#ifdef FINSH_USING_MSH +#if defined(RT_USING_MSH) || defined(FINSH_USING_MSH) + +#ifndef FINSH_ARG_MAX +#define FINSH_ARG_MAX 8 +#endif #include "msh.h" -#include -#include +#include "shell.h" +#include #ifdef RT_USING_DFS #include @@ -25,46 +29,8 @@ #include #endif -#ifndef FINSH_ARG_MAX -#define FINSH_ARG_MAX 8 -#endif - typedef int (*cmd_function_t)(int argc, char **argv); -#ifdef FINSH_USING_MSH -#ifdef FINSH_USING_MSH_ONLY -rt_bool_t msh_is_used(void) -{ - return RT_TRUE; -} -#else -#ifdef FINSH_USING_MSH_DEFAULT -static rt_bool_t __msh_state = RT_TRUE; -#else -static rt_bool_t __msh_state = RT_FALSE; -#endif -rt_bool_t msh_is_used(void) -{ - return __msh_state; -} - -static int msh_exit(int argc, char **argv) -{ - /* return to finsh shell mode */ - __msh_state = RT_FALSE; - return 0; -} -FINSH_FUNCTION_EXPORT_ALIAS(msh_exit, __cmd_exit, return to RT-Thread shell mode.); - -static int msh_enter(void) -{ - /* enter module shell mode */ - __msh_state = RT_TRUE; - return 0; -} -FINSH_FUNCTION_EXPORT_ALIAS(msh_enter, msh, use module shell); -#endif - int msh_help(int argc, char **argv) { rt_kprintf("RT-Thread shell commands:\n"); @@ -87,7 +53,7 @@ int msh_help(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(msh_help, __cmd_help, RT-Thread shell help.); +MSH_CMD_EXPORT_ALIAS(msh_help, help, RT-Thread shell help.); int cmd_ps(int argc, char **argv) { @@ -102,7 +68,7 @@ int cmd_ps(int argc, char **argv) list_thread(); return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_ps, __cmd_ps, List threads in the system.); +MSH_CMD_EXPORT_ALIAS(cmd_ps, ps, List threads in the system.); #ifdef RT_USING_HEAP int cmd_free(int argc, char **argv) @@ -117,7 +83,7 @@ int cmd_free(int argc, char **argv) #endif return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_free, __cmd_free, Show the memory usage in the system.); +MSH_CMD_EXPORT_ALIAS(cmd_free, free, Show the memory usage in the system.); #endif static int msh_split(char *cmd, rt_size_t length, char *argv[FINSH_ARG_MAX]) @@ -232,7 +198,7 @@ int msh_exec_module(const char *cmd_line, int size) length = cmd_length + 32; /* allocate program name memory */ - pg_name = (char *) rt_malloc(length); + pg_name = (char *) rt_malloc(length + 3); if (pg_name == RT_NULL) return -RT_ENOMEM; @@ -331,16 +297,25 @@ static int _msh_exec_cmd(char *cmd, rt_size_t length, int *retp) return 0; } +#ifdef RT_USING_GDBSERVER +pid_t exec(char*, int, int, char**); +#else +pid_t exec(char*, int, char**); +#endif + #if defined(RT_USING_LWP) && defined(RT_USING_DFS) -static int _msh_exec_lwp(char *cmd, rt_size_t length) +#ifdef RT_USING_GDBSERVER +int _msh_exec_lwp(int debug, char *cmd, rt_size_t length) +#else +int _msh_exec_lwp(char *cmd, rt_size_t length) +#endif { int argc; int cmd0_size = 0; char *argv[FINSH_ARG_MAX]; int fd = -1; char *pg_name; - - extern int exec(char*, int, char**); + int ret; /* find the size of first command */ while ((cmd[cmd0_size] != ' ' && cmd[cmd0_size] != '\t') && cmd0_size < length) @@ -357,15 +332,176 @@ static int _msh_exec_lwp(char *cmd, rt_size_t length) pg_name = argv[0]; /* try to open program */ fd = open(pg_name, O_RDONLY, 0); - if (fd < 0) - return -1; + { + /* try to open *.elf file */ + pg_name = rt_malloc(strlen(argv[0]) + 64); + if (pg_name) + { + strcpy(pg_name, argv[0]); + strcat(pg_name, ".elf"); + + fd = open(pg_name, O_RDONLY, 0); + + /* try it in /bin */ + if (fd < 0) + { + if (strstr(argv[0], "elf") != NULL) + snprintf(pg_name, 64, "/bin/%s", argv[0]); + else + snprintf(pg_name, 64, "/bin/%s.elf", argv[0]); + fd = open(pg_name, O_RDONLY, 0); + } + + if (fd < 0) + { + rt_free(pg_name); + return -1; + } + } + else return -1; /* out of memory */ + } /* found program */ close(fd); - exec(pg_name, argc, argv); - return 0; +#ifdef RT_USING_GDBSERVER + ret = exec(pg_name, debug, argc, argv); +#else + ret = exec(pg_name, argc, argv); +#endif + if (pg_name != argv[0]) + rt_free(pg_name); + + return ret; +} +#endif + +#if defined(RT_USING_DFS) +static int msh_readline(int fd, char *line_buf, int size) +{ + char ch; + int index = 0; + + do + { + if (read(fd, &ch, 1) != 1) + { + /* nothing in this file */ + return 0; + } + } + while (ch == '\n' || ch == '\r'); + + /* set the first character */ + line_buf[index ++] = ch; + + while (index < size) + { + if (read(fd, &ch, 1) == 1) + { + if (ch == '\n' || ch == '\r') + { + line_buf[index] = '\0'; + break; + } + + line_buf[index++] = ch; + } + else + { + line_buf[index] = '\0'; + break; + } + } + + return index; +} + +int msh_exec_script(const char *cmd_line, int size) +{ + int ret; + int fd = -1; + char *pg_name; + int length, cmd_length = 0; + + if (size == 0) return -RT_ERROR; + + /* get the length of command0 */ + while ((cmd_line[cmd_length] != ' ' && cmd_line[cmd_length] != '\t') && cmd_length < size) + cmd_length ++; + + /* get name length */ + length = cmd_length + 32; + + /* allocate program name memory */ + pg_name = (char *) rt_malloc(length); + if (pg_name == RT_NULL) return -RT_ENOMEM; + + /* copy command0 */ + memcpy(pg_name, cmd_line, cmd_length); + pg_name[cmd_length] = '\0'; + + if (strstr(pg_name, ".sh") != RT_NULL || strstr(pg_name, ".SH") != RT_NULL) + { + /* try to open program */ + fd = open(pg_name, O_RDONLY, 0); + + /* search in /bin path */ + if (fd < 0) + { + rt_snprintf(pg_name, length - 1, "/bin/%.*s", cmd_length, cmd_line); + fd = open(pg_name, O_RDONLY, 0); + } + } + + rt_free(pg_name); + if (fd >= 0) + { + /* found script */ + char *line_buf; + int length; + + line_buf = (char *) rt_malloc(RT_CONSOLEBUF_SIZE); + if (line_buf == RT_NULL) + { + close(fd); + return -RT_ENOMEM; + } + + /* read line by line and then exec it */ + do + { + length = msh_readline(fd, line_buf, RT_CONSOLEBUF_SIZE); + if (length > 0) + { + char ch = '\0'; + int index; + + for (index = 0; index < length; index ++) + { + ch = line_buf[index]; + if (ch == ' ' || ch == '\t') continue; + else break; + } + + if (ch != '#') /* not a comment */ + msh_exec(line_buf, length); + } + } + while (length > 0); + + close(fd); + rt_free(line_buf); + + ret = 0; + } + else + { + ret = -1; + } + + return ret; } #endif @@ -407,7 +543,13 @@ int msh_exec(char *cmd, rt_size_t length) #endif #ifdef RT_USING_LWP - if (_msh_exec_lwp(cmd, length) == 0) +#ifdef RT_USING_GDBSERVER + /* exec from msh_exec , debug = 0*/ + /* _msh_exec_lwp return is pid , <= 0 means failed */ + if (_msh_exec_lwp(0, cmd, length) > 0) +#else + if (_msh_exec_lwp(cmd, length) > 0) +#endif { return 0; } @@ -595,7 +737,7 @@ void msh_auto_complete(char *prefix) ptr --; } -#ifdef RT_USING_MODULE +#if defined(RT_USING_MODULE) || defined(RT_USING_LWP) /* There is a chance that the user want to run the module directly. So * try to complete the file names. If the completed path is not a * module, the system won't crash anyway. */ @@ -642,6 +784,5 @@ void msh_auto_complete(char *prefix) return ; } -#endif -#endif /* FINSH_USING_MSH */ +#endif /* RT_USING_MSH */ diff --git a/components/finsh/msh.h b/components/finsh/msh.h index b7153107eab3b7f95997ffa51beed0ec90ef793d..bbcb1b9b4774e6013c756e2995e44cfcbd75f585 100644 --- a/components/finsh/msh.h +++ b/components/finsh/msh.h @@ -13,7 +13,6 @@ #include -rt_bool_t msh_is_used(void); int msh_exec(char *cmd, rt_size_t length); void msh_auto_complete(char *prefix); diff --git a/components/finsh/msh_file.c b/components/finsh/msh_file.c index 1368838b94c15ef897e79fce06d33b34ca928aae..8d4eaae89fe751e6679886cccd5e65d86d951cda 100644 --- a/components/finsh/msh_file.c +++ b/components/finsh/msh_file.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,138 +9,10 @@ */ #include - -#if defined(FINSH_USING_MSH) && defined(RT_USING_DFS) - -#include #include "msh.h" -#include - -static int msh_readline(int fd, char *line_buf, int size) -{ - char ch; - int index = 0; - - do - { - if (read(fd, &ch, 1) != 1) - { - /* nothing in this file */ - return 0; - } - } - while (ch == '\n' || ch == '\r'); - - /* set the first character */ - line_buf[index ++] = ch; - - while (index < size) - { - if (read(fd, &ch, 1) == 1) - { - if (ch == '\n' || ch == '\r') - { - line_buf[index] = '\0'; - break; - } - - line_buf[index++] = ch; - } - else - { - line_buf[index] = '\0'; - break; - } - } - - return index; -} - -int msh_exec_script(const char *cmd_line, int size) -{ - int ret; - int fd = -1; - char *pg_name; - int length, cmd_length = 0; - - if (size == 0) return -RT_ERROR; - - /* get the length of command0 */ - while ((cmd_line[cmd_length] != ' ' && cmd_line[cmd_length] != '\t') && cmd_length < size) - cmd_length ++; - - /* get name length */ - length = cmd_length + 32; - - /* allocate program name memory */ - pg_name = (char *) rt_malloc(length); - if (pg_name == RT_NULL) return -RT_ENOMEM; - /* copy command0 */ - memcpy(pg_name, cmd_line, cmd_length); - pg_name[cmd_length] = '\0'; - - if (strstr(pg_name, ".sh") != RT_NULL || strstr(pg_name, ".SH") != RT_NULL) - { - /* try to open program */ - fd = open(pg_name, O_RDONLY, 0); - - /* search in /bin path */ - if (fd < 0) - { - rt_snprintf(pg_name, length - 1, "/bin/%.*s", cmd_length, cmd_line); - fd = open(pg_name, O_RDONLY, 0); - } - } - - rt_free(pg_name); - if (fd >= 0) - { - /* found script */ - char *line_buf; - int length; - - line_buf = (char *) rt_malloc(RT_CONSOLEBUF_SIZE); - if (line_buf == RT_NULL) - { - close(fd); - return -RT_ENOMEM; - } - - /* read line by line and then exec it */ - do - { - length = msh_readline(fd, line_buf, RT_CONSOLEBUF_SIZE); - if (length > 0) - { - char ch = '\0'; - int index; - - for (index = 0; index < length; index ++) - { - ch = line_buf[index]; - if (ch == ' ' || ch == '\t') continue; - else break; - } - - if (ch != '#') /* not a comment */ - msh_exec(line_buf, length); - } - } - while (length > 0); - - close(fd); - rt_free(line_buf); - - ret = 0; - } - else - { - ret = -1; - } - - return ret; -} +#if defined(RT_USING_MSH) && defined(RT_USING_DFS) +#include #ifdef DFS_USING_WORKDIR extern char working_directory[]; @@ -165,7 +37,7 @@ int cmd_ls(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_ls, __cmd_ls, List information about the FILEs.); +MSH_CMD_EXPORT_ALIAS(cmd_ls, ls, List information about the FILEs.); int cmd_cp(int argc, char **argv) { @@ -183,7 +55,7 @@ int cmd_cp(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_cp, __cmd_cp, Copy SOURCE to DEST.); +MSH_CMD_EXPORT_ALIAS(cmd_cp, cp, Copy SOURCE to DEST.); int cmd_mv(int argc, char **argv) { @@ -242,7 +114,7 @@ int cmd_mv(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_mv, __cmd_mv, Rename SOURCE to DEST.); +MSH_CMD_EXPORT_ALIAS(cmd_mv, mv, Rename SOURCE to DEST.); int cmd_cat(int argc, char **argv) { @@ -263,9 +135,9 @@ int cmd_cat(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_cat, __cmd_cat, Concatenate FILE(s)); +MSH_CMD_EXPORT_ALIAS(cmd_cat, cat, Concatenate FILE(s)); -static void directory_delete_for_msh(const char *pathname, char f, char v) +static void msh_deltree(const char *pathname, char f, char v) { DIR *dir = NULL; struct dirent *dirent = NULL; @@ -312,7 +184,7 @@ static void directory_delete_for_msh(const char *pathname, char f, char v) } else if (dirent->d_type == DT_DIR) { - directory_delete_for_msh(full_path, f, v); + msh_deltree(full_path, f, v); } } } @@ -370,7 +242,7 @@ int cmd_rm(int argc, char **argv) if (r == 0) rt_kprintf("cannot remove '%s': Is a directory\n", argv[index]); else - directory_delete_for_msh(argv[index], f, v); + msh_deltree(argv[index], f, v); } else if (s.st_mode & S_IFREG) { @@ -392,7 +264,7 @@ int cmd_rm(int argc, char **argv) } return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_rm, __cmd_rm, Remove(unlink) the FILE(s).); +MSH_CMD_EXPORT_ALIAS(cmd_rm, rm, Remove(unlink) the FILE(s).); #ifdef DFS_USING_WORKDIR int cmd_cd(int argc, char **argv) @@ -411,14 +283,14 @@ int cmd_cd(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_cd, __cmd_cd, Change the shell working directory.); +MSH_CMD_EXPORT_ALIAS(cmd_cd, cd, Change the shell working directory.); int cmd_pwd(int argc, char **argv) { rt_kprintf("%s\n", working_directory); return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_pwd, __cmd_pwd, Print the name of the current working directory.); +MSH_CMD_EXPORT_ALIAS(cmd_pwd, pwd, Print the name of the current working directory.); #endif int cmd_mkdir(int argc, char **argv) @@ -435,7 +307,7 @@ int cmd_mkdir(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_mkdir, __cmd_mkdir, Create the DIRECTORY.); +MSH_CMD_EXPORT_ALIAS(cmd_mkdir, mkdir, Create the DIRECTORY.); int cmd_mkfs(int argc, char **argv) { @@ -467,7 +339,7 @@ int cmd_mkfs(int argc, char **argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_mkfs, __cmd_mkfs, format disk with file system); +MSH_CMD_EXPORT_ALIAS(cmd_mkfs, mkfs, format disk with file system); extern int df(const char *path); int cmd_df(int argc, char** argv) @@ -490,7 +362,7 @@ int cmd_df(int argc, char** argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_df, __cmd_df, disk free); +MSH_CMD_EXPORT_ALIAS(cmd_df, df, disk free); int cmd_echo(int argc, char** argv) { @@ -520,7 +392,6 @@ int cmd_echo(int argc, char** argv) return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_echo, __cmd_echo, echo string to file); - -#endif /* defined(FINSH_USING_MSH) && defined(RT_USING_DFS) */ +MSH_CMD_EXPORT_ALIAS(cmd_echo, echo, echo string to file); +#endif /* defined(RT_USING_MSH) && defined(RT_USING_DFS) */ diff --git a/components/finsh/shell.c b/components/finsh/shell.c index 61f0b9562e6c1c56f524059def2618c3276590db..3e110408ba3144da6535f3d181e0d73828219da4 100644 --- a/components/finsh/shell.c +++ b/components/finsh/shell.c @@ -19,19 +19,17 @@ */ #include +#include +#include -#ifdef RT_USING_FINSH +#if defined(RT_USING_MSH) || defined(FINSH_USING_MSH) -#include "finsh.h" #include "shell.h" - -#ifdef FINSH_USING_MSH #include "msh.h" -#endif -#ifdef _WIN32 -#include /* for putchar */ -#endif +#if defined(RT_USING_DFS) +#include +#endif /* RT_USING_DFS */ /* finsh thread */ #ifndef RT_USING_HEAP @@ -42,12 +40,8 @@ struct finsh_shell _shell; #endif /* finsh symtab */ -#ifdef FINSH_USING_SYMTAB struct finsh_syscall *_syscall_table_begin = NULL; struct finsh_syscall *_syscall_table_end = NULL; -struct finsh_sysvar *_sysvar_table_begin = NULL; -struct finsh_sysvar *_sysvar_table_end = NULL; -#endif struct finsh_shell *shell; static char *finsh_prompt_custom = RT_NULL; @@ -62,16 +56,6 @@ struct finsh_syscall* finsh_syscall_next(struct finsh_syscall* call) return (struct finsh_syscall*)ptr; } - -struct finsh_sysvar* finsh_sysvar_next(struct finsh_sysvar* call) -{ - unsigned int *ptr; - ptr = (unsigned int*) (call + 1); - while ((*ptr == 0) && ((unsigned int*)ptr < (unsigned int*) _sysvar_table_end)) - ptr ++; - - return (struct finsh_sysvar*)ptr; -} #endif /* defined(_MSC_VER) || (defined(__GNUC__) && defined(__x86_64__)) */ #ifdef RT_USING_HEAP @@ -97,14 +81,9 @@ int finsh_set_prompt(const char * prompt) } #endif /* RT_USING_HEAP */ -#if defined(RT_USING_DFS) -#include -#endif /* RT_USING_DFS */ - +#define _MSH_PROMPT "msh " const char *finsh_get_prompt(void) { -#define _MSH_PROMPT "msh " -#define _PROMPT "finsh " static char finsh_prompt[RT_CONSOLEBUF_SIZE + 1] = {0}; /* check prompt mode */ @@ -120,11 +99,7 @@ const char *finsh_get_prompt(void) return finsh_prompt; } -#ifdef FINSH_USING_MSH - if (msh_is_used()) strcpy(finsh_prompt, _MSH_PROMPT); - else -#endif - strcpy(finsh_prompt, _PROMPT); + strcpy(finsh_prompt, _MSH_PROMPT); #if defined(RT_USING_DFS) && defined(DFS_USING_WORKDIR) /* get current working directory */ @@ -372,71 +347,12 @@ static void finsh_wait_auth(void) static void shell_auto_complete(char *prefix) { - rt_kprintf("\n"); -#ifdef FINSH_USING_MSH - if (msh_is_used() == RT_TRUE) - { - msh_auto_complete(prefix); - } - else -#endif - { -#ifndef FINSH_USING_MSH_ONLY - extern void list_prefix(char * prefix); - list_prefix(prefix); -#endif - } + msh_auto_complete(prefix); rt_kprintf("%s%s", FINSH_PROMPT, prefix); } -#ifndef FINSH_USING_MSH_ONLY -void finsh_run_line(struct finsh_parser *parser, const char *line) -{ - const char *err_str; - - if(shell->echo_mode) - rt_kprintf("\n"); - finsh_parser_run(parser, (unsigned char *)line); - - /* compile node root */ - if (finsh_errno() == 0) - { - finsh_compiler_run(parser->root); - } - else - { - err_str = finsh_error_string(finsh_errno()); - rt_kprintf("%s\n", err_str); - } - - /* run virtual machine */ - if (finsh_errno() == 0) - { - char ch; - finsh_vm_run(); - - ch = (unsigned char)finsh_stack_bottom(); - if (ch > 0x20 && ch < 0x7e) - { - rt_kprintf("\t'%c', %d, 0x%08x\n", - (unsigned char)finsh_stack_bottom(), - (unsigned int)finsh_stack_bottom(), - (unsigned int)finsh_stack_bottom()); - } - else - { - rt_kprintf("\t%d, 0x%08x\n", - (unsigned int)finsh_stack_bottom(), - (unsigned int)finsh_stack_bottom()); - } - } - - finsh_flush(parser); -} -#endif - #ifdef FINSH_USING_HISTORY static rt_bool_t shell_handle_history(struct finsh_shell *shell) { @@ -508,10 +424,6 @@ void finsh_thread_entry(void *parameter) shell->echo_mode = 0; #endif -#ifndef FINSH_USING_MSH_ONLY - finsh_init(&shell->parser); -#endif - #if !defined(RT_USING_POSIX) && defined(RT_USING_DEVICE) /* set console device as shell device */ if (shell->device == RT_NULL) @@ -681,7 +593,8 @@ void finsh_thread_entry(void *parameter) } else { - rt_kprintf("\b \b"); + if (shell->echo_mode) + rt_kprintf("\b \b"); shell->line[shell->line_position] = 0; } @@ -695,25 +608,9 @@ void finsh_thread_entry(void *parameter) shell_push_history(shell); #endif -#ifdef FINSH_USING_MSH - if (msh_is_used() == RT_TRUE) - { - if (shell->echo_mode) - rt_kprintf("\n"); - msh_exec(shell->line, shell->line_position); - } - else -#endif - { -#ifndef FINSH_USING_MSH_ONLY - /* add ';' and run the command line */ - shell->line[shell->line_position] = ';'; - - if (shell->line_position != 0) finsh_run_line(&shell->parser, shell->line); - else - if (shell->echo_mode) rt_kprintf("\n"); -#endif - } + if (shell->echo_mode) + rt_kprintf("\n"); + msh_exec(shell->line, shell->line_position); rt_kprintf(FINSH_PROMPT); memset(shell->line, 0, sizeof(shell->line)); @@ -766,23 +663,14 @@ void finsh_system_function_init(const void *begin, const void *end) _syscall_table_end = (struct finsh_syscall *) end; } -void finsh_system_var_init(const void *begin, const void *end) -{ - _sysvar_table_begin = (struct finsh_sysvar *) begin; - _sysvar_table_end = (struct finsh_sysvar *) end; -} - #if defined(__ICCARM__) || defined(__ICCRX__) /* for IAR compiler */ #ifdef FINSH_USING_SYMTAB #pragma section="FSymTab" -#pragma section="VSymTab" #endif #elif defined(__ADSPBLACKFIN__) /* for VisaulDSP++ Compiler*/ #ifdef FINSH_USING_SYMTAB extern "asm" int __fsymtab_start; extern "asm" int __fsymtab_end; -extern "asm" int __vsymtab_start; -extern "asm" int __vsymtab_end; #endif #elif defined(_MSC_VER) #pragma section("FSymTab$a", read) @@ -820,31 +708,20 @@ int finsh_system_init(void) #if defined(__CC_ARM) || defined(__CLANG_ARM) /* ARM C Compiler */ extern const int FSymTab$$Base; extern const int FSymTab$$Limit; - extern const int VSymTab$$Base; - extern const int VSymTab$$Limit; finsh_system_function_init(&FSymTab$$Base, &FSymTab$$Limit); -#ifndef FINSH_USING_MSH_ONLY - finsh_system_var_init(&VSymTab$$Base, &VSymTab$$Limit); -#endif #elif defined (__ICCARM__) || defined(__ICCRX__) /* for IAR Compiler */ finsh_system_function_init(__section_begin("FSymTab"), __section_end("FSymTab")); - finsh_system_var_init(__section_begin("VSymTab"), - __section_end("VSymTab")); #elif defined (__GNUC__) || defined(__TI_COMPILER_VERSION__) /* GNU GCC Compiler and TI CCS */ extern const int __fsymtab_start; extern const int __fsymtab_end; - extern const int __vsymtab_start; - extern const int __vsymtab_end; finsh_system_function_init(&__fsymtab_start, &__fsymtab_end); - finsh_system_var_init(&__vsymtab_start, &__vsymtab_end); #elif defined(__ADSPBLACKFIN__) /* for VisualDSP++ Compiler */ finsh_system_function_init(&__fsymtab_start, &__fsymtab_end); - finsh_system_var_init(&__vsymtab_start, &__vsymtab_end); #elif defined(_MSC_VER) unsigned int *ptr_begin, *ptr_end; - + if(shell) { rt_kprintf("finsh shell already init.\n"); @@ -893,5 +770,4 @@ int finsh_system_init(void) } INIT_APP_EXPORT(finsh_system_init); -#endif /* RT_USING_FINSH */ - +#endif /* RT_USING_MSH */ diff --git a/components/finsh/shell.h b/components/finsh/shell.h index 8f94e23e8b572ae33ce47ad093e873272271c979..0eb5e05674016f725cc443b15f785663f9c452f9 100644 --- a/components/finsh/shell.h +++ b/components/finsh/shell.h @@ -74,10 +74,6 @@ struct finsh_shell char cmd_history[FINSH_HISTORY_LINES][FINSH_CMD_SIZE]; #endif -#ifndef FINSH_USING_MSH_ONLY - struct finsh_parser parser; -#endif - char line[FINSH_CMD_SIZE + 1]; rt_uint16_t line_position; rt_uint16_t line_curpos; diff --git a/components/finsh/symbol.c b/components/finsh/symbol.c deleted file mode 100644 index 78df9fac5ce43430146e842869aa7ceafdbe5366..0000000000000000000000000000000000000000 --- a/components/finsh/symbol.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-03-22 Bernard first version - */ - -#include - -#if defined(RT_USING_FINSH) && !defined(FINSH_USING_SYMTAB) - -#include "finsh.h" - -long hello(void); -long version(void); -long list(void); -long list_thread(void); -long list_sem(void); -long list_mutex(void); -long list_fevent(void); -long list_event(void); -long list_mailbox(void); -long list_msgqueue(void); -long list_mempool(void); -long list_timer(void); - -struct finsh_syscall _syscall_table[] = -{ - {"hello", hello}, - {"version", version}, - {"list", list}, - {"list_thread", list_thread}, -#ifdef RT_USING_SEMAPHORE - {"list_sem", list_sem}, -#endif -#ifdef RT_USING_MUTEX - {"list_mutex", list_mutex}, -#endif -#ifdef RT_USING_FEVENT - {"list_fevent", list_fevent}, -#endif -#ifdef RT_USING_EVENT - {"list_event", list_event}, -#endif -#ifdef RT_USING_MAILBOX - {"list_mb", list_mailbox}, -#endif -#ifdef RT_USING_MESSAGEQUEUE - {"list_mq", list_msgqueue}, -#endif -#ifdef RT_USING_MEMPOOL - {"list_memp", list_mempool}, -#endif - {"list_timer", list_timer}, -}; -struct finsh_syscall *_syscall_table_begin = &_syscall_table[0]; -struct finsh_syscall *_syscall_table_end = &_syscall_table[sizeof(_syscall_table) / sizeof(struct finsh_syscall)]; - -struct finsh_sysvar *_sysvar_table_begin = NULL; -struct finsh_sysvar *_sysvar_table_end = NULL; - -#endif /* RT_USING_FINSH && !FINSH_USING_SYMTAB */ - diff --git a/components/libc/Kconfig b/components/libc/Kconfig index 65c8d44225ccccf8dabf72f7b3c1cc92a8333276..ae8131703d941f4d18d0a5fcf863c902dfd2df47 100644 --- a/components/libc/Kconfig +++ b/components/libc/Kconfig @@ -4,6 +4,28 @@ config RT_USING_LIBC bool "Enable libc APIs from toolchain" default y +if RT_USING_LIBC && RT_USING_LWP + choice + prompt "Select c standard library" + default RT_USING_MUSL + help + Select c standard library + + config RT_USING_NEWLIB + bool "Use libc: newlib" + + config RT_USING_MUSL + bool "Use libc: musl (libc.a/libm.a in RT-Thread)" + + endchoice +endif + +if RT_USING_MUSL + config RT_USING_MLIB + bool "Use libc: mlib" + default n +endif + config RT_USING_PTHREADS bool "Enable pthreads APIs" default n @@ -25,10 +47,6 @@ if RT_USING_LIBC && RT_USING_DFS bool "Enable mmap() API" default n - config RT_USING_POSIX_TERMIOS - bool "Enable termios APIs" - default n - config RT_USING_POSIX_GETLINE bool "Enable getline()/getdelim() APIs" default n @@ -36,6 +54,15 @@ if RT_USING_LIBC && RT_USING_DFS config RT_USING_POSIX_AIO bool "Enable AIO" default n + + config RT_POSIX_AIO_THREAD_STACK_SIZE + int "Set posix aio thread stack size" + default 2048 + depends on RT_USING_POSIX_AIO + + config RT_USING_POSIX_CLOCKTIME + bool "Enable POSIX clock_time APIs" + default n endif endif diff --git a/components/libc/aio/posix_aio.c b/components/libc/aio/posix_aio.c index 3eb7634495ed1b22eb30d5abe36e5856c5a377fb..d7a0bac6d7d006febaeedc1be5f1fbd5075f57cb 100644 --- a/components/libc/aio/posix_aio.c +++ b/components/libc/aio/posix_aio.c @@ -19,6 +19,10 @@ #include "posix_aio.h" +#ifndef RT_POSIX_AIO_THREAD_STACK_SIZE +#define RT_POSIX_AIO_THREAD_STACK_SIZE 2048 +#endif + struct rt_workqueue* aio_queue = NULL; /** @@ -457,7 +461,7 @@ int lio_listio(int mode, struct aiocb * const list[], int nent, int aio_system_init(void) { - aio_queue = rt_workqueue_create("aio", 2048, RT_THREAD_PRIORITY_MAX/2); + aio_queue = rt_workqueue_create("aio", RT_POSIX_AIO_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX / 2); RT_ASSERT(aio_queue != NULL); return 0; diff --git a/components/libc/compilers/common/SConscript b/components/libc/compilers/common/SConscript index 2407301405ed4e719c1e87665d60877473405bcd..96fd5ad9d335a4bdedefe5c266713f63ed02e76a 100644 --- a/components/libc/compilers/common/SConscript +++ b/components/libc/compilers/common/SConscript @@ -1,22 +1,25 @@ from building import * -Import('rtconfig') - src = [] cwd = GetCurrentDir() group = [] CPPPATH = [cwd] +CPPDEFINES = [] if GetDepend('RT_USING_LIBC'): - src += Glob('*.c') + src += Glob('*.c') else: - if GetDepend('RT_LIBC_USING_TIME') and not GetDepend('RT_USING_MINILIBC'): - src += ['time.c'] + if GetDepend('RT_LIBC_USING_TIME') and not GetDepend('RT_USING_MINILIBC'): + src += ['time.c'] if GetDepend('RT_USING_POSIX') == False: - SrcRemove(src, ['unistd.c']) + SrcRemove(src, ['unistd.c']) + +if GetDepend('RT_USING_MUSL'): + SrcRemove(src, ['time.c']) + CPPDEFINES = ['_TIMEVAL_DEFINED'] -if not GetDepend('RT_USING_MINILIBC') and (GetDepend('RT_USING_LIBC') or GetDepend('RT_LIBC_USING_TIME')): - group = DefineGroup('libc', src, depend = [''], CPPPATH = CPPPATH) +if not GetDepend('RT_USING_MINILIBC') and not GetDepend('RT_USING_MUSL') and (GetDepend('RT_USING_LIBC') or GetDepend('RT_LIBC_USING_TIME')): + group = DefineGroup('libc', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/compilers/minilibc/SConscript b/components/libc/compilers/minilibc/SConscript index dec657028fe2b9795579d72a8c491fcb5d1520d4..9e1ab5860bdfcefd3c17547216df4795a64bab43 100644 --- a/components/libc/compilers/minilibc/SConscript +++ b/components/libc/compilers/minilibc/SConscript @@ -1,14 +1,14 @@ from building import * Import('rtconfig') -src = Glob('*.c') + Glob('*.cpp') -cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +cwd = GetCurrentDir() group = [] CPPPATH = [cwd] CPPDEFINES = ['RT_USING_MINILIBC'] -if rtconfig.PLATFORM == 'gcc' and rtconfig.ARCH != 'sim' and not GetDepend('RT_USING_LIBC') and GetDepend('RT_USING_MINILIBC'): +if rtconfig.PLATFORM == 'gcc' and not GetDepend('RT_USING_LIBC') and rtconfig.ARCH != 'sim': group = DefineGroup('libc', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) diff --git a/components/libc/compilers/musl/.gitignore b/components/libc/compilers/musl/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..0a9ce4f3e2c93ab435bf2a27c80d2cbb2a764886 --- /dev/null +++ b/components/libc/compilers/musl/.gitignore @@ -0,0 +1 @@ +libc diff --git a/components/libc/compilers/musl/SConscript b/components/libc/compilers/musl/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c9ede8d4f49fd5f7f1d153b43dfa548b2af640a1 --- /dev/null +++ b/components/libc/compilers/musl/SConscript @@ -0,0 +1,26 @@ +import os +from building import * +Import('rtconfig') + +src = Glob('*.c') +cwd = GetCurrentDir() +group = [] + +if rtconfig.PLATFORM == 'gcc' and GetDepend('RT_USING_MUSL') and not GetDepend('RT_USING_MLIB'): + CPPDEFINES = ['__STDC_ISO_10646__=201206L', '_STDC_PREDEF_H'] + LIBS = ['c', 'gcc'] + + if os.path.exists(os.path.join(cwd, 'libc', 'lib', 'libc.a')): + CFLAGS = ' -nostdinc' + CPPPATH = [cwd, cwd + '/libc/include'] + LIBPATH = [cwd + '/libc/lib'] + + group = DefineGroup('musl', src, depend = ['RT_USING_LIBC', 'RT_USING_MUSL'], CFLAGS = CFLAGS, + CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LIBS = LIBS, LIBPATH = LIBPATH) + else: + CPPPATH = [cwd] + LINKFLAGS = ' --specs=kernel.specs' + group = DefineGroup('musl', src, depend = ['RT_USING_LIBC', 'RT_USING_MUSL'], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS, + CPPDEFINES = CPPDEFINES, LIBS = LIBS) + +Return('group') diff --git a/components/libc/compilers/musl/libc.c b/components/libc/compilers/musl/libc.c new file mode 100644 index 0000000000000000000000000000000000000000..561672e7ff214b45a9325e7da5fcd211a25c86ff --- /dev/null +++ b/components/libc/compilers/musl/libc.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017/10/15 bernard the first version + */ +#include +#include +#include +#include +#include + +#include "libc.h" + +int _EXFUN(putenv,(char *__string)); +extern char **__environ; + +int libc_system_init(void) +{ +#if defined(RT_USING_DFS) & defined(RT_USING_DFS_DEVFS) + +#if defined(RT_USING_CONSOLE) + rt_device_t dev_console; + + dev_console = rt_console_get_device(); + if (dev_console) + { + #if defined(RT_USING_POSIX) + libc_stdio_set_console(dev_console->parent.name, O_RDWR); + #else + libc_stdio_set_console(dev_console->parent.name, O_WRONLY); + #endif + } +#endif + + /* set PATH and HOME */ + putenv("PATH=/bin"); + putenv("HOME=/home"); +#endif + + return 0; +} +INIT_COMPONENT_EXPORT(libc_system_init); + +#ifdef RT_USING_MUSL +#if !defined(RT_USING_MLIB) +int *__errno_location(void) +{ + return _rt_errno(); +} +#endif +int *___errno_location(void) +{ + return _rt_errno(); +} + +#endif + +int env_set(int argc, char** argv) +{ + switch (argc) + { + case 1: + { + int index; + + /* show all of environment variables */ + for(index = 0; __environ[index]!=NULL; index++) + { + printf("%2d.%s\n", index, __environ[index]); + } + } + break; + case 2: + { + char *c = strchr(argv[1], '='); + if (c) + { + /* use setenv to add/update environment variable */ + *c = '\0'; + setenv(argv[1], c + 1, 1); + } + else + { + const char *value = getenv(argv[1]); + if (value) + { + printf("%s=%s\n", argv[1], value); + } + } + } + break; + default: + break; + } + + return 0; +} +MSH_CMD_EXPORT_ALIAS(env_set, set, set or show environment variable); diff --git a/components/libc/compilers/musl/libc.h b/components/libc/compilers/musl/libc.h new file mode 100644 index 0000000000000000000000000000000000000000..ab9334fe262a39bb508aa0a0980b951a327648f2 --- /dev/null +++ b/components/libc/compilers/musl/libc.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017/10/15 bernard the first version + */ +#ifndef __RTT_LIBC_H__ +#define __RTT_LIBC_H__ + +#include +#include +#include +#include + +#ifndef _EXFUN +#define _EXFUN(name, proto) name proto +#endif + +#define MILLISECOND_PER_SECOND 1000UL +#define MICROSECOND_PER_SECOND 1000000UL +#define NANOSECOND_PER_SECOND 1000000000UL + +#define MILLISECOND_PER_TICK (MILLISECOND_PER_SECOND / RT_TICK_PER_SECOND) +#define MICROSECOND_PER_TICK (MICROSECOND_PER_SECOND / RT_TICK_PER_SECOND) +#define NANOSECOND_PER_TICK (NANOSECOND_PER_SECOND / RT_TICK_PER_SECOND) + +int libc_system_init(void); +int libc_stdio_set_console(const char* device_name, int mode); +int libc_stdio_get_console(void); + +/* some time related function */ +int libc_set_time(const struct timespec *time); +int libc_get_time(struct timespec *time); +int libc_time_to_tick(const struct timespec *time); + +#endif diff --git a/components/finsh/finsh_error.h b/components/libc/compilers/musl/mem.c similarity index 35% rename from components/finsh/finsh_error.h rename to components/libc/compilers/musl/mem.c index 614e02a350a7621929a08dd797a37960cd5740ed..abc7a47b7a36ed9f812f14d56bd9de587a586dbe 100644 --- a/components/finsh/finsh_error.h +++ b/components/libc/compilers/musl/mem.c @@ -5,19 +5,26 @@ * * Change Logs: * Date Author Notes - * 2010-03-22 Bernard first version + * 2020/10/7 bernard the first version */ -#ifndef __FINSH_ERROR_H__ -#define __FINSH_ERROR_H__ +#include -#include +void *malloc(size_t n) +{ + return rt_malloc(n); +} -int finsh_error_init(void); +void *calloc(size_t m, size_t n) +{ + return rt_calloc(m, n); +} -/* get error number */ -uint8_t finsh_errno(void); +void *realloc(void *p, size_t n) +{ + return rt_realloc(p, n); +} -int finsh_error_set(uint8_t type); -const char* finsh_error_string(uint8_t type); - -#endif +void free(void *p) +{ + rt_free(p); +} diff --git a/components/libc/compilers/musl/stdio.c b/components/libc/compilers/musl/stdio.c new file mode 100644 index 0000000000000000000000000000000000000000..7b77ca9cf4c81b8d33d7e5bbd87983d6606c84bc --- /dev/null +++ b/components/libc/compilers/musl/stdio.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017/10/15 bernard the first version + */ +#include +#include + +#include +#include "libc.h" + +#define STDIO_DEVICE_NAME_MAX 32 + +int _EXFUN(fileno, (FILE *)); + +static FILE* std_console = NULL; +int sys_dup2(int oldfd, int new); + +int libc_stdio_set_console(const char* device_name, int mode) +{ + FILE *fp; + char name[STDIO_DEVICE_NAME_MAX]; + char *file_mode; + + snprintf(name, sizeof(name) - 1, "/dev/%s", device_name); + name[STDIO_DEVICE_NAME_MAX - 1] = '\0'; + + if (mode == O_RDWR) file_mode = "r+"; + else if (mode == O_WRONLY) file_mode = "wb"; + else file_mode = "rb"; + + fp = fopen(name, file_mode); + if (fp) + { + setvbuf(fp, NULL, _IONBF, 0); + + if (std_console) + { + fclose(std_console); + std_console = NULL; + } + std_console = fp; + } + + if (std_console) + { + int fd = fileno(std_console); + + /* set fd (0, 1, 2) */ + sys_dup2(fd, 0); + sys_dup2(fd, 1); + sys_dup2(fd, 2); + return fd; + } + + return -1; +} + +int libc_stdio_get_console(void) +{ + int ret = -1; + if (std_console) + { + ret = fileno(std_console); + } + + return ret; +} diff --git a/components/libc/compilers/musl/time.c b/components/libc/compilers/musl/time.c new file mode 100644 index 0000000000000000000000000000000000000000..5a4e89f50f6597421b978495d1d6daf3c15c6091 --- /dev/null +++ b/components/libc/compilers/musl/time.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#include +#include + +#ifdef RT_USING_DEVICE +int gettimeofday(struct timeval *tp, void *ignore) +{ + time_t time; + rt_device_t device; + + device = rt_device_find("rtc"); + RT_ASSERT(device != RT_NULL); + + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); + if (tp != RT_NULL) + { + tp->tv_sec = time; + tp->tv_usec = 0; + } + + return time; +} +#endif + +time_t time(time_t *t) +{ + time_t time_now = 0; + +#ifdef RT_USING_RTC + static rt_device_t device = RT_NULL; + + /* optimization: find rtc device only first. */ + if (device == RT_NULL) + { + device = rt_device_find("rtc"); + } + + /* read timestamp from RTC device. */ + if (device != RT_NULL) + { + if (rt_device_open(device, 0) == RT_EOK) + { + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time_now); + rt_device_close(device); + } + } +#endif /* RT_USING_RTC */ + + /* if t is not NULL, write timestamp to *t */ + if (t != RT_NULL) + { + *t = time_now; + } + + return time_now; +} + +RT_WEAK clock_t clock(void) +{ + return rt_tick_get(); +} diff --git a/components/libc/compilers/newlib/SConscript b/components/libc/compilers/newlib/SConscript index 06e5faad098bbc2fe25a8109b9345ac36ead8172..38d87f5e650b0d1b2cc04b2204b19131b1524056 100644 --- a/components/libc/compilers/newlib/SConscript +++ b/components/libc/compilers/newlib/SConscript @@ -5,8 +5,8 @@ src = Glob('*.c') cwd = GetCurrentDir() group = [] -CPPPATH = [cwd] -CPPDEFINES = ['RT_USING_NEWLIB'] +CPPDEFINES = [] +CPPPATH = [] # link with libc and libm: # libm is a frequently used lib. Newlib is compiled with -ffunction-sections in @@ -14,8 +14,18 @@ CPPDEFINES = ['RT_USING_NEWLIB'] # been referenced. So setting this won't result in bigger text size. LIBS = ['c', 'm'] -if rtconfig.PLATFORM == 'gcc': - group = DefineGroup('newlib', src, depend = ['RT_USING_LIBC'], +if rtconfig.PLATFORM == 'gcc' and GetDepend('RT_USING_LIBC'): + if GetDepend('RT_USING_MUSL'): + # musl libc is used as a software library. + src = [] + elif GetDepend('RT_USING_NEWLIB'): + # RT_USING_NEWLIB is defined already + CPPPATH = [cwd] + else: + CPPPATH = [cwd] + CPPDEFINES = ['RT_USING_NEWLIB'] + + group = DefineGroup('newlib', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LIBS = LIBS) Return('group') diff --git a/components/libc/compilers/newlib/syscalls.c b/components/libc/compilers/newlib/syscalls.c index 228fa0d140e0ce39dbc7968b974123313a11fdc3..aac6ff1d0b8aecc50920786f830ef9a0d98b4092 100644 --- a/components/libc/compilers/newlib/syscalls.c +++ b/components/libc/compilers/newlib/syscalls.c @@ -431,7 +431,7 @@ void abort(void) rt_thread_t self = rt_thread_self(); rt_kprintf("thread:%-8.*s abort!\n", RT_NAME_MAX, self->name); - rt_thread_suspend(self); + rt_thread_suspend_with_flag(self, RT_UNINTERRUPTIBLE); rt_schedule(); } diff --git a/components/libc/libdl/dlmodule.c b/components/libc/libdl/dlmodule.c index 314cf52709f691e68f3d8f83dfab8612e64b36ea..3c513acc277eee58c54d17d7c31047d5d829267d 100644 --- a/components/libc/libdl/dlmodule.c +++ b/components/libc/libdl/dlmodule.c @@ -128,7 +128,7 @@ static void _dlmodule_exit(void) (thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_INIT) { rt_timer_stop(&(thread->thread_timer)); - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); } } } diff --git a/components/libc/time/SConscript b/components/libc/time/SConscript index 4ecd5d24bc7c784798e5e0bed1f4dbec17ad8044..7548076ab249ef69d26ccc8352c8509d56b373f3 100644 --- a/components/libc/time/SConscript +++ b/components/libc/time/SConscript @@ -7,6 +7,6 @@ src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] group = DefineGroup('pthreads', src, - depend = ['RT_USING_PTHREADS'], CPPPATH = CPPPATH) + depend = ['RT_USING_POSIX_CLOCKTIME'], CPPPATH = CPPPATH) Return('group') diff --git a/components/libc/time/clock_time.c b/components/libc/time/clock_time.c index 83b3b916ca1730936d9142fd003c58a2bfbaad7a..4a9e06ddeae4cb4a0dea045ec64b2ee762afd588 100644 --- a/components/libc/time/clock_time.c +++ b/components/libc/time/clock_time.c @@ -10,8 +10,6 @@ */ #include -#include - #include "clock_time.h" static struct timeval _timevalue; @@ -48,7 +46,7 @@ int clock_time_to_tick(const struct timespec *time) RT_ASSERT(time != RT_NULL); tick = RT_WAITING_FOREVER; - if (time != NULL) + if (time != RT_NULL) { /* get current tp */ clock_gettime(CLOCK_REALTIME, &tp); diff --git a/components/libc/time/clock_time.h b/components/libc/time/clock_time.h index 16b2306f4b2dad41879c9a4bfda0b3d192c2425f..0909d7961326bd7fa3aa2bd845ac72597b0395c9 100644 --- a/components/libc/time/clock_time.h +++ b/components/libc/time/clock_time.h @@ -45,6 +45,8 @@ int clock_getres (clockid_t clockid, struct timespec *res); int clock_gettime (clockid_t clockid, struct timespec *tp); int clock_settime (clockid_t clockid, const struct timespec *tp); +int clock_time_to_tick(const struct timespec *time); + #ifdef __cplusplus } #endif diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig index 1b37829935e70a2d6e3f9ed2019eccefdf7b4a3f..26f83ead98cd1e731ed8709eb66d3cc53679bc35 100644 --- a/components/lwp/Kconfig +++ b/components/lwp/Kconfig @@ -1,8 +1,65 @@ -config RT_USING_LWP - bool "Using light-weight process" +menuconfig RT_USING_LWP + bool "light-weight process" select RT_USING_DFS select RT_USING_LIBC - depends on ARCH_ARM_CORTEX_M || ARCH_ARM_ARM9 || ARCH_ARM_CORTEX_A + select RT_USING_POSIX_CLOCKTIME + depends on ARCH_ARM_CORTEX_M || ARCH_ARM_ARM9 || ARCH_ARM_CORTEX_A || ARCH_RISCV64 default n help The lwP is a light weight process running in user mode. + +if RT_USING_LWP + config RT_LWP_MAX_NR + int "The max number of light-weight process" + default 30 + + config LWP_TASK_STACK_SIZE + int "The lwp thread kernel stack size" + default 16384 + + config RT_CH_MSG_MAX_NR + int "The maximum number of channel messages" + default 1024 + + config LWP_CONSOLE_INPUT_BUFFER_SIZE + int "The input buffer size of lwp console device" + default 1024 + + config LWP_TID_MAX_NR + int "The maximum number of lwp thread id" + default 64 + + if ARCH_MM_MMU + config RT_LWP_SHM_MAX_NR + int "The maximum number of shared memory" + default 64 + endif + + if ARCH_MM_MPU + config RT_LWP_MPU_MAX_NR + int "The maximum number of mpu region" + default 2 + + config RT_LWP_USING_SHM + bool "Enable shared memory" + default y + endif + + config LWP_UNIX98_PTY + bool "The unix98 PTY support" + default n + + if LWP_UNIX98_PTY + config LWP_PTY_INPUT_BFSZ + int "The unix98 PTY input buffer size" + default 1024 + + config LWP_PTY_PTS_SIZE + int "The unix98 PTY device max num" + default 3 + + config LWP_PTY_USING_DEBUG + bool "The unix98 PTY debug output" + default n + endif +endif diff --git a/components/lwp/SConscript b/components/lwp/SConscript index f151f3b92e17146f34b8ce69718ec42f71452fd2..0b44b08eb3567006a5d3f440b7f7e4dc288b550c 100644 --- a/components/lwp/SConscript +++ b/components/lwp/SConscript @@ -1,19 +1,44 @@ Import('rtconfig') from building import * +import os cwd = GetCurrentDir() src = [] CPPPATH = [cwd] -support_arch = {"arm": ["cortex-m3", "cortex-m4", "cortex-m7", "arm926", "cortex-a"]} +support_arch = {"arm": ["cortex-m3", "cortex-m4", "cortex-m7", "arm926", "cortex-a"], + "aarch64":["cortex-a"], + "risc-v": ["rv64"], + "x86": ["i386"]} platform_file = {'armcc': 'rvds.S', 'gcc': 'gcc.S', 'iar': 'iar.S'} -if rtconfig.PLATFORM in platform_file.keys(): # support platforms - if rtconfig.ARCH in support_arch.keys() and rtconfig.CPU in support_arch[rtconfig.ARCH]: - # arch/arm/cortex-m7/lwp_gcc.S - asm_path = 'arch/' + rtconfig.ARCH + '/' + rtconfig.CPU + '/*_' + platform_file[rtconfig.PLATFORM] - src = Glob('*.c') + Glob(asm_path) +platform = rtconfig.PLATFORM +arch = rtconfig.ARCH +cpu = rtconfig.CPU + +# fix the cpu for risc-v +if arch == 'risc-v': + rv64 = ['virt64', 'c906'] + if cpu in rv64: + cpu = 'rv64' + +if GetDepend('LWP_UNIX98_PTY'): + # print("LWP_UNIX98_PTY") + src += Glob('unix98pty/*.c') + CPPPATH += ['unix98pty/'] + +if platform in platform_file.keys(): # support platforms + if arch in support_arch.keys() and cpu in support_arch[arch]: + asm_path = 'arch/' + arch + '/' + cpu + '/*_' + platform_file[platform] + arch_common = 'arch/' + arch + '/' + 'common/*.c' + if not GetDepend('ARCH_MM_MMU'): + excluded_files = ['ioremap.c', 'lwp_futex.c', 'lwp_mm_area.c', 'lwp_pmutex.c', 'lwp_shm.c', 'lwp_user_mm.c'] + src += [f for f in Glob('*.c') if os.path.basename(str(f)) not in excluded_files] + Glob(asm_path) + Glob(arch_common) + else: + src += Glob('*.c') + Glob(asm_path) + Glob(arch_common) + src += Glob('arch/' + arch + '/' + cpu + '/*.c') CPPPATH = [cwd] + CPPPATH += [cwd + '/arch/' + arch + '/' + cpu] group = DefineGroup('lwP', src, depend = ['RT_USING_LWP'], CPPPATH = CPPPATH) diff --git a/components/lwp/arch/aarch64/common/reloc.c b/components/lwp/arch/aarch64/common/reloc.c new file mode 100644 index 0000000000000000000000000000000000000000..2ad00c9d015245ba742d4ff94ad9235960276201 --- /dev/null +++ b/components/lwp/arch/aarch64/common/reloc.c @@ -0,0 +1,28 @@ +#include +#include +#include +#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +#define Elf_Word Elf64_Word +#define Elf_Addr Elf64_Addr +#define Elf_Half Elf64_Half +#define Elf_Ehdr Elf64_Ehdr #define Elf_Phdr Elf64_Phdr +#define Elf_Shdr Elf64_Shdr + +typedef struct +{ + Elf_Word st_name; + Elf_Addr st_value; + Elf_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf_Half st_shndx; +} Elf_sym; + +void lwp_elf_reloc(void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf_sym *dynsym) +{ +} diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_arch.c b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c new file mode 100644 index 0000000000000000000000000000000000000000..c5f4cebdb9c8d1a9e34389b1672314eb5ea1483d --- /dev/null +++ b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 Jesven first version + */ + +#include +#include + +#ifdef RT_USING_USERSPACE + +#include +#include +#include +#include +#include + +extern size_t MMUTable[]; + +int arch_user_space_init(struct rt_lwp *lwp) +{ + size_t *mmu_table; + + mmu_table = (size_t*)rt_pages_alloc(0); + if (!mmu_table) + { + return -1; + } + + lwp->end_heap = USER_HEAP_VADDR; + memset(mmu_table, 0, ARCH_PAGE_SIZE); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_table, ARCH_PAGE_SIZE); + rt_hw_mmu_map_init(&lwp->mmu_info, (void*)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, mmu_table, PV_OFFSET); + + return 0; +} + +void *arch_kernel_mmu_table_get(void) +{ + return (void*)NULL; +} + +void arch_kuser_init(rt_mmu_info *mmu_info, void *vectors) +{ +} + +void arch_user_space_vtable_free(struct rt_lwp *lwp) +{ + if (lwp && lwp->mmu_info.vtable) + { + rt_pages_free(lwp->mmu_info.vtable, 0); + } +} + +int arch_expand_user_stack(void *addr) +{ + int ret = 0; + size_t stack_addr = (size_t)addr; + + stack_addr &= ~ARCH_PAGE_MASK; + if ((stack_addr >= (size_t)USER_STACK_VSTART) && (stack_addr < (size_t)USER_STACK_VEND)) + { + void *map = lwp_map_user(lwp_self(), (void*)stack_addr, ARCH_PAGE_SIZE, 0); + + if (map || lwp_user_accessable(addr, 1)) + { + ret = 1; + } + } + return ret; +} + +#endif diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_arch.h b/components/lwp/arch/aarch64/cortex-a/lwp_arch.h new file mode 100644 index 0000000000000000000000000000000000000000..d817380570300363db2a7f76e2cbca36bcf12bcd --- /dev/null +++ b/components/lwp/arch/aarch64/cortex-a/lwp_arch.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 Jesven first version + */ + +#ifndef LWP_ARCH_H__ +#define LWP_ARCH_H__ + +#include + +#ifdef RT_USING_USERSPACE + +#define USER_VADDR_TOP 0x0001000000000000UL +#define USER_HEAP_VEND 0x0000ffffB0000000UL +#define USER_HEAP_VADDR 0x0000ffff80000000UL +#define USER_STACK_VSTART 0x0000ffff70000000UL +#define USER_STACK_VEND USER_HEAP_VADDR +#define LDSO_LOAD_VADDR 0x60000000UL +#define USER_VADDR_START 0x00200000UL +#define USER_LOAD_VADDR USER_VADDR_START + +#ifdef __cplusplus +extern "C" { +#endif + +int arch_user_space_init(struct rt_lwp *lwp); +void arch_user_space_vtable_free(struct rt_lwp *lwp); +void *arch_kernel_mmu_table_get(void); +void arch_kuser_init(rt_mmu_info *mmu_info, void *vectors); +int arch_expand_user_stack(void *addr); + +unsigned long ffz(unsigned long x); + +rt_inline void icache_invalid_all(void) +{ + asm volatile ("ic ialluis\n\tisb sy":::"memory"); +} + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /*LWP_ARCH_H__*/ diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..c06c2980495bd5a1bd76e60456ae348f5125f296 --- /dev/null +++ b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S @@ -0,0 +1,674 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 Jesven first version + */ + +#include "rtconfig.h" + +#include "asm-fpu.h" + +/********************* + * SPSR BIT * + *********************/ + +#define SPSR_Mode(v) ((v) << 0) +#define SPSR_A64 (0 << 4) +#define SPSR_RESEVRED_5 (0 << 5) +#define SPSR_FIQ_MASKED(v) ((v) << 6) +#define SPSR_IRQ_MASKED(v) ((v) << 7) +#define SPSR_SERROR_MASKED(v) ((v) << 8) +#define SPSR_D_MASKED(v) ((v) << 9) +#define SPSR_RESEVRED_10_19 (0 << 10) +#define SPSR_IL(v) ((v) << 20) +#define SPSR_SS(v) ((v) << 21) +#define SPSR_RESEVRED_22_27 (0 << 22) +#define SPSR_V(v) ((v) << 28) +#define SPSR_C(v) ((v) << 29) +#define SPSR_Z(v) ((v) << 30) +#define SPSR_N(v) ((v) << 31) + +/********************* + * CONTEXT_OFFSET * + *********************/ + +#define CONTEXT_OFFSET_ELR_EL1 0x0 +#define CONTEXT_OFFSET_SPSR_EL1 0x8 +#define CONTEXT_OFFSET_SP_EL0 0x10 +#define CONTEXT_OFFSET_X30 0x18 +#define CONTEXT_OFFSET_FPCR 0x20 +#define CONTEXT_OFFSET_FPSR 0x28 +#define CONTEXT_OFFSET_X28 0x30 +#define CONTEXT_OFFSET_X29 0x38 +#define CONTEXT_OFFSET_X26 0x40 +#define CONTEXT_OFFSET_X27 0x48 +#define CONTEXT_OFFSET_X24 0x50 +#define CONTEXT_OFFSET_X25 0x58 +#define CONTEXT_OFFSET_X22 0x60 +#define CONTEXT_OFFSET_X23 0x68 +#define CONTEXT_OFFSET_X20 0x70 +#define CONTEXT_OFFSET_X21 0x78 +#define CONTEXT_OFFSET_X18 0x80 +#define CONTEXT_OFFSET_X19 0x88 +#define CONTEXT_OFFSET_X16 0x90 +#define CONTEXT_OFFSET_X17 0x98 +#define CONTEXT_OFFSET_X14 0xa0 +#define CONTEXT_OFFSET_X15 0xa8 +#define CONTEXT_OFFSET_X12 0xb0 +#define CONTEXT_OFFSET_X13 0xb8 +#define CONTEXT_OFFSET_X10 0xc0 +#define CONTEXT_OFFSET_X11 0xc8 +#define CONTEXT_OFFSET_X8 0xd0 +#define CONTEXT_OFFSET_X9 0xd8 +#define CONTEXT_OFFSET_X6 0xe0 +#define CONTEXT_OFFSET_X7 0xe8 +#define CONTEXT_OFFSET_X4 0xf0 +#define CONTEXT_OFFSET_X5 0xf8 +#define CONTEXT_OFFSET_X2 0x100 +#define CONTEXT_OFFSET_X3 0x108 +#define CONTEXT_OFFSET_X0 0x110 +#define CONTEXT_OFFSET_X1 0x118 + +#define CONTEXT_OFFSET_Q15 0x120 +#define CONTEXT_OFFSET_Q14 0x130 +#define CONTEXT_OFFSET_Q13 0x140 +#define CONTEXT_OFFSET_Q12 0x150 +#define CONTEXT_OFFSET_Q11 0x160 +#define CONTEXT_OFFSET_Q10 0x170 +#define CONTEXT_OFFSET_Q9 0x180 +#define CONTEXT_OFFSET_Q8 0x190 +#define CONTEXT_OFFSET_Q7 0x1a0 +#define CONTEXT_OFFSET_Q6 0x1b0 +#define CONTEXT_OFFSET_Q5 0x1c0 +#define CONTEXT_OFFSET_Q4 0x1d0 +#define CONTEXT_OFFSET_Q3 0x1e0 +#define CONTEXT_OFFSET_Q2 0x1f0 +#define CONTEXT_OFFSET_Q1 0x200 +#define CONTEXT_OFFSET_Q0 0x210 + +#define CONTEXT_FPU_SIZE 0x100 +#define CONTEXT_SIZE 0x220 + +/**************************************************/ + +.text + +/* + * void lwp_user_entry(args, text, ustack, kstack); + */ +.global lwp_user_entry +.type lwp_user_entry, % function +lwp_user_entry: + mov sp, x3 + mov x4, #(SPSR_Mode(0) | SPSR_A64) + mov x3, x2 ;/* user stack top */ + msr daifset, #3 + dsb sy + mrs x30, sp_el0 + msr spsr_el1, x4 + msr elr_el1, x1 + eret + +/* + * void lwp_user_thread_entry(args, text, ustack, kstack); + */ +.global lwp_user_thread_entry +.type lwp_user_thread_entry, % function +lwp_user_thread_entry: + sub x4, x2, #0x10 + adr x2, lwp_thread_return + ldr x5, [x2] + str x5, [x4] + ldr x5, [x2, #4] + str x5, [x4, #4] + ldr x5, [x2, #8] + str x5, [x4, #8] + + mov x5, x4 + dc cvau, x5 + add x5, x5, #8 + dc cvau, x5 + dsb sy + ic ialluis + dsb sy + + msr sp_el0, x4 + + mov sp, x3 + mov x4, #(SPSR_Mode(0) | SPSR_A64) + msr daifset, #3 + dsb sy + mrs x30, sp_el0 + msr spsr_el1, x4 + msr elr_el1, x1 + eret + +/* +void lwp_set_thread_context(void *exit_addr, void *new_thread_stack, void *user_stack, void **thread_sp); +*/ +.global lwp_set_thread_context +lwp_set_thread_context: + sub x1, x1, #CONTEXT_SIZE + str x2, [x1, #CONTEXT_OFFSET_SP_EL0] + sub x1, x1, #CONTEXT_SIZE + str xzr, [x1, #CONTEXT_OFFSET_X0] /* new thread return 0 */ + mov x4, #((3 << 6) | 0x4 | 0x1) /* el1h, disable interrupt */ + str x4, [x1, #CONTEXT_OFFSET_SPSR_EL1] + str x0, [x1, #CONTEXT_OFFSET_ELR_EL1] + str x1, [x3] + ret + +.global lwp_get_user_sp +lwp_get_user_sp: + mrs x0, sp_el0 + ret + +.global sys_fork +.global sys_vfork +.global sys_fork_exit +sys_fork: +sys_vfork: + bl _sys_fork +sys_fork_exit: + b svc_exit + +.global sys_clone +.global sys_clone_exit +sys_clone: + bl _sys_clone +sys_clone_exit: + b svc_exit + +/* +void lwp_exec_user(void *args, void *kernel_stack, void *user_entry) +*/ +.global lwp_exec_user +lwp_exec_user: + mov sp, x1 + mov x4, #(SPSR_Mode(0) | SPSR_A64) + ldr x3, =0x0000ffff80000000 + msr daifset, #3 + msr spsr_el1, x4 + msr elr_el1, x2 + eret + +/* + * void SVC_Handler(regs); + */ +.global SVC_Handler +.type SVC_Handler, % function +SVC_Handler: + /* x0 is initial sp */ + mov sp, x0 + + msr daifclr, #3 /* enable interrupt */ + + bl rt_thread_self + bl lwp_user_setting_save + + ldp x8, x9, [sp, #(CONTEXT_OFFSET_X8)] + and x0, x8, #0xf000 + cmp x0, #0xe000 + beq lwp_signal_quit + +#ifdef RT_USING_GDBSERVER + cmp x0, #0xf000 + beq ret_from_user +#endif + + uxtb x0, w8 + bl lwp_get_sys_api + cmp x0, xzr + mov x30, x0 + beq svc_exit + ldp x0, x1, [sp, #(CONTEXT_OFFSET_X0)] + ldp x2, x3, [sp, #(CONTEXT_OFFSET_X2)] + ldp x4, x5, [sp, #(CONTEXT_OFFSET_X4)] + ldp x6, x7, [sp, #(CONTEXT_OFFSET_X6)] + blr x30 +svc_exit: + msr daifset, #3 + + ldp x2, x3, [sp], #0x10 /* SPSR and ELR. */ + msr spsr_el1, x3 + msr elr_el1, x2 + + ldp x29, x30, [sp], #0x10 + msr sp_el0, x29 + ldp x28, x29, [sp], #0x10 + msr fpcr, x28 + msr fpsr, x29 + ldp x28, x29, [sp], #0x10 + ldp x26, x27, [sp], #0x10 + ldp x24, x25, [sp], #0x10 + ldp x22, x23, [sp], #0x10 + ldp x20, x21, [sp], #0x10 + ldp x18, x19, [sp], #0x10 + ldp x16, x17, [sp], #0x10 + ldp x14, x15, [sp], #0x10 + ldp x12, x13, [sp], #0x10 + ldp x10, x11, [sp], #0x10 + ldp x8, x9, [sp], #0x10 + add sp, sp, #0x40 + RESTORE_FPU sp + +.global ret_to_user +ret_to_user: + SAVE_FPU sp + stp x0, x1, [sp, #-0x10]! + stp x2, x3, [sp, #-0x10]! + stp x4, x5, [sp, #-0x10]! + stp x6, x7, [sp, #-0x10]! + stp x8, x9, [sp, #-0x10]! + stp x10, x11, [sp, #-0x10]! + stp x12, x13, [sp, #-0x10]! + stp x14, x15, [sp, #-0x10]! + stp x16, x17, [sp, #-0x10]! + stp x18, x19, [sp, #-0x10]! + stp x20, x21, [sp, #-0x10]! + stp x22, x23, [sp, #-0x10]! + stp x24, x25, [sp, #-0x10]! + stp x26, x27, [sp, #-0x10]! + stp x28, x29, [sp, #-0x10]! + + mrs x0, fpcr + mrs x1, fpsr + stp x0, x1, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + +#ifdef RT_USING_GDBSERVER + bl thread_is_in_debug + mov x1, #(1 << 21) + mrs x2, spsr_el1 + cbz w0, 1f + orr x2, x2, x1 + b 2f +1: + bic x2, x2, x1 +2: + msr spsr_el1, x2 +#endif + + bl lwp_signal_check + cmp x0, xzr + + ldp x29, x30, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + msr fpcr, x0 + msr fpsr, x1 + + ldp x28, x29, [sp], #0x10 + ldp x26, x27, [sp], #0x10 + ldp x24, x25, [sp], #0x10 + ldp x22, x23, [sp], #0x10 + ldp x20, x21, [sp], #0x10 + ldp x18, x19, [sp], #0x10 + ldp x16, x17, [sp], #0x10 + ldp x14, x15, [sp], #0x10 + ldp x12, x13, [sp], #0x10 + ldp x10, x11, [sp], #0x10 + ldp x8, x9, [sp], #0x10 + ldp x6, x7, [sp], #0x10 + ldp x4, x5, [sp], #0x10 + ldp x2, x3, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + RESTORE_FPU sp + + bne user_do_signal + +#ifdef RT_USING_GDBSERVER + SAVE_FPU sp + stp x0, x1, [sp, #-0x10]! + stp x2, x3, [sp, #-0x10]! + stp x4, x5, [sp, #-0x10]! + stp x6, x7, [sp, #-0x10]! + stp x8, x9, [sp, #-0x10]! + stp x10, x11, [sp, #-0x10]! + stp x12, x13, [sp, #-0x10]! + stp x14, x15, [sp, #-0x10]! + stp x16, x17, [sp, #-0x10]! + stp x18, x19, [sp, #-0x10]! + stp x20, x21, [sp, #-0x10]! + stp x22, x23, [sp, #-0x10]! + stp x24, x25, [sp, #-0x10]! + stp x26, x27, [sp, #-0x10]! + stp x28, x29, [sp, #-0x10]! + mrs x0, fpcr + mrs x1, fpsr + stp x0, x1, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mrs x0, elr_el1 + bl lwp_check_debug_attach_req + ldp x29, x30, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + msr fpcr, x0 + msr fpsr, x1 + ldp x28, x29, [sp], #0x10 + ldp x26, x27, [sp], #0x10 + ldp x24, x25, [sp], #0x10 + ldp x22, x23, [sp], #0x10 + ldp x20, x21, [sp], #0x10 + ldp x18, x19, [sp], #0x10 + ldp x16, x17, [sp], #0x10 + ldp x14, x15, [sp], #0x10 + ldp x12, x13, [sp], #0x10 + ldp x10, x11, [sp], #0x10 + ldp x8, x9, [sp], #0x10 + ldp x6, x7, [sp], #0x10 + ldp x4, x5, [sp], #0x10 + ldp x2, x3, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + RESTORE_FPU sp +#endif + eret + +.global lwp_check_exit +lwp_check_exit: + SAVE_FPU sp + stp x0, x1, [sp, #-0x10]! + stp x2, x3, [sp, #-0x10]! + stp x4, x5, [sp, #-0x10]! + stp x6, x7, [sp, #-0x10]! + stp x10, x11, [sp, #-0x10]! + stp x12, x13, [sp, #-0x10]! + stp x14, x15, [sp, #-0x10]! + stp x16, x17, [sp, #-0x10]! + stp x18, x19, [sp, #-0x10]! + stp x20, x21, [sp, #-0x10]! + stp x22, x23, [sp, #-0x10]! + stp x24, x25, [sp, #-0x10]! + stp x26, x27, [sp, #-0x10]! + stp x28, x29, [sp, #-0x10]! + mrs x0, fpcr + mrs x1, fpsr + stp x0, x1, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + + bl lwp_check_exit_request + cmp x0, xzr + bne 1f + ldp x29, x30, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + msr fpcr, x0 + msr fpsr, x1 + ldp x28, x29, [sp], #0x10 + ldp x26, x27, [sp], #0x10 + ldp x24, x25, [sp], #0x10 + ldp x22, x23, [sp], #0x10 + ldp x20, x21, [sp], #0x10 + ldp x18, x19, [sp], #0x10 + ldp x16, x17, [sp], #0x10 + ldp x14, x15, [sp], #0x10 + ldp x12, x13, [sp], #0x10 + ldp x10, x11, [sp], #0x10 + ldp x6, x7, [sp], #0x10 + ldp x4, x5, [sp], #0x10 + ldp x2, x3, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + RESTORE_FPU sp + + br x30 +1: + mov x0, xzr + b sys_exit + +/* +struct rt_hw_exp_stack +{ + unsigned long pc; 0 + unsigned long cpsr; + unsigned long sp_el0; 0x10 + unsigned long x30; + unsigned long fpcr; 0x20 + unsigned long fpsr; + unsigned long x28; 0x30 + unsigned long x29; + unsigned long x26; 0x40 + unsigned long x27; + unsigned long x24; 0x50 + unsigned long x25; + unsigned long x22; 0x60 + unsigned long x23; + unsigned long x20; 0x70 + unsigned long x21; + unsigned long x18; 0x80 + unsigned long x19; + unsigned long x16; 0x90 + unsigned long x17; + unsigned long x14; 0xa0 + unsigned long x15; + unsigned long x12; 0xb0 + unsigned long x13; + unsigned long x10; 0xc0 + unsigned long x11; + unsigned long x8; 0xd0 + unsigned long x9; + unsigned long x6; 0xe0 + unsigned long x7; + unsigned long x4; 0xf0 + unsigned long x5; + unsigned long x2; 0x100 + unsigned long x3; + unsigned long x0; 0x110 + unsigned long x1; + + unsigned long long fpu[16]; 0x120 + 0x220 = 0x120 + 0x10 * 0x10 +}; +*/ +#ifdef RT_USING_GDBSERVER +.global lwp_check_debug +lwp_check_debug: + SAVE_FPU sp + stp x0, x1, [sp, #-0x10]! + stp x2, x3, [sp, #-0x10]! + stp x4, x5, [sp, #-0x10]! + stp x6, x7, [sp, #-0x10]! + stp x10, x11, [sp, #-0x10]! + stp x12, x13, [sp, #-0x10]! + stp x14, x15, [sp, #-0x10]! + stp x16, x17, [sp, #-0x10]! + stp x18, x19, [sp, #-0x10]! + stp x20, x21, [sp, #-0x10]! + stp x22, x23, [sp, #-0x10]! + stp x24, x25, [sp, #-0x10]! + stp x26, x27, [sp, #-0x10]! + stp x28, x29, [sp, #-0x10]! + + mrs x0, fpcr + mrs x1, fpsr + stp x0, x1, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + + bl lwp_check_debug_suspend + cmp w0, wzr + beq lwp_check_debug_quit + + mrs x2, sp_el0 + sub x2, x2, #8 + mov x3, x2 + msr sp_el0, x2 + ldr x0, =lwp_debugreturn + ldr w1, [x0] + str w1, [x2] + ldr w1, [x0, #4] + str w1, [x2, #4] + + dc cvau, x2 + add x2, x2, #4 + dc cvau, x2 + + dsb sy + isb sy + + ic ialluis + isb sy + + msr elr_el1, x3 /* lwp_debugreturn */ + mrs x1, spsr_el1 + stp x0, x1, [sp, #-0x10]! + mov x1, #(SPSR_Mode(0) | SPSR_A64) + msr spsr_el1, x1 + eret +ret_from_user: + /* sp_el0 += 8 for drop ins lwp_debugreturn */ + mrs x0, sp_el0 + add x0, x0, #8 + msr sp_el0, x0 + /* now is el1, sp is pos(empty) - sizeof(context) */ + mov x0, sp + add x0, x0, #0x220 /* sizeof(context) */ + mov sp, x0 + ldp x0, x1, [sp], #0x10 /* x0 is origin spsr_el1 */ + msr spsr_el1, x0 +lwp_check_debug_quit: + ldp x29, x30, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + msr fpcr, x0 + msr fpsr, x1 + ldp x28, x29, [sp], #0x10 + ldp x26, x27, [sp], #0x10 + ldp x24, x25, [sp], #0x10 + ldp x22, x23, [sp], #0x10 + ldp x20, x21, [sp], #0x10 + ldp x18, x19, [sp], #0x10 + ldp x16, x17, [sp], #0x10 + ldp x14, x15, [sp], #0x10 + ldp x12, x13, [sp], #0x10 + ldp x10, x11, [sp], #0x10 + ldp x6, x7, [sp], #0x10 + ldp x4, x5, [sp], #0x10 + ldp x2, x3, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + RESTORE_FPU sp + ret +#endif + +lwp_signal_quit: + msr daifset, #3 +/* + drop stack data +*/ + add sp, sp, #CONTEXT_SIZE + bl lwp_signal_restore + /* x0 is user_ctx : ori sp, pc, cpsr */ + ldr x1, [x0] + ldr x2, [x0, #8] + ldr x3, [x0, #16] + msr spsr_el1, x3 + msr elr_el1, x2 + add x1, x1, #16 + msr sp_el0, x1 + + msr spsel, #0 + + ldp x29, x30, [sp], #0x10 + ldp x28, x29, [sp], #0x10 + msr fpcr, x28 + msr fpsr, x29 + ldp x28, x29, [sp], #0x10 + ldp x26, x27, [sp], #0x10 + ldp x24, x25, [sp], #0x10 + ldp x22, x23, [sp], #0x10 + ldp x20, x21, [sp], #0x10 + ldp x18, x19, [sp], #0x10 + ldp x16, x17, [sp], #0x10 + ldp x14, x15, [sp], #0x10 + ldp x12, x13, [sp], #0x10 + ldp x10, x11, [sp], #0x10 + ldp x8, x9, [sp], #0x10 + ldp x6, x7, [sp], #0x10 + ldp x4, x5, [sp], #0x10 + ldp x2, x3, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + RESTORE_FPU sp + + msr spsel, #1 + + b ret_to_user + +user_do_signal: + msr spsel, #0 + SAVE_FPU sp + stp x0, x1, [sp, #-0x10]! + stp x2, x3, [sp, #-0x10]! + stp x4, x5, [sp, #-0x10]! + stp x6, x7, [sp, #-0x10]! + stp x8, x9, [sp, #-0x10]! + stp x10, x11, [sp, #-0x10]! + stp x12, x13, [sp, #-0x10]! + stp x14, x15, [sp, #-0x10]! + stp x16, x17, [sp, #-0x10]! + stp x18, x19, [sp, #-0x10]! + stp x20, x21, [sp, #-0x10]! + stp x22, x23, [sp, #-0x10]! + stp x24, x25, [sp, #-0x10]! + stp x26, x27, [sp, #-0x10]! + stp x28, x29, [sp, #-0x10]! + mrs x28, fpcr + mrs x29, fpsr + stp x28, x29, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + + sub sp, sp, #0x10 + adr x0, lwp_sigreturn + ldr w1, [x0] + str w1, [sp] + ldr w1, [x0, #4] + str w1, [sp, #4] + + mov x20, sp /* lwp_sigreturn */ + mov x0, sp + + dc cvau, x0 + dsb sy + ic ialluis + dsb sy + + msr spsel, #1 + + mrs x1, elr_el1 + mrs x2, spsr_el1 + bl lwp_signal_backup + /* x0 is signal */ + mov x19, x0 + bl lwp_sighandler_get + adds x1, x0, xzr + mov x0, x19 + bne 1f + mov x1, x20 +1: + msr elr_el1, x1 + mov x30, x20 + eret + +#ifdef RT_USING_GDBSERVER +lwp_debugreturn: + mov x9, 0xf000 + svc #0 +#endif + +lwp_sigreturn: + mov x8, #0xe000 + svc #0 + +lwp_thread_return: + mov x0, xzr + mov x8, #0x01 + svc #0 + +.globl rt_cpu_get_thread_idr +rt_cpu_get_thread_idr: + mrs x0, tpidr_el0 + ret + +.global lwp_set_thread_area +lwp_set_thread_area: +.globl rt_cpu_set_thread_idr +rt_cpu_set_thread_idr: + msr tpidr_el0, x0 + ret diff --git a/components/lwp/arch/arm/arm926/lwp_gcc.S b/components/lwp/arch/arm/arm926/lwp_gcc.S deleted file mode 100644 index 2a8ce492ebe20ccebd84e15b0b25c843c7eb9d67..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/arm926/lwp_gcc.S +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-10 Jesven first version - */ - -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_MON 0x16 -#define Mode_ABT 0x17 -#define Mode_UDF 0x1B -#define Mode_SYS 0x1F - -#define A_Bit 0x100 -#define I_Bit 0x80 @; when I bit is set, IRQ is disabled -#define F_Bit 0x40 @; when F bit is set, FIQ is disabled -#define T_Bit 0x20 - -.cpu arm9 -.syntax unified -.text - -/* - * void lwp_user_entry(args, text, data); - */ -.global lwp_user_entry -.type lwp_user_entry, % function -lwp_user_entry: - mrs r9, cpsr - mov r8, r9 - bic r9, #0x1f - orr r9, #Mode_USR - - orr r8, #I_Bit - msr cpsr_c, r8 - - msr spsr, r9 - - /* set data address. */ - mov r9, r2 - movs pc, r1 - -/* - * void SVC_Handler(void); - */ -.global SVC_Handler -.type SVC_Handler, % function -SVC_Handler: - push {lr} - mrs lr, spsr - push {r4, r5, lr} - - mrs r4, cpsr - bic r4, #I_Bit - msr cpsr_c, r4 - - push {r0 - r3, r12} - and r0, r7, #0xff - bl lwp_get_sys_api - cmp r0, #0 /* r0 = api */ - mov r4, r0 - pop {r0 - r3, r12} - beq svc_exit - ldr lr, = svc_exit - bx r4 - -svc_exit: - mrs r4, cpsr - orr r4, #I_Bit - msr cpsr_c, r4 - - pop {r4, r5, lr} - msr spsr_cxsf, lr - pop {lr} - movs pc, lr diff --git a/components/lwp/arch/arm/common/reloc.c b/components/lwp/arch/arm/common/reloc.c new file mode 100644 index 0000000000000000000000000000000000000000..d3fae5fc1327f0323deb34b5598854554a966907 --- /dev/null +++ b/components/lwp/arch/arm/common/reloc.c @@ -0,0 +1,120 @@ +#include +#include +#include +#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +typedef struct +{ + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf32_Half st_shndx; +} Elf32_sym; + +#ifdef RT_USING_USERSPACE +void lwp_elf_reloc(rt_mmu_info *m_info, void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf32_sym *dynsym) +{ + size_t rel_off; + void* addr; + + if (rel_dyn_size && !dynsym) + { + return; + } + for (rel_off = 0; rel_off < rel_dyn_size; rel_off += 8) + { + uint32_t v1, v2; + + /* + memcpy(&v1, rel_dyn_start + rel_off, 4); + memcpy(&v2, rel_dyn_start + rel_off + 4, 4); + */ + + addr = rt_hw_mmu_v2p(m_info, (void*)((char*)rel_dyn_start + rel_off)); + addr = (void*)((char*)addr - PV_OFFSET); + memcpy(&v1, addr, 4); + addr = rt_hw_mmu_v2p(m_info, (void*)((char*)rel_dyn_start + rel_off + 4)); + addr = (void*)((char*)addr - PV_OFFSET); + memcpy(&v2, addr, 4); + + addr = rt_hw_mmu_v2p(m_info, (void*)((char*)text_start + v1)); + addr = (void*)((char*)addr - PV_OFFSET); + if ((v2 & 0xff) == R_ARM_RELATIVE) + { + // *(uint32_t*)(text_start + v1) += (uint32_t)text_start; + *(uint32_t*)addr += (uint32_t)text_start; + } + else if ((v2 & 0xff) == R_ARM_ABS32) + { + uint32_t t; + t = (v2 >> 8); + if (t) /* 0 is UDF */ + { + // *(uint32_t*)(text_start + v1) = (uint32_t)(text_start + dynsym[t].st_value); + *(uint32_t*)addr = (uint32_t)((char*)text_start + dynsym[t].st_value); + } + } + } + /* modify got */ + if (got_size) + { + uint32_t *got_item = (uint32_t*)got_start; + + for (rel_off = 0; rel_off < got_size; rel_off += 4, got_item++) + { + //*got_item += (uint32_t)text_start; + addr = rt_hw_mmu_v2p(m_info, got_item); + addr = (void*)((char*)addr - PV_OFFSET); + *(uint32_t *)addr += (uint32_t)text_start; + } + } +} +#else + +void lwp_elf_reloc(void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf32_sym *dynsym) +{ + size_t rel_off; + + if (rel_dyn_size && !dynsym) + { + return; + } + for (rel_off = 0; rel_off < rel_dyn_size; rel_off += 8) + { + uint32_t v1, v2; + + memcpy(&v1, (void*)((char*)rel_dyn_start + rel_off), 4); + memcpy(&v2, (void*)((char*)rel_dyn_start + rel_off + 4), 4); + + if ((v2 & 0xff) == R_ARM_RELATIVE) + { + *(uint32_t*)((char*)text_start + v1) += (uint32_t)text_start; + } + else if ((v2 & 0xff) == R_ARM_ABS32) + { + uint32_t t; + t = (v2 >> 8); + if (t) /* 0 is UDF */ + { + *(uint32_t*)((char*)text_start + v1) = (uint32_t)((char*)text_start + dynsym[t].st_value); + } + } + } + /* modify got */ + if (got_size) + { + uint32_t *got_item = (uint32_t*)got_start; + + for (rel_off = 0; rel_off < got_size; rel_off += 4, got_item++) + { + *got_item += (uint32_t)text_start; + } + } +} +#endif diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.c b/components/lwp/arch/arm/cortex-a/lwp_arch.c new file mode 100644 index 0000000000000000000000000000000000000000..0d0d0cf39f1936bc3bf67e34d02a6804e349e331 --- /dev/null +++ b/components/lwp/arch/arm/cortex-a/lwp_arch.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-28 Jesven first version + */ + +#include +#include + +#ifdef RT_USING_USERSPACE + +#include +#include +#include +#include +#include + +extern size_t MMUTable[]; + +int arch_user_space_init(struct rt_lwp *lwp) +{ + size_t *mmu_table; + + mmu_table = (size_t*)rt_pages_alloc(2); + if (!mmu_table) + { + return -1; + } + + lwp->end_heap = USER_HEAP_VADDR; + rt_memcpy(mmu_table + (KERNEL_VADDR_START >> ARCH_SECTION_SHIFT), MMUTable + (KERNEL_VADDR_START >> ARCH_SECTION_SHIFT), ARCH_PAGE_SIZE); + rt_memset(mmu_table, 0, 3 * ARCH_PAGE_SIZE); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_table, 4 * ARCH_PAGE_SIZE); + rt_hw_mmu_map_init(&lwp->mmu_info, (void*)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, mmu_table, PV_OFFSET); + + return 0; +} + +void *arch_kernel_mmu_table_get(void) +{ + return (void*)((char*)MMUTable + PV_OFFSET); +} + +void arch_kuser_init(rt_mmu_info *mmu_info, void *vectors) +{ + extern char __kuser_helper_start[], __kuser_helper_end[]; + int kuser_sz = __kuser_helper_end - __kuser_helper_start; + + rt_hw_mmu_map_auto(mmu_info, vectors, 0x1000, MMU_MAP_U_RO); + + rt_memcpy((void*)((char*)vectors + 0x1000 - kuser_sz), __kuser_helper_start, kuser_sz); + /* + * vectors + 0xfe0 = __kuser_get_tls + * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8 + */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)((char*)vectors + 0x1000 - kuser_sz), kuser_sz); + rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void*)((char*)vectors + 0x1000 - kuser_sz), kuser_sz); +} + +void arch_user_space_vtable_free(struct rt_lwp *lwp) +{ + if (lwp && lwp->mmu_info.vtable) + { + rt_pages_free(lwp->mmu_info.vtable, 2); + } +} + +int arch_expand_user_stack(void *addr) +{ + int ret = 0; + size_t stack_addr = (size_t)addr; + + stack_addr &= ~ARCH_PAGE_MASK; + if ((stack_addr >= (size_t)USER_STACK_VSTART) && (stack_addr < (size_t)USER_STACK_VEND)) + { + void *map = lwp_map_user(lwp_self(), (void*)stack_addr, ARCH_PAGE_SIZE, 0); + + if (map || lwp_user_accessable(addr, 1)) + { + ret = 1; + } + } + return ret; +} + +#endif diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.h b/components/lwp/arch/arm/cortex-a/lwp_arch.h new file mode 100644 index 0000000000000000000000000000000000000000..90b2ded273e9d540a1510885ee7732a4d9bcb9e5 --- /dev/null +++ b/components/lwp/arch/arm/cortex-a/lwp_arch.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef LWP_ARCH_H__ +#define LWP_ARCH_H__ + +#include + +#ifdef RT_USING_USERSPACE + +#define USER_VADDR_TOP 0xC0000000UL +#define USER_HEAP_VEND 0xB0000000UL +#define USER_HEAP_VADDR 0x80000000UL +#define USER_STACK_VSTART 0x70000000UL +#define USER_STACK_VEND USER_HEAP_VADDR +#define LDSO_LOAD_VADDR 0x60000000UL +#define USER_VADDR_START 0x00100000UL +#define USER_LOAD_VADDR USER_VADDR_START + +#ifdef __cplusplus +extern "C" { +#endif + +int arch_user_space_init(struct rt_lwp *lwp); +void arch_user_space_vtable_free(struct rt_lwp *lwp); +void *arch_kernel_mmu_table_get(void); +void arch_kuser_init(rt_mmu_info *mmu_info, void *vectors); +int arch_expand_user_stack(void *addr); + +rt_inline unsigned long ffz(unsigned long x) +{ + return __builtin_ffs(~x) - 1; +} + +rt_inline void icache_invalid_all(void) +{ + asm volatile ("mcr p15, 0, r0, c7, c5, 0\ndsb\nisb":::"memory");//iciallu +} + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /*LWP_ARCH_H__*/ diff --git a/components/lwp/arch/arm/cortex-a/lwp_gcc.S b/components/lwp/arch/arm/cortex-a/lwp_gcc.S index 395974a2b72a266341e8bffa387a040a8a87b932..009c751945892f756c96f4c8774db6e6af50c15f 100644 --- a/components/lwp/arch/arm/cortex-a/lwp_gcc.S +++ b/components/lwp/arch/arm/cortex-a/lwp_gcc.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,6 +8,8 @@ * 2018-12-10 Jesven first version */ +#include "rtconfig.h" + #define Mode_USR 0x10 #define Mode_FIQ 0x11 #define Mode_IRQ 0x12 @@ -27,7 +29,7 @@ .text /* - * void lwp_user_entry(args, text, data); + * void lwp_user_entry(args, text, ustack, kstack); */ .global lwp_user_entry .type lwp_user_entry, % function @@ -37,11 +39,115 @@ lwp_user_entry: orr r9, #Mode_USR cpsid i msr spsr, r9 + mov sp, r3 + mov r3, r2 ;/* user stack top */ /* set data address. */ - mov r9, r2 movs pc, r1 +/* + * void lwp_user_thread_entry(args, text, ustack, kstack); + */ +.global lwp_user_thread_entry +.type lwp_user_thread_entry, % function +lwp_user_thread_entry: + cps #Mode_SYS + sub sp, r2, #12 + ldr r2, =lwp_thread_return + ldr r4, [r2] + str r4, [sp] + ldr r4, [r2, #4] + str r4, [sp, #4] + ldr r4, [r2, #8] + str r4, [sp, #8] + + mov r4, sp + mcr p15, 0, r4, c7, c11, 1 ;//dc cmvau + add r4, #4 + mcr p15, 0, r4, c7, c11, 1 ;//dc cmvau + add r4, #4 + mcr p15, 0, r4, c7, c11, 1 ;//dc cmvau + dsb + isb + mcr p15, 0, r4, c7, c5, 0 ;//iciallu + dsb + isb + + mov lr, sp + cps #Mode_SVC + + mrs r9, cpsr + bic r9, #0x1f + orr r9, #Mode_USR + cpsid i + msr spsr, r9 + mov sp, r3 + + /* set data address. */ + movs pc, r1 + +/* +void lwp_set_thread_context(void *exit_addr, void *new_thread_stack, void *user_stack, void **thread_sp); +*/ +.global lwp_set_thread_context +lwp_set_thread_context: + sub r1, #(10 * 4 + 4 * 4) /* {r4 - r12, lr} , {r4, r5, spsr, u_pc} */ + stmfd r1!, {r0} + mov r12, #0 + stmfd r1!, {r12} + stmfd r1!, {r1 - r12} + stmfd r1!, {r12} /* new thread return value */ + mrs r12, cpsr + orr r12, #(1 << 7) /* disable irq */ + stmfd r1!, {r12} /* spsr */ + mov r12, #0 + stmfd r1!, {r12} /* now user lr is 0 */ + stmfd r1!, {r2} /* user sp */ +#ifdef RT_USING_FPU + stmfd r1!, {r12} /* not use fpu */ +#endif + str r1, [r3] + mov pc, lr + +.global lwp_get_user_sp +lwp_get_user_sp: + cps #Mode_SYS + mov r0, sp + cps #Mode_SVC + mov pc, lr + +.global sys_fork +.global sys_vfork +.global sys_fork_exit +sys_fork: +sys_vfork: + push {r4 - r12, lr} + bl _sys_fork +sys_fork_exit: + pop {r4 - r12, lr} + b svc_exit + +.global sys_clone +.global sys_clone_exit +sys_clone: + push {r4 - r12, lr} + bl _sys_clone +sys_clone_exit: + pop {r4 - r12, lr} + b svc_exit +/* +void lwp_exec_user(void *args, void *kernel_stack, void *user_entry) +*/ +.global lwp_exec_user +lwp_exec_user: + cpsid i + mov sp, r1 + mov lr, r2 + mov r2, #Mode_USR + msr spsr_cxsf, r2 + ldr r3, =0x80000000 + b ret_to_user + /* * void SVC_Handler(void); */ @@ -51,13 +157,27 @@ vector_swi: push {lr} mrs lr, spsr push {r4, r5, lr} + cpsie i push {r0 - r3, r12} + + bl rt_thread_self + bl lwp_user_setting_save + + and r0, r7, #0xf000 + cmp r0, #0xe000 + beq lwp_signal_quit + +#ifdef RT_USING_GDBSERVER + cmp r0, #0xf000 + beq ret_from_user +#endif and r0, r7, #0xff bl lwp_get_sys_api cmp r0, #0 /* r0 = api */ mov lr, r0 + pop {r0 - r3, r12} beq svc_exit blx lr @@ -67,4 +187,242 @@ svc_exit: pop {r4, r5, lr} msr spsr_cxsf, lr pop {lr} + +.global ret_to_user +ret_to_user: + push {r0-r3, r12, lr} + bl lwp_signal_check + cmp r0, #0 + pop {r0-r3, r12, lr} + bne user_do_signal +#ifdef RT_USING_GDBSERVER + push {r0-r3, r12, lr} + mov r0, lr + bl lwp_check_debug_attach_req + pop {r0-r3, r12, lr} +#endif + movs pc, lr + +#ifdef RT_USING_LWP +.global lwp_check_exit +lwp_check_exit: + push {r0 - r12, lr} + bl lwp_check_exit_request + cmp r0, #0 + beq 1f + mov r0, #0 + bl sys_exit +1: + pop {r0 - r12, pc} +#endif + +#ifdef RT_USING_GDBSERVER +.global lwp_check_debug +lwp_check_debug: + push {r0 - r12, lr} + bl lwp_check_debug_suspend + cmp r0, #0 + beq lwp_check_debug_quit + + cps #Mode_SYS + sub sp, #8 + ldr r0, =lwp_debugreturn + ldr r1, [r0] + str r1, [sp] + ldr r1, [r0, #4] + str r1, [sp, #4] + + mov r1, sp + mcr p15, 0, r1, c7, c11, 1 ;//dc cmvau + add r1, #4 + mcr p15, 0, r1, c7, c11, 1 ;//dc cmvau + dsb + isb + mcr p15, 0, r0, c7, c5, 0 ;//iciallu + dsb + isb + + mov r0, sp /* lwp_debugreturn */ + cps #Mode_SVC + + mrs r1, spsr + push {r1} + mov r1, #Mode_USR + msr spsr_cxsf, r1 + movs pc, r0 +ret_from_user: + cps #Mode_SYS + add sp, #8 + cps #Mode_SVC + /* + pop {r0 - r3, r12} + pop {r4 - r6, lr} + */ + add sp, #(4*9) + pop {r4} + msr spsr_cxsf, r4 +lwp_check_debug_quit: + pop {r0 - r12, pc} +#endif + +lwp_signal_quit: + cpsid i + pop {r0 - r3, r12} + pop {r4, r5, lr} + pop {lr} + bl lwp_signal_restore + /* r0 is user_ctx : ori sp, pc, cpsr*/ + ldr r1, [r0] + ldr r2, [r0, #4] + ldr r3, [r0, #8] + msr spsr_cxsf, r3 + mov lr, r2 + cps #Mode_SYS + mov sp, r1 + pop {r0-r12, lr} + cps #Mode_SVC + b ret_to_user + +user_do_signal: + mov r0, r0 + cps #Mode_SYS + push {r0-r12, lr} + + sub sp, #8 + ldr r0, =lwp_sigreturn + ldr r1, [r0] + str r1, [sp] + ldr r1, [r0, #4] + str r1, [sp, #4] + + mov r1, sp + mcr p15, 0, r1, c7, c11, 1 ;//dc cmvau + add r1, #4 + mcr p15, 0, r1, c7, c11, 1 ;//dc cmvau + dsb + isb + mcr p15, 0, r0, c7, c5, 0 ;//iciallu + dsb + isb + + mov r5, sp ;//if func is 0 + mov lr, sp + + add r0, sp, #8 /* lwp_sigreturn */ + cps #Mode_SVC + mov r1, lr + mrs r2, spsr + bl lwp_signal_backup + /* r0 is signal */ + mov r4, r0 + bl lwp_sighandler_get + mov lr, r0 + cmp lr, #0 + moveq lr, r5 + mov r0, r4 movs pc, lr + +lwp_debugreturn: + mov r7, #0xf000 + svc #0 + +lwp_sigreturn: + mov r7, #0xe000 + svc #0 + +lwp_thread_return: + mov r0, #0 + mov r7, #0x01 + svc #0 + +.global check_vfp +check_vfp: +#ifdef RT_USING_FPU + vmrs r0, fpexc + ubfx r0, r0, #30, #1 +#else + mov r0, #0 +#endif + mov pc, lr + +.global get_vfp +get_vfp: +#ifdef RT_USING_FPU + vstmia r0!, {d0-d15} + vstmia r0!, {d16-d31} + vmrs r1, fpscr + str r1, [r0] +#endif + mov pc, lr + +.globl rt_cpu_get_thread_idr +rt_cpu_get_thread_idr: + mrc p15, 0, r0, c13, c0, 3 + bx lr + +.global lwp_set_thread_area +lwp_set_thread_area: +.globl rt_cpu_set_thread_idr +rt_cpu_set_thread_idr: + mcr p15, 0, r0, c13, c0, 3 + bx lr + +/* kuser suppurt */ + .macro kuser_pad, sym, size + .if (. - \sym) & 3 + .rept 4 - (. - \sym) & 3 + .byte 0 + .endr + .endif + .rept (\size - (. - \sym)) / 4 + .word 0xe7fddef1 + .endr + .endm + +.align 5 +.globl __kuser_helper_start +__kuser_helper_start: +__kuser_cmpxchg64: @ 0xffff0f60 + stmfd sp!, {r4, r5, r6, lr} + ldmia r0, {r4, r5} @ load old val + ldmia r1, {r6, lr} @ load new val +1: ldmia r2, {r0, r1} @ load current val + eors r3, r0, r4 @ compare with oldval (1) + eorseq r3, r1, r5 @ compare with oldval (2) +2: stmiaeq r2, {r6, lr} @ store newval if eq + rsbs r0, r3, #0 @ set return val and C flag + ldmfd sp!, {r4, r5, r6, pc} + + kuser_pad __kuser_cmpxchg64, 64 + +__kuser_memory_barrier: @ 0xffff0fa0 + dmb + mov pc, lr + + kuser_pad __kuser_memory_barrier, 32 + +__kuser_cmpxchg: @ 0xffff0fc0 +1: ldr r3, [r2] @ load current val + subs r3, r3, r0 @ compare with oldval +2: streq r1, [r2] @ store newval if eq + rsbs r0, r3, #0 @ set return val and C flag + mov pc, lr + +kuser_pad __kuser_cmpxchg, 32 + +__kuser_get_tls: @ 0xffff0fe0 + mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code + mov pc, lr + ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init + + kuser_pad __kuser_get_tls, 16 + + .rep 3 + .word 0 @ 0xffff0ff0 software TLS value, then + .endr @ pad up to __kuser_helper_version + +__kuser_helper_version: @ 0xffff0ffc + .word ((__kuser_helper_end - __kuser_helper_start) >> 5) + + .globl __kuser_helper_end +__kuser_helper_end: diff --git a/components/lwp/arch/arm/cortex-a9/lwp_gcc.S b/components/lwp/arch/arm/cortex-a9/lwp_gcc.S deleted file mode 100644 index 93e88f7c97a2f811f6fbf4f0ac8231c6cdfcf8c7..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-a9/lwp_gcc.S +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-10 Jesven first version - */ - -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_MON 0x16 -#define Mode_ABT 0x17 -#define Mode_UDF 0x1B -#define Mode_SYS 0x1F - -#define A_Bit 0x100 -#define I_Bit 0x80 @; when I bit is set, IRQ is disabled -#define F_Bit 0x40 @; when F bit is set, FIQ is disabled -#define T_Bit 0x20 - -.cpu cortex-a9 -.syntax unified -.text - -/* - * void lwp_user_entry(args, text, data); - */ -.global lwp_user_entry -.type lwp_user_entry, % function -lwp_user_entry: - mrs r9, cpsr - bic r9, #0x1f - orr r9, #Mode_USR - cpsid i - msr spsr, r9 - - /* set data address. */ - mov r9, r2 - movs pc, r1 - -/* - * void vector_swi(void); - */ -.global vector_swi -.type vector_swi, % function -vector_swi: - push {lr} - mrs lr, spsr - push {r4, r5, lr} - cpsie i - - push {r0 - r3, r12} - and r0, r7, #0xff - bl lwp_get_sys_api - cmp r0, #0 /* r0 = api */ - mov lr, r0 - pop {r0 - r3, r12} - beq svc_exit - blx lr - -svc_exit: - cpsid i - pop {r4, r5, lr} - msr spsr_cxsf, lr - pop {lr} - movs pc, lr diff --git a/components/lwp/arch/arm/cortex-m3/lwp_gcc.S b/components/lwp/arch/arm/cortex-m3/lwp_gcc.S deleted file mode 100644 index 846b06bb263fa5cdd9dcb904df3e4e24edafef0a..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-m3/lwp_gcc.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-10-30 heyuanjie first version - */ - -.cpu cortex-m3 -.syntax unified -.thumb -.text - -/* - * void* lwp_get_sys_api(rt_uint32_t number); - */ -.global lwp_get_sys_api -.global lwp_get_kernel_sp -.global lwp_set_kernel_sp - - -/* - * void lwp_user_entry(args, text, data); - */ -.global lwp_user_entry -.type lwp_user_entry, % function -lwp_user_entry: - PUSH {R0-R3} @; push text&data addr. - - MOV R0, SP @; v1 = SP - BL lwp_set_kernel_sp @; lwp_set_kernel_sp(v1) - - @; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 @; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} @; pop app address to R1. - @; set data address. - MOV R9, R2 - - @; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - -/* - * void SVC_Handler(void); - */ -.global SVC_Handler -.type SVC_Handler, % function -SVC_Handler: - PUSH {LR} - - @; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - PUSH {R1} @; push app SP. - - @; get SVC number. - mov R0, R7 - - @; get kernel system API - BL lwp_get_sys_api - - PUSH {R0} @; push api - - @; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} @; pop api to R2. - POP {R1} @; pop app SP to R1. - - stmfd r0!, {r1} @; save app SP to kernel SP - - @;push app parm5~6 to kernel SP - STMFD R0!, {R4 - R5} - @; copy R1(app SP) to R0(kernel SP). - push {r8-r11} - LDMFD R1, {R4 - R11} @; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} @; push exception_stack_frame to server SP. - pop {r8-r11} - - LDR R3, =svc_exit - STR R3, [R0, #20] @; update LR - STR R2, [R0, #24] @; update api to PC - MSR PSP, R0 @; update SP, API is executed with kernel SP - - @; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - POP {LR} @; 0xFFFFFFED - ORR LR, LR, #0x10 - BX LR -/* -* void svc_exit(void); -*/ -.global svc_exit -.type svc_exit, % function -svc_exit: - @; get user SP. - PUSH {R0} @; push result to SP. - BL lwp_get_kernel_sp - ldr r3, [r0, #-4] - pop {r0} - - ldr lr, [r3, #20] - ldr r1, [r3, #24] @; load pc - add r3, #32 @; exception_stack_frame size - MSR PSP, R3 @; restore app stack pointer - @; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - @; return to lwp. - ORR R1, R1, #0x01 @; only Thumb-mode. - BX R1 @; return to user app. diff --git a/components/lwp/arch/arm/cortex-m3/lwp_iar.S b/components/lwp/arch/arm/cortex-m3/lwp_iar.S deleted file mode 100644 index a2185693758ec21051ad5dba267ad518270ff5e6..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-m3/lwp_iar.S +++ /dev/null @@ -1,123 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2018-10-30 heyuanjie first version -; */ - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(args, text, data); -; */ - EXPORT lwp_user_entry -lwp_user_entry: - PUSH {R0-R3} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} ; pop app address to R1. - ; set data address. - MOV R9, R2 - - ; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - -;/* -; * void SVC_Handler(void); -; */ - EXPORT SVC_Handler -SVC_Handler: - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - PUSH {R1} ; push app SP. - - ; get SVC number. - mov R0, R7 - - ; get kernel system API - BL lwp_get_sys_api - - PUSH {R0} ; push api - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - stmfd r0!, {r1} ; save app SP to kernel SP - - ;push app parm5~6 to kernel SP - STMFD R0!, {R4 - R5} - ; copy R1(app SP) to R0(kernel SP). - push {r8-r11} - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - pop {r8-r11} - - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update SP, API is executed with kernel SP - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - POP {LR} ; 0xFFFFFFED - ORR LR, LR, #0x10 - BX LR - -;/* -; * void svc_exit(void); -; */ - EXPORT svc_exit -svc_exit: - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - ldr r3, [r0, #-4] - pop {r0} - - ldr lr, [r3, #20] - ldr r1, [r3, #24] ; load pc - add r3, r3, #32 ; exception_stack_frame size - MSR PSP, R3 ; restore app stack pointer - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - END diff --git a/components/lwp/arch/arm/cortex-m3/lwp_rvds.S b/components/lwp/arch/arm/cortex-m3/lwp_rvds.S deleted file mode 100644 index 246751a84729b17f39e3405fb4ea5a02748f0d13..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-m3/lwp_rvds.S +++ /dev/null @@ -1,135 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2018-10-30 heyuanjie first version -; */ - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(args, text, data); -; */ -lwp_user_entry PROC - EXPORT lwp_user_entry - - PUSH {R0-R3} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} ; pop app address to R1. - ; set data address. - MOV R9, R2 - - ; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - - ; never reach here! - ENDP - -;/* -; * void SVC_Handler(void); -; */ -SVC_Handler PROC - EXPORT SVC_Handler - - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - PUSH {R1} ; push app SP. - - ; get SVC number. - mov R0, R7 - - ; get kernel system API - BL lwp_get_sys_api - - PUSH {R0} ; push api - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - stmfd r0!, {r1} ; save app SP to kernel SP - - ;push app parm5~6 to kernel SP - STMFD R0!, {R4 - R5} - ; copy R1(app SP) to R0(kernel SP). - push {r8-r11} - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - pop {r8-r11} - - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update SP, API is executed with kernel SP - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - POP {LR} ; 0xFFFFFFED - ORR LR, LR, #0x10 - BX LR - - ENDP - -;/* -; * void svc_exit(void); -; */ -svc_exit PROC - EXPORT svc_exit - - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - ldr r3, [r0, #-4] - pop {r0} - - ldr lr, [r3, #20] - ldr r1, [r3, #24] ; load pc - add r3, #32 ; exception_stack_frame size - MSR PSP, R3 ; restore app stack pointer - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - ENDP - - ALIGN - - END diff --git a/components/lwp/arch/arm/cortex-m4/lwp_gcc.S b/components/lwp/arch/arm/cortex-m4/lwp_gcc.S deleted file mode 100644 index e71dbb82c9ea16dc7cc9fef81f1aae50182cfb18..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-m4/lwp_gcc.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-10-30 heyuanjie first version - */ - -.cpu cortex-m4 -.syntax unified -.thumb -.text - -/* - * void* lwp_get_sys_api(rt_uint32_t number); - */ -.global lwp_get_sys_api -.global lwp_get_kernel_sp -.global lwp_set_kernel_sp - - -/* - * void lwp_user_entry(args, text, data); - */ -.global lwp_user_entry -.type lwp_user_entry, % function -lwp_user_entry: - PUSH {R0-R3} @; push text&data addr. - - MOV R0, SP @; v1 = SP - BL lwp_set_kernel_sp @; lwp_set_kernel_sp(v1) - - @; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 @; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} @; pop app address to R1. - @; set data address. - MOV R9, R2 - - @; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - -/* - * void SVC_Handler(void); - */ -.global SVC_Handler -.type SVC_Handler, % function -SVC_Handler: - PUSH {LR} - - @; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - PUSH {R1} @; push app SP. - - @; get SVC number. - mov R0, R7 - - @; get kernel system API - BL lwp_get_sys_api - - PUSH {R0} @; push api - - @; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} @; pop api to R2. - POP {R1} @; pop app SP to R1. - - stmfd r0!, {r1} @; save app SP to kernel SP - - @;push app parm5~6 to kernel SP - STMFD R0!, {R4 - R5} - @; copy R1(app SP) to R0(kernel SP). - push {r8-r11} - LDMFD R1, {R4 - R11} @; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} @; push exception_stack_frame to server SP. - pop {r8-r11} - - LDR R3, =svc_exit - STR R3, [R0, #20] @; update LR - STR R2, [R0, #24] @; update api to PC - MSR PSP, R0 @; update SP, API is executed with kernel SP - - @; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - POP {LR} @; 0xFFFFFFED - ORR LR, LR, #0x10 - BX LR -/* -* void svc_exit(void); -*/ -.global svc_exit -.type svc_exit, % function -svc_exit: - @; get user SP. - PUSH {R0} @; push result to SP. - BL lwp_get_kernel_sp - ldr r3, [r0, #-4] - pop {r0} - - ldr lr, [r3, #20] - ldr r1, [r3, #24] @; load pc - add r3, #32 @; exception_stack_frame size - MSR PSP, R3 @; restore app stack pointer - @; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - @; return to lwp. - ORR R1, R1, #0x01 @; only Thumb-mode. - BX R1 @; return to user app. diff --git a/components/lwp/arch/arm/cortex-m4/lwp_iar.S b/components/lwp/arch/arm/cortex-m4/lwp_iar.S deleted file mode 100644 index a2185693758ec21051ad5dba267ad518270ff5e6..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-m4/lwp_iar.S +++ /dev/null @@ -1,123 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2018-10-30 heyuanjie first version -; */ - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(args, text, data); -; */ - EXPORT lwp_user_entry -lwp_user_entry: - PUSH {R0-R3} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} ; pop app address to R1. - ; set data address. - MOV R9, R2 - - ; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - -;/* -; * void SVC_Handler(void); -; */ - EXPORT SVC_Handler -SVC_Handler: - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - PUSH {R1} ; push app SP. - - ; get SVC number. - mov R0, R7 - - ; get kernel system API - BL lwp_get_sys_api - - PUSH {R0} ; push api - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - stmfd r0!, {r1} ; save app SP to kernel SP - - ;push app parm5~6 to kernel SP - STMFD R0!, {R4 - R5} - ; copy R1(app SP) to R0(kernel SP). - push {r8-r11} - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - pop {r8-r11} - - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update SP, API is executed with kernel SP - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - POP {LR} ; 0xFFFFFFED - ORR LR, LR, #0x10 - BX LR - -;/* -; * void svc_exit(void); -; */ - EXPORT svc_exit -svc_exit: - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - ldr r3, [r0, #-4] - pop {r0} - - ldr lr, [r3, #20] - ldr r1, [r3, #24] ; load pc - add r3, r3, #32 ; exception_stack_frame size - MSR PSP, R3 ; restore app stack pointer - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - END diff --git a/components/lwp/arch/arm/cortex-m4/lwp_rvds.S b/components/lwp/arch/arm/cortex-m4/lwp_rvds.S deleted file mode 100644 index 246751a84729b17f39e3405fb4ea5a02748f0d13..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-m4/lwp_rvds.S +++ /dev/null @@ -1,135 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2018-10-30 heyuanjie first version -; */ - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(args, text, data); -; */ -lwp_user_entry PROC - EXPORT lwp_user_entry - - PUSH {R0-R3} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} ; pop app address to R1. - ; set data address. - MOV R9, R2 - - ; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - - ; never reach here! - ENDP - -;/* -; * void SVC_Handler(void); -; */ -SVC_Handler PROC - EXPORT SVC_Handler - - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - PUSH {R1} ; push app SP. - - ; get SVC number. - mov R0, R7 - - ; get kernel system API - BL lwp_get_sys_api - - PUSH {R0} ; push api - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - stmfd r0!, {r1} ; save app SP to kernel SP - - ;push app parm5~6 to kernel SP - STMFD R0!, {R4 - R5} - ; copy R1(app SP) to R0(kernel SP). - push {r8-r11} - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - pop {r8-r11} - - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update SP, API is executed with kernel SP - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - POP {LR} ; 0xFFFFFFED - ORR LR, LR, #0x10 - BX LR - - ENDP - -;/* -; * void svc_exit(void); -; */ -svc_exit PROC - EXPORT svc_exit - - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - ldr r3, [r0, #-4] - pop {r0} - - ldr lr, [r3, #20] - ldr r1, [r3, #24] ; load pc - add r3, #32 ; exception_stack_frame size - MSR PSP, R3 ; restore app stack pointer - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - ENDP - - ALIGN - - END diff --git a/components/lwp/arch/arm/cortex-m7/lwp_gcc.S b/components/lwp/arch/arm/cortex-m7/lwp_gcc.S deleted file mode 100644 index 848c592919554402f9475903d5f10d58cd651c80..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-m7/lwp_gcc.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-10-30 heyuanjie first version - */ - -.cpu cortex-m7 -.syntax unified -.thumb -.text - -/* - * void* lwp_get_sys_api(rt_uint32_t number); - */ -.global lwp_get_sys_api -.global lwp_get_kernel_sp -.global lwp_set_kernel_sp - - -/* - * void lwp_user_entry(args, text, data); - */ -.global lwp_user_entry -.type lwp_user_entry, % function -lwp_user_entry: - PUSH {R0-R3} @; push text&data addr. - - MOV R0, SP @; v1 = SP - BL lwp_set_kernel_sp @; lwp_set_kernel_sp(v1) - - @; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 @; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} @; pop app address to R1. - @; set data address. - MOV R9, R2 - - @; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - -/* - * void SVC_Handler(void); - */ -.global SVC_Handler -.type SVC_Handler, % function -SVC_Handler: - PUSH {LR} - - @; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - PUSH {R1} @; push app SP. - - @; get SVC number. - mov R0, R7 - - @; get kernel system API - BL lwp_get_sys_api - - PUSH {R0} @; push api - - @; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} @; pop api to R2. - POP {R1} @; pop app SP to R1. - - stmfd r0!, {r1} @; save app SP to kernel SP - - @;push app parm5~6 to kernel SP - STMFD R0!, {R4 - R5} - @; copy R1(app SP) to R0(kernel SP). - push {r8-r11} - LDMFD R1, {R4 - R11} @; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} @; push exception_stack_frame to server SP. - pop {r8-r11} - - LDR R3, =svc_exit - STR R3, [R0, #20] @; update LR - STR R2, [R0, #24] @; update api to PC - MSR PSP, R0 @; update SP, API is executed with kernel SP - - @; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - POP {LR} @; 0xFFFFFFED - ORR LR, LR, #0x10 - BX LR -/* -* void svc_exit(void); -*/ -.global svc_exit -.type svc_exit, % function -svc_exit: - @; get user SP. - PUSH {R0} @; push result to SP. - BL lwp_get_kernel_sp - ldr r3, [r0, #-4] - pop {r0} - - ldr lr, [r3, #20] - ldr r1, [r3, #24] @; load pc - add r3, #32 @; exception_stack_frame size - MSR PSP, R3 @; restore app stack pointer - @; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - @; return to lwp. - ORR R1, R1, #0x01 @; only Thumb-mode. - BX R1 @; return to user app. diff --git a/components/lwp/arch/arm/cortex-m7/lwp_iar.S b/components/lwp/arch/arm/cortex-m7/lwp_iar.S deleted file mode 100644 index a2185693758ec21051ad5dba267ad518270ff5e6..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-m7/lwp_iar.S +++ /dev/null @@ -1,123 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2018-10-30 heyuanjie first version -; */ - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(args, text, data); -; */ - EXPORT lwp_user_entry -lwp_user_entry: - PUSH {R0-R3} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} ; pop app address to R1. - ; set data address. - MOV R9, R2 - - ; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - -;/* -; * void SVC_Handler(void); -; */ - EXPORT SVC_Handler -SVC_Handler: - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - PUSH {R1} ; push app SP. - - ; get SVC number. - mov R0, R7 - - ; get kernel system API - BL lwp_get_sys_api - - PUSH {R0} ; push api - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - stmfd r0!, {r1} ; save app SP to kernel SP - - ;push app parm5~6 to kernel SP - STMFD R0!, {R4 - R5} - ; copy R1(app SP) to R0(kernel SP). - push {r8-r11} - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - pop {r8-r11} - - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update SP, API is executed with kernel SP - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - POP {LR} ; 0xFFFFFFED - ORR LR, LR, #0x10 - BX LR - -;/* -; * void svc_exit(void); -; */ - EXPORT svc_exit -svc_exit: - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - ldr r3, [r0, #-4] - pop {r0} - - ldr lr, [r3, #20] - ldr r1, [r3, #24] ; load pc - add r3, r3, #32 ; exception_stack_frame size - MSR PSP, R3 ; restore app stack pointer - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - END diff --git a/components/lwp/arch/arm/cortex-m7/lwp_rvds.S b/components/lwp/arch/arm/cortex-m7/lwp_rvds.S deleted file mode 100644 index 246751a84729b17f39e3405fb4ea5a02748f0d13..0000000000000000000000000000000000000000 --- a/components/lwp/arch/arm/cortex-m7/lwp_rvds.S +++ /dev/null @@ -1,135 +0,0 @@ -;/* -; * Copyright (c) 2006-2018, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2018-10-30 heyuanjie first version -; */ - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(args, text, data); -; */ -lwp_user_entry PROC - EXPORT lwp_user_entry - - PUSH {R0-R3} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} ; pop app address to R1. - ; set data address. - MOV R9, R2 - - ; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - - ; never reach here! - ENDP - -;/* -; * void SVC_Handler(void); -; */ -SVC_Handler PROC - EXPORT SVC_Handler - - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - PUSH {R1} ; push app SP. - - ; get SVC number. - mov R0, R7 - - ; get kernel system API - BL lwp_get_sys_api - - PUSH {R0} ; push api - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - stmfd r0!, {r1} ; save app SP to kernel SP - - ;push app parm5~6 to kernel SP - STMFD R0!, {R4 - R5} - ; copy R1(app SP) to R0(kernel SP). - push {r8-r11} - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - pop {r8-r11} - - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update SP, API is executed with kernel SP - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - POP {LR} ; 0xFFFFFFED - ORR LR, LR, #0x10 - BX LR - - ENDP - -;/* -; * void svc_exit(void); -; */ -svc_exit PROC - EXPORT svc_exit - - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - ldr r3, [r0, #-4] - pop {r0} - - ldr lr, [r3, #20] - ldr r1, [r3, #24] ; load pc - add r3, #32 ; exception_stack_frame size - MSR PSP, R3 ; restore app stack pointer - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - ENDP - - ALIGN - - END diff --git a/components/lwp/arch/risc-v/rv64/SConscript b/components/lwp/arch/risc-v/rv64/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e98e7650b12eb2d853bb57f59afb5f50e2a02cec --- /dev/null +++ b/components/lwp/arch/risc-v/rv64/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('lwp-riscv', src, depend = ['RT_USING_LWP'], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/lwp/arch/risc-v/rv64/lwp_arch.c b/components/lwp/arch/risc-v/rv64/lwp_arch.c new file mode 100644 index 0000000000000000000000000000000000000000..118e1731058139331c02ca92411bd1a6728d29b8 --- /dev/null +++ b/components/lwp/arch/risc-v/rv64/lwp_arch.c @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-11-18 Jesven first version + * 2021-02-03 lizhirui port to riscv64 + * 2021-02-06 lizhirui add thread filter + * 2021-02-19 lizhirui port to new version of rt-smart + * 2021-03-02 lizhirui add a auxillary function for interrupt + * 2021-03-04 lizhirui delete thread filter + * 2021-03-04 lizhirui modify for new version of rt-smart + * 2021-11-22 JasonHu add lwp_set_thread_context + * 2021-11-30 JasonHu add clone/fork support + */ + +#include +#include + +#ifdef RT_USING_USERSPACE + +#include +#include +#include +#include +#include + +#include +#include +#include + +extern rt_ubase_t MMUTable[]; + +int arch_expand_user_stack(void *addr) +{ + int ret = 0; + rt_ubase_t stack_addr = (rt_ubase_t)addr; + + stack_addr &= ~PAGE_OFFSET_MASK; + if ((stack_addr >= (rt_ubase_t)USER_STACK_VSTART) && (stack_addr < (rt_ubase_t)USER_STACK_VEND)) + { + void *map = lwp_map_user(lwp_self(), (void *)stack_addr, PAGE_SIZE, RT_FALSE); + + if (map || lwp_user_accessable(addr, 1)) + { + ret = 1; + } + } + return ret; +} + +void *lwp_copy_return_code_to_user_stack() +{ + void lwp_thread_return(); + void lwp_thread_return_end(); + rt_thread_t tid = rt_thread_self(); + + if (tid->user_stack != RT_NULL) + { + rt_size_t size = (rt_size_t)lwp_thread_return_end - (rt_size_t)lwp_thread_return; + rt_size_t userstack = (rt_size_t)tid->user_stack + tid->user_stack_size - size; + rt_memcpy((void *)userstack, lwp_thread_return, size); + return (void *)userstack; + } + + return RT_NULL; +} + +rt_mmu_info* arch_kernel_get_mmu_info(void) +{ + extern rt_mmu_info *mmu_info; + + return mmu_info; +} + +rt_ubase_t lwp_fix_sp(rt_ubase_t cursp) +{ + void lwp_thread_return(); + void lwp_thread_return_end(); + + if (cursp == 0) + { + return 0; + } + + return cursp - ((rt_size_t)lwp_thread_return_end - (rt_size_t)lwp_thread_return); +} + +rt_thread_t rt_thread_sp_to_thread(void *spmember_addr) +{ + return (rt_thread_t)(((rt_ubase_t)spmember_addr) - (offsetof(struct rt_thread, sp))); +} + +void *get_thread_kernel_stack_top(rt_thread_t thread) +{ + return (void *)(((rt_size_t)thread->stack_addr) + ((rt_size_t)thread->stack_size)); +} + +void *lwp_get_user_sp(void) +{ + /* user sp saved in interrupt context */ + rt_thread_t self = rt_thread_self(); + rt_uint8_t *stack_top = (rt_uint8_t *)self->stack_addr + self->stack_size; + struct rt_hw_stack_frame *frame = (struct rt_hw_stack_frame *)(stack_top - sizeof(struct rt_hw_stack_frame)); + + return (void *)frame->user_sp_exc_stack; +} + +int arch_user_space_init(struct rt_lwp *lwp) +{ + rt_ubase_t *mmu_table; + + mmu_table = (rt_ubase_t *)rt_pages_alloc(0); + if (!mmu_table) + { + return -1; + } + + lwp->end_heap = USER_HEAP_VADDR; + + rt_memcpy(mmu_table, MMUTable, PAGE_SIZE); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_table, 4 * PAGE_SIZE); + rt_hw_mmu_map_init(&lwp->mmu_info, (void *)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, (rt_size_t *)mmu_table, 0); + + return 0; +} + +void *arch_kernel_mmu_table_get(void) +{ + return (void *)((char *)MMUTable); +} + +void arch_user_space_vtable_free(struct rt_lwp *lwp) +{ + if (lwp && lwp->mmu_info.vtable) + { + rt_pages_free(lwp->mmu_info.vtable, 0); + } +} + +long _sys_clone(void *arg[]); +long sys_clone(void *arg[]) +{ + return _sys_clone(arg); +} + +long _sys_fork(void); +long sys_fork(void) +{ + return _sys_fork(); +} + +long _sys_vfork(void); +long sys_vfork(void) +{ + return _sys_fork(); +} + +/** + * set exec context for fork/clone. + */ +void lwp_set_thread_context(void *exit_addr, void *new_thread_stack, void *user_stack, void **thread_sp) +{ + RT_ASSERT(exit_addr != RT_NULL); + RT_ASSERT(user_stack != RT_NULL); + RT_ASSERT(new_thread_stack != RT_NULL); + RT_ASSERT(thread_sp != RT_NULL); + struct rt_hw_stack_frame *syscall_frame; + struct rt_hw_stack_frame *thread_frame; + + rt_uint8_t *stk; + rt_uint8_t *syscall_stk; + + stk = (rt_uint8_t *)new_thread_stack; + /* reserve syscall context, all the registers are copyed from parent */ + stk -= CTX_REG_NR * REGBYTES; + syscall_stk = stk; + + syscall_frame = (struct rt_hw_stack_frame *)stk; + + /* modify user sp */ + syscall_frame->user_sp_exc_stack = (rt_ubase_t)user_stack; + + /* skip ecall */ + syscall_frame->epc += 4; + + /* child return value is 0 */ + syscall_frame->a0 = 0; + syscall_frame->a1 = 0; + + /* build temp thread context */ + stk -= sizeof(struct rt_hw_stack_frame); + + thread_frame = (struct rt_hw_stack_frame *)stk; + + int i; + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)thread_frame)[i] = 0xdeadbeaf; + } + + /* set pc for thread */ + thread_frame->epc = (rt_ubase_t)exit_addr; + + /* set old exception mode as supervisor, because in kernel */ + thread_frame->sstatus = read_csr(sstatus) | SSTATUS_SPP; + thread_frame->sstatus &= ~SSTATUS_SIE; /* must disable interrupt */ + + /* set stack as syscall stack */ + thread_frame->user_sp_exc_stack = (rt_ubase_t)syscall_stk; + + /* save new stack top */ + *thread_sp = (void *)stk; + + /** + * The stack for child thread: + * + * +------------------------+ --> kernel stack top + * | syscall stack | + * | | + * | @sp | --> `user_stack` + * | @epc | --> user ecall addr + 4 (skip ecall) + * | @a0&a1 | --> 0 (for child return 0) + * | | + * +------------------------+ --> temp thread stack top + * | temp thread stack | ^ + * | | | + * | @sp | ---------/ + * | @epc | --> `exit_addr` (sys_clone_exit/sys_fork_exit) + * | | + * +------------------------+ --> thread sp + */ +} + +#endif diff --git a/components/lwp/arch/risc-v/rv64/lwp_arch.h b/components/lwp/arch/risc-v/rv64/lwp_arch.h new file mode 100644 index 0000000000000000000000000000000000000000..e6d09285ab48ed2ae4ecc0372ee78ae529a696bb --- /dev/null +++ b/components/lwp/arch/risc-v/rv64/lwp_arch.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef LWP_ARCH_H__ +#define LWP_ARCH_H__ + +#include + +#ifdef RT_USING_USERSPACE + +#ifdef RT_USING_USERSPACE_32BIT_LIMIT +#define USER_HEAP_VADDR 0xF0000000UL +#define USER_HEAP_VEND 0xFE000000UL +#define USER_STACK_VSTART 0xE0000000UL +#define USER_STACK_VEND USER_HEAP_VADDR +#define USER_VADDR_START 0xC0000000UL +#define USER_VADDR_TOP 0xFF000000UL +#define USER_LOAD_VADDR 0xD0000000UL +#define LDSO_LOAD_VADDR USER_LOAD_VADDR +#else +#define USER_HEAP_VADDR 0x300000000UL +#define USER_HEAP_VEND 0xffffffffffff0000UL +#define USER_STACK_VSTART 0x270000000UL +#define USER_STACK_VEND USER_HEAP_VADDR +#define USER_VADDR_START 0x100000000UL +#define USER_VADDR_TOP 0xfffffffffffff000UL +#define USER_LOAD_VADDR 0x200000000 +#define LDSO_LOAD_VADDR 0x200000000 +#endif + +#define MMU_MAP_U_RWCB 0 +#define MMU_MAP_U_RW 0 + +#ifdef __cplusplus +extern "C" { +#endif + +int arch_user_space_init(struct rt_lwp *lwp); +void arch_user_space_vtable_free(struct rt_lwp *lwp); +void *arch_kernel_mmu_table_get(void); +void arch_kuser_init(rt_mmu_info *mmu_info, void *vectors); +int arch_expand_user_stack(void *addr); + +rt_mmu_info* arch_kernel_get_mmu_info(void); + +rt_inline unsigned long ffz(unsigned long x) +{ + return __builtin_ffs(~x) - 1; +} + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /*LWP_ARCH_H__*/ diff --git a/components/lwp/arch/risc-v/rv64/lwp_gcc.S b/components/lwp/arch/risc-v/rv64/lwp_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..4823d133f3eaf591dbbe278fc94c5b37b41314d7 --- /dev/null +++ b/components/lwp/arch/risc-v/rv64/lwp_gcc.S @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Jesven first version + * 2021-02-03 lizhirui port to riscv64 + * 2021-02-19 lizhirui port to new version of rt-smart + */ + +#include "rtconfig.h" + +#define __ASSEMBLY__ +#include "cpuport.h" +#include "encoding.h" +#include "stackframe.h" + +.section .text.lwp + +/* + * void lwp_user_entry(args, text, ustack, kstack); + */ +.global lwp_user_entry +.type lwp_user_entry, % function +lwp_user_entry: + li t0, SSTATUS_SPP | SSTATUS_SIE // set as user mode, close interrupt + csrc sstatus, t0 + li t0, SSTATUS_SPIE // enable interrupt when return to user mode + csrs sstatus, t0 + + csrw sepc, a1 + mv a3, a2 + sret//enter user mode + +/* + * void lwp_user_thread_entry(args, text, ustack, kstack); + */ +.global lwp_user_thread_entry +.type lwp_user_thread_entry, % function +lwp_user_thread_entry: + li t0, SSTATUS_SPP | SSTATUS_SIE // set as user mode, close interrupt + csrc sstatus, t0 + li t0, SSTATUS_SPIE // enable interrupt when return to user mode + csrs sstatus, t0 + + csrw sepc, a1 + mv s0, a0 + mv s1, a1 + mv s2, a2 + mv s3, a3 + mv a0, s2 + call lwp_copy_return_code_to_user_stack + mv a0, s2 + call lwp_fix_sp + mv sp, a0//user_sp + mv ra, a0//return address + mv a0, s0//args + sret//enter user mode + +.global ret_to_user +ret_to_user: + call lwp_signal_check + beqz a0, ret_to_user_exit + RESTORE_ALL + //now sp is user sp + J user_do_signal + +ret_to_user_exit: + RESTORE_ALL + sret + +/*#ifdef RT_USING_LWP +.global lwp_check_exit +lwp_check_exit: + push {r0 - r12, lr} + bl lwp_check_exit_request + cmp r0, #0 + beq 1f + mov r0, #0 + bl sys_exit +1: + pop {r0 - r12, pc} +#endif*/ + +/*#ifdef RT_USING_GDBSERVER +.global lwp_check_debug +lwp_check_debug: + push {r0 - r12, lr} + bl lwp_check_debug_suspend + cmp r0, #0 + beq lwp_check_debug_quit + + cps #Mode_SYS + sub sp, #8 + ldr r0, =lwp_debugreturn + ldr r1, [r0] + str r1, [sp] + ldr r1, [r0, #4] + str r1, [sp, #4] + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 ;//iciallu + dsb + isb + mov r0, sp // lwp_debugreturn + cps #Mode_SVC + + mrs r1, spsr + push {r1} + mov r1, #Mode_USR + msr spsr_cxsf, r1 + movs pc, r0 +ret_from_user: + cps #Mode_SYS + add sp, #8 + cps #Mode_SVC*/ + /* + pop {r0 - r3, r12} + pop {r4 - r6, lr} + */ + /*add sp, #(4*9) + pop {r4} + msr spsr_cxsf, r4 +lwp_check_debug_quit: + pop {r0 - r12, pc} +//#endif +*/ + +.global lwp_signal_quit +lwp_signal_quit: + call lwp_signal_restore + //a0 is user_ctx + mv sp, a0 + RESTORE_ALL + sret + + +user_do_signal: + //now sp is user sp + //save context to user sp + SAVE_ALL + //ensure original user sp correct + mv t0, sp + addi t0, t0, CTX_REG_NR * REGBYTES + STORE t0, CTX_REG_NR * REGBYTES(sp) + OPEN_INTERRUPT + mv s0, sp + la t0, lwp_sigreturn//t0 = src + la t1, lwp_sigreturn_end + sub t1, t1, t0//t1 = size + sub s0, s0, t1//s0 = dst + +lwp_sigreturn_copy_loop: + addi t2, t1, -1//t2 = memory index + add t3, t0, t2//t3 = src addr + add t4, s0, t2//t4 = dst addr + lb t5, 0(t3) + sb t5, 0(t4) + mv t1, t2 + bnez t1, lwp_sigreturn_copy_loop + + mv a0, sp//sp + li a1, 0//pc + li a2, 0//flag + call lwp_signal_backup + //a0 = signal id + mv sp, s0//update new sp + mv s2, a0//signal id backup + call lwp_sighandler_get//need a0 returned by lwp_signal_backup + mv ra, s0//lwp_sigreturn func addr + mv s1, s0//if func = 0,s1 = lwp_sigreturn func + beqz a0, skip_user_signal_handler + mv s1, a0 + +skip_user_signal_handler: + li t0, 0x100 + csrc sstatus, t0 + csrw sepc, s1 + mv a0, s2//signal id as arg 0 + sret//enter lwp signal handler + +.align 3 +lwp_debugreturn: + li a7, 0xff + ecall + +.align 3 +lwp_sigreturn: + li a7, 0xfe + ecall + +.align 3 +lwp_sigreturn_end: + +.align 3 +.global lwp_thread_return +lwp_thread_return: + li a0, 0 + li a7, 1 + ecall + +.align 3 +.global lwp_thread_return_end +lwp_thread_return_end: + +.global check_vfp +check_vfp: + //don't use fpu temporarily + li a0, 0 + ret + +.global get_vfp +get_vfp: + //don't use fpu temporarily + li a0, 0 + ret + +.globl rt_cpu_get_thread_idr +rt_cpu_get_thread_idr: + mv a0, tp + ret + +.global lwp_set_thread_area +lwp_set_thread_area: +.globl rt_cpu_set_thread_idr +rt_cpu_set_thread_idr: + mv tp, a0 + ret + +.global sys_fork_exit +sys_fork_exit: + j syscall_exit + +.global sys_clone_exit +sys_clone_exit: + j syscall_exit + +.global lwp_exec_user +lwp_exec_user: + ret//don't support diff --git a/components/lwp/arch/risc-v/rv64/reloc.c b/components/lwp/arch/risc-v/rv64/reloc.c new file mode 100644 index 0000000000000000000000000000000000000000..75d17277cd00053c0d13c3056a3eec708eb5fdda --- /dev/null +++ b/components/lwp/arch/risc-v/rv64/reloc.c @@ -0,0 +1,108 @@ +#include +#include +#include +#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +typedef struct +{ + Elf64_Word st_name; + Elf64_Addr st_value; + Elf64_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf64_Half st_shndx; +} Elf64_sym; + +#ifdef RT_USING_USERSPACE +void lwp_elf_reloc(rt_mmu_info *m_info, void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf64_sym *dynsym) +{ + size_t rel_off; + void* addr; + + if (rel_dyn_size && !dynsym) + { + return; + } + for (rel_off = 0; rel_off < rel_dyn_size; rel_off += 8) + { + uint32_t v1, v2; + + addr = rt_hw_mmu_v2p(m_info, (void *)(((rt_size_t)rel_dyn_start) + rel_off)); + memcpy(&v1, addr, 4); + addr = rt_hw_mmu_v2p(m_info, (void *)(((rt_size_t)rel_dyn_start) + rel_off + 4)); + memcpy(&v2, addr, 4); + + addr = rt_hw_mmu_v2p(m_info, (void *)((rt_size_t)text_start + v1)); + if ((v2 & 0xff) == R_ARM_RELATIVE) + { + *(rt_size_t*)addr += (rt_size_t)text_start; + } + else if ((v2 & 0xff) == R_ARM_ABS32) + { + uint32_t t; + t = (v2 >> 8); + if (t) /* 0 is UDF */ + { + *(rt_size_t*)addr = (((rt_size_t)text_start) + dynsym[t].st_value); + } + } + } + /* modify got */ + if (got_size) + { + uint32_t *got_item = (uint32_t*)got_start; + + for (rel_off = 0; rel_off < got_size; rel_off += 4, got_item++) + { + addr = rt_hw_mmu_v2p(m_info, got_item); + *(rt_size_t *)addr += (rt_size_t)text_start; + } + } +} +#else + +void lwp_elf_reloc(void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf64_sym *dynsym) +{ + size_t rel_off; + + if (rel_dyn_size && !dynsym) + { + return; + } + for (rel_off = 0; rel_off < rel_dyn_size; rel_off += 8) + { + uint32_t v1, v2; + + memcpy(&v1, ((rt_uint8_t *)rel_dyn_start) + rel_off, 4); + memcpy(&v2, ((rt_uint8_t *)rel_dyn_start) + rel_off + 4, 4); + + if ((v2 & 0xff) == R_ARM_RELATIVE) + { + *(uint32_t*)(((rt_size_t)text_start) + v1) += (uint32_t)text_start; + } + else if ((v2 & 0xff) == R_ARM_ABS32) + { + uint32_t t; + t = (v2 >> 8); + if (t) /* 0 is UDF */ + { + *(uint32_t*)(((rt_size_t)text_start) + v1) = (uint32_t)(((rt_size_t)text_start) + dynsym[t].st_value); + } + } + } + /* modify got */ + if (got_size) + { + uint32_t *got_item = (uint32_t*)got_start; + + for (rel_off = 0; rel_off < got_size; rel_off += 4, got_item++) + { + *got_item += (uint32_t)text_start; + } + } +} +#endif diff --git a/components/lwp/arch/x86/i386/SConscript b/components/lwp/arch/x86/i386/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c0d3aead777d389ef93caf0803640b8a4d5d89cf --- /dev/null +++ b/components/lwp/arch/x86/i386/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('lwp-x86-i386', src, depend = ['RT_USING_LWP'], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/lwp/arch/x86/i386/lwp_arch.c b/components/lwp/arch/x86/i386/lwp_arch.c new file mode 100644 index 0000000000000000000000000000000000000000..568205955913fce1d6fb27b0a1207e5f4f749ba8 --- /dev/null +++ b/components/lwp/arch/x86/i386/lwp_arch.c @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-7-14 JasonHu first version + */ + +#include +#include +#include +#include + +#ifdef RT_USING_USERSPACE + +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef RT_USING_SIGNALS +#include +#endif /* RT_USING_SIGNALS */ + +extern size_t g_mmu_table[]; + +int arch_expand_user_stack(void *addr) +{ + int ret = 0; + size_t stack_addr = (size_t)addr; + + stack_addr &= ~PAGE_OFFSET_MASK; + if ((stack_addr >= (size_t)USER_STACK_VSTART) && (stack_addr < (size_t)USER_STACK_VEND)) + { + void *map = lwp_map_user(lwp_self(), (void *)stack_addr, PAGE_SIZE, RT_FALSE); + + if (map || lwp_user_accessable(addr, 1)) + { + ret = 1; /* map success */ + } + else /* map failed, send signal SIGSEGV */ + { +#ifdef RT_USING_SIGNALS + dbg_log(DBG_ERROR, "[fault] thread %s mapped addr %p failed!\n", rt_thread_self()->name, addr); + lwp_thread_kill(rt_thread_self(), SIGSEGV); + ret = 1; /* return 1, will return back to intr, then check exit */ +#endif + } + } + else /* not stack, send signal SIGSEGV */ + { +#ifdef RT_USING_SIGNALS + dbg_log(DBG_ERROR, "[fault] thread %s access unmapped addr %p!\n", rt_thread_self()->name, addr); + lwp_thread_kill(rt_thread_self(), SIGSEGV); + ret = 1; /* return 1, will return back to intr, then check exit */ +#endif + } + return ret; +} + +void *get_thread_kernel_stack_top(rt_thread_t thread) +{ + return RT_NULL; +} + +/** + * don't support this in i386, it's ok! + */ +void *lwp_get_user_sp() +{ + return RT_NULL; +} + +int arch_user_space_init(struct rt_lwp *lwp) +{ + rt_size_t *mmu_table; + + mmu_table = (rt_size_t *)rt_pages_alloc(0); + if (!mmu_table) + { + return -1; + } + rt_memset(mmu_table, 0, ARCH_PAGE_SIZE); + + lwp->end_heap = USER_HEAP_VADDR; + memcpy(mmu_table, g_mmu_table, ARCH_PAGE_SIZE / 4); + memset((rt_uint8_t *)mmu_table + ARCH_PAGE_SIZE / 4, 0, ARCH_PAGE_SIZE / 4 * 3); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_table, ARCH_PAGE_SIZE); + if (rt_hw_mmu_map_init(&lwp->mmu_info, (void*)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, mmu_table, PV_OFFSET) < 0) + { + rt_pages_free(mmu_table, 0); + return -1; + } + return 0; +} + +void *arch_kernel_mmu_table_get(void) +{ + return (void *)((char *)g_mmu_table); +} + +void arch_user_space_vtable_free(struct rt_lwp *lwp) +{ + if (lwp && lwp->mmu_info.vtable) + { + rt_pages_free(lwp->mmu_info.vtable, 0); + lwp->mmu_info.vtable = NULL; + } +} + +void lwp_set_thread_area(void *p) +{ + rt_hw_seg_tls_set((rt_ubase_t) p); + rt_thread_t cur = rt_thread_self(); + cur->thread_idr = p; /* update thread idr after first set */ +} + +void *rt_cpu_get_thread_idr(void) +{ + rt_thread_t cur = rt_thread_self(); + if (!cur->lwp) /* no lwp, don't get thread idr from tls seg */ + return NULL; + return (void *)rt_hw_seg_tls_get(); /* get thread idr from tls seg */ +} + +void rt_cpu_set_thread_idr(void *p) +{ + rt_thread_t cur = rt_thread_self(); + if (!cur->lwp) /* no lwp, don't set thread idr to tls seg */ + return; + rt_hw_seg_tls_set((rt_ubase_t) p); /* set tls seg addr as thread idr */ +} + +static void lwp_user_stack_init(rt_hw_stack_frame_t *frame) +{ + frame->ds = frame->es = USER_DATA_SEL; + frame->cs = USER_CODE_SEL; + frame->ss = USER_STACK_SEL; + frame->gs = USER_TLS_SEL; + frame->fs = 0; /* unused */ + + frame->edi = frame->esi = \ + frame->ebp = frame->esp_dummy = 0; + frame->eax = frame->ebx = \ + frame->ecx = frame->edx = 0; + + frame->error_code = 0; + frame->vec_no = 0; + + frame->eflags = (EFLAGS_MBS | EFLAGS_IF_1 | EFLAGS_IOPL_3); +} + +extern void lwp_switch_to_user(void *frame); +/** + * user entry, set frame. + * at the end of execute, we need enter user mode, + * in x86, we can set stack, arg, text entry in a stack frame, + * then pop then into register, final use iret to switch kernel mode to user mode. + */ +void lwp_user_entry(void *args, const void *text, void *ustack, void *k_stack) +{ + rt_uint8_t *stk = k_stack; + stk -= sizeof(struct rt_hw_stack_frame); + struct rt_hw_stack_frame *frame = (struct rt_hw_stack_frame *)stk; + + lwp_user_stack_init(frame); + frame->esp = (rt_uint32_t)ustack - 32; + frame->ebx = (rt_uint32_t)args; + frame->eip = (rt_uint32_t)text; + lwp_switch_to_user(frame); + /* should never return */ +} + +void lwp_exec_user(void *args, void *kernel_stack, void *user_entry) +{ + lwp_user_entry(args, (const void *)user_entry, (void *)USER_STACK_VEND, kernel_stack); +} + +extern void lwp_thread_return(); +extern void lwp_thread_return_end(); + +static void *lwp_copy_return_code_to_user_stack(void *ustack) +{ + size_t size = (size_t)lwp_thread_return_end - (size_t)lwp_thread_return; + void *retcode = (void *)((size_t)ustack - size); + memcpy(retcode, (void *)lwp_thread_return, size); + return retcode; +} + +/** + * when called sys_thread_create, need create a thread, after thread stared, will come here, + * like lwp_user_entry, will enter user mode, but we must set thread exit function. it looks like: + * void func(void *arg) + * { + * ... + * } + * when thread func return, we must call exit code to exit thread, or not the program runs away. + * so we need copy exit code to user and call exit code when func return. + */ +void lwp_user_thread_entry(void *args, const void *text, void *ustack, void *k_stack) +{ + RT_ASSERT(ustack != NULL); + + rt_uint8_t *stk; + stk = (rt_uint8_t *)((rt_uint8_t *)k_stack + sizeof(rt_ubase_t)); + stk = (rt_uint8_t *)RT_ALIGN_DOWN(((rt_ubase_t)stk), sizeof(rt_ubase_t)); + stk -= sizeof(struct rt_hw_stack_frame); + struct rt_hw_stack_frame *frame = (struct rt_hw_stack_frame *)stk; + + lwp_user_stack_init(frame); + + /* make user thread stack */ + unsigned long *retcode = lwp_copy_return_code_to_user_stack(ustack); /* copy ret code */ + unsigned long *retstack = (unsigned long *)RT_ALIGN_DOWN(((rt_ubase_t)retcode), sizeof(rt_ubase_t)); + + /** + * x86 call stack + * + * retcode here + * + * arg n + * arg n - 1 + * ... + * arg 2 + * arg 1 + * arg 0 + * eip (caller return addr, point to retcode) + * esp + */ + *(--retstack) = (unsigned long) args; /* arg */ + *(--retstack) = (unsigned long) retcode; /* ret eip */ + + frame->esp = (rt_uint32_t)retstack; + frame->eip = (rt_uint32_t)text; + lwp_switch_to_user(frame); + /* should never return */ +} + +rt_thread_t rt_thread_sp_to_thread(void *spmember_addr) +{ + return (rt_thread_t)(((rt_ubase_t)spmember_addr) - (offsetof(struct rt_thread, sp))); +} + +/** + * set exec context for fork/clone. + * user_stack(unused) + */ +void lwp_set_thread_context(void *exit_addr, void *new_thread_stack, void *user_stack, void **thread_sp) +{ + /** + * thread kernel stack was set to tss.esp0, when intrrupt/syscall occur, + * the stack frame will store in kernel stack top, so we can get the stack + * frame by kernel stack top. + */ + rt_hw_stack_frame_t *frame = (rt_hw_stack_frame_t *)((rt_ubase_t)new_thread_stack - sizeof(rt_hw_stack_frame_t)); + + frame->eax = 0; /* child return 0 */ + + rt_hw_context_t *context = (rt_hw_context_t *) (((rt_uint32_t *)frame) - HW_CONTEXT_MEMBER_NR); + context->eip = (void *)exit_addr; /* when thread started, jump to intr exit for enter user mode */ + context->ebp = context->ebx = context->esi = context->edi = 0; + + /** + * set sp as the address of first member of rt_hw_context, + * when scheduler call switch, pop stack from context stack. + */ + *thread_sp = (void *)&context->ebp; + + /** + * after set context, the stack like this: + * + * ----------- + * stack frame| eax = 0 + * ----------- + * context(only HW_CONTEXT_MEMBER_NR)| eip = rt_hw_intr_exit + * ----------- + * thread sp | to <- rt_hw_context_switch(from, to) + * ----------- + */ +} + +#ifdef RT_USING_SIGNALS + +#define SIGNAL_RET_CODE_SIZE 16 + +struct rt_signal_frame +{ + char *ret_addr; /* return addr when handler return */ + int signo; /* signal for user handler arg */ + rt_hw_stack_frame_t frame; /* save kernel signal stack */ + char ret_code[SIGNAL_RET_CODE_SIZE]; /* save return code */ +}; +typedef struct rt_signal_frame rt_signal_frame_t; + +extern void lwp_signal_return(); +extern void lwp_signal_return_end(); + +void lwp_try_do_signal(rt_hw_stack_frame_t *frame) +{ + if (!lwp_signal_check()) + return; + + /* 1. backup signal mask */ + int signal = lwp_signal_backup((void *) frame->esp, (void *) frame->eip, (void *) frame->eflags); + + /* 2. get signal handler */ + lwp_sighandler_t handler = lwp_sighandler_get(signal); + if (handler == RT_NULL) /* no handler, ignore */ + { + lwp_signal_restore(); + return; + } + + rt_base_t level = rt_hw_interrupt_disable(); + /* 3. backup frame */ + rt_signal_frame_t *sig_frame = (rt_signal_frame_t *)((frame->esp - sizeof(rt_signal_frame_t)) & -8UL); + memcpy(&sig_frame->frame, frame, sizeof(rt_hw_stack_frame_t)); + sig_frame->signo = signal; + + /** + * 4. copy user return code into user stack + * + * save current frame on user stack. the user stack like: + * + * ---------- + * user code stack + * ----------+ -> esp before enter kernel + * signal frame + * ----------+ -> esp when handle signal handler + * signal handler stack + * ---------- + */ + size_t ret_code_size = (size_t)lwp_signal_return_end - (size_t)lwp_signal_return; + memcpy(sig_frame->ret_code, (void *)lwp_signal_return, ret_code_size); + sig_frame->ret_addr = sig_frame->ret_code; + + /* 5. jmp to user execute handler, update frame register info */ + lwp_user_stack_init(frame); + frame->eip = (rt_uint32_t) handler; + frame->esp = (rt_uint32_t) sig_frame; + + rt_hw_interrupt_enable(level); +} + +void lwp_signal_do_return(rt_hw_stack_frame_t *frame) +{ + /** + * ASSUME: in x86, each stack push and pop element is 4 byte. so STACK_ELEM_SIZE = sizeof(int) => 4. + * when signal handler return, the stack move to the buttom of signal frame. + * but return will pop eip from esp, then {esp += STACK_ELEM_SIZE}, thus {esp = (signal frame) + STACK_ELEM_SIZE}. + * so {(signal frame) = esp - STACK_ELEM_SIZE} + */ + rt_signal_frame_t *sig_frame = (rt_signal_frame_t *)(frame->esp - sizeof(rt_uint32_t)); + memcpy(frame, &sig_frame->frame, sizeof(rt_hw_stack_frame_t)); + + /** + * restore signal info, but don't use rt_user_context, + * we use sig_frame to restore stack frame + */ + lwp_signal_restore(); +} +#endif /* RT_USING_SIGNALS */ + +#endif /* RT_USING_USERSPACE */ diff --git a/components/lwp/arch/x86/i386/lwp_arch.h b/components/lwp/arch/x86/i386/lwp_arch.h new file mode 100644 index 0000000000000000000000000000000000000000..74049be6d0091587ac07274343f728c43574638a --- /dev/null +++ b/components/lwp/arch/x86/i386/lwp_arch.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-18 JasonHu first version + */ + +#ifndef LWP_ARCH_H__ +#define LWP_ARCH_H__ + +#include +#include + +#ifdef RT_USING_USERSPACE +#define USER_VADDR_TOP 0xFFFFF000UL +#define USER_HEAP_VEND 0xE0000000UL +#define USER_HEAP_VADDR 0x90000000UL +#define USER_STACK_VSTART 0x80000000UL +#define USER_STACK_VEND USER_HEAP_VADDR +#define LDSO_LOAD_VADDR 0x70000000UL +#define USER_VADDR_START 0x40000000UL +#define USER_LOAD_VADDR USER_VADDR_START + +#define SIGNAL_RETURN_SYSCAL_ID 0xe000 + +#ifdef __cplusplus +extern "C" { +#endif + +int arch_user_space_init(struct rt_lwp *lwp); +void arch_user_space_vtable_free(struct rt_lwp *lwp); +void *arch_kernel_mmu_table_get(void); +void arch_kuser_init(rt_mmu_info *mmu_info, void *vectors); +int arch_expand_user_stack(void *addr); + +rt_thread_t rt_thread_sp_to_thread(void *spmember_addr); + +void lwp_signal_do_return(rt_hw_stack_frame_t *frame); + +rt_inline unsigned long ffz(unsigned long x) +{ + return __builtin_ffs(~x) - 1; +} + +#ifdef __cplusplus +} +#endif + +#endif /* RT_USING_USERSPACE */ + +#endif /*LWP_ARCH_H__*/ diff --git a/components/lwp/arch/x86/i386/lwp_gcc.S b/components/lwp/arch/x86/i386/lwp_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..bda54e2924365f7e1661124dfe19fb3694748e45 --- /dev/null +++ b/components/lwp/arch/x86/i386/lwp_gcc.S @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-7-14 JasonHu first version + */ + +#include "rtconfig.h" + +.section .text.lwp + +/* + * void lwp_switch_to_user(frame); + */ +.global lwp_switch_to_user +lwp_switch_to_user: + movl 0x4(%esp), %esp + addl $4,%esp // skip intr no + popal + popl %gs + popl %fs + popl %es + popl %ds + addl $4, %esp // skip error_code + iret // enter to user mode + +.extern syscall_exit +.global sys_fork +.global sys_vfork +.global sys_fork_exit +sys_fork: +sys_vfork: + jmp _sys_fork +sys_fork_exit: + jmp syscall_exit + +.global sys_clone +.global sys_clone_exit +sys_clone: + jmp _sys_clone +sys_clone_exit: + jmp syscall_exit + +/** + * rt thread return code + */ +.align 4 +.global lwp_thread_return +lwp_thread_return: + movl $1, %eax // eax = 1, sys_exit + movl $0, %ebx + int $0x80 +.align 4 +.global lwp_thread_return_end +lwp_thread_return_end: + +#ifdef RT_USING_SIGNALS +/** + * signal return code + */ +.align 4 +.global lwp_signal_return +lwp_signal_return: + movl $0xe000, %eax // special syscall id for return code + int $0x80 +.align 4 +.global lwp_signal_return_end +lwp_signal_return_end: + +#endif /* RT_USING_SIGNALS */ diff --git a/components/lwp/arch/x86/i386/reloc.c b/components/lwp/arch/x86/i386/reloc.c new file mode 100644 index 0000000000000000000000000000000000000000..598638461dfcf24494a334f966d2c534ae6d50d5 --- /dev/null +++ b/components/lwp/arch/x86/i386/reloc.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-28 JasonHu first version + */ + +#include +#include +#include +#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +typedef struct +{ + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf32_Half st_shndx; +} Elf32_sym; + +#ifdef RT_USING_USERSPACE +void lwp_elf_reloc(rt_mmu_info *m_info, void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf32_sym *dynsym) +{ + +} +#else + +void lwp_elf_reloc(void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf32_sym *dynsym) +{ + +} +#endif diff --git a/components/lwp/ioremap.c b/components/lwp/ioremap.c new file mode 100644 index 0000000000000000000000000000000000000000..e48e655e2e65a4d42a016976387eba95181e5834 --- /dev/null +++ b/components/lwp/ioremap.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-06 Jesven first version + */ +#include +#include + +#include + +#ifdef RT_USING_USERSPACE +#include +#include + +static struct lwp_avl_struct *k_map_area; +extern rt_mmu_info mmu_info; + +static void _iounmap_range(void *addr, size_t size) +{ + void *va = RT_NULL, *pa = RT_NULL; + int i = 0; + + for (va = addr, i = 0; i < size; va = (void *)((char *)va + ARCH_PAGE_SIZE), i += ARCH_PAGE_SIZE) + { + pa = rt_hw_mmu_v2p(&mmu_info, va); + if (pa) + { + rt_hw_mmu_unmap(&mmu_info, va, ARCH_PAGE_SIZE); + } + } +} + +static void *_ioremap_type(void *paddr, size_t size, int type) +{ + rt_base_t level; + void *v_addr = NULL; + size_t attr; + + switch (type) + { + case MM_AREA_TYPE_PHY: + attr = MMU_MAP_K_DEVICE; + break; + case MM_AREA_TYPE_PHY_CACHED: + attr = MMU_MAP_K_RWCB; + break; + default: + return v_addr; + } + + level = rt_hw_interrupt_disable(); + v_addr = rt_hw_mmu_map(&mmu_info, 0, paddr, size, attr); + if (v_addr) + { + int ret = lwp_map_area_insert(&k_map_area, (size_t)v_addr, size, type); + if (ret != 0) + { + _iounmap_range(v_addr, size); + v_addr = NULL; + } + } + rt_hw_interrupt_enable(level); + return v_addr; +} + +void *rt_ioremap(void *paddr, size_t size) +{ + return _ioremap_type(paddr, size, MM_AREA_TYPE_PHY); +} + +void *rt_ioremap_nocache(void *paddr, size_t size) +{ + return _ioremap_type(paddr, size, MM_AREA_TYPE_PHY); +} + +void *rt_ioremap_cached(void *paddr, size_t size) +{ + return _ioremap_type(paddr, size, MM_AREA_TYPE_PHY_CACHED); +} + +void rt_iounmap(volatile void *vaddr) +{ + rt_base_t level; + struct lwp_avl_struct *ma_avl_node; + + level = rt_hw_interrupt_disable(); + ma_avl_node = lwp_map_find(k_map_area, (size_t)vaddr); + if (ma_avl_node) + { + struct rt_mm_area_struct *ma = (struct rt_mm_area_struct *)ma_avl_node->data; + + _iounmap_range((void *)ma->addr, ma->size); + lwp_map_area_remove(&k_map_area, (size_t)vaddr); + } + rt_hw_interrupt_enable(level); +} + +#else +void *rt_ioremap(void *paddr, size_t size) +{ + return paddr; +} + +void *rt_ioremap_nocache(void *paddr, size_t size) +{ + return paddr; +} + +void *rt_ioremap_cached(void *paddr, size_t size) +{ + return paddr; +} + +void rt_iounmap(volatile void *vaddr) +{ +} +#endif diff --git a/components/lwp/ioremap.h b/components/lwp/ioremap.h new file mode 100644 index 0000000000000000000000000000000000000000..a2d64523f102f97d883967d67332fa8147e2a4f4 --- /dev/null +++ b/components/lwp/ioremap.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-06 Jesven first version + */ +#ifndef __IOREMAP_H__ +#define __IOREMAP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +void *rt_ioremap(void *paddr, size_t size); +void *rt_ioremap_nocache(void *paddr, size_t size); +void *rt_ioremap_cached (void *paddr, size_t size); +void rt_iounmap(volatile void *addr); + +#ifdef __cplusplus +} +#endif + +#endif /*__LWP_IOREMAP_H__*/ diff --git a/components/lwp/lwp.c b/components/lwp/lwp.c index 7881fcc68fa1461bee7aabc561855eb43e093954..e2c197973f762aa2e34eb3598e583b5482b27d16 100644 --- a/components/lwp/lwp.c +++ b/components/lwp/lwp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,372 +7,1325 @@ * Date Author Notes * 2006-03-12 Bernard first version * 2018-11-02 heyuanjie fix complie error in iar + * 2021-02-03 lizhirui add 64-bit arch support and riscv64 arch support + * 2021-08-26 linzhenxing add lwp_setcwd\lwp_getcwd */ -#include #include +#include + #include +#include #ifndef RT_USING_DFS - #error "lwp need file system(RT_USING_DFS)" +#error "lwp need file system(RT_USING_DFS)" #endif #include "lwp.h" +#include "lwp_arch.h" +#include "console.h" -#define DBG_TAG "LWP" -#define DBG_LVL DBG_WARNING +#define DBG_TAG "LWP" +#define DBG_LVL DBG_WARNING #include -extern void lwp_user_entry(void *args, const void *text, void *data); +#ifdef RT_USING_USERSPACE +#ifdef RT_USING_GDBSERVER +#include +#include +#endif + +#include +#include +#endif /* end of RT_USING_USERSPACE */ + +static const char elf_magic[] = {0x7f, 'E', 'L', 'F'}; +#ifdef DFS_USING_WORKDIR +extern char working_directory[]; +#endif +struct termios stdin_termios, old_stdin_termios; + +extern void lwp_user_entry(void *args, const void *text, void *ustack, void *k_stack); +int load_ldso(struct rt_lwp *lwp, char *exec_name, char *const argv[], char *const envp[]); + +void lwp_setcwd(char *buf) +{ + struct rt_lwp *lwp = RT_NULL; + + if(strlen(buf) >= DFS_PATH_MAX) + { + rt_kprintf("buf too long!\n"); + return ; + } + + lwp = (struct rt_lwp *)rt_thread_self()->lwp; + if (lwp) + { + rt_strncpy(lwp->working_directory, buf, DFS_PATH_MAX); + } + else + { + rt_strncpy(working_directory, buf, DFS_PATH_MAX); + } + + return ; +} + +char *lwp_getcwd(void) +{ + char *dir_buf = RT_NULL; + struct rt_lwp *lwp = RT_NULL; + + lwp = (struct rt_lwp *)rt_thread_self()->lwp; + if (lwp) + { + if(lwp->working_directory[0] != '/') + { + dir_buf = &working_directory[0]; + } + else + { + dir_buf = &lwp->working_directory[0]; + } + } + else + dir_buf = &working_directory[0]; + + return dir_buf; +} /** * RT-Thread light-weight process */ void lwp_set_kernel_sp(uint32_t *sp) { - struct rt_lwp *user_data; - user_data = (struct rt_lwp *)rt_thread_self()->lwp; - user_data->kernel_sp = sp; + rt_thread_self()->kernel_sp = (rt_uint32_t *)sp; } uint32_t *lwp_get_kernel_sp(void) { - struct rt_lwp *user_data; - user_data = (struct rt_lwp *)rt_thread_self()->lwp; - - return user_data->kernel_sp; +#ifdef RT_USING_USERSPACE + return (uint32_t *)rt_thread_self()->sp; +#else + uint32_t* kernel_sp; + extern rt_uint32_t rt_interrupt_from_thread; + extern rt_uint32_t rt_thread_switch_interrupt_flag; + if (rt_thread_switch_interrupt_flag) + { + kernel_sp = (uint32_t *)((rt_thread_t)rt_container_of(rt_interrupt_from_thread, struct rt_thread, sp))->kernel_sp; + } + else + { + kernel_sp = (uint32_t *)rt_thread_self()->kernel_sp; + } + return kernel_sp; +#endif } -static int lwp_argscopy(struct rt_lwp *lwp, int argc, char **argv) +#ifdef RT_USING_USERSPACE +struct process_aux *lwp_argscopy(struct rt_lwp *lwp, int argc, char **argv, char **envp) +{ + int size = sizeof(size_t) * 5; /* store argc, argv, envp, aux, NULL */ + int *args; + char *str; + char *str_k; + char **new_argve; + int i; + int len; + size_t *args_k; + struct process_aux *aux; + + for (i = 0; i < argc; i++) + { + size += (rt_strlen(argv[i]) + 1); + } + size += (sizeof(size_t) * argc); + + i = 0; + if (envp) + { + while (envp[i] != 0) + { + size += (rt_strlen(envp[i]) + 1); + size += sizeof(size_t); + i++; + } + } + + /* for aux */ + size += sizeof(struct process_aux); + + if (size > ARCH_PAGE_SIZE) + { + return RT_NULL; + } + + /* args = (int *)lwp_map_user(lwp, 0, size); */ + args = (int *)lwp_map_user(lwp, (void *)(USER_VADDR_TOP - ARCH_PAGE_SIZE), size, 0); + if (args == RT_NULL) + { + return RT_NULL; + } + + args_k = (size_t *)rt_hw_mmu_v2p(&lwp->mmu_info, args); + args_k = (size_t *)((size_t)args_k - PV_OFFSET); + + /* argc, argv[], 0, envp[], 0 , aux[] */ + str = (char *)((size_t)args + (argc + 2 + i + 1 + AUX_ARRAY_ITEMS_NR * 2 + 1) * sizeof(size_t)); + str_k = (char *)((size_t)args_k + (argc + 2 + i + 1 + AUX_ARRAY_ITEMS_NR * 2 + 1) * sizeof(size_t)); + + new_argve = (char **)&args_k[1]; + args_k[0] = argc; + + for (i = 0; i < argc; i++) + { + len = rt_strlen(argv[i]) + 1; + new_argve[i] = str; + rt_memcpy(str_k, argv[i], len); + str += len; + str_k += len; + } + new_argve[i] = 0; + i++; + + new_argve[i] = 0; + if (envp) + { + int j; + + for (j = 0; envp[j] != 0; j++) + { + len = rt_strlen(envp[j]) + 1; + new_argve[i] = str; + rt_memcpy(str_k, envp[j], len); + str += len; + str_k += len; + i++; + } + new_argve[i] = 0; + } + i++; + + /* aux */ + aux = (struct process_aux *)(new_argve + i); + aux->item[0].key = AT_EXECFN; + aux->item[0].value = (size_t)(size_t)new_argve[0]; + i += AUX_ARRAY_ITEMS_NR * 2; + new_argve[i] = 0; + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, args_k, size); + + lwp->args = args; + + return aux; +} +#else +static struct process_aux *lwp_argscopy(struct rt_lwp *lwp, int argc, char **argv, char **envp) { - int size = sizeof(int)*3; /* store argc, argv, NULL */ +#ifdef ARCH_MM_MMU + int size = sizeof(int) * 5; /* store argc, argv, envp, aux, NULL */ + struct process_aux *aux; +#else + int size = sizeof(int) * 4; /* store argc, argv, envp, NULL */ +#endif /* ARCH_MM_MMU */ int *args; char *str; - char **new_argv; + char **new_argve; int i; int len; - for (i = 0; i < argc; i ++) + for (i = 0; i < argc; i++) { size += (rt_strlen(argv[i]) + 1); } - size += (sizeof(int) * argc); + size += (sizeof(int) * argc); + + i = 0; + if (envp) + { + while (envp[i] != 0) + { + size += (rt_strlen(envp[i]) + 1); + size += sizeof(int); + i++; + } + } - args = (int*)rt_malloc(size); +#ifdef ARCH_MM_MMU + /* for aux */ + size += sizeof(struct process_aux); + + args = (int *)rt_malloc(size); if (args == RT_NULL) - return -1; + { + return RT_NULL; + } - str = (char*)((int)args + (argc + 3) * sizeof(int)); - new_argv = (char**)&args[2]; + /* argc, argv[], 0, envp[], 0 */ + str = (char *)((size_t)args + (argc + 2 + i + 1 + AUX_ARRAY_ITEMS_NR * 2 + 1) * sizeof(int)); +#else + args = (int *)rt_malloc(size); + if (args == RT_NULL) + { + return RT_NULL; + } + str = (char*)((int)args + (argc + 2 + i + 1) * sizeof(int)); +#endif /* ARCH_MM_MMU */ + + new_argve = (char **)&args[1]; args[0] = argc; - args[1] = (int)new_argv; - for (i = 0; i < argc; i ++) + for (i = 0; i < argc; i++) { len = rt_strlen(argv[i]) + 1; - new_argv[i] = str; + new_argve[i] = str; rt_memcpy(str, argv[i], len); str += len; } - new_argv[i] = 0; + new_argve[i] = 0; + i++; + + new_argve[i] = 0; + if (envp) + { + int j; + for (j = 0; envp[j] != 0; j++) + { + len = rt_strlen(envp[j]) + 1; + new_argve[i] = str; + rt_memcpy(str, envp[j], len); + str += len; + i++; + } + new_argve[i] = 0; + } +#ifdef ARCH_MM_MMU + /* aux */ + aux = (struct process_aux *)(new_argve + i); + aux->item[0].key = AT_EXECFN; + aux->item[0].value = (uint32_t)(size_t)new_argve[0]; + i += AUX_ARRAY_ITEMS_NR * 2; + new_argve[i] = 0; + lwp->args = args; - return 0; + return aux; +#else + lwp->args = args; + lwp->args_length = size; + + return (struct process_aux *)(new_argve + i); +#endif /* ARCH_MM_MMU */ } +#endif + +#ifdef ARCH_MM_MMU +#define check_off(voff, vlen) \ + do \ + { \ + if (voff > vlen) \ + { \ + result = -RT_ERROR; \ + goto _exit; \ + } \ + } while (0) -static int lwp_load(const char *filename, struct rt_lwp *lwp, uint8_t *load_addr, size_t addr_size) +#define check_read(vrlen, vrlen_want) \ + do \ + { \ + if (vrlen < vrlen_want) \ + { \ + result = -RT_ERROR; \ + goto _exit; \ + } \ + } while (0) + +static size_t load_fread(void *ptr, size_t size, size_t nmemb, int fd) { - int fd; - uint8_t *ptr; - int result = RT_EOK; - int nbytes; - struct lwp_header header; - struct lwp_chunk chunk; + size_t read_block = 0; - /* check file name */ - RT_ASSERT(filename != RT_NULL); - /* check lwp control block */ - RT_ASSERT(lwp != RT_NULL); + while (nmemb) + { + size_t count; - if (load_addr != RT_NULL) + count = read(fd, ptr, size * nmemb) / size; + if (count < nmemb) + { + LOG_E("ERROR: file size error!"); + break; + } + + ptr = (void *)((uint8_t *)ptr + (count * size)); + nmemb -= count; + read_block += count; + } + + return read_block; +} + +typedef struct +{ + Elf_Word st_name; + Elf_Addr st_value; + Elf_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf_Half st_shndx; +} Elf_sym; + +#ifdef RT_USING_USERSPACE +void lwp_elf_reloc(rt_mmu_info *m_info, void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf_sym *dynsym); +#else +void lwp_elf_reloc(void *text_start, void *rel_dyn_start, size_t rel_dyn_size, void *got_start, size_t got_size, Elf_sym *dynsym); +#endif + +#ifdef RT_USING_USERSPACE +struct map_range +{ + void *start; + size_t size; +}; + +static void expand_map_range(struct map_range *m, void *start, size_t size) +{ + if (!m->start) { - lwp->lwp_type = LWP_TYPE_FIX_ADDR; - ptr = load_addr; + m->start = start; + m->size = size; } else { - lwp->lwp_type = LWP_TYPE_DYN_ADDR; - ptr = RT_NULL; + void *end = (void *)((char*)start + size); + void *mend = (void *)((char*)m->start + m->size); + + if (m->start > start) + { + m->start = start; + } + if (mend < end) + { + mend = end; + } + m->size = (char *)mend - (char *)m->start; + } +} + +static int map_range_ckeck(struct map_range *m1, struct map_range *m2) +{ + void *m1_start = (void *)((size_t)m1->start & ~ARCH_PAGE_MASK); + void *m1_end = (void *)((((size_t)m1->start + m1->size) + ARCH_PAGE_MASK) & ~ARCH_PAGE_MASK); + void *m2_start = (void *)((size_t)m2->start & ~ARCH_PAGE_MASK); + void *m2_end = (void *)((((size_t)m2->start + m2->size) + ARCH_PAGE_MASK) & ~ARCH_PAGE_MASK); + + if (m1->size) + { + if (m1_start < (void *)USER_LOAD_VADDR) + { + return -1; + } + if (m1_start > (void *)USER_STACK_VSTART) + { + return -1; + } + if (m1_end < (void *)USER_LOAD_VADDR) + { + return -1; + } + if (m1_end > (void *)USER_STACK_VSTART) + { + return -1; + } + } + if (m2->size) + { + if (m2_start < (void *)USER_LOAD_VADDR) + { + return -1; + } + if (m2_start > (void *)USER_STACK_VSTART) + { + return -1; + } + if (m2_end < (void *)USER_LOAD_VADDR) + { + return -1; + } + if (m2_end > (void *)USER_STACK_VSTART) + { + return -1; + } } - /* open lwp */ - fd = open(filename, 0, O_RDONLY); - if (fd < 0) + if ((m1->size != 0) && (m2->size != 0)) { - dbg_log(DBG_ERROR, "open file:%s failed!\n", filename); - result = -RT_ENOSYS; - goto _exit; + if (m1_start < m2_start) + { + if (m1_end > m2_start) + { + return -1; + } + } + else /* m2_start <= m1_start */ + { + if (m2_end > m1_start) + { + return -1; + } + } } + return 0; +} +#endif - /* read lwp header */ - nbytes = read(fd, &header, sizeof(struct lwp_header)); - if (nbytes != sizeof(struct lwp_header)) +static int load_elf(int fd, int len, struct rt_lwp *lwp, uint8_t *load_addr, struct process_aux *aux) +{ + uint32_t i; + uint32_t off = 0; + size_t load_off = 0; + char *p_section_str = 0; + Elf_sym *dynsym = 0; + Elf_Ehdr eheader; + Elf_Phdr pheader; + Elf_Shdr sheader; + int result = RT_EOK; + uint32_t magic; + size_t read_len; + void *got_start = 0; + size_t got_size = 0; + void *rel_dyn_start = 0; + size_t rel_dyn_size = 0; + size_t dynsym_off = 0; + size_t dynsym_size = 0; +#ifdef RT_USING_USERSPACE + struct map_range user_area[2] = {{NULL, 0}, {NULL, 0}}; /* 0 is text, 1 is data */ + void *pa, *va; + void *va_self; + + rt_mmu_info *m_info = &lwp->mmu_info; +#endif + + if (len < sizeof eheader) { - dbg_log(DBG_ERROR, "read lwp header return error size: %d!\n", nbytes); - result = -RT_EIO; - goto _exit; + return -RT_ERROR; } - /* check file header */ - if (header.magic != LWP_MAGIC) + lseek(fd, 0, SEEK_SET); + read_len = load_fread(&magic, 1, sizeof magic, fd); + check_read(read_len, sizeof magic); + + if (memcmp(elf_magic, &magic, 4) != 0) { - dbg_log(DBG_ERROR, "erro header magic number: 0x%02X\n", header.magic); - result = -RT_EINVAL; - goto _exit; + return -RT_ERROR; } - /* read text chunk info */ - nbytes = read(fd, &chunk, sizeof(struct lwp_chunk)); - if (nbytes != sizeof(struct lwp_chunk)) + lseek(fd, off, SEEK_SET); + read_len = load_fread(&eheader, 1, sizeof eheader, fd); + check_read(read_len, sizeof eheader); + +#ifndef ARCH_CPU_64BIT + if (eheader.e_ident[4] != 1) + { /* not 32bit */ + return -RT_ERROR; + } +#else + if (eheader.e_ident[4] != 2) + { /* not 64bit */ + return -RT_ERROR; + } +#endif + + if (eheader.e_ident[6] != 1) + { /* ver not 1 */ + return -RT_ERROR; + } + + if ((eheader.e_type != ET_DYN) +#ifdef RT_USING_USERSPACE + && (eheader.e_type != ET_EXEC) +#endif + ) { - dbg_log(DBG_ERROR, "read text chunk info failed!\n"); - result = -RT_EIO; - goto _exit; + /* not pie or exec elf */ + return -RT_ERROR; } - dbg_log(DBG_LOG, "chunk name: %s, total len %d, data %d, need space %d!\n", - "text", /*chunk.name*/ chunk.total_len, chunk.data_len, chunk.data_len_space); +#ifdef RT_USING_USERSPACE + { + off = eheader.e_phoff; + for (i = 0; i < eheader.e_phnum; i++, off += sizeof pheader) + { + check_off(off, len); + lseek(fd, off, SEEK_SET); + read_len = load_fread(&pheader, 1, sizeof pheader, fd); + check_read(read_len, sizeof pheader); + + if (pheader.p_type == PT_DYNAMIC) + { + /* load ld.so */ + return 1; /* 1 means dynamic */ + } + } + } +#endif - /* load text */ + if (eheader.e_entry != 0) { - lwp->text_size = RT_ALIGN(chunk.data_len_space, 4); - if (load_addr) - lwp->text_entry = ptr; - else + if ((eheader.e_entry != USER_LOAD_VADDR) + && (eheader.e_entry != LDSO_LOAD_VADDR)) { -#ifdef RT_USING_CACHE - lwp->text_entry = (rt_uint8_t *)rt_malloc_align(lwp->text_size, RT_CPU_CACHE_LINE_SZ); + /* the entry is invalidate */ + return -RT_ERROR; + } + } + + { /* load aux */ + uint8_t *process_header; + size_t process_header_size; + + off = eheader.e_phoff; + process_header_size = eheader.e_phnum * sizeof pheader; +#ifdef RT_USING_USERSPACE + if (process_header_size > ARCH_PAGE_SIZE - sizeof(char[16])) + { + return -RT_ERROR; + } + va = (uint8_t *)lwp_map_user(lwp, (void *)(USER_VADDR_TOP - ARCH_PAGE_SIZE * 2), process_header_size, 0); + if (!va) + { + return -RT_ERROR; + } + pa = rt_hw_mmu_v2p(m_info, va); + process_header = (uint8_t *)pa - PV_OFFSET; +#else + process_header = (uint8_t *)rt_malloc(process_header_size + sizeof(char[16])); + if (!process_header) + { + return -RT_ERROR; + } +#endif + check_off(off, len); + lseek(fd, off, SEEK_SET); + read_len = load_fread(process_header, 1, process_header_size, fd); + check_read(read_len, process_header_size); +#ifdef RT_USING_USERSPACE + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, process_header, process_header_size); +#endif + + aux->item[1].key = AT_PAGESZ; +#ifdef RT_USING_USERSPACE + aux->item[1].value = ARCH_PAGE_SIZE; #else - lwp->text_entry = (rt_uint8_t *)rt_malloc(lwp->text_size); + aux->item[1].value = RT_MM_PAGE_SIZE; #endif + aux->item[2].key = AT_RANDOM; + { + uint32_t random_value = rt_tick_get(); + uint8_t *random; +#ifdef RT_USING_USERSPACE + uint8_t *krandom; + + random = (uint8_t *)(USER_VADDR_TOP - ARCH_PAGE_SIZE - sizeof(char[16])); - if (lwp->text_entry == RT_NULL) + krandom = (uint8_t *)rt_hw_mmu_v2p(m_info, random); + krandom = (uint8_t *)krandom - PV_OFFSET; + rt_memcpy(krandom, &random_value, sizeof random_value); +#else + random = (uint8_t *)(process_header + process_header_size); + rt_memcpy(random, &random_value, sizeof random_value); +#endif + aux->item[2].value = (size_t)random; + } + aux->item[3].key = AT_PHDR; +#ifdef RT_USING_USERSPACE + aux->item[3].value = (size_t)va; +#else + aux->item[3].value = (size_t)process_header; +#endif + aux->item[4].key = AT_PHNUM; + aux->item[4].value = eheader.e_phnum; + aux->item[5].key = AT_PHENT; + aux->item[5].value = sizeof pheader; +#ifdef RT_USING_USERSPACE + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, aux, sizeof *aux); +#endif + } + + if (load_addr) + { + load_off = (size_t)load_addr; + } +#ifdef RT_USING_USERSPACE + else + { + /* map user */ + off = eheader.e_shoff; + for (i = 0; i < eheader.e_shnum; i++, off += sizeof sheader) + { + check_off(off, len); + lseek(fd, off, SEEK_SET); + read_len = load_fread(&sheader, 1, sizeof sheader, fd); + check_read(read_len, sizeof sheader); + + if ((sheader.sh_flags & SHF_ALLOC) == 0) { - dbg_log(DBG_ERROR, "alloc text memory faild!\n"); - result = -RT_ENOMEM; - goto _exit; + continue; } - else + + switch (sheader.sh_type) { - dbg_log(DBG_LOG, "lwp text malloc : %p, size: %d!\n", lwp->text_entry, lwp->text_size); + case SHT_PROGBITS: + if ((sheader.sh_flags & SHF_WRITE) == 0) + { + expand_map_range(&user_area[0], (void *)sheader.sh_addr, sheader.sh_size); + } + else + { + expand_map_range(&user_area[1], (void *)sheader.sh_addr, sheader.sh_size); + } + break; + case SHT_NOBITS: + expand_map_range(&user_area[1], (void *)sheader.sh_addr, sheader.sh_size); + break; + default: + expand_map_range(&user_area[1], (void *)sheader.sh_addr, sheader.sh_size); + break; } } - dbg_log(DBG_INFO, "load text %d => (0x%08x, 0x%08x)\n", lwp->text_size, (uint32_t)lwp->text_entry, (uint32_t)lwp->text_entry + lwp->text_size); - nbytes = read(fd, lwp->text_entry, chunk.data_len); - if (nbytes != chunk.data_len) + if (user_area[0].size == 0) { - dbg_log(DBG_ERROR, "read text region from file failed!\n"); - result = -RT_EIO; + /* no code */ + result = -RT_ERROR; goto _exit; } -#ifdef RT_USING_CACHE - else + + if (user_area[0].start == NULL) { - rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lwp->text_entry, lwp->text_size); - rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, lwp->text_entry, lwp->text_size); + /* DYN */ + load_off = USER_LOAD_VADDR; + user_area[0].start = (void *)((char*)user_area[0].start + load_off); + user_area[1].start = (void *)((char*)user_area[1].start + load_off); } -#endif - if (ptr != RT_NULL) ptr += nbytes; + if (map_range_ckeck(&user_area[0], &user_area[1]) != 0) + { + result = -RT_ERROR; + goto _exit; + } - /* skip text hole */ - if ((chunk.total_len - sizeof(struct lwp_chunk) - chunk.data_len)) + /* text and data */ + for (i = 0; i < 2; i++) { - dbg_log(DBG_LOG, "skip text hole %d!\n", (chunk.total_len - sizeof(struct lwp_chunk) - chunk.data_len)); - lseek(fd, (chunk.total_len - sizeof(struct lwp_chunk) - chunk.data_len), SEEK_CUR); + if (user_area[i].size != 0) + { + va = lwp_map_user(lwp, user_area[i].start, user_area[i].size, (int)(i == 0)); + if (!va || (va != user_area[i].start)) + { + result = -RT_ERROR; + goto _exit; + } + } } + lwp->text_size = user_area[0].size; } - - /* load data */ - nbytes = read(fd, &chunk, sizeof(struct lwp_chunk)); - if (nbytes != sizeof(struct lwp_chunk)) +#else + else { - dbg_log(DBG_ERROR, "read data chunk info failed!\n"); - result = -RT_EIO; - goto _exit; - } - - dbg_log(DBG_LOG, "chunk name: %s, total len %d, data %d, need space %d!\n", - chunk.name, chunk.total_len, chunk.data_len, chunk.data_len_space); + size_t start = -1UL; + size_t end = 0UL; + size_t total_size; - { - lwp->data_size = RT_ALIGN(chunk.data_len_space, 4); - if (load_addr) - lwp->data = ptr; - else + off = eheader.e_shoff; + for (i = 0; i < eheader.e_shnum; i++, off += sizeof sheader) { - lwp->data = rt_malloc(lwp->data_size); - if (lwp->data == RT_NULL) + check_off(off, len); + lseek(fd, off, SEEK_SET); + read_len = load_fread(&sheader, 1, sizeof sheader, fd); + check_read(read_len, sizeof sheader); + + if ((sheader.sh_flags & SHF_ALLOC) == 0) { - dbg_log(DBG_ERROR, "alloc data memory faild!\n"); - result = -RT_ENOMEM; - goto _exit; + continue; } - else + + switch (sheader.sh_type) { - dbg_log(DBG_LOG, "lwp data malloc : %p, size: %d!\n", lwp->data, lwp->data_size); - rt_memset(lwp->data, 0, lwp->data_size); + case SHT_PROGBITS: + case SHT_NOBITS: + if (start > sheader.sh_addr) + { + start = sheader.sh_addr; + } + if (sheader.sh_addr + sheader.sh_size > end) + { + end = sheader.sh_addr + sheader.sh_size; + } + break; + default: + break; } } - dbg_log(DBG_INFO, "load data %d => (0x%08x, 0x%08x)\n", lwp->data_size, (uint32_t)lwp->data, (uint32_t)lwp->data + lwp->data_size); - nbytes = read(fd, lwp->data, chunk.data_len); - if (nbytes != chunk.data_len) + total_size = end - start; + +#ifdef RT_USING_CACHE + load_off = (size_t)rt_malloc_align(total_size, RT_CPU_CACHE_LINE_SZ); +#else + load_off = (size_t)rt_malloc(total_size); +#endif + if (load_off == 0) { - dbg_log(DBG_ERROR, "read data region from file failed!\n"); - result = -RT_ERROR; + LOG_E("alloc text memory faild!"); + result = -RT_ENOMEM; goto _exit; } + else + { + LOG_D("lwp text malloc : %p, size: %d!", (void *)load_off, lwp->text_size); + } + lwp->load_off = load_off; /* for free */ + lwp->text_size = total_size; } +#endif + lwp->text_entry = (void *)(eheader.e_entry + load_off); -_exit: - if (fd >= 0) - close(fd); - - if (result != RT_EOK) + off = eheader.e_phoff; + for (i = 0; i < eheader.e_phnum; i++, off += sizeof pheader) { - if (lwp->lwp_type == LWP_TYPE_DYN_ADDR) + check_off(off, len); + lseek(fd, off, SEEK_SET); + read_len = load_fread(&pheader, 1, sizeof pheader, fd); + check_read(read_len, sizeof pheader); + + if (pheader.p_type == PT_LOAD) { - dbg_log(DBG_ERROR, "lwp dynamic load faild, %d\n", result); - if (lwp->text_entry) + if (pheader.p_filesz > pheader.p_memsz) { - dbg_log(DBG_LOG, "lwp text free: %p\n", lwp->text_entry); -#ifdef RT_USING_CACHE - rt_free_align(lwp->text_entry); + return -RT_ERROR; + } + + check_off(pheader.p_offset, len); + lseek(fd, pheader.p_offset, SEEK_SET); +#ifdef RT_USING_USERSPACE + { + uint32_t size = pheader.p_filesz; + size_t tmp_len = 0; + + va = (void *)(pheader.p_vaddr + load_addr); + read_len = 0; + while (size) + { + pa = rt_hw_mmu_v2p(m_info, va); + va_self = (void *)((char *)pa - PV_OFFSET); + LOG_D("va_self = %p pa = %p", va_self, pa); + tmp_len = (size < ARCH_PAGE_SIZE) ? size : ARCH_PAGE_SIZE; + tmp_len = load_fread(va_self, 1, tmp_len, fd); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, va_self, tmp_len); + read_len += tmp_len; + size -= tmp_len; + va = (void *)((char *)va + ARCH_PAGE_SIZE); + } + } +#else + read_len = load_fread((void*)(pheader.p_vaddr + load_off), 1, pheader.p_filesz, fd); +#endif + check_read(read_len, pheader.p_filesz); + + if (pheader.p_filesz < pheader.p_memsz) + { +#ifdef RT_USING_USERSPACE + uint32_t size = pheader.p_memsz - pheader.p_filesz; + uint32_t size_s; + uint32_t off; + + off = pheader.p_filesz & ARCH_PAGE_MASK; + va = (void *)((pheader.p_vaddr + pheader.p_filesz + load_off) & ~ARCH_PAGE_MASK); + while (size) + { + size_s = (size < ARCH_PAGE_SIZE - off) ? size : ARCH_PAGE_SIZE - off; + pa = rt_hw_mmu_v2p(m_info, va); + va_self = (void *)((char *)pa - PV_OFFSET); + memset((void *)((char *)va_self + off), 0, size_s); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)((char *)va_self + off), size_s); + off = 0; + size -= size_s; + va = (void *)((char *)va + ARCH_PAGE_SIZE); + } #else - rt_free(lwp->text_entry); + memset((uint8_t *)pheader.p_vaddr + pheader.p_filesz + load_off, 0, (size_t)(pheader.p_memsz - pheader.p_filesz)); #endif } - if (lwp->data) + } + } + + /* relocate */ + if (eheader.e_type == ET_DYN) + { + /* section info */ + off = eheader.e_shoff; + /* find section string table */ + check_off(off, len); + lseek(fd, off + (sizeof sheader) * eheader.e_shstrndx, SEEK_SET); + read_len = load_fread(&sheader, 1, sizeof sheader, fd); + check_read(read_len, sizeof sheader); + + p_section_str = (char *)rt_malloc(sheader.sh_size); + if (!p_section_str) + { + LOG_E("out of memory!"); + result = -ENOMEM; + goto _exit; + } + + check_off(sheader.sh_offset, len); + lseek(fd, sheader.sh_offset, SEEK_SET); + read_len = load_fread(p_section_str, 1, sheader.sh_size, fd); + check_read(read_len, sheader.sh_size); + + check_off(off, len); + lseek(fd, off, SEEK_SET); + for (i = 0; i < eheader.e_shnum; i++, off += sizeof sheader) + { + read_len = load_fread(&sheader, 1, sizeof sheader, fd); + check_read(read_len, sizeof sheader); + + if (strcmp(p_section_str + sheader.sh_name, ".got") == 0) + { + got_start = (void *)((uint8_t *)sheader.sh_addr + load_off); + got_size = (size_t)sheader.sh_size; + } + else if (strcmp(p_section_str + sheader.sh_name, ".rel.dyn") == 0) { - dbg_log(DBG_LOG, "lwp data free: %p\n", lwp->data); - rt_free(lwp->data); + rel_dyn_start = (void *)((uint8_t *)sheader.sh_addr + load_off); + rel_dyn_size = (size_t)sheader.sh_size; } + else if (strcmp(p_section_str + sheader.sh_name, ".dynsym") == 0) + { + dynsym_off = (size_t)sheader.sh_offset; + dynsym_size = (size_t)sheader.sh_size; + } + } + /* reloc */ + if (dynsym_size) + { + dynsym = rt_malloc(dynsym_size); + if (!dynsym) + { + LOG_E("ERROR: Malloc error!"); + result = -ENOMEM; + goto _exit; + } + check_off(dynsym_off, len); + lseek(fd, dynsym_off, SEEK_SET); + read_len = load_fread(dynsym, 1, dynsym_size, fd); + check_read(read_len, dynsym_size); } +#ifdef RT_USING_USERSPACE + lwp_elf_reloc(m_info, (void *)load_off, rel_dyn_start, rel_dyn_size, got_start, got_size, dynsym); +#else + lwp_elf_reloc((void *)load_off, rel_dyn_start, rel_dyn_size, got_start, got_size, dynsym); + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lwp->text_entry, lwp->text_size); + rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, lwp->text_entry, lwp->text_size); +#endif } + LOG_D("lwp->text_entry = 0x%p", lwp->text_entry); + LOG_D("lwp->text_size = 0x%p", lwp->text_size); +_exit: + if (dynsym) + { + rt_free(dynsym); + } + if (p_section_str) + { + rt_free(p_section_str); + } + if (result != RT_EOK) + { + LOG_E("lwp load faild, %d", result); + } return result; } +#endif /* ARCH_MM_MMU */ -static void lwp_cleanup(struct rt_thread *tid) +RT_WEAK int lwp_load(const char *filename, struct rt_lwp *lwp, uint8_t *load_addr, size_t addr_size, struct process_aux *aux) { - struct rt_lwp *lwp; + uint8_t *ptr; + int ret = -1; + int len; + int fd = -1; - dbg_log(DBG_INFO, "thread: %s, stack_addr: %08X\n", tid->name, tid->stack_addr); + /* check file name */ + RT_ASSERT(filename != RT_NULL); + /* check lwp control block */ + RT_ASSERT(lwp != RT_NULL); - lwp = (struct rt_lwp *)tid->lwp; + /* copy file name to process name */ + rt_strncpy(lwp->cmd, filename, RT_NAME_MAX); - if (lwp->lwp_type == LWP_TYPE_DYN_ADDR) + if (load_addr != RT_NULL) { - dbg_log(DBG_INFO, "dynamic lwp\n"); - if (lwp->text_entry) - { - dbg_log(DBG_LOG, "lwp text free: %p\n", lwp->text_entry); -#ifdef RT_USING_CACHE - rt_free_align(lwp->text_entry); -#else - rt_free(lwp->text_entry); -#endif - } - if (lwp->data) - { - dbg_log(DBG_LOG, "lwp data free: %p\n", lwp->data); - rt_free(lwp->data); - } + lwp->lwp_type = LWP_TYPE_FIX_ADDR; + ptr = load_addr; + } + else + { + lwp->lwp_type = LWP_TYPE_DYN_ADDR; + ptr = RT_NULL; } - dbg_log(DBG_LOG, "lwp free memory pages\n"); - rt_lwp_mem_deinit(lwp); + fd = open(filename, O_BINARY | O_RDONLY, 0); + if (fd < 0) + { + LOG_E("ERROR: Can't open elf file %s!", filename); + goto out; + } + len = lseek(fd, 0, SEEK_END); + if (len < 0) + { + LOG_E("ERROR: File %s size error!", filename); + goto out; + } - /* cleanup fd table */ - rt_free(lwp->fdt.fds); - rt_free(lwp->args); + lseek(fd, 0, SEEK_SET); - dbg_log(DBG_LOG, "lwp free: %p\n", lwp); - rt_free(lwp); + ret = load_elf(fd, len, lwp, ptr, aux); + if ((ret != RT_EOK) && (ret != 1)) + { + LOG_E("lwp load ret = %d", ret); + } - /* TODO: cleanup fd table */ +out: + if (fd > 0) + { + close(fd); + } + return ret; } -static void lwp_thread(void *parameter) +void lwp_cleanup(struct rt_thread *tid) +{ + rt_base_t level; + struct rt_lwp *lwp; + + if (tid == NULL) + { + return; + } + + LOG_I("cleanup thread: %s, stack_addr: %08X", tid->name, tid->stack_addr); + + level = rt_hw_interrupt_disable(); + lwp = (struct rt_lwp *)tid->lwp; + + lwp_tid_put(tid->tid); + rt_list_remove(&tid->sibling); + lwp_ref_dec(lwp); + rt_hw_interrupt_enable(level); + + return; +} + +static void lwp_copy_stdio_fdt(struct rt_lwp *lwp) +{ + struct dfs_fd *d; + struct dfs_fdtable *lwp_fdt; + + lwp_fdt = &lwp->fdt; + /* init 4 fds */ + lwp_fdt->fds = rt_calloc(4, sizeof(void *)); + if (lwp_fdt->fds) + { + lwp_fdt->maxfd = 4; + d = fd_get(0); + fd_associate(lwp_fdt, 0, d); + d = fd_get(1); + fd_associate(lwp_fdt, 1, d); + d = fd_get(2); + fd_associate(lwp_fdt, 2, d); + } + + return; +} + +static void lwp_thread_entry(void *parameter) { rt_thread_t tid; struct rt_lwp *lwp; - lwp = (struct rt_lwp *)parameter; - rt_lwp_mem_init(lwp); tid = rt_thread_self(); - tid->lwp = lwp; + lwp = (struct rt_lwp *)tid->lwp; tid->cleanup = lwp_cleanup; + tid->user_stack = RT_NULL; + +#ifdef RT_USING_GDBSERVER + if (lwp->debug) + { + lwp->bak_first_ins = *(uint32_t *)lwp->text_entry; + *(uint32_t *)lwp->text_entry = INS_BREAK_CONNECT; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lwp->text_entry, sizeof(uint32_t)); + icache_invalid_all(); + } +#endif - lwp_user_entry(lwp->args, lwp->text_entry, lwp->data); +#ifdef ARCH_MM_MMU + lwp_user_entry(lwp->args, lwp->text_entry, (void *)USER_STACK_VEND, tid->stack_addr + tid->stack_size); +#else + lwp_user_entry(lwp->args, lwp->text_entry, lwp->data_entry, (void *)((uint32_t)lwp->data_entry + lwp->data_size)); +#endif /* ARCH_MM_MMU */ } -struct rt_lwp *rt_lwp_self(void) +struct rt_lwp *lwp_self(void) { - return (struct rt_lwp *)rt_thread_self()->lwp; + rt_thread_t tid; + + tid = rt_thread_self(); + if (tid) + { + return (struct rt_lwp *)tid->lwp; + } + + return RT_NULL; } -int exec(char *filename, int argc, char **argv) +#ifdef RT_USING_GDBSERVER +pid_t lwp_execve(char *filename, int debug, int argc, char **argv, char **envp) +#else +pid_t lwp_execve(char *filename, int argc, char **argv, char **envp) +#endif { - struct rt_lwp *lwp; int result; + rt_base_t level; + struct rt_lwp *lwp; + char *thread_name; + char *argv_last = argv[argc - 1]; + int bg = 0; + struct process_aux *aux; + int tid = 0; if (filename == RT_NULL) + { return -RT_ERROR; + } + + lwp = lwp_new(); - lwp = (struct rt_lwp *)rt_malloc(sizeof(struct rt_lwp)); if (lwp == RT_NULL) { dbg_log(DBG_ERROR, "lwp struct out of memory!\n"); return -RT_ENOMEM; } - dbg_log(DBG_INFO, "lwp malloc : %p, size: %d!\n", lwp, sizeof(struct rt_lwp)); + LOG_D("lwp malloc : %p, size: %d!", lwp, sizeof(struct rt_lwp)); + + if ((tid = lwp_tid_get()) == 0) + { + lwp_ref_dec(lwp); + return -ENOMEM; + } +#ifdef RT_USING_USERSPACE + if (lwp_user_space_init(lwp) != 0) + { + lwp_tid_put(tid); + lwp_ref_dec(lwp); + return -ENOMEM; + } +#endif - rt_memset(lwp, 0, sizeof(*lwp)); - if (lwp_argscopy(lwp, argc, argv) != 0) + if (argv_last[0] == '&' && argv_last[1] == '\0') { - rt_free(lwp); + argc--; + bg = 1; + } + + if ((aux = lwp_argscopy(lwp, argc, argv, envp)) == RT_NULL) + { + lwp_tid_put(tid); + lwp_ref_dec(lwp); return -ENOMEM; } - result = lwp_load(filename, lwp, RT_NULL, 0); + result = lwp_load(filename, lwp, RT_NULL, 0, aux); +#ifdef ARCH_MM_MMU + if (result == 1) + { + /* dynmaic */ + lwp_unmap_user(lwp, (void *)(USER_VADDR_TOP - ARCH_PAGE_SIZE)); + result = load_ldso(lwp, filename, argv, envp); + } +#endif /* ARCH_MM_MMU */ if (result == RT_EOK) { - rt_thread_t tid; + rt_thread_t thread = RT_NULL; + rt_uint32_t priority = 25, tick = 200; + + lwp_copy_stdio_fdt(lwp); - tid = rt_thread_create("user", lwp_thread, (void *)lwp, - 1024 * 4, 2, 200); - if (tid != RT_NULL) + /* obtain the base name */ + thread_name = strrchr(filename, '/'); + thread_name = thread_name ? thread_name + 1 : filename; +#ifndef ARCH_MM_MMU + struct lwp_app_head *app_head = lwp->text_entry; + if (app_head->priority) { - dbg_log(DBG_LOG, "lwp kernel => (0x%08x, 0x%08x)\n", (rt_uint32_t)tid->stack_addr, (rt_uint32_t)tid->stack_addr + tid->stack_size); - rt_thread_startup(tid); - return RT_EOK; + priority = app_head->priority; } - else + if (app_head->tick) { -#ifdef RT_USING_CACHE - rt_free_align(lwp->text_entry); -#else - rt_free(lwp->text_entry); + tick = app_head->tick; + } +#endif /* not defined ARCH_MM_MMU */ + thread = rt_thread_create(thread_name, lwp_thread_entry, RT_NULL, + LWP_TASK_STACK_SIZE, priority, tick); + if (thread != RT_NULL) + { + struct rt_lwp *self_lwp; + + thread->tid = tid; + lwp_tid_set_thread(tid, thread); + LOG_D("lwp kernel => (0x%08x, 0x%08x)\n", (rt_uint32_t)thread->stack_addr, + (rt_uint32_t)thread->stack_addr + thread->stack_size); + level = rt_hw_interrupt_disable(); + self_lwp = lwp_self(); + if (self_lwp) + { + //lwp->tgroup_leader = &thread; //add thread group leader for lwp + lwp->__pgrp = tid; + lwp->session = self_lwp->session; + /* lwp add to children link */ + lwp->sibling = self_lwp->first_child; + self_lwp->first_child = lwp; + lwp->parent = self_lwp; + } + else + { + //lwp->tgroup_leader = &thread; //add thread group leader for lwp + lwp->__pgrp = tid; + } + if (!bg) + { + if (lwp->session == -1) + { + struct tty_struct *tty = RT_NULL; + tty = (struct tty_struct *)console_tty_get(); + lwp->tty = tty; + lwp->tty->pgrp = lwp->__pgrp; + lwp->tty->session = lwp->session; + lwp->tty->foreground = lwp; + tcgetattr(1, &stdin_termios); + old_stdin_termios = stdin_termios; + stdin_termios.c_lflag |= ICANON | ECHO | ECHOCTL; + tcsetattr(1, 0, &stdin_termios); + } + else + { + if (self_lwp != RT_NULL) + { + lwp->tty = self_lwp->tty; + lwp->tty->pgrp = lwp->__pgrp; + lwp->tty->session = lwp->session; + lwp->tty->foreground = lwp; + } + else + { + lwp->tty = RT_NULL; + } + + } + } + thread->lwp = lwp; +#ifndef ARCH_MM_MMU + struct lwp_app_head *app_head = (struct lwp_app_head*)lwp->text_entry; + thread->user_stack = app_head->stack_offset ? + (void *)(app_head->stack_offset - + app_head->data_offset + + (uint32_t)lwp->data_entry) : RT_NULL; + thread->user_stack_size = app_head->stack_size; + /* init data area */ + rt_memset(lwp->data_entry, 0, lwp->data_size); + /* init user stack */ + rt_memset(thread->user_stack, '#', thread->user_stack_size); +#endif /* not defined ARCH_MM_MMU */ + rt_list_insert_after(&lwp->t_grp, &thread->sibling); + +#ifdef RT_USING_GDBSERVER + if (debug) + { + lwp->debug = debug; + } #endif - rt_free(lwp->data); + rt_hw_interrupt_enable(level); + + rt_thread_startup(thread); + return lwp_to_pid(lwp); } } - rt_free(lwp->args); - rt_free(lwp); + lwp_tid_put(tid); + lwp_ref_dec(lwp); return -RT_ERROR; } + +extern char **__environ; + +#ifdef RT_USING_GDBSERVER +pid_t exec(char *filename, int debug, int argc, char **argv) +{ + return lwp_execve(filename, debug, argc, argv, __environ); +} +#else +pid_t exec(char *filename, int argc, char **argv) +{ + return lwp_execve(filename, argc, argv, __environ); +} +#endif + +#ifdef ARCH_MM_MMU +void lwp_user_setting_save(rt_thread_t thread) +{ + if (thread) + { + thread->thread_idr = rt_cpu_get_thread_idr(); + } +} + +void lwp_user_setting_restore(rt_thread_t thread) +{ + if (!thread) + { + return; + } + rt_cpu_set_thread_idr(thread->thread_idr); + +#ifdef RT_USING_GDBSERVER + { + struct rt_lwp *l = (struct rt_lwp *)thread->lwp; + + if (l != 0) + { + set_process_id((size_t)l->pid); + } + else + { + set_process_id(0); + } + if (l && l->debug) + { + uint32_t step_type = 0; + + step_type = gdb_get_step_type(); + + if ((step_type == 2) || (thread->step_exec && (step_type == 1))) + { + arch_activate_step(); + } + else + { + arch_deactivate_step(); + } + } + } +#endif +} +#endif /* ARCH_MM_MMU */ diff --git a/components/lwp/lwp.h b/components/lwp/lwp.h index f013f36768ad1f9eacab27358ec0d8731a5f2dab..99db3f0363a1da6321a10f278d591ae2bbd6a928 100644 --- a/components/lwp/lwp.h +++ b/components/lwp/lwp.h @@ -1,16 +1,55 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-06-29 heyuanjie first version + * 2019-10-12 Jesven Add MMU and userspace support + * 2020-10-08 Bernard Architecture and code cleanup + * 2021-08-26 linzhenxing add lwp_setcwd\lwp_getcwd */ +/* + * RT-Thread light-weight process + */ #ifndef __LWP_H__ #define __LWP_H__ +#include + +#include +#include +#include + +#include "lwp_pid.h" +#include "lwp_ipc.h" +#include "lwp_signal.h" +#include "lwp_syscall.h" +#include "lwp_avl.h" + +#ifdef RT_USING_USERSPACE +#include "lwp_shm.h" + +#include "mmu.h" +#include "page.h" +#else +#include "lwp_mpu.h" +#endif +#include "lwp_arch.h" + +#ifdef RT_USING_MUSL +#include +#endif +#ifdef RT_USING_TTY +struct tty_struct; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + #define LWP_MAGIC 0x5A #define LWP_TYPE_FIX_ADDR 0x01 @@ -18,54 +57,210 @@ #define LWP_ARG_MAX 8 -#include -#include -#include -#include - struct rt_lwp { +#ifdef RT_USING_USERSPACE + rt_mmu_info mmu_info; + struct lwp_avl_struct *map_area; + size_t end_heap; +#else +#ifdef ARCH_MM_MPU + struct rt_mpu_info mpu_info; +#endif /* ARCH_MM_MPU */ +#endif uint8_t lwp_type; - uint8_t heap_cnt; - uint8_t reserv[2]; + uint8_t reserv[3]; - rt_list_t hlist; /**< headp list */ + struct rt_lwp *parent; + struct rt_lwp *first_child; + struct rt_lwp *sibling; - uint8_t *text_entry; - uint32_t text_size; + rt_list_t wait_list; + int32_t finish; + int lwp_ret; - uint8_t *data; + void *text_entry; + uint32_t text_size; + void *data_entry; uint32_t data_size; - uint32_t *kernel_sp; /**< kernel stack point */ - struct dfs_fdtable fdt; + int ref; void *args; + uint32_t args_length; + pid_t pid; + pid_t __pgrp; /*Accessed via process_group()*/ + pid_t tty_old_pgrp; + pid_t session; + rt_list_t t_grp; + + int leader; /*boolean value for session group_leader*/ + struct dfs_fdtable fdt; + char cmd[RT_NAME_MAX]; + + int sa_flags; + lwp_sigset_t signal; + lwp_sigset_t signal_mask; + int signal_mask_bak; + rt_uint32_t signal_in_process; + lwp_sighandler_t signal_handler[_LWP_NSIG]; + + struct lwp_avl_struct *object_root; + struct rt_mutex object_mutex; + struct rt_user_context user_ctx; + + struct rt_wqueue wait_queue; /*for console */ + struct tty_struct *tty; /* NULL if no tty */ + + struct lwp_avl_struct *address_search_head; /* for addressed object fast rearch */ + char working_directory[DFS_PATH_MAX]; +#ifdef RT_USING_GDBSERVER + int debug; + uint32_t bak_first_ins; +#endif }; -struct lwp_header +struct rt_lwp *lwp_self(void); + +enum lwp_exit_request_type { - uint8_t magic; - uint8_t compress_encrypt_algo; - uint16_t reserved; + LWP_EXIT_REQUEST_NONE = 0, + LWP_EXIT_REQUEST_TRIGGERED, + LWP_EXIT_REQUEST_IN_PROCESS, +}; +void lwp_setcwd(char *buf); +char *lwp_getcwd(void); +void lwp_request_thread_exit(rt_thread_t thread_to_exit); +int lwp_check_exit_request(void); +void lwp_terminate(struct rt_lwp *lwp); +void lwp_wait_subthread_exit(void); + +void lwp_set_thread_area(void *p); +void* rt_cpu_get_thread_idr(void); +void rt_cpu_set_thread_idr(void *p); + +int lwp_tid_get(void); +void lwp_tid_put(int tid); +rt_thread_t lwp_tid_get_thread(int tid); +void lwp_tid_set_thread(int tid, rt_thread_t thread); + +size_t lwp_user_strlen(const char *s, int *err); + +/*create by lwp_setsid.c*/ +int setsid(void); +#ifdef RT_USING_USERSPACE +void lwp_mmu_switch(struct rt_thread *thread); +#endif +void lwp_user_setting_save(rt_thread_t thread); +void lwp_user_setting_restore(rt_thread_t thread); + +#ifdef RT_USING_USERSPACE +struct __pthread { + /* Part 1 -- these fields may be external or + * * internal (accessed via asm) ABI. Do not change. */ + struct pthread *self; + uintptr_t *dtv; + struct pthread *prev, *next; /* non-ABI */ + uintptr_t sysinfo; + uintptr_t canary, canary2; - uint32_t crc32; + /* Part 2 -- implementation details, non-ABI. */ + int tid; + int errno_val; + volatile int detach_state; + volatile int cancel; + volatile unsigned char canceldisable, cancelasync; + unsigned char tsd_used:1; + unsigned char dlerror_flag:1; + unsigned char *map_base; + size_t map_size; + void *stack; + size_t stack_size; + size_t guard_size; + void *result; + struct __ptcb *cancelbuf; + void **tsd; + struct { + volatile void *volatile head; + long off; + volatile void *volatile pending; + } robust_list; + volatile int timer_id; + locale_t locale; + volatile int killlock[1]; + char *dlerror_buf; + void *stdio_locks; + + /* Part 3 -- the positions of these fields relative to + * * the end of the structure is external and internal ABI. */ + uintptr_t canary_at_end; + uintptr_t *dtv_copy; }; +#endif -struct lwp_chunk -{ - uint32_t total_len; +/* for futex op */ +#define FUTEX_WAIT 0 +#define FUTEX_WAKE 1 + +/* for pmutex op */ +#define PMUTEX_INIT 0 +#define PMUTEX_LOCK 1 +#define PMUTEX_UNLOCK 2 +#define PMUTEX_DESTROY 3 + +#ifdef __cplusplus +} +#endif + +#define AUX_ARRAY_ITEMS_NR 6 - char name[4]; - uint32_t data_len; - uint32_t data_len_space; +/* aux key */ +#define AT_NULL 0 +#define AT_IGNORE 1 +#define AT_EXECFD 2 +#define AT_PHDR 3 +#define AT_PHENT 4 +#define AT_PHNUM 5 +#define AT_PAGESZ 6 +#define AT_BASE 7 +#define AT_FLAGS 8 +#define AT_ENTRY 9 +#define AT_NOTELF 10 +#define AT_UID 11 +#define AT_EUID 12 +#define AT_GID 13 +#define AT_EGID 14 +#define AT_CLKTCK 17 +#define AT_PLATFORM 15 +#define AT_HWCAP 16 +#define AT_FPUCW 18 +#define AT_DCACHEBSIZE 19 +#define AT_ICACHEBSIZE 20 +#define AT_UCACHEBSIZE 21 +#define AT_IGNOREPPC 22 +#define AT_SECURE 23 +#define AT_BASE_PLATFORM 24 +#define AT_RANDOM 25 +#define AT_HWCAP2 26 +#define AT_EXECFN 31 + +struct process_aux_item +{ + size_t key; + size_t value; }; -extern struct rt_lwp *rt_lwp_self(void); +struct process_aux +{ + struct process_aux_item item[AUX_ARRAY_ITEMS_NR]; +}; -extern void rt_lwp_mem_init(struct rt_lwp *lwp); -extern void rt_lwp_mem_deinit(struct rt_lwp *lwp); -extern void *rt_lwp_mem_malloc(rt_uint32_t size); -extern void rt_lwp_mem_free(void *addr); -extern void *rt_lwp_mem_realloc(void *rmem, rt_size_t newsize); +struct lwp_args_info +{ + char **argv; + char **envp; + int argc; + int envc; + int size; +}; #endif diff --git a/components/lwp/lwp_avl.c b/components/lwp/lwp_avl.c new file mode 100644 index 0000000000000000000000000000000000000000..71eb0892644bef8cdd90e2719ef4720ff29a092a --- /dev/null +++ b/components/lwp/lwp_avl.c @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-12 Jesven first version + */ +#include +#include + +static void lwp_avl_rebalance(struct lwp_avl_struct ***nodeplaces_ptr, int count) +{ + for (; count > 0; count--) + { + struct lwp_avl_struct **nodeplace = *--nodeplaces_ptr; + struct lwp_avl_struct *node = *nodeplace; + struct lwp_avl_struct *nodeleft = node->avl_left; + struct lwp_avl_struct *noderight = node->avl_right; + int heightleft = heightof(nodeleft); + int heightright = heightof(noderight); + if (heightright + 1 < heightleft) + { + struct lwp_avl_struct *nodeleftleft = nodeleft->avl_left; + struct lwp_avl_struct *nodeleftright = nodeleft->avl_right; + int heightleftright = heightof(nodeleftright); + if (heightof(nodeleftleft) >= heightleftright) + { + node->avl_left = nodeleftright; + nodeleft->avl_right = node; + nodeleft->avl_height = 1 + (node->avl_height = 1 + heightleftright); + *nodeplace = nodeleft; + } + else + { + nodeleft->avl_right = nodeleftright->avl_left; + node->avl_left = nodeleftright->avl_right; + nodeleftright->avl_left = nodeleft; + nodeleftright->avl_right = node; + nodeleft->avl_height = node->avl_height = heightleftright; + nodeleftright->avl_height = heightleft; + *nodeplace = nodeleftright; + } + } + else if (heightleft + 1 < heightright) + { + struct lwp_avl_struct *noderightright = noderight->avl_right; + struct lwp_avl_struct *noderightleft = noderight->avl_left; + int heightrightleft = heightof(noderightleft); + if (heightof(noderightright) >= heightrightleft) + { + node->avl_right = noderightleft; + noderight->avl_left = node; + noderight->avl_height = 1 + (node->avl_height = 1 + heightrightleft); + *nodeplace = noderight; + } + else + { + noderight->avl_left = noderightleft->avl_right; + node->avl_right = noderightleft->avl_left; + noderightleft->avl_right = noderight; + noderightleft->avl_left = node; + noderight->avl_height = node->avl_height = heightrightleft; + noderightleft->avl_height = heightright; + *nodeplace = noderightleft; + } + } + else + { + int height = (heightleft < heightright ? heightright : heightleft) + 1; + if (height == node->avl_height) + break; + node->avl_height = height; + } + } +} + +void lwp_avl_remove(struct lwp_avl_struct *node_to_delete, struct lwp_avl_struct **ptree) +{ + avl_key_t key = node_to_delete->avl_key; + struct lwp_avl_struct **nodeplace = ptree; + struct lwp_avl_struct **stack[avl_maxheight]; + uint32_t stack_count = 0; + struct lwp_avl_struct ***stack_ptr = &stack[0]; /* = &stack[stackcount] */ + struct lwp_avl_struct **nodeplace_to_delete; + for (;;) + { + struct lwp_avl_struct *node = *nodeplace; + if (node == AVL_EMPTY) + { + return; + } + + *stack_ptr++ = nodeplace; + stack_count++; + if (key == node->avl_key) + break; + if (key < node->avl_key) + nodeplace = &node->avl_left; + else + nodeplace = &node->avl_right; + } + nodeplace_to_delete = nodeplace; + if (node_to_delete->avl_left == AVL_EMPTY) + { + *nodeplace_to_delete = node_to_delete->avl_right; + stack_ptr--; + stack_count--; + } + else + { + struct lwp_avl_struct ***stack_ptr_to_delete = stack_ptr; + struct lwp_avl_struct **nodeplace = &node_to_delete->avl_left; + struct lwp_avl_struct *node; + for (;;) + { + node = *nodeplace; + if (node->avl_right == AVL_EMPTY) + break; + *stack_ptr++ = nodeplace; + stack_count++; + nodeplace = &node->avl_right; + } + *nodeplace = node->avl_left; + node->avl_left = node_to_delete->avl_left; + node->avl_right = node_to_delete->avl_right; + node->avl_height = node_to_delete->avl_height; + *nodeplace_to_delete = node; + *stack_ptr_to_delete = &node->avl_left; + } + lwp_avl_rebalance(stack_ptr, stack_count); +} + +void lwp_avl_insert(struct lwp_avl_struct *new_node, struct lwp_avl_struct **ptree) +{ + avl_key_t key = new_node->avl_key; + struct lwp_avl_struct **nodeplace = ptree; + struct lwp_avl_struct **stack[avl_maxheight]; + int stack_count = 0; + struct lwp_avl_struct ***stack_ptr = &stack[0]; /* = &stack[stackcount] */ + for (;;) + { + struct lwp_avl_struct *node = *nodeplace; + if (node == AVL_EMPTY) + break; + *stack_ptr++ = nodeplace; + stack_count++; + if (key < node->avl_key) + nodeplace = &node->avl_left; + else + nodeplace = &node->avl_right; + } + new_node->avl_left = AVL_EMPTY; + new_node->avl_right = AVL_EMPTY; + new_node->avl_height = 1; + *nodeplace = new_node; + lwp_avl_rebalance(stack_ptr, stack_count); +} + +struct lwp_avl_struct *lwp_avl_find(avl_key_t key, struct lwp_avl_struct *ptree) +{ + for (;;) + { + if (ptree == AVL_EMPTY) + { + return (struct lwp_avl_struct *)0; + } + if (key == ptree->avl_key) + break; + if (key < ptree->avl_key) + ptree = ptree->avl_left; + else + ptree = ptree->avl_right; + } + return ptree; +} + +int lwp_avl_traversal(struct lwp_avl_struct *ptree, int (*fun)(struct lwp_avl_struct *, void *), void *arg) +{ + int ret; + + if (!ptree) + { + return 0; + } + if (ptree->avl_left) + { + ret = lwp_avl_traversal(ptree->avl_left, fun, arg); + if (ret != 0) + { + return ret; + } + } + ret = (*fun)(ptree, arg); + if (ret != 0) + { + return ret; + } + if (ptree->avl_right) + { + ret = lwp_avl_traversal(ptree->avl_right, fun, arg); + if (ret != 0) + { + return ret; + } + } + return ret; +} + +RT_WEAK struct lwp_avl_struct* lwp_map_find_first(struct lwp_avl_struct* ptree) +{ + if (ptree == AVL_EMPTY) + { + return (struct lwp_avl_struct *)0; + } + while (1) + { + if (!ptree->avl_left) + { + break; + } + ptree = ptree->avl_left; + } + return ptree; +} + diff --git a/components/lwp/lwp_avl.h b/components/lwp/lwp_avl.h new file mode 100644 index 0000000000000000000000000000000000000000..2d555794d664e9c49b2f011e4fb45ef50fc0589a --- /dev/null +++ b/components/lwp/lwp_avl.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-12 Jesven first version + */ +#ifndef LWP_AVL_H__ +#define LWP_AVL_H__ + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define avl_key_t size_t +#define AVL_EMPTY (struct lwp_avl_struct *)0 +#define avl_maxheight 32 +#define heightof(tree) ((tree) == AVL_EMPTY ? 0 : (tree)->avl_height) + +struct lwp_avl_struct +{ + struct lwp_avl_struct *avl_left; + struct lwp_avl_struct *avl_right; + int avl_height; + avl_key_t avl_key; + void *data; +}; + +void lwp_avl_remove(struct lwp_avl_struct * node_to_delete, struct lwp_avl_struct ** ptree); +void lwp_avl_insert (struct lwp_avl_struct * new_node, struct lwp_avl_struct ** ptree); +struct lwp_avl_struct* lwp_avl_find(avl_key_t key, struct lwp_avl_struct* ptree); +int lwp_avl_traversal(struct lwp_avl_struct* ptree, int (*fun)(struct lwp_avl_struct*, void *), void *arg); +struct lwp_avl_struct* lwp_map_find_first(struct lwp_avl_struct* ptree); + +#ifdef __cplusplus +} +#endif + +#endif /* LWP_AVL_H__ */ diff --git a/components/lwp/lwp_elf.h b/components/lwp/lwp_elf.h new file mode 100644 index 0000000000000000000000000000000000000000..e4817fe6f908ea358144ab0b2b097cb0986ccacd --- /dev/null +++ b/components/lwp/lwp_elf.h @@ -0,0 +1,3520 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-28 Jesven first version + */ +#ifndef LWP_ELF_H__ +#define LWP_ELF_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef ARCH_CPU_64BIT +#define elfhdr elf64_hdr +#define elf_phdr elf64_phdr +#define elf_shdr elf64_shdr +#define elf_note elf64_note +#define elf_addr_t Elf64_Off +#define Elf_Word Elf64_Word +#define Elf_Addr Elf64_Addr +#define Elf_Half Elf64_Half +#define Elf_Ehdr Elf64_Ehdr +#define Elf_Phdr Elf64_Phdr +#define Elf_Shdr Elf64_Shdr +#else +#define elfhdr elf32_hdr +#define elf_phdr elf32_phdr +#define elf_shdr elf32_shdr +#define elf_note elf32_note +#define elf_addr_t Elf32_Off +#define Elf_Word Elf32_Word +#define Elf_Addr Elf32_Addr +#define Elf_Half Elf32_Half +#define Elf_Ehdr Elf32_Ehdr +#define Elf_Phdr Elf32_Phdr +#define Elf_Shdr Elf32_Shdr +#endif + +/* Type for a 16-bit quantity. */ +typedef uint16_t Elf32_Half; +typedef uint16_t Elf64_Half; + +/* Types for signed and unsigned 32-bit quantities. */ +typedef uint32_t Elf32_Word; +typedef int32_t Elf32_Sword; +typedef uint32_t Elf64_Word; +typedef int32_t Elf64_Sword; + +/* Types for signed and unsigned 64-bit quantities. */ +typedef uint64_t Elf32_Xword; +typedef int64_t Elf32_Sxword; +typedef uint64_t Elf64_Xword; +typedef int64_t Elf64_Sxword; + +/* Type of addresses. */ +typedef uint32_t Elf32_Addr; +typedef uint64_t Elf64_Addr; + +/* Type of file offsets. */ +typedef uint32_t Elf32_Off; +typedef uint64_t Elf64_Off; + +/* Type for section indices, which are 16-bit quantities. */ +typedef uint16_t Elf32_Section; +typedef uint16_t Elf64_Section; + +/* Type for version symbol information. */ +typedef Elf32_Half Elf32_Versym; +typedef Elf64_Half Elf64_Versym; + + +/* The ELF file header. This appears at the start of every ELF file. */ + +#define EI_NIDENT (16) + +typedef struct elfhdr +{ + unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ + Elf32_Half e_type; /* Object file type */ + Elf32_Half e_machine; /* Architecture */ + Elf32_Word e_version; /* Object file version */ + Elf32_Addr e_entry; /* Entry point virtual address */ + Elf32_Off e_phoff; /* Program header table file offset */ + Elf32_Off e_shoff; /* Section header table file offset */ + Elf32_Word e_flags; /* Processor-specific flags */ + Elf32_Half e_ehsize; /* ELF header size in bytes */ + Elf32_Half e_phentsize; /* Program header table entry size */ + Elf32_Half e_phnum; /* Program header table entry count */ + Elf32_Half e_shentsize; /* Section header table entry size */ + Elf32_Half e_shnum; /* Section header table entry count */ + Elf32_Half e_shstrndx; /* Section header string table index */ +} Elf32_Ehdr; + +typedef struct +{ + unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ + Elf64_Half e_type; /* Object file type */ + Elf64_Half e_machine; /* Architecture */ + Elf64_Word e_version; /* Object file version */ + Elf64_Addr e_entry; /* Entry point virtual address */ + Elf64_Off e_phoff; /* Program header table file offset */ + Elf64_Off e_shoff; /* Section header table file offset */ + Elf64_Word e_flags; /* Processor-specific flags */ + Elf64_Half e_ehsize; /* ELF header size in bytes */ + Elf64_Half e_phentsize; /* Program header table entry size */ + Elf64_Half e_phnum; /* Program header table entry count */ + Elf64_Half e_shentsize; /* Section header table entry size */ + Elf64_Half e_shnum; /* Section header table entry count */ + Elf64_Half e_shstrndx; /* Section header string table index */ +} Elf64_Ehdr; + +/* Fields in the e_ident array. The EI_* macros are indices into the + array. The macros under each EI_* macro are the values the byte + may have. */ + +#define EI_MAG0 0 /* File identification byte 0 index */ +#define ELFMAG0 0x7f /* Magic number byte 0 */ + +#define EI_MAG1 1 /* File identification byte 1 index */ +#define ELFMAG1 'E' /* Magic number byte 1 */ + +#define EI_MAG2 2 /* File identification byte 2 index */ +#define ELFMAG2 'L' /* Magic number byte 2 */ + +#define EI_MAG3 3 /* File identification byte 3 index */ +#define ELFMAG3 'F' /* Magic number byte 3 */ + +/* Conglomeration of the identification bytes, for easy testing as a word. */ +#define ELFMAG "\177ELF" +#define SELFMAG 4 + +#define EI_CLASS 4 /* File class byte index */ +#define ELFCLASSNONE 0 /* Invalid class */ +#define ELFCLASS32 1 /* 32-bit objects */ +#define ELFCLASS64 2 /* 64-bit objects */ +#define ELFCLASSNUM 3 + +#define EI_DATA 5 /* Data encoding byte index */ +#define ELFDATANONE 0 /* Invalid data encoding */ +#define ELFDATA2LSB 1 /* 2's complement, little endian */ +#define ELFDATA2MSB 2 /* 2's complement, big endian */ +#define ELFDATANUM 3 + +#define EI_VERSION 6 /* File version byte index */ + /* Value must be EV_CURRENT */ + +#define EI_OSABI 7 /* OS ABI identification */ +#define ELFOSABI_NONE 0 /* UNIX System V ABI */ +#define ELFOSABI_SYSV 0 /* Alias. */ +#define ELFOSABI_HPUX 1 /* HP-UX */ +#define ELFOSABI_NETBSD 2 /* NetBSD. */ +#define ELFOSABI_GNU 3 /* Object uses GNU ELF extensions. */ +#define ELFOSABI_LINUX ELFOSABI_GNU /* Compatibility alias. */ +#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ +#define ELFOSABI_AIX 7 /* IBM AIX. */ +#define ELFOSABI_IRIX 8 /* SGI Irix. */ +#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ +#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ +#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ +#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ +#define ELFOSABI_ARM_AEABI 64 /* ARM EABI */ +#define ELFOSABI_ARM 97 /* ARM */ +#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ + +#define EI_ABIVERSION 8 /* ABI version */ + +#define EI_PAD 9 /* Byte index of padding bytes */ + +/* Legal values for e_type (object file type). */ + +#define ET_NONE 0 /* No file type */ +#define ET_REL 1 /* Relocatable file */ +#define ET_EXEC 2 /* Executable file */ +#define ET_DYN 3 /* Shared object file */ +#define ET_CORE 4 /* Core file */ +#define ET_NUM 5 /* Number of defined types */ +#define ET_LOOS 0xfe00 /* OS-specific range start */ +#define ET_HIOS 0xfeff /* OS-specific range end */ +#define ET_LOPROC 0xff00 /* Processor-specific range start */ +#define ET_HIPROC 0xffff /* Processor-specific range end */ + +/* Legal values for e_machine (architecture). */ + +#define EM_NONE 0 /* No machine */ +#define EM_M32 1 /* AT&T WE 32100 */ +#define EM_SPARC 2 /* SUN SPARC */ +#define EM_386 3 /* Intel 80386 */ +#define EM_68K 4 /* Motorola m68k family */ +#define EM_88K 5 /* Motorola m88k family */ +#define EM_860 7 /* Intel 80860 */ +#define EM_MIPS 8 /* MIPS R3000 big-endian */ +#define EM_S370 9 /* IBM System/370 */ +#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ + +#define EM_PARISC 15 /* HPPA */ +#define EM_VPP500 17 /* Fujitsu VPP500 */ +#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ +#define EM_960 19 /* Intel 80960 */ +#define EM_PPC 20 /* PowerPC */ +#define EM_PPC64 21 /* PowerPC 64-bit */ +#define EM_S390 22 /* IBM S390 */ + +#define EM_V800 36 /* NEC V800 series */ +#define EM_FR20 37 /* Fujitsu FR20 */ +#define EM_RH32 38 /* TRW RH-32 */ +#define EM_RCE 39 /* Motorola RCE */ +#define EM_ARM 40 /* ARM */ +#define EM_FAKE_ALPHA 41 /* Digital Alpha */ +#define EM_SH 42 /* Hitachi SH */ +#define EM_SPARCV9 43 /* SPARC v9 64-bit */ +#define EM_TRICORE 44 /* Siemens Tricore */ +#define EM_ARC 45 /* Argonaut RISC Core */ +#define EM_H8_300 46 /* Hitachi H8/300 */ +#define EM_H8_300H 47 /* Hitachi H8/300H */ +#define EM_H8S 48 /* Hitachi H8S */ +#define EM_H8_500 49 /* Hitachi H8/500 */ +#define EM_IA_64 50 /* Intel Merced */ +#define EM_MIPS_X 51 /* Stanford MIPS-X */ +#define EM_COLDFIRE 52 /* Motorola Coldfire */ +#define EM_68HC12 53 /* Motorola M68HC12 */ +#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ +#define EM_PCP 55 /* Siemens PCP */ +#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ +#define EM_NDR1 57 /* Denso NDR1 microprocessor */ +#define EM_STARCORE 58 /* Motorola Start*Core processor */ +#define EM_ME16 59 /* Toyota ME16 processor */ +#define EM_ST100 60 /* STMicroelectronic ST100 processor */ +#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ +#define EM_X86_64 62 /* AMD x86-64 architecture */ +#define EM_PDSP 63 /* Sony DSP Processor */ + +#define EM_FX66 66 /* Siemens FX66 microcontroller */ +#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ +#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ +#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ +#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ +#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ +#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ +#define EM_SVX 73 /* Silicon Graphics SVx */ +#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ +#define EM_VAX 75 /* Digital VAX */ +#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ +#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ +#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ +#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ +#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ +#define EM_HUANY 81 /* Harvard University machine-independent object files */ +#define EM_PRISM 82 /* SiTera Prism */ +#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ +#define EM_FR30 84 /* Fujitsu FR30 */ +#define EM_D10V 85 /* Mitsubishi D10V */ +#define EM_D30V 86 /* Mitsubishi D30V */ +#define EM_V850 87 /* NEC v850 */ +#define EM_M32R 88 /* Mitsubishi M32R */ +#define EM_MN10300 89 /* Matsushita MN10300 */ +#define EM_MN10200 90 /* Matsushita MN10200 */ +#define EM_PJ 91 /* picoJava */ +#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ +#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ +#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ +#define EM_ALTERA_NIOS2 113 /* Altera Nios II */ +#define EM_AARCH64 183 /* ARM AARCH64 */ +#define EM_TILEPRO 188 /* Tilera TILEPro */ +#define EM_MICROBLAZE 189 /* Xilinx MicroBlaze */ +#define EM_TILEGX 191 /* Tilera TILE-Gx */ +#define EM_NUM 192 + +/* If it is necessary to assign new unofficial EM_* values, please + pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the + chances of collision with official or non-GNU unofficial values. */ + +#define EM_ALPHA 0x9026 + +/* Legal values for e_version (version). */ + +#define EV_NONE 0 /* Invalid ELF version */ +#define EV_CURRENT 1 /* Current version */ +#define EV_NUM 2 + +/* Section header. */ + +typedef struct +{ + Elf32_Word sh_name; /* Section name (string tbl index) */ + Elf32_Word sh_type; /* Section type */ + Elf32_Word sh_flags; /* Section flags */ + Elf32_Addr sh_addr; /* Section virtual addr at execution */ + Elf32_Off sh_offset; /* Section file offset */ + Elf32_Word sh_size; /* Section size in bytes */ + Elf32_Word sh_link; /* Link to another section */ + Elf32_Word sh_info; /* Additional section information */ + Elf32_Word sh_addralign; /* Section alignment */ + Elf32_Word sh_entsize; /* Entry size if section holds table */ +} Elf32_Shdr; + +typedef struct +{ + Elf64_Word sh_name; /* Section name (string tbl index) */ + Elf64_Word sh_type; /* Section type */ + Elf64_Xword sh_flags; /* Section flags */ + Elf64_Addr sh_addr; /* Section virtual addr at execution */ + Elf64_Off sh_offset; /* Section file offset */ + Elf64_Xword sh_size; /* Section size in bytes */ + Elf64_Word sh_link; /* Link to another section */ + Elf64_Word sh_info; /* Additional section information */ + Elf64_Xword sh_addralign; /* Section alignment */ + Elf64_Xword sh_entsize; /* Entry size if section holds table */ +} Elf64_Shdr; + +/* Special section indices. */ + +#define SHN_UNDEF 0 /* Undefined section */ +#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ +#define SHN_LOPROC 0xff00 /* Start of processor-specific */ +#define SHN_BEFORE 0xff00 /* Order section before all others + (Solaris). */ +#define SHN_AFTER 0xff01 /* Order section after all others + (Solaris). */ +#define SHN_HIPROC 0xff1f /* End of processor-specific */ +#define SHN_LOOS 0xff20 /* Start of OS-specific */ +#define SHN_HIOS 0xff3f /* End of OS-specific */ +#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ +#define SHN_COMMON 0xfff2 /* Associated symbol is common */ +#define SHN_XINDEX 0xffff /* Index is in extra table. */ +#define SHN_HIRESERVE 0xffff /* End of reserved indices */ + +/* Legal values for sh_type (section type). */ + +#define SHT_NULL 0 /* Section header table entry unused */ +#define SHT_PROGBITS 1 /* Program data */ +#define SHT_SYMTAB 2 /* Symbol table */ +#define SHT_STRTAB 3 /* String table */ +#define SHT_RELA 4 /* Relocation entries with addends */ +#define SHT_HASH 5 /* Symbol hash table */ +#define SHT_DYNAMIC 6 /* Dynamic linking information */ +#define SHT_NOTE 7 /* Notes */ +#define SHT_NOBITS 8 /* Program space with no data (bss) */ +#define SHT_REL 9 /* Relocation entries, no addends */ +#define SHT_SHLIB 10 /* Reserved */ +#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ +#define SHT_INIT_ARRAY 14 /* Array of constructors */ +#define SHT_FINI_ARRAY 15 /* Array of destructors */ +#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ +#define SHT_GROUP 17 /* Section group */ +#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ +#define SHT_NUM 19 /* Number of defined types. */ +#define SHT_LOOS 0x60000000 /* Start OS-specific. */ +#define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes. */ +#define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ +#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ +#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ +#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ +#define SHT_SUNW_move 0x6ffffffa +#define SHT_SUNW_COMDAT 0x6ffffffb +#define SHT_SUNW_syminfo 0x6ffffffc +#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ +#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ +#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ +#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ +#define SHT_HIOS 0x6fffffff /* End OS-specific type */ +#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ +#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ +#define SHT_LOUSER 0x80000000 /* Start of application-specific */ +#define SHT_HIUSER 0x8fffffff /* End of application-specific */ + +/* Legal values for sh_flags (section flags). */ + +#define SHF_WRITE (1 << 0) /* Writable */ +#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ +#define SHF_EXECINSTR (1 << 2) /* Executable */ +#define SHF_MERGE (1 << 4) /* Might be merged */ +#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ +#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ +#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ +#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling + required */ +#define SHF_GROUP (1 << 9) /* Section is member of a group. */ +#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ +#define SHF_COMPRESSED (1 << 11) /* Section with compressed data. */ +#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ +#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ +#define SHF_ORDERED (1 << 30) /* Special ordering requirement + (Solaris). */ +#define SHF_EXCLUDE (1U << 31) /* Section is excluded unless + referenced or allocated (Solaris).*/ + +/* Section compression header. Used when SHF_COMPRESSED is set. */ + +typedef struct +{ + Elf32_Word ch_type; /* Compression format. */ + Elf32_Word ch_size; /* Uncompressed data size. */ + Elf32_Word ch_addralign; /* Uncompressed data alignment. */ +} Elf32_Chdr; + +typedef struct +{ + Elf64_Word ch_type; /* Compression format. */ + Elf64_Word ch_reserved; + Elf64_Xword ch_size; /* Uncompressed data size. */ + Elf64_Xword ch_addralign; /* Uncompressed data alignment. */ +} Elf64_Chdr; + +/* Legal values for ch_type (compression algorithm). */ +#define ELFCOMPRESS_ZLIB 1 /* ZLIB/DEFLATE algorithm. */ +#define ELFCOMPRESS_LOOS 0x60000000 /* Start of OS-specific. */ +#define ELFCOMPRESS_HIOS 0x6fffffff /* End of OS-specific. */ +#define ELFCOMPRESS_LOPROC 0x70000000 /* Start of processor-specific. */ +#define ELFCOMPRESS_HIPROC 0x7fffffff /* End of processor-specific. */ + +/* Section group handling. */ +#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ + +/* Symbol table entry. */ + +typedef struct +{ + Elf32_Word st_name; /* Symbol name (string tbl index) */ + Elf32_Addr st_value; /* Symbol value */ + Elf32_Word st_size; /* Symbol size */ + unsigned char st_info; /* Symbol type and binding */ + unsigned char st_other; /* Symbol visibility */ + Elf32_Section st_shndx; /* Section index */ +} Elf32_Sym; + +typedef struct +{ + Elf64_Word st_name; /* Symbol name (string tbl index) */ + unsigned char st_info; /* Symbol type and binding */ + unsigned char st_other; /* Symbol visibility */ + Elf64_Section st_shndx; /* Section index */ + Elf64_Addr st_value; /* Symbol value */ + Elf64_Xword st_size; /* Symbol size */ +} Elf64_Sym; + +/* The syminfo section if available contains additional information about + every dynamic symbol. */ + +typedef struct +{ + Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ + Elf32_Half si_flags; /* Per symbol flags */ +} Elf32_Syminfo; + +typedef struct +{ + Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ + Elf64_Half si_flags; /* Per symbol flags */ +} Elf64_Syminfo; + +/* Possible values for si_boundto. */ +#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ +#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ +#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ + +/* Possible bitmasks for si_flags. */ +#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ +#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ +#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ +#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy + loaded */ +/* Syminfo version values. */ +#define SYMINFO_NONE 0 +#define SYMINFO_CURRENT 1 +#define SYMINFO_NUM 2 + + +/* How to extract and insert information held in the st_info field. */ + +#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) +#define ELF32_ST_TYPE(val) ((val) & 0xf) +#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) + +/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ +#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) +#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) +#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) + +/* Legal values for ST_BIND subfield of st_info (symbol binding). */ + +#define STB_LOCAL 0 /* Local symbol */ +#define STB_GLOBAL 1 /* Global symbol */ +#define STB_WEAK 2 /* Weak symbol */ +#define STB_NUM 3 /* Number of defined types. */ +#define STB_LOOS 10 /* Start of OS-specific */ +#define STB_GNU_UNIQUE 10 /* Unique symbol. */ +#define STB_HIOS 12 /* End of OS-specific */ +#define STB_LOPROC 13 /* Start of processor-specific */ +#define STB_HIPROC 15 /* End of processor-specific */ + +/* Legal values for ST_TYPE subfield of st_info (symbol type). */ + +#define STT_NOTYPE 0 /* Symbol type is unspecified */ +#define STT_OBJECT 1 /* Symbol is a data object */ +#define STT_FUNC 2 /* Symbol is a code object */ +#define STT_SECTION 3 /* Symbol associated with a section */ +#define STT_FILE 4 /* Symbol's name is file name */ +#define STT_COMMON 5 /* Symbol is a common data object */ +#define STT_TLS 6 /* Symbol is thread-local data object*/ +#define STT_NUM 7 /* Number of defined types. */ +#define STT_LOOS 10 /* Start of OS-specific */ +#define STT_GNU_IFUNC 10 /* Symbol is indirect code object */ +#define STT_HIOS 12 /* End of OS-specific */ +#define STT_LOPROC 13 /* Start of processor-specific */ +#define STT_HIPROC 15 /* End of processor-specific */ + + +/* Symbol table indices are found in the hash buckets and chain table + of a symbol hash table section. This special index value indicates + the end of a chain, meaning no further symbols are found in that bucket. */ + +#define STN_UNDEF 0 /* End of a chain. */ + + +/* How to extract and insert information held in the st_other field. */ + +#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) + +/* For ELF64 the definitions are the same. */ +#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) + +/* Symbol visibility specification encoded in the st_other field. */ +#define STV_DEFAULT 0 /* Default symbol visibility rules */ +#define STV_INTERNAL 1 /* Processor specific hidden class */ +#define STV_HIDDEN 2 /* Sym unavailable in other modules */ +#define STV_PROTECTED 3 /* Not preemptible, not exported */ + + +/* Relocation table entry without addend (in section of type SHT_REL). */ + +typedef struct +{ + Elf32_Addr r_offset; /* Address */ + Elf32_Word r_info; /* Relocation type and symbol index */ +} Elf32_Rel; + +/* I have seen two different definitions of the Elf64_Rel and + Elf64_Rela structures, so we'll leave them out until Novell (or + whoever) gets their act together. */ +/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ + +typedef struct +{ + Elf64_Addr r_offset; /* Address */ + Elf64_Xword r_info; /* Relocation type and symbol index */ +} Elf64_Rel; + +/* Relocation table entry with addend (in section of type SHT_RELA). */ + +typedef struct +{ + Elf32_Addr r_offset; /* Address */ + Elf32_Word r_info; /* Relocation type and symbol index */ + Elf32_Sword r_addend; /* Addend */ +} Elf32_Rela; + +typedef struct +{ + Elf64_Addr r_offset; /* Address */ + Elf64_Xword r_info; /* Relocation type and symbol index */ + Elf64_Sxword r_addend; /* Addend */ +} Elf64_Rela; + +/* How to extract and insert information held in the r_info field. */ + +#define ELF32_R_SYM(val) ((val) >> 8) +#define ELF32_R_TYPE(val) ((val) & 0xff) +#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) + +#define ELF64_R_SYM(i) ((i) >> 32) +#define ELF64_R_TYPE(i) ((i) & 0xffffffff) +#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) + +/* Program segment header. */ + +typedef struct elf_phdr +{ + Elf32_Word p_type; /* Segment type */ + Elf32_Off p_offset; /* Segment file offset */ + Elf32_Addr p_vaddr; /* Segment virtual address */ + Elf32_Addr p_paddr; /* Segment physical address */ + Elf32_Word p_filesz; /* Segment size in file */ + Elf32_Word p_memsz; /* Segment size in memory */ + Elf32_Word p_flags; /* Segment flags */ + Elf32_Word p_align; /* Segment alignment */ +} Elf32_Phdr; + +typedef struct +{ + Elf64_Word p_type; /* Segment type */ + Elf64_Word p_flags; /* Segment flags */ + Elf64_Off p_offset; /* Segment file offset */ + Elf64_Addr p_vaddr; /* Segment virtual address */ + Elf64_Addr p_paddr; /* Segment physical address */ + Elf64_Xword p_filesz; /* Segment size in file */ + Elf64_Xword p_memsz; /* Segment size in memory */ + Elf64_Xword p_align; /* Segment alignment */ +} Elf64_Phdr; + +/* Special value for e_phnum. This indicates that the real number of + program headers is too large to fit into e_phnum. Instead the real + value is in the field sh_info of section 0. */ + +#define PN_XNUM 0xffff + +/* Legal values for p_type (segment type). */ + +#define PT_NULL 0 /* Program header table entry unused */ +#define PT_LOAD 1 /* Loadable program segment */ +#define PT_DYNAMIC 2 /* Dynamic linking information */ +#define PT_INTERP 3 /* Program interpreter */ +#define PT_NOTE 4 /* Auxiliary information */ +#define PT_SHLIB 5 /* Reserved */ +#define PT_PHDR 6 /* Entry for header table itself */ +#define PT_TLS 7 /* Thread-local storage segment */ +#define PT_NUM 8 /* Number of defined types */ +#define PT_LOOS 0x60000000 /* Start of OS-specific */ +#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ +#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ +#define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ +#define PT_LOSUNW 0x6ffffffa +#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ +#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ +#define PT_HISUNW 0x6fffffff +#define PT_HIOS 0x6fffffff /* End of OS-specific */ +#define PT_LOPROC 0x70000000 /* Start of processor-specific */ +#define PT_HIPROC 0x7fffffff /* End of processor-specific */ + +/* Legal values for p_flags (segment flags). */ + +#define PF_X (1 << 0) /* Segment is executable */ +#define PF_W (1 << 1) /* Segment is writable */ +#define PF_R (1 << 2) /* Segment is readable */ +#define PF_MASKOS 0x0ff00000 /* OS-specific */ +#define PF_MASKPROC 0xf0000000 /* Processor-specific */ + +/* Legal values for note segment descriptor types for core files. */ + +#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ +#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ +#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ +#define NT_PRXREG 4 /* Contains copy of prxregset struct */ +#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ +#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ +#define NT_AUXV 6 /* Contains copy of auxv array */ +#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ +#define NT_ASRS 8 /* Contains copy of asrset struct */ +#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ +#define NT_PSINFO 13 /* Contains copy of psinfo struct */ +#define NT_PRCRED 14 /* Contains copy of prcred struct */ +#define NT_UTSNAME 15 /* Contains copy of utsname struct */ +#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ +#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ +#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */ +#define NT_SIGINFO 0x53494749 /* Contains copy of siginfo_t, + size might increase */ +#define NT_FILE 0x46494c45 /* Contains information about mapped + files */ +#define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */ +#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ +#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ +#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ +#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ +#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ +#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ +#define NT_S390_HIGH_GPRS 0x300 /* s390 upper register halves */ +#define NT_S390_TIMER 0x301 /* s390 timer register */ +#define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */ +#define NT_S390_TODPREG 0x303 /* s390 TOD programmable register */ +#define NT_S390_CTRS 0x304 /* s390 control registers */ +#define NT_S390_PREFIX 0x305 /* s390 prefix register */ +#define NT_S390_LAST_BREAK 0x306 /* s390 breaking event address */ +#define NT_S390_SYSTEM_CALL 0x307 /* s390 system call restart data */ +#define NT_S390_TDB 0x308 /* s390 transaction diagnostic block */ +#define NT_ARM_VFP 0x400 /* ARM VFP/NEON registers */ +#define NT_ARM_TLS 0x401 /* ARM TLS register */ +#define NT_ARM_HW_BREAK 0x402 /* ARM hardware breakpoint registers */ +#define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */ + +/* Legal values for the note segment descriptor types for object files. */ + +#define NT_VERSION 1 /* Contains a version string. */ + + +/* Dynamic section entry. */ + +typedef struct +{ + Elf32_Sword d_tag; /* Dynamic entry type */ + union + { + Elf32_Word d_val; /* Integer value */ + Elf32_Addr d_ptr; /* Address value */ + } d_un; +} Elf32_Dyn; + +typedef struct +{ + Elf64_Sxword d_tag; /* Dynamic entry type */ + union + { + Elf64_Xword d_val; /* Integer value */ + Elf64_Addr d_ptr; /* Address value */ + } d_un; +} Elf64_Dyn; + +/* Legal values for d_tag (dynamic entry type). */ + +#define DT_NULL 0 /* Marks end of dynamic section */ +#define DT_NEEDED 1 /* Name of needed library */ +#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ +#define DT_PLTGOT 3 /* Processor defined value */ +#define DT_HASH 4 /* Address of symbol hash table */ +#define DT_STRTAB 5 /* Address of string table */ +#define DT_SYMTAB 6 /* Address of symbol table */ +#define DT_RELA 7 /* Address of Rela relocs */ +#define DT_RELASZ 8 /* Total size of Rela relocs */ +#define DT_RELAENT 9 /* Size of one Rela reloc */ +#define DT_STRSZ 10 /* Size of string table */ +#define DT_SYMENT 11 /* Size of one symbol table entry */ +#define DT_INIT 12 /* Address of init function */ +#define DT_FINI 13 /* Address of termination function */ +#define DT_SONAME 14 /* Name of shared object */ +#define DT_RPATH 15 /* Library search path (deprecated) */ +#define DT_SYMBOLIC 16 /* Start symbol search here */ +#define DT_REL 17 /* Address of Rel relocs */ +#define DT_RELSZ 18 /* Total size of Rel relocs */ +#define DT_RELENT 19 /* Size of one Rel reloc */ +#define DT_PLTREL 20 /* Type of reloc in PLT */ +#define DT_DEBUG 21 /* For debugging; unspecified */ +#define DT_TEXTREL 22 /* Reloc might modify .text */ +#define DT_JMPREL 23 /* Address of PLT relocs */ +#define DT_BIND_NOW 24 /* Process relocations of object */ +#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ +#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ +#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ +#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ +#define DT_RUNPATH 29 /* Library search path */ +#define DT_FLAGS 30 /* Flags for the object being loaded */ +#define DT_ENCODING 32 /* Start of encoded range */ +#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ +#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ +#define DT_NUM 34 /* Number used */ +#define DT_LOOS 0x6000000d /* Start of OS-specific */ +#define DT_HIOS 0x6ffff000 /* End of OS-specific */ +#define DT_LOPROC 0x70000000 /* Start of processor-specific */ +#define DT_HIPROC 0x7fffffff /* End of processor-specific */ +#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ + +/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the + Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's + approach. */ +#define DT_VALRNGLO 0x6ffffd00 +#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ +#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ +#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ +#define DT_CHECKSUM 0x6ffffdf8 +#define DT_PLTPADSZ 0x6ffffdf9 +#define DT_MOVEENT 0x6ffffdfa +#define DT_MOVESZ 0x6ffffdfb +#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ +#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting + the following DT_* entry. */ +#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ +#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ +#define DT_VALRNGHI 0x6ffffdff +#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ +#define DT_VALNUM 12 + +/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the + Dyn.d_un.d_ptr field of the Elf*_Dyn structure. + + If any adjustment is made to the ELF object after it has been + built these entries will need to be adjusted. */ +#define DT_ADDRRNGLO 0x6ffffe00 +#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table. */ +#define DT_TLSDESC_PLT 0x6ffffef6 +#define DT_TLSDESC_GOT 0x6ffffef7 +#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ +#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ +#define DT_CONFIG 0x6ffffefa /* Configuration information. */ +#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ +#define DT_AUDIT 0x6ffffefc /* Object auditing. */ +#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ +#define DT_MOVETAB 0x6ffffefe /* Move table. */ +#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ +#define DT_ADDRRNGHI 0x6ffffeff +#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ +#define DT_ADDRNUM 11 + +/* The versioning entry types. The next are defined as part of the + GNU extension. */ +#define DT_VERSYM 0x6ffffff0 + +#define DT_RELACOUNT 0x6ffffff9 +#define DT_RELCOUNT 0x6ffffffa + +/* These were chosen by Sun. */ +#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ +#define DT_VERDEF 0x6ffffffc /* Address of version definition + table */ +#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ +#define DT_VERNEED 0x6ffffffe /* Address of table with needed + versions */ +#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ +#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ +#define DT_VERSIONTAGNUM 16 + +/* Sun added these machine-independent extensions in the "processor-specific" + range. Be compatible. */ +#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ +#define DT_FILTER 0x7fffffff /* Shared object to get values from */ +#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) +#define DT_EXTRANUM 3 + +/* Values of `d_un.d_val' in the DT_FLAGS entry. */ +#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ +#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ +#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ +#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ +#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ + +/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 + entry in the dynamic section. */ +#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ +#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ +#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ +#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ +#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ +#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ +#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ +#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ +#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ +#define DF_1_TRANS 0x00000200 +#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ +#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ +#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ +#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ +#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ +#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ +#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ +#define DF_1_NODIRECT 0x00020000 /* Object has no-direct binding. */ +#define DF_1_IGNMULDEF 0x00040000 +#define DF_1_NOKSYMS 0x00080000 +#define DF_1_NOHDR 0x00100000 +#define DF_1_EDITED 0x00200000 /* Object is modified after built. */ +#define DF_1_NORELOC 0x00400000 +#define DF_1_SYMINTPOSE 0x00800000 /* Object has individual interposers. */ +#define DF_1_GLOBAUDIT 0x01000000 /* Global auditing required. */ +#define DF_1_SINGLETON 0x02000000 /* Singleton symbols are used. */ + +/* Flags for the feature selection in DT_FEATURE_1. */ +#define DTF_1_PARINIT 0x00000001 +#define DTF_1_CONFEXP 0x00000002 + +/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ +#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ +#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not + generally available. */ + +/* Version definition sections. */ + +typedef struct +{ + Elf32_Half vd_version; /* Version revision */ + Elf32_Half vd_flags; /* Version information */ + Elf32_Half vd_ndx; /* Version Index */ + Elf32_Half vd_cnt; /* Number of associated aux entries */ + Elf32_Word vd_hash; /* Version name hash value */ + Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ + Elf32_Word vd_next; /* Offset in bytes to next verdef + entry */ +} Elf32_Verdef; + +typedef struct +{ + Elf64_Half vd_version; /* Version revision */ + Elf64_Half vd_flags; /* Version information */ + Elf64_Half vd_ndx; /* Version Index */ + Elf64_Half vd_cnt; /* Number of associated aux entries */ + Elf64_Word vd_hash; /* Version name hash value */ + Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ + Elf64_Word vd_next; /* Offset in bytes to next verdef + entry */ +} Elf64_Verdef; + + +/* Legal values for vd_version (version revision). */ +#define VER_DEF_NONE 0 /* No version */ +#define VER_DEF_CURRENT 1 /* Current version */ +#define VER_DEF_NUM 2 /* Given version number */ + +/* Legal values for vd_flags (version information flags). */ +#define VER_FLG_BASE 0x1 /* Version definition of file itself */ +#define VER_FLG_WEAK 0x2 /* Weak version identifier */ + +/* Versym symbol index values. */ +#define VER_NDX_LOCAL 0 /* Symbol is local. */ +#define VER_NDX_GLOBAL 1 /* Symbol is global. */ +#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ +#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ + +/* Auxialiary version information. */ + +typedef struct +{ + Elf32_Word vda_name; /* Version or dependency names */ + Elf32_Word vda_next; /* Offset in bytes to next verdaux + entry */ +} Elf32_Verdaux; + +typedef struct +{ + Elf64_Word vda_name; /* Version or dependency names */ + Elf64_Word vda_next; /* Offset in bytes to next verdaux + entry */ +} Elf64_Verdaux; + + +/* Version dependency section. */ + +typedef struct +{ + Elf32_Half vn_version; /* Version of structure */ + Elf32_Half vn_cnt; /* Number of associated aux entries */ + Elf32_Word vn_file; /* Offset of filename for this + dependency */ + Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ + Elf32_Word vn_next; /* Offset in bytes to next verneed + entry */ +} Elf32_Verneed; + +typedef struct +{ + Elf64_Half vn_version; /* Version of structure */ + Elf64_Half vn_cnt; /* Number of associated aux entries */ + Elf64_Word vn_file; /* Offset of filename for this + dependency */ + Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ + Elf64_Word vn_next; /* Offset in bytes to next verneed + entry */ +} Elf64_Verneed; + + +/* Legal values for vn_version (version revision). */ +#define VER_NEED_NONE 0 /* No version */ +#define VER_NEED_CURRENT 1 /* Current version */ +#define VER_NEED_NUM 2 /* Given version number */ + +/* Auxiliary needed version information. */ + +typedef struct +{ + Elf32_Word vna_hash; /* Hash value of dependency name */ + Elf32_Half vna_flags; /* Dependency specific information */ + Elf32_Half vna_other; /* Unused */ + Elf32_Word vna_name; /* Dependency name string offset */ + Elf32_Word vna_next; /* Offset in bytes to next vernaux + entry */ +} Elf32_Vernaux; + +typedef struct +{ + Elf64_Word vna_hash; /* Hash value of dependency name */ + Elf64_Half vna_flags; /* Dependency specific information */ + Elf64_Half vna_other; /* Unused */ + Elf64_Word vna_name; /* Dependency name string offset */ + Elf64_Word vna_next; /* Offset in bytes to next vernaux + entry */ +} Elf64_Vernaux; + + +/* Legal values for vna_flags. */ +#define VER_FLG_WEAK 0x2 /* Weak version identifier */ + + +/* Auxiliary vector. */ + +/* This vector is normally only used by the program interpreter. The + usual definition in an ABI supplement uses the name auxv_t. The + vector is not usually defined in a standard file, but it + can't hurt. We rename it to avoid conflicts. The sizes of these + types are an arrangement between the exec server and the program + interpreter, so we don't fully specify them here. */ + +typedef struct +{ + uint32_t a_type; /* Entry type */ + union + { + uint32_t a_val; /* Integer value */ + /* We use to have pointer elements added here. We cannot do that, + though, since it does not work when using 32-bit definitions + on 64-bit platforms and vice versa. */ + } a_un; +} Elf32_auxv_t; + +typedef struct +{ + uint64_t a_type; /* Entry type */ + union + { + uint64_t a_val; /* Integer value */ + /* We use to have pointer elements added here. We cannot do that, + though, since it does not work when using 32-bit definitions + on 64-bit platforms and vice versa. */ + } a_un; +} Elf64_auxv_t; + +//#include +/* Note section contents. Each entry in the note section begins with + a header of a fixed form. */ + +typedef struct +{ + Elf32_Word n_namesz; /* Length of the note's name. */ + Elf32_Word n_descsz; /* Length of the note's descriptor. */ + Elf32_Word n_type; /* Type of the note. */ +} Elf32_Nhdr; + +typedef struct +{ + Elf64_Word n_namesz; /* Length of the note's name. */ + Elf64_Word n_descsz; /* Length of the note's descriptor. */ + Elf64_Word n_type; /* Type of the note. */ +} Elf64_Nhdr; + +/* Known names of notes. */ + +/* Solaris entries in the note section have this name. */ +#define ELF_NOTE_SOLARIS "SUNW Solaris" + +/* Note entries for GNU systems have this name. */ +#define ELF_NOTE_GNU "GNU" + + +/* Defined types of notes for Solaris. */ + +/* Value of descriptor (one word) is desired pagesize for the binary. */ +#define ELF_NOTE_PAGESIZE_HINT 1 + + +/* Defined note types for GNU systems. */ + +/* ABI information. The descriptor consists of words: + word 0: OS descriptor + word 1: major version of the ABI + word 2: minor version of the ABI + word 3: subminor version of the ABI +*/ +#define NT_GNU_ABI_TAG 1 +#define ELF_NOTE_ABI NT_GNU_ABI_TAG /* Old name. */ + +/* Known OSes. These values can appear in word 0 of an + NT_GNU_ABI_TAG note section entry. */ +#define ELF_NOTE_OS_LINUX 0 +#define ELF_NOTE_OS_GNU 1 +#define ELF_NOTE_OS_SOLARIS2 2 +#define ELF_NOTE_OS_FREEBSD 3 + +/* Synthetic hwcap information. The descriptor begins with two words: + word 0: number of entries + word 1: bitmask of enabled entries + Then follow variable-length entries, one byte followed by a + '\0'-terminated hwcap name string. The byte gives the bit + number to test if enabled, (1U << bit) & bitmask. */ +#define NT_GNU_HWCAP 2 + +/* Build ID bits as generated by ld --build-id. + The descriptor consists of any nonzero number of bytes. */ +#define NT_GNU_BUILD_ID 3 + +/* Version note generated by GNU gold containing a version string. */ +#define NT_GNU_GOLD_VERSION 4 + + +/* Move records. */ +typedef struct +{ + Elf32_Xword m_value; /* Symbol value. */ + Elf32_Word m_info; /* Size and index. */ + Elf32_Word m_poffset; /* Symbol offset. */ + Elf32_Half m_repeat; /* Repeat count. */ + Elf32_Half m_stride; /* Stride info. */ +} Elf32_Move; + +typedef struct +{ + Elf64_Xword m_value; /* Symbol value. */ + Elf64_Xword m_info; /* Size and index. */ + Elf64_Xword m_poffset; /* Symbol offset. */ + Elf64_Half m_repeat; /* Repeat count. */ + Elf64_Half m_stride; /* Stride info. */ +} Elf64_Move; + +/* Macro to construct move records. */ +#define ELF32_M_SYM(info) ((info) >> 8) +#define ELF32_M_SIZE(info) ((unsigned char) (info)) +#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) + +#define ELF64_M_SYM(info) ELF32_M_SYM (info) +#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) +#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) + + +/* Motorola 68k specific definitions. */ + +/* Values for Elf32_Ehdr.e_flags. */ +#define EF_CPU32 0x00810000 + +/* m68k relocs. */ + +#define R_68K_NONE 0 /* No reloc */ +#define R_68K_32 1 /* Direct 32 bit */ +#define R_68K_16 2 /* Direct 16 bit */ +#define R_68K_8 3 /* Direct 8 bit */ +#define R_68K_PC32 4 /* PC relative 32 bit */ +#define R_68K_PC16 5 /* PC relative 16 bit */ +#define R_68K_PC8 6 /* PC relative 8 bit */ +#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ +#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ +#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ +#define R_68K_GOT32O 10 /* 32 bit GOT offset */ +#define R_68K_GOT16O 11 /* 16 bit GOT offset */ +#define R_68K_GOT8O 12 /* 8 bit GOT offset */ +#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ +#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ +#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ +#define R_68K_PLT32O 16 /* 32 bit PLT offset */ +#define R_68K_PLT16O 17 /* 16 bit PLT offset */ +#define R_68K_PLT8O 18 /* 8 bit PLT offset */ +#define R_68K_COPY 19 /* Copy symbol at runtime */ +#define R_68K_GLOB_DAT 20 /* Create GOT entry */ +#define R_68K_JMP_SLOT 21 /* Create PLT entry */ +#define R_68K_RELATIVE 22 /* Adjust by program base */ +#define R_68K_TLS_GD32 25 /* 32 bit GOT offset for GD */ +#define R_68K_TLS_GD16 26 /* 16 bit GOT offset for GD */ +#define R_68K_TLS_GD8 27 /* 8 bit GOT offset for GD */ +#define R_68K_TLS_LDM32 28 /* 32 bit GOT offset for LDM */ +#define R_68K_TLS_LDM16 29 /* 16 bit GOT offset for LDM */ +#define R_68K_TLS_LDM8 30 /* 8 bit GOT offset for LDM */ +#define R_68K_TLS_LDO32 31 /* 32 bit module-relative offset */ +#define R_68K_TLS_LDO16 32 /* 16 bit module-relative offset */ +#define R_68K_TLS_LDO8 33 /* 8 bit module-relative offset */ +#define R_68K_TLS_IE32 34 /* 32 bit GOT offset for IE */ +#define R_68K_TLS_IE16 35 /* 16 bit GOT offset for IE */ +#define R_68K_TLS_IE8 36 /* 8 bit GOT offset for IE */ +#define R_68K_TLS_LE32 37 /* 32 bit offset relative to + static TLS block */ +#define R_68K_TLS_LE16 38 /* 16 bit offset relative to + static TLS block */ +#define R_68K_TLS_LE8 39 /* 8 bit offset relative to + static TLS block */ +#define R_68K_TLS_DTPMOD32 40 /* 32 bit module number */ +#define R_68K_TLS_DTPREL32 41 /* 32 bit module-relative offset */ +#define R_68K_TLS_TPREL32 42 /* 32 bit TP-relative offset */ +/* Keep this the last entry. */ +#define R_68K_NUM 43 + +/* Intel 80386 specific definitions. */ + +/* i386 relocs. */ + +#define R_386_NONE 0 /* No reloc */ +#define R_386_32 1 /* Direct 32 bit */ +#define R_386_PC32 2 /* PC relative 32 bit */ +#define R_386_GOT32 3 /* 32 bit GOT entry */ +#define R_386_PLT32 4 /* 32 bit PLT address */ +#define R_386_COPY 5 /* Copy symbol at runtime */ +#define R_386_GLOB_DAT 6 /* Create GOT entry */ +#define R_386_JMP_SLOT 7 /* Create PLT entry */ +#define R_386_RELATIVE 8 /* Adjust by program base */ +#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ +#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ +#define R_386_32PLT 11 +#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ +#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS + block offset */ +#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block + offset */ +#define R_386_TLS_LE 17 /* Offset relative to static TLS + block */ +#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of + general dynamic thread local data */ +#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of + local dynamic thread local data + in LE code */ +#define R_386_16 20 +#define R_386_PC16 21 +#define R_386_8 22 +#define R_386_PC8 23 +#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic + thread local data */ +#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ +#define R_386_TLS_GD_CALL 26 /* Relocation for call to + __tls_get_addr() */ +#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ +#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic + thread local data in LE code */ +#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ +#define R_386_TLS_LDM_CALL 30 /* Relocation for call to + __tls_get_addr() in LDM code */ +#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ +#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ +#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS + block offset */ +#define R_386_TLS_LE_32 34 /* Negated offset relative to static + TLS block */ +#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ +#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ +#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ +#define R_386_SIZE32 38 /* 32-bit symbol size */ +#define R_386_TLS_GOTDESC 39 /* GOT offset for TLS descriptor. */ +#define R_386_TLS_DESC_CALL 40 /* Marker of call through TLS + descriptor for + relaxation. */ +#define R_386_TLS_DESC 41 /* TLS descriptor containing + pointer to code and to + argument, returning the TLS + offset for the symbol. */ +#define R_386_IRELATIVE 42 /* Adjust indirectly by program base */ +/* Keep this the last entry. */ +#define R_386_NUM 43 + +/* SUN SPARC specific definitions. */ + +/* Legal values for ST_TYPE subfield of st_info (symbol type). */ + +#define STT_SPARC_REGISTER 13 /* Global register reserved to app. */ + +/* Values for Elf64_Ehdr.e_flags. */ + +#define EF_SPARCV9_MM 3 +#define EF_SPARCV9_TSO 0 +#define EF_SPARCV9_PSO 1 +#define EF_SPARCV9_RMO 2 +#define EF_SPARC_LEDATA 0x800000 /* little endian data */ +#define EF_SPARC_EXT_MASK 0xFFFF00 +#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ +#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ +#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ +#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ + +/* SPARC relocs. */ + +#define R_SPARC_NONE 0 /* No reloc */ +#define R_SPARC_8 1 /* Direct 8 bit */ +#define R_SPARC_16 2 /* Direct 16 bit */ +#define R_SPARC_32 3 /* Direct 32 bit */ +#define R_SPARC_DISP8 4 /* PC relative 8 bit */ +#define R_SPARC_DISP16 5 /* PC relative 16 bit */ +#define R_SPARC_DISP32 6 /* PC relative 32 bit */ +#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ +#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ +#define R_SPARC_HI22 9 /* High 22 bit */ +#define R_SPARC_22 10 /* Direct 22 bit */ +#define R_SPARC_13 11 /* Direct 13 bit */ +#define R_SPARC_LO10 12 /* Truncated 10 bit */ +#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ +#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ +#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ +#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ +#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ +#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ +#define R_SPARC_COPY 19 /* Copy symbol at runtime */ +#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ +#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ +#define R_SPARC_RELATIVE 22 /* Adjust by program base */ +#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ + +/* Additional Sparc64 relocs. */ + +#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ +#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ +#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ +#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ +#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ +#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ +#define R_SPARC_10 30 /* Direct 10 bit */ +#define R_SPARC_11 31 /* Direct 11 bit */ +#define R_SPARC_64 32 /* Direct 64 bit */ +#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ +#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ +#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ +#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ +#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ +#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ +#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ +#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ +#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ +#define R_SPARC_GLOB_JMP 42 /* was part of v9 ABI but was removed */ +#define R_SPARC_7 43 /* Direct 7 bit */ +#define R_SPARC_5 44 /* Direct 5 bit */ +#define R_SPARC_6 45 /* Direct 6 bit */ +#define R_SPARC_DISP64 46 /* PC relative 64 bit */ +#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ +#define R_SPARC_HIX22 48 /* High 22 bit complemented */ +#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ +#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ +#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ +#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ +#define R_SPARC_REGISTER 53 /* Global register usage */ +#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ +#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ +#define R_SPARC_TLS_GD_HI22 56 +#define R_SPARC_TLS_GD_LO10 57 +#define R_SPARC_TLS_GD_ADD 58 +#define R_SPARC_TLS_GD_CALL 59 +#define R_SPARC_TLS_LDM_HI22 60 +#define R_SPARC_TLS_LDM_LO10 61 +#define R_SPARC_TLS_LDM_ADD 62 +#define R_SPARC_TLS_LDM_CALL 63 +#define R_SPARC_TLS_LDO_HIX22 64 +#define R_SPARC_TLS_LDO_LOX10 65 +#define R_SPARC_TLS_LDO_ADD 66 +#define R_SPARC_TLS_IE_HI22 67 +#define R_SPARC_TLS_IE_LO10 68 +#define R_SPARC_TLS_IE_LD 69 +#define R_SPARC_TLS_IE_LDX 70 +#define R_SPARC_TLS_IE_ADD 71 +#define R_SPARC_TLS_LE_HIX22 72 +#define R_SPARC_TLS_LE_LOX10 73 +#define R_SPARC_TLS_DTPMOD32 74 +#define R_SPARC_TLS_DTPMOD64 75 +#define R_SPARC_TLS_DTPOFF32 76 +#define R_SPARC_TLS_DTPOFF64 77 +#define R_SPARC_TLS_TPOFF32 78 +#define R_SPARC_TLS_TPOFF64 79 +#define R_SPARC_GOTDATA_HIX22 80 +#define R_SPARC_GOTDATA_LOX10 81 +#define R_SPARC_GOTDATA_OP_HIX22 82 +#define R_SPARC_GOTDATA_OP_LOX10 83 +#define R_SPARC_GOTDATA_OP 84 +#define R_SPARC_H34 85 +#define R_SPARC_SIZE32 86 +#define R_SPARC_SIZE64 87 +#define R_SPARC_WDISP10 88 +#define R_SPARC_JMP_IREL 248 +#define R_SPARC_IRELATIVE 249 +#define R_SPARC_GNU_VTINHERIT 250 +#define R_SPARC_GNU_VTENTRY 251 +#define R_SPARC_REV32 252 +/* Keep this the last entry. */ +#define R_SPARC_NUM 253 + +/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ + +#define DT_SPARC_REGISTER 0x70000001 +#define DT_SPARC_NUM 2 + +/* MIPS R3000 specific definitions. */ + +/* Legal values for e_flags field of Elf32_Ehdr. */ + +#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used. */ +#define EF_MIPS_PIC 2 /* Contains PIC code. */ +#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence. */ +#define EF_MIPS_XGOT 8 +#define EF_MIPS_64BIT_WHIRL 16 +#define EF_MIPS_ABI2 32 +#define EF_MIPS_ABI_ON32 64 +#define EF_MIPS_FP64 512 /* Uses FP64 (12 callee-saved). */ +#define EF_MIPS_NAN2008 1024 /* Uses IEEE 754-2008 NaN encoding. */ +#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level. */ + +/* Legal values for MIPS architecture level. */ + +#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ +#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ +#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ +#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ +#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ +#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ +#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ +#define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32r2 code. */ +#define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64r2 code. */ + +/* The following are unofficial names and should not be used. */ + +#define E_MIPS_ARCH_1 EF_MIPS_ARCH_1 +#define E_MIPS_ARCH_2 EF_MIPS_ARCH_2 +#define E_MIPS_ARCH_3 EF_MIPS_ARCH_3 +#define E_MIPS_ARCH_4 EF_MIPS_ARCH_4 +#define E_MIPS_ARCH_5 EF_MIPS_ARCH_5 +#define E_MIPS_ARCH_32 EF_MIPS_ARCH_32 +#define E_MIPS_ARCH_64 EF_MIPS_ARCH_64 + +/* Special section indices. */ + +#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols. */ +#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ +#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ +#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols. */ +#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols. */ + +/* Legal values for sh_type field of Elf32_Shdr. */ + +#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link. */ +#define SHT_MIPS_MSYM 0x70000001 +#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols. */ +#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes. */ +#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ +#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging info. */ +#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information. */ +#define SHT_MIPS_PACKAGE 0x70000007 +#define SHT_MIPS_PACKSYM 0x70000008 +#define SHT_MIPS_RELD 0x70000009 +#define SHT_MIPS_IFACE 0x7000000b +#define SHT_MIPS_CONTENT 0x7000000c +#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ +#define SHT_MIPS_SHDR 0x70000010 +#define SHT_MIPS_FDESC 0x70000011 +#define SHT_MIPS_EXTSYM 0x70000012 +#define SHT_MIPS_DENSE 0x70000013 +#define SHT_MIPS_PDESC 0x70000014 +#define SHT_MIPS_LOCSYM 0x70000015 +#define SHT_MIPS_AUXSYM 0x70000016 +#define SHT_MIPS_OPTSYM 0x70000017 +#define SHT_MIPS_LOCSTR 0x70000018 +#define SHT_MIPS_LINE 0x70000019 +#define SHT_MIPS_RFDESC 0x7000001a +#define SHT_MIPS_DELTASYM 0x7000001b +#define SHT_MIPS_DELTAINST 0x7000001c +#define SHT_MIPS_DELTACLASS 0x7000001d +#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ +#define SHT_MIPS_DELTADECL 0x7000001f +#define SHT_MIPS_SYMBOL_LIB 0x70000020 +#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ +#define SHT_MIPS_TRANSLATE 0x70000022 +#define SHT_MIPS_PIXIE 0x70000023 +#define SHT_MIPS_XLATE 0x70000024 +#define SHT_MIPS_XLATE_DEBUG 0x70000025 +#define SHT_MIPS_WHIRL 0x70000026 +#define SHT_MIPS_EH_REGION 0x70000027 +#define SHT_MIPS_XLATE_OLD 0x70000028 +#define SHT_MIPS_PDR_EXCEPTION 0x70000029 + +/* Legal values for sh_flags field of Elf32_Shdr. */ + +#define SHF_MIPS_GPREL 0x10000000 /* Must be in global data area. */ +#define SHF_MIPS_MERGE 0x20000000 +#define SHF_MIPS_ADDR 0x40000000 +#define SHF_MIPS_STRINGS 0x80000000 +#define SHF_MIPS_NOSTRIP 0x08000000 +#define SHF_MIPS_LOCAL 0x04000000 +#define SHF_MIPS_NAMES 0x02000000 +#define SHF_MIPS_NODUPE 0x01000000 + + +/* Symbol tables. */ + +/* MIPS specific values for `st_other'. */ +#define STO_MIPS_DEFAULT 0x0 +#define STO_MIPS_INTERNAL 0x1 +#define STO_MIPS_HIDDEN 0x2 +#define STO_MIPS_PROTECTED 0x3 +#define STO_MIPS_PLT 0x8 +#define STO_MIPS_SC_ALIGN_UNUSED 0xff + +/* MIPS specific values for `st_info'. */ +#define STB_MIPS_SPLIT_COMMON 13 + +/* Entries found in sections of type SHT_MIPS_GPTAB. */ + +typedef union +{ + struct + { + Elf32_Word gt_current_g_value; /* -G value used for compilation. */ + Elf32_Word gt_unused; /* Not used. */ + } gt_header; /* First entry in section. */ + struct + { + Elf32_Word gt_g_value; /* If this value were used for -G. */ + Elf32_Word gt_bytes; /* This many bytes would be used. */ + } gt_entry; /* Subsequent entries in section. */ +} Elf32_gptab; + +/* Entry found in sections of type SHT_MIPS_REGINFO. */ + +typedef struct +{ + Elf32_Word ri_gprmask; /* General registers used. */ + Elf32_Word ri_cprmask[4]; /* Coprocessor registers used. */ + Elf32_Sword ri_gp_value; /* $gp register value. */ +} Elf32_RegInfo; + +/* Entries found in sections of type SHT_MIPS_OPTIONS. */ + +typedef struct +{ + unsigned char kind; /* Determines interpretation of the + variable part of descriptor. */ + unsigned char size; /* Size of descriptor, including header. */ + Elf32_Section section; /* Section header index of section affected, + 0 for global options. */ + Elf32_Word info; /* Kind-specific information. */ +} Elf_Options; + +/* Values for `kind' field in Elf_Options. */ + +#define ODK_NULL 0 /* Undefined. */ +#define ODK_REGINFO 1 /* Register usage information. */ +#define ODK_EXCEPTIONS 2 /* Exception processing options. */ +#define ODK_PAD 3 /* Section padding options. */ +#define ODK_HWPATCH 4 /* Hardware workarounds performed */ +#define ODK_FILL 5 /* record the fill value used by the linker. */ +#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ +#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ +#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ + +/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ + +#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ +#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ +#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ +#define OEX_SMM 0x20000 /* Force sequential memory mode? */ +#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ +#define OEX_PRECISEFP OEX_FPDBUG +#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ + +#define OEX_FPU_INVAL 0x10 +#define OEX_FPU_DIV0 0x08 +#define OEX_FPU_OFLO 0x04 +#define OEX_FPU_UFLO 0x02 +#define OEX_FPU_INEX 0x01 + +/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ + +#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ +#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ +#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ +#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ + +#define OPAD_PREFIX 0x1 +#define OPAD_POSTFIX 0x2 +#define OPAD_SYMBOL 0x4 + +/* Entry found in `.options' section. */ + +typedef struct +{ + Elf32_Word hwp_flags1; /* Extra flags. */ + Elf32_Word hwp_flags2; /* Extra flags. */ +} Elf_Options_Hw; + +/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ + +#define OHWA0_R4KEOP_CHECKED 0x00000001 +#define OHWA1_R4KEOP_CLEAN 0x00000002 + +/* MIPS relocs. */ + +#define R_MIPS_NONE 0 /* No reloc */ +#define R_MIPS_16 1 /* Direct 16 bit */ +#define R_MIPS_32 2 /* Direct 32 bit */ +#define R_MIPS_REL32 3 /* PC relative 32 bit */ +#define R_MIPS_26 4 /* Direct 26 bit shifted */ +#define R_MIPS_HI16 5 /* High 16 bit */ +#define R_MIPS_LO16 6 /* Low 16 bit */ +#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ +#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ +#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ +#define R_MIPS_PC16 10 /* PC relative 16 bit */ +#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ +#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ + +#define R_MIPS_SHIFT5 16 +#define R_MIPS_SHIFT6 17 +#define R_MIPS_64 18 +#define R_MIPS_GOT_DISP 19 +#define R_MIPS_GOT_PAGE 20 +#define R_MIPS_GOT_OFST 21 +#define R_MIPS_GOT_HI16 22 +#define R_MIPS_GOT_LO16 23 +#define R_MIPS_SUB 24 +#define R_MIPS_INSERT_A 25 +#define R_MIPS_INSERT_B 26 +#define R_MIPS_DELETE 27 +#define R_MIPS_HIGHER 28 +#define R_MIPS_HIGHEST 29 +#define R_MIPS_CALL_HI16 30 +#define R_MIPS_CALL_LO16 31 +#define R_MIPS_SCN_DISP 32 +#define R_MIPS_REL16 33 +#define R_MIPS_ADD_IMMEDIATE 34 +#define R_MIPS_PJUMP 35 +#define R_MIPS_RELGOT 36 +#define R_MIPS_JALR 37 +#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ +#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ +#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ +#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ +#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ +#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ +#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ +#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ +#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ +#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ +#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ +#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ +#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ +#define R_MIPS_GLOB_DAT 51 +#define R_MIPS_COPY 126 +#define R_MIPS_JUMP_SLOT 127 +/* Keep this the last entry. */ +#define R_MIPS_NUM 128 + +/* Legal values for p_type field of Elf32_Phdr. */ + +#define PT_MIPS_REGINFO 0x70000000 /* Register usage information. */ +#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ +#define PT_MIPS_OPTIONS 0x70000002 +#define PT_MIPS_ABIFLAGS 0x70000003 /* FP mode requirement. */ + +/* Special program header types. */ + +#define PF_MIPS_LOCAL 0x10000000 + +/* Legal values for d_tag field of Elf32_Dyn. */ + +#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ +#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ +#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ +#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ +#define DT_MIPS_FLAGS 0x70000005 /* Flags */ +#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ +#define DT_MIPS_MSYM 0x70000007 +#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ +#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ +#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ +#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ +#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ +#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ +#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ +#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ +#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ +#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ +#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ +#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in + DT_MIPS_DELTA_CLASS. */ +#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ +#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in + DT_MIPS_DELTA_INSTANCE. */ +#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ +#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in + DT_MIPS_DELTA_RELOC. */ +#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta + relocations refer to. */ +#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in + DT_MIPS_DELTA_SYM. */ +#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the + class declaration. */ +#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in + DT_MIPS_DELTA_CLASSSYM. */ +#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ +#define DT_MIPS_PIXIE_INIT 0x70000023 +#define DT_MIPS_SYMBOL_LIB 0x70000024 +#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 +#define DT_MIPS_LOCAL_GOTIDX 0x70000026 +#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 +#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 +#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ +#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ +#define DT_MIPS_DYNSTR_ALIGN 0x7000002b +#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ +#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve + function stored in GOT. */ +#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added + by rld on dlopen() calls. */ +#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ +#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ +#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ +/* The address of .got.plt in an executable using the new non-PIC ABI. */ +#define DT_MIPS_PLTGOT 0x70000032 +/* The base of the PLT in an executable using the new non-PIC ABI if that + PLT is writable. For a non-writable PLT, this is omitted or has a zero + value. */ +#define DT_MIPS_RWPLT 0x70000034 +/* An alternative description of the classic MIPS RLD_MAP that is usable + in a PIE as it stores a relative offset from the address of the tag + rather than an absolute address. */ +#define DT_MIPS_RLD_MAP_REL 0x70000035 +#define DT_MIPS_NUM 0x36 + +/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ + +#define RHF_NONE 0 /* No flags */ +#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ +#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ +#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ +#define RHF_NO_MOVE (1 << 3) +#define RHF_SGI_ONLY (1 << 4) +#define RHF_GUARANTEE_INIT (1 << 5) +#define RHF_DELTA_C_PLUS_PLUS (1 << 6) +#define RHF_GUARANTEE_START_INIT (1 << 7) +#define RHF_PIXIE (1 << 8) +#define RHF_DEFAULT_DELAY_LOAD (1 << 9) +#define RHF_REQUICKSTART (1 << 10) +#define RHF_REQUICKSTARTED (1 << 11) +#define RHF_CORD (1 << 12) +#define RHF_NO_UNRES_UNDEF (1 << 13) +#define RHF_RLD_ORDER_SAFE (1 << 14) + +/* Entries found in sections of type SHT_MIPS_LIBLIST. */ + +typedef struct +{ + Elf32_Word l_name; /* Name (string table index) */ + Elf32_Word l_time_stamp; /* Timestamp */ + Elf32_Word l_checksum; /* Checksum */ + Elf32_Word l_version; /* Interface version */ + Elf32_Word l_flags; /* Flags */ +} Elf32_Lib; + +typedef struct +{ + Elf64_Word l_name; /* Name (string table index) */ + Elf64_Word l_time_stamp; /* Timestamp */ + Elf64_Word l_checksum; /* Checksum */ + Elf64_Word l_version; /* Interface version */ + Elf64_Word l_flags; /* Flags */ +} Elf64_Lib; + + +/* Legal values for l_flags. */ + +#define LL_NONE 0 +#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ +#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ +#define LL_REQUIRE_MINOR (1 << 2) +#define LL_EXPORTS (1 << 3) +#define LL_DELAY_LOAD (1 << 4) +#define LL_DELTA (1 << 5) + +/* Entries found in sections of type SHT_MIPS_CONFLICT. */ + +typedef Elf32_Addr Elf32_Conflict; + +typedef struct +{ + /* Version of flags structure. */ + Elf32_Half version; + /* The level of the ISA: 1-5, 32, 64. */ + unsigned char isa_level; + /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise. */ + unsigned char isa_rev; + /* The size of general purpose registers. */ + unsigned char gpr_size; + /* The size of co-processor 1 registers. */ + unsigned char cpr1_size; + /* The size of co-processor 2 registers. */ + unsigned char cpr2_size; + /* The floating-point ABI. */ + unsigned char fp_abi; + /* Processor-specific extension. */ + Elf32_Word isa_ext; + /* Mask of ASEs used. */ + Elf32_Word ases; + /* Mask of general flags. */ + Elf32_Word flags1; + Elf32_Word flags2; +} Elf_MIPS_ABIFlags_v0; + +/* Values for the register size bytes of an abi flags structure. */ + +#define MIPS_AFL_REG_NONE 0x00 /* No registers. */ +#define MIPS_AFL_REG_32 0x01 /* 32-bit registers. */ +#define MIPS_AFL_REG_64 0x02 /* 64-bit registers. */ +#define MIPS_AFL_REG_128 0x03 /* 128-bit registers. */ + +/* Masks for the ases word of an ABI flags structure. */ + +#define MIPS_AFL_ASE_DSP 0x00000001 /* DSP ASE. */ +#define MIPS_AFL_ASE_DSPR2 0x00000002 /* DSP R2 ASE. */ +#define MIPS_AFL_ASE_EVA 0x00000004 /* Enhanced VA Scheme. */ +#define MIPS_AFL_ASE_MCU 0x00000008 /* MCU (MicroController) ASE. */ +#define MIPS_AFL_ASE_MDMX 0x00000010 /* MDMX ASE. */ +#define MIPS_AFL_ASE_MIPS3D 0x00000020 /* MIPS-3D ASE. */ +#define MIPS_AFL_ASE_MT 0x00000040 /* MT ASE. */ +#define MIPS_AFL_ASE_SMARTMIPS 0x00000080 /* SmartMIPS ASE. */ +#define MIPS_AFL_ASE_VIRT 0x00000100 /* VZ ASE. */ +#define MIPS_AFL_ASE_MSA 0x00000200 /* MSA ASE. */ +#define MIPS_AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */ +#define MIPS_AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */ +#define MIPS_AFL_ASE_XPA 0x00001000 /* XPA ASE. */ +#define MIPS_AFL_ASE_MASK 0x00001fff /* All ASEs. */ + +/* Values for the isa_ext word of an ABI flags structure. */ + +#define MIPS_AFL_EXT_XLR 1 /* RMI Xlr instruction. */ +#define MIPS_AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */ +#define MIPS_AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */ +#define MIPS_AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */ +#define MIPS_AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */ +#define MIPS_AFL_EXT_5900 6 /* MIPS R5900 instruction. */ +#define MIPS_AFL_EXT_4650 7 /* MIPS R4650 instruction. */ +#define MIPS_AFL_EXT_4010 8 /* LSI R4010 instruction. */ +#define MIPS_AFL_EXT_4100 9 /* NEC VR4100 instruction. */ +#define MIPS_AFL_EXT_3900 10 /* Toshiba R3900 instruction. */ +#define MIPS_AFL_EXT_10000 11 /* MIPS R10000 instruction. */ +#define MIPS_AFL_EXT_SB1 12 /* Broadcom SB-1 instruction. */ +#define MIPS_AFL_EXT_4111 13 /* NEC VR4111/VR4181 instruction. */ +#define MIPS_AFL_EXT_4120 14 /* NEC VR4120 instruction. */ +#define MIPS_AFL_EXT_5400 15 /* NEC VR5400 instruction. */ +#define MIPS_AFL_EXT_5500 16 /* NEC VR5500 instruction. */ +#define MIPS_AFL_EXT_LOONGSON_2E 17 /* ST Microelectronics Loongson 2E. */ +#define MIPS_AFL_EXT_LOONGSON_2F 18 /* ST Microelectronics Loongson 2F. */ + +/* Masks for the flags1 word of an ABI flags structure. */ +#define MIPS_AFL_FLAGS1_ODDSPREG 1 /* Uses odd single-precision registers. */ + +/* Object attribute values. */ +enum +{ + /* Not tagged or not using any ABIs affected by the differences. */ + Val_GNU_MIPS_ABI_FP_ANY = 0, + /* Using hard-float -mdouble-float. */ + Val_GNU_MIPS_ABI_FP_DOUBLE = 1, + /* Using hard-float -msingle-float. */ + Val_GNU_MIPS_ABI_FP_SINGLE = 2, + /* Using soft-float. */ + Val_GNU_MIPS_ABI_FP_SOFT = 3, + /* Using -mips32r2 -mfp64. */ + Val_GNU_MIPS_ABI_FP_OLD_64 = 4, + /* Using -mfpxx. */ + Val_GNU_MIPS_ABI_FP_XX = 5, + /* Using -mips32r2 -mfp64. */ + Val_GNU_MIPS_ABI_FP_64 = 6, + /* Using -mips32r2 -mfp64 -mno-odd-spreg. */ + Val_GNU_MIPS_ABI_FP_64A = 7, + /* Maximum allocated FP ABI value. */ + Val_GNU_MIPS_ABI_FP_MAX = 7 +}; + +/* HPPA specific definitions. */ + +/* Legal values for e_flags field of Elf32_Ehdr. */ + +#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ +#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ +#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ +#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ +#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch + prediction. */ +#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ +#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ + +/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ + +#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ +#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ +#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ + +/* Additional section indeces. */ + +#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared + symbols in ANSI C. */ +#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ + +/* Legal values for sh_type field of Elf32_Shdr. */ + +#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ +#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ +#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ + +/* Legal values for sh_flags field of Elf32_Shdr. */ + +#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ +#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ +#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ + +/* Legal values for ST_TYPE subfield of st_info (symbol type). */ + +#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ + +#define STT_HP_OPAQUE (STT_LOOS + 0x1) +#define STT_HP_STUB (STT_LOOS + 0x2) + +/* HPPA relocs. */ + +#define R_PARISC_NONE 0 /* No reloc. */ +#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ +#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ +#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ +#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ +#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ +#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ +#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ +#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ +#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ +#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ +#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ +#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ +#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ +#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ +#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ +#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ +#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ +#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ +#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ +#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ +#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ +#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ +#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ +#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ +#define R_PARISC_FPTR64 64 /* 64 bits function address. */ +#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ +#define R_PARISC_PLABEL21L 66 /* Left 21 bits of fdesc address. */ +#define R_PARISC_PLABEL14R 70 /* Right 14 bits of fdesc address. */ +#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ +#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ +#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ +#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ +#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ +#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ +#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ +#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ +#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ +#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ +#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ +#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ +#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ +#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ +#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ +#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ +#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ +#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ +#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ +#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ +#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ +#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ +#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ +#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ +#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ +#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ +#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ +#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ +#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ +#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ +#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ +#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ +#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ +#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ +#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ +#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ +#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ +#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ +#define R_PARISC_LORESERVE 128 +#define R_PARISC_COPY 128 /* Copy relocation. */ +#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ +#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ +#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ +#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ +#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ +#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ +#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ +#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ +#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ +#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ +#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ +#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ +#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ +#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ +#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ +#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ +#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ +#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ +#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ +#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ +#define R_PARISC_GNU_VTENTRY 232 +#define R_PARISC_GNU_VTINHERIT 233 +#define R_PARISC_TLS_GD21L 234 /* GD 21-bit left. */ +#define R_PARISC_TLS_GD14R 235 /* GD 14-bit right. */ +#define R_PARISC_TLS_GDCALL 236 /* GD call to __t_g_a. */ +#define R_PARISC_TLS_LDM21L 237 /* LD module 21-bit left. */ +#define R_PARISC_TLS_LDM14R 238 /* LD module 14-bit right. */ +#define R_PARISC_TLS_LDMCALL 239 /* LD module call to __t_g_a. */ +#define R_PARISC_TLS_LDO21L 240 /* LD offset 21-bit left. */ +#define R_PARISC_TLS_LDO14R 241 /* LD offset 14-bit right. */ +#define R_PARISC_TLS_DTPMOD32 242 /* DTP module 32-bit. */ +#define R_PARISC_TLS_DTPMOD64 243 /* DTP module 64-bit. */ +#define R_PARISC_TLS_DTPOFF32 244 /* DTP offset 32-bit. */ +#define R_PARISC_TLS_DTPOFF64 245 /* DTP offset 32-bit. */ +#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L +#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R +#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L +#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R +#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 +#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 +#define R_PARISC_HIRESERVE 255 + +/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ + +#define PT_HP_TLS (PT_LOOS + 0x0) +#define PT_HP_CORE_NONE (PT_LOOS + 0x1) +#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) +#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) +#define PT_HP_CORE_COMM (PT_LOOS + 0x4) +#define PT_HP_CORE_PROC (PT_LOOS + 0x5) +#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) +#define PT_HP_CORE_STACK (PT_LOOS + 0x7) +#define PT_HP_CORE_SHM (PT_LOOS + 0x8) +#define PT_HP_CORE_MMF (PT_LOOS + 0x9) +#define PT_HP_PARALLEL (PT_LOOS + 0x10) +#define PT_HP_FASTBIND (PT_LOOS + 0x11) +#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) +#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) +#define PT_HP_STACK (PT_LOOS + 0x14) + +#define PT_PARISC_ARCHEXT 0x70000000 +#define PT_PARISC_UNWIND 0x70000001 + +/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ + +#define PF_PARISC_SBP 0x08000000 + +#define PF_HP_PAGE_SIZE 0x00100000 +#define PF_HP_FAR_SHARED 0x00200000 +#define PF_HP_NEAR_SHARED 0x00400000 +#define PF_HP_CODE 0x01000000 +#define PF_HP_MODIFY 0x02000000 +#define PF_HP_LAZYSWAP 0x04000000 +#define PF_HP_SBP 0x08000000 + + +/* Alpha specific definitions. */ + +/* Legal values for e_flags field of Elf64_Ehdr. */ + +#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ +#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ + +/* Legal values for sh_type field of Elf64_Shdr. */ + +/* These two are primerily concerned with ECOFF debugging info. */ +#define SHT_ALPHA_DEBUG 0x70000001 +#define SHT_ALPHA_REGINFO 0x70000002 + +/* Legal values for sh_flags field of Elf64_Shdr. */ + +#define SHF_ALPHA_GPREL 0x10000000 + +/* Legal values for st_other field of Elf64_Sym. */ +#define STO_ALPHA_NOPV 0x80 /* No PV required. */ +#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ + +/* Alpha relocs. */ + +#define R_ALPHA_NONE 0 /* No reloc */ +#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ +#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ +#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ +#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ +#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ +#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ +#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ +#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ +#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ +#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ +#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ +#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ +#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ +#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ +#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ +#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ +#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ +#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ +#define R_ALPHA_TLS_GD_HI 28 +#define R_ALPHA_TLSGD 29 +#define R_ALPHA_TLS_LDM 30 +#define R_ALPHA_DTPMOD64 31 +#define R_ALPHA_GOTDTPREL 32 +#define R_ALPHA_DTPREL64 33 +#define R_ALPHA_DTPRELHI 34 +#define R_ALPHA_DTPRELLO 35 +#define R_ALPHA_DTPREL16 36 +#define R_ALPHA_GOTTPREL 37 +#define R_ALPHA_TPREL64 38 +#define R_ALPHA_TPRELHI 39 +#define R_ALPHA_TPRELLO 40 +#define R_ALPHA_TPREL16 41 +/* Keep this the last entry. */ +#define R_ALPHA_NUM 46 + +/* Magic values of the LITUSE relocation addend. */ +#define LITUSE_ALPHA_ADDR 0 +#define LITUSE_ALPHA_BASE 1 +#define LITUSE_ALPHA_BYTOFF 2 +#define LITUSE_ALPHA_JSR 3 +#define LITUSE_ALPHA_TLS_GD 4 +#define LITUSE_ALPHA_TLS_LDM 5 + +/* Legal values for d_tag of Elf64_Dyn. */ +#define DT_ALPHA_PLTRO (DT_LOPROC + 0) +#define DT_ALPHA_NUM 1 + +/* PowerPC specific declarations */ + +/* Values for Elf32/64_Ehdr.e_flags. */ +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ + +/* Cygnus local bits below */ +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib + flag */ + +/* PowerPC relocations defined by the ABIs */ +#define R_PPC_NONE 0 +#define R_PPC_ADDR32 1 /* 32bit absolute address */ +#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ +#define R_PPC_ADDR16 3 /* 16bit absolute address */ +#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ +#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ +#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ +#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ +#define R_PPC_ADDR14_BRTAKEN 8 +#define R_PPC_ADDR14_BRNTAKEN 9 +#define R_PPC_REL24 10 /* PC relative 26 bit */ +#define R_PPC_REL14 11 /* PC relative 16 bit */ +#define R_PPC_REL14_BRTAKEN 12 +#define R_PPC_REL14_BRNTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLTREL24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_UADDR32 24 +#define R_PPC_UADDR16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 + +/* PowerPC relocations defined for the TLS access ABI. */ +#define R_PPC_TLS 67 /* none (sym+add)@tls */ +#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ +#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ +#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ +#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ +#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ +#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ +#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ +#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ +#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ +#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ +#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ +#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ +#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ +#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ +#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ +#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ +#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ +#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ +#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ +#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ +#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ +#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ +#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ +#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ +#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ +#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ +#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ +#define R_PPC_TLSGD 95 /* none (sym+add)@tlsgd */ +#define R_PPC_TLSLD 96 /* none (sym+add)@tlsld */ + +/* The remaining relocs are from the Embedded ELF ABI, and are not + in the SVR4 ELF ABI. */ +#define R_PPC_EMB_NADDR32 101 +#define R_PPC_EMB_NADDR16 102 +#define R_PPC_EMB_NADDR16_LO 103 +#define R_PPC_EMB_NADDR16_HI 104 +#define R_PPC_EMB_NADDR16_HA 105 +#define R_PPC_EMB_SDAI16 106 +#define R_PPC_EMB_SDA2I16 107 +#define R_PPC_EMB_SDA2REL 108 +#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ +#define R_PPC_EMB_MRKREF 110 +#define R_PPC_EMB_RELSEC16 111 +#define R_PPC_EMB_RELST_LO 112 +#define R_PPC_EMB_RELST_HI 113 +#define R_PPC_EMB_RELST_HA 114 +#define R_PPC_EMB_BIT_FLD 115 +#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ + +/* Diab tool relocations. */ +#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ +#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ +#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ +#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ +#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ +#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ + +/* GNU extension to support local ifunc. */ +#define R_PPC_IRELATIVE 248 + +/* GNU relocs used in PIC code sequences. */ +#define R_PPC_REL16 249 /* half16 (sym+add-.) */ +#define R_PPC_REL16_LO 250 /* half16 (sym+add-.)@l */ +#define R_PPC_REL16_HI 251 /* half16 (sym+add-.)@h */ +#define R_PPC_REL16_HA 252 /* half16 (sym+add-.)@ha */ + +/* This is a phony reloc to handle any old fashioned TOC16 references + that may still be in object files. */ +#define R_PPC_TOC16 255 + +/* PowerPC specific values for the Dyn d_tag field. */ +#define DT_PPC_GOT (DT_LOPROC + 0) +#define DT_PPC_OPT (DT_LOPROC + 1) +#define DT_PPC_NUM 2 + +/* PowerPC specific values for the DT_PPC_OPT Dyn entry. */ +#define PPC_OPT_TLS 1 + +/* PowerPC64 relocations defined by the ABIs */ +#define R_PPC64_NONE R_PPC_NONE +#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ +#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ +#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ +#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ +#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ +#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ +#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ +#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN +#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN +#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ +#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ +#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN +#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN +#define R_PPC64_GOT16 R_PPC_GOT16 +#define R_PPC64_GOT16_LO R_PPC_GOT16_LO +#define R_PPC64_GOT16_HI R_PPC_GOT16_HI +#define R_PPC64_GOT16_HA R_PPC_GOT16_HA + +#define R_PPC64_COPY R_PPC_COPY +#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT +#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT +#define R_PPC64_RELATIVE R_PPC_RELATIVE + +#define R_PPC64_UADDR32 R_PPC_UADDR32 +#define R_PPC64_UADDR16 R_PPC_UADDR16 +#define R_PPC64_REL32 R_PPC_REL32 +#define R_PPC64_PLT32 R_PPC_PLT32 +#define R_PPC64_PLTREL32 R_PPC_PLTREL32 +#define R_PPC64_PLT16_LO R_PPC_PLT16_LO +#define R_PPC64_PLT16_HI R_PPC_PLT16_HI +#define R_PPC64_PLT16_HA R_PPC_PLT16_HA + +#define R_PPC64_SECTOFF R_PPC_SECTOFF +#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO +#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI +#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA +#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ +#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ +#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ +#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ +#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ +#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ +#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ +#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ +#define R_PPC64_PLT64 45 /* doubleword64 L + A */ +#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ +#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ +#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ +#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ +#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ +#define R_PPC64_TOC 51 /* doubleword64 .TOC */ +#define R_PPC64_PLTGOT16 52 /* half16* M + A */ +#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ +#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ +#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ + +#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ +#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ +#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ +#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ +#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ +#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ +#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ +#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ +#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ +#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ +#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ + +/* PowerPC64 relocations defined for the TLS access ABI. */ +#define R_PPC64_TLS 67 /* none (sym+add)@tls */ +#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ +#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ +#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ +#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ +#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ +#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ +#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ +#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ +#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ +#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ +#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ +#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ +#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ +#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ +#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ +#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ +#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ +#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ +#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ +#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ +#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ +#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ +#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ +#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ +#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ +#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ +#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ +#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ +#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ +#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ +#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ +#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ +#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ +#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ +#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ +#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ +#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ +#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ +#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ +#define R_PPC64_TLSGD 107 /* none (sym+add)@tlsgd */ +#define R_PPC64_TLSLD 108 /* none (sym+add)@tlsld */ +#define R_PPC64_TOCSAVE 109 /* none */ + +/* Added when HA and HI relocs were changed to report overflows. */ +#define R_PPC64_ADDR16_HIGH 110 +#define R_PPC64_ADDR16_HIGHA 111 +#define R_PPC64_TPREL16_HIGH 112 +#define R_PPC64_TPREL16_HIGHA 113 +#define R_PPC64_DTPREL16_HIGH 114 +#define R_PPC64_DTPREL16_HIGHA 115 + +/* GNU extension to support local ifunc. */ +#define R_PPC64_JMP_IREL 247 +#define R_PPC64_IRELATIVE 248 +#define R_PPC64_REL16 249 /* half16 (sym+add-.) */ +#define R_PPC64_REL16_LO 250 /* half16 (sym+add-.)@l */ +#define R_PPC64_REL16_HI 251 /* half16 (sym+add-.)@h */ +#define R_PPC64_REL16_HA 252 /* half16 (sym+add-.)@ha */ + +/* e_flags bits specifying ABI. + 1 for original function descriptor using ABI, + 2 for revised ABI without function descriptors, + 0 for unspecified or not using any features affected by the differences. */ +#define EF_PPC64_ABI 3 + +/* PowerPC64 specific values for the Dyn d_tag field. */ +#define DT_PPC64_GLINK (DT_LOPROC + 0) +#define DT_PPC64_OPD (DT_LOPROC + 1) +#define DT_PPC64_OPDSZ (DT_LOPROC + 2) +#define DT_PPC64_OPT (DT_LOPROC + 3) +#define DT_PPC64_NUM 4 + +/* PowerPC64 specific values for the DT_PPC64_OPT Dyn entry. */ +#define PPC64_OPT_TLS 1 +#define PPC64_OPT_MULTI_TOC 2 + +/* PowerPC64 specific values for the Elf64_Sym st_other field. */ +#define STO_PPC64_LOCAL_BIT 5 +#define STO_PPC64_LOCAL_MASK (7 << STO_PPC64_LOCAL_BIT) +#define PPC64_LOCAL_ENTRY_OFFSET(other) \ + (((1 << (((other) & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT)) >> 2) << 2) + + +/* ARM specific declarations */ + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x01 +#define EF_ARM_HASENTRY 0x02 +#define EF_ARM_INTERWORK 0x04 +#define EF_ARM_APCS_26 0x08 +#define EF_ARM_APCS_FLOAT 0x10 +#define EF_ARM_PIC 0x20 +#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ +#define EF_ARM_NEW_ABI 0x80 +#define EF_ARM_OLD_ABI 0x100 +#define EF_ARM_SOFT_FLOAT 0x200 +#define EF_ARM_VFP_FLOAT 0x400 +#define EF_ARM_MAVERICK_FLOAT 0x800 + +#define EF_ARM_ABI_FLOAT_SOFT 0x200 /* NB conflicts with EF_ARM_SOFT_FLOAT */ +#define EF_ARM_ABI_FLOAT_HARD 0x400 /* NB conflicts with EF_ARM_VFP_FLOAT */ + + +/* Other constants defined in the ARM ELF spec. version B-01. */ +/* NB. These conflict with values defined above. */ +#define EF_ARM_SYMSARESORTED 0x04 +#define EF_ARM_DYNSYMSUSESEGIDX 0x08 +#define EF_ARM_MAPSYMSFIRST 0x10 +#define EF_ARM_EABIMASK 0XFF000000 + +/* Constants defined in AAELF. */ +#define EF_ARM_BE8 0x00800000 +#define EF_ARM_LE8 0x00400000 + +#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) +#define EF_ARM_EABI_UNKNOWN 0x00000000 +#define EF_ARM_EABI_VER1 0x01000000 +#define EF_ARM_EABI_VER2 0x02000000 +#define EF_ARM_EABI_VER3 0x03000000 +#define EF_ARM_EABI_VER4 0x04000000 +#define EF_ARM_EABI_VER5 0x05000000 + +/* Additional symbol types for Thumb. */ +#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ +#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ + +/* ARM-specific values for sh_flags */ +#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ +#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined + in the input to a link step. */ + +/* ARM-specific program header flags */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location + addressed by the static base. */ +#define PF_ARM_PI 0x20000000 /* Position-independent segment. */ +#define PF_ARM_ABS 0x40000000 /* Absolute segment. */ + +/* Processor specific values for the Phdr p_type field. */ +#define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */ + +/* Processor specific values for the Shdr sh_type field. */ +#define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */ +#define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */ +#define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */ + + +/* AArch64 relocs. */ + +#define R_AARCH64_NONE 0 /* No relocation. */ + +/* ILP32 AArch64 relocs. */ +#define R_AARCH64_P32_ABS32 1 /* Direct 32 bit. */ +#define R_AARCH64_P32_COPY 180 /* Copy symbol at runtime. */ +#define R_AARCH64_P32_GLOB_DAT 181 /* Create GOT entry. */ +#define R_AARCH64_P32_JUMP_SLOT 182 /* Create PLT entry. */ +#define R_AARCH64_P32_RELATIVE 183 /* Adjust by program base. */ +#define R_AARCH64_P32_TLS_DTPMOD 184 /* Module number, 32 bit. */ +#define R_AARCH64_P32_TLS_DTPREL 185 /* Module-relative offset, 32 bit. */ +#define R_AARCH64_P32_TLS_TPREL 186 /* TP-relative offset, 32 bit. */ +#define R_AARCH64_P32_TLSDESC 187 /* TLS Descriptor. */ +#define R_AARCH64_P32_IRELATIVE 188 /* STT_GNU_IFUNC relocation. */ + +/* LP64 AArch64 relocs. */ +#define R_AARCH64_ABS64 257 /* Direct 64 bit. */ +#define R_AARCH64_ABS32 258 /* Direct 32 bit. */ +#define R_AARCH64_ABS16 259 /* Direct 16-bit. */ +#define R_AARCH64_PREL64 260 /* PC-relative 64-bit. */ +#define R_AARCH64_PREL32 261 /* PC-relative 32-bit. */ +#define R_AARCH64_PREL16 262 /* PC-relative 16-bit. */ +#define R_AARCH64_MOVW_UABS_G0 263 /* Dir. MOVZ imm. from bits 15:0. */ +#define R_AARCH64_MOVW_UABS_G0_NC 264 /* Likewise for MOVK; no check. */ +#define R_AARCH64_MOVW_UABS_G1 265 /* Dir. MOVZ imm. from bits 31:16. */ +#define R_AARCH64_MOVW_UABS_G1_NC 266 /* Likewise for MOVK; no check. */ +#define R_AARCH64_MOVW_UABS_G2 267 /* Dir. MOVZ imm. from bits 47:32. */ +#define R_AARCH64_MOVW_UABS_G2_NC 268 /* Likewise for MOVK; no check. */ +#define R_AARCH64_MOVW_UABS_G3 269 /* Dir. MOV{K,Z} imm. from 63:48. */ +#define R_AARCH64_MOVW_SABS_G0 270 /* Dir. MOV{N,Z} imm. from 15:0. */ +#define R_AARCH64_MOVW_SABS_G1 271 /* Dir. MOV{N,Z} imm. from 31:16. */ +#define R_AARCH64_MOVW_SABS_G2 272 /* Dir. MOV{N,Z} imm. from 47:32. */ +#define R_AARCH64_LD_PREL_LO19 273 /* PC-rel. LD imm. from bits 20:2. */ +#define R_AARCH64_ADR_PREL_LO21 274 /* PC-rel. ADR imm. from bits 20:0. */ +#define R_AARCH64_ADR_PREL_PG_HI21 275 /* Page-rel. ADRP imm. from 32:12. */ +#define R_AARCH64_ADR_PREL_PG_HI21_NC 276 /* Likewise; no overflow check. */ +#define R_AARCH64_ADD_ABS_LO12_NC 277 /* Dir. ADD imm. from bits 11:0. */ +#define R_AARCH64_LDST8_ABS_LO12_NC 278 /* Likewise for LD/ST; no check. */ +#define R_AARCH64_TSTBR14 279 /* PC-rel. TBZ/TBNZ imm. from 15:2. */ +#define R_AARCH64_CONDBR19 280 /* PC-rel. cond. br. imm. from 20:2. */ +#define R_AARCH64_JUMP26 282 /* PC-rel. B imm. from bits 27:2. */ +#define R_AARCH64_CALL26 283 /* Likewise for CALL. */ +#define R_AARCH64_LDST16_ABS_LO12_NC 284 /* Dir. ADD imm. from bits 11:1. */ +#define R_AARCH64_LDST32_ABS_LO12_NC 285 /* Likewise for bits 11:2. */ +#define R_AARCH64_LDST64_ABS_LO12_NC 286 /* Likewise for bits 11:3. */ +#define R_AARCH64_MOVW_PREL_G0 287 /* PC-rel. MOV{N,Z} imm. from 15:0. */ +#define R_AARCH64_MOVW_PREL_G0_NC 288 /* Likewise for MOVK; no check. */ +#define R_AARCH64_MOVW_PREL_G1 289 /* PC-rel. MOV{N,Z} imm. from 31:16. */ +#define R_AARCH64_MOVW_PREL_G1_NC 290 /* Likewise for MOVK; no check. */ +#define R_AARCH64_MOVW_PREL_G2 291 /* PC-rel. MOV{N,Z} imm. from 47:32. */ +#define R_AARCH64_MOVW_PREL_G2_NC 292 /* Likewise for MOVK; no check. */ +#define R_AARCH64_MOVW_PREL_G3 293 /* PC-rel. MOV{N,Z} imm. from 63:48. */ +#define R_AARCH64_LDST128_ABS_LO12_NC 299 /* Dir. ADD imm. from bits 11:4. */ +#define R_AARCH64_MOVW_GOTOFF_G0 300 /* GOT-rel. off. MOV{N,Z} imm. 15:0. */ +#define R_AARCH64_MOVW_GOTOFF_G0_NC 301 /* Likewise for MOVK; no check. */ +#define R_AARCH64_MOVW_GOTOFF_G1 302 /* GOT-rel. o. MOV{N,Z} imm. 31:16. */ +#define R_AARCH64_MOVW_GOTOFF_G1_NC 303 /* Likewise for MOVK; no check. */ +#define R_AARCH64_MOVW_GOTOFF_G2 304 /* GOT-rel. o. MOV{N,Z} imm. 47:32. */ +#define R_AARCH64_MOVW_GOTOFF_G2_NC 305 /* Likewise for MOVK; no check. */ +#define R_AARCH64_MOVW_GOTOFF_G3 306 /* GOT-rel. o. MOV{N,Z} imm. 63:48. */ +#define R_AARCH64_GOTREL64 307 /* GOT-relative 64-bit. */ +#define R_AARCH64_GOTREL32 308 /* GOT-relative 32-bit. */ +#define R_AARCH64_GOT_LD_PREL19 309 /* PC-rel. GOT off. load imm. 20:2. */ +#define R_AARCH64_LD64_GOTOFF_LO15 310 /* GOT-rel. off. LD/ST imm. 14:3. */ +#define R_AARCH64_ADR_GOT_PAGE 311 /* P-page-rel. GOT off. ADRP 32:12. */ +#define R_AARCH64_LD64_GOT_LO12_NC 312 /* Dir. GOT off. LD/ST imm. 11:3. */ +#define R_AARCH64_LD64_GOTPAGE_LO15 313 /* GOT-page-rel. GOT off. LD/ST 14:3 */ +#define R_AARCH64_TLSGD_ADR_PREL21 512 /* PC-relative ADR imm. 20:0. */ +#define R_AARCH64_TLSGD_ADR_PAGE21 513 /* page-rel. ADRP imm. 32:12. */ +#define R_AARCH64_TLSGD_ADD_LO12_NC 514 /* direct ADD imm. from 11:0. */ +#define R_AARCH64_TLSGD_MOVW_G1 515 /* GOT-rel. MOV{N,Z} 31:16. */ +#define R_AARCH64_TLSGD_MOVW_G0_NC 516 /* GOT-rel. MOVK imm. 15:0. */ +#define R_AARCH64_TLSLD_ADR_PREL21 517 /* Like 512; local dynamic model. */ +#define R_AARCH64_TLSLD_ADR_PAGE21 518 /* Like 513; local dynamic model. */ +#define R_AARCH64_TLSLD_ADD_LO12_NC 519 /* Like 514; local dynamic model. */ +#define R_AARCH64_TLSLD_MOVW_G1 520 /* Like 515; local dynamic model. */ +#define R_AARCH64_TLSLD_MOVW_G0_NC 521 /* Like 516; local dynamic model. */ +#define R_AARCH64_TLSLD_LD_PREL19 522 /* TLS PC-rel. load imm. 20:2. */ +#define R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 /* TLS DTP-rel. MOV{N,Z} 47:32. */ +#define R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 /* TLS DTP-rel. MOV{N,Z} 31:16. */ +#define R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 /* Likewise; MOVK; no check. */ +#define R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 /* TLS DTP-rel. MOV{N,Z} 15:0. */ +#define R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 527 /* Likewise; MOVK; no check. */ +#define R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 /* DTP-rel. ADD imm. from 23:12. */ +#define R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 /* DTP-rel. ADD imm. from 11:0. */ +#define R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 /* Likewise; no ovfl. check. */ +#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 /* DTP-rel. LD/ST imm. 11:0. */ +#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 /* Likewise; no check. */ +#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 /* DTP-rel. LD/ST imm. 11:1. */ +#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 /* Likewise; no check. */ +#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 /* DTP-rel. LD/ST imm. 11:2. */ +#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 /* Likewise; no check. */ +#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 /* DTP-rel. LD/ST imm. 11:3. */ +#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 /* Likewise; no check. */ +#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 /* GOT-rel. MOV{N,Z} 31:16. */ +#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 /* GOT-rel. MOVK 15:0. */ +#define R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 /* Page-rel. ADRP 32:12. */ +#define R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 /* Direct LD off. 11:3. */ +#define R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 /* PC-rel. load imm. 20:2. */ +#define R_AARCH64_TLSLE_MOVW_TPREL_G2 544 /* TLS TP-rel. MOV{N,Z} 47:32. */ +#define R_AARCH64_TLSLE_MOVW_TPREL_G1 545 /* TLS TP-rel. MOV{N,Z} 31:16. */ +#define R_AARCH64_TLSLE_MOVW_TPREL_G1_NC 546 /* Likewise; MOVK; no check. */ +#define R_AARCH64_TLSLE_MOVW_TPREL_G0 547 /* TLS TP-rel. MOV{N,Z} 15:0. */ +#define R_AARCH64_TLSLE_MOVW_TPREL_G0_NC 548 /* Likewise; MOVK; no check. */ +#define R_AARCH64_TLSLE_ADD_TPREL_HI12 549 /* TP-rel. ADD imm. 23:12. */ +#define R_AARCH64_TLSLE_ADD_TPREL_LO12 550 /* TP-rel. ADD imm. 11:0. */ +#define R_AARCH64_TLSLE_ADD_TPREL_LO12_NC 551 /* Likewise; no ovfl. check. */ +#define R_AARCH64_TLSLE_LDST8_TPREL_LO12 552 /* TP-rel. LD/ST off. 11:0. */ +#define R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 553 /* Likewise; no ovfl. check. */ +#define R_AARCH64_TLSLE_LDST16_TPREL_LO12 554 /* TP-rel. LD/ST off. 11:1. */ +#define R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 555 /* Likewise; no check. */ +#define R_AARCH64_TLSLE_LDST32_TPREL_LO12 556 /* TP-rel. LD/ST off. 11:2. */ +#define R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 557 /* Likewise; no check. */ +#define R_AARCH64_TLSLE_LDST64_TPREL_LO12 558 /* TP-rel. LD/ST off. 11:3. */ +#define R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 559 /* Likewise; no check. */ +#define R_AARCH64_TLSDESC_LD_PREL19 560 /* PC-rel. load immediate 20:2. */ +#define R_AARCH64_TLSDESC_ADR_PREL21 561 /* PC-rel. ADR immediate 20:0. */ +#define R_AARCH64_TLSDESC_ADR_PAGE21 562 /* Page-rel. ADRP imm. 32:12. */ +#define R_AARCH64_TLSDESC_LD64_LO12 563 /* Direct LD off. from 11:3. */ +#define R_AARCH64_TLSDESC_ADD_LO12 564 /* Direct ADD imm. from 11:0. */ +#define R_AARCH64_TLSDESC_OFF_G1 565 /* GOT-rel. MOV{N,Z} imm. 31:16. */ +#define R_AARCH64_TLSDESC_OFF_G0_NC 566 /* GOT-rel. MOVK imm. 15:0; no ck. */ +#define R_AARCH64_TLSDESC_LDR 567 /* Relax LDR. */ +#define R_AARCH64_TLSDESC_ADD 568 /* Relax ADD. */ +#define R_AARCH64_TLSDESC_CALL 569 /* Relax BLR. */ +#define R_AARCH64_TLSLE_LDST128_TPREL_LO12 570 /* TP-rel. LD/ST off. 11:4. */ +#define R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC 571 /* Likewise; no check. */ +#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12 572 /* DTP-rel. LD/ST imm. 11:4. */ +#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC 573 /* Likewise; no check. */ +#define R_AARCH64_COPY 1024 /* Copy symbol at runtime. */ +#define R_AARCH64_GLOB_DAT 1025 /* Create GOT entry. */ +#define R_AARCH64_JUMP_SLOT 1026 /* Create PLT entry. */ +#define R_AARCH64_RELATIVE 1027 /* Adjust by program base. */ +#define R_AARCH64_TLS_DTPMOD 1028 /* Module number, 64 bit. */ +#define R_AARCH64_TLS_DTPREL 1029 /* Module-relative offset, 64 bit. */ +#define R_AARCH64_TLS_TPREL 1030 /* TP-relative offset, 64 bit. */ +#define R_AARCH64_TLSDESC 1031 /* TLS Descriptor. */ +#define R_AARCH64_IRELATIVE 1032 /* STT_GNU_IFUNC relocation. */ + +/* ARM relocs. */ + +#define R_ARM_NONE 0 /* No reloc */ +#define R_ARM_PC24 1 /* Deprecated PC relative 26 + bit branch. */ +#define R_ARM_ABS32 2 /* Direct 32 bit */ +#define R_ARM_REL32 3 /* PC relative 32 bit */ +#define R_ARM_PC13 4 +#define R_ARM_ABS16 5 /* Direct 16 bit */ +#define R_ARM_ABS12 6 /* Direct 12 bit */ +#define R_ARM_THM_ABS5 7 /* Direct & 0x7C (LDR, STR). */ +#define R_ARM_ABS8 8 /* Direct 8 bit */ +#define R_ARM_SBREL32 9 +#define R_ARM_THM_PC22 10 /* PC relative 24 bit (Thumb32 BL). */ +#define R_ARM_THM_PC8 11 /* PC relative & 0x3FC + (Thumb16 LDR, ADD, ADR). */ +#define R_ARM_AMP_VCALL9 12 +#define R_ARM_SWI24 13 /* Obsolete static relocation. */ +#define R_ARM_TLS_DESC 13 /* Dynamic relocation. */ +#define R_ARM_THM_SWI8 14 /* Reserved. */ +#define R_ARM_XPC25 15 /* Reserved. */ +#define R_ARM_THM_XPC22 16 /* Reserved. */ +#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ +#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ +#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ +#define R_ARM_COPY 20 /* Copy symbol at runtime */ +#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ +#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ +#define R_ARM_RELATIVE 23 /* Adjust by program base */ +#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ +#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ +#define R_ARM_GOT32 26 /* 32 bit GOT entry */ +#define R_ARM_PLT32 27 /* Deprecated, 32 bit PLT address. */ +#define R_ARM_CALL 28 /* PC relative 24 bit (BL, BLX). */ +#define R_ARM_JUMP24 29 /* PC relative 24 bit + (B, BL). */ +#define R_ARM_THM_JUMP24 30 /* PC relative 24 bit (Thumb32 B.W). */ +#define R_ARM_BASE_ABS 31 /* Adjust by program base. */ +#define R_ARM_ALU_PCREL_7_0 32 /* Obsolete. */ +#define R_ARM_ALU_PCREL_15_8 33 /* Obsolete. */ +#define R_ARM_ALU_PCREL_23_15 34 /* Obsolete. */ +#define R_ARM_LDR_SBREL_11_0 35 /* Deprecated, prog. base relative. */ +#define R_ARM_ALU_SBREL_19_12 36 /* Deprecated, prog. base relative. */ +#define R_ARM_ALU_SBREL_27_20 37 /* Deprecated, prog. base relative. */ +#define R_ARM_TARGET1 38 +#define R_ARM_SBREL31 39 /* Program base relative. */ +#define R_ARM_V4BX 40 +#define R_ARM_TARGET2 41 +#define R_ARM_PREL31 42 /* 32 bit PC relative. */ +#define R_ARM_MOVW_ABS_NC 43 /* Direct 16-bit (MOVW). */ +#define R_ARM_MOVT_ABS 44 /* Direct high 16-bit (MOVT). */ +#define R_ARM_MOVW_PREL_NC 45 /* PC relative 16-bit (MOVW). */ +#define R_ARM_MOVT_PREL 46 /* PC relative (MOVT). */ +#define R_ARM_THM_MOVW_ABS_NC 47 /* Direct 16 bit (Thumb32 MOVW). */ +#define R_ARM_THM_MOVT_ABS 48 /* Direct high 16 bit + (Thumb32 MOVT). */ +#define R_ARM_THM_MOVW_PREL_NC 49 /* PC relative 16 bit + (Thumb32 MOVW). */ +#define R_ARM_THM_MOVT_PREL 50 /* PC relative high 16 bit + (Thumb32 MOVT). */ +#define R_ARM_THM_JUMP19 51 /* PC relative 20 bit + (Thumb32 B.W). */ +#define R_ARM_THM_JUMP6 52 /* PC relative X & 0x7E + (Thumb16 CBZ, CBNZ). */ +#define R_ARM_THM_ALU_PREL_11_0 53 /* PC relative 12 bit + (Thumb32 ADR.W). */ +#define R_ARM_THM_PC12 54 /* PC relative 12 bit + (Thumb32 LDR{D,SB,H,SH}). */ +#define R_ARM_ABS32_NOI 55 /* Direct 32-bit. */ +#define R_ARM_REL32_NOI 56 /* PC relative 32-bit. */ +#define R_ARM_ALU_PC_G0_NC 57 /* PC relative (ADD, SUB). */ +#define R_ARM_ALU_PC_G0 58 /* PC relative (ADD, SUB). */ +#define R_ARM_ALU_PC_G1_NC 59 /* PC relative (ADD, SUB). */ +#define R_ARM_ALU_PC_G1 60 /* PC relative (ADD, SUB). */ +#define R_ARM_ALU_PC_G2 61 /* PC relative (ADD, SUB). */ +#define R_ARM_LDR_PC_G1 62 /* PC relative (LDR,STR,LDRB,STRB). */ +#define R_ARM_LDR_PC_G2 63 /* PC relative (LDR,STR,LDRB,STRB). */ +#define R_ARM_LDRS_PC_G0 64 /* PC relative (STR{D,H}, + LDR{D,SB,H,SH}). */ +#define R_ARM_LDRS_PC_G1 65 /* PC relative (STR{D,H}, + LDR{D,SB,H,SH}). */ +#define R_ARM_LDRS_PC_G2 66 /* PC relative (STR{D,H}, + LDR{D,SB,H,SH}). */ +#define R_ARM_LDC_PC_G0 67 /* PC relative (LDC, STC). */ +#define R_ARM_LDC_PC_G1 68 /* PC relative (LDC, STC). */ +#define R_ARM_LDC_PC_G2 69 /* PC relative (LDC, STC). */ +#define R_ARM_ALU_SB_G0_NC 70 /* Program base relative (ADD,SUB). */ +#define R_ARM_ALU_SB_G0 71 /* Program base relative (ADD,SUB). */ +#define R_ARM_ALU_SB_G1_NC 72 /* Program base relative (ADD,SUB). */ +#define R_ARM_ALU_SB_G1 73 /* Program base relative (ADD,SUB). */ +#define R_ARM_ALU_SB_G2 74 /* Program base relative (ADD,SUB). */ +#define R_ARM_LDR_SB_G0 75 /* Program base relative (LDR, + STR, LDRB, STRB). */ +#define R_ARM_LDR_SB_G1 76 /* Program base relative + (LDR, STR, LDRB, STRB). */ +#define R_ARM_LDR_SB_G2 77 /* Program base relative + (LDR, STR, LDRB, STRB). */ +#define R_ARM_LDRS_SB_G0 78 /* Program base relative + (LDR, STR, LDRB, STRB). */ +#define R_ARM_LDRS_SB_G1 79 /* Program base relative + (LDR, STR, LDRB, STRB). */ +#define R_ARM_LDRS_SB_G2 80 /* Program base relative + (LDR, STR, LDRB, STRB). */ +#define R_ARM_LDC_SB_G0 81 /* Program base relative (LDC,STC). */ +#define R_ARM_LDC_SB_G1 82 /* Program base relative (LDC,STC). */ +#define R_ARM_LDC_SB_G2 83 /* Program base relative (LDC,STC). */ +#define R_ARM_MOVW_BREL_NC 84 /* Program base relative 16 + bit (MOVW). */ +#define R_ARM_MOVT_BREL 85 /* Program base relative high + 16 bit (MOVT). */ +#define R_ARM_MOVW_BREL 86 /* Program base relative 16 + bit (MOVW). */ +#define R_ARM_THM_MOVW_BREL_NC 87 /* Program base relative 16 + bit (Thumb32 MOVW). */ +#define R_ARM_THM_MOVT_BREL 88 /* Program base relative high + 16 bit (Thumb32 MOVT). */ +#define R_ARM_THM_MOVW_BREL 89 /* Program base relative 16 + bit (Thumb32 MOVW). */ +#define R_ARM_TLS_GOTDESC 90 +#define R_ARM_TLS_CALL 91 +#define R_ARM_TLS_DESCSEQ 92 /* TLS relaxation. */ +#define R_ARM_THM_TLS_CALL 93 +#define R_ARM_PLT32_ABS 94 +#define R_ARM_GOT_ABS 95 /* GOT entry. */ +#define R_ARM_GOT_PREL 96 /* PC relative GOT entry. */ +#define R_ARM_GOT_BREL12 97 /* GOT entry relative to GOT + origin (LDR). */ +#define R_ARM_GOTOFF12 98 /* 12 bit, GOT entry relative + to GOT origin (LDR, STR). */ +#define R_ARM_GOTRELAX 99 +#define R_ARM_GNU_VTENTRY 100 +#define R_ARM_GNU_VTINHERIT 101 +#define R_ARM_THM_PC11 102 /* PC relative & 0xFFE (Thumb16 B). */ +#define R_ARM_THM_PC9 103 /* PC relative & 0x1FE + (Thumb16 B/B). */ +#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic + thread local data */ +#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic + thread local data */ +#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS + block */ +#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of + static TLS block offset */ +#define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static + TLS block */ +#define R_ARM_TLS_LDO12 109 /* 12 bit relative to TLS + block (LDR, STR). */ +#define R_ARM_TLS_LE12 110 /* 12 bit relative to static + TLS block (LDR, STR). */ +#define R_ARM_TLS_IE12GP 111 /* 12 bit GOT entry relative + to GOT origin (LDR). */ +#define R_ARM_ME_TOO 128 /* Obsolete. */ +#define R_ARM_THM_TLS_DESCSEQ 129 +#define R_ARM_THM_TLS_DESCSEQ16 129 +#define R_ARM_THM_TLS_DESCSEQ32 130 +#define R_ARM_THM_GOT_BREL12 131 /* GOT entry relative to GOT + origin, 12 bit (Thumb32 LDR). */ +#define R_ARM_IRELATIVE 160 +#define R_ARM_RXPC25 249 +#define R_ARM_RSBREL32 250 +#define R_ARM_THM_RPC22 251 +#define R_ARM_RREL32 252 +#define R_ARM_RABS22 253 +#define R_ARM_RPC24 254 +#define R_ARM_RBASE 255 +/* Keep this the last entry. */ +#define R_ARM_NUM 256 + +/* IA-64 specific declarations. */ + +/* Processor specific flags for the Ehdr e_flags field. */ +#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ +#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ +#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ + +/* Processor specific values for the Phdr p_type field. */ +#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ +#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ +#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) +#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) +#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) + +/* Processor specific flags for the Phdr p_flags field. */ +#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ + +/* Processor specific values for the Shdr sh_type field. */ +#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ +#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ + +/* Processor specific flags for the Shdr sh_flags field. */ +#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ +#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ + +/* Processor specific values for the Dyn d_tag field. */ +#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) +#define DT_IA_64_NUM 1 + +/* IA-64 relocations. */ +#define R_IA64_NONE 0x00 /* none */ +#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ +#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ +#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ +#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ +#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ +#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ +#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ +#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ +#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ +#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ +#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ +#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ +#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ +#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ +#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ +#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ +#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ +#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ +#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ +#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ +#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ +#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ +#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ +#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ +#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ +#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ +#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ +#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ +#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ +#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ +#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ +#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ +#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ +#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ +#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ +#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ +#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ +#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ +#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ +#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ +#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ +#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ +#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ +#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ +#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ +#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ +#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ +#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ +#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ +#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ +#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ +#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ +#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ +#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ +#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ +#define R_IA64_COPY 0x84 /* copy relocation */ +#define R_IA64_SUB 0x85 /* Addend and symbol difference */ +#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ +#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ +#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ +#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ +#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ +#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ +#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ +#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ +#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ +#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ +#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ +#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ +#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ +#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ +#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ +#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ +#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ + +/* SH specific declarations */ + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_SH_MACH_MASK 0x1f +#define EF_SH_UNKNOWN 0x0 +#define EF_SH1 0x1 +#define EF_SH2 0x2 +#define EF_SH3 0x3 +#define EF_SH_DSP 0x4 +#define EF_SH3_DSP 0x5 +#define EF_SH4AL_DSP 0x6 +#define EF_SH3E 0x8 +#define EF_SH4 0x9 +#define EF_SH2E 0xb +#define EF_SH4A 0xc +#define EF_SH2A 0xd +#define EF_SH4_NOFPU 0x10 +#define EF_SH4A_NOFPU 0x11 +#define EF_SH4_NOMMU_NOFPU 0x12 +#define EF_SH2A_NOFPU 0x13 +#define EF_SH3_NOMMU 0x14 +#define EF_SH2A_SH4_NOFPU 0x15 +#define EF_SH2A_SH3_NOFPU 0x16 +#define EF_SH2A_SH4 0x17 +#define EF_SH2A_SH3E 0x18 + +/* SH relocs. */ +#define R_SH_NONE 0 +#define R_SH_DIR32 1 +#define R_SH_REL32 2 +#define R_SH_DIR8WPN 3 +#define R_SH_IND12W 4 +#define R_SH_DIR8WPL 5 +#define R_SH_DIR8WPZ 6 +#define R_SH_DIR8BP 7 +#define R_SH_DIR8W 8 +#define R_SH_DIR8L 9 +#define R_SH_SWITCH16 25 +#define R_SH_SWITCH32 26 +#define R_SH_USES 27 +#define R_SH_COUNT 28 +#define R_SH_ALIGN 29 +#define R_SH_CODE 30 +#define R_SH_DATA 31 +#define R_SH_LABEL 32 +#define R_SH_SWITCH8 33 +#define R_SH_GNU_VTINHERIT 34 +#define R_SH_GNU_VTENTRY 35 +#define R_SH_TLS_GD_32 144 +#define R_SH_TLS_LD_32 145 +#define R_SH_TLS_LDO_32 146 +#define R_SH_TLS_IE_32 147 +#define R_SH_TLS_LE_32 148 +#define R_SH_TLS_DTPMOD32 149 +#define R_SH_TLS_DTPOFF32 150 +#define R_SH_TLS_TPOFF32 151 +#define R_SH_GOT32 160 +#define R_SH_PLT32 161 +#define R_SH_COPY 162 +#define R_SH_GLOB_DAT 163 +#define R_SH_JMP_SLOT 164 +#define R_SH_RELATIVE 165 +#define R_SH_GOTOFF 166 +#define R_SH_GOTPC 167 +/* Keep this the last entry. */ +#define R_SH_NUM 256 + +/* S/390 specific definitions. */ + +/* Valid values for the e_flags field. */ + +#define EF_S390_HIGH_GPRS 0x00000001 /* High GPRs kernel facility needed. */ + +/* Additional s390 relocs */ + +#define R_390_NONE 0 /* No reloc. */ +#define R_390_8 1 /* Direct 8 bit. */ +#define R_390_12 2 /* Direct 12 bit. */ +#define R_390_16 3 /* Direct 16 bit. */ +#define R_390_32 4 /* Direct 32 bit. */ +#define R_390_PC32 5 /* PC relative 32 bit. */ +#define R_390_GOT12 6 /* 12 bit GOT offset. */ +#define R_390_GOT32 7 /* 32 bit GOT offset. */ +#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ +#define R_390_COPY 9 /* Copy symbol at runtime. */ +#define R_390_GLOB_DAT 10 /* Create GOT entry. */ +#define R_390_JMP_SLOT 11 /* Create PLT entry. */ +#define R_390_RELATIVE 12 /* Adjust by program base. */ +#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ +#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ +#define R_390_GOT16 15 /* 16 bit GOT offset. */ +#define R_390_PC16 16 /* PC relative 16 bit. */ +#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ +#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ +#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ +#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ +#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ +#define R_390_64 22 /* Direct 64 bit. */ +#define R_390_PC64 23 /* PC relative 64 bit. */ +#define R_390_GOT64 24 /* 64 bit GOT offset. */ +#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ +#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ +#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ +#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ +#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ +#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ +#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ +#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ +#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ +#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ +#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ +#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ +#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ +#define R_390_TLS_GDCALL 38 /* Tag for function call in general + dynamic TLS code. */ +#define R_390_TLS_LDCALL 39 /* Tag for function call in local + dynamic TLS code. */ +#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic + thread local data. */ +#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic + thread local data. */ +#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS + block offset. */ +#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS + block offset. */ +#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS + block offset. */ +#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic + thread local data in LE code. */ +#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic + thread local data in LE code. */ +#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for + negated static TLS block offset. */ +#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for + negated static TLS block offset. */ +#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for + negated static TLS block offset. */ +#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to + static TLS block. */ +#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to + static TLS block. */ +#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS + block. */ +#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS + block. */ +#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ +#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ +#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS + block. */ +#define R_390_20 57 /* Direct 20 bit. */ +#define R_390_GOT20 58 /* 20 bit GOT offset. */ +#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */ +#define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS + block offset. */ +#define R_390_IRELATIVE 61 /* STT_GNU_IFUNC relocation. */ +/* Keep this the last entry. */ +#define R_390_NUM 62 + + +/* CRIS relocations. */ +#define R_CRIS_NONE 0 +#define R_CRIS_8 1 +#define R_CRIS_16 2 +#define R_CRIS_32 3 +#define R_CRIS_8_PCREL 4 +#define R_CRIS_16_PCREL 5 +#define R_CRIS_32_PCREL 6 +#define R_CRIS_GNU_VTINHERIT 7 +#define R_CRIS_GNU_VTENTRY 8 +#define R_CRIS_COPY 9 +#define R_CRIS_GLOB_DAT 10 +#define R_CRIS_JUMP_SLOT 11 +#define R_CRIS_RELATIVE 12 +#define R_CRIS_16_GOT 13 +#define R_CRIS_32_GOT 14 +#define R_CRIS_16_GOTPLT 15 +#define R_CRIS_32_GOTPLT 16 +#define R_CRIS_32_GOTREL 17 +#define R_CRIS_32_PLT_GOTREL 18 +#define R_CRIS_32_PLT_PCREL 19 + +#define R_CRIS_NUM 20 + + +/* AMD x86-64 relocations. */ +#define R_X86_64_NONE 0 /* No reloc */ +#define R_X86_64_64 1 /* Direct 64 bit */ +#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ +#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ +#define R_X86_64_PLT32 4 /* 32 bit PLT address */ +#define R_X86_64_COPY 5 /* Copy symbol at runtime */ +#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ +#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ +#define R_X86_64_RELATIVE 8 /* Adjust by program base */ +#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative + offset to GOT */ +#define R_X86_64_32 10 /* Direct 32 bit zero extended */ +#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ +#define R_X86_64_16 12 /* Direct 16 bit zero extended */ +#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ +#define R_X86_64_8 14 /* Direct 8 bit sign extended */ +#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ +#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ +#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ +#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ +#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset + to two GOT entries for GD symbol */ +#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset + to two GOT entries for LD symbol */ +#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ +#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset + to GOT entry for IE symbol */ +#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ +#define R_X86_64_PC64 24 /* PC relative 64 bit */ +#define R_X86_64_GOTOFF64 25 /* 64 bit offset to GOT */ +#define R_X86_64_GOTPC32 26 /* 32 bit signed pc relative + offset to GOT */ +#define R_X86_64_GOT64 27 /* 64-bit GOT entry offset */ +#define R_X86_64_GOTPCREL64 28 /* 64-bit PC relative offset + to GOT entry */ +#define R_X86_64_GOTPC64 29 /* 64-bit PC relative offset to GOT */ +#define R_X86_64_GOTPLT64 30 /* like GOT64, says PLT entry needed */ +#define R_X86_64_PLTOFF64 31 /* 64-bit GOT relative offset + to PLT entry */ +#define R_X86_64_SIZE32 32 /* Size of symbol plus 32-bit addend */ +#define R_X86_64_SIZE64 33 /* Size of symbol plus 64-bit addend */ +#define R_X86_64_GOTPC32_TLSDESC 34 /* GOT offset for TLS descriptor. */ +#define R_X86_64_TLSDESC_CALL 35 /* Marker for call through TLS + descriptor. */ +#define R_X86_64_TLSDESC 36 /* TLS descriptor. */ +#define R_X86_64_IRELATIVE 37 /* Adjust indirectly by program base */ +#define R_X86_64_RELATIVE64 38 /* 64-bit adjust by program base */ + +#define R_X86_64_NUM 39 + + +/* AM33 relocations. */ +#define R_MN10300_NONE 0 /* No reloc. */ +#define R_MN10300_32 1 /* Direct 32 bit. */ +#define R_MN10300_16 2 /* Direct 16 bit. */ +#define R_MN10300_8 3 /* Direct 8 bit. */ +#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ +#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ +#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ +#define R_MN10300_GNU_VTINHERIT 7 /* Ancient C++ vtable garbage... */ +#define R_MN10300_GNU_VTENTRY 8 /* ... collection annotation. */ +#define R_MN10300_24 9 /* Direct 24 bit. */ +#define R_MN10300_GOTPC32 10 /* 32-bit PCrel offset to GOT. */ +#define R_MN10300_GOTPC16 11 /* 16-bit PCrel offset to GOT. */ +#define R_MN10300_GOTOFF32 12 /* 32-bit offset from GOT. */ +#define R_MN10300_GOTOFF24 13 /* 24-bit offset from GOT. */ +#define R_MN10300_GOTOFF16 14 /* 16-bit offset from GOT. */ +#define R_MN10300_PLT32 15 /* 32-bit PCrel to PLT entry. */ +#define R_MN10300_PLT16 16 /* 16-bit PCrel to PLT entry. */ +#define R_MN10300_GOT32 17 /* 32-bit offset to GOT entry. */ +#define R_MN10300_GOT24 18 /* 24-bit offset to GOT entry. */ +#define R_MN10300_GOT16 19 /* 16-bit offset to GOT entry. */ +#define R_MN10300_COPY 20 /* Copy symbol at runtime. */ +#define R_MN10300_GLOB_DAT 21 /* Create GOT entry. */ +#define R_MN10300_JMP_SLOT 22 /* Create PLT entry. */ +#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ +#define R_MN10300_TLS_GD 24 /* 32-bit offset for global dynamic. */ +#define R_MN10300_TLS_LD 25 /* 32-bit offset for local dynamic. */ +#define R_MN10300_TLS_LDO 26 /* Module-relative offset. */ +#define R_MN10300_TLS_GOTIE 27 /* GOT offset for static TLS block + offset. */ +#define R_MN10300_TLS_IE 28 /* GOT address for static TLS block + offset. */ +#define R_MN10300_TLS_LE 29 /* Offset relative to static TLS + block. */ +#define R_MN10300_TLS_DTPMOD 30 /* ID of module containing symbol. */ +#define R_MN10300_TLS_DTPOFF 31 /* Offset in module TLS block. */ +#define R_MN10300_TLS_TPOFF 32 /* Offset in static TLS block. */ +#define R_MN10300_SYM_DIFF 33 /* Adjustment for next reloc as needed + by linker relaxation. */ +#define R_MN10300_ALIGN 34 /* Alignment requirement for linker + relaxation. */ +#define R_MN10300_NUM 35 + + +/* M32R relocs. */ +#define R_M32R_NONE 0 /* No reloc. */ +#define R_M32R_16 1 /* Direct 16 bit. */ +#define R_M32R_32 2 /* Direct 32 bit. */ +#define R_M32R_24 3 /* Direct 24 bit. */ +#define R_M32R_10_PCREL 4 /* PC relative 10 bit shifted. */ +#define R_M32R_18_PCREL 5 /* PC relative 18 bit shifted. */ +#define R_M32R_26_PCREL 6 /* PC relative 26 bit shifted. */ +#define R_M32R_HI16_ULO 7 /* High 16 bit with unsigned low. */ +#define R_M32R_HI16_SLO 8 /* High 16 bit with signed low. */ +#define R_M32R_LO16 9 /* Low 16 bit. */ +#define R_M32R_SDA16 10 /* 16 bit offset in SDA. */ +#define R_M32R_GNU_VTINHERIT 11 +#define R_M32R_GNU_VTENTRY 12 +/* M32R relocs use SHT_RELA. */ +#define R_M32R_16_RELA 33 /* Direct 16 bit. */ +#define R_M32R_32_RELA 34 /* Direct 32 bit. */ +#define R_M32R_24_RELA 35 /* Direct 24 bit. */ +#define R_M32R_10_PCREL_RELA 36 /* PC relative 10 bit shifted. */ +#define R_M32R_18_PCREL_RELA 37 /* PC relative 18 bit shifted. */ +#define R_M32R_26_PCREL_RELA 38 /* PC relative 26 bit shifted. */ +#define R_M32R_HI16_ULO_RELA 39 /* High 16 bit with unsigned low */ +#define R_M32R_HI16_SLO_RELA 40 /* High 16 bit with signed low */ +#define R_M32R_LO16_RELA 41 /* Low 16 bit */ +#define R_M32R_SDA16_RELA 42 /* 16 bit offset in SDA */ +#define R_M32R_RELA_GNU_VTINHERIT 43 +#define R_M32R_RELA_GNU_VTENTRY 44 +#define R_M32R_REL32 45 /* PC relative 32 bit. */ + +#define R_M32R_GOT24 48 /* 24 bit GOT entry */ +#define R_M32R_26_PLTREL 49 /* 26 bit PC relative to PLT shifted */ +#define R_M32R_COPY 50 /* Copy symbol at runtime */ +#define R_M32R_GLOB_DAT 51 /* Create GOT entry */ +#define R_M32R_JMP_SLOT 52 /* Create PLT entry */ +#define R_M32R_RELATIVE 53 /* Adjust by program base */ +#define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */ +#define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */ +#define R_M32R_GOT16_HI_ULO 56 /* High 16 bit GOT entry with unsigned + low */ +#define R_M32R_GOT16_HI_SLO 57 /* High 16 bit GOT entry with signed + low */ +#define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */ +#define R_M32R_GOTPC_HI_ULO 59 /* High 16 bit PC relative offset to + GOT with unsigned low */ +#define R_M32R_GOTPC_HI_SLO 60 /* High 16 bit PC relative offset to + GOT with signed low */ +#define R_M32R_GOTPC_LO 61 /* Low 16 bit PC relative offset to + GOT */ +#define R_M32R_GOTOFF_HI_ULO 62 /* High 16 bit offset to GOT + with unsigned low */ +#define R_M32R_GOTOFF_HI_SLO 63 /* High 16 bit offset to GOT + with signed low */ +#define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */ +#define R_M32R_NUM 256 /* Keep this the last entry. */ + +/* MicroBlaze relocations */ +#define R_MICROBLAZE_NONE 0 /* No reloc. */ +#define R_MICROBLAZE_32 1 /* Direct 32 bit. */ +#define R_MICROBLAZE_32_PCREL 2 /* PC relative 32 bit. */ +#define R_MICROBLAZE_64_PCREL 3 /* PC relative 64 bit. */ +#define R_MICROBLAZE_32_PCREL_LO 4 /* Low 16 bits of PCREL32. */ +#define R_MICROBLAZE_64 5 /* Direct 64 bit. */ +#define R_MICROBLAZE_32_LO 6 /* Low 16 bit. */ +#define R_MICROBLAZE_SRO32 7 /* Read-only small data area. */ +#define R_MICROBLAZE_SRW32 8 /* Read-write small data area. */ +#define R_MICROBLAZE_64_NONE 9 /* No reloc. */ +#define R_MICROBLAZE_32_SYM_OP_SYM 10 /* Symbol Op Symbol relocation. */ +#define R_MICROBLAZE_GNU_VTINHERIT 11 /* GNU C++ vtable hierarchy. */ +#define R_MICROBLAZE_GNU_VTENTRY 12 /* GNU C++ vtable member usage. */ +#define R_MICROBLAZE_GOTPC_64 13 /* PC-relative GOT offset. */ +#define R_MICROBLAZE_GOT_64 14 /* GOT entry offset. */ +#define R_MICROBLAZE_PLT_64 15 /* PLT offset (PC-relative). */ +#define R_MICROBLAZE_REL 16 /* Adjust by program base. */ +#define R_MICROBLAZE_JUMP_SLOT 17 /* Create PLT entry. */ +#define R_MICROBLAZE_GLOB_DAT 18 /* Create GOT entry. */ +#define R_MICROBLAZE_GOTOFF_64 19 /* 64 bit offset to GOT. */ +#define R_MICROBLAZE_GOTOFF_32 20 /* 32 bit offset to GOT. */ +#define R_MICROBLAZE_COPY 21 /* Runtime copy. */ +#define R_MICROBLAZE_TLS 22 /* TLS Reloc. */ +#define R_MICROBLAZE_TLSGD 23 /* TLS General Dynamic. */ +#define R_MICROBLAZE_TLSLD 24 /* TLS Local Dynamic. */ +#define R_MICROBLAZE_TLSDTPMOD32 25 /* TLS Module ID. */ +#define R_MICROBLAZE_TLSDTPREL32 26 /* TLS Offset Within TLS Block. */ +#define R_MICROBLAZE_TLSDTPREL64 27 /* TLS Offset Within TLS Block. */ +#define R_MICROBLAZE_TLSGOTTPREL32 28 /* TLS Offset From Thread Pointer. */ +#define R_MICROBLAZE_TLSTPREL32 29 /* TLS Offset From Thread Pointer. */ + +/* Legal values for d_tag (dynamic entry type). */ +#define DT_NIOS2_GP 0x70000002 /* Address of _gp. */ + +/* Nios II relocations. */ +#define R_NIOS2_NONE 0 /* No reloc. */ +#define R_NIOS2_S16 1 /* Direct signed 16 bit. */ +#define R_NIOS2_U16 2 /* Direct unsigned 16 bit. */ +#define R_NIOS2_PCREL16 3 /* PC relative 16 bit. */ +#define R_NIOS2_CALL26 4 /* Direct call. */ +#define R_NIOS2_IMM5 5 /* 5 bit constant expression. */ +#define R_NIOS2_CACHE_OPX 6 /* 5 bit expression, shift 22. */ +#define R_NIOS2_IMM6 7 /* 6 bit constant expression. */ +#define R_NIOS2_IMM8 8 /* 8 bit constant expression. */ +#define R_NIOS2_HI16 9 /* High 16 bit. */ +#define R_NIOS2_LO16 10 /* Low 16 bit. */ +#define R_NIOS2_HIADJ16 11 /* High 16 bit, adjusted. */ +#define R_NIOS2_BFD_RELOC_32 12 /* 32 bit symbol value + addend. */ +#define R_NIOS2_BFD_RELOC_16 13 /* 16 bit symbol value + addend. */ +#define R_NIOS2_BFD_RELOC_8 14 /* 8 bit symbol value + addend. */ +#define R_NIOS2_GPREL 15 /* 16 bit GP pointer offset. */ +#define R_NIOS2_GNU_VTINHERIT 16 /* GNU C++ vtable hierarchy. */ +#define R_NIOS2_GNU_VTENTRY 17 /* GNU C++ vtable member usage. */ +#define R_NIOS2_UJMP 18 /* Unconditional branch. */ +#define R_NIOS2_CJMP 19 /* Conditional branch. */ +#define R_NIOS2_CALLR 20 /* Indirect call through register. */ +#define R_NIOS2_ALIGN 21 /* Alignment requirement for + linker relaxation. */ +#define R_NIOS2_GOT16 22 /* 16 bit GOT entry. */ +#define R_NIOS2_CALL16 23 /* 16 bit GOT entry for function. */ +#define R_NIOS2_GOTOFF_LO 24 /* %lo of offset to GOT pointer. */ +#define R_NIOS2_GOTOFF_HA 25 /* %hiadj of offset to GOT pointer. */ +#define R_NIOS2_PCREL_LO 26 /* %lo of PC relative offset. */ +#define R_NIOS2_PCREL_HA 27 /* %hiadj of PC relative offset. */ +#define R_NIOS2_TLS_GD16 28 /* 16 bit GOT offset for TLS GD. */ +#define R_NIOS2_TLS_LDM16 29 /* 16 bit GOT offset for TLS LDM. */ +#define R_NIOS2_TLS_LDO16 30 /* 16 bit module relative offset. */ +#define R_NIOS2_TLS_IE16 31 /* 16 bit GOT offset for TLS IE. */ +#define R_NIOS2_TLS_LE16 32 /* 16 bit LE TP-relative offset. */ +#define R_NIOS2_TLS_DTPMOD 33 /* Module number. */ +#define R_NIOS2_TLS_DTPREL 34 /* Module-relative offset. */ +#define R_NIOS2_TLS_TPREL 35 /* TP-relative offset. */ +#define R_NIOS2_COPY 36 /* Copy symbol at runtime. */ +#define R_NIOS2_GLOB_DAT 37 /* Create GOT entry. */ +#define R_NIOS2_JUMP_SLOT 38 /* Create PLT entry. */ +#define R_NIOS2_RELATIVE 39 /* Adjust by program base. */ +#define R_NIOS2_GOTOFF 40 /* 16 bit offset to GOT pointer. */ +#define R_NIOS2_CALL26_NOAT 41 /* Direct call in .noat section. */ +#define R_NIOS2_GOT_LO 42 /* %lo() of GOT entry. */ +#define R_NIOS2_GOT_HA 43 /* %hiadj() of GOT entry. */ +#define R_NIOS2_CALL_LO 44 /* %lo() of function GOT entry. */ +#define R_NIOS2_CALL_HA 45 /* %hiadj() of function GOT entry. */ + +/* TILEPro relocations. */ +#define R_TILEPRO_NONE 0 /* No reloc */ +#define R_TILEPRO_32 1 /* Direct 32 bit */ +#define R_TILEPRO_16 2 /* Direct 16 bit */ +#define R_TILEPRO_8 3 /* Direct 8 bit */ +#define R_TILEPRO_32_PCREL 4 /* PC relative 32 bit */ +#define R_TILEPRO_16_PCREL 5 /* PC relative 16 bit */ +#define R_TILEPRO_8_PCREL 6 /* PC relative 8 bit */ +#define R_TILEPRO_LO16 7 /* Low 16 bit */ +#define R_TILEPRO_HI16 8 /* High 16 bit */ +#define R_TILEPRO_HA16 9 /* High 16 bit, adjusted */ +#define R_TILEPRO_COPY 10 /* Copy relocation */ +#define R_TILEPRO_GLOB_DAT 11 /* Create GOT entry */ +#define R_TILEPRO_JMP_SLOT 12 /* Create PLT entry */ +#define R_TILEPRO_RELATIVE 13 /* Adjust by program base */ +#define R_TILEPRO_BROFF_X1 14 /* X1 pipe branch offset */ +#define R_TILEPRO_JOFFLONG_X1 15 /* X1 pipe jump offset */ +#define R_TILEPRO_JOFFLONG_X1_PLT 16 /* X1 pipe jump offset to PLT */ +#define R_TILEPRO_IMM8_X0 17 /* X0 pipe 8-bit */ +#define R_TILEPRO_IMM8_Y0 18 /* Y0 pipe 8-bit */ +#define R_TILEPRO_IMM8_X1 19 /* X1 pipe 8-bit */ +#define R_TILEPRO_IMM8_Y1 20 /* Y1 pipe 8-bit */ +#define R_TILEPRO_MT_IMM15_X1 21 /* X1 pipe mtspr */ +#define R_TILEPRO_MF_IMM15_X1 22 /* X1 pipe mfspr */ +#define R_TILEPRO_IMM16_X0 23 /* X0 pipe 16-bit */ +#define R_TILEPRO_IMM16_X1 24 /* X1 pipe 16-bit */ +#define R_TILEPRO_IMM16_X0_LO 25 /* X0 pipe low 16-bit */ +#define R_TILEPRO_IMM16_X1_LO 26 /* X1 pipe low 16-bit */ +#define R_TILEPRO_IMM16_X0_HI 27 /* X0 pipe high 16-bit */ +#define R_TILEPRO_IMM16_X1_HI 28 /* X1 pipe high 16-bit */ +#define R_TILEPRO_IMM16_X0_HA 29 /* X0 pipe high 16-bit, adjusted */ +#define R_TILEPRO_IMM16_X1_HA 30 /* X1 pipe high 16-bit, adjusted */ +#define R_TILEPRO_IMM16_X0_PCREL 31 /* X0 pipe PC relative 16 bit */ +#define R_TILEPRO_IMM16_X1_PCREL 32 /* X1 pipe PC relative 16 bit */ +#define R_TILEPRO_IMM16_X0_LO_PCREL 33 /* X0 pipe PC relative low 16 bit */ +#define R_TILEPRO_IMM16_X1_LO_PCREL 34 /* X1 pipe PC relative low 16 bit */ +#define R_TILEPRO_IMM16_X0_HI_PCREL 35 /* X0 pipe PC relative high 16 bit */ +#define R_TILEPRO_IMM16_X1_HI_PCREL 36 /* X1 pipe PC relative high 16 bit */ +#define R_TILEPRO_IMM16_X0_HA_PCREL 37 /* X0 pipe PC relative ha() 16 bit */ +#define R_TILEPRO_IMM16_X1_HA_PCREL 38 /* X1 pipe PC relative ha() 16 bit */ +#define R_TILEPRO_IMM16_X0_GOT 39 /* X0 pipe 16-bit GOT offset */ +#define R_TILEPRO_IMM16_X1_GOT 40 /* X1 pipe 16-bit GOT offset */ +#define R_TILEPRO_IMM16_X0_GOT_LO 41 /* X0 pipe low 16-bit GOT offset */ +#define R_TILEPRO_IMM16_X1_GOT_LO 42 /* X1 pipe low 16-bit GOT offset */ +#define R_TILEPRO_IMM16_X0_GOT_HI 43 /* X0 pipe high 16-bit GOT offset */ +#define R_TILEPRO_IMM16_X1_GOT_HI 44 /* X1 pipe high 16-bit GOT offset */ +#define R_TILEPRO_IMM16_X0_GOT_HA 45 /* X0 pipe ha() 16-bit GOT offset */ +#define R_TILEPRO_IMM16_X1_GOT_HA 46 /* X1 pipe ha() 16-bit GOT offset */ +#define R_TILEPRO_MMSTART_X0 47 /* X0 pipe mm "start" */ +#define R_TILEPRO_MMEND_X0 48 /* X0 pipe mm "end" */ +#define R_TILEPRO_MMSTART_X1 49 /* X1 pipe mm "start" */ +#define R_TILEPRO_MMEND_X1 50 /* X1 pipe mm "end" */ +#define R_TILEPRO_SHAMT_X0 51 /* X0 pipe shift amount */ +#define R_TILEPRO_SHAMT_X1 52 /* X1 pipe shift amount */ +#define R_TILEPRO_SHAMT_Y0 53 /* Y0 pipe shift amount */ +#define R_TILEPRO_SHAMT_Y1 54 /* Y1 pipe shift amount */ +#define R_TILEPRO_DEST_IMM8_X1 55 /* X1 pipe destination 8-bit */ +/* Relocs 56-59 are currently not defined. */ +#define R_TILEPRO_TLS_GD_CALL 60 /* "jal" for TLS GD */ +#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61 /* X0 pipe "addi" for TLS GD */ +#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62 /* X1 pipe "addi" for TLS GD */ +#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63 /* Y0 pipe "addi" for TLS GD */ +#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64 /* Y1 pipe "addi" for TLS GD */ +#define R_TILEPRO_TLS_IE_LOAD 65 /* "lw_tls" for TLS IE */ +#define R_TILEPRO_IMM16_X0_TLS_GD 66 /* X0 pipe 16-bit TLS GD offset */ +#define R_TILEPRO_IMM16_X1_TLS_GD 67 /* X1 pipe 16-bit TLS GD offset */ +#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68 /* X0 pipe low 16-bit TLS GD offset */ +#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69 /* X1 pipe low 16-bit TLS GD offset */ +#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70 /* X0 pipe high 16-bit TLS GD offset */ +#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71 /* X1 pipe high 16-bit TLS GD offset */ +#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72 /* X0 pipe ha() 16-bit TLS GD offset */ +#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73 /* X1 pipe ha() 16-bit TLS GD offset */ +#define R_TILEPRO_IMM16_X0_TLS_IE 74 /* X0 pipe 16-bit TLS IE offset */ +#define R_TILEPRO_IMM16_X1_TLS_IE 75 /* X1 pipe 16-bit TLS IE offset */ +#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76 /* X0 pipe low 16-bit TLS IE offset */ +#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77 /* X1 pipe low 16-bit TLS IE offset */ +#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78 /* X0 pipe high 16-bit TLS IE offset */ +#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79 /* X1 pipe high 16-bit TLS IE offset */ +#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80 /* X0 pipe ha() 16-bit TLS IE offset */ +#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81 /* X1 pipe ha() 16-bit TLS IE offset */ +#define R_TILEPRO_TLS_DTPMOD32 82 /* ID of module containing symbol */ +#define R_TILEPRO_TLS_DTPOFF32 83 /* Offset in TLS block */ +#define R_TILEPRO_TLS_TPOFF32 84 /* Offset in static TLS block */ +#define R_TILEPRO_IMM16_X0_TLS_LE 85 /* X0 pipe 16-bit TLS LE offset */ +#define R_TILEPRO_IMM16_X1_TLS_LE 86 /* X1 pipe 16-bit TLS LE offset */ +#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87 /* X0 pipe low 16-bit TLS LE offset */ +#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88 /* X1 pipe low 16-bit TLS LE offset */ +#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89 /* X0 pipe high 16-bit TLS LE offset */ +#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90 /* X1 pipe high 16-bit TLS LE offset */ +#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91 /* X0 pipe ha() 16-bit TLS LE offset */ +#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92 /* X1 pipe ha() 16-bit TLS LE offset */ + +#define R_TILEPRO_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ +#define R_TILEPRO_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ + +#define R_TILEPRO_NUM 130 + + +/* TILE-Gx relocations. */ +#define R_TILEGX_NONE 0 /* No reloc */ +#define R_TILEGX_64 1 /* Direct 64 bit */ +#define R_TILEGX_32 2 /* Direct 32 bit */ +#define R_TILEGX_16 3 /* Direct 16 bit */ +#define R_TILEGX_8 4 /* Direct 8 bit */ +#define R_TILEGX_64_PCREL 5 /* PC relative 64 bit */ +#define R_TILEGX_32_PCREL 6 /* PC relative 32 bit */ +#define R_TILEGX_16_PCREL 7 /* PC relative 16 bit */ +#define R_TILEGX_8_PCREL 8 /* PC relative 8 bit */ +#define R_TILEGX_HW0 9 /* hword 0 16-bit */ +#define R_TILEGX_HW1 10 /* hword 1 16-bit */ +#define R_TILEGX_HW2 11 /* hword 2 16-bit */ +#define R_TILEGX_HW3 12 /* hword 3 16-bit */ +#define R_TILEGX_HW0_LAST 13 /* last hword 0 16-bit */ +#define R_TILEGX_HW1_LAST 14 /* last hword 1 16-bit */ +#define R_TILEGX_HW2_LAST 15 /* last hword 2 16-bit */ +#define R_TILEGX_COPY 16 /* Copy relocation */ +#define R_TILEGX_GLOB_DAT 17 /* Create GOT entry */ +#define R_TILEGX_JMP_SLOT 18 /* Create PLT entry */ +#define R_TILEGX_RELATIVE 19 /* Adjust by program base */ +#define R_TILEGX_BROFF_X1 20 /* X1 pipe branch offset */ +#define R_TILEGX_JUMPOFF_X1 21 /* X1 pipe jump offset */ +#define R_TILEGX_JUMPOFF_X1_PLT 22 /* X1 pipe jump offset to PLT */ +#define R_TILEGX_IMM8_X0 23 /* X0 pipe 8-bit */ +#define R_TILEGX_IMM8_Y0 24 /* Y0 pipe 8-bit */ +#define R_TILEGX_IMM8_X1 25 /* X1 pipe 8-bit */ +#define R_TILEGX_IMM8_Y1 26 /* Y1 pipe 8-bit */ +#define R_TILEGX_DEST_IMM8_X1 27 /* X1 pipe destination 8-bit */ +#define R_TILEGX_MT_IMM14_X1 28 /* X1 pipe mtspr */ +#define R_TILEGX_MF_IMM14_X1 29 /* X1 pipe mfspr */ +#define R_TILEGX_MMSTART_X0 30 /* X0 pipe mm "start" */ +#define R_TILEGX_MMEND_X0 31 /* X0 pipe mm "end" */ +#define R_TILEGX_SHAMT_X0 32 /* X0 pipe shift amount */ +#define R_TILEGX_SHAMT_X1 33 /* X1 pipe shift amount */ +#define R_TILEGX_SHAMT_Y0 34 /* Y0 pipe shift amount */ +#define R_TILEGX_SHAMT_Y1 35 /* Y1 pipe shift amount */ +#define R_TILEGX_IMM16_X0_HW0 36 /* X0 pipe hword 0 */ +#define R_TILEGX_IMM16_X1_HW0 37 /* X1 pipe hword 0 */ +#define R_TILEGX_IMM16_X0_HW1 38 /* X0 pipe hword 1 */ +#define R_TILEGX_IMM16_X1_HW1 39 /* X1 pipe hword 1 */ +#define R_TILEGX_IMM16_X0_HW2 40 /* X0 pipe hword 2 */ +#define R_TILEGX_IMM16_X1_HW2 41 /* X1 pipe hword 2 */ +#define R_TILEGX_IMM16_X0_HW3 42 /* X0 pipe hword 3 */ +#define R_TILEGX_IMM16_X1_HW3 43 /* X1 pipe hword 3 */ +#define R_TILEGX_IMM16_X0_HW0_LAST 44 /* X0 pipe last hword 0 */ +#define R_TILEGX_IMM16_X1_HW0_LAST 45 /* X1 pipe last hword 0 */ +#define R_TILEGX_IMM16_X0_HW1_LAST 46 /* X0 pipe last hword 1 */ +#define R_TILEGX_IMM16_X1_HW1_LAST 47 /* X1 pipe last hword 1 */ +#define R_TILEGX_IMM16_X0_HW2_LAST 48 /* X0 pipe last hword 2 */ +#define R_TILEGX_IMM16_X1_HW2_LAST 49 /* X1 pipe last hword 2 */ +#define R_TILEGX_IMM16_X0_HW0_PCREL 50 /* X0 pipe PC relative hword 0 */ +#define R_TILEGX_IMM16_X1_HW0_PCREL 51 /* X1 pipe PC relative hword 0 */ +#define R_TILEGX_IMM16_X0_HW1_PCREL 52 /* X0 pipe PC relative hword 1 */ +#define R_TILEGX_IMM16_X1_HW1_PCREL 53 /* X1 pipe PC relative hword 1 */ +#define R_TILEGX_IMM16_X0_HW2_PCREL 54 /* X0 pipe PC relative hword 2 */ +#define R_TILEGX_IMM16_X1_HW2_PCREL 55 /* X1 pipe PC relative hword 2 */ +#define R_TILEGX_IMM16_X0_HW3_PCREL 56 /* X0 pipe PC relative hword 3 */ +#define R_TILEGX_IMM16_X1_HW3_PCREL 57 /* X1 pipe PC relative hword 3 */ +#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */ +#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */ +#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */ +#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */ +#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */ +#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */ +#define R_TILEGX_IMM16_X0_HW0_GOT 64 /* X0 pipe hword 0 GOT offset */ +#define R_TILEGX_IMM16_X1_HW0_GOT 65 /* X1 pipe hword 0 GOT offset */ +#define R_TILEGX_IMM16_X0_HW0_PLT_PCREL 66 /* X0 pipe PC-rel PLT hword 0 */ +#define R_TILEGX_IMM16_X1_HW0_PLT_PCREL 67 /* X1 pipe PC-rel PLT hword 0 */ +#define R_TILEGX_IMM16_X0_HW1_PLT_PCREL 68 /* X0 pipe PC-rel PLT hword 1 */ +#define R_TILEGX_IMM16_X1_HW1_PLT_PCREL 69 /* X1 pipe PC-rel PLT hword 1 */ +#define R_TILEGX_IMM16_X0_HW2_PLT_PCREL 70 /* X0 pipe PC-rel PLT hword 2 */ +#define R_TILEGX_IMM16_X1_HW2_PLT_PCREL 71 /* X1 pipe PC-rel PLT hword 2 */ +#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */ +#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */ +#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */ +#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */ +#define R_TILEGX_IMM16_X0_HW3_PLT_PCREL 76 /* X0 pipe PC-rel PLT hword 3 */ +#define R_TILEGX_IMM16_X1_HW3_PLT_PCREL 77 /* X1 pipe PC-rel PLT hword 3 */ +#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78 /* X0 pipe hword 0 TLS GD offset */ +#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79 /* X1 pipe hword 0 TLS GD offset */ +#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80 /* X0 pipe hword 0 TLS LE offset */ +#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81 /* X1 pipe hword 0 TLS LE offset */ +#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */ +#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */ +#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */ +#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */ +#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */ +#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */ +#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */ +#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */ +/* Relocs 90-91 are currently not defined. */ +#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92 /* X0 pipe hword 0 TLS IE offset */ +#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93 /* X1 pipe hword 0 TLS IE offset */ +#define R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 94 /* X0 pipe PC-rel PLT last hword 0 */ +#define R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 95 /* X1 pipe PC-rel PLT last hword 0 */ +#define R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 96 /* X0 pipe PC-rel PLT last hword 1 */ +#define R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 97 /* X1 pipe PC-rel PLT last hword 1 */ +#define R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 98 /* X0 pipe PC-rel PLT last hword 2 */ +#define R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 99 /* X1 pipe PC-rel PLT last hword 2 */ +#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */ +#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */ +#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */ +#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */ +/* Relocs 104-105 are currently not defined. */ +#define R_TILEGX_TLS_DTPMOD64 106 /* 64-bit ID of symbol's module */ +#define R_TILEGX_TLS_DTPOFF64 107 /* 64-bit offset in TLS block */ +#define R_TILEGX_TLS_TPOFF64 108 /* 64-bit offset in static TLS block */ +#define R_TILEGX_TLS_DTPMOD32 109 /* 32-bit ID of symbol's module */ +#define R_TILEGX_TLS_DTPOFF32 110 /* 32-bit offset in TLS block */ +#define R_TILEGX_TLS_TPOFF32 111 /* 32-bit offset in static TLS block */ +#define R_TILEGX_TLS_GD_CALL 112 /* "jal" for TLS GD */ +#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113 /* X0 pipe "addi" for TLS GD */ +#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114 /* X1 pipe "addi" for TLS GD */ +#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115 /* Y0 pipe "addi" for TLS GD */ +#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116 /* Y1 pipe "addi" for TLS GD */ +#define R_TILEGX_TLS_IE_LOAD 117 /* "ld_tls" for TLS IE */ +#define R_TILEGX_IMM8_X0_TLS_ADD 118 /* X0 pipe "addi" for TLS GD/IE */ +#define R_TILEGX_IMM8_X1_TLS_ADD 119 /* X1 pipe "addi" for TLS GD/IE */ +#define R_TILEGX_IMM8_Y0_TLS_ADD 120 /* Y0 pipe "addi" for TLS GD/IE */ +#define R_TILEGX_IMM8_Y1_TLS_ADD 121 /* Y1 pipe "addi" for TLS GD/IE */ + +#define R_TILEGX_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ +#define R_TILEGX_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ + +#define R_TILEGX_NUM 130 + +#ifdef __cplusplus +} +#endif + +#endif /*__LWP_ELF_H__*/ diff --git a/components/lwp/lwp_futex.c b/components/lwp/lwp_futex.c new file mode 100644 index 0000000000000000000000000000000000000000..44c798f31b7f6a40e3695eaa97f320334ab1af46 --- /dev/null +++ b/components/lwp/lwp_futex.c @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021/01/02 bernard the first version + */ + +#include +#include +#ifdef RT_USING_USERSPACE +#include +#endif +#include "clock_time.h" + +struct rt_futex +{ + int *uaddr; + rt_list_t waiting_thread; + struct lwp_avl_struct node; + struct rt_object *custom_obj; +}; + +static struct rt_mutex _futex_lock; + +static int futex_system_init(void) +{ + rt_mutex_init(&_futex_lock, "futexList", RT_IPC_FLAG_FIFO); + return 0; +} +INIT_PREV_EXPORT(futex_system_init); + +rt_err_t futex_destory(void *data) +{ + rt_err_t ret = -1; + rt_base_t level; + struct rt_futex *futex = (struct rt_futex *)data; + + if (futex) + { + level = rt_hw_interrupt_disable(); + /* remove futex from futext avl */ + lwp_avl_remove(&futex->node, (struct lwp_avl_struct **)futex->node.data); + rt_hw_interrupt_enable(level); + + /* release object */ + rt_free(futex); + ret = 0; + } + return ret; +} + +struct rt_futex* futex_create(int *uaddr, struct rt_lwp *lwp) +{ + struct rt_futex *futex = RT_NULL; + struct rt_object *obj = RT_NULL; + + if (!lwp) + { + return RT_NULL; + } + futex = (struct rt_futex *)rt_malloc(sizeof(struct rt_futex)); + if (!futex) + { + return RT_NULL; + } + obj = rt_custom_object_create("futex", (void *)futex, futex_destory); + if (!obj) + { + rt_free(futex); + return RT_NULL; + } + + futex->uaddr = uaddr; + futex->node.avl_key = (avl_key_t)uaddr; + futex->node.data = &lwp->address_search_head; + futex->custom_obj = obj; + rt_list_init(&(futex->waiting_thread)); + + /* insert into futex head */ + lwp_avl_insert(&futex->node, &lwp->address_search_head); + return futex; +} + +static struct rt_futex* futex_get(void *uaddr, struct rt_lwp *lwp) +{ + struct rt_futex *futex = RT_NULL; + struct lwp_avl_struct *node = RT_NULL; + + node = lwp_avl_find((avl_key_t)uaddr, lwp->address_search_head); + if (!node) + { + return RT_NULL; + } + futex = rt_container_of(node, struct rt_futex, node); + return futex; +} + +int futex_wait(struct rt_futex *futex, int value, const struct timespec *timeout) +{ + rt_base_t level = 0; + rt_err_t ret = -RT_EINTR; + + if (*(futex->uaddr) == value) + { + rt_thread_t thread = rt_thread_self(); + + level = rt_hw_interrupt_disable(); + ret = rt_thread_suspend_with_flag(thread, RT_INTERRUPTIBLE); + + if (ret < 0) + { + rt_mutex_release(&_futex_lock); + rt_hw_interrupt_enable(level); + rt_set_errno(EINTR); + return ret; + } + + /* add into waiting thread list */ + rt_list_insert_before(&(futex->waiting_thread), &(thread->tlist)); + + /* with timeout */ + if (timeout) + { + rt_int32_t time = clock_time_to_tick(timeout); + + /* start the timer of thread */ + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &time); + rt_timer_start(&(thread->thread_timer)); + } + rt_mutex_release(&_futex_lock); + rt_hw_interrupt_enable(level); + + /* do schedule */ + rt_schedule(); + + ret = thread->error; + /* check errno */ + } + else + { + rt_set_errno(EAGAIN); + } + + return ret; +} + +void futex_wake(struct rt_futex *futex, int number) +{ + rt_base_t level = rt_hw_interrupt_disable(); + + while (!rt_list_isempty(&(futex->waiting_thread)) && number) + { + rt_thread_t thread; + + thread = rt_list_entry(futex->waiting_thread.next, struct rt_thread, tlist); + /* remove from waiting list */ + rt_list_remove(&(thread->tlist)); + + thread->error = RT_EOK; + /* resume the suspended thread */ + rt_thread_resume(thread); + + number --; + } + rt_mutex_release(&_futex_lock); + rt_hw_interrupt_enable(level); + + /* do schedule */ + rt_schedule(); +} + +int sys_futex(int *uaddr, int op, int val, const struct timespec *timeout, + int *uaddr2, int val3) +{ + struct rt_lwp *lwp = RT_NULL; + struct rt_futex *futex = RT_NULL; + int ret = 0; + rt_err_t lock_ret = 0; + + if (!lwp_user_accessable(uaddr, sizeof(int))) + { + rt_set_errno(EINVAL); + return -RT_EINVAL; + } + if (timeout) + { + if (!lwp_user_accessable((void *)timeout, sizeof(struct timespec))) + { + rt_set_errno(EINVAL); + return -RT_EINVAL; + } + } + + lock_ret = rt_mutex_take_interruptible(&_futex_lock, RT_WAITING_FOREVER); + if (lock_ret != RT_EOK) + { + rt_set_errno(EAGAIN); + return -RT_EINTR; + } + + lwp = lwp_self(); + futex = futex_get(uaddr, lwp); + if (futex == RT_NULL) + { + /* create a futex according to this uaddr */ + futex = futex_create(uaddr, lwp); + if (futex == RT_NULL) + { + rt_mutex_release(&_futex_lock); + rt_set_errno(ENOMEM); + return -RT_ENOMEM; + } + if (lwp_user_object_add(lwp, futex->custom_obj) != 0) + { + rt_custom_object_destroy(futex->custom_obj); + rt_set_errno(ENOMEM); + return -RT_ENOMEM; + } + } + + switch (op) + { + case FUTEX_WAIT: + ret = futex_wait(futex, val, timeout); + /* _futex_lock is released by futex_wait */ + break; + + case FUTEX_WAKE: + futex_wake(futex, val); + /* _futex_lock is released by futex_wake */ + break; + + default: + rt_mutex_release(&_futex_lock); + rt_set_errno(ENOSYS); + ret = -ENOSYS; + break; + } + + return ret; +} diff --git a/components/lwp/lwp_ipc.c b/components/lwp/lwp_ipc.c new file mode 100644 index 0000000000000000000000000000000000000000..ea96db71c0cd0b90366142f951d3d2f86386aab8 --- /dev/null +++ b/components/lwp/lwp_ipc.c @@ -0,0 +1,1144 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-12 Jesven first version + */ +#include +#include +#include + +#include "lwp_ipc.h" +#include "lwp_ipc_internal.h" + +#include +#include + +/** + * the IPC channel states + */ +enum +{ + RT_IPC_STAT_IDLE, /* no suspended threads */ + RT_IPC_STAT_WAIT, /* suspended receivers exist */ + RT_IPC_STAT_ACTIVE, /* suspended senders exist */ +}; + +/** + * IPC message structure. + * + * They are allocated and released in the similar way like 'rt_chfd'. + */ +struct rt_ipc_msg +{ + struct rt_channel_msg msg; /**< the payload of msg */ + rt_list_t mlist; /**< the msg list */ + rt_uint8_t need_reply; /**< whether msg wait reply*/ +}; +typedef struct rt_ipc_msg *rt_ipc_msg_t; + +static rt_ipc_msg_t _ipc_msg_free_list = (rt_ipc_msg_t)RT_NULL; /* released chain */ +static int rt_ipc_msg_used = 0; /* first unallocated entry */ +static struct rt_ipc_msg ipc_msg_pool[RT_CH_MSG_MAX_NR]; /* initial message array */ + +/** + * Allocate an IPC message from the statically-allocated array. + */ +static rt_ipc_msg_t _ipc_msg_alloc(void) +{ + rt_ipc_msg_t p = (rt_ipc_msg_t)RT_NULL; + + if (_ipc_msg_free_list) /* use the released chain first */ + { + p = _ipc_msg_free_list; + _ipc_msg_free_list = (rt_ipc_msg_t)p->msg.sender; /* emtry payload as a pointer */ + } + else if (rt_ipc_msg_used < RT_CH_MSG_MAX_NR) + { + p = &ipc_msg_pool[rt_ipc_msg_used]; + rt_ipc_msg_used++; + } + return p; +} + +/** + * Put a released IPC message back to the released chain. + */ +static void _ipc_msg_free(rt_ipc_msg_t p_msg) +{ + p_msg->msg.sender = (void*)_ipc_msg_free_list; + _ipc_msg_free_list = p_msg; +} + +/** + * Initialized the IPC message. + */ +static void rt_ipc_msg_init(rt_ipc_msg_t msg, struct rt_channel_msg *data, rt_uint8_t need_reply) +{ + RT_ASSERT(msg != RT_NULL); + + msg->need_reply = need_reply; + msg->msg = *data; + msg->msg.sender = (void*)rt_thread_self(); + rt_list_init(&msg->mlist); +} + +/** + * Initialized the list of the waiting receivers on the IPC channel. + */ +rt_inline rt_err_t rt_channel_object_init(struct rt_ipc_object *ipc) +{ + rt_list_init(&(ipc->suspend_thread)); /* receiver list */ + + return RT_EOK; +} + +/** + * Wakeup the first suspened thread in the list. + */ +rt_inline rt_err_t rt_channel_list_resume(rt_list_t *list) +{ + struct rt_thread *thread; + + /* get the first thread entry waiting for sending */ + thread = rt_list_entry(list->next, struct rt_thread, tlist); + + rt_thread_resume(thread); + + return RT_EOK; +} + +/** + * Wakeup all the suspended threads in the list. + */ +rt_inline rt_err_t rt_channel_list_resume_all(rt_list_t *list) +{ + struct rt_thread *thread; + register rt_ubase_t temp; + + /* wakeup all suspended threads for sending */ + while (!rt_list_isempty(list)) + { + temp = rt_hw_interrupt_disable(); + thread = rt_list_entry(list->next, struct rt_thread, tlist); + thread->error = -RT_ERROR; + rt_thread_resume(thread); + rt_hw_interrupt_enable(temp); + } + + return RT_EOK; +} + +/** + * Suspend the thread and chain it into the end of the list. + */ +rt_inline rt_err_t rt_channel_list_suspend(rt_list_t *list, struct rt_thread *thread) +{ + /* suspend thread */ + rt_err_t ret = rt_thread_suspend_with_flag(thread, RT_INTERRUPTIBLE); + + if (ret == RT_EOK) + { + rt_list_insert_before(list, &(thread->tlist)); /* list end */ + } + + return ret; +} + + +static void _rt_channel_check_wq_wakup(rt_channel_t ch) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + if (rt_list_isempty(&ch->wait_msg)) + { + rt_hw_interrupt_enable(level); + return; + } + + rt_wqueue_wakeup(&ch->reader_queue, 0); + rt_hw_interrupt_enable(level); +} + +/** + * Create a new or open an existing IPC channel. + */ +rt_channel_t rt_raw_channel_open(const char *name, int flags) +{ + register rt_ubase_t temp = 0; + rt_channel_t ch = RT_NULL; + + struct rt_object *object; + struct rt_list_node *node; + struct rt_object_information *information; + + temp = rt_hw_interrupt_disable(); + information = rt_object_get_information(RT_Object_Class_Channel); + RT_ASSERT(information != RT_NULL); + + /* retrieve the existing IPC channels */ + for (node = information->object_list.next; + node != &(information->object_list); + node = node->next) + { + object = rt_list_entry(node, struct rt_object, list); + if (rt_strncmp(object->name, name, RT_NAME_MAX) == 0) + { + if ((flags & O_CREAT) && (flags & O_EXCL)) + { + goto quit; + } + /* find the IPC channel with the specific name */ + ch = (rt_channel_t)object; + ch->ref++; /* increase the reference count */ + break; + } + } + if (!ch) /* create a new IPC channel */ + { + if (flags & O_CREAT) + { + RT_DEBUG_NOT_IN_INTERRUPT; + + /* allocate a real IPC channel structure */ + ch = (rt_channel_t)rt_object_allocate(RT_Object_Class_Channel, name); + } + + if (!ch) + { + goto quit; + } + + rt_channel_object_init(&ch->parent); /* suspended receivers */ + rt_list_init(&ch->wait_msg); /* unhandled messages */ + rt_list_init(&ch->wait_thread); /* suspended senders */ + rt_wqueue_init(&ch->reader_queue); /* reader poll queue */ + ch->reply = RT_NULL; + ch->stat = RT_IPC_STAT_IDLE; /* no suspended threads */ + ch->ref = 1; + } +quit: + rt_hw_interrupt_enable(temp); + return ch; +} + +/** + * Close an existiong IPC channel, release the resources. + */ +rt_err_t rt_raw_channel_close(rt_channel_t ch) +{ + register rt_ubase_t temp; + + RT_DEBUG_NOT_IN_INTERRUPT; + + if (ch == RT_NULL) + { + return -RT_EIO; + } + + temp = rt_hw_interrupt_disable(); + if (rt_object_get_type(&ch->parent.parent) != RT_Object_Class_Channel) + { + rt_hw_interrupt_enable(temp); + return -RT_EIO; + } + if (rt_object_is_systemobject(&ch->parent.parent) != RT_FALSE) + { + rt_hw_interrupt_enable(temp); + return -RT_EIO; + } + + if (ch->ref == 0) + { + rt_hw_interrupt_enable(temp); + return -RT_EIO; + } + ch->ref--; + if (ch->ref == 0) + { + /* wakeup all the suspended receivers and senders */ + rt_channel_list_resume_all(&ch->parent.suspend_thread); + rt_channel_list_resume_all(&ch->wait_thread); + + /* all ipc msg will lost */ + rt_list_init(&ch->wait_msg); + + rt_object_delete(&ch->parent.parent); /* release the IPC channel structure */ + } + rt_hw_interrupt_enable(temp); + return RT_EOK; +} + +static rt_err_t wakeup_sender_wait_recv(void *object, struct rt_thread *thread) +{ + rt_channel_t ch; + + ch = (rt_channel_t)object; + if (ch->stat == RT_IPC_STAT_ACTIVE && ch->reply == thread) + { + ch->stat = RT_IPC_STAT_IDLE; + ch->reply = RT_NULL; + } + else + { + rt_ipc_msg_t msg; + rt_list_t *l; + + l = ch->wait_msg.next; + while (l != &ch->wait_msg) + { + msg = rt_list_entry(l, struct rt_ipc_msg, mlist); + if (msg->need_reply && msg->msg.sender == thread) + { + rt_list_remove(&msg->mlist); /* remove the msg from the channel */ + _ipc_msg_free(msg); + break; + } + l = l->next; + } + } + thread->error = -RT_EINTR; + return rt_thread_resume(thread); /* wake up the sender */ +} + +static rt_err_t wakeup_sender_wait_reply(void *object, struct rt_thread *thread) +{ + rt_channel_t ch; + + ch = (rt_channel_t)object; + RT_ASSERT(ch->stat == RT_IPC_STAT_ACTIVE && ch->reply == thread); + ch->stat = RT_IPC_STAT_IDLE; + ch->reply = RT_NULL; + thread->error = -RT_EINTR; + return rt_thread_resume(thread); /* wake up the sender */ +} + +static void sender_timeout(void *parameter) +{ + struct rt_thread *thread = (struct rt_thread*)parameter; + rt_channel_t ch; + + ch = (rt_channel_t)(thread->wakeup.user_data); + if (ch->stat == RT_IPC_STAT_ACTIVE && ch->reply == thread) + { + ch->stat = RT_IPC_STAT_IDLE; + ch->reply = RT_NULL; + } + else + { + rt_ipc_msg_t msg; + rt_list_t *l; + + l = ch->wait_msg.next; + while (l != &ch->wait_msg) + { + msg = rt_list_entry(l, struct rt_ipc_msg, mlist); + if (msg->need_reply && msg->msg.sender == thread) + { + rt_list_remove(&msg->mlist); /* remove the msg from the channel */ + _ipc_msg_free(msg); + break; + } + l = l->next; + } + } + thread->error = -RT_ETIMEOUT; + thread->wakeup.func = RT_NULL; + + rt_list_remove(&(thread->tlist)); + /* insert to schedule ready list */ + rt_schedule_insert_thread(thread); + /* do schedule */ + rt_schedule(); +} + +/** + * Send data through an IPC channel, wait for the reply or not. + */ +static rt_err_t _rt_raw_channel_send_recv_timeout(rt_channel_t ch, rt_channel_msg_t data, int need_reply, rt_channel_msg_t data_ret, rt_int32_t time) +{ + rt_ipc_msg_t msg; + struct rt_thread *thread_recv, *thread_send = 0; + register rt_base_t temp; + rt_err_t ret; + void (*old_timeout_func)(void *) = 0; + + if (need_reply) + { + RT_DEBUG_NOT_IN_INTERRUPT; + } + + if (ch == RT_NULL) + { + return -RT_EIO; + } + + temp = rt_hw_interrupt_disable(); + + if (rt_object_get_type(&ch->parent.parent) != RT_Object_Class_Channel) + { + rt_hw_interrupt_enable(temp); + return -RT_EIO; + } + if (need_reply && time == 0) + { + rt_hw_interrupt_enable(temp); + return -RT_ETIMEOUT; + } + + /* allocate an IPC message */ + msg = _ipc_msg_alloc(); + if (!msg) + { + rt_hw_interrupt_enable(temp); + return -RT_ENOMEM; + } + + rt_ipc_msg_init(msg, data, need_reply); + + if (need_reply) + { + thread_send = rt_thread_self(); + thread_send->error = RT_EOK; + } + + switch (ch->stat) + { + case RT_IPC_STAT_IDLE: + case RT_IPC_STAT_ACTIVE: + if (need_reply) + { + ret = rt_channel_list_suspend(&ch->wait_thread, thread_send); + if (ret != RT_EOK) + { + _ipc_msg_free(msg); + rt_hw_interrupt_enable(temp); + return ret; + } + rt_thread_wakeup_set(thread_send, wakeup_sender_wait_recv, (void*)ch); + if (time > 0) + { + rt_timer_control(&(thread_send->thread_timer), + RT_TIMER_CTRL_GET_FUNC, + &old_timeout_func); + rt_timer_control(&(thread_send->thread_timer), + RT_TIMER_CTRL_SET_FUNC, + sender_timeout); + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread_send->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &time); + rt_timer_start(&(thread_send->thread_timer)); + } + } + /* + * If there is no thread waiting for messages, chain the message + * into the list. + */ + rt_list_insert_before(&ch->wait_msg, &msg->mlist); + break; + case RT_IPC_STAT_WAIT: + /* + * If there are suspended receivers on the IPC channel, transfer the + * pointer of the message to the first receiver directly and wake it + * up. + */ + RT_ASSERT(ch->parent.suspend_thread.next != &ch->parent.suspend_thread); + + if (need_reply) + { + ret = rt_channel_list_suspend(&ch->wait_thread, thread_send); + if (ret != RT_EOK) + { + _ipc_msg_free(msg); + rt_hw_interrupt_enable(temp); + return ret; + } + ch->reply = thread_send; /* record the current waiting sender */ + ch->stat = RT_IPC_STAT_ACTIVE; + rt_thread_wakeup_set(thread_send, wakeup_sender_wait_reply, (void*)ch); + if (time > 0) + { + rt_timer_control(&(thread_send->thread_timer), + RT_TIMER_CTRL_GET_FUNC, + &old_timeout_func); + rt_timer_control(&(thread_send->thread_timer), + RT_TIMER_CTRL_SET_FUNC, + sender_timeout); + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread_send->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &time); + rt_timer_start(&(thread_send->thread_timer)); + } + } + else + { + ch->stat = RT_IPC_STAT_IDLE; + } + thread_recv = rt_list_entry(ch->parent.suspend_thread.next, struct rt_thread, tlist); + thread_recv->msg_ret = msg; /* to the first suspended receiver */ + thread_recv->error = RT_EOK; + rt_channel_list_resume(&ch->parent.suspend_thread); + break; + default: + break; + } + + if ( ch->stat == RT_IPC_STAT_IDLE) + { + _rt_channel_check_wq_wakup(ch); + } + rt_hw_interrupt_enable(temp); + + /* reschedule in order to let the potential receivers run */ + rt_schedule(); + + if (need_reply) + { + temp = rt_hw_interrupt_disable(); + if (old_timeout_func) + { + rt_timer_control(&(thread_send->thread_timer), + RT_TIMER_CTRL_SET_FUNC, + old_timeout_func); + } + ret = thread_send->error; + rt_hw_interrupt_enable(temp); + + if (ret != RT_EOK) + { + return ret; + } + + /* If the sender gets the chance to run, the requested reply must be valid. */ + RT_ASSERT(data_ret != RT_NULL); + *data_ret = ((rt_ipc_msg_t)(thread_send->msg_ret))->msg; /* extract data */ + temp = rt_hw_interrupt_disable(); + _ipc_msg_free(thread_send->msg_ret); /* put back the message to kernel */ + rt_hw_interrupt_enable(temp); + thread_send->msg_ret = RT_NULL; + } + + return RT_EOK; +} + +/** + * Send data through an IPC channel with no reply. + */ +rt_err_t rt_raw_channel_send(rt_channel_t ch, rt_channel_msg_t data) +{ + return _rt_raw_channel_send_recv_timeout(ch, data, 0, 0, RT_WAITING_FOREVER); +} + +/** + * Send data through an IPC channel and wait for the relpy. + */ +rt_err_t rt_raw_channel_send_recv(rt_channel_t ch, rt_channel_msg_t data, rt_channel_msg_t data_ret) +{ + return _rt_raw_channel_send_recv_timeout(ch, data, 1, data_ret, RT_WAITING_FOREVER); +} + +/** + * Send data through an IPC channel and wait for the relpy. + */ +rt_err_t rt_raw_channel_send_recv_timeout(rt_channel_t ch, rt_channel_msg_t data, rt_channel_msg_t data_ret, rt_int32_t time) +{ + return _rt_raw_channel_send_recv_timeout(ch, data, 1, data_ret, time); +} + +/** + * Reply to the waiting sender and wake it up. + */ +rt_err_t rt_raw_channel_reply(rt_channel_t ch, rt_channel_msg_t data) +{ + rt_ipc_msg_t msg; + struct rt_thread *thread; + register rt_base_t temp; + + if (ch == RT_NULL) + { + return -RT_EIO; + } + + temp = rt_hw_interrupt_disable(); + + if (rt_object_get_type(&ch->parent.parent) != RT_Object_Class_Channel) + { + rt_hw_interrupt_enable(temp); + return -RT_EIO; + } + + if (ch->stat != RT_IPC_STAT_ACTIVE) + { + rt_hw_interrupt_enable(temp); + return -RT_ERROR; + } + + if (ch->reply == RT_NULL) + { + rt_hw_interrupt_enable(temp); + return -RT_ERROR; + } + + /* allocate an IPC message */ + msg = _ipc_msg_alloc(); + if (!msg) + { + rt_hw_interrupt_enable(temp); + return -RT_ENOMEM; + } + + rt_ipc_msg_init(msg, data, 0); + + thread = ch->reply; + thread->msg_ret = msg; /* transfer the reply to the sender */ + rt_thread_resume(thread); /* wake up the sender */ + ch->stat = RT_IPC_STAT_IDLE; + ch->reply = RT_NULL; + + _rt_channel_check_wq_wakup(ch); + rt_hw_interrupt_enable(temp); + rt_schedule(); + + return RT_EOK; +} + +static rt_err_t wakeup_receiver(void *object, struct rt_thread *thread) +{ + rt_channel_t ch; + rt_err_t ret; + + ch = (rt_channel_t)object; + ch->stat = RT_IPC_STAT_IDLE; + thread->error = -RT_EINTR; + ret = rt_channel_list_resume(&ch->parent.suspend_thread); + _rt_channel_check_wq_wakup(ch); + return ret; +} + +static void receiver_timeout(void *parameter) +{ + struct rt_thread *thread = (struct rt_thread*)parameter; + rt_channel_t ch; + + ch = (rt_channel_t)(thread->wakeup.user_data); + + ch->stat = RT_IPC_STAT_IDLE; + thread->error = -RT_ETIMEOUT; + thread->wakeup.func = RT_NULL; + + rt_list_remove(&(thread->tlist)); + /* insert to schedule ready list */ + rt_schedule_insert_thread(thread); + + _rt_channel_check_wq_wakup(ch); + /* do schedule */ + rt_schedule(); +} + +/** + * Fetch a message from the specified IPC channel. + */ +static rt_err_t _rt_raw_channel_recv_timeout(rt_channel_t ch, rt_channel_msg_t data, rt_int32_t time) +{ + struct rt_thread *thread; + rt_ipc_msg_t msg_ret; + register rt_base_t temp; + rt_err_t ret; + void (*old_timeout_func)(void *) = 0; + + RT_DEBUG_NOT_IN_INTERRUPT; + + if (ch == RT_NULL) + { + return -RT_EIO; + } + + temp = rt_hw_interrupt_disable(); + + if (rt_object_get_type(&ch->parent.parent) != RT_Object_Class_Channel) + { + rt_hw_interrupt_enable(temp); + return -RT_EIO; + } + if (ch->stat != RT_IPC_STAT_IDLE) + { + rt_hw_interrupt_enable(temp); + return -RT_ERROR; + } + + if (ch->wait_msg.next != &ch->wait_msg) /* there exist unhandled messages */ + { + msg_ret = rt_list_entry(ch->wait_msg.next, struct rt_ipc_msg, mlist); + rt_list_remove(ch->wait_msg.next); /* remove the message from the channel */ + if (msg_ret->need_reply) + { + RT_ASSERT(ch->wait_thread.next != &ch->wait_thread); + + thread = rt_list_entry(ch->wait_thread.next, struct rt_thread, tlist); + rt_list_remove(ch->wait_thread.next); + ch->reply = thread; /* record the waiting sender */ + ch->stat = RT_IPC_STAT_ACTIVE; /* no valid suspened receivers */ + } + *data = msg_ret->msg; /* extract the transferred data */ + _ipc_msg_free(msg_ret); /* put back the message to kernel */ + } + else + { + if (time == 0) + { + rt_hw_interrupt_enable(temp); + return -RT_ETIMEOUT; + } + /* no valid message, we must wait */ + thread = rt_thread_self(); + + ret = rt_channel_list_suspend(&ch->parent.suspend_thread, thread); + if (ret != RT_EOK) + { + rt_hw_interrupt_enable(temp); + return ret; + } + rt_thread_wakeup_set(thread, wakeup_receiver, (void*)ch); + ch->stat = RT_IPC_STAT_WAIT;/* no valid suspended senders */ + thread->error = RT_EOK; + if (time > 0) + { + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_GET_FUNC, + &old_timeout_func); + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_FUNC, + receiver_timeout); + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &time); + rt_timer_start(&(thread->thread_timer)); + } + rt_hw_interrupt_enable(temp); + + rt_schedule(); /* let the senders run */ + + temp = rt_hw_interrupt_disable(); + if (old_timeout_func) + { + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_FUNC, + old_timeout_func); + } + ret = thread->error; + if ( ret != RT_EOK) + { + rt_hw_interrupt_enable(temp); + return ret; + } + /* If waked up, the received message has been store into the thread. */ + *data = ((rt_ipc_msg_t)(thread->msg_ret))->msg; /* extract data */ + _ipc_msg_free(thread->msg_ret); /* put back the message to kernel */ + thread->msg_ret = RT_NULL; + } + + rt_hw_interrupt_enable(temp); + + return RT_EOK; +} + +rt_err_t rt_raw_channel_recv(rt_channel_t ch, rt_channel_msg_t data) +{ + return _rt_raw_channel_recv_timeout(ch, data, RT_WAITING_FOREVER); +} + +rt_err_t rt_raw_channel_recv_timeout(rt_channel_t ch, rt_channel_msg_t data, rt_int32_t time) +{ + return _rt_raw_channel_recv_timeout(ch, data, time); +} +/** + * Peek a message from the specified IPC channel. + */ +rt_err_t rt_raw_channel_peek(rt_channel_t ch, rt_channel_msg_t data) +{ + return _rt_raw_channel_recv_timeout(ch, data, 0); +} + +/* for API */ + +static int lwp_fd_new(int fdt_type) +{ + struct dfs_fdtable *fdt; + + if (fdt_type) + { + fdt = dfs_fdtable_get_global(); + } + else + { + fdt = dfs_fdtable_get(); + } + return fdt_fd_new(fdt); +} + +static struct dfs_fd *lwp_fd_get(int fdt_type, int fd) +{ + struct dfs_fdtable *fdt; + + if (fdt_type) + { + fdt = dfs_fdtable_get_global(); + } + else + { + fdt = dfs_fdtable_get(); + } + return fdt_fd_get(fdt, fd); +} + +static void lwp_fd_release(int fdt_type, int fd) +{ + struct dfs_fdtable *fdt; + + if (fdt_type) + { + fdt = dfs_fdtable_get_global(); + } + else + { + fdt = dfs_fdtable_get(); + } + fdt_fd_release(fdt, fd); +} + +static int _chfd_alloc(int fdt_type) +{ + /* create a BSD socket */ + int fd; + + /* allocate a fd */ + fd = lwp_fd_new(fdt_type); + + if (fd < 0) + { + return -1; + } + return fd; +} + +static void _chfd_free(int fd, int fdt_type) +{ + struct dfs_fd *d; + + d = lwp_fd_get(fdt_type, fd); + if (d == RT_NULL) + { + return; + } + lwp_fd_release(fdt_type, fd); +} + +/* for fops */ +static int channel_fops_poll(struct dfs_fd *file, struct rt_pollreq *req) +{ + int mask = POLLOUT; + rt_channel_t ch; + + ch = (rt_channel_t)file->fnode->data; + rt_poll_add(&(ch->reader_queue), req); + if (ch->stat != RT_IPC_STAT_IDLE) + { + return mask; + } + if (!rt_list_isempty(&ch->wait_msg)) + { + mask |= POLLIN; + } + return mask; +} + +static int channel_fops_close(struct dfs_fd *file) +{ + rt_channel_t ch; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ch = (rt_channel_t)file->fnode->data; + ch->ref--; + if (ch->ref == 0) + { + /* wakeup all the suspended receivers and senders */ + rt_channel_list_resume_all(&ch->parent.suspend_thread); + rt_channel_list_resume_all(&ch->wait_thread); + + /* all ipc msg will lost */ + rt_list_init(&ch->wait_msg); + + rt_object_delete(&ch->parent.parent); /* release the IPC channel structure */ + } + rt_hw_interrupt_enable(level); + return 0; +} + +static const struct dfs_file_ops channel_fops = +{ + NULL, /* open */ + channel_fops_close, + NULL, + NULL, + NULL, + NULL, + NULL, /* lseek */ + NULL, /* getdents */ + channel_fops_poll, +}; + +int lwp_channel_open(int fdt_type, const char *name, int flags) +{ + int fd; + rt_channel_t ch = RT_NULL; + struct dfs_fd *d; + + fd = _chfd_alloc(fdt_type); /* allocate an IPC channel descriptor */ + if (fd == -1) + { + goto quit; + } + d = lwp_fd_get(fdt_type, fd); + d->fnode = (struct dfs_fnode *)rt_malloc(sizeof(struct dfs_fnode)); + if (!d->fnode) + { + _chfd_free(fd, fdt_type); + fd = -1; + goto quit; + } + + ch = rt_raw_channel_open(name, flags); + if (ch) + { + rt_memset(d->fnode, 0, sizeof(struct dfs_fnode)); + rt_list_init(&d->fnode->list); + d->fnode->type = FT_USER; + d->fnode->path = NULL; + d->fnode->fullpath = NULL; + + d->fnode->fops = &channel_fops; + + d->flags = O_RDWR; /* set flags as read and write */ + d->fnode->size = 0; + d->pos = 0; + d->fnode->ref_count = 1; + + /* set socket to the data of dfs_fd */ + d->fnode->data = (void *)ch; + } + else + { + rt_free(d->fnode); + _chfd_free(fd, fdt_type); + fd = -1; + } +quit: + return fd; +} + +static rt_channel_t fd_2_channel(int fdt_type, int fd) +{ + struct dfs_fd *d; + + d = lwp_fd_get(fdt_type, fd); + if (d) + { + rt_channel_t ch; + + ch = (rt_channel_t)d->fnode->data; + if (ch) + { + return ch; + } + } + return RT_NULL; +} + +rt_err_t lwp_channel_close(int fdt_type, int fd) +{ + rt_channel_t ch; + struct dfs_fd *d; + + d = lwp_fd_get(fdt_type, fd); + if (!d) + { + return -RT_EIO; + } + + if (!d->fnode) + { + return -RT_EIO; + } + + ch = fd_2_channel(fdt_type, fd); + rt_free(d->fnode); + if (!ch) + { + return -RT_EIO; + } + _chfd_free(fd, fdt_type); + + return rt_raw_channel_close(ch); +} + +rt_err_t lwp_channel_send(int fdt_type, int fd, rt_channel_msg_t data) +{ + rt_channel_t ch; + ch = fd_2_channel(fdt_type, fd); + if (ch) + { + return rt_raw_channel_send(ch, data); + } + return -RT_EIO; +} + +rt_err_t lwp_channel_send_recv_timeout(int fdt_type, int fd, rt_channel_msg_t data, rt_channel_msg_t data_ret, rt_int32_t time) +{ + rt_channel_t ch; + ch = fd_2_channel(fdt_type, fd); + if (ch) + { + return rt_raw_channel_send_recv_timeout(ch, data, data_ret, time); + } + return -RT_EIO; +} + +rt_err_t lwp_channel_reply(int fdt_type, int fd, rt_channel_msg_t data) +{ + rt_channel_t ch; + ch = fd_2_channel(fdt_type, fd); + if (ch) + { + return rt_raw_channel_reply(ch, data); + } + return -RT_EIO; +} + +rt_err_t lwp_channel_recv_timeout(int fdt_type, int fd, rt_channel_msg_t data, rt_int32_t time) +{ + rt_channel_t ch; + ch = fd_2_channel(fdt_type, fd); + if (ch) + { + return rt_raw_channel_recv_timeout(ch, data, time); + } + return -RT_EIO; +} + +int rt_channel_open(const char *name, int flags) +{ + return lwp_channel_open(FDT_TYPE_KERNEL, name, flags); +} + +rt_err_t rt_channel_close(int fd) +{ + return lwp_channel_close(FDT_TYPE_KERNEL, fd); +} + +rt_err_t rt_channel_send(int fd, rt_channel_msg_t data) +{ + return lwp_channel_send(FDT_TYPE_KERNEL, fd, data); +} + +rt_err_t rt_channel_send_recv_timeout(int fd, rt_channel_msg_t data, rt_channel_msg_t data_ret, rt_int32_t time) +{ + return lwp_channel_send_recv_timeout(FDT_TYPE_KERNEL, fd, data, data_ret, time); +} + +rt_err_t rt_channel_send_recv(int fd, rt_channel_msg_t data, rt_channel_msg_t data_ret) +{ + return lwp_channel_send_recv_timeout(FDT_TYPE_KERNEL, fd, data, data_ret, RT_WAITING_FOREVER); +} + +rt_err_t rt_channel_reply(int fd, rt_channel_msg_t data) +{ + return lwp_channel_reply(FDT_TYPE_KERNEL, fd, data); +} + +rt_err_t rt_channel_recv_timeout(int fd, rt_channel_msg_t data, rt_int32_t time) +{ + return lwp_channel_recv_timeout(FDT_TYPE_KERNEL, fd, data, time); +} + +rt_err_t rt_channel_recv(int fd, rt_channel_msg_t data) +{ + return lwp_channel_recv_timeout(FDT_TYPE_KERNEL, fd, data, RT_WAITING_FOREVER); +} + +rt_err_t rt_channel_peek(int fd, rt_channel_msg_t data) +{ + return lwp_channel_recv_timeout(FDT_TYPE_KERNEL, fd, data, 0); +} + +#ifdef RT_USING_FINSH +static int list_channel(void) +{ + rt_base_t level; + rt_channel_t *channels; + rt_ubase_t index, count; + struct rt_object *object; + struct rt_list_node *node; + struct rt_object_information *information; + + const char* stat_strs[] = {"idle", "wait", "active"}; + + information = rt_object_get_information(RT_Object_Class_Channel); + RT_ASSERT(information != RT_NULL); + + count = 0; + level = rt_hw_interrupt_disable(); + /* get the count of IPC channels */ + for (node = information->object_list.next; + node != &(information->object_list); + node = node->next) + { + count ++; + } + rt_hw_interrupt_enable(level); + + if (count == 0) return 0; + + channels = (rt_channel_t *) rt_calloc(count, sizeof(rt_channel_t)); + if (channels == RT_NULL) return 0; /* out of memory */ + + index = 0; + level = rt_hw_interrupt_disable(); + /* retrieve pointer of IPC channels */ + for (node = information->object_list.next; + node != &(information->object_list); + node = node->next) + { + object = rt_list_entry(node, struct rt_object, list); + + channels[index] = (rt_channel_t)object; + index ++; + } + rt_hw_interrupt_enable(level); + + rt_kprintf(" channel state\n"); + rt_kprintf("-------- -------\n"); + for (index = 0; index < count; index ++) + { + if (channels[index] != RT_NULL) + { + rt_kprintf("%-*.s", RT_NAME_MAX, channels[index]->parent.parent.name); + if (channels[index]->stat < 3) + rt_kprintf(" %s\n", stat_strs[channels[index]->stat]); + } + } + + rt_free(channels); + + return 0; +} +MSH_CMD_EXPORT(list_channel, list IPC channel information); +#endif + diff --git a/components/lwp/lwp_ipc.h b/components/lwp/lwp_ipc.h new file mode 100644 index 0000000000000000000000000000000000000000..adfe906914823c82d5e788a2490495d0d7455737 --- /dev/null +++ b/components/lwp/lwp_ipc.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-12 Jesven first version + */ + +#ifndef LWP_IPC_H__ +#define LWP_IPC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +enum +{ + RT_CHANNEL_RAW, + RT_CHANNEL_BUFFER +}; + +struct rt_channel_msg +{ + void *sender; + int type; + union + { + struct chbuf + { + void *buf; + size_t length; + } b; + void* d; + } u; +}; +typedef struct rt_channel_msg *rt_channel_msg_t; + +int rt_channel_open(const char *name, int flags); +rt_err_t rt_channel_close(int fd); +rt_err_t rt_channel_send(int fd, rt_channel_msg_t data); +rt_err_t rt_channel_send_recv(int fd, rt_channel_msg_t data, rt_channel_msg_t data_ret); +rt_err_t rt_channel_send_recv_timeout(int fd, rt_channel_msg_t data, rt_channel_msg_t data_ret, rt_int32_t time); +rt_err_t rt_channel_reply(int fd, rt_channel_msg_t data); +rt_err_t rt_channel_recv(int fd, rt_channel_msg_t data); +rt_err_t rt_channel_recv_timeout(int fd, rt_channel_msg_t data, rt_int32_t time); +rt_err_t rt_channel_peek(int fd, rt_channel_msg_t data); + +rt_channel_t rt_raw_channel_open(const char *name, int flags); +rt_err_t rt_raw_channel_close(rt_channel_t ch); +rt_err_t rt_raw_channel_send(rt_channel_t ch, rt_channel_msg_t data); +rt_err_t rt_raw_channel_send_recv(rt_channel_t ch, rt_channel_msg_t data, rt_channel_msg_t data_ret); +rt_err_t rt_raw_channel_send_recv_timeout(rt_channel_t ch, rt_channel_msg_t data, rt_channel_msg_t data_ret, rt_int32_t time); +rt_err_t rt_raw_channel_reply(rt_channel_t ch, rt_channel_msg_t data); +rt_err_t rt_raw_channel_recv(rt_channel_t ch, rt_channel_msg_t data); +rt_err_t rt_raw_channel_recv_timeout(rt_channel_t ch, rt_channel_msg_t data, rt_int32_t time); +rt_err_t rt_raw_channel_peek(rt_channel_t ch, rt_channel_msg_t data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/lwp/lwp_ipc_internal.h b/components/lwp/lwp_ipc_internal.h new file mode 100644 index 0000000000000000000000000000000000000000..1efa7a1c0284fd489a2540a244937063680b81d3 --- /dev/null +++ b/components/lwp/lwp_ipc_internal.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-16 Jesven first version + */ +#ifndef LWP_IPC_INTERNAL_H__ +#define LWP_IPC_INTERNAL_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum +{ + FDT_TYPE_LWP, + FDT_TYPE_KERNEL +}; + +int lwp_channel_open(int fdt_type, const char *name, int flags); +rt_err_t lwp_channel_close(int fdt_type, int fd); +rt_err_t lwp_channel_send(int fdt_type, int fd, rt_channel_msg_t data); +rt_err_t lwp_channel_send_recv_timeout(int fdt_type, int fd, rt_channel_msg_t data, rt_channel_msg_t data_ret, rt_int32_t time); +rt_err_t lwp_channel_reply(int fdt_type, int fd, rt_channel_msg_t data); +rt_err_t lwp_channel_recv_timeout(int fdt_type, int fd, rt_channel_msg_t data, rt_int32_t time); + +#ifdef __cplusplus +} +#endif + +#endif /* LWP_IPC_INTERNAL_H__*/ diff --git a/components/lwp/lwp_mem.c b/components/lwp/lwp_mem.c deleted file mode 100644 index 63fd5c89e1893ef32808c58c7e400fe8baab58c4..0000000000000000000000000000000000000000 --- a/components/lwp/lwp_mem.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-06-10 Bernard first version - */ - -#include -#include - -#define DBG_TAG "LWPMEM" -#define DBG_LVL DBG_WARNING -#include - -// todo: remove repleat code -#define RT_MEMHEAP_SIZE RT_ALIGN(sizeof(struct rt_lwp_memheap_item), RT_ALIGN_SIZE) -#define MEMITEM_SIZE(item) ((rt_uint32_t)item->next - (rt_uint32_t)item - RT_MEMHEAP_SIZE) - -#ifndef LWP_MEM_PAGE_SIZE - #define LWP_MEM_PAGE_SIZE (4 * 1024) -#endif - -#ifndef LWP_MEM_MAX_PAGE_COUNT - #define LWP_MEM_MAX_PAGE_COUNT (256 * 4) -#endif - -static void *rt_lwp_malloc_page(struct rt_lwp *lwp, rt_size_t npages) -{ - void *chunk; - char name[6]; - struct rt_lwp_memheap *lwp_heap; - rt_size_t page_cnt; - - RT_ASSERT(lwp != RT_NULL); - - page_cnt = lwp->heap_cnt + npages; - if (page_cnt > LWP_MEM_MAX_PAGE_COUNT) - { - dbg_log(DBG_ERROR, "alloc new page failed, lwp memory size out of limited: %d\n", page_cnt); - return RT_NULL; - } - - lwp_heap = rt_malloc(sizeof(struct rt_lwp_memheap)); - if (lwp_heap == RT_NULL) - { - dbg_log(DBG_ERROR, "alloc new page head failed, out of memory : %d\n", page_cnt); - return RT_NULL; - } - - chunk = rt_malloc(npages * LWP_MEM_PAGE_SIZE); - if (chunk == RT_NULL) - { - dbg_log(DBG_ERROR, "alloc new page buffer failed, out of memory : %d\n", page_cnt); - rt_free(lwp_heap); - return RT_NULL; - } - - dbg_log(DBG_LOG, "lwp alloc page: %d\n", npages); - - rt_sprintf(name, "lwp%02x", lwp->heap_cnt); - rt_lwp_memheap_init(lwp_heap, name, chunk, npages * LWP_MEM_PAGE_SIZE); - - rt_list_insert_before(&lwp->hlist, &lwp_heap->mlist); - - lwp->heap_cnt += npages; - - return chunk; -} - -static void rt_lwp_free_page(struct rt_lwp *lwp, struct rt_lwp_memheap *lwp_heap) -{ - rt_size_t npages; - - RT_ASSERT(lwp != RT_NULL); - RT_ASSERT(lwp_heap != RT_NULL); - RT_ASSERT(lwp_heap->start_addr != RT_NULL); - - npages = lwp_heap->pool_size / LWP_MEM_PAGE_SIZE; - lwp->heap_cnt -= npages; - - dbg_log(DBG_LOG, "lwp free page: %d\n", npages); - - rt_list_remove(&lwp_heap->mlist); - - rt_free(lwp_heap->start_addr); - rt_free(lwp_heap); -} - -void rt_lwp_mem_init(struct rt_lwp *lwp) -{ - RT_ASSERT(lwp != RT_NULL); - rt_list_init(&lwp->hlist); -} - -void rt_lwp_mem_deinit(struct rt_lwp *lwp) -{ - struct rt_list_node *node; - - RT_ASSERT(lwp != RT_NULL); - - node = lwp->hlist.next; - - while (node != &(lwp->hlist)) - { - struct rt_lwp_memheap *lwp_heap; - - lwp_heap = rt_list_entry(node, struct rt_lwp_memheap, mlist); - RT_ASSERT(lwp_heap != RT_NULL); - - /* update note before free page*/ - node = node->next; - - rt_lwp_free_page(lwp, lwp_heap); - } -} - -void *rt_lwp_mem_malloc(rt_uint32_t size) -{ - struct rt_lwp *lwp; - struct rt_list_node *node; - void *addr = RT_NULL; - rt_uint32_t npages; - - if (size == 0) - return RT_NULL; - - lwp = rt_lwp_self(); - RT_ASSERT(lwp != RT_NULL); - - for (node = lwp->hlist.next; node != &(lwp->hlist); node = node->next) - { - struct rt_lwp_memheap *lwp_heap; - lwp_heap = rt_list_entry(node, struct rt_lwp_memheap, mlist); - - addr = rt_lwp_memheap_alloc(lwp_heap, size); - if (addr != RT_NULL) - { - dbg_log(DBG_LOG, "lwp alloc 0x%x/%d\n", addr, size); - return addr; - } - } - - npages = (size + rt_lwp_memheap_unavailable_size_get() + LWP_MEM_PAGE_SIZE) / LWP_MEM_PAGE_SIZE; - if (RT_NULL != rt_lwp_malloc_page(lwp, npages)) - return rt_lwp_mem_malloc(size); - else - return RT_NULL; -} - -void rt_lwp_mem_free(void *addr) -{ - struct rt_lwp_memheap_item *header_ptr; - struct rt_lwp_memheap *lwp_heap; - - if (addr == RT_NULL) - return ; - - /* get memory item */ - header_ptr = (struct rt_lwp_memheap_item *)((rt_uint8_t *)addr - RT_MEMHEAP_SIZE); - RT_ASSERT(header_ptr); - - lwp_heap = header_ptr->pool_ptr; - RT_ASSERT(lwp_heap); - - dbg_log(DBG_LOG, "lwp free 0x%x\n", addr); - rt_lwp_memheap_free((void *)addr); - - if (rt_lwp_memheap_is_empty(lwp_heap)) - { - rt_lwp_free_page(rt_lwp_self(), lwp_heap); - } -} - -void *rt_lwp_mem_realloc(void *rmem, rt_size_t newsize) -{ - void *new_ptr; - struct rt_lwp_memheap_item *header_ptr; - - if (rmem == RT_NULL) - return rt_lwp_mem_malloc(newsize); - - if (newsize == 0) - { - rt_lwp_mem_free(rmem); - return RT_NULL; - } - - /* get old memory item */ - header_ptr = (struct rt_lwp_memheap_item *) - ((rt_uint8_t *)rmem - RT_MEMHEAP_SIZE); - - new_ptr = rt_lwp_memheap_realloc(header_ptr->pool_ptr, rmem, newsize); - if (new_ptr == RT_NULL) - { - /* allocate memory block from other memheap */ - new_ptr = rt_lwp_mem_malloc(newsize); - if (new_ptr != RT_NULL && rmem != RT_NULL) - { - rt_size_t oldsize; - - /* get the size of old memory block */ - oldsize = MEMITEM_SIZE(header_ptr); - if (newsize > oldsize) - rt_memcpy(new_ptr, rmem, oldsize); - else - rt_memcpy(new_ptr, rmem, newsize); - - dbg_log(DBG_LOG, "lwp realloc with memcpy 0x%x -> 0x%x/%d\n", rmem, new_ptr, newsize); - rt_lwp_mem_free(rmem); - - } - } - - dbg_log(DBG_LOG, "lwp realloc in same address 0x%x/%d\n", rmem, newsize); - - return new_ptr; -} diff --git a/components/lwp/lwp_memheap.c b/components/lwp/lwp_memheap.c deleted file mode 100644 index 7d512a503f2bc471e7948653c3bb0eea8a987c3c..0000000000000000000000000000000000000000 --- a/components/lwp/lwp_memheap.c +++ /dev/null @@ -1,576 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-04-10 Bernard first implementation - * 2012-10-16 Bernard add the mutex lock for heap object. - * 2012-12-29 Bernard memheap can be used as system heap. - * change mutex lock to semaphore lock. - * 2013-04-10 Bernard add rt_lwp_memheap_realloc function. - * 2013-05-24 Bernard fix the rt_lwp_memheap_realloc issue. - * 2013-07-11 Grissiom fix the memory block splitting issue. - * 2013-07-15 Grissiom optimize rt_lwp_memheap_realloc - */ - -#include -#include -#include - -/* dynamic pool magic and mask */ -#define RT_MEMHEAP_MAGIC 0x1ea01ea0 -#define RT_MEMHEAP_MASK 0xfffffffe -#define RT_MEMHEAP_USED 0x01 -#define RT_MEMHEAP_FREED 0x00 - -#define RT_MEMHEAP_IS_USED(i) ((i)->magic & RT_MEMHEAP_USED) -#define RT_MEMHEAP_MINIALLOC 12 - -#define RT_MEMHEAP_SIZE RT_ALIGN(sizeof(struct rt_lwp_memheap_item), RT_ALIGN_SIZE) -#define MEMITEM_SIZE(item) ((rt_uint32_t)item->next - (rt_uint32_t)item - RT_MEMHEAP_SIZE) - -/* - * The initialized memory pool will be: - * +-----------------------------------+--------------------------+ - * | whole freed memory block | Used Memory Block Tailer | - * +-----------------------------------+--------------------------+ - * - * block_list --> whole freed memory block - * - * The length of Used Memory Block Tailer is 0, - * which is prevents block merging across list - */ -rt_err_t rt_lwp_memheap_init(struct rt_lwp_memheap *memheap, - const char *name, - void *start_addr, - rt_uint32_t size) -{ - struct rt_lwp_memheap_item *item; - - RT_ASSERT(memheap != RT_NULL); - - /* initialize pool object */ - memheap->start_addr = start_addr; - memheap->pool_size = RT_ALIGN_DOWN(size, RT_ALIGN_SIZE); - memheap->available_size = memheap->pool_size - (2 * RT_MEMHEAP_SIZE); - memheap->max_used_size = memheap->pool_size - memheap->available_size; - - /* initialize the free list header */ - item = &(memheap->free_header); - item->magic = RT_MEMHEAP_MAGIC; - item->pool_ptr = memheap; - item->next = RT_NULL; - item->prev = RT_NULL; - item->next_free = item; - item->prev_free = item; - - /* set the free list to free list header */ - memheap->free_list = item; - - /* initialize the first big memory block */ - item = (struct rt_lwp_memheap_item *)start_addr; - item->magic = RT_MEMHEAP_MAGIC; - item->pool_ptr = memheap; - item->next = RT_NULL; - item->prev = RT_NULL; - item->next_free = item; - item->prev_free = item; - - item->next = (struct rt_lwp_memheap_item *) - ((rt_uint8_t *)item + memheap->available_size + RT_MEMHEAP_SIZE); - item->prev = item->next; - - /* block list header */ - memheap->block_list = item; - - /* place the big memory block to free list */ - item->next_free = memheap->free_list->next_free; - item->prev_free = memheap->free_list; - memheap->free_list->next_free->prev_free = item; - memheap->free_list->next_free = item; - - /* move to the end of memory pool to build a small tailer block, - * which prevents block merging - */ - item = item->next; - /* it's a used memory block */ - item->magic = RT_MEMHEAP_MAGIC | RT_MEMHEAP_USED; - item->pool_ptr = memheap; - item->next = (struct rt_lwp_memheap_item *)start_addr; - item->prev = (struct rt_lwp_memheap_item *)start_addr; - /* not in free list */ - item->next_free = item->prev_free = RT_NULL; - - /* initialize semaphore lock */ - rt_sem_init(&(memheap->lock), name, 1, RT_IPC_FLAG_FIFO); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("memory heap: start addr 0x%08x, size %d, free list header 0x%08x\n", - start_addr, size, &(memheap->free_header))); - - return RT_EOK; -} - -void *rt_lwp_memheap_alloc(struct rt_lwp_memheap *heap, rt_uint32_t size) -{ - rt_err_t result; - rt_uint32_t free_size; - struct rt_lwp_memheap_item *header_ptr; - - RT_ASSERT(heap != RT_NULL); - - /* align allocated size */ - size = RT_ALIGN(size, RT_ALIGN_SIZE); - if (size < RT_MEMHEAP_MINIALLOC) - size = RT_MEMHEAP_MINIALLOC; - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("allocate %d on heap:%8.*s", - size, RT_NAME_MAX, heap->parent.name)); - - if (size < heap->available_size) - { - /* search on free list */ - free_size = 0; - - /* lock memheap */ - result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); - if (result != RT_EOK) - { - rt_set_errno(result); - - return RT_NULL; - } - - /* get the first free memory block */ - header_ptr = heap->free_list->next_free; - while (header_ptr != heap->free_list && free_size < size) - { - /* get current freed memory block size */ - free_size = MEMITEM_SIZE(header_ptr); - if (free_size < size) - { - /* move to next free memory block */ - header_ptr = header_ptr->next_free; - } - } - - /* determine if the memory is available. */ - if (free_size >= size) - { - /* a block that satisfies the request has been found. */ - - /* determine if the block needs to be split. */ - if (free_size >= (size + RT_MEMHEAP_SIZE + RT_MEMHEAP_MINIALLOC)) - { - struct rt_lwp_memheap_item *new_ptr; - - /* split the block. */ - new_ptr = (struct rt_lwp_memheap_item *) - (((rt_uint8_t *)header_ptr) + size + RT_MEMHEAP_SIZE); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("split: block[0x%08x] nextm[0x%08x] prevm[0x%08x] to new[0x%08x]\n", - header_ptr, - header_ptr->next, - header_ptr->prev, - new_ptr)); - - /* mark the new block as a memory block and freed. */ - new_ptr->magic = RT_MEMHEAP_MAGIC; - - /* put the pool pointer into the new block. */ - new_ptr->pool_ptr = heap; - - /* break down the block list */ - new_ptr->prev = header_ptr; - new_ptr->next = header_ptr->next; - header_ptr->next->prev = new_ptr; - header_ptr->next = new_ptr; - - /* remove header ptr from free list */ - header_ptr->next_free->prev_free = header_ptr->prev_free; - header_ptr->prev_free->next_free = header_ptr->next_free; - header_ptr->next_free = RT_NULL; - header_ptr->prev_free = RT_NULL; - - /* insert new_ptr to free list */ - new_ptr->next_free = heap->free_list->next_free; - new_ptr->prev_free = heap->free_list; - heap->free_list->next_free->prev_free = new_ptr; - heap->free_list->next_free = new_ptr; - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("new ptr: next_free 0x%08x, prev_free 0x%08x\n", - new_ptr->next_free, - new_ptr->prev_free)); - - /* decrement the available byte count. */ - heap->available_size = heap->available_size - - size - - RT_MEMHEAP_SIZE; - if (heap->pool_size - heap->available_size > heap->max_used_size) - heap->max_used_size = heap->pool_size - heap->available_size; - } - else - { - /* decrement the entire free size from the available bytes count. */ - heap->available_size = heap->available_size - free_size; - if (heap->pool_size - heap->available_size > heap->max_used_size) - heap->max_used_size = heap->pool_size - heap->available_size; - - /* remove header_ptr from free list */ - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("one block: block[0x%08x], next_free 0x%08x, prev_free 0x%08x\n", - header_ptr, - header_ptr->next_free, - header_ptr->prev_free)); - - header_ptr->next_free->prev_free = header_ptr->prev_free; - header_ptr->prev_free->next_free = header_ptr->next_free; - header_ptr->next_free = RT_NULL; - header_ptr->prev_free = RT_NULL; - } - - /* Mark the allocated block as not available. */ - header_ptr->magic |= RT_MEMHEAP_USED; - - /* release lock */ - rt_sem_release(&(heap->lock)); - - /* Return a memory address to the caller. */ - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("alloc mem: memory[0x%08x], heap[0x%08x], size: %d\n", - (void *)((rt_uint8_t *)header_ptr + RT_MEMHEAP_SIZE), - header_ptr, - size)); - - return (void *)((rt_uint8_t *)header_ptr + RT_MEMHEAP_SIZE); - } - - /* release lock */ - rt_sem_release(&(heap->lock)); - } - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("allocate memory: failed\n")); - - /* Return the completion status. */ - return RT_NULL; -} - -void *rt_lwp_memheap_realloc(struct rt_lwp_memheap *heap, void *ptr, rt_size_t newsize) -{ - rt_err_t result; - rt_size_t oldsize; - struct rt_lwp_memheap_item *header_ptr; - struct rt_lwp_memheap_item *new_ptr; - - if (newsize == 0) - { - rt_lwp_memheap_free(ptr); - - return RT_NULL; - } - /* align allocated size */ - newsize = RT_ALIGN(newsize, RT_ALIGN_SIZE); - if (newsize < RT_MEMHEAP_MINIALLOC) - newsize = RT_MEMHEAP_MINIALLOC; - - if (ptr == RT_NULL) - { - return rt_lwp_memheap_alloc(heap, newsize); - } - - /* get memory block header and get the size of memory block */ - header_ptr = (struct rt_lwp_memheap_item *) - ((rt_uint8_t *)ptr - RT_MEMHEAP_SIZE); - oldsize = MEMITEM_SIZE(header_ptr); - /* re-allocate memory */ - if (newsize > oldsize) - { - void *new_ptr; - struct rt_lwp_memheap_item *next_ptr; - - /* lock memheap */ - result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); - if (result != RT_EOK) - { - rt_set_errno(result); - return RT_NULL; - } - - next_ptr = header_ptr->next; - - /* header_ptr should not be the tail */ - RT_ASSERT(next_ptr > header_ptr); - - /* check whether the following free space is enough to expand */ - if (!RT_MEMHEAP_IS_USED(next_ptr)) - { - rt_int32_t nextsize; - - nextsize = MEMITEM_SIZE(next_ptr); - RT_ASSERT(next_ptr > 0); - - /* Here is the ASCII art of the situation that we can make use of - * the next free node without alloc/memcpy, |*| is the control - * block: - * - * oldsize free node - * |*|-----------|*|----------------------|*| - * newsize >= minialloc - * |*|----------------|*|-----------------|*| - */ - if (nextsize + oldsize > newsize + RT_MEMHEAP_MINIALLOC) - { - /* decrement the entire free size from the available bytes count. */ - heap->available_size = heap->available_size - (newsize - oldsize); - if (heap->pool_size - heap->available_size > heap->max_used_size) - heap->max_used_size = heap->pool_size - heap->available_size; - - /* remove next_ptr from free list */ - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("remove block: block[0x%08x], next_free 0x%08x, prev_free 0x%08x", - next_ptr, - next_ptr->next_free, - next_ptr->prev_free)); - - next_ptr->next_free->prev_free = next_ptr->prev_free; - next_ptr->prev_free->next_free = next_ptr->next_free; - next_ptr->next->prev = next_ptr->prev; - next_ptr->prev->next = next_ptr->next; - - /* build a new one on the right place */ - next_ptr = (struct rt_lwp_memheap_item *)((char *)ptr + newsize); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("new free block: block[0x%08x] nextm[0x%08x] prevm[0x%08x]", - next_ptr, - next_ptr->next, - next_ptr->prev)); - - /* mark the new block as a memory block and freed. */ - next_ptr->magic = RT_MEMHEAP_MAGIC; - - /* put the pool pointer into the new block. */ - next_ptr->pool_ptr = heap; - - next_ptr->prev = header_ptr; - next_ptr->next = header_ptr->next; - header_ptr->next->prev = next_ptr; - header_ptr->next = next_ptr; - - /* insert next_ptr to free list */ - next_ptr->next_free = heap->free_list->next_free; - next_ptr->prev_free = heap->free_list; - heap->free_list->next_free->prev_free = next_ptr; - heap->free_list->next_free = next_ptr; - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("new ptr: next_free 0x%08x, prev_free 0x%08x", - next_ptr->next_free, - next_ptr->prev_free)); - - /* release lock */ - rt_sem_release(&(heap->lock)); - - return ptr; - } - } - - /* release lock */ - rt_sem_release(&(heap->lock)); - - /* re-allocate a memory block */ - new_ptr = (void *)rt_lwp_memheap_alloc(heap, newsize); - if (new_ptr != RT_NULL) - { - rt_memcpy(new_ptr, ptr, oldsize < newsize ? oldsize : newsize); - rt_lwp_memheap_free(ptr); - } - - return new_ptr; - } - - /* don't split when there is less than one node space left */ - if (newsize + RT_MEMHEAP_SIZE + RT_MEMHEAP_MINIALLOC >= oldsize) - return ptr; - - /* lock memheap */ - result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); - if (result != RT_EOK) - { - rt_set_errno(result); - - return RT_NULL; - } - - /* split the block. */ - new_ptr = (struct rt_lwp_memheap_item *) - (((rt_uint8_t *)header_ptr) + newsize + RT_MEMHEAP_SIZE); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("split: block[0x%08x] nextm[0x%08x] prevm[0x%08x] to new[0x%08x]\n", - header_ptr, - header_ptr->next, - header_ptr->prev, - new_ptr)); - - /* mark the new block as a memory block and freed. */ - new_ptr->magic = RT_MEMHEAP_MAGIC; - /* put the pool pointer into the new block. */ - new_ptr->pool_ptr = heap; - - /* break down the block list */ - new_ptr->prev = header_ptr; - new_ptr->next = header_ptr->next; - header_ptr->next->prev = new_ptr; - header_ptr->next = new_ptr; - - /* determine if the block can be merged with the next neighbor. */ - if (!RT_MEMHEAP_IS_USED(new_ptr->next)) - { - struct rt_lwp_memheap_item *free_ptr; - - /* merge block with next neighbor. */ - free_ptr = new_ptr->next; - heap->available_size = heap->available_size - MEMITEM_SIZE(free_ptr); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("merge: right node 0x%08x, next_free 0x%08x, prev_free 0x%08x\n", - header_ptr, header_ptr->next_free, header_ptr->prev_free)); - - free_ptr->next->prev = new_ptr; - new_ptr->next = free_ptr->next; - - /* remove free ptr from free list */ - free_ptr->next_free->prev_free = free_ptr->prev_free; - free_ptr->prev_free->next_free = free_ptr->next_free; - } - - /* insert the split block to free list */ - new_ptr->next_free = heap->free_list->next_free; - new_ptr->prev_free = heap->free_list; - heap->free_list->next_free->prev_free = new_ptr; - heap->free_list->next_free = new_ptr; - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("new free ptr: next_free 0x%08x, prev_free 0x%08x\n", - new_ptr->next_free, - new_ptr->prev_free)); - - /* increment the available byte count. */ - heap->available_size = heap->available_size + MEMITEM_SIZE(new_ptr); - - /* release lock */ - rt_sem_release(&(heap->lock)); - - /* return the old memory block */ - return ptr; -} - -void rt_lwp_memheap_free(void *ptr) -{ - rt_err_t result; - struct rt_lwp_memheap *heap; - struct rt_lwp_memheap_item *header_ptr, *new_ptr; - rt_uint32_t insert_header; - - /* NULL check */ - if (ptr == RT_NULL) return; - - /* set initial status as OK */ - insert_header = 1; - new_ptr = RT_NULL; - header_ptr = (struct rt_lwp_memheap_item *) - ((rt_uint8_t *)ptr - RT_MEMHEAP_SIZE); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("free memory: memory[0x%08x], block[0x%08x]\n", - ptr, header_ptr)); - - /* check magic */ - RT_ASSERT((header_ptr->magic & RT_MEMHEAP_MASK) == RT_MEMHEAP_MAGIC); - RT_ASSERT(header_ptr->magic & RT_MEMHEAP_USED); - /* check whether this block of memory has been over-written. */ - RT_ASSERT((header_ptr->next->magic & RT_MEMHEAP_MASK) == RT_MEMHEAP_MAGIC); - - /* get pool ptr */ - heap = header_ptr->pool_ptr; - - /* lock memheap */ - result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); - if (result != RT_EOK) - { - rt_set_errno(result); - - return ; - } - - /* Mark the memory as available. */ - header_ptr->magic &= ~RT_MEMHEAP_USED; - /* Adjust the available number of bytes. */ - heap->available_size = heap->available_size + MEMITEM_SIZE(header_ptr); - - /* Determine if the block can be merged with the previous neighbor. */ - if (!RT_MEMHEAP_IS_USED(header_ptr->prev)) - { - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("merge: left node 0x%08x\n", - header_ptr->prev)); - - /* adjust the available number of bytes. */ - heap->available_size = heap->available_size + RT_MEMHEAP_SIZE; - - /* yes, merge block with previous neighbor. */ - (header_ptr->prev)->next = header_ptr->next; - (header_ptr->next)->prev = header_ptr->prev; - - /* move header pointer to previous. */ - header_ptr = header_ptr->prev; - /* don't insert header to free list */ - insert_header = 0; - } - - /* determine if the block can be merged with the next neighbor. */ - if (!RT_MEMHEAP_IS_USED(header_ptr->next)) - { - /* adjust the available number of bytes. */ - heap->available_size = heap->available_size + RT_MEMHEAP_SIZE; - - /* merge block with next neighbor. */ - new_ptr = header_ptr->next; - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("merge: right node 0x%08x, next_free 0x%08x, prev_free 0x%08x\n", - new_ptr, new_ptr->next_free, new_ptr->prev_free)); - - new_ptr->next->prev = header_ptr; - header_ptr->next = new_ptr->next; - - /* remove new ptr from free list */ - new_ptr->next_free->prev_free = new_ptr->prev_free; - new_ptr->prev_free->next_free = new_ptr->next_free; - } - - if (insert_header) - { - /* no left merge, insert to free list */ - header_ptr->next_free = heap->free_list->next_free; - header_ptr->prev_free = heap->free_list; - heap->free_list->next_free->prev_free = header_ptr; - heap->free_list->next_free = header_ptr; - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("insert to free list: next_free 0x%08x, prev_free 0x%08x\n", - header_ptr->next_free, header_ptr->prev_free)); - } - - /* release lock */ - rt_sem_release(&(heap->lock)); -} - -rt_bool_t rt_lwp_memheap_is_empty(struct rt_lwp_memheap *memheap) -{ - RT_ASSERT(memheap != RT_NULL); - - return (memheap->available_size + 2 * sizeof(struct rt_lwp_memheap_item)) == memheap->pool_size; -} - -rt_bool_t rt_lwp_memheap_unavailable_size_get(void) -{ - return 2 * RT_MEMHEAP_SIZE + 3; -} diff --git a/components/lwp/lwp_memheap.h b/components/lwp/lwp_memheap.h deleted file mode 100644 index d0c09dfd01740abd1a48130fecaf6a1ca3e1f683..0000000000000000000000000000000000000000 --- a/components/lwp/lwp_memheap.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-06-10 Bernard first version - */ - -#ifndef __LWP_MEMHEAP_H__ -#define __LWP_MEMHEAP_H__ - -#include -#include - -/** - * memory item on the heap - */ -struct rt_lwp_memheap_item -{ - rt_uint32_t magic; /**< magic number for memheap */ - struct rt_lwp_memheap *pool_ptr; /**< point of pool */ - - struct rt_lwp_memheap_item *next; /**< next memheap item */ - struct rt_lwp_memheap_item *prev; /**< prev memheap item */ - - struct rt_lwp_memheap_item *next_free; /**< next free memheap item */ - struct rt_lwp_memheap_item *prev_free; /**< prev free memheap item */ -}; - -/** - * Base structure of memory heap object - */ -struct rt_lwp_memheap -{ - struct rt_object parent; /**< inherit from rt_object */ - - void *start_addr; /**< pool start address and size */ - - rt_uint32_t pool_size; /**< pool size */ - rt_uint32_t available_size; /**< available size */ - rt_uint32_t max_used_size; /**< maximum allocated size */ - - struct rt_lwp_memheap_item *block_list; /**< used block list */ - struct rt_lwp_memheap_item *free_list; /**< free block list */ - struct rt_lwp_memheap_item free_header; /**< free block list header */ - - struct rt_semaphore lock; /**< semaphore lock */ - - rt_list_t mlist; -}; - -extern rt_err_t rt_lwp_memheap_init(struct rt_lwp_memheap *memheap, const char *name, void *start_addr, rt_uint32_t size); -extern void *rt_lwp_memheap_alloc(struct rt_lwp_memheap *heap, rt_uint32_t size); -extern void rt_lwp_memheap_free(void *ptr); -extern void *rt_lwp_memheap_realloc(struct rt_lwp_memheap *heap, void *ptr, rt_size_t newsize); -extern rt_bool_t rt_lwp_memheap_is_empty(struct rt_lwp_memheap *memheap); -extern rt_bool_t rt_lwp_memheap_unavailable_size_get(void); - -#endif diff --git a/components/lwp/lwp_mm_area.c b/components/lwp/lwp_mm_area.c new file mode 100644 index 0000000000000000000000000000000000000000..08ecf0684ad48b89e7ccc6f40eac5d62cdf4c93d --- /dev/null +++ b/components/lwp/lwp_mm_area.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-28 Jesven first version + */ +#include + +#ifdef RT_USING_USERSPACE +#include + +int lwp_map_area_insert(struct lwp_avl_struct **avl_tree, size_t addr, size_t size, int ma_type) +{ + struct lwp_avl_struct *node = RT_NULL; + struct rt_mm_area_struct *ma = RT_NULL; + + if (!size) + { + return -1; + } + ma = (struct rt_mm_area_struct *)rt_malloc(sizeof(struct rt_mm_area_struct)); + if (!ma) + { + return -1; + } + ma->addr = addr; + ma->size = size; + ma->type = ma_type; + + node = (struct lwp_avl_struct *)rt_malloc(sizeof(struct lwp_avl_struct)); + if (!node) + { + rt_free(ma); + return -1; + } + memset(node, 0, sizeof(struct lwp_avl_struct)); + + node->avl_key = ma->addr; + node->data = (void *)ma; + lwp_avl_insert(node, avl_tree); + return 0; +} + +void lwp_map_area_remove(struct lwp_avl_struct **avl_tree, size_t addr) +{ + struct lwp_avl_struct *node = RT_NULL; + + node = lwp_avl_find(addr, *avl_tree); + if (!node) + { + return; + } + lwp_avl_remove(node, avl_tree); + rt_free(node->data); + rt_free(node); +} + +struct lwp_avl_struct* lwp_map_find(struct lwp_avl_struct* ptree, size_t addr) +{ + struct lwp_avl_struct *node = ptree; + + while (1) + { + if (!node) + { + return node; + } + if ((size_t)node->avl_key <= addr) + { + struct rt_mm_area_struct *ma = (struct rt_mm_area_struct *)node->data; + if ((ma->addr <= addr) && (addr < ma->addr + ma->size)) + { + /* find area */ + break; + } + node = node->avl_right; + } + else + { + node = node->avl_left; + } + } + return node; +} + +struct lwp_avl_struct* lwp_map_find_first(struct lwp_avl_struct* ptree) +{ + if (ptree == AVL_EMPTY) + { + return (struct lwp_avl_struct *)0; + } + while (1) + { + if (!ptree->avl_left) + { + break; + } + ptree = ptree->avl_left; + } + return ptree; +} + +int top_mem_fun(struct lwp_avl_struct* ptree, void *arg) +{ + size_t *vs = (size_t *)arg; + struct rt_mm_area_struct *ma; + + ma = (struct rt_mm_area_struct *)ptree->data; + *vs += ma->size; + return 0; +} + +size_t lwp_vmem_count(struct lwp_avl_struct *ptree) +{ + size_t vsize = 0; + lwp_avl_traversal(ptree, top_mem_fun, &vsize); + return vsize; +} +#endif diff --git a/components/lwp/lwp_mm_area.h b/components/lwp/lwp_mm_area.h new file mode 100644 index 0000000000000000000000000000000000000000..555a03ce48f6b7d90a7df60696f7daed02934ac5 --- /dev/null +++ b/components/lwp/lwp_mm_area.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-28 Jesven first version + */ +#ifndef __LWP_MM_AREA_H__ +#define __LWP_MM_AREA_H__ + +#include +#include + +#include + +#ifdef RT_USING_USERSPACE + +#ifdef __cplusplus +extern "C" { +#endif + +enum +{ + MM_AREA_TYPE_PHY = 0, /* mm_area physical address is IO register or reserved memory no cached*/ + MM_AREA_TYPE_PHY_CACHED, /* mm_area physical address is IO register or reserved memory with cached */ + MM_AREA_TYPE_SHM, /* mm_area physical address is shared memory */ + MM_AREA_TYPE_DATA, /* mm_area physical address is alloced from page manager for data */ + MM_AREA_TYPE_TEXT, /* mm_area physical address is alloced from page manager for text */ + MM_AREA_TYPE_UNKNOW, +}; + +struct rt_mm_area_struct +{ + size_t addr; + size_t size; + int type; +}; + +int lwp_map_area_insert(struct lwp_avl_struct **avl_tree, size_t addr, size_t size, int ma_type); +void lwp_map_area_remove(struct lwp_avl_struct **avl_tree, size_t addr); +struct lwp_avl_struct* lwp_map_find(struct lwp_avl_struct* ptree, size_t addr); +struct lwp_avl_struct* lwp_map_find_first(struct lwp_avl_struct* ptree); +size_t lwp_vmem_count(struct lwp_avl_struct *ptree); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /*__LWP_MM_AREA_H__*/ diff --git a/components/lwp/lwp_pid.c b/components/lwp/lwp_pid.c new file mode 100644 index 0000000000000000000000000000000000000000..6d635c7fdbceb2ffb792637e8665767204afafaa --- /dev/null +++ b/components/lwp/lwp_pid.c @@ -0,0 +1,1038 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-16 zhangjun first version + * 2021-02-20 lizhirui fix warning + */ + +#include +#include +#include + +#include "lwp.h" +#include "lwp_pid.h" +#include "tty.h" + +#ifdef RT_USING_USERSPACE +#include "lwp_user_mm.h" + +#ifdef RT_USING_GDBSERVER +#include +#include +#endif + +#endif + +#define DBG_TAG "LWP_PID" +#define DBG_LVL DBG_INFO +#include + +#define PID_MAX 10000 + +#define PID_CT_ASSERT(name, x) \ + struct assert_##name {char ary[2 * (x) - 1];} + +PID_CT_ASSERT(pid_min_nr, RT_LWP_MAX_NR > 1); +PID_CT_ASSERT(pid_max_nr, RT_LWP_MAX_NR < PID_MAX); + +static struct lwp_avl_struct lwp_pid_ary[RT_LWP_MAX_NR]; +static struct lwp_avl_struct *lwp_pid_free_head = RT_NULL; +static int lwp_pid_ary_alloced = 0; +static struct lwp_avl_struct *lwp_pid_root = RT_NULL; +static pid_t current_pid = 0; + +struct lwp_avl_struct *lwp_get_pid_ary(void) +{ + return lwp_pid_ary; +} + +static pid_t lwp_pid_get(void) +{ + rt_base_t level; + struct lwp_avl_struct *p; + pid_t pid = 0; + + level = rt_hw_interrupt_disable(); + p = lwp_pid_free_head; + if (p) + { + lwp_pid_free_head = (struct lwp_avl_struct *)p->avl_right; + } + else if (lwp_pid_ary_alloced < RT_LWP_MAX_NR) + { + p = lwp_pid_ary + lwp_pid_ary_alloced; + lwp_pid_ary_alloced++; + } + if (p) + { + int found_noused = 0; + + RT_ASSERT(p->data == RT_NULL); + for (pid = current_pid + 1; pid < PID_MAX; pid++) + { + if (!lwp_avl_find(pid, lwp_pid_root)) + { + found_noused = 1; + break; + } + } + if (!found_noused) + { + for (pid = 1; pid <= current_pid; pid++) + { + if (!lwp_avl_find(pid, lwp_pid_root)) + { + found_noused = 1; + break; + } + } + } + p->avl_key = pid; + lwp_avl_insert(p, &lwp_pid_root); + current_pid = pid; + } + rt_hw_interrupt_enable(level); + return pid; +} + +static void lwp_pid_put(pid_t pid) +{ + rt_base_t level; + struct lwp_avl_struct *p; + + level = rt_hw_interrupt_disable(); + p = lwp_avl_find(pid, lwp_pid_root); + if (p) + { + p->data = RT_NULL; + lwp_avl_remove(p, &lwp_pid_root); + p->avl_right = lwp_pid_free_head; + lwp_pid_free_head = p; + } + rt_hw_interrupt_enable(level); +} + +static void lwp_pid_set_lwp(pid_t pid, struct rt_lwp *lwp) +{ + rt_base_t level; + struct lwp_avl_struct *p; + + level = rt_hw_interrupt_disable(); + p = lwp_avl_find(pid, lwp_pid_root); + if (p) + { + p->data = lwp; + } + rt_hw_interrupt_enable(level); +} + +static void __exit_files(struct rt_lwp *lwp) +{ + int fd = lwp->fdt.maxfd - 1; + + while (fd >= 0) + { + struct dfs_fd *d; + + d = lwp->fdt.fds[fd]; + if (d) + { + dfs_file_close(d); + fdt_fd_release(&lwp->fdt, fd); + } + fd--; + } +} + +void lwp_user_object_lock_init(struct rt_lwp *lwp) +{ + rt_mutex_init(&lwp->object_mutex, "lwp_obj", RT_IPC_FLAG_PRIO); +} + +void lwp_user_object_lock_destroy(struct rt_lwp *lwp) +{ + rt_mutex_detach(&lwp->object_mutex); +} + +void lwp_user_object_lock(struct rt_lwp *lwp) +{ + if (lwp) + { + rt_mutex_take(&lwp->object_mutex, RT_WAITING_FOREVER); + } + else + { + RT_ASSERT(0); + } +} + +void lwp_user_object_unlock(struct rt_lwp *lwp) +{ + if (lwp) + { + rt_mutex_release(&lwp->object_mutex); + } + else + { + RT_ASSERT(0); + } +} + +int lwp_user_object_add(struct rt_lwp *lwp, rt_object_t object) +{ + int ret = -1; + + if (lwp && object) + { + lwp_user_object_lock(lwp); + if (!lwp_avl_find((avl_key_t)object, lwp->object_root)) + { + struct lwp_avl_struct *node; + + node = (struct lwp_avl_struct *)rt_malloc(sizeof(struct lwp_avl_struct)); + if (node) + { + rt_base_t level; + + level = rt_hw_interrupt_disable(); + object->lwp_ref_count++; + rt_hw_interrupt_enable(level); + node->avl_key = (avl_key_t)object; + lwp_avl_insert(node, &lwp->object_root); + ret = 0; + } + } + lwp_user_object_unlock(lwp); + } + return ret; +} + +static rt_err_t _object_node_delete(struct rt_lwp *lwp, struct lwp_avl_struct *node) +{ + rt_err_t ret = -1; + rt_object_t object; + + if (!lwp || !node) + { + return ret; + } + object = (rt_object_t)node->avl_key; + object->lwp_ref_count--; + if (object->lwp_ref_count == 0) + { + /* remove from kernel object list */ + switch (object->type) + { + case RT_Object_Class_Semaphore: + ret = rt_sem_delete((rt_sem_t)object); + break; + case RT_Object_Class_Mutex: + ret = rt_mutex_delete((rt_mutex_t)object); + break; + case RT_Object_Class_Event: + ret = rt_event_delete((rt_event_t)object); + break; + case RT_Object_Class_MailBox: + ret = rt_mb_delete((rt_mailbox_t)object); + break; + case RT_Object_Class_MessageQueue: + ret = rt_mq_delete((rt_mq_t)object); + break; + case RT_Object_Class_Timer: + ret = rt_timer_delete((rt_timer_t)object); + break; + case RT_Object_Class_Custom: + ret = rt_custom_object_destroy(object); + break; + default: + LOG_E("input object type(%d) error", object->type); + break; + } + } + else + { + ret = 0; + } + lwp_avl_remove(node, &lwp->object_root); + rt_free(node); + return ret; +} + +rt_err_t lwp_user_object_delete(struct rt_lwp *lwp, rt_object_t object) +{ + rt_err_t ret = -1; + + if (lwp && object) + { + struct lwp_avl_struct *node; + + lwp_user_object_lock(lwp); + node = lwp_avl_find((avl_key_t)object, lwp->object_root); + ret = _object_node_delete(lwp, node); + lwp_user_object_unlock(lwp); + } + return ret; +} + +void lwp_user_object_clear(struct rt_lwp *lwp) +{ + struct lwp_avl_struct *node; + + lwp_user_object_lock(lwp); + while ((node = lwp_map_find_first(lwp->object_root)) != RT_NULL) + { + _object_node_delete(lwp, node); + } + lwp_user_object_unlock(lwp); +} + +static int _object_dup(struct lwp_avl_struct *node, void *arg) +{ + rt_object_t object; + struct rt_lwp *dst_lwp = (struct rt_lwp *)arg; + + object = (rt_object_t)node->avl_key; + lwp_user_object_add(dst_lwp, object); + return 0; +} + +void lwp_user_object_dup(struct rt_lwp *dst_lwp, struct rt_lwp *src_lwp) +{ + lwp_user_object_lock(src_lwp); + lwp_avl_traversal(src_lwp->object_root, _object_dup, dst_lwp); + lwp_user_object_unlock(src_lwp); +} + +struct rt_lwp* lwp_new(void) +{ + pid_t pid; + rt_base_t level; + struct rt_lwp* lwp = RT_NULL; + + level = rt_hw_interrupt_disable(); + + pid = lwp_pid_get(); + if (pid == 0) + { + LOG_E("pid slot fulled!\n"); + goto out; + } + lwp = (struct rt_lwp *)rt_malloc(sizeof(struct rt_lwp)); + if (lwp == RT_NULL) + { + lwp_pid_put(pid); + LOG_E("no memory for lwp struct!\n"); + goto out; + } + rt_memset(lwp, 0, sizeof(*lwp)); + rt_list_init(&lwp->wait_list); + lwp->pid = pid; + lwp->leader = 0; + lwp->session = -1; + lwp->tty = RT_NULL; + //lwp->tgroup_leader = RT_NULL; + lwp_pid_set_lwp(pid, lwp); + rt_list_init(&lwp->t_grp); + lwp_user_object_lock_init(lwp); + lwp->address_search_head = RT_NULL; + rt_wqueue_init(&lwp->wait_queue); + + lwp->ref = 1; +out: + rt_hw_interrupt_enable(level); + return lwp; +} + +void lwp_free(struct rt_lwp* lwp) +{ + rt_base_t level; + + if (lwp == RT_NULL) + { + return; + } + + LOG_D("lwp free: %p\n", lwp); + + level = rt_hw_interrupt_disable(); + + lwp->finish = 1; + if (lwp->args != RT_NULL) + { +#ifndef ARCH_MM_MMU + lwp->args_length = RT_NULL; +#ifndef ARCH_MM_MPU + rt_free(lwp->args); +#endif /* not defined ARCH_MM_MPU */ +#endif /* ARCH_MM_MMU */ + lwp->args = RT_NULL; + } + + if (lwp->fdt.fds != RT_NULL) + { + /* auto clean fds */ + __exit_files(lwp); + rt_free(lwp->fdt.fds); + lwp->fdt.fds = RT_NULL; + } + + lwp_user_object_clear(lwp); + lwp_user_object_lock_destroy(lwp); + + /* free data section */ + if (lwp->data_entry != RT_NULL) + { +#ifdef ARCH_MM_MMU + rt_free_align(lwp->data_entry); +#else +#ifdef ARCH_MM_MPU + rt_lwp_umap_user(lwp, lwp->text_entry, 0); + rt_lwp_free_user(lwp, lwp->data_entry, lwp->data_size); +#else + rt_free_align(lwp->data_entry); +#endif /* ARCH_MM_MPU */ +#endif /* ARCH_MM_MMU */ + lwp->data_entry = RT_NULL; + } + + /* free text section */ + if (lwp->lwp_type == LWP_TYPE_DYN_ADDR) + { + if (lwp->text_entry) + { + LOG_D("lwp text free: %p", lwp->text_entry); +#ifndef ARCH_MM_MMU + rt_free((void*)lwp->text_entry); +#endif /* not defined ARCH_MM_MMU */ + lwp->text_entry = RT_NULL; + } + } + +#ifdef RT_USING_USERSPACE + lwp_unmap_user_space(lwp); +#endif + + /* for children */ + while (lwp->first_child) + { + struct rt_lwp *child; + + child = lwp->first_child; + lwp->first_child = child->sibling; + if (child->finish) + { + lwp_pid_put(lwp_to_pid(child)); + rt_free(child); + } + else + { + child->sibling = RT_NULL; + child->parent = RT_NULL; + } + } + + /* for parent */ + { + extern struct termios old_stdin_termios; + struct rt_lwp *self_lwp = (struct rt_lwp *)lwp_self(); + if (lwp->session == -1) + { + tcsetattr(1, 0, &old_stdin_termios); + } + if (lwp->tty != RT_NULL) + { + if (lwp->tty->foreground == lwp) + { + lwp->tty->foreground = self_lwp; + lwp->tty = RT_NULL; + } + } + + if (lwp->parent) + { + struct rt_thread *thread; + if (!rt_list_isempty(&lwp->wait_list)) + { + thread = rt_list_entry(lwp->wait_list.next, struct rt_thread, tlist); + thread->error = RT_EOK; + thread->msg_ret = (void*)(rt_size_t)lwp->lwp_ret; + rt_thread_resume(thread); + rt_hw_interrupt_enable(level); + return; + } + else + { + struct rt_lwp **it = &lwp->parent->first_child; + + while (*it != lwp) + { + it = &(*it)->sibling; + } + *it = lwp->sibling; + } + } + lwp_pid_put(lwp_to_pid(lwp)); + rt_free(lwp); + } + + rt_hw_interrupt_enable(level); +} + +void lwp_ref_inc(struct rt_lwp *lwp) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + lwp->ref++; + rt_hw_interrupt_enable(level); +} + +void lwp_ref_dec(struct rt_lwp *lwp) +{ + rt_base_t level; + int ref; + + level = rt_hw_interrupt_disable(); + if (lwp->ref) + { + lwp->ref--; + ref = lwp->ref; + if (!ref) + { +#ifdef RT_USING_GDBSERVER + struct rt_channel_msg msg; + + if (lwp->debug) + { + memset(&msg, 0, sizeof msg); + rt_raw_channel_send(gdb_get_server_channel(), &msg); + } +#endif /* RT_USING_GDBSERVER */ + +#ifndef ARCH_MM_MMU +#ifdef RT_LWP_USING_SHM + lwp_shm_lwp_free(lwp); +#endif /* RT_LWP_USING_SHM */ +#endif /* not defined ARCH_MM_MMU */ + lwp_free(lwp); + } + } + rt_hw_interrupt_enable(level); +} + +struct rt_lwp* lwp_from_pid(pid_t pid) +{ + rt_base_t level; + struct lwp_avl_struct *p; + struct rt_lwp *lwp = RT_NULL; + + level = rt_hw_interrupt_disable(); + p = lwp_avl_find(pid, lwp_pid_root); + if (p) + { + lwp = (struct rt_lwp *)p->data; + } + rt_hw_interrupt_enable(level); + return lwp; +} + +pid_t lwp_to_pid(struct rt_lwp* lwp) +{ + if (!lwp) + { + return 0; + } + return lwp->pid; +} + +char* lwp_pid2name(int32_t pid) +{ + struct rt_lwp *lwp; + char* process_name = RT_NULL; + + lwp = lwp_from_pid(pid); + if (lwp) + { + process_name = strrchr(lwp->cmd, '/'); + process_name = process_name? process_name + 1: lwp->cmd; + } + return process_name; +} + +pid_t lwp_name2pid(const char *name) +{ + int idx; + pid_t pid = 0; + rt_thread_t main_thread; + char* process_name = RT_NULL; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + for (idx = 0; idx < RT_LWP_MAX_NR; idx++) + { + /* 0 is reserved */ + struct rt_lwp *lwp = (struct rt_lwp *)lwp_pid_ary[idx].data; + + if (lwp) + { + process_name = strrchr(lwp->cmd, '/'); + process_name = process_name? process_name + 1: lwp->cmd; + if (!rt_strncmp(name, process_name, RT_NAME_MAX)) + { + main_thread = rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling); + if (!(main_thread->stat & RT_THREAD_CLOSE)) + { + pid = lwp->pid; + } + } + } + } + rt_hw_interrupt_enable(level); + return pid; +} + +int lwp_getpid(void) +{ + return ((struct rt_lwp *)rt_thread_self()->lwp)->pid; +} + +pid_t waitpid(pid_t pid, int *status, int options) +{ + pid_t ret = -1; + rt_base_t level; + struct rt_thread *thread; + struct rt_lwp *lwp; + struct rt_lwp *lwp_self; + + level = rt_hw_interrupt_disable(); + lwp = lwp_from_pid(pid); + if (!lwp) + { + goto quit; + } + + lwp_self = (struct rt_lwp *)rt_thread_self()->lwp; + if (!lwp_self) + { + goto quit; + } + if (lwp->parent != lwp_self) + { + goto quit; + } + + if (lwp->finish) + { + ret = pid; + } + else + { + if (!rt_list_isempty(&lwp->wait_list)) + { + goto quit; + } + thread = rt_thread_self(); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); + rt_list_insert_before(&lwp->wait_list, &(thread->tlist)); + rt_schedule(); + if (thread->error == RT_EOK) + { + ret = pid; + } + } + + if (ret != -1) + { + struct rt_lwp **lwp_node; + + *status = lwp->lwp_ret; + lwp_node = &lwp_self->first_child; + while (*lwp_node != lwp) + { + RT_ASSERT(*lwp_node != RT_NULL); + lwp_node = &(*lwp_node)->sibling; + } + (*lwp_node) = lwp->sibling; + + lwp_pid_put(pid); + rt_free(lwp); + } + +quit: + rt_hw_interrupt_enable(level); + return ret; +} + +#ifdef RT_USING_FINSH +/* copy from components/finsh/cmd.c */ +static void object_split(int len) +{ + while (len--) + { + rt_kprintf("-"); + } +} + +static void print_thread_info(struct rt_thread* thread, int maxlen) +{ + rt_uint8_t *ptr; + rt_uint8_t stat; + +#ifdef RT_USING_SMP + if (thread->oncpu != RT_CPU_DETACHED) + rt_kprintf("%-*.*s %3d %3d ", maxlen, RT_NAME_MAX, thread->name, thread->oncpu, thread->current_priority); + else + rt_kprintf("%-*.*s N/A %3d ", maxlen, RT_NAME_MAX, thread->name, thread->current_priority); +#else + rt_kprintf("%-*.*s %3d ", maxlen, RT_NAME_MAX, thread->name, thread->current_priority); +#endif /*RT_USING_SMP*/ + + stat = (thread->stat & RT_THREAD_STAT_MASK); + if (stat == RT_THREAD_READY) rt_kprintf(" ready "); + else if ((stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) rt_kprintf(" suspend"); + else if (stat == RT_THREAD_INIT) rt_kprintf(" init "); + else if (stat == RT_THREAD_CLOSE) rt_kprintf(" close "); + else if (stat == RT_THREAD_RUNNING) rt_kprintf(" running"); + +#if defined(ARCH_CPU_STACK_GROWS_UPWARD) + ptr = (rt_uint8_t *)thread->stack_addr + thread->stack_size; + while (*ptr == '#')ptr--; + + rt_kprintf(" 0x%08x 0x%08x %02d%% 0x%08x %03d\n", + ((rt_uint32_t)thread->sp - (rt_uint32_t)thread->stack_addr), + thread->stack_size, + ((rt_uint32_t)ptr - (rt_uint32_t)thread->stack_addr) * 100 / thread->stack_size, + thread->remaining_tick, + thread->error); +#else + ptr = (rt_uint8_t *)thread->stack_addr; + while (*ptr == '#')ptr++; + + rt_kprintf(" 0x%08x 0x%08x %02d%% 0x%08x %03d\n", + (thread->stack_size + (rt_uint32_t)(rt_size_t)thread->stack_addr - (rt_uint32_t)(rt_size_t)thread->sp), + thread->stack_size, + (thread->stack_size + (rt_uint32_t)(rt_size_t)thread->stack_addr - (rt_uint32_t)(rt_size_t)ptr) * 100 + / thread->stack_size, + thread->remaining_tick, + thread->error); +#endif +} + +long list_process(void) +{ + int index; + int maxlen; + rt_ubase_t level; + struct rt_thread *thread; + struct rt_list_node *node, *list; + const char *item_title = "thread"; + + int count = 0; + struct rt_thread **threads; + + maxlen = RT_NAME_MAX; +#ifdef RT_USING_SMP + rt_kprintf("%-*.s %-*.s %-*.s cpu pri status sp stack size max used left tick error\n", 4, "PID", maxlen, "CMD", maxlen, item_title); + object_split(4);rt_kprintf(" ");object_split(maxlen);rt_kprintf(" ");object_split(maxlen);rt_kprintf(" "); + rt_kprintf( "--- --- ------- ---------- ---------- ------ ---------- ---\n"); +#else + rt_kprintf("%-*.s %-*.s %-*.s pri status sp stack size max used left tick error\n", 4, "PID", maxlen, "CMD", maxlen, item_title); + object_split(4);rt_kprintf(" ");object_split(maxlen);rt_kprintf(" ");object_split(maxlen);rt_kprintf(" "); + rt_kprintf( "--- ------- ---------- ---------- ------ ---------- ---\n"); +#endif /*RT_USING_SMP*/ + + count = rt_object_get_length(RT_Object_Class_Thread); + if (count > 0) + { + /* get thread pointers */ + threads = (struct rt_thread **)rt_calloc(count, sizeof(struct rt_thread *)); + if (threads) + { + index = rt_object_get_pointers(RT_Object_Class_Thread, (rt_object_t *)threads, count); + + if (index > 0) + { + for (index = 0; index type & ~RT_Object_Class_Static) != RT_Object_Class_Thread) + { + rt_hw_interrupt_enable(level); + continue; + } + + rt_memcpy(&th, thread, sizeof(struct rt_thread)); + rt_hw_interrupt_enable(level); + + if (th.lwp == RT_NULL) + { + rt_kprintf(" %-*.*s ", maxlen, RT_NAME_MAX, "kernel"); + print_thread_info(&th, maxlen); + } + } + } + rt_free(threads); + } + } + + for (index = 0; index < RT_LWP_MAX_NR; index++) + { + struct rt_lwp *lwp = (struct rt_lwp *)lwp_pid_ary[index].data; + + if (lwp) + { + list = &lwp->t_grp; + for (node = list->next; node != list; node = node->next) + { + thread = rt_list_entry(node, struct rt_thread, sibling); + rt_kprintf("%4d %-*.*s ", lwp_to_pid(lwp), maxlen, RT_NAME_MAX, lwp->cmd); + print_thread_info(thread, maxlen); + } + } + } + return 0; +} +MSH_CMD_EXPORT(list_process, list process); + +static void cmd_kill(int argc, char** argv) +{ + int pid; + int sig = 0; + + if (argc < 2) + { + rt_kprintf("kill pid or kill pid -s signal\n"); + return; + } + + pid = atoi(argv[1]); + if (argc >= 4) + { + if (argv[2][0] == '-' && argv[2][1] == 's') + { + sig = atoi(argv[3]); + } + } + lwp_kill(pid, sig); +} +MSH_CMD_EXPORT_ALIAS(cmd_kill, kill, send a signal to a process); + +static void cmd_killall(int argc, char** argv) +{ + int pid; + if (argc < 2) + { + rt_kprintf("killall processes_name\n"); + return; + } + + while((pid = lwp_name2pid(argv[1])) >= 0) + { + lwp_kill(pid, 0); + rt_thread_mdelay(100); + } +} +MSH_CMD_EXPORT_ALIAS(cmd_killall, killall, kill processes by name); + +#endif + +int lwp_check_exit_request(void) +{ + rt_thread_t thread = rt_thread_self(); + if (!thread->lwp) + { + return 0; + } + + if (thread->exit_request == LWP_EXIT_REQUEST_TRIGGERED) + { + thread->exit_request = LWP_EXIT_REQUEST_IN_PROCESS; + return 1; + } + return 0; +} + +static int found_thread(struct rt_lwp* lwp, rt_thread_t thread) +{ + int found = 0; + rt_base_t level; + rt_list_t *list; + + level = rt_hw_interrupt_disable(); + list = lwp->t_grp.next; + while (list != &lwp->t_grp) + { + rt_thread_t iter_thread; + + iter_thread = rt_list_entry(list, struct rt_thread, sibling); + if (thread == iter_thread) + { + found = 1; + break; + } + list = list->next; + } + rt_hw_interrupt_enable(level); + return found; +} + +void lwp_request_thread_exit(rt_thread_t thread_to_exit) +{ + rt_thread_t main_thread; + rt_base_t level; + rt_list_t *list; + struct rt_lwp *lwp; + + lwp = lwp_self(); + + if ((!thread_to_exit) || (!lwp)) + { + return; + } + + level = rt_hw_interrupt_disable(); + + main_thread = rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling); + if (thread_to_exit == main_thread) + { + goto finish; + } + if ((struct rt_lwp *)thread_to_exit->lwp != lwp) + { + goto finish; + } + + for (list = lwp->t_grp.next; list != &lwp->t_grp; list = list->next) + { + rt_thread_t thread; + + thread = rt_list_entry(list, struct rt_thread, sibling); + if (thread != thread_to_exit) + { + continue; + } + if (thread->exit_request == LWP_EXIT_REQUEST_NONE) + { + thread->exit_request = LWP_EXIT_REQUEST_TRIGGERED; + } + if ((thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) + { + thread->error = -RT_EINTR; + rt_hw_dsb(); + rt_thread_wakeup(thread); + } + break; + } + + while (found_thread(lwp, thread_to_exit)) + { + rt_thread_mdelay(10); + } + +finish: + rt_hw_interrupt_enable(level); + return; +} + +void lwp_terminate(struct rt_lwp *lwp) +{ + rt_base_t level; + rt_list_t *list; + + if (!lwp) + { + /* kernel thread not support */ + return; + } + + level = rt_hw_interrupt_disable(); + for (list = lwp->t_grp.next; list != &lwp->t_grp; list = list->next) + { + rt_thread_t thread; + + thread = rt_list_entry(list, struct rt_thread, sibling); + if (thread->exit_request == LWP_EXIT_REQUEST_NONE) + { + thread->exit_request = LWP_EXIT_REQUEST_TRIGGERED; + } + if ((thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) + { + thread->error = RT_EINTR; + rt_hw_dsb(); + rt_thread_wakeup(thread); + } + } + rt_hw_interrupt_enable(level); +} + +void lwp_wait_subthread_exit(void) +{ + rt_base_t level; + struct rt_lwp *lwp; + rt_thread_t thread; + rt_thread_t main_thread; + + lwp = lwp_self(); + if (!lwp) + { + return; + } + + thread = rt_thread_self(); + main_thread = rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling); + if (thread != main_thread) + { + return; + } + + while (1) + { + int subthread_is_terminated; + + level = rt_hw_interrupt_disable(); + subthread_is_terminated = (int)(thread->sibling.prev == &lwp->t_grp); + if (!subthread_is_terminated) + { + rt_thread_t sub_thread; + rt_list_t *list; + int all_subthread_in_init = 1; + + /* check all subthread is in init state */ + for (list = thread->sibling.prev; list != &lwp->t_grp; list = list->prev) + { + + sub_thread = rt_list_entry(list, struct rt_thread, sibling); + if ((sub_thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_INIT) + { + all_subthread_in_init = 0; + break; + } + } + if (all_subthread_in_init) + { + /* delete all subthread */ + while ((list = thread->sibling.prev) != &lwp->t_grp) + { + sub_thread = rt_list_entry(list, struct rt_thread, sibling); + rt_list_remove(&sub_thread->sibling); + rt_thread_delete(sub_thread); + } + subthread_is_terminated = 1; + } + } + rt_hw_interrupt_enable(level); + + if (subthread_is_terminated) + { + break; + } + rt_thread_mdelay(10); + } +} diff --git a/components/lwp/lwp_pid.h b/components/lwp/lwp_pid.h new file mode 100644 index 0000000000000000000000000000000000000000..d20254693dbe8cf06145a0c41315ab3e83fd0396 --- /dev/null +++ b/components/lwp/lwp_pid.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-02-23 Jesven first version. + */ + +#ifndef LWP_PID_H__ +#define LWP_PID_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +struct rt_lwp; + +struct lwp_avl_struct *lwp_get_pid_ary(void); + +struct rt_lwp* lwp_new(void); +void lwp_free(struct rt_lwp* lwp); + +void lwp_ref_inc(struct rt_lwp *lwp); +void lwp_ref_dec(struct rt_lwp *lwp); + +struct rt_lwp* lwp_from_pid(pid_t pid); +pid_t lwp_to_pid(struct rt_lwp* lwp); + +pid_t lwp_name2pid(const char* name); +char* lwp_pid2name(int32_t pid); + +int lwp_getpid(void); + +pid_t waitpid(pid_t pid, int *status, int options); +long list_process(void); + +void lwp_user_object_lock_init(struct rt_lwp *lwp); +void lwp_user_object_lock_destroy(struct rt_lwp *lwp); +void lwp_user_object_lock(struct rt_lwp *lwp); +void lwp_user_object_unlock(struct rt_lwp *lwp); +int lwp_user_object_add(struct rt_lwp *lwp, rt_object_t object); +rt_err_t lwp_user_object_delete(struct rt_lwp *lwp, rt_object_t object); +void lwp_user_object_clear(struct rt_lwp *lwp); +void lwp_user_object_dup(struct rt_lwp *dst_lwp, struct rt_lwp *src_lwp); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/lwp/lwp_pmutex.c b/components/lwp/lwp_pmutex.c new file mode 100644 index 0000000000000000000000000000000000000000..e3f82877fbf3f4906d204cddb8c47525348e5b6d --- /dev/null +++ b/components/lwp/lwp_pmutex.c @@ -0,0 +1,391 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021/01/02 bernard the first version + */ + +#include +#include +#ifdef RT_USING_USERSPACE +#include +#endif +#include "clock_time.h" + +#define PMUTEX_NORMAL 0 /* Unable to recursion */ +#define PMUTEX_RECURSIVE 1 /* Can be recursion */ + +struct rt_pmutex +{ + union + { + rt_mutex_t kmutex; + rt_sem_t ksem; /* use sem to emulate the mutex without recursive */ + } lock; + + struct lwp_avl_struct node; + struct rt_object *custom_obj; + rt_uint8_t type; /* pmutex type */ +}; + +static struct rt_mutex _pmutex_lock; + +static int pmutex_system_init(void) +{ + rt_mutex_init(&_pmutex_lock, "pmtxLock", RT_IPC_FLAG_FIFO); + return 0; +} +INIT_PREV_EXPORT(pmutex_system_init); + +static rt_err_t pmutex_destory(void *data) +{ + rt_err_t ret = -1; + rt_base_t level = 0; + struct rt_pmutex *pmutex = (struct rt_pmutex *)data; + + if (pmutex) + { + level = rt_hw_interrupt_disable(); + /* remove pmutex from pmutext avl */ + lwp_avl_remove(&pmutex->node, (struct lwp_avl_struct **)pmutex->node.data); + rt_hw_interrupt_enable(level); + + if (pmutex->type == PMUTEX_NORMAL) + { + rt_sem_delete(pmutex->lock.ksem); + } + else + { + rt_mutex_delete(pmutex->lock.kmutex); + } + + /* release object */ + rt_free(pmutex); + ret = 0; + } + return ret; +} + +static struct rt_pmutex* pmutex_create(void *umutex, struct rt_lwp *lwp) +{ + struct rt_pmutex *pmutex = RT_NULL; + struct rt_object *obj = RT_NULL; + rt_ubase_t type; + + if (!lwp) + { + return RT_NULL; + } + + long *p = (long *)umutex; + /* umutex[0] bit[0-1] saved mutex type */ + type = *p & 3; + if (type != PMUTEX_NORMAL && type != PMUTEX_RECURSIVE) + { + return RT_NULL; + } + + pmutex = (struct rt_pmutex *)rt_malloc(sizeof(struct rt_pmutex)); + if (!pmutex) + { + return RT_NULL; + } + + if (type == PMUTEX_NORMAL) + { + pmutex->lock.ksem = rt_sem_create("pmutex", 1, RT_IPC_FLAG_PRIO); + if (!pmutex->lock.ksem) + { + rt_free(pmutex); + return RT_NULL; + } + } + else + { + pmutex->lock.kmutex = rt_mutex_create("pmutex", RT_IPC_FLAG_PRIO); + if (!pmutex->lock.kmutex) + { + rt_free(pmutex); + return RT_NULL; + } + } + + obj = rt_custom_object_create("pmutex", (void *)pmutex, pmutex_destory); + if (!obj) + { + if (pmutex->type == PMUTEX_NORMAL) + { + rt_sem_delete(pmutex->lock.ksem); + } + else + { + rt_mutex_delete(pmutex->lock.kmutex); + } + rt_free(pmutex); + return RT_NULL; + } + pmutex->node.avl_key = (avl_key_t)umutex; + pmutex->node.data = &lwp->address_search_head; + pmutex->custom_obj = obj; + pmutex->type = type; + + /* insert into pmutex head */ + lwp_avl_insert(&pmutex->node, &lwp->address_search_head); + return pmutex; +} + +static struct rt_pmutex* pmutex_get(void *umutex, struct rt_lwp *lwp) +{ + struct rt_pmutex *pmutex = RT_NULL; + struct lwp_avl_struct *node = RT_NULL; + + node = lwp_avl_find((avl_key_t)umutex, lwp->address_search_head); + if (!node) + { + return RT_NULL; + } + pmutex = rt_container_of(node, struct rt_pmutex, node); + return pmutex; +} + +static int _pthread_mutex_init(void *umutex) +{ + struct rt_lwp *lwp = RT_NULL; + struct rt_pmutex *pmutex = RT_NULL; + rt_err_t lock_ret = 0; + + /* umutex union is 6 x (void *) */ + if (!lwp_user_accessable(umutex, sizeof(void *) * 6)) + { + rt_set_errno(EINVAL); + return -EINVAL; + } + + lock_ret = rt_mutex_take_interruptible(&_pmutex_lock, RT_WAITING_FOREVER); + if (lock_ret != RT_EOK) + { + rt_set_errno(EAGAIN); + return -EINTR; + } + + lwp = lwp_self(); + pmutex = pmutex_get(umutex, lwp); + if (pmutex == RT_NULL) + { + /* create a pmutex according to this umutex */ + pmutex = pmutex_create(umutex, lwp); + if (pmutex == RT_NULL) + { + rt_mutex_release(&_pmutex_lock); + rt_set_errno(ENOMEM); + return -ENOMEM; + } + if (lwp_user_object_add(lwp, pmutex->custom_obj) != 0) + { + rt_custom_object_destroy(pmutex->custom_obj); + rt_set_errno(ENOMEM); + return -ENOMEM; + } + } + else + { + rt_base_t level = rt_hw_interrupt_disable(); + + if (pmutex->type == PMUTEX_NORMAL) + { + pmutex->lock.ksem->value = 1; + } + else + { + pmutex->lock.kmutex->value = 1; + pmutex->lock.kmutex->owner = RT_NULL; + pmutex->lock.kmutex->original_priority = 0xFF; + pmutex->lock.kmutex->hold = 0; + } + rt_hw_interrupt_enable(level); + } + + rt_mutex_release(&_pmutex_lock); + + return 0; +} + +static int _pthread_mutex_lock_timeout(void *umutex, struct timespec *timeout) +{ + struct rt_lwp *lwp = RT_NULL; + struct rt_pmutex *pmutex = RT_NULL; + rt_err_t lock_ret = 0; + rt_int32_t time = RT_WAITING_FOREVER; + + if (timeout) + { + if (!lwp_user_accessable((void *)timeout, sizeof(struct timespec))) + { + rt_set_errno(EINVAL); + return -EINVAL; + } + time = clock_time_to_tick(timeout); + } + + lock_ret = rt_mutex_take_interruptible(&_pmutex_lock, RT_WAITING_FOREVER); + if (lock_ret != RT_EOK) + { + rt_set_errno(EAGAIN); + return -EINTR; + } + + lwp = lwp_self(); + pmutex = pmutex_get(umutex, lwp); + if (pmutex == RT_NULL) + { + rt_mutex_release(&_pmutex_lock); + rt_set_errno(EINVAL); + return -ENOMEM; /* umutex not recored in kernel */ + } + + rt_mutex_release(&_pmutex_lock); + + switch (pmutex->type) + { + case PMUTEX_NORMAL: + lock_ret = rt_sem_take_interruptible(pmutex->lock.ksem, time); + break; + case PMUTEX_RECURSIVE: + lock_ret = rt_mutex_take_interruptible(pmutex->lock.kmutex, time); + break; + default: /* unknown type */ + return -EINVAL; + } + + if (lock_ret != RT_EOK) + { + if (lock_ret == -RT_ETIMEOUT) + { + if (time == 0) /* timeout is 0, means try lock failed */ + { + rt_set_errno(EBUSY); + return -EBUSY; + } + else + { + rt_set_errno(ETIMEDOUT); + return -ETIMEDOUT; + } + } + else + { + rt_set_errno(EAGAIN); + return -EAGAIN; + } + } + return 0; +} + +static int _pthread_mutex_unlock(void *umutex) +{ + struct rt_lwp *lwp = RT_NULL; + struct rt_pmutex *pmutex = RT_NULL; + rt_err_t lock_ret = 0; + + lock_ret = rt_mutex_take_interruptible(&_pmutex_lock, RT_WAITING_FOREVER); + if (lock_ret != RT_EOK) + { + rt_set_errno(EAGAIN); + return -EINTR; + } + + lwp = lwp_self(); + pmutex = pmutex_get(umutex, lwp); + if (pmutex == RT_NULL) + { + rt_mutex_release(&_pmutex_lock); + rt_set_errno(EINVAL); + return -EINVAL; + } + + rt_mutex_release(&_pmutex_lock); + + switch (pmutex->type) + { + case PMUTEX_NORMAL: + lock_ret = rt_sem_release(pmutex->lock.ksem); + break; + case PMUTEX_RECURSIVE: + lock_ret = rt_mutex_release(pmutex->lock.kmutex); + break; + default: /* unknown type */ + return -EINVAL; + } + + if (lock_ret != RT_EOK) + { + rt_set_errno(EPERM); + return -EAGAIN; + } + return 0; +} + +static int _pthread_mutex_destroy(void *umutex) +{ + struct rt_lwp *lwp = RT_NULL; + struct rt_pmutex *pmutex = RT_NULL; + rt_err_t lock_ret = 0; + + lock_ret = rt_mutex_take_interruptible(&_pmutex_lock, RT_WAITING_FOREVER); + if (lock_ret != RT_EOK) + { + rt_set_errno(EAGAIN); + return -EINTR; + } + + lwp = lwp_self(); + pmutex = pmutex_get(umutex, lwp); + if (pmutex == RT_NULL) + { + rt_mutex_release(&_pmutex_lock); + rt_set_errno(EINVAL); + return -EINVAL; + } + + lwp_user_object_delete(lwp, pmutex->custom_obj); + rt_mutex_release(&_pmutex_lock); + + return 0; +} + +int sys_pmutex(void *umutex, int op, void *arg) +{ + int ret = -EINVAL; + + switch (op) + { + case PMUTEX_INIT: + ret = _pthread_mutex_init(umutex); + break; + case PMUTEX_LOCK: + ret = _pthread_mutex_lock_timeout(umutex, (struct timespec*)arg); + if (ret == -ENOMEM) + { + /* lock not init, try init it and lock again. */ + ret = _pthread_mutex_init(umutex); + if (ret == 0) + { + ret = _pthread_mutex_lock_timeout(umutex, (struct timespec*)arg); + } + } + break; + case PMUTEX_UNLOCK: + ret = _pthread_mutex_unlock(umutex); + break; + case PMUTEX_DESTROY: + ret = _pthread_mutex_destroy(umutex); + break; + default: + rt_set_errno(EINVAL); + break; + } + return ret; +} diff --git a/components/lwp/lwp_setsid.c b/components/lwp/lwp_setsid.c new file mode 100644 index 0000000000000000000000000000000000000000..d72363bde56a4e8d6c15e2658b7c33ac890c5ada --- /dev/null +++ b/components/lwp/lwp_setsid.c @@ -0,0 +1,27 @@ +#include +#include + +#include "lwp.h" +//#include "lwp_tid.h" +#include "lwp_pid.h" + +int setsid(void) +{ + int err = -EPERM; + struct rt_thread *current_thread = rt_thread_self(); + struct rt_lwp *current_lwp = (struct rt_lwp *)rt_thread_self()->lwp; + + if (current_lwp->session == current_thread->tid) + { + return err; + } + + current_lwp->session = current_thread->tid; + current_lwp->__pgrp = current_thread->tid; + current_lwp->leader = 1; + current_lwp->tty = RT_NULL; + current_lwp->tty_old_pgrp = 0; + + err = current_lwp->session; + return err; +} diff --git a/components/lwp/lwp_shm.c b/components/lwp/lwp_shm.c new file mode 100644 index 0000000000000000000000000000000000000000..5312c049eff09cdc2c3ce00394fe1a72af16d742 --- /dev/null +++ b/components/lwp/lwp_shm.c @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-12 Jesven first version + */ +#include +#include + +#ifdef RT_USING_USERSPACE +#include +#include + +#include +#include + +/* the kernel structure to represent a share-memory */ +struct lwp_shm_struct +{ + size_t addr; /* point to the next item in the free list when not used */ + size_t size; + int ref; + size_t key; +}; + +static struct lwp_avl_struct *shm_tree_key; +static struct lwp_avl_struct *shm_tree_pa; + +static int shm_free_list = -1; /* the single-direct list of freed items */ +static int shm_id_used = 0; /* the latest allocated item in the array */ +static struct lwp_shm_struct _shm_ary[RT_LWP_SHM_MAX_NR]; + +/* + * Try to allocate an structure 'lwp_shm_struct' from the freed list or the + * static array. + */ +static int _shm_id_alloc(void) +{ + int id = -1; + + if (shm_free_list != -1) /* first try the freed list */ + { + id = shm_free_list; + shm_free_list = (int)_shm_ary[shm_free_list].addr; /* single-direction */ + } + else if (shm_id_used < RT_LWP_SHM_MAX_NR) /* then try the array */ + { + id = shm_id_used; + shm_id_used++; + } + return id; +} + +/* Release the item in the static array to the freed list. */ +static void shm_id_free(int id) +{ + /* link the freed itme to the single-direction list */ + _shm_ary[id].addr = (size_t)shm_free_list; + shm_free_list = id; +} + +/* Locate the shared memory through 'key' or create a new one. */ +static int _lwp_shmget(size_t key, size_t size, int create) +{ + int id = -1; + struct lwp_avl_struct *node_key = 0; + struct lwp_avl_struct *node_pa = 0; + void *page_addr = 0, *page_addr_p = RT_NULL; + uint32_t bit = 0; + + /* try to locate the item with the key in the binary tree */ + node_key = lwp_avl_find(key, shm_tree_key); + if (node_key) + { + return (struct lwp_shm_struct *)node_key->data - _shm_ary; /* the index */ + } + + /* If there doesn't exist such an item and we're allowed to create one ... */ + if (create) + { + struct lwp_shm_struct* p; + + if (!size) + { + goto err; + } + + id = _shm_id_alloc(); + if (id == -1) + { + goto err; + } + + /* allocate pages up to 2's exponent to cover the required size */ + bit = rt_page_bits(size); + page_addr = rt_pages_alloc(bit); /* virtual address */ + if (!page_addr) + { + goto err; + } + page_addr_p = (void *)((char *)page_addr + PV_OFFSET); /* physical address */ + + /* initialize the shared memory structure */ + p = _shm_ary + id; + p->addr = (size_t)page_addr_p; + p->size = (1UL << (bit + ARCH_PAGE_SHIFT)); + p->ref = 0; + p->key = key; + + /* then insert it into the balancing binary tree */ + node_key = (struct lwp_avl_struct *)rt_malloc(sizeof(struct lwp_avl_struct) * 2); + if (!node_key) + { + goto err; + } + node_key->avl_key = p->key; + node_key->data = (void *)p; + lwp_avl_insert(node_key, &shm_tree_key); + node_pa = node_key + 1; + node_pa->avl_key = p->addr; + node_pa->data = (void *)p; + lwp_avl_insert(node_pa, &shm_tree_pa); + } + return id; + +err: + if (id != -1) + { + shm_id_free(id); + } + if (page_addr) + { + rt_pages_free(page_addr, bit); + } + if (node_key) + { + rt_free(node_key); + } + return -1; +} + +/* A wrapping function, get the shared memory with interrupts disabled. */ +int lwp_shmget(size_t key, size_t size, int create) +{ + int ret = 0; + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + ret = _lwp_shmget(key, size, create); + rt_hw_interrupt_enable(level); + return ret; +} + +/* Locate the binary tree node_key corresponding to the shared-memory id. */ +static struct lwp_avl_struct *shm_id_to_node(int id) +{ + struct lwp_avl_struct *node_key = 0; + struct lwp_shm_struct *p = RT_NULL; + + /* check id */ + if (id < 0 || id >= RT_LWP_SHM_MAX_NR) + { + return RT_NULL; + } + + p = _shm_ary + id; /* the address of the shared-memory structure */ + node_key = lwp_avl_find(p->key, shm_tree_key); + if (!node_key) + { + return RT_NULL; + } + if (node_key->data != (void *)p) + { + return RT_NULL; + } + return node_key; +} + +/* Free the shared pages, the shared-memory structure and its binary tree node_key. */ +static int _lwp_shmrm(int id) +{ + struct lwp_avl_struct *node_key = RT_NULL; + struct lwp_avl_struct *node_pa = RT_NULL; + struct lwp_shm_struct* p = RT_NULL; + uint32_t bit = 0; + + node_key = shm_id_to_node(id); + if (!node_key) + { + return -1; + } + p = (struct lwp_shm_struct *)node_key->data; + if (p->ref) + { + return 0; + } + bit = rt_page_bits(p->size); + rt_pages_free((void *)((char *)p->addr - PV_OFFSET), bit); + lwp_avl_remove(node_key, &shm_tree_key); + node_pa = node_key + 1; + lwp_avl_remove(node_pa, &shm_tree_pa); + rt_free(node_key); + shm_id_free(id); + return 0; +} + +/* A wrapping function, free the shared memory with interrupt disabled. */ +int lwp_shmrm(int id) +{ + int ret = 0; + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + ret = _lwp_shmrm(id); + rt_hw_interrupt_enable(level); + return ret; +} + +/* Map the shared memory specified by 'id' to the specified virtual address. */ +static void *_lwp_shmat(int id, void *shm_vaddr) +{ + struct rt_lwp *lwp = RT_NULL; + struct lwp_avl_struct *node_key = RT_NULL; + struct lwp_shm_struct *p = RT_NULL; + void *va = RT_NULL; + + /* The id is used to locate the node_key in the binary tree, and then get the + * shared-memory structure linked to the node_key. We don't use the id to refer + * to the shared-memory structure directly, because the binary tree is used + * to verify the structure is really in use. + */ + node_key = shm_id_to_node(id); + if (!node_key) + { + return RT_NULL; + } + p = (struct lwp_shm_struct *)node_key->data; /* p = _shm_ary[id]; */ + + /* map the shared memory into the address space of the current thread */ + lwp = lwp_self(); + if (!lwp) + { + return RT_NULL; + } + va = lwp_map_user_type(lwp, shm_vaddr, (void *)p->addr, p->size, 1, MM_AREA_TYPE_SHM); + if (va) + { + p->ref++; + } + return va; +} + +/* A wrapping function: attach the shared memory to the specified address. */ +void *lwp_shmat(int id, void *shm_vaddr) +{ + void *ret = RT_NULL; + rt_base_t level = 0; + + if (((size_t)shm_vaddr & ARCH_PAGE_MASK) != 0) + { + return RT_NULL; + } + level= rt_hw_interrupt_disable(); + ret = _lwp_shmat(id, shm_vaddr); + rt_hw_interrupt_enable(level); + return ret; +} + +static struct lwp_shm_struct *_lwp_shm_struct_get(struct rt_lwp *lwp, void *shm_vaddr) +{ + void *pa = RT_NULL; + struct lwp_avl_struct *node_pa = RT_NULL; + + if (!lwp) + { + return RT_NULL; + } + pa = rt_hw_mmu_v2p(&lwp->mmu_info, shm_vaddr); /* physical memory */ + + node_pa = lwp_avl_find((size_t)pa, shm_tree_pa); + if (!node_pa) + { + return RT_NULL; + } + return (struct lwp_shm_struct *)node_pa->data; +} + +static int _lwp_shm_ref_inc(struct rt_lwp *lwp, void *shm_vaddr) +{ + struct lwp_shm_struct* p = _lwp_shm_struct_get(lwp, shm_vaddr); + + if (p) + { + p->ref++; + return p->ref; + } + return -1; +} + +int lwp_shm_ref_inc(struct rt_lwp *lwp, void *shm_vaddr) +{ + int ret = 0; + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + ret = _lwp_shm_ref_inc(lwp, shm_vaddr); + rt_hw_interrupt_enable(level); + + return ret; +} + +static int _lwp_shm_ref_dec(struct rt_lwp *lwp, void *shm_vaddr) +{ + struct lwp_shm_struct* p = _lwp_shm_struct_get(lwp, shm_vaddr); + + if (p && (p->ref > 0)) + { + p->ref--; + return p->ref; + } + return -1; +} + +int lwp_shm_ref_dec(struct rt_lwp *lwp, void *shm_vaddr) +{ + int ret = 0; + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + ret = _lwp_shm_ref_dec(lwp, shm_vaddr); + rt_hw_interrupt_enable(level); + + return ret; +} + +/* Unmap the shared memory from the address space of the current thread. */ +int _lwp_shmdt(void *shm_vaddr) +{ + struct rt_lwp *lwp = RT_NULL; + int ret = 0; + + lwp = lwp_self(); + if (!lwp) + { + return -1; + } + ret = _lwp_shm_ref_dec(lwp, shm_vaddr); + if (ret >= 0) + { + lwp_unmap_user_phy(lwp, shm_vaddr); + return 0; + } + return -1; +} +/* A wrapping function: detach the mapped shared memory. */ +int lwp_shmdt(void *shm_vaddr) +{ + int ret = 0; + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + ret = _lwp_shmdt(shm_vaddr); + rt_hw_interrupt_enable(level); + + return ret; +} + +/* Get the virtual address of a shared memory in kernel. */ +void *_lwp_shminfo(int id) +{ + struct lwp_avl_struct *node_key = RT_NULL; + struct lwp_shm_struct *p = RT_NULL; + + /* the share memory is in use only if it exsits in the binary tree */ + node_key = shm_id_to_node(id); + if (!node_key) + { + return RT_NULL; + } + p = (struct lwp_shm_struct *)node_key->data; /* p = _shm_ary[id]; */ + + return (void *)((char *)p->addr - PV_OFFSET); /* get the virtual address */ +} + +/* A wrapping function: get the virtual address of a shared memory. */ +void *lwp_shminfo(int id) +{ + void *vaddr = RT_NULL; + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + vaddr = _lwp_shminfo(id); + rt_hw_interrupt_enable(level); + return vaddr; +} + +#ifdef RT_USING_FINSH +static int _shm_info(struct lwp_avl_struct* node_key, void *data) +{ + int id = 0; + struct lwp_shm_struct* p = (struct lwp_shm_struct *)node_key->data; + + id = p - _shm_ary; + rt_kprintf("0x%08x 0x%08x 0x%08x %8d\n", p->key, p->addr, p->size, id); + return 0; +} + +void list_shm(void) +{ + rt_base_t level = 0; + + rt_kprintf(" key paddr size id\n"); + rt_kprintf("---------- ---------- ---------- --------\n"); + level = rt_hw_interrupt_disable(); + lwp_avl_traversal(shm_tree_key, _shm_info, NULL); + rt_hw_interrupt_enable(level); +} +MSH_CMD_EXPORT(list_shm, show share memory info); +#endif + +#endif diff --git a/components/lwp/lwp_shm.h b/components/lwp/lwp_shm.h new file mode 100644 index 0000000000000000000000000000000000000000..db6b1656140df81a40a50dd6bc67d15d6a367b54 --- /dev/null +++ b/components/lwp/lwp_shm.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-12 Jesven first version + */ +#ifndef __LWP_SHM_H__ +#define __LWP_SHM_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int lwp_shmget(size_t key, size_t size, int create); +int lwp_shmrm(int id); +void* lwp_shmat(int id, void* shm_vaddr); +int lwp_shmdt(void* shm_vaddr); +void *lwp_shminfo(int id); +int lwp_shm_ref_inc(struct rt_lwp *lwp, void *shm_vaddr); +int lwp_shm_ref_dec(struct rt_lwp *lwp, void *shm_vaddr); + +#ifdef __cplusplus +} +#endif + +#endif /*__LWP_SHM_H__*/ diff --git a/components/lwp/lwp_signal.c b/components/lwp/lwp_signal.c new file mode 100644 index 0000000000000000000000000000000000000000..0abb71f702595f0c40ee706bd5c377ca695c8288 --- /dev/null +++ b/components/lwp/lwp_signal.c @@ -0,0 +1,606 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-12 Jesven first version + */ + +#include +#include + +#include "lwp.h" +#include "lwp_arch.h" +#include "signal.h" + +rt_inline void lwp_sigaddset(lwp_sigset_t *set, int _sig) +{ + unsigned long sig = _sig - 1; + + if (_LWP_NSIG_WORDS == 1) + { + set->sig[0] |= 1UL << sig; + } + else + { + set->sig[sig / _LWP_NSIG_BPW] |= 1UL << (sig % _LWP_NSIG_BPW); + } +} + +rt_inline void lwp_sigdelset(lwp_sigset_t *set, int _sig) +{ + unsigned long sig = _sig - 1; + + if (_LWP_NSIG_WORDS == 1) + { + set->sig[0] &= ~(1UL << sig); + } + else + { + set->sig[sig / _LWP_NSIG_BPW] &= ~(1UL << (sig % _LWP_NSIG_BPW)); + } +} + +rt_inline int lwp_sigisemptyset(lwp_sigset_t *set) +{ + switch (_LWP_NSIG_WORDS) + { + case 4: + return (set->sig[3] | set->sig[2] | + set->sig[1] | set->sig[0]) == 0; + case 2: + return (set->sig[1] | set->sig[0]) == 0; + case 1: + return set->sig[0] == 0; + default: + return 1; + } +} + +rt_inline int lwp_sigismember(lwp_sigset_t *set, int _sig) +{ + unsigned long sig = _sig - 1; + + if (_LWP_NSIG_WORDS == 1) + { + return 1 & (set->sig[0] >> sig); + } + else + { + return 1 & (set->sig[sig / _LWP_NSIG_BPW] >> (sig % _LWP_NSIG_BPW)); + } +} + +rt_inline int next_signal(lwp_sigset_t *pending, lwp_sigset_t *mask) +{ + unsigned long i, *s, *m, x; + int sig = 0; + + s = pending->sig; + m = mask->sig; + + x = *s & ~*m; + if (x) + { + sig = ffz(~x) + 1; + return sig; + } + + switch (_LWP_NSIG_WORDS) + { + default: + for (i = 1; i < _LWP_NSIG_WORDS; ++i) + { + x = *++s &~ *++m; + if (!x) + continue; + sig = ffz(~x) + i*_LWP_NSIG_BPW + 1; + break; + } + break; + + case 2: + x = s[1] &~ m[1]; + if (!x) + break; + sig = ffz(~x) + _LWP_NSIG_BPW + 1; + break; + + case 1: + /* Nothing to do */ + break; + } + + return sig; +} + +int lwp_suspend_sigcheck(rt_thread_t thread, int suspend_flag) +{ + struct rt_lwp *lwp = (struct rt_lwp*)thread->lwp; + int ret = 0; + + switch (suspend_flag) + { + case RT_INTERRUPTIBLE: + if (!lwp_sigisemptyset(&thread->signal)) + { + break; + } + if (thread->lwp && !lwp_sigisemptyset(&lwp->signal)) + { + break; + } + ret = 1; + break; + case RT_KILLABLE: + if (lwp_sigismember(&thread->signal, SIGKILL)) + { + break; + } + if (thread->lwp && lwp_sigismember(&lwp->signal, SIGKILL)) + { + break; + } + ret = 1; + break; + case RT_UNINTERRUPTIBLE: + ret = 1; + break; + default: + RT_ASSERT(0); + break; + } + return ret; +} + +int lwp_signal_check(void) +{ + rt_base_t level; + struct rt_thread *thread; + struct rt_lwp *lwp; + uint32_t have_signal = 0; + + level = rt_hw_interrupt_disable(); + + thread = rt_thread_self(); + + if (thread->signal_in_process) + { + goto out; + } + + lwp = (struct rt_lwp*)thread->lwp; + + if (lwp->signal_in_process) + { + goto out; + } + + have_signal = !lwp_sigisemptyset(&thread->signal); + if (have_signal) + { + thread->signal_in_process = 1; + goto out; + } + have_signal = !lwp_sigisemptyset(&lwp->signal); + if (have_signal) + { + lwp->signal_in_process = 1; + } +out: + rt_hw_interrupt_enable(level); + return have_signal; +} + +int lwp_signal_backup(void *user_sp, void *user_pc, void* user_flag) +{ + rt_base_t level; + struct rt_thread *thread; + struct rt_lwp *lwp; + int signal; + + level = rt_hw_interrupt_disable(); + thread = rt_thread_self(); + if (thread->signal_in_process) + { + thread->user_ctx.sp = user_sp; + thread->user_ctx.pc = user_pc; + thread->user_ctx.flag = user_flag; + + signal = next_signal(&thread->signal, &thread->signal_mask); + RT_ASSERT(signal != 0); + lwp_sigaddset(&thread->signal_mask, signal); + thread->signal_mask_bak = signal; + lwp_sigdelset(&thread->signal, signal); + } + else + { + lwp = (struct rt_lwp*)thread->lwp; + lwp->user_ctx.sp = user_sp; + lwp->user_ctx.pc = user_pc; + lwp->user_ctx.flag = user_flag; + + signal = next_signal(&lwp->signal, &lwp->signal_mask); + RT_ASSERT(signal != 0); + lwp_sigaddset(&lwp->signal_mask, signal); + lwp->signal_mask_bak = signal; + lwp_sigdelset(&lwp->signal, signal); + } + rt_hw_interrupt_enable(level); + return signal; +} + +struct rt_user_context *lwp_signal_restore(void) +{ + rt_base_t level; + struct rt_thread *thread; + struct rt_lwp *lwp; + struct rt_user_context *ctx; + + level = rt_hw_interrupt_disable(); + thread = rt_thread_self(); + if (thread->signal_in_process) + { + ctx = &thread->user_ctx; + thread->signal_in_process = 0; + + lwp_sigdelset(&thread->signal_mask, thread->signal_mask_bak); + thread->signal_mask_bak = 0; + } + else + { + lwp = (struct rt_lwp*)thread->lwp; + ctx = &lwp->user_ctx; + RT_ASSERT(lwp->signal_in_process != 0); + lwp->signal_in_process = 0; + + lwp_sigdelset(&lwp->signal_mask, lwp->signal_mask_bak); + lwp->signal_mask_bak = 0; + } + rt_hw_interrupt_enable(level); + return ctx; +} + +rt_inline int _lwp_check_ignore(int sig) +{ + if (sig == SIGCHLD || sig == SIGCONT) + { + return 1; + } + return 0; +} + +void sys_exit(int value); +lwp_sighandler_t lwp_sighandler_get(int sig) +{ + lwp_sighandler_t func = RT_NULL; + struct rt_lwp *lwp; + rt_thread_t thread; + rt_base_t level; + + if (sig == 0 || sig > _LWP_NSIG) + { + return func; + } + level = rt_hw_interrupt_disable(); + thread = rt_thread_self(); +#ifndef ARCH_MM_MMU + if (thread->signal_in_process) + { + func = thread->signal_handler[sig - 1]; + goto out; + } +#endif + lwp = (struct rt_lwp*)thread->lwp; + + func = lwp->signal_handler[sig - 1]; + if (!func) + { + if (_lwp_check_ignore(sig)) + { + goto out; + } + if (lwp->signal_in_process) + { + lwp_terminate(lwp); + } + sys_exit(0); + } +out: + rt_hw_interrupt_enable(level); + + if (func == (lwp_sighandler_t)SIG_IGN) + { + func = RT_NULL; + } + return func; +} + +void lwp_sighandler_set(int sig, lwp_sighandler_t func) +{ + rt_base_t level; + + if (sig == 0 || sig > _LWP_NSIG) + return; + if (sig == SIGKILL || sig == SIGSTOP) + return; + level = rt_hw_interrupt_disable(); + ((struct rt_lwp*)rt_thread_self()->lwp)->signal_handler[sig - 1] = func; + rt_hw_interrupt_enable(level); +} + +#ifndef ARCH_MM_MMU +void lwp_thread_sighandler_set(int sig, lwp_sighandler_t func) +{ + rt_base_t level; + + if (sig == 0 || sig > _LWP_NSIG) + return; + level = rt_hw_interrupt_disable(); + rt_thread_self()->signal_handler[sig - 1] = func; + rt_hw_interrupt_enable(level); +} +#endif + +int lwp_sigaction(int sig, const struct lwp_sigaction *act, + struct lwp_sigaction *oact, size_t sigsetsize) +{ + rt_base_t level; + struct rt_lwp *lwp; + int ret = -RT_EINVAL; + lwp_sigset_t newset; + + level = rt_hw_interrupt_disable(); + lwp = (struct rt_lwp*)rt_thread_self()->lwp; + if (!lwp) + { + goto out; + } + if (sigsetsize != sizeof(lwp_sigset_t)) + { + goto out; + } + if (!act && !oact) + { + goto out; + } + if (oact) + { + oact->sa_flags = lwp->sa_flags; + oact->sa_mask = lwp->signal_mask; + oact->sa_restorer = RT_NULL; + oact->__sa_handler._sa_handler = lwp->signal_handler[sig - 1]; + } + if (act) + { + lwp->sa_flags = act->sa_flags; + newset = act->sa_mask; + lwp_sigdelset(&newset, SIGKILL); + lwp_sigdelset(&newset, SIGSTOP); + lwp->signal_mask = newset; + lwp_sighandler_set(sig, act->__sa_handler._sa_handler); + } + ret = 0; +out: + rt_hw_interrupt_enable(level); + return ret; +} + +rt_inline void sigorsets(lwp_sigset_t *dset, const lwp_sigset_t *set0, const lwp_sigset_t *set1) +{ + switch (_LWP_NSIG_WORDS) + { + case 4: + dset->sig[3] = set0->sig[3] | set1->sig[3]; + dset->sig[2] = set0->sig[2] | set1->sig[2]; + case 2: + dset->sig[1] = set0->sig[1] | set1->sig[1]; + case 1: + dset->sig[0] = set0->sig[0] | set1->sig[0]; + default: + return; + } +} + +rt_inline void sigandsets(lwp_sigset_t *dset, const lwp_sigset_t *set0, const lwp_sigset_t *set1) +{ + switch (_LWP_NSIG_WORDS) + { + case 4: + dset->sig[3] = set0->sig[3] & set1->sig[3]; + dset->sig[2] = set0->sig[2] & set1->sig[2]; + case 2: + dset->sig[1] = set0->sig[1] & set1->sig[1]; + case 1: + dset->sig[0] = set0->sig[0] & set1->sig[0]; + default: + return; + } +} + +int lwp_sigprocmask(int how, const lwp_sigset_t *sigset, lwp_sigset_t *oset) +{ + int ret = -1; + rt_base_t level; + struct rt_lwp *lwp; + struct rt_thread *thread; + lwp_sigset_t newset; + + level = rt_hw_interrupt_disable(); + + thread = rt_thread_self(); + lwp = (struct rt_lwp*)thread->lwp; + if (!lwp) + { + goto out; + } + if (oset) + { + rt_memcpy(oset, &lwp->signal_mask, sizeof(lwp_sigset_t)); + } + + if (sigset) + { + switch (how) + { + case SIG_BLOCK: + sigorsets(&newset, &lwp->signal_mask, sigset); + break; + case SIG_UNBLOCK: + sigandsets(&newset, &lwp->signal_mask, sigset); + break; + case SIG_SETMASK: + newset = *sigset; + break; + default: + ret = RT_EINVAL; + goto out; + } + + lwp_sigdelset(&newset, SIGKILL); + lwp_sigdelset(&newset, SIGSTOP); + + lwp->signal_mask = newset; + } + ret = 0; +out: + rt_hw_interrupt_enable(level); + return ret; +} + +int lwp_thread_sigprocmask(int how, const lwp_sigset_t *sigset, lwp_sigset_t *oset) +{ + rt_base_t level; + struct rt_thread *thread; + lwp_sigset_t newset; + + level = rt_hw_interrupt_disable(); + thread = rt_thread_self(); + + if (oset) + { + rt_memcpy(oset, &thread->signal_mask, sizeof(lwp_sigset_t)); + } + + if (sigset) + { + switch (how) + { + case SIG_BLOCK: + sigorsets(&newset, &thread->signal_mask, sigset); + break; + case SIG_UNBLOCK: + sigandsets(&newset, &thread->signal_mask, sigset); + break; + case SIG_SETMASK: + newset = *sigset; + break; + default: + goto out; + } + + lwp_sigdelset(&newset, SIGKILL); + lwp_sigdelset(&newset, SIGSTOP); + + thread->signal_mask = newset; + } +out: + rt_hw_interrupt_enable(level); + return 0; +} + +static void _do_signal_wakeup(rt_thread_t thread, int sig) +{ + if ((thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) + { + int need_schedule = 1; + + if ((thread->stat & RT_SIGNAL_COMMON_WAKEUP_MASK) != RT_SIGNAL_COMMON_WAKEUP_MASK) + { + rt_thread_wakeup(thread); + } + else if ((sig == SIGKILL) && ((thread->stat & RT_SIGNAL_KILL_WAKEUP_MASK) != RT_SIGNAL_KILL_WAKEUP_MASK)) + { + rt_thread_wakeup(thread); + } + else + { + need_schedule = 0; + } + + /* do schedule */ + if (need_schedule) + { + rt_schedule(); + } + } +} + +int lwp_kill(pid_t pid, int sig) +{ + rt_base_t level; + struct rt_lwp *lwp; + int ret = -1; + rt_thread_t thread; + + if (sig < 0 || sig >= _LWP_NSIG) + { + rt_set_errno(EINVAL); + return ret; + } + level = rt_hw_interrupt_disable(); + lwp = lwp_from_pid(pid); + if (!lwp) + { + rt_set_errno(ESRCH); + goto out; + } + if (sig) + { + /* check main thread */ + thread = rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling); + if (!lwp_sigismember(&lwp->signal_mask, sig)) /* if signal masked */ + { + lwp_sigaddset(&lwp->signal, sig); + _do_signal_wakeup(thread, sig); + } + } + ret = 0; +out: + rt_hw_interrupt_enable(level); + return ret; +} + +int lwp_thread_kill(rt_thread_t thread, int sig) +{ + rt_base_t level; + int ret = -RT_EINVAL; + + if (!thread) + { + rt_set_errno(ESRCH); + return ret; + } + if (sig < 0 || sig >= _LWP_NSIG) + { + rt_set_errno(EINVAL); + return ret; + } + level = rt_hw_interrupt_disable(); + if (!thread->lwp) + { + rt_set_errno(EPERM); + goto out; + } + if (!lwp_sigismember(&thread->signal_mask, sig)) /* if signal masked */ + { + lwp_sigaddset(&thread->signal, sig); + _do_signal_wakeup(thread, sig); + } + ret = 0; +out: + rt_hw_interrupt_enable(level); + return ret; +} diff --git a/components/lwp/lwp_signal.h b/components/lwp/lwp_signal.h new file mode 100644 index 0000000000000000000000000000000000000000..6d393f0098a61cf9b26bfc4960a92f95e4d7ac6e --- /dev/null +++ b/components/lwp/lwp_signal.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-02-23 Jesven first version. + */ + +#ifndef LWP_SIGNAL_H__ +#define LWP_SIGNAL_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int lwp_signal_check(void); +int lwp_signal_backup(void *user_sp, void *user_pc, void* user_flag); +struct rt_user_context *lwp_signal_restore(void); +lwp_sighandler_t lwp_sighandler_get(int sig); +void lwp_sighandler_set(int sig, lwp_sighandler_t func); +#ifndef ARCH_MM_MMU +void lwp_thread_sighandler_set(int sig, lwp_sighandler_t func); +#endif +int lwp_sigprocmask(int how, const lwp_sigset_t *sigset, lwp_sigset_t *oset); +int lwp_sigaction(int sig, const struct lwp_sigaction *act, struct lwp_sigaction * oact, size_t sigsetsize); +int lwp_thread_sigprocmask(int how, const lwp_sigset_t *sigset, lwp_sigset_t *oset); + +int lwp_kill(pid_t pid, int sig); +int lwp_thread_kill(rt_thread_t thread, int sig); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/lwp/lwp_syscall.c b/components/lwp/lwp_syscall.c index be95c5fb896f000505614b05beb0788023ee6bfe..2457dd698e8a13ae55ad20105ac2df753a3368d5 100644 --- a/components/lwp/lwp_syscall.c +++ b/components/lwp/lwp_syscall.c @@ -1,269 +1,4168 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-06-10 Bernard first version + * 2021-02-03 lizhirui add limit condition for network syscall and add 64-bit arch support + * 2021-02-06 lizhirui fix some bugs + * 2021-02-12 lizhirui add 64-bit support for sys_brk + * 2021-02-20 lizhirui fix some warnings */ /* RT-Thread System call */ +#include +#include + #include -#include -#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif +#ifdef RT_USING_DFS #include +#include #include +#endif #if (defined(RT_USING_SAL) && defined(SAL_USING_POSIX)) #include -#define SYSCALL_NET(f) ((void*)(f)) +#define SYSCALL_NET(f) ((void *)(f)) +#else +#define SYSCALL_NET(f) ((void *)sys_notimpl) +#endif + +#if defined(RT_USING_DFS) && defined(RT_USING_USERSPACE) +#define SYSCALL_USPACE(f) ((void *)(f)) #else -#define SYSCALL_NET(f) ((void*)sys_notimpl) +#define SYSCALL_USPACE(f) ((void *)sys_notimpl) #endif -#define DBG_TAG "LWP_CALL" -#define DBG_LVL DBG_WARNING +#define DBG_TAG "SYSCALL" +#define DBG_LVL DBG_INFO #include -static void __exit_files(rt_thread_t tid) +#ifdef RT_USING_SAL +#include +#include + +#include +#include +#endif /* RT_USING_SAL */ + +#include +#include "lwp_ipc_internal.h" + +#ifndef GRND_NONBLOCK +#define GRND_NONBLOCK 0x0001 +#endif /* GRND_NONBLOCK */ + +#ifndef GRND_RANDOM +#define GRND_RANDOM 0x0002 +#endif /*GRND_RANDOM */ + +#define SET_ERRNO(no) rt_set_errno(-(no)) +#define GET_ERRNO() ((rt_get_errno() > 0) ? (-rt_get_errno()) : rt_get_errno()) +struct musl_sockaddr { - struct rt_lwp *lwp; + uint16_t sa_family; + char sa_data[14]; +}; - lwp = (struct rt_lwp *)tid->lwp; - while (lwp->fdt.maxfd > 0) +int sys_dup(int oldfd); +int sys_dup2(int oldfd, int new); +void lwp_cleanup(struct rt_thread *tid); + +#ifdef ARCH_MM_MMU +#define ALLOC_KERNEL_STACK_SIZE 5120 + +extern void lwp_user_thread_entry(void *args, const void *text, void *ustack, void *user_stack); +int sys_futex(int *uaddr, int op, int val, void *timeout, void *uaddr2, int val3); +int sys_pmutex(void *umutex, int op, void *arg); +int sys_cacheflush(void *addr, int len, int cache); +static void *kmem_get(size_t size) +{ + return rt_malloc(size); +} + +static void kmem_put(void *kptr) +{ + rt_free(kptr); +} +#else +#define ALLOC_KERNEL_STACK_SIZE 1536 +#define ALLOC_KERNEL_STACK_SIZE_MIN 1024 +#define ALLOC_KERNEL_STACK_SIZE_MAX 4096 + +extern void lwp_user_entry(void *args, const void *text, void *data, void *user_stack); +extern void set_user_context(void *stack); +#endif /* ARCH_MM_MMU */ + +/* The same socket option is defined differently in the user interfaces and the + * implementation. The options should be converted in the kernel. */ + +/* socket levels */ +#define INTF_SOL_SOCKET 1 +#define IMPL_SOL_SOCKET 0xFFF + +#define INTF_IPPROTO_IP 0 +#define IMPL_IPPROTO_IP 0 + +#define INTF_IPPROTO_TCP 6 +#define IMPL_IPPROTO_TCP 6 + +#define INTF_IPPROTO_IPV6 41 +#define IMPL_IPPROTO_IPV6 41 + +/* SOL_SOCKET option names */ +#define INTF_SO_BROADCAST 6 +#define INTF_SO_KEEPALIVE 9 +#define INTF_SO_REUSEADDR 2 +#define INTF_SO_TYPE 3 +#define INTF_SO_ERROR 4 +#define INTF_SO_SNDTIMEO 21 +#define INTF_SO_RCVTIMEO 20 +#define INTF_SO_RCVBUF 8 +#define INTF_SO_LINGER 13 +#define INTF_SO_NO_CHECK 11 +#define INTF_SO_ACCEPTCONN 30 +#define INTF_SO_DONTROUTE 5 +#define INTF_SO_OOBINLINE 10 +#define INTF_SO_REUSEPORT 15 +#define INTF_SO_SNDBUF 7 +#define INTF_SO_SNDLOWAT 19 +#define INTF_SO_RCVLOWAT 18 + +#define IMPL_SO_BROADCAST 0x0020 +#define IMPL_SO_KEEPALIVE 0x0008 +#define IMPL_SO_REUSEADDR 0x0004 +#define IMPL_SO_TYPE 0x1008 +#define IMPL_SO_ERROR 0x1007 +#define IMPL_SO_SNDTIMEO 0x1005 +#define IMPL_SO_RCVTIMEO 0x1006 +#define IMPL_SO_RCVBUF 0x1002 +#define IMPL_SO_LINGER 0x0080 +#define IMPL_SO_NO_CHECK 0x100a +#define IMPL_SO_ACCEPTCONN 0x0002 +#define IMPL_SO_DONTROUTE 0x0010 +#define IMPL_SO_OOBINLINE 0x0100 +#define IMPL_SO_REUSEPORT 0x0200 +#define IMPL_SO_SNDBUF 0x1001 +#define IMPL_SO_SNDLOWAT 0x1003 +#define IMPL_SO_RCVLOWAT 0x1004 + +/* IPPROTO_IP option names */ +#define INTF_IP_TTL 2 +#define INTF_IP_TOS 1 +#define INTF_IP_MULTICAST_TTL 33 +#define INTF_IP_MULTICAST_IF 32 +#define INTF_IP_MULTICAST_LOOP 34 +#define INTF_IP_ADD_MEMBERSHIP 35 +#define INTF_IP_DROP_MEMBERSHIP 36 + +#define IMPL_IP_TTL 2 +#define IMPL_IP_TOS 1 +#define IMPL_IP_MULTICAST_TTL 5 +#define IMPL_IP_MULTICAST_IF 6 +#define IMPL_IP_MULTICAST_LOOP 7 +#define IMPL_IP_ADD_MEMBERSHIP 3 +#define IMPL_IP_DROP_MEMBERSHIP 4 + +/* IPPROTO_TCP option names */ +#define INTF_TCP_NODELAY 1 +#define INTF_TCP_KEEPALIVE 9 +#define INTF_TCP_KEEPIDLE 4 +#define INTF_TCP_KEEPINTVL 5 +#define INTF_TCP_KEEPCNT 6 + +#define IMPL_TCP_NODELAY 0x01 +#define IMPL_TCP_KEEPALIVE 0x02 +#define IMPL_TCP_KEEPIDLE 0x03 +#define IMPL_TCP_KEEPINTVL 0x04 +#define IMPL_TCP_KEEPCNT 0x05 + +/* IPPROTO_IPV6 option names */ +#define INTF_IPV6_V6ONLY 26 +#define IMPL_IPV6_V6ONLY 27 + +#ifdef RT_USING_SAL +static void convert_sockopt(int *level, int *optname) +{ + if (*level == INTF_SOL_SOCKET) + { + *level = IMPL_SOL_SOCKET; + + switch (*optname) + { + case INTF_SO_REUSEADDR: + *optname = IMPL_SO_REUSEADDR; + break; + case INTF_SO_KEEPALIVE: + *optname = IMPL_SO_KEEPALIVE; + break; + case INTF_SO_BROADCAST: + *optname = IMPL_SO_BROADCAST; + break; + case INTF_SO_ACCEPTCONN: + *optname = IMPL_SO_ACCEPTCONN; + break; + case INTF_SO_DONTROUTE: + *optname = IMPL_SO_DONTROUTE; + break; + case INTF_SO_LINGER: + *optname = IMPL_SO_LINGER; + break; + case INTF_SO_OOBINLINE: + *optname = IMPL_SO_OOBINLINE; + break; + case INTF_SO_REUSEPORT: + *optname = IMPL_SO_REUSEPORT; + break; + case INTF_SO_SNDBUF: + *optname = IMPL_SO_SNDBUF; + break; + case INTF_SO_RCVBUF: + *optname = IMPL_SO_RCVBUF; + break; + case INTF_SO_SNDLOWAT: + *optname = IMPL_SO_SNDLOWAT; + break; + case INTF_SO_RCVLOWAT: + *optname = IMPL_SO_RCVLOWAT; + break; + case INTF_SO_SNDTIMEO: + *optname = IMPL_SO_SNDTIMEO; + break; + case INTF_SO_RCVTIMEO: + *optname = IMPL_SO_RCVTIMEO; + break; + case INTF_SO_ERROR: + *optname = IMPL_SO_ERROR; + break; + case INTF_SO_TYPE: + *optname = IMPL_SO_TYPE; + break; + case INTF_SO_NO_CHECK: + *optname = IMPL_SO_NO_CHECK; + break; + + /* + * SO_DONTLINGER (*level = ((int)(~SO_LINGER))), + * SO_USELOOPBACK (*level = 0x0040) and + * SO_CONTIMEO (*level = 0x1009) are not supported for now. + */ + default: + *optname = 0; + break; + } + return; + } + + if (*level == INTF_IPPROTO_IP) + { + *level = IMPL_IPPROTO_IP; + + switch (*optname) + { + case INTF_IP_TTL: + *optname = IMPL_IP_TTL; + break; + case INTF_IP_TOS: + *optname = IMPL_IP_TOS; + break; + case INTF_IP_MULTICAST_TTL: + *optname = IMPL_IP_MULTICAST_TTL; + break; + case INTF_IP_MULTICAST_IF: + *optname = IMPL_IP_MULTICAST_IF; + break; + case INTF_IP_MULTICAST_LOOP: + *optname = IMPL_IP_MULTICAST_LOOP; + break; + case INTF_IP_ADD_MEMBERSHIP: + *optname = IMPL_IP_ADD_MEMBERSHIP; + break; + case INTF_IP_DROP_MEMBERSHIP: + *optname = IMPL_IP_DROP_MEMBERSHIP; + break; + default: + break; + } + } + + if (*level == INTF_IPPROTO_TCP) + { + *level = IMPL_IPPROTO_TCP; + + switch (*optname) + { + case INTF_TCP_NODELAY: + *optname = IMPL_TCP_NODELAY; + break; + case INTF_TCP_KEEPALIVE: + *optname = IMPL_TCP_KEEPALIVE; + break; + case INTF_TCP_KEEPIDLE: + *optname = IMPL_TCP_KEEPIDLE; + break; + case INTF_TCP_KEEPINTVL: + *optname = IMPL_TCP_KEEPINTVL; + break; + case INTF_TCP_KEEPCNT: + *optname = IMPL_TCP_KEEPCNT; + break; + default: + break; + } + return; + } + + if (*level == INTF_IPPROTO_IPV6) + { + *level = IMPL_IPPROTO_IPV6; + + switch (*optname) + { + case INTF_IPV6_V6ONLY: + *optname = IMPL_IPV6_V6ONLY; + break; + default: + break; + } + return; + } + +} +#endif /* RT_USING_SAL */ + +#ifdef RT_USING_LWIP + static void sockaddr_tolwip(const struct musl_sockaddr *std, struct sockaddr *lwip) { - lwp->fdt.maxfd --; - close(lwp->fdt.maxfd); + if (std && lwip) + { + lwip->sa_len = sizeof(*lwip); + lwip->sa_family = (sa_family_t) std->sa_family; + memcpy(lwip->sa_data, std->sa_data, sizeof(lwip->sa_data)); + } + } + + static void sockaddr_tomusl(const struct sockaddr *lwip, struct musl_sockaddr *std) + { + if (std && lwip) + { + std->sa_family = (uint16_t) lwip->sa_family; + memcpy(std->sa_data, lwip->sa_data, sizeof(std->sa_data)); + } } +#endif + +static void lwp_user_thread(void *parameter) +{ + rt_thread_t tid; + rt_size_t user_stack; + + tid = rt_thread_self(); + + user_stack = (rt_size_t)tid->user_stack + tid->user_stack_size; + user_stack &= ~7; //align 8 + +#ifdef ARCH_MM_MMU + lwp_user_thread_entry(parameter, tid->user_entry, (void *)user_stack, tid->stack_addr + tid->stack_size); +#else + set_user_context((void*)user_stack); + lwp_user_entry(parameter, tid->user_entry, ((struct rt_lwp *)tid->lwp)->data_entry, (void*)user_stack); +#endif /* ARCH_MM_MMU */ } /* thread/process */ void sys_exit(int value) { - rt_thread_t tid; + rt_base_t level; + rt_thread_t tid, main_thread; + struct rt_lwp *lwp; + + LOG_D("thread/process exit."); - /* TODO: handle the return_value */ - dbg_log(DBG_LOG, "enter sys_exit\n"); tid = rt_thread_self(); - __exit_files(tid); - rt_thread_delete(tid); + lwp = (struct rt_lwp *)tid->lwp; + + level = rt_hw_interrupt_disable(); +#ifdef ARCH_MM_MMU + if (tid->clear_child_tid) + { + int t = 0; + int *clear_child_tid = tid->clear_child_tid; + + tid->clear_child_tid = RT_NULL; + lwp_put_to_user(clear_child_tid, &t, sizeof t); + sys_futex(tid->clear_child_tid, FUTEX_WAKE, 1, RT_NULL, RT_NULL, 0); + } + main_thread = rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling); + if (main_thread == tid) + { + lwp_terminate(lwp); + lwp_wait_subthread_exit(); + lwp->lwp_ret = value; + } +#else + main_thread = rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling); + if (main_thread == tid) + { + rt_thread_t sub_thread; + rt_list_t *list; + + lwp_terminate(lwp); + + /* delete all subthread */ + while ((list = tid->sibling.prev) != &lwp->t_grp) + { + sub_thread = rt_list_entry(list, struct rt_thread, sibling); + rt_list_remove(&sub_thread->sibling); + rt_thread_delete(sub_thread); + } + lwp->lwp_ret = value; + } +#endif /* ARCH_MM_MMU */ + rt_thread_delete(tid); rt_schedule(); + rt_hw_interrupt_enable(level); + + return; +} +/* exit group */ +void sys_exit_group(int status) +{ return; } /* syscall: "read" ret: "ssize_t" args: "int" "void *" "size_t" */ ssize_t sys_read(int fd, void *buf, size_t nbyte) { - return read(fd, buf, nbyte); +#ifdef RT_USING_USERSPACE + void *kmem = RT_NULL; + ssize_t ret = -1; + + if (!nbyte) + { + return -EINVAL; + } + + if (!lwp_user_accessable((void *)buf, nbyte)) + { + return -EFAULT; + } + + kmem = kmem_get(nbyte); + if (!kmem) + { + return -ENOMEM; + } + + ret = read(fd, kmem, nbyte); + if (ret > 0) + { + lwp_put_to_user(buf, kmem, ret); + } + + kmem_put(kmem); + return (ret < 0 ? GET_ERRNO() : ret); +#else + if (!lwp_user_accessable((void *)buf, nbyte)) + { + return -EFAULT; + } + ssize_t ret = read(fd, buf, nbyte); + return (ret < 0 ? GET_ERRNO() : ret); +#endif } /* syscall: "write" ret: "ssize_t" args: "int" "const void *" "size_t" */ ssize_t sys_write(int fd, const void *buf, size_t nbyte) { - return write(fd, buf, nbyte); +#ifdef RT_USING_USERSPACE + void *kmem = RT_NULL; + ssize_t ret = -1; + + if (!nbyte) + { + return -EINVAL; + } + + if (!lwp_user_accessable((void *)buf, nbyte)) + { + return -EFAULT; + } + + kmem = kmem_get(nbyte); + if (!kmem) + { + return -ENOMEM; + } + + lwp_get_from_user(kmem, (void *)buf, nbyte); + ret = write(fd, kmem, nbyte); + + kmem_put(kmem); + return (ret < 0 ? GET_ERRNO() : ret); +#else + if (!lwp_user_accessable((void *)buf, nbyte)) + { + return -EFAULT; + } + ssize_t ret = write(fd, buf, nbyte); + return (ret < 0 ? GET_ERRNO() : ret); +#endif } /* syscall: "lseek" ret: "off_t" args: "int" "off_t" "int" */ off_t sys_lseek(int fd, off_t offset, int whence) { - return lseek(fd, offset, whence); + off_t ret = lseek(fd, offset, whence); + return (ret < 0 ? GET_ERRNO() : ret); } /* syscall: "open" ret: "int" args: "const char *" "int" "..." */ -int sys_open(const char *name, int mode, ...) +int sys_open(const char *name, int flag, ...) { - return open(name, mode, 0); +#ifdef RT_USING_USERSPACE + int ret = -1; + rt_size_t len = 0; + char *kname = RT_NULL; + + if (!lwp_user_accessable((void *)name, 1)) + { + return -EFAULT; + } + + len = rt_strlen(name); + if (!len) + { + return -EINVAL; + } + + kname = (char *)kmem_get(len + 1); + if (!kname) + { + return -ENOMEM; + } + + lwp_get_from_user(kname, (void *)name, len + 1); + ret = open(kname, flag, 0); + + kmem_put(kname); + return (ret < 0 ? GET_ERRNO() : ret); +#else + if (!lwp_user_accessable((void *)name, 1)) + { + return -EFAULT; + } + int ret = open(name, flag, 0); + return (ret < 0 ? GET_ERRNO() : ret); +#endif } /* syscall: "close" ret: "int" args: "int" */ int sys_close(int fd) { - return close(fd); + int ret = close(fd); + return (ret < 0 ? GET_ERRNO() : ret); } /* syscall: "ioctl" ret: "int" args: "int" "u_long" "..." */ int sys_ioctl(int fd, unsigned long cmd, void* data) { - return ioctl(fd, cmd, data); + int ret = ioctl(fd, cmd, data); + return (ret < 0 ? GET_ERRNO() : ret); } -/* syscall: "nanosleep" ret: "int" args: "const struct timespec *" "struct timespec *" */ -int sys_nanosleep(const struct timespec *rqtp, struct timespec *rmtp) +int sys_fstat(int file, struct stat *buf) { - rt_tick_t tick; - - dbg_log(DBG_LOG, "sys_nanosleep\n"); +#ifdef RT_USING_USERSPACE + int ret = -1; + struct stat statbuff; - tick = rqtp->tv_sec * RT_TICK_PER_SECOND + (rqtp->tv_nsec * RT_TICK_PER_SECOND)/ 1000000000; - rt_thread_delay(tick); - - if (rmtp) + if (!lwp_user_accessable((void *)buf, sizeof(struct stat))) { - tick = rt_tick_get() - tick; - /* get the passed time */ - rmtp->tv_sec = tick/RT_TICK_PER_SECOND; - rmtp->tv_nsec = (tick%RT_TICK_PER_SECOND) * (1000000000/RT_TICK_PER_SECOND); + return -EFAULT; } - - return 0; -} - -/* syscall: "getpriority" ret: "int" args: "int" "id_t" */ -int sys_getpriority(int which, id_t who) -{ - if (which == PRIO_PROCESS) + else { - rt_thread_t tid; + ret = fstat(file, &statbuff); - tid = rt_thread_self(); - if (who == (id_t)tid || who == 0xff) + if (ret == 0) { - return tid->current_priority; + lwp_put_to_user(buf, &statbuff, sizeof statbuff); + } + else + { + ret = GET_ERRNO(); } + return (ret < 0 ? GET_ERRNO() : ret); } - - return 0xff; +#else + if (!lwp_user_accessable((void *)buf, sizeof(struct stat))) + { + return -EFAULT; + } + int ret = fstat(file, buf); + return (ret < 0 ? GET_ERRNO() : ret); +#endif } -/* syscall: "setpriority" ret: "int" args: "int" "id_t" "int" */ -int sys_setpriority(int which, id_t who, int prio) +/* DFS and lwip definitions */ +#define IMPL_POLLIN (0x01) + +#define IMPL_POLLOUT (0x02) + +#define IMPL_POLLERR (0x04) +#define IMPL_POLLHUP (0x08) +#define IMPL_POLLNVAL (0x10) + +/* musl definitions */ +#define INTF_POLLIN 0x001 +#define INTF_POLLPRI 0x002 +#define INTF_POLLOUT 0x004 +#define INTF_POLLERR 0x008 +#define INTF_POLLHUP 0x010 +#define INTF_POLLNVAL 0x020 +#define INTF_POLLRDNORM 0x040 +#define INTF_POLLRDBAND 0x080 +#define INTF_POLLWRNORM 0x100 +#define INTF_POLLWRBAND 0x200 +#define INTF_POLLMSG 0x400 +#define INTF_POLLRDHUP 0x2000 + +#define INTF_POLLIN_MASK (INTF_POLLIN | INTF_POLLRDNORM | INTF_POLLRDBAND | INTF_POLLPRI) +#define INTF_POLLOUT_MASK (INTF_POLLOUT | INTF_POLLWRNORM | INTF_POLLWRBAND) + +static void musl2dfs_events(short *events) { - if (which == PRIO_PROCESS) + short origin_e = *events; + short result_e = 0; + + if (origin_e & INTF_POLLIN_MASK) { - rt_thread_t tid; + result_e |= IMPL_POLLIN; + } - tid = rt_thread_self(); - if ((who == (id_t)tid || who == 0xff) && (prio >= 0 && prio < RT_THREAD_PRIORITY_MAX)) - { - rt_thread_control(tid, RT_THREAD_CTRL_CHANGE_PRIORITY, &prio); - return 0; - } + if (origin_e & INTF_POLLOUT_MASK) + { + result_e |= IMPL_POLLOUT; } - return -1; -} + if (origin_e & INTF_POLLERR) + { + result_e |= IMPL_POLLERR; + } -/* syscall: "gettimeofday" ret: "int" args: "struct timeval *" "struct timezone *" */ -int sys_gettimeofday(struct timeval *tp, struct timezone *tzp) -{ - if (tp) + if (origin_e & INTF_POLLHUP) { - tp->tv_sec = rt_tick_get() / RT_TICK_PER_SECOND; - tp->tv_usec = (rt_tick_get() % RT_TICK_PER_SECOND) * (1000000 / RT_TICK_PER_SECOND); + result_e |= IMPL_POLLHUP; } - return 0; -} + if (origin_e & INTF_POLLNVAL) + { + result_e |= IMPL_POLLNVAL; + } -/* syscall: "settimeofday" ret: "int" args: "const struct timeval *" "const struct timezone *" */ -int sys_settimeofday(const struct timeval *tv, const struct timezone *tzp) -{ - return 0; + *events = result_e; } -/* syscall: "msgget" ret: "int" args: "key_t" "int" */ -int sys_msgget(key_t key, int msgflg) +static void dfs2musl_events(short *events) { - return -1; -} + short origin_e = *events; + short result_e = 0; -/* syscall: "msgsnd" ret: "int" args: "int" "const void *" "size_t" "int" */ -int sys_msgsend(int msqid, const void *msgp, size_t msgsz, int msgflg) -{ - return -1; -} + if (origin_e & IMPL_POLLIN) + { + result_e |= INTF_POLLIN_MASK; + } -/* syscall: "msgrcv" ret: "int" args: "int" "void *" "size_t" "long" "int" */ -int sys_msgrcv(int msqid, void *msgp, size_t msgsz, long msgtyp, int msgflg) -{ - return -1; -} + if (origin_e & IMPL_POLLOUT) + { + result_e |= INTF_POLLOUT_MASK; + } -/* syscall: "sys_log" ret: "int" args: "const char*" "size" */ -int sys_log(const char* log, int size) -{ - rt_device_t console = rt_console_get_device(); + if (origin_e & IMPL_POLLERR) + { + result_e |= INTF_POLLERR; + } - if (console) rt_device_write(console, -1, log, size); + if (origin_e & IMPL_POLLHUP) + { + result_e |= INTF_POLLHUP; + } - return 0; -} + if (origin_e & IMPL_POLLNVAL) + { + result_e |= INTF_POLLNVAL; + } -void *sys_malloc(size_t size) -{ - return rt_lwp_mem_malloc(size); + *events = result_e; } -void sys_free(void *addr) +int sys_poll(struct pollfd *fds, nfds_t nfds, int timeout) { - rt_lwp_mem_free(addr); -} + int ret = -1; + int i = 0; +#ifdef RT_USING_USERSPACE + struct pollfd *kfds = RT_NULL; -void *sys_realloc(void *rmem, size_t newsize) -{ - return rt_lwp_mem_realloc(rmem, newsize); -} + if (!lwp_user_accessable((void *)fds, nfds * sizeof *fds)) + { + return -EFAULT; + } -int sys_fstat(int file, struct stat *buf) -{ - return fstat(file, buf); -} + kfds = (struct pollfd *)kmem_get(nfds * sizeof *kfds); + if (!kfds) + { + return -ENOMEM; + } -int sys_notimpl(void) -{ - return -ENOSYS; -} + lwp_get_from_user(kfds, fds, nfds * sizeof *kfds); -const static void* func_table[] = -{ - (void *)sys_exit, // 0x01 - (void *)sys_read, // 0x02 - (void *)sys_write, // 0x03 - (void *)sys_lseek, // 0x04 - (void *)sys_open, // 0x05 - (void *)sys_close, // 0x06 - (void *)sys_ioctl, // 0x07 - - (void *)sys_nanosleep, // 0x08 - - (void *)sys_getpriority, // 0x09 - (void *)sys_setpriority, // 0x0a - - (void *)sys_gettimeofday, // 0x0b - (void *)sys_settimeofday, // 0x0c - - (void *)sys_malloc, // 0x0d - (void *)sys_free, // 0x0e - (void *)sys_realloc, //0x0f - (void *)sys_fstat, // 0x10 - (void *)poll, // 0x11 - - SYSCALL_NET(accept), // 0x12 - SYSCALL_NET(bind), // 0x13 - SYSCALL_NET(shutdown), // 0x14 - SYSCALL_NET(getpeername),// 0x15 - SYSCALL_NET(getsockname),// 0x16 - SYSCALL_NET(getsockopt), // 0x17 - SYSCALL_NET(setsockopt), // 0x18 - SYSCALL_NET(connect), // 0x19 - SYSCALL_NET(listen), // 0x1a - SYSCALL_NET(recv), // 0x1b - SYSCALL_NET(recvfrom), // 0x1c - SYSCALL_NET(send), // 0x1d - SYSCALL_NET(sendto), // 0x1e - SYSCALL_NET(socket), // 0x1f - - (void *)select, // 0x20 + for (i = 0; i < nfds; i++) + { + musl2dfs_events(&kfds[i].events); + } + ret = poll(kfds, nfds, timeout); + if (ret > 0) + { + for (i = 0; i < nfds; i++) + { + dfs2musl_events(&kfds->revents); + } + lwp_put_to_user(fds, kfds, nfds * sizeof *kfds); + } + + kmem_put(kfds); + return ret; +#else +#ifdef RT_USING_MUSL + for (i = 0; i < nfds; i++) + { + musl2dfs_events(&fds->events); + } +#endif /* RT_USING_MUSL */ + if (!lwp_user_accessable((void *)fds, nfds * sizeof *fds)) + { + return -EFAULT; + } + ret = poll(fds, nfds, timeout); +#ifdef RT_USING_MUSL + if (ret > 0) + { + for (i = 0; i < nfds; i++) + { + dfs2musl_events(&fds->revents); + } + } +#endif /* RT_USING_MUSL */ + return ret; +#endif /* RT_USING_USERSPACE */ +} + +int sys_select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, struct timeval *timeout) +{ +#ifdef RT_USING_USERSPACE + int ret = -1; + fd_set *kreadfds = RT_NULL, *kwritefds = RT_NULL, *kexceptfds = RT_NULL; + + if (readfds) + { + if (!lwp_user_accessable((void *)readfds, sizeof *readfds)) + { + SET_ERRNO(EFAULT); + goto quit; + } + kreadfds = (fd_set *)kmem_get(sizeof *kreadfds); + if (!kreadfds) + { + SET_ERRNO(ENOMEM); + goto quit; + } + lwp_get_from_user(kreadfds, readfds, sizeof *kreadfds); + } + if (writefds) + { + if (!lwp_user_accessable((void *)writefds, sizeof *writefds)) + { + SET_ERRNO(EFAULT); + goto quit; + } + kwritefds = (fd_set *)kmem_get(sizeof *kwritefds); + if (!kwritefds) + { + SET_ERRNO(ENOMEM); + goto quit; + } + lwp_get_from_user(kwritefds, writefds, sizeof *kwritefds); + } + if (exceptfds) + { + if (!lwp_user_accessable((void *)exceptfds, sizeof *exceptfds)) + { + SET_ERRNO(EFAULT); + goto quit; + } + kexceptfds = (fd_set *)kmem_get(sizeof *kexceptfds); + if (!kexceptfds) + { + SET_ERRNO(EINVAL); + goto quit; + } + lwp_get_from_user(kexceptfds, exceptfds, sizeof *kexceptfds); + } + + ret = select(nfds, kreadfds, kwritefds, kexceptfds, timeout); + if (kreadfds) + { + lwp_put_to_user(readfds, kreadfds, sizeof *kreadfds); + } + if (kwritefds) + { + lwp_put_to_user(writefds, kwritefds, sizeof *kwritefds); + } + if (kexceptfds) + { + lwp_put_to_user(exceptfds, kexceptfds, sizeof *kexceptfds); + } +quit: + if (kreadfds) + { + kmem_put(kreadfds); + } + if (kwritefds) + { + kmem_put(kwritefds); + } + if (kexceptfds) + { + kmem_put(kexceptfds); + } + return (ret < 0 ? GET_ERRNO() : ret); +#else + int ret; + + if (!lwp_user_accessable((void *)readfds, sizeof *readfds)) + { + return -EFAULT; + } + if (!lwp_user_accessable((void *)writefds, sizeof *writefds)) + { + return -EFAULT; + } + if (!lwp_user_accessable((void *)exceptfds, sizeof *exceptfds)) + { + return -EFAULT; + } + ret = select(nfds, readfds, writefds, exceptfds, timeout); + return (ret < 0 ? GET_ERRNO() : ret); +#endif +} + +int sys_unlink(const char *pathname) +{ +#ifdef RT_USING_USERSPACE + int ret = -1; + rt_size_t len = 0; + char *kname = RT_NULL; + int a_err = 0; + + lwp_user_strlen(pathname, &a_err); + if (a_err) + { + return -EFAULT; + } + + len = rt_strlen(pathname); + if (!len) + { + return -EINVAL; + } + + kname = (char *)kmem_get(len + 1); + if (!kname) + { + return -ENOMEM; + } + + lwp_get_from_user(kname, (void *)pathname, len + 1); + ret = unlink(kname); + + kmem_put(kname); + return (ret < 0 ? GET_ERRNO() : ret); +#else + int ret = 0; + ret = unlink(pathname); + return (ret < 0 ? GET_ERRNO() : ret); +#endif +} + +/* syscall: "nanosleep" ret: "int" args: "const struct timespec *" "struct timespec *" */ +int sys_nanosleep(const struct timespec *rqtp, struct timespec *rmtp) +{ + rt_tick_t tick; +#ifdef RT_USING_USERSPACE + struct timespec rqtp_k; + struct timespec rmtp_k; + + dbg_log(DBG_LOG, "sys_nanosleep\n"); + + if (!lwp_user_accessable((void *)rqtp, sizeof *rqtp)) + { + return -EFAULT; + } + + lwp_get_from_user(&rqtp_k, (void *)rqtp, sizeof rqtp_k); + + tick = rqtp_k.tv_sec * RT_TICK_PER_SECOND + ((uint64_t)rqtp_k.tv_nsec * RT_TICK_PER_SECOND) / 1000000000; + rt_thread_delay(tick); + + if (rmtp) + { + if (!lwp_user_accessable((void *)rmtp, sizeof *rmtp)) + { + return -EFAULT; + } + + tick = rt_tick_get() - tick; + /* get the passed time */ + rmtp_k.tv_sec = tick / RT_TICK_PER_SECOND; + rmtp_k.tv_nsec = (tick % RT_TICK_PER_SECOND) * (1000000000 / RT_TICK_PER_SECOND); + + lwp_put_to_user(rmtp, (void *)&rmtp_k, sizeof rmtp_k); + } +#else + dbg_log(DBG_LOG, "sys_nanosleep\n"); + + if (!lwp_user_accessable((void *)rqtp, sizeof *rqtp)) + { + return -EFAULT; + } + + tick = rqtp->tv_sec * RT_TICK_PER_SECOND + ((uint64_t)rqtp->tv_nsec * RT_TICK_PER_SECOND) / 1000000000; + rt_thread_delay(tick); + + if (rmtp) + { + if (!lwp_user_accessable((void *)rmtp, sizeof *rmtp)) + { + return -EFAULT; + } + + tick = rt_tick_get() - tick; + /* get the passed time */ + rmtp->tv_sec = tick / RT_TICK_PER_SECOND; + rmtp->tv_nsec = (tick % RT_TICK_PER_SECOND) * (1000000000 / RT_TICK_PER_SECOND); + } +#endif + + return 0; +} + +/* syscall: "gettimeofday" ret: "int" args: "struct timeval *" "struct timezone *" */ +int sys_gettimeofday(struct timeval *tp, struct timezone *tzp) +{ +#ifdef RT_USING_USERSPACE + struct timeval t_k; + + if (tp) + { + if (!lwp_user_accessable((void *)tp, sizeof *tp)) + { + return -EFAULT; + } + + t_k.tv_sec = rt_tick_get() / RT_TICK_PER_SECOND; + t_k.tv_usec = (rt_tick_get() % RT_TICK_PER_SECOND) * (1000000 / RT_TICK_PER_SECOND); + + lwp_put_to_user(tp, (void *)&t_k, sizeof t_k); + } +#else + if (tp) + { + if (!lwp_user_accessable((void *)tp, sizeof *tp)) + { + return -EFAULT; + } + tp->tv_sec = rt_tick_get() / RT_TICK_PER_SECOND; + tp->tv_usec = (rt_tick_get() % RT_TICK_PER_SECOND) * (1000000 / RT_TICK_PER_SECOND); + } +#endif + + return 0; +} + +int sys_settimeofday(const struct timeval *tv, const struct timezone *tzp) +{ + return 0; +} + +#ifdef RT_USING_GDBSERVER +int lwp_execve(char *filename, int debug, int argc, char **argv, char **envp); +#else +int lwp_execve(char *filename, int argc, char **argv, char **envp); +#endif + +int sys_exec(char *filename, int argc, char **argv, char **envp) +{ +#ifdef RT_USING_GDBSERVER + return lwp_execve(filename, 0, argc, argv, envp); +#else + return lwp_execve(filename, argc, argv, envp); +#endif +} + +int sys_kill(int pid, int sig) +{ + int ret = 0; + ret = lwp_kill(pid, sig); + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_getpid(void) +{ + return lwp_getpid(); +} + +/* syscall: "getpriority" ret: "int" args: "int" "id_t" */ +int sys_getpriority(int which, id_t who) +{ + if (which == PRIO_PROCESS) + { + rt_thread_t tid; + + tid = rt_thread_self(); + if (who == (id_t)(rt_size_t)tid || who == 0xff) + { + return tid->current_priority; + } + } + + return 0xff; +} + +/* syscall: "setpriority" ret: "int" args: "int" "id_t" "int" */ +int sys_setpriority(int which, id_t who, int prio) +{ + if (which == PRIO_PROCESS) + { + rt_thread_t tid; + + tid = rt_thread_self(); + if ((who == (id_t)(rt_size_t)tid || who == 0xff) && (prio >= 0 && prio < RT_THREAD_PRIORITY_MAX)) + { + rt_thread_control(tid, RT_THREAD_CTRL_CHANGE_PRIORITY, &prio); + return 0; + } + } + + return -1; +} + +rt_sem_t sys_sem_create(const char *name, rt_uint32_t value, rt_uint8_t flag) +{ + rt_sem_t sem = rt_sem_create(name, value, flag); + if (lwp_user_object_add(lwp_self(), (rt_object_t)sem) != 0) + { + rt_sem_delete(sem); + sem = NULL; + } + return sem; +} + +rt_err_t sys_sem_delete(rt_sem_t sem) +{ + return lwp_user_object_delete(lwp_self(), (rt_object_t)sem); +} + +rt_err_t sys_sem_take(rt_sem_t sem, rt_int32_t time) +{ + return rt_sem_take_interruptible(sem, time); +} + +rt_err_t sys_sem_release(rt_sem_t sem) +{ + return rt_sem_release(sem); +} + +rt_mutex_t sys_mutex_create(const char *name, rt_uint8_t flag) +{ + rt_mutex_t mutex = rt_mutex_create(name, flag); + if (lwp_user_object_add(lwp_self(), (rt_object_t)mutex) != 0) + { + rt_mutex_delete(mutex); + mutex = NULL; + } + return mutex; +} + +rt_err_t sys_mutex_delete(rt_mutex_t mutex) +{ + return lwp_user_object_delete(lwp_self(), (rt_object_t)mutex); +} + +rt_err_t sys_mutex_take(rt_mutex_t mutex, rt_int32_t time) +{ + return rt_mutex_take_interruptible(mutex, time); +} + +rt_err_t sys_mutex_release(rt_mutex_t mutex) +{ + return rt_mutex_release(mutex); +} + +#ifdef RT_USING_USERSPACE +/* memory allocation */ +extern rt_base_t lwp_brk(void *addr); +rt_base_t sys_brk(void *addr) +{ + return lwp_brk(addr); +} + +extern void *lwp_mmap2(void *addr, size_t length, int prot, + int flags, int fd, off_t pgoffset); +void *sys_mmap2(void *addr, size_t length, int prot, + int flags, int fd, off_t pgoffset) +{ + return lwp_mmap2(addr, length, prot, flags, fd, pgoffset); +} + +extern int lwp_munmap(void *addr); +int sys_munmap(void *addr, size_t length) +{ + return lwp_munmap(addr); +} +#endif + +rt_event_t sys_event_create(const char *name, rt_uint8_t flag) +{ + rt_event_t event = rt_event_create(name, flag); + if (lwp_user_object_add(lwp_self(), (rt_object_t)event) != 0) + { + rt_event_delete(event); + event = NULL; + } + return event; +} + +rt_err_t sys_event_delete(rt_event_t event) +{ + return lwp_user_object_delete(lwp_self(), (rt_object_t)event); +} + +rt_err_t sys_event_send(rt_event_t event, rt_uint32_t set) +{ + return rt_event_send(event, set); +} + +rt_err_t sys_event_recv(rt_event_t event, + rt_uint32_t set, + rt_uint8_t opt, + rt_int32_t timeout, + rt_uint32_t *recved) +{ + if (!lwp_user_accessable((void *)recved, sizeof(rt_uint32_t *))) + { + return -EFAULT; + } + return rt_event_recv(event, set, opt, timeout, recved); +} + +rt_mailbox_t sys_mb_create(const char *name, rt_size_t size, rt_uint8_t flag) +{ + rt_mailbox_t mb = rt_mb_create(name, size, flag); + if (lwp_user_object_add(lwp_self(), (rt_object_t)mb) != 0) + { + rt_mb_delete(mb); + mb = NULL; + } + return mb; +} + +rt_err_t sys_mb_delete(rt_mailbox_t mb) +{ + return lwp_user_object_delete(lwp_self(), (rt_object_t)mb); +} + +rt_err_t sys_mb_send(rt_mailbox_t mb, rt_uint32_t value) +{ + return rt_mb_send(mb, value); +} + +rt_err_t sys_mb_send_wait(rt_mailbox_t mb, + rt_uint32_t value, + rt_int32_t timeout) +{ + return rt_mb_send_wait(mb, value, timeout); +} + +rt_err_t sys_mb_recv(rt_mailbox_t mb, rt_uint32_t *value, rt_int32_t timeout) +{ + if (!lwp_user_accessable((void *)value, sizeof(rt_uint32_t *))) + { + return -EFAULT; + } + return rt_mb_recv(mb, (rt_ubase_t *)value, timeout); +} + +rt_mq_t sys_mq_create(const char *name, + rt_size_t msg_size, + rt_size_t max_msgs, + rt_uint8_t flag) +{ + rt_mq_t mq = rt_mq_create(name, msg_size, max_msgs, flag); + if (lwp_user_object_add(lwp_self(), (rt_object_t)mq) != 0) + { + rt_mq_delete(mq); + mq = NULL; + } + return mq; +} + +rt_err_t sys_mq_delete(rt_mq_t mq) +{ + return lwp_user_object_delete(lwp_self(), (rt_object_t)mq); +} + +rt_err_t sys_mq_send(rt_mq_t mq, void *buffer, rt_size_t size) +{ + if (!lwp_user_accessable((void *)buffer, size)) + { + return -EFAULT; + } + return rt_mq_send(mq, buffer, size); +} + +rt_err_t sys_mq_urgent(rt_mq_t mq, void *buffer, rt_size_t size) +{ + if (!lwp_user_accessable((void *)buffer, size)) + { + return -EFAULT; + } + return rt_mq_urgent(mq, buffer, size); +} + +rt_err_t sys_mq_recv(rt_mq_t mq, + void *buffer, + rt_size_t size, + rt_int32_t timeout) +{ + if (!lwp_user_accessable((void *)buffer, size)) + { + return -EFAULT; + } + return rt_mq_recv(mq, buffer, size, timeout); +} + +static void timer_timeout_callback(void *parameter) +{ + rt_sem_t sem = (rt_sem_t)parameter; + rt_sem_release(sem); +} + +rt_timer_t sys_timer_create(const char *name, + void *data, + rt_tick_t time, + rt_uint8_t flag) +{ + rt_timer_t timer = rt_timer_create(name, timer_timeout_callback, (void *)data, time, flag); + if (lwp_user_object_add(lwp_self(), (rt_object_t)timer) != 0) + { + rt_timer_delete(timer); + timer = NULL; + } + return timer; +} + +rt_err_t sys_timer_delete(rt_timer_t timer) +{ + return lwp_user_object_delete(lwp_self(), (rt_object_t)timer); +} + +rt_err_t sys_timer_start(rt_timer_t timer) +{ + return rt_timer_start(timer); +} + +rt_err_t sys_timer_stop(rt_timer_t timer) +{ + return rt_timer_stop(timer); +} + +rt_err_t sys_timer_control(rt_timer_t timer, int cmd, void *arg) +{ + return rt_timer_control(timer, cmd, arg); +} + +rt_thread_t sys_thread_create(void *arg[]) +{ + rt_base_t level = 0; + void *user_stack = 0; + struct rt_lwp *lwp = 0; + rt_thread_t thread = RT_NULL; + int tid = 0; + + lwp = rt_thread_self()->lwp; + lwp_ref_inc(lwp); +#ifdef RT_USING_USERSPACE + user_stack = lwp_map_user(lwp, 0, (size_t)arg[3], 0); + if (!user_stack) + { + goto fail; + } + if ((tid = lwp_tid_get()) == 0) + { + goto fail; + } + thread = rt_thread_create((const char *)arg[0], + lwp_user_thread, + (void *)arg[2], + ALLOC_KERNEL_STACK_SIZE, + (rt_uint8_t)(size_t)arg[4], + (rt_uint32_t)(rt_size_t)arg[5]); + if (!thread) + { + goto fail; + } + + thread->cleanup = lwp_cleanup; + thread->user_entry = (void (*)(void *))arg[1]; + thread->user_stack = (void *)user_stack; + thread->user_stack_size = (rt_size_t)arg[3]; +#else + rt_uint32_t kstack_size = (rt_uint32_t)arg[7]; + if (kstack_size < ALLOC_KERNEL_STACK_SIZE_MIN) + { + /* When kstack size is 0, the default size of the kernel stack is used */ + kstack_size = kstack_size ? ALLOC_KERNEL_STACK_SIZE_MIN : ALLOC_KERNEL_STACK_SIZE; + } + else if (kstack_size > ALLOC_KERNEL_STACK_SIZE_MAX) + { + kstack_size = ALLOC_KERNEL_STACK_SIZE_MAX; + } + + user_stack = (void *)arg[3]; + if ((!user_stack) || ((rt_uint32_t)arg[6] == RT_NULL)) + { + goto fail; + } + + if ((tid = lwp_tid_get()) == 0) + { + goto fail; + } + + thread = rt_thread_create((const char *)arg[0], lwp_user_thread, (void *)arg[2], kstack_size, (rt_uint8_t)(size_t)arg[5], (rt_uint32_t)arg[6]); + if (!thread) + { + goto fail; + } + thread->cleanup = lwp_cleanup; + thread->user_entry = (void (*)(void *))arg[1]; + thread->user_stack = (void *)user_stack; + thread->user_stack_size = (uint32_t)arg[4]; + rt_memset(thread->user_stack, '#', thread->user_stack_size); +#endif /* RT_USING_USERSPACE */ + + thread->lwp = (void*)lwp; + thread->tid = tid; + lwp_tid_set_thread(tid, thread); + + level = rt_hw_interrupt_disable(); + rt_list_insert_after(&lwp->t_grp, &thread->sibling); + rt_hw_interrupt_enable(level); + + return thread; + +fail: + lwp_tid_put(tid); + if (lwp) + { + lwp_ref_dec(lwp); + } + return RT_NULL; +} +#ifdef ARCH_MM_MMU +#define CLONE_VM 0x00000100 +#define CLONE_FS 0x00000200 +#define CLONE_FILES 0x00000400 +#define CLONE_SIGHAND 0x00000800 +#define CLONE_PTRACE 0x00002000 +#define CLONE_VFORK 0x00004000 +#define CLONE_PARENT 0x00008000 +#define CLONE_THREAD 0x00010000 +#define CLONE_NEWNS 0x00020000 +#define CLONE_SYSVSEM 0x00040000 +#define CLONE_SETTLS 0x00080000 +#define CLONE_PARENT_SETTID 0x00100000 +#define CLONE_CHILD_CLEARTID 0x00200000 +#define CLONE_DETACHED 0x00400000 +#define CLONE_UNTRACED 0x00800000 +#define CLONE_CHILD_SETTID 0x01000000 +#define CLONE_NEWCGROUP 0x02000000 +#define CLONE_NEWUTS 0x04000000 +#define CLONE_NEWIPC 0x08000000 +#define CLONE_NEWUSER 0x10000000 +#define CLONE_NEWPID 0x20000000 +#define CLONE_NEWNET 0x40000000 +#define CLONE_IO 0x80000000 + +/* arg[] -> flags + * stack + * new_tid + * tls + * set_clear_tid_address + * quit_func + * start_args + * */ +#define SYS_CLONE_ARGS_NR 7 +int lwp_set_thread_context(void (*exit)(void), void *new_thread_stack, + void *user_stack, void **thread_sp); + +long sys_clone(void *arg[]); +void sys_clone_exit(void); +long _sys_clone(void *arg[]) +{ + rt_base_t level = 0; + struct rt_lwp *lwp = 0; + rt_thread_t thread = RT_NULL; + rt_thread_t self = RT_NULL; + int tid = 0; + + unsigned long flags = 0; + void *user_stack = RT_NULL; + int *new_tid = RT_NULL; + void *tls = RT_NULL; + /* + musl call flags (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND + | CLONE_THREAD | CLONE_SYSVSEM | CLONE_SETTLS + | CLONE_PARENT_SETTID | CLONE_CHILD_CLEARTID | CLONE_DETACHED); + */ + + /* check args */ + if (!lwp_user_accessable(arg, sizeof(void *[SYS_CLONE_ARGS_NR]))) + { + return -EFAULT; + } + + flags = (unsigned long)(size_t)arg[0]; + if ((flags & (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_THREAD | CLONE_SYSVSEM)) + != (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_THREAD | CLONE_SYSVSEM)) + { + return -EINVAL; + } + + user_stack = arg[1]; + new_tid = (int *)arg[2]; + tls = (void *)arg[3]; + + if ((flags & CLONE_PARENT_SETTID) == CLONE_PARENT_SETTID) + { + if (!lwp_user_accessable(new_tid, sizeof(int))) + { + return -EFAULT; + } + } + + self = rt_thread_self(); + lwp = self->lwp; + lwp_ref_inc(lwp); + if (!user_stack) + { + SET_ERRNO(EINVAL); + goto fail; + } + if ((tid = lwp_tid_get()) == 0) + { + SET_ERRNO(ENOMEM); + goto fail; + } + + thread = rt_thread_create(self->name, + RT_NULL, + RT_NULL, + self->stack_size, + self->init_priority, + self->init_tick); + if (!thread) + { + goto fail; + } + + thread->cleanup = lwp_cleanup; + thread->user_entry = RT_NULL; + thread->user_stack = RT_NULL; + thread->user_stack_size = 0; + thread->lwp = (void *)lwp; + thread->tid = tid; + + if ((flags & CLONE_SETTLS) == CLONE_SETTLS) + { + thread->thread_idr = tls; + } + if ((flags & CLONE_PARENT_SETTID) == CLONE_PARENT_SETTID) + { + *new_tid = (int)(tid); + } + if ((flags & CLONE_CHILD_CLEARTID) == CLONE_CHILD_CLEARTID) + { + thread->clear_child_tid = (int *)arg[4]; + } + + level = rt_hw_interrupt_disable(); + rt_list_insert_after(&lwp->t_grp, &thread->sibling); + rt_hw_interrupt_enable(level); + + /* copy origin stack */ + rt_memcpy(thread->stack_addr, self->stack_addr, thread->stack_size); + lwp_tid_set_thread(tid, thread); + lwp_set_thread_context(sys_clone_exit, + (void *)((char *)thread->stack_addr + thread->stack_size), + user_stack, &thread->sp); + /* new thread never reach there */ + rt_thread_startup(thread); + return (long)tid; +fail: + lwp_tid_put(tid); + if (lwp) + { + lwp_ref_dec(lwp); + } + return GET_ERRNO(); +} + +int lwp_dup_user(struct lwp_avl_struct* ptree, void *arg); +void *lwp_get_user_sp(void); + +static int _copy_process(struct rt_lwp *dest_lwp, struct rt_lwp *src_lwp) +{ + return lwp_avl_traversal(src_lwp->map_area, lwp_dup_user, dest_lwp); +} + +static void lwp_struct_copy(struct rt_lwp *dst, struct rt_lwp *src) +{ +#ifdef RT_USING_USERSPACE + dst->end_heap = src->end_heap; +#endif + dst->lwp_type = src->lwp_type; + dst->text_entry = src->text_entry; + dst->text_size = src->text_size; + dst->data_entry = src->data_entry; + dst->data_size = src->data_size; + dst->args = src->args; + dst->leader = 0; + dst->session = src->session; + dst->tty_old_pgrp = 0; + dst->__pgrp = src->__pgrp; + dst->tty = src->tty; + rt_memcpy(dst->cmd, src->cmd, RT_NAME_MAX); + + dst->sa_flags = src->sa_flags; + dst->signal_mask = src->signal_mask; + rt_memcpy(dst->signal_handler, src->signal_handler, sizeof dst->signal_handler); +} + +static int lwp_copy_files(struct rt_lwp *dst, struct rt_lwp *src) +{ + struct dfs_fdtable *dst_fdt; + struct dfs_fdtable *src_fdt; + + src_fdt = &src->fdt; + dst_fdt = &dst->fdt; + /* init fds */ + dst_fdt->fds = rt_calloc(src_fdt->maxfd, sizeof(void *)); + if (dst_fdt->fds) + { + struct dfs_fd *d_s; + struct dfs_fd *d_d; + int i; + + dst_fdt->maxfd = src_fdt->maxfd; + + dfs_fd_lock(); + /* copy stdio */ + for (i = 0; i < src_fdt->maxfd; i++) + { + d_s = fdt_fd_get(src_fdt, i); + if (d_s) + { + dfs_fm_lock(); + if (!d_s->fnode) + { + dfs_fm_unlock(); + continue; + } + d_s->fnode->ref_count++; + dfs_fm_unlock(); + + /* alloc dfs_fd struct */ + d_d = (struct dfs_fd *)rt_calloc(1, sizeof(struct dfs_fd)); + if (!d_d) + { + dfs_fd_unlock(); + return -1; + } + dst_fdt->fds[i] = d_d; + d_d->magic = d_s->magic; + d_d->ref_count = 1; + d_d->pos = d_s->pos; + d_d->fnode = d_s->fnode; + d_d->data = d_s->data; + } + } + dfs_fd_unlock(); + return 0; + } + return -1; +} + +int sys_fork(void); +int sys_vfork(void); +void sys_fork_exit(void); +int _sys_fork(void) +{ + rt_base_t level; + int tid = 0; + struct rt_lwp *lwp = RT_NULL; + struct rt_lwp *self_lwp = RT_NULL; + rt_thread_t thread = RT_NULL; + rt_thread_t self_thread = RT_NULL; + void *user_stack = RT_NULL; + + /* new lwp */ + lwp = lwp_new(); + if (!lwp) + { + SET_ERRNO(ENOMEM); + goto fail; + } + + /* new tid */ + if ((tid = lwp_tid_get()) == 0) + { + SET_ERRNO(ENOMEM); + goto fail; + } + + /* user space init */ + if (lwp_user_space_init(lwp) != 0) + { + SET_ERRNO(ENOMEM); + goto fail; + } + + self_lwp = lwp_self(); + + /* copy process */ + if (_copy_process(lwp, self_lwp) != 0) + { + SET_ERRNO(ENOMEM); + goto fail; + } + + /* copy lwp struct data */ + lwp_struct_copy(lwp, self_lwp); + + /* copy files */ + if (lwp_copy_files(lwp, self_lwp) != 0) + { + SET_ERRNO(ENOMEM); + goto fail; + } + + /* create thread */ + self_thread = rt_thread_self(); + + thread = rt_thread_create(self_thread->name, + RT_NULL, + RT_NULL, + self_thread->stack_size, + self_thread->init_priority, + self_thread->init_tick); + if (!thread) + { + goto fail; + } + + thread->cleanup = self_thread->cleanup; + thread->user_entry = self_thread->user_entry; + thread->user_stack = self_thread->user_stack; + thread->user_stack_size = self_thread->user_stack_size; + thread->signal_mask = self_thread->signal_mask; + thread->thread_idr = self_thread->thread_idr; + thread->lwp = (void *)lwp; + thread->tid = tid; + + level = rt_hw_interrupt_disable(); + + /* add thread to lwp process */ + rt_list_insert_after(&lwp->t_grp, &thread->sibling); + + /* lwp add to children link */ + lwp->sibling = self_lwp->first_child; + self_lwp->first_child = lwp; + lwp->parent = self_lwp; + + rt_hw_interrupt_enable(level); + + /* copy origin stack */ + rt_memcpy(thread->stack_addr, self_thread->stack_addr, self_thread->stack_size); + lwp_tid_set_thread(tid, thread); + + /* duplicate user objects */ + lwp_user_object_dup(lwp, self_lwp); + + level = rt_hw_interrupt_disable(); + user_stack = lwp_get_user_sp(); + rt_hw_interrupt_enable(level); + + lwp_set_thread_context(sys_fork_exit, + (void *)((char *)thread->stack_addr + thread->stack_size), + user_stack, &thread->sp); + /* new thread never reach there */ + level = rt_hw_interrupt_disable(); + if (lwp->tty != RT_NULL) + { + lwp->tty->foreground = lwp; + } + rt_hw_interrupt_enable(level); + rt_thread_startup(thread); + return lwp_to_pid(lwp); +fail: + if (tid != 0) + { + lwp_tid_put(tid); + } + if (lwp) + { + lwp_ref_dec(lwp); + } + return GET_ERRNO(); +} + +size_t lwp_user_strlen(const char *s, int *err) +{ + size_t len = 0; + + while (1) + { + if (!lwp_user_accessable((void *)(s + len), sizeof(char))) + { + if (err) + { + *err = 1; + } + return 0; + } + if (s[len] == '\0') + { + if (err) + { + *err = 0; + } + return len; + } + len++; + } +} + +struct process_aux *lwp_argscopy(struct rt_lwp *lwp, int argc, char **argv, char **envp); +int lwp_load(const char *filename, struct rt_lwp *lwp, uint8_t *load_addr, size_t addr_size, struct process_aux *aux); +void lwp_exec_user(void *args, void *kernel_stack, void *user_entry); +void lwp_user_obj_free(struct rt_lwp *lwp); + +#define _swap_lwp_data(lwp_used, lwp_new, type, member) \ + do {\ + type tmp;\ + tmp = lwp_used->member;\ + lwp_used->member = lwp_new->member;\ + lwp_new->member = tmp;\ + } while (0) + +static char *_insert_args(int new_argc, char *new_argv[], struct lwp_args_info *args) +{ + void *page = NULL; + int err = 0; + char **nargv; + char **nenvp; + char *p; + int i, len; + int nsize; + + if (new_argc == 0) + { + goto quit; + } + page = rt_pages_alloc(0); /* 1 page */ + if (!page) + { + goto quit; + } + + nsize = new_argc * sizeof(char *); + for (i = 0; i < new_argc; i++) + { + nsize += rt_strlen(new_argv[i]) + 1; + } + if (nsize + args->size > ARCH_PAGE_SIZE) + { + err = 1; + goto quit; + } + nargv = (char **)page; + nenvp = nargv + args->argc + new_argc + 1; + p = (char *)(nenvp + args->envc + 1); + /* insert argv */ + for (i = 0; i < new_argc; i++) + { + nargv[i] = p; + len = rt_strlen(new_argv[i]) + 1; + rt_memcpy(p, new_argv[i], len); + p += len; + } + /* copy argv */ + nargv += new_argc; + for (i = 0; i < args->argc; i++) + { + nargv[i] = p; + len = rt_strlen(args->argv[i]) + 1; + rt_memcpy(p, args->argv[i], len); + p += len; + } + nargv[i] = NULL; + /* copy envp */ + for (i = 0; i < args->envc; i++) + { + nenvp[i] = p; + len = rt_strlen(args->envp[i]) + 1; + rt_memcpy(p, args->envp[i], len); + p += len; + } + nenvp[i] = NULL; + + /* update args */ + args->argv = (char **)page; + args->argc = args->argc + new_argc; + args->envp = args->argv + args->argc + 1; + /* args->envc no change */ + args->size = args->size + nsize; + +quit: + if (err && page) + { + rt_pages_free(page, 0); + page = NULL; + } + return page; +} + +#define INTERP_BUF_SIZE 128 +static char *_load_script(const char *filename, struct lwp_args_info *args) +{ + void *page = NULL; + char *new_page; + int fd = -1; + int len; + char interp[INTERP_BUF_SIZE]; + char *cp; + char *i_name; + char *i_arg; + + fd = open(filename, O_BINARY | O_RDONLY, 0); + if (fd < 0) + { + goto quit; + } + len = read(fd, interp, INTERP_BUF_SIZE); + if (len < 2) + { + goto quit; + } + + if ((interp[0] != '#') || (interp[1] != '!')) + { + goto quit; + } + + if (len == INTERP_BUF_SIZE) + { + len--; + } + interp[len] = '\0'; + + if ((cp = strchr(interp, '\n')) == NULL) + { + cp = interp + INTERP_BUF_SIZE - 1; + } + *cp = '\0'; + while (cp > interp) + { + cp--; + if ((*cp == ' ') || (*cp == '\t')) + { + *cp = '\0'; + } + else + { + break; + } + } + for (cp = interp + 2; (*cp == ' ') || (*cp == '\t'); cp++) + { + /* nothing */ + } + if (*cp == '\0') + { + goto quit; /* No interpreter name found */ + } + i_name = cp; + i_arg = NULL; + for (; *cp && (*cp != ' ') && (*cp != '\t'); cp++) + { + /* nothing */ + } + while ((*cp == ' ') || (*cp == '\t')) + { + *cp++ = '\0'; + } + if (*cp) + { + i_arg = cp; + } + + if (i_arg) + { + new_page = _insert_args(1, &i_arg, args); + rt_pages_free(page, 0); + page = new_page; + if (!page) + { + goto quit; + } + } + new_page = _insert_args(1, &i_name, args); + rt_pages_free(page, 0); + page = new_page; + +quit: + if (fd >= 0) + { + close(fd); + } + return page; +} + +int load_ldso(struct rt_lwp *lwp, char *exec_name, char *const argv[], char *const envp[]) +{ + int ret = -1; + int i; + void *page; + void *new_page; + int argc = 0; + int envc = 0; + int size; + char **kargv; + char **kenvp; + size_t len; + char *p; + char *i_arg; + struct lwp_args_info args_info; + struct process_aux *aux; + + size = sizeof(char *); + if (argv) + { + while (1) + { + if (!argv[argc]) + { + break; + } + len = rt_strlen((const char *)argv[argc]); + size += sizeof(char *) + len + 1; + argc++; + } + } + if (envp) + { + while (1) + { + if (!envp[envc]) + { + break; + } + len = rt_strlen((const char *)envp[envc]); + size += sizeof(char *) + len + 1; + envc++; + } + } + + page = rt_pages_alloc(0); /* 1 page */ + if (!page) + { + SET_ERRNO(ENOMEM); + goto quit; + } + kargv = (char **)page; + kenvp = kargv + argc + 1; + p = (char *)(kenvp + envc + 1); + /* copy argv */ + if (argv) + { + for (i = 0; i < argc; i++) + { + kargv[i] = p; + len = rt_strlen(argv[i]) + 1; + rt_memcpy(p, argv[i], len); + p += len; + } + kargv[i] = NULL; + } + /* copy envp */ + if (envp) + { + for (i = 0; i < envc; i++) + { + kenvp[i] = p; + len = rt_strlen(envp[i]) + 1; + rt_memcpy(p, envp[i], len); + p += len; + } + kenvp[i] = NULL; + } + + args_info.argc = argc; + args_info.argv = kargv; + args_info.envc = envc; + args_info.envp = kenvp; + args_info.size = size; + + new_page = _insert_args(1, &exec_name, &args_info); + rt_pages_free(page, 0); + page = new_page; + if (!page) + { + SET_ERRNO(ENOMEM); + goto quit; + } + + i_arg = "-e"; + new_page = _insert_args(1, &i_arg, &args_info); + rt_pages_free(page, 0); + page = new_page; + if (!page) + { + SET_ERRNO(ENOMEM); + goto quit; + } + + i_arg = "ld.so"; + new_page = _insert_args(1, &i_arg, &args_info); + rt_pages_free(page, 0); + page = new_page; + if (!page) + { + SET_ERRNO(ENOMEM); + goto quit; + } + + if ((aux = lwp_argscopy(lwp, args_info.argc, args_info.argv, args_info.envp)) == NULL) + { + SET_ERRNO(ENOMEM); + goto quit; + } + + ret = lwp_load("/bin/ld.so", lwp, RT_NULL, 0, aux); + + rt_strncpy(lwp->cmd, exec_name, RT_NAME_MAX); +quit: + if (page) + { + rt_pages_free(page, 0); + } + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_execve(const char *path, char *const argv[], char *const envp[]) +{ + int ret = -1; + int argc = 0; + int envc = 0; + void *page = NULL; + void *new_page; + int size = 0; + size_t len; + int access_err; + char **kargv; + char **kenvp; + char *p; + struct rt_lwp *new_lwp = NULL; + struct rt_lwp *lwp; + rt_base_t level; + int uni_thread; + rt_thread_t thread; + struct process_aux *aux; + int i; + struct lwp_args_info args_info; + + lwp = lwp_self(); + thread = rt_thread_self(); + uni_thread = 1; + level = rt_hw_interrupt_disable(); + if (lwp->t_grp.prev != &thread->sibling) + { + uni_thread = 0; + } + if (lwp->t_grp.next != &thread->sibling) + { + uni_thread = 0; + } + rt_hw_interrupt_enable(level); + if (!uni_thread) + { + SET_ERRNO(EINVAL); + goto quit; + } + + len = lwp_user_strlen(path, &access_err); + if (access_err) + { + SET_ERRNO(EFAULT); + goto quit; + } + + size += sizeof(char *); + if (argv) + { + while (1) + { + if (!lwp_user_accessable((void *)(argv + argc), sizeof(char *))) + { + SET_ERRNO(EFAULT); + goto quit; + } + if (!argv[argc]) + { + break; + } + len = lwp_user_strlen((const char *)argv[argc], &access_err); + if (access_err) + { + SET_ERRNO(EFAULT); + goto quit; + } + size += sizeof(char *) + len + 1; + argc++; + } + } + size += sizeof(char *); + if (envp) + { + while (1) + { + if (!lwp_user_accessable((void *)(envp + envc), sizeof(char *))) + { + SET_ERRNO(EFAULT); + goto quit; + } + if (!envp[envc]) + { + break; + } + len = lwp_user_strlen((const char *)envp[envc], &access_err); + if (access_err) + { + SET_ERRNO(EFAULT); + goto quit; + } + size += sizeof(char *) + len + 1; + envc++; + } + } + if (size > ARCH_PAGE_SIZE) + { + SET_ERRNO(EINVAL); + goto quit; + } + page = rt_pages_alloc(0); /* 1 page */ + if (!page) + { + SET_ERRNO(ENOMEM); + goto quit; + } + + kargv = (char **)page; + kenvp = kargv + argc + 1; + p = (char *)(kenvp + envc + 1); + /* copy argv */ + if (argv) + { + for (i = 0; i < argc; i++) + { + kargv[i] = p; + len = rt_strlen(argv[i]) + 1; + rt_memcpy(p, argv[i], len); + p += len; + } + kargv[i] = NULL; + } + /* copy envp */ + if (envp) + { + for (i = 0; i < envc; i++) + { + kenvp[i] = p; + len = rt_strlen(envp[i]) + 1; + rt_memcpy(p, envp[i], len); + p += len; + } + kenvp[i] = NULL; + } + + /* alloc new lwp to operation */ + new_lwp = (struct rt_lwp *)rt_malloc(sizeof(struct rt_lwp)); + if (!new_lwp) + { + SET_ERRNO(ENOMEM); + goto quit; + } + rt_memset(new_lwp, 0, sizeof(struct rt_lwp)); + new_lwp->ref = 1; + lwp_user_object_lock_init(new_lwp); + ret = arch_user_space_init(new_lwp); + if (ret != 0) + { + SET_ERRNO(ENOMEM); + goto quit; + } + /* file is a script ? */ + args_info.argc = argc; + args_info.argv = kargv; + args_info.envc = envc; + args_info.envp = kenvp; + args_info.size = size; + while (1) + { + new_page = _load_script(path, &args_info); + if (!new_page) + { + break; + } + rt_pages_free(page, 0); + page = new_page; + path = args_info.argv[0]; + } + + /* now load elf */ + if ((aux = lwp_argscopy(new_lwp, args_info.argc, args_info.argv, args_info.envp)) == NULL) + { + SET_ERRNO(ENOMEM); + goto quit; + } + ret = lwp_load(path, new_lwp, RT_NULL, 0, aux); + if (ret == 1) + { + /* dynamic */ + lwp_unmap_user(new_lwp, (void *)(USER_VADDR_TOP - ARCH_PAGE_SIZE)); + ret = load_ldso(new_lwp, (char *)path, args_info.argv, args_info.envp); + } + if (ret == RT_EOK) + { + int off = 0; + int last_backslash = 0; + char *run_name = args_info.argv[0]; + + /* clear all user objects */ + lwp_user_object_clear(lwp); + + /* find last \ or / */ + while (1) + { + char c = run_name[off++]; + + if (c == '\0') + { + break; + } + if (c == '\\' || c == '/') + { + last_backslash = off; + } + } + + /* load ok, now set thread name and swap the data of lwp and new_lwp */ + level = rt_hw_interrupt_disable(); + + rt_strncpy(thread->name, run_name + last_backslash, RT_NAME_MAX); + + rt_pages_free(page, 0); + +#ifdef RT_USING_USERSPACE + _swap_lwp_data(lwp, new_lwp, rt_mmu_info, mmu_info); + _swap_lwp_data(lwp, new_lwp, struct lwp_avl_struct *, map_area); + _swap_lwp_data(lwp, new_lwp, size_t, end_heap); +#endif + _swap_lwp_data(lwp, new_lwp, uint8_t, lwp_type); + _swap_lwp_data(lwp, new_lwp, void *, text_entry); + _swap_lwp_data(lwp, new_lwp, uint32_t, text_size); + _swap_lwp_data(lwp, new_lwp, void *, data_entry); + _swap_lwp_data(lwp, new_lwp, uint32_t, data_size); + + _swap_lwp_data(lwp, new_lwp, void *, args); + + rt_memset(&thread->signal_mask, 0, sizeof(thread->signal_mask)); + rt_memset(&thread->signal_mask_bak, 0, sizeof(thread->signal_mask_bak)); + lwp->sa_flags = 0; + rt_memset(&lwp->signal_mask, 0, sizeof(lwp->signal_mask)); + rt_memset(&lwp->signal_mask_bak, 0, sizeof(lwp->signal_mask_bak)); + rt_memset(lwp->signal_handler, 0, sizeof(lwp->signal_handler)); + + /* to do: clsoe files with flag CLOEXEC */ + + lwp_mmu_switch(thread); + + rt_hw_interrupt_enable(level); + + lwp_ref_dec(new_lwp); + lwp_exec_user(lwp->args, + thread->stack_addr + thread->stack_size, + lwp->text_entry); + /* never reach here */ + } + return -EINVAL; +quit: + if (page) + { + rt_pages_free(page, 0); + } + if (new_lwp) + { + lwp_ref_dec(new_lwp); + } + return (ret < 0 ? GET_ERRNO() : ret); +} +#endif /* ARCH_MM_MMU */ + +rt_err_t sys_thread_delete(rt_thread_t thread) +{ +#ifdef ARCH_MM_MMU + return rt_thread_delete(thread); +#else + rt_err_t ret = 0; + + if(thread->type != RT_Object_Class_Thread) + { + ret = -EINVAL; + goto __exit; + } + + ret = rt_thread_delete(thread); + + if (rt_thread_self() == thread) + { + rt_schedule(); + } + +__exit: + return ret; +#endif +} + +rt_err_t sys_thread_startup(rt_thread_t thread) +{ + return rt_thread_startup(thread); +} + +rt_thread_t sys_thread_self(void) +{ + return rt_thread_self(); +} + +/* sys channel */ + +int sys_channel_open(const char *name, int flags) +{ + return lwp_channel_open(FDT_TYPE_LWP, name, flags); +} + +rt_err_t sys_channel_close(int fd) +{ + return lwp_channel_close(FDT_TYPE_LWP, fd); +} + +rt_err_t sys_channel_send(int fd, rt_channel_msg_t data) +{ + return lwp_channel_send(FDT_TYPE_LWP, fd, data); +} + +rt_err_t sys_channel_send_recv_timeout(int fd, rt_channel_msg_t data, rt_channel_msg_t data_ret, rt_int32_t time) +{ + return lwp_channel_send_recv_timeout(FDT_TYPE_LWP, fd, data, data_ret, time); +} + +rt_err_t sys_channel_reply(int fd, rt_channel_msg_t data) +{ + return lwp_channel_reply(FDT_TYPE_LWP, fd, data); +} + +rt_err_t sys_channel_recv_timeout(int fd, rt_channel_msg_t data, rt_int32_t time) +{ + return lwp_channel_recv_timeout(FDT_TYPE_LWP, fd, data, time); +} + +/*****/ + +static struct rt_semaphore critical_lock; + +static int critical_init(void) +{ + rt_sem_init(&critical_lock, "ct_lock", 1, RT_IPC_FLAG_FIFO); + return 0; +} +INIT_DEVICE_EXPORT(critical_init); + +void sys_enter_critical(void) +{ + rt_sem_take(&critical_lock, RT_WAITING_FOREVER); +} + +void sys_exit_critical(void) +{ + rt_sem_release(&critical_lock); +} + +/* syscall: "sys_log" ret: "int" args: "const char*" "size" */ +static int __sys_log_enable = 0; +static int sys_log_enable(int argc, char** argv) +{ + if (argc == 1) + { + rt_kprintf("sys_log = %d\n", __sys_log_enable); + return 0; + } + else + { + __sys_log_enable = atoi(argv[1]); + } + + return 0; +} +MSH_CMD_EXPORT_ALIAS(sys_log_enable, sys_log, sys_log 1(enable)/0(disable)); + +int sys_log(const char* log, int size) +{ + rt_device_t console = rt_console_get_device(); + + if (console && __sys_log_enable) + { + rt_device_write(console, -1, log, size); + } + + return 0; +} + +int sys_stat(const char *file, struct stat *buf) +{ + int ret = 0; + ret = stat(file, buf); + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_notimpl(void) +{ + return -ENOSYS; +} + +uint32_t sys_hw_interrupt_disable(void) +{ + return rt_hw_interrupt_disable(); +} + +void sys_hw_interrupt_enable(uint32_t level) +{ + rt_hw_interrupt_enable(level); +} + +#ifdef RT_USING_USERSPACE +int sys_shmget(size_t key, size_t size, int create) +{ + return lwp_shmget(key, size, create); +} + +int sys_shmrm(int id) +{ + return lwp_shmrm(id); +} + +void* sys_shmat(int id, void* shm_vaddr) +{ + return lwp_shmat(id, shm_vaddr); +} + +int sys_shmdt(void* shm_vaddr) +{ + return lwp_shmdt(shm_vaddr); +} +#elif defined RT_LWP_USING_SHM +void *sys_shm_alloc(int size) +{ + if (size < 0) + { + return RT_NULL; + } + return lwp_shm_alloc((rt_size_t)size); +} + +void *sys_shm_retain(void *mem) +{ + if (!lwp_user_accessable(mem, sizeof (void *))) + { + return RT_NULL; + } + return lwp_shm_retain(mem); +} + +int sys_shm_free(void *mem) +{ + if (!lwp_user_accessable(mem, sizeof (void *))) + { + return -EFAULT; + } + lwp_shm_free(mem); + return 0; +} +#endif + +/* device interfaces */ +rt_err_t sys_device_init(rt_device_t dev) +{ + return rt_device_init(dev); +} + +rt_err_t sys_device_register(rt_device_t dev, const char *name, rt_uint16_t flags) +{ + return rt_device_register(dev, name, flags); +} + +rt_err_t sys_device_control(rt_device_t dev, int cmd, void *arg) +{ + return rt_device_control(dev, cmd, arg); +} + +rt_device_t sys_device_find(const char* name) +{ + return rt_device_find(name); +} + +rt_err_t sys_device_open(rt_device_t dev, rt_uint16_t oflag) +{ + return rt_device_open(dev, oflag); +} + +rt_err_t sys_device_close(rt_device_t dev) +{ + return rt_device_close(dev); +} + +rt_size_t sys_device_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + return rt_device_read(dev, pos, buffer, size); +} + +rt_size_t sys_device_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + return rt_device_write(dev, pos, buffer, size); +} + +#ifdef RT_USING_SAL +/* network interfaces */ +int sys_accept(int socket, struct musl_sockaddr *addr, socklen_t *addrlen) +{ + int ret = -1; + struct sockaddr ksa; + struct musl_sockaddr kmusladdr; + socklen_t uaddrlen; + socklen_t kaddrlen; + + if (addr) + { + if (!lwp_user_accessable(addrlen, sizeof (socklen_t *))) + { + return -EFAULT; + } + lwp_get_from_user(&uaddrlen, addrlen, sizeof (socklen_t *)); + if (!uaddrlen) + { + return -EINVAL; + } + + if (!lwp_user_accessable(addr, uaddrlen)) + { + return -EFAULT; + } + } + + kaddrlen = sizeof(struct sockaddr); + ret = accept(socket, &ksa, &kaddrlen); + if (ret >= 0) + { + if (addr) + { + sockaddr_tomusl(&ksa, &kmusladdr); + if (uaddrlen > sizeof(struct musl_sockaddr)) + { + uaddrlen = sizeof(struct musl_sockaddr); + } + lwp_put_to_user(addr, &kmusladdr, uaddrlen); + lwp_put_to_user(addrlen, &uaddrlen, sizeof (socklen_t *)); + } + } + return ret; +} + +int sys_bind(int socket, const struct musl_sockaddr *name, socklen_t namelen) +{ + struct sockaddr sa; + struct musl_sockaddr kname; + + if (!lwp_user_accessable((void *)name, namelen)) + { + return -EFAULT; + } + lwp_get_from_user(&kname, (void *)name, namelen); + + sockaddr_tolwip(&kname, &sa); + + return bind(socket, &sa, namelen); +} + +int sys_shutdown(int socket, int how) +{ + return shutdown(socket, how); +} + +int sys_getpeername (int socket, struct musl_sockaddr *name, socklen_t *namelen) +{ + int ret = -1; + struct sockaddr sa; + struct musl_sockaddr kname; + socklen_t unamelen; + socklen_t knamelen; + + if (!lwp_user_accessable(namelen, sizeof (socklen_t *))) + { + return -EFAULT; + } + lwp_get_from_user(&unamelen, namelen, sizeof (socklen_t *)); + if (!unamelen) + { + return -EINVAL; + } + + if (!lwp_user_accessable(name, unamelen)) + { + return -EFAULT; + } + + knamelen = sizeof(struct sockaddr); + ret = getpeername(socket, &sa, &knamelen); + + if (ret == 0) + { + sockaddr_tomusl(&sa, &kname); + if (unamelen > sizeof(struct musl_sockaddr)) + { + unamelen = sizeof(struct musl_sockaddr); + } + lwp_put_to_user(name, &kname, unamelen); + lwp_put_to_user(namelen, &unamelen, sizeof (socklen_t *)); + } + else + { + ret = GET_ERRNO(); + } + + return ret; +} + +int sys_getsockname (int socket, struct musl_sockaddr *name, socklen_t *namelen) +{ + int ret = -1; + struct sockaddr sa; + struct musl_sockaddr kname; + socklen_t unamelen; + socklen_t knamelen; + + if (!lwp_user_accessable(namelen, sizeof (socklen_t *))) + { + return -EFAULT; + } + lwp_get_from_user(&unamelen, namelen, sizeof (socklen_t *)); + if (!unamelen) + { + return -EINVAL; + } + + if (!lwp_user_accessable(name, unamelen)) + { + return -EFAULT; + } + + knamelen = sizeof(struct sockaddr); + ret = getsockname(socket, &sa, &knamelen); + if (ret == 0) + { + sockaddr_tomusl(&sa, &kname); + if (unamelen > sizeof(struct musl_sockaddr)) + { + unamelen = sizeof(struct musl_sockaddr); + } + lwp_put_to_user(name, &kname, unamelen); + lwp_put_to_user(namelen, &unamelen, sizeof(socklen_t *)); + } + else + { + ret = GET_ERRNO(); + } + return ret; +} + +int sys_getsockopt(int socket, int level, int optname, void *optval, socklen_t *optlen) +{ + int ret; + convert_sockopt(&level, &optname); + ret = getsockopt(socket, level, optname, optval, optlen); + + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_setsockopt(int socket, int level, int optname, const void *optval, socklen_t optlen) +{ + int ret; + convert_sockopt(&level, &optname); + ret = setsockopt(socket, level, optname, optval, optlen); + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_connect(int socket, const struct musl_sockaddr *name, socklen_t namelen) +{ + int ret; + struct sockaddr sa; + struct musl_sockaddr kname; + + if (!lwp_user_accessable((void *)name, namelen)) + { + return -EFAULT; + } + lwp_get_from_user(&kname, (void *)name, namelen); + + sockaddr_tolwip(&kname, &sa); + + ret = connect(socket, &sa, namelen); + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_listen(int socket, int backlog) +{ + return listen(socket, backlog); +} + +#define MUSLC_MSG_OOB 0x0001 +#define MUSLC_MSG_PEEK 0x0002 +#define MUSLC_MSG_DONTWAIT 0x0040 +#define MUSLC_MSG_WAITALL 0x0100 +#define MUSLC_MSG_MORE 0x8000 + +static int netflags_muslc_2_lwip(int flags) +{ + int flgs = 0; + + if (flags & MUSLC_MSG_PEEK) + { + flgs |= MSG_PEEK; + } + if (flags & MUSLC_MSG_WAITALL) + { + flgs |= MSG_WAITALL; + } + if (flags & MUSLC_MSG_OOB) + { + flgs |= MSG_OOB; + } + if (flags & MUSLC_MSG_DONTWAIT) + { + flgs |= MSG_DONTWAIT; + } + if (flags & MUSLC_MSG_MORE) + { + flgs |= MSG_MORE; + } + return flgs; +} + +int sys_recvfrom(int socket, void *mem, size_t len, int flags, + struct musl_sockaddr *from, socklen_t *fromlen) +{ + int flgs = 0; +#ifdef RT_USING_USERSPACE + int ret = -1; + void *kmem = RT_NULL; +#endif + + flgs = netflags_muslc_2_lwip(flags); +#ifdef RT_USING_USERSPACE + if (!len) + { + return -EINVAL; + } + + if (!lwp_user_accessable((void *)mem, len)) + { + return -EFAULT; + } + + kmem = kmem_get(len); + if (!kmem) + { + return -ENOMEM; + } + + if (flags == 0x2) + { + flags = 0x1; + } + + if (from) + { + struct sockaddr sa; + + ret = recvfrom(socket, kmem, len, flgs, &sa, fromlen); + sockaddr_tomusl(&sa, from); + } + else + { + ret = recvfrom(socket, kmem, len, flgs, NULL, NULL); + } + + if (ret > 0) + { + lwp_put_to_user(mem, kmem, len); + } + + kmem_put(kmem); + return (ret < 0 ? GET_ERRNO() : ret); +#else + int ret = -1; + if (from) + { + struct sockaddr sa = {0}; + + ret = recvfrom(socket, mem, len, flgs, &sa, fromlen); + sockaddr_tomusl(&sa, from); + } + else + { + ret = recvfrom(socket, mem, len, flags, NULL, NULL); + } + return (ret < 0 ? GET_ERRNO() : ret); +#endif +} + +int sys_recv(int socket, void *mem, size_t len, int flags) +{ + int flgs = 0; + int ret; + + flgs = netflags_muslc_2_lwip(flags); + ret = recvfrom(socket, mem, len, flgs, NULL, NULL); + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_sendto(int socket, const void *dataptr, size_t size, int flags, + const struct musl_sockaddr *to, socklen_t tolen) +{ + int flgs = 0; +#ifdef RT_USING_USERSPACE + int ret = -1; + void *kmem = RT_NULL; +#endif + + flgs = netflags_muslc_2_lwip(flags); +#ifdef RT_USING_USERSPACE + if (!size) + { + return -EINVAL; + } + + if (!lwp_user_accessable((void *)dataptr, size)) + { + return -EFAULT; + } + + kmem = kmem_get(size); + if (!kmem) + { + return -ENOMEM; + } + + lwp_get_from_user(kmem, (void *)dataptr, size); + + if (to) + { + struct sockaddr sa; + sockaddr_tolwip(to, &sa); + + ret = sendto(socket, kmem, size, flgs, &sa, tolen); + } + else + { + ret = sendto(socket, kmem, size, flgs, NULL, tolen); + } + + kmem_put(kmem); + return (ret < 0 ? GET_ERRNO() : ret); +#else + int ret; + if (to) + { + struct sockaddr sa; + sockaddr_tolwip(to, &sa); + + ret = sendto(socket, dataptr, size, flgs, &sa, tolen); + } + else + { + ret = sendto(socket, dataptr, size, flgs, NULL, tolen); + } + return (ret < 0 ? GET_ERRNO() : ret); +#endif +} + +int sys_send(int socket, const void *dataptr, size_t size, int flags) +{ + int ret; + int flgs = 0; + + flgs = netflags_muslc_2_lwip(flags); + ret = sendto(socket, dataptr, size, flgs, NULL, 0); + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_socket(int domain, int type, int protocol) +{ + int fd = -1; + int nonblock = 0; + /* not support SOCK_CLOEXEC type */ + if (type & SOCK_CLOEXEC) + { + type &= ~SOCK_CLOEXEC; + } + if (type & SOCK_NONBLOCK) + { + nonblock = 1; + type &= ~SOCK_NONBLOCK; + } + + fd = socket(domain, type, protocol); + if (fd < 0) + { + goto out; + } + if (nonblock) + { + fcntl(fd, F_SETFL, O_NONBLOCK); + } + +out: + return (fd < 0 ? GET_ERRNO() : fd); +} + +int sys_closesocket(int socket) +{ + return closesocket(socket); +} + +#endif + +rt_thread_t sys_thread_find(char *name) +{ + return rt_thread_find(name); +} + +rt_tick_t sys_tick_get(void) +{ + return rt_tick_get(); +} + +rt_err_t sys_thread_mdelay(rt_int32_t ms) +{ + return rt_thread_mdelay(ms); +} + +struct k_sigaction { + void (*handler)(int); + unsigned long flags; + void (*restorer)(void); + unsigned mask[2]; +}; + +int sys_sigaction(int sig, const struct k_sigaction *act, + struct k_sigaction *oact, size_t sigsetsize) +{ + int ret = -RT_EINVAL; + struct lwp_sigaction kact, *pkact = RT_NULL; + struct lwp_sigaction koact, *pkoact = RT_NULL; + + if (!sigsetsize) + { + SET_ERRNO(EINVAL); + goto out; + } + if (sigsetsize > sizeof(lwp_sigset_t)) + { + sigsetsize = sizeof(lwp_sigset_t); + } + if (!act && !oact) + { + SET_ERRNO(EINVAL); + goto out; + } + if (oact) + { + if (!lwp_user_accessable((void *)oact, sizeof(*oact))) + { + SET_ERRNO(EFAULT); + goto out; + } + pkoact = &koact; + } + if (act) + { + if (!lwp_user_accessable((void *)act, sizeof(*act))) + { + SET_ERRNO(EFAULT); + goto out; + } + kact.sa_flags = act->flags; + kact.__sa_handler._sa_handler = act->handler; + memcpy(&kact.sa_mask, &act->mask, sigsetsize); + kact.sa_restorer = act->restorer; + pkact = &kact; + } + + ret = lwp_sigaction(sig, pkact, pkoact, sigsetsize); +#ifdef ARCH_MM_MMU + if (ret == 0 && oact) + { + lwp_put_to_user(&oact->handler, &pkoact->__sa_handler._sa_handler, sizeof(void (*)(int))); + lwp_put_to_user(&oact->mask, &pkoact->sa_mask, sigsetsize); + lwp_put_to_user(&oact->flags, &pkoact->sa_flags, sizeof(int)); + lwp_put_to_user(&oact->restorer, &pkoact->sa_restorer, sizeof(void (*)(void))); + } +#endif /* ARCH_MM_MMU */ +out: + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_sigprocmask(int how, const sigset_t *sigset, sigset_t *oset, size_t size) +{ + int ret = -1; + lwp_sigset_t *pnewset = RT_NULL, *poldset = RT_NULL; +#ifdef ARCH_MM_MMU + lwp_sigset_t newset, oldset; +#endif /* ARCH_MM_MMU*/ + + if (!size) + { + return -EINVAL; + } + if (!oset && !sigset) + { + return -EINVAL; + } + if (size > sizeof(lwp_sigset_t)) + { + size = sizeof(lwp_sigset_t); + } + if (oset) + { +#ifdef ARCH_MM_MMU + if (!lwp_user_accessable((void *)oset, size)) + { + return -EFAULT; + } + poldset = &oldset; +#else + if (!lwp_user_accessable((void *)oset, size)) + { + return -EFAULT; + } + poldset = (lwp_sigset_t *)oset; +#endif + } + if (sigset) + { +#ifdef ARCH_MM_MMU + if (!lwp_user_accessable((void *)sigset, size)) + { + return -EFAULT; + } + lwp_get_from_user(&newset, (void *)sigset, size); + pnewset = &newset; +#else + if (!lwp_user_accessable((void *)sigset, size)) + { + return -EFAULT; + } + pnewset = (lwp_sigset_t *)sigset; +#endif /* ARCH_MM_MMU */ + } + ret = lwp_sigprocmask(how, pnewset, poldset); +#ifdef ARCH_MM_MMU + if (ret < 0) + { + return ret; + } + if (oset) + { + lwp_put_to_user(oset, poldset, size); + } +#endif /* ARCH_MM_MMU */ + return (ret < 0 ? -EFAULT: ret); +} + +int sys_tkill(int tid, int sig) +{ +#ifdef ARCH_MM_MMU + rt_base_t level; + rt_thread_t thread; + int ret; + + level = rt_hw_interrupt_disable(); + thread = lwp_tid_get_thread(tid); + ret = lwp_thread_kill(thread, sig); + rt_hw_interrupt_enable(level); + return ret; +#else + return lwp_thread_kill((rt_thread_t)tid, sig); +#endif +} + +int sys_thread_sigprocmask(int how, const lwp_sigset_t *sigset, lwp_sigset_t *oset, size_t size) +{ + int ret = -1; + lwp_sigset_t *pnewset = RT_NULL, *poldset = RT_NULL; +#ifdef ARCH_MM_MMU + lwp_sigset_t newset, oldset; +#endif /* ARCH_MM_MMU */ + + if (!size) + { + return -EINVAL; + } + if (!oset && !sigset) + { + return -EINVAL; + } + if (size != sizeof(lwp_sigset_t)) + { + return -EINVAL; + } + if (oset) + { +#ifdef ARCH_MM_MMU + if (!lwp_user_accessable((void *)oset, size)) + { + return -EFAULT; + } + poldset = &oldset; +#else + if (!lwp_user_accessable((void *)oset, size)) + { + return -EFAULT; + } + poldset = oset; +#endif + } + if (sigset) + { +#ifdef ARCH_MM_MMU + if (!lwp_user_accessable((void *)sigset, size)) + { + return -EFAULT; + } + lwp_get_from_user(&newset, (void *)sigset, sizeof(lwp_sigset_t)); + pnewset = &newset; +#else + if (!lwp_user_accessable((void *)sigset, size)) + { + return -EFAULT; + } + pnewset = (lwp_sigset_t *)sigset; +#endif + } + ret = lwp_thread_sigprocmask(how, pnewset, poldset); + if (ret < 0) + { + return ret; + } +#ifdef ARCH_MM_MMU + if (oset) + { + lwp_put_to_user(oset, poldset, sizeof(lwp_sigset_t)); + } +#endif + return (ret < 0 ? -EFAULT: ret); +} + +#ifndef ARCH_MM_MMU +int sys_lwp_sighandler_set(int sig, lwp_sighandler_t func) +{ + if (!lwp_user_accessable((void *)func, sizeof(lwp_sighandler_t))) + { + return -EFAULT; + } + + lwp_sighandler_set(sig, func); + return 0; +} + +int sys_thread_sighandler_set(int sig, lwp_sighandler_t func) +{ + if (!lwp_user_accessable((void *)func, sizeof(lwp_sighandler_t))) + { + return -EFAULT; + } + + lwp_thread_sighandler_set(sig, func); + return 0; +} +#endif /* not defined ARCH_MM_MMU */ + +int32_t sys_waitpid(int32_t pid, int *status, int options) +{ + int ret = -1; +#ifdef RT_USING_USERSPACE + if (!lwp_user_accessable((void *)status, sizeof(int))) + { + return -EFAULT; + } + else + { + ret = waitpid(pid, status, options); + } +#else + if (!lwp_user_accessable((void *)status, sizeof(int))) + { + return -EFAULT; + } + ret = waitpid(pid, status, options); +#endif + return ret; +} + +#if defined(RT_USING_SAL) && defined(SAL_USING_POSIX) +struct musl_addrinfo +{ + int ai_flags; + int ai_family; + int ai_socktype; + int ai_protocol; + socklen_t ai_addrlen; + + struct musl_sockaddr *ai_addr; + char *ai_canonname; + + struct musl_addrinfo *ai_next; +}; + +int sys_getaddrinfo(const char *nodename, + const char *servname, + const struct musl_addrinfo *hints, + struct musl_addrinfo *res) +{ + int ret = -1; + struct addrinfo *k_res = NULL; + char *k_nodename = NULL; + char *k_servname = NULL; + struct addrinfo *k_hints = NULL; +#ifdef RT_USING_USERSPACE + int err; +#endif + +#ifdef RT_USING_USERSPACE + if (!lwp_user_accessable((void *)res, sizeof(*res))) + { + SET_ERRNO(EFAULT); + goto exit; + } +#endif + if (nodename) + { +#ifdef RT_USING_USERSPACE + lwp_user_strlen(nodename, &err); + if (err) + { + SET_ERRNO(EFAULT); + goto exit; + } +#endif + k_nodename = rt_strdup(nodename); + if (!k_nodename) + { + SET_ERRNO(ENOMEM); + goto exit; + } + } + if (servname) + { +#ifdef RT_USING_USERSPACE + lwp_user_strlen(servname, &err); + if (err) + { + SET_ERRNO(EFAULT); + goto exit; + } +#endif + k_servname = rt_strdup(servname); + if (!k_servname) + { + SET_ERRNO(ENOMEM); + goto exit; + } + } + + if (hints) + { +#ifdef RT_USING_USERSPACE + if (!lwp_user_accessable((void *)hints, sizeof(*hints))) + { + SET_ERRNO(EFAULT); + goto exit; + } +#endif + k_hints = (struct addrinfo *) rt_malloc(sizeof *hints); + if (!k_hints) + { + SET_ERRNO(ENOMEM); + goto exit; + } + + rt_memset(k_hints, 0x0, sizeof(struct addrinfo)); + k_hints->ai_flags = hints->ai_flags; + k_hints->ai_family = hints->ai_family; + k_hints->ai_socktype = hints->ai_socktype; + k_hints->ai_protocol = hints->ai_protocol; + k_hints->ai_addrlen = hints->ai_addrlen; + } + + ret = sal_getaddrinfo(k_nodename, k_servname, k_hints, &k_res); + if (ret == 0) + { + /* set sockaddr */ + sockaddr_tomusl(k_res->ai_addr, res->ai_addr); + res->ai_addrlen = k_res->ai_addrlen; + + /* set up addrinfo */ + res->ai_family = k_res->ai_family; + res->ai_flags = k_res->ai_flags; + res->ai_next = NULL; + + if (hints != NULL) + { + /* copy socktype & protocol from hints if specified */ + res->ai_socktype = hints->ai_socktype; + res->ai_protocol = hints->ai_protocol; + } + + sal_freeaddrinfo(k_res); + k_res = NULL; + } + +exit: + if (k_nodename) + { + rt_free(k_nodename); + } + if (k_servname) + { + rt_free(k_servname); + } + if (k_hints) + { + rt_free(k_hints); + } + + return (ret < 0 ? GET_ERRNO() : ret); +} + +#define HOSTENT_BUFSZ 512 +int sys_gethostbyname2_r(const char *name, int af, struct hostent *ret, + char *buf, size_t buflen, + struct hostent **result, int *err) +{ + int ret_val = -1; + int sal_ret = -1 , sal_err = -1; + struct hostent sal_he; + struct hostent *sal_result = NULL; + char *sal_buf = NULL; + char *k_name = NULL; + int a_err = 0; + +#ifdef RT_USING_USERSPACE + if (!lwp_user_accessable((void *)err, sizeof(*err))) + { + SET_ERRNO(EFAULT); + goto __exit; + } + + if (!lwp_user_accessable((void *)result, sizeof(*result)) + || !lwp_user_accessable((void *)ret, sizeof(*ret)) + || !lwp_user_accessable((void *)buf, buflen)) + { + /* not all arguments given */ + *err = EFAULT; + SET_ERRNO(EFAULT); + goto __exit; + } + + lwp_user_strlen(name, &a_err); + if (a_err) + { + *err = EFAULT; + SET_ERRNO(EFAULT); + goto __exit; + } +#endif + + *result = ret; + sal_buf = (char *)malloc(HOSTENT_BUFSZ); + if (sal_buf == NULL) + { + SET_ERRNO(ENOMEM); + goto __exit; + } + + k_name = rt_strdup(name); + if (k_name == NULL) + { + SET_ERRNO(ENOMEM); + goto __exit; + } + + /* get host by name in SAL */ + sal_ret = sal_gethostbyname_r(k_name, &sal_he, sal_buf, HOSTENT_BUFSZ, &sal_result, &sal_err); + if (sal_ret == 0) + { + int index = 0, cnt = 0; + char *ptr = buf; + + /* get counter */ + index = 0; + while (sal_he.h_addr_list[index] != NULL) + { + index++; + } + cnt = index + 1; + + /* update user space hostent */ + ret->h_addrtype = sal_he.h_addrtype; + ret->h_length = sal_he.h_length; + + rt_strncpy(ptr, k_name, buflen - (ptr - buf)); + ret->h_name = ptr; + ptr += rt_strlen(k_name); + + ret->h_addr_list = (char**)ptr; + ptr += cnt * sizeof(char *); + + index = 0; + while (sal_he.h_addr_list[index] != NULL) + { + ret->h_addr_list[index] = ptr; + rt_memcpy(ptr, sal_he.h_addr_list[index], sal_he.h_length); + + ptr += sal_he.h_length; + index++; + } + ret->h_addr_list[index] = NULL; + } + + ret_val = 0; + +__exit: + /* release buffer */ + if (sal_buf) + { + free(sal_buf); + } + if (k_name) + { + free(k_name); + } + + return (ret_val < 0 ? GET_ERRNO() : ret_val); +} +#endif + +char *sys_getcwd(char *buf, size_t size) +{ + if (!lwp_user_accessable((void *)buf, size)) + { + return RT_NULL; + } + getcwd(buf, size); + + return (char *)strlen(buf); +} + +int sys_chdir(const char *path) +{ +#ifdef RT_USING_USERSPACE + int err = 0; + + lwp_user_strlen(path, &err); + if (err) + { + return -EFAULT; + } + err = chdir(path); + return (err < 0 ? GET_ERRNO() : err); +#else + int ret = chdir(path); + return (ret < 0 ? GET_ERRNO() : ret); +#endif +} + +int sys_mkdir(const char *path, mode_t mode) +{ +#ifdef RT_USING_USERSPACE + int err = 0; + + lwp_user_strlen(path, &err); + if (err) + { + return -EFAULT; + } + err = mkdir(path, mode); + return (err < 0 ? GET_ERRNO() : err); +#else + int ret = mkdir(path, mode); + return (ret < 0 ? GET_ERRNO() : ret); +#endif +} + +int sys_rmdir(const char *path) +{ +#ifdef RT_USING_USERSPACE + int err = 0; + + lwp_user_strlen(path, &err); + if (err) + { + return -EFAULT; + } + err = unlink(path); + return (err < 0 ? GET_ERRNO() : err); +#else + int ret = unlink(path); + return (ret < 0 ? GET_ERRNO() : ret); +#endif +} + +#ifdef RT_USING_MUSL +typedef uint64_t ino_t; +#endif +struct libc_dirent { + ino_t d_ino; + off_t d_off; + unsigned short d_reclen; + unsigned char d_type; + char d_name[256]; +}; +int sys_getdents(int fd, struct libc_dirent *dirp, size_t nbytes) +{ + int ret = -1; + struct dfs_fd *dfs_fd; + size_t cnt = (nbytes / sizeof(struct libc_dirent)); + size_t rtt_nbytes = 0; + struct dirent *rtt_dirp; + +#ifdef RT_USING_USERSPACE + if (!lwp_user_accessable((void *)dirp, sizeof(struct libc_dirent))) + { + return -EFAULT; + } +#endif + + if (cnt == 0) + { + return -EINVAL; + } + rtt_nbytes = cnt * sizeof(struct dirent); + rtt_dirp = (struct dirent *)rt_malloc(rtt_nbytes); + if (!rtt_dirp) + { + return -ENOMEM; + } + dfs_fd = fd_get(fd); + ret = dfs_file_getdents(dfs_fd, rtt_dirp, rtt_nbytes); + if (ret > 0) + { + size_t i = 0; + cnt = ret / sizeof(struct dirent); + for (i = 0; i < cnt; i++) + { + dirp[i].d_ino = 0; + dirp[i].d_off = i*sizeof(struct libc_dirent); + dirp[i].d_type = rtt_dirp[i].d_type; + dirp[i].d_reclen = sizeof(struct libc_dirent); + strcpy(dirp[i].d_name, rtt_dirp[i].d_name); + } + ret = cnt * sizeof(struct libc_dirent); + } + rt_free(rtt_dirp); + return (ret < 0 ? GET_ERRNO() : ret); +} + +rt_err_t sys_get_errno(void) +{ + return rt_get_errno(); +} +#ifdef ARCH_MM_MMU +int sys_set_thread_area(void *p) +{ + rt_thread_t thread; + + thread = rt_thread_self(); + thread->thread_idr = p; + lwp_set_thread_area(p); + + return 0; +} + +int sys_set_tid_address(int *tidptr) +{ + rt_thread_t thread; + +#ifdef RT_USING_USERSPACE + if (!lwp_user_accessable((void *)tidptr, sizeof(int))) + { + return -EFAULT; + } +#endif + thread = rt_thread_self(); + thread->clear_child_tid = tidptr; + return thread->tid; +} +#endif /* ARCH_MM_MMU */ + +int sys_gettid(void) +{ + return rt_thread_self()->tid; +} + +int sys_access(const char *filename, int mode) +{ + int ret = 0; +#ifdef RT_USING_USERSPACE + rt_size_t len = 0; + char *kname = RT_NULL; + int a_err = 0; + + lwp_user_strlen(filename, &a_err); + if (a_err) + { + return -EFAULT; + } + + len = rt_strlen(filename); + if (!len) + { + return -EINVAL; + } + + kname = (char *)kmem_get(len + 1); + if (!ret && !kname) + { + return -ENOMEM; + } + + if (!ret) + { + lwp_get_from_user(kname, (void *)filename, len + 1); + ret = access(kname, mode); + kmem_put(kname); + } +#else + ret = access(filename, mode); +#endif + + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_pipe(int fd[2]) +{ + int ret; + if (!lwp_user_accessable((void *)fd, sizeof(int[2]))) + { + return -EFAULT; + } + ret = pipe(fd); + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_clock_settime(clockid_t clk, const struct timespec *ts) +{ + rt_device_t device; + time_t now; + + device = rt_device_find("rtc"); + if (device == RT_NULL) + { + return -ENODEV; + } + +#ifdef RT_USING_USERSPACE + size_t size = sizeof(struct timespec); + struct timespec *kts = NULL; + + if (!lwp_user_accessable((void *)ts, size)) + { + return -EFAULT; + } + + kts = kmem_get(size); + if (!kts) + { + return -ENOMEM; + } + + lwp_get_from_user(kts, (void *)ts, size); + now = kts->tv_sec; + + kmem_put(kts); +#else + if (!lwp_user_accessable((void *)ts, sizeof(struct timespec))) + { + return -EFAULT; + } + now = ts->tv_sec; +#endif + return rt_device_control(device, RT_DEVICE_CTRL_RTC_SET_TIME, &now); +} + +int sys_clock_gettime(clockid_t clk, struct timespec *ts) +{ + int ret = 0; + rt_device_t device; + time_t now; + + device = rt_device_find("rtc"); + if (device == RT_NULL) + { + return -ENODEV; + } + ret = rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &now); + +#ifdef RT_USING_USERSPACE + size_t size = sizeof(struct timespec); + struct timespec *kts = NULL; + + if (!lwp_user_accessable((void *)ts, size)) + { + return -EFAULT; + } + + kts = kmem_get(size); + if (!kts) + { + return -ENOMEM; + } + + kts->tv_sec = now; + kts->tv_nsec = 0; + lwp_put_to_user(ts, kts, size); + + kmem_put(kts); +#else + if (!lwp_user_accessable((void *)ts, sizeof(struct timespec))) + { + return -EFAULT; + } + ts->tv_sec = now; + ts->tv_nsec = 0; +#endif + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_clock_getres(clockid_t clk, struct timespec *ts) +{ +#ifdef RT_USING_USERSPACE + struct timespec kts; + size_t size = sizeof(struct timespec); + + if (!lwp_user_accessable((void *)ts, size)) + { + return -EFAULT; + } + + kts.tv_sec = 1; + kts.tv_nsec = 0; + lwp_put_to_user(ts, &kts, size); +#else + if (!lwp_user_accessable((void *)ts, sizeof(struct timespec))) + { + return -EFAULT; + } + ts->tv_sec = 1; + ts->tv_nsec = 0; +#endif + return 0; +} + +int sys_rename(const char *oldpath, const char *newpath) +{ + int ret = -1; +#ifdef RT_USING_USERSPACE + int err; + + lwp_user_strlen(oldpath, &err); + if (err) + { + return -EFAULT; + } + + lwp_user_strlen(newpath, &err); + if (err) + { + return -EFAULT; + } +#endif + ret = rename(oldpath, newpath); + return (ret < 0 ? GET_ERRNO() : ret); +} + +typedef unsigned long long rlim_t; + +struct rlimit { + rlim_t rlim_cur; + rlim_t rlim_max; +}; + +#define RLIMIT_CPU 0 +#define RLIMIT_FSIZE 1 +#define RLIMIT_DATA 2 +#define RLIMIT_STACK 3 +#define RLIMIT_CORE 4 +#define RLIMIT_RSS 5 +#define RLIMIT_NPROC 6 +#define RLIMIT_NOFILE 7 +#define RLIMIT_MEMLOCK 8 +#define RLIMIT_AS 9 + +int sys_prlimit64(pid_t pid, + unsigned int resource, + const struct rlimit *new_rlim, + struct rlimit *old_rlim) +{ + return -ENOSYS; +} + +int sys_getrlimit(unsigned int resource, unsigned long rlim[2]) +{ + int ret = -1; + + if (!lwp_user_accessable((void *)rlim, sizeof(unsigned long [2]))) + { + return -EFAULT; + } + switch (resource) + { + case RLIMIT_NOFILE: + { + struct dfs_fdtable *fdt = dfs_fdtable_get(); + + dfs_fd_lock(); + rlim[0] = fdt->maxfd; + dfs_fd_unlock(); + rlim[1] = DFS_FD_MAX; + ret = 0; + } + break; + default: + return -EINVAL; + break; + } + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_setrlimit(unsigned int resource, struct rlimit *rlim) +{ + return -ENOSYS; +} + +int sys_setsid(void) +{ + int ret = 0; + ret = setsid(); + return (ret < 0 ? GET_ERRNO() : ret); +} + +int sys_cacheflush(void *addr, int len, int cache); + +int sys_getrandom(void *buf, size_t buflen, unsigned int flags) +{ + int ret = -1; + int count = 0; + void *kmem = RT_NULL; + rt_device_t rd_dev = RT_NULL; + + if (flags & GRND_RANDOM) + rd_dev = rt_device_find("random"); + else + rd_dev = rt_device_find("urandom"); + + if (rd_dev == RT_NULL) + { + return -EFAULT; + } + + if (rt_device_open(rd_dev, RT_DEVICE_OFLAG_RDONLY) != RT_EOK) + { + return -EFAULT; + } + + if (!lwp_user_accessable(buf, buflen)) + { + rt_device_close(rd_dev); + return -EFAULT; + } + + kmem = kmem_get(buflen); + if (!kmem) + { + rt_device_close(rd_dev); + return -ENOMEM; + } + + while (count < buflen) + { + ret = rt_device_read(rd_dev, count, kmem + count, buflen - count); + if (ret <= 0) + break; + count += ret; + } + rt_device_close(rd_dev); + + ret = count; + if (count > 0) + { + ret = lwp_put_to_user(buf, kmem, count); + } + kmem_put(kmem); + + return ret; +} + +const static void* func_table[] = +{ + (void *)sys_exit, /* 01 */ + (void *)sys_read, + (void *)sys_write, + (void *)sys_lseek, + (void *)sys_open, /* 05 */ + (void *)sys_close, + (void *)sys_ioctl, + (void *)sys_fstat, + (void *)sys_poll, + (void *)sys_nanosleep, /* 10 */ + (void *)sys_gettimeofday, + (void *)sys_settimeofday, + (void *)sys_exec, + (void *)sys_kill, + (void *)sys_getpid, /* 15 */ + (void *)sys_getpriority, + (void *)sys_setpriority, + (void *)sys_sem_create, + (void *)sys_sem_delete, + (void *)sys_sem_take, /* 20 */ + (void *)sys_sem_release, + (void *)sys_mutex_create, + (void *)sys_mutex_delete, + (void *)sys_mutex_take, + (void *)sys_mutex_release, /* 25 */ + (void *)sys_event_create, + (void *)sys_event_delete, + (void *)sys_event_send, + (void *)sys_event_recv, + (void *)sys_mb_create, /* 30 */ + (void *)sys_mb_delete, + (void *)sys_mb_send, + (void *)sys_mb_send_wait, + (void *)sys_mb_recv, + (void *)sys_mq_create, /* 35 */ + (void *)sys_mq_delete, + (void *)sys_mq_send, + (void *)sys_mq_urgent, + (void *)sys_mq_recv, + (void *)sys_thread_create, /* 40 */ + (void *)sys_thread_delete, + (void *)sys_thread_startup, + (void *)sys_thread_self, + (void *)sys_channel_open, + (void *)sys_channel_close, /* 45 */ + (void *)sys_channel_send, + (void *)sys_channel_send_recv_timeout, + (void *)sys_channel_reply, + (void *)sys_channel_recv_timeout, + (void *)sys_enter_critical, /* 50 */ + (void *)sys_exit_critical, + + SYSCALL_USPACE(sys_brk), + SYSCALL_USPACE(sys_mmap2), + SYSCALL_USPACE(sys_munmap), +#ifdef ARCH_MM_MMU + SYSCALL_USPACE(sys_shmget), /* 55 */ + SYSCALL_USPACE(sys_shmrm), + SYSCALL_USPACE(sys_shmat), + SYSCALL_USPACE(sys_shmdt), +#else +#ifdef RT_LWP_USING_SHM + (void *)sys_shm_alloc, /* 55 */ + (void *)sys_shm_free, + (void *)sys_shm_retain, + (void *)sys_notimpl, +#else + (void *)sys_notimpl, /* 55 */ + (void *)sys_notimpl, + (void *)sys_notimpl, + (void *)sys_notimpl, +#endif /* RT_LWP_USING_SHM */ +#endif /* ARCH_MM_MMU */ + (void *)sys_device_init, + (void *)sys_device_register, /* 60 */ + (void *)sys_device_control, + (void *)sys_device_find, + (void *)sys_device_open, + (void *)sys_device_close, + (void *)sys_device_read, /* 65 */ + (void *)sys_device_write, + + (void *)sys_stat, + (void *)sys_thread_find, + + SYSCALL_NET(sys_accept), + SYSCALL_NET(sys_bind), /* 70 */ + SYSCALL_NET(sys_shutdown), + SYSCALL_NET(sys_getpeername), + SYSCALL_NET(sys_getsockname), + SYSCALL_NET(sys_getsockopt), + SYSCALL_NET(sys_setsockopt), /* 75 */ + SYSCALL_NET(sys_connect), + SYSCALL_NET(sys_listen), + SYSCALL_NET(sys_recv), + SYSCALL_NET(sys_recvfrom), + SYSCALL_NET(sys_send), /* 80 */ + SYSCALL_NET(sys_sendto), + SYSCALL_NET(sys_socket), + + SYSCALL_NET(sys_closesocket), + SYSCALL_NET(sys_getaddrinfo), + SYSCALL_NET(sys_gethostbyname2_r), /* 85 */ + + (void *)sys_notimpl, //(void *)network, + (void *)sys_notimpl, //(void *)network, + (void *)sys_notimpl, //(void *)network, + (void *)sys_notimpl, //(void *)network, + (void *)sys_notimpl, //(void *)network, /* 90 */ + (void *)sys_notimpl, //(void *)network, + (void *)sys_notimpl, //(void *)network, + (void *)sys_notimpl, //(void *)network, + +#ifdef RT_USING_DFS + (void *)sys_select, +#else + (void *)sys_notimpl, +#endif + + (void *)sys_notimpl, //(void *)sys_hw_interrupt_disable, /* 95 */ + (void *)sys_notimpl, //(void *)sys_hw_interrupt_enable, + + (void *)sys_tick_get, + (void *)sys_exit_group, + + (void *)sys_notimpl, //(void *)rt_delayed_work_init, + (void *)sys_notimpl, //(void *)rt_work_submit, /* 100 */ + (void *)sys_notimpl, //(void *)rt_wqueue_wakeup, + (void *)sys_thread_mdelay, + (void *)sys_sigaction, + (void *)sys_sigprocmask, + (void *)sys_tkill, /* 105 */ + (void *)sys_thread_sigprocmask, +#ifdef ARCH_MM_MMU + (void *)sys_cacheflush, + (void *)sys_notimpl, + (void *)sys_notimpl, +#else + (void *)sys_notimpl, + (void *)sys_lwp_sighandler_set, + (void *)sys_thread_sighandler_set, +#endif + (void *)sys_waitpid, /* 110 */ + + (void *)sys_timer_create, + (void *)sys_timer_delete, + (void *)sys_timer_start, + (void *)sys_timer_stop, + (void *)sys_timer_control, /* 115 */ + (void *)sys_getcwd, + (void *)sys_chdir, + (void *)sys_unlink, + (void *)sys_mkdir, + (void *)sys_rmdir, /* 120 */ + (void *)sys_getdents, + (void *)sys_get_errno, +#ifdef ARCH_MM_MMU + (void *)sys_set_thread_area, + (void *)sys_set_tid_address, +#else + (void *)sys_notimpl, + (void *)sys_notimpl, +#endif + (void *)sys_access, /* 125 */ + (void *)sys_pipe, + (void *)sys_clock_settime, + (void *)sys_clock_gettime, + (void *)sys_clock_getres, + SYSCALL_USPACE(sys_clone), /* 130 */ + SYSCALL_USPACE(sys_futex), + SYSCALL_USPACE(sys_pmutex), + (void *)sys_dup, + (void *)sys_dup2, + (void *)sys_rename, /* 135 */ + SYSCALL_USPACE(sys_fork), + SYSCALL_USPACE(sys_execve), + SYSCALL_USPACE(sys_vfork), + (void *)sys_gettid, + (void *)sys_prlimit64, /* 140 */ + (void *)sys_getrlimit, + (void *)sys_setrlimit, + (void *)sys_setsid, + (void *)sys_getrandom, }; const void *lwp_get_sys_api(rt_uint32_t number) { - const void *func = (const void*)sys_notimpl; + const void *func = (const void *)sys_notimpl; if (number == 0xff) { @@ -272,7 +4171,7 @@ const void *lwp_get_sys_api(rt_uint32_t number) else { number -= 1; - if (number < sizeof(func_table)/sizeof(func_table[0])) + if (number < sizeof(func_table) / sizeof(func_table[0])) { func = func_table[number]; } diff --git a/components/lwp/lwp_syscall.h b/components/lwp/lwp_syscall.h index a2809059f0b679d276ca77a6145c12291639e0f8..bb3fab6535857f132aa951bfe1a1bcf824f04cbf 100644 --- a/components/lwp/lwp_syscall.h +++ b/components/lwp/lwp_syscall.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-12-10 Jesven fix complie error in iar and keil + * 2019-11-12 Jesven the first version */ #ifndef __LWP_SYSCALL_H__ @@ -14,9 +14,14 @@ #include #include #include +#include #include #include +#ifdef __cplusplus +extern "C" { +#endif + typedef long suseconds_t; /* microseconds (signed) */ typedef uint32_t id_t; /* may contain pid, uid or gid */ @@ -30,35 +35,62 @@ typedef uint32_t id_t; /* may contain pid, uid or gid */ #define PRIO_PGRP 1 #define PRIO_USER 2 -#ifndef TIMEVAL_TO_TIMESPEC -#define TIMEVAL_TO_TIMESPEC(tv, ts) { \ - (ts)->tv_sec = (tv)->tv_sec; \ - (ts)->tv_nsec = (tv)->tv_usec * 1000; \ -} -#endif - -#ifndef TIMESPEC_TO_TIMEVAL -#define TIMESPEC_TO_TIMEVAL(tv, ts) { \ - (tv)->tv_sec = (ts)->tv_sec; \ - (tv)->tv_usec = (ts)->tv_nsec / 1000; \ -} -#endif - void sys_exit(int value); ssize_t sys_read(int fd, void *buf, size_t nbyte); ssize_t sys_write(int fd, const void *buf, size_t nbyte); off_t sys_lseek(int fd, off_t offset, int whence); int sys_open(const char *name, int mode, ...); int sys_close(int fd); +int sys_ioctl(int fd, unsigned long cmd, void* data); +int sys_fstat(int file, struct stat *buf); +int sys_poll(struct pollfd *fds, nfds_t nfds, int timeout); int sys_nanosleep(const struct timespec *rqtp, struct timespec *rmtp); -int sys_getpriority(int which, id_t who); -int sys_setpriority(int which, id_t who, int prio); int sys_gettimeofday(struct timeval *tp, struct timezone *tzp); int sys_settimeofday(const struct timeval *tv, const struct timezone *tzp); -int sys_msgget(key_t key, int msgflg); -int sys_msgsend(int msqid, const void *msgp, size_t msgsz, int msgflg); -int sys_msgrcv(int msqid, void *msgp, size_t msgsz, long msgtyp, int msgflg); +int sys_exec(char *filename, int argc, char **argv, char **envp); +int sys_kill(int pid, int sig); +int sys_getpid(void); +int sys_getpriority(int which, id_t who); +int sys_setpriority(int which, id_t who, int prio); +rt_sem_t sys_sem_create(const char *name, rt_uint32_t value, rt_uint8_t flag); +rt_err_t sys_sem_delete(rt_sem_t sem); +rt_err_t sys_sem_take(rt_sem_t sem, rt_int32_t time); +rt_err_t sys_sem_release(rt_sem_t sem); +rt_mutex_t sys_mutex_create(const char *name, rt_uint8_t flag); +rt_err_t sys_mutex_delete(rt_mutex_t mutex); +rt_err_t sys_mutex_take(rt_mutex_t mutex, rt_int32_t time); +rt_err_t sys_mutex_release(rt_mutex_t mutex); +rt_event_t sys_event_create(const char *name, rt_uint8_t flag); +rt_err_t sys_event_delete(rt_event_t event); +rt_err_t sys_event_send(rt_event_t event, rt_uint32_t set); +rt_err_t sys_event_recv(rt_event_t event, rt_uint32_t set, rt_uint8_t opt, rt_int32_t timeout, rt_uint32_t *recved); +rt_mailbox_t sys_mb_create(const char *name, rt_size_t size, rt_uint8_t flag); +rt_err_t sys_mb_delete(rt_mailbox_t mb); +rt_err_t sys_mb_send(rt_mailbox_t mb, rt_uint32_t value); +rt_err_t sys_mb_send_wait(rt_mailbox_t mb, rt_uint32_t value, rt_int32_t timeout); +rt_err_t sys_mb_recv(rt_mailbox_t mb, rt_uint32_t *value, rt_int32_t timeout); +rt_mq_t sys_mq_create(const char *name, rt_size_t msg_size, rt_size_t max_msgs, rt_uint8_t flag); +rt_err_t sys_mq_delete(rt_mq_t mq); +rt_err_t sys_mq_send(rt_mq_t mq, void *buffer, rt_size_t size); +rt_err_t sys_mq_urgent(rt_mq_t mq, void *buffer, rt_size_t size); +rt_err_t sys_mq_recv(rt_mq_t mq, void *buffer, rt_size_t size, rt_int32_t timeout); +rt_thread_t sys_thread_create(void *arg[]); +rt_err_t sys_thread_delete(rt_thread_t thread); +rt_err_t sys_thread_startup(rt_thread_t thread); +rt_thread_t sys_thread_self(void); +int sys_channel_open(const char *name, int flags); +rt_err_t sys_channel_close(int fd); +rt_err_t sys_channel_send(int fd, rt_channel_msg_t data); +rt_err_t sys_channel_send_recv(int fd, rt_channel_msg_t data, rt_channel_msg_t data_ret); +rt_err_t sys_channel_reply(int fd, rt_channel_msg_t data); +rt_err_t sys_channel_recv(int fd, rt_channel_msg_t data); +void sys_enter_critical(void); +void sys_exit_critical(void); int sys_log(const char* log, int size); +#ifdef __cplusplus +} +#endif + #endif diff --git a/components/lwp/lwp_tid.c b/components/lwp/lwp_tid.c new file mode 100644 index 0000000000000000000000000000000000000000..3caa9207d51cebb5a9d7860419efaa8cca78e12e --- /dev/null +++ b/components/lwp/lwp_tid.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-15 shaojinchun first version + */ + +#include +#include + +#include "lwp.h" + +#ifdef RT_USING_USERSPACE +#include "lwp_user_mm.h" + +#ifdef RT_USING_GDBSERVER +#include +#include +#endif + +#endif + +#define DBG_TAG "LWP_TID" +#define DBG_LVL DBG_INFO +#include + +#define TID_MAX 10000 + +#define TID_CT_ASSERT(name, x) \ + struct assert_##name {char ary[2 * (x) - 1];} + +TID_CT_ASSERT(tid_min_nr, LWP_TID_MAX_NR > 1); +TID_CT_ASSERT(tid_max_nr, LWP_TID_MAX_NR < TID_MAX); + +static struct lwp_avl_struct lwp_tid_ary[LWP_TID_MAX_NR]; +static struct lwp_avl_struct *lwp_tid_free_head = RT_NULL; +static int lwp_tid_ary_alloced = 0; +static struct lwp_avl_struct *lwp_tid_root = RT_NULL; +static int current_tid = 0; + +int lwp_tid_get(void) +{ + rt_base_t level; + struct lwp_avl_struct *p; + int tid = 0; + + level = rt_hw_interrupt_disable(); + p = lwp_tid_free_head; + if (p) + { + lwp_tid_free_head = (struct lwp_avl_struct *)p->avl_right; + } + else if (lwp_tid_ary_alloced < LWP_TID_MAX_NR) + { + p = lwp_tid_ary + lwp_tid_ary_alloced; + lwp_tid_ary_alloced++; + } + if (p) + { + int found_noused = 0; + + RT_ASSERT(p->data == RT_NULL); + for (tid = current_tid + 1; tid < TID_MAX; tid++) + { + if (!lwp_avl_find(tid, lwp_tid_root)) + { + found_noused = 1; + break; + } + } + if (!found_noused) + { + for (tid = 1; tid <= current_tid; tid++) + { + if (!lwp_avl_find(tid, lwp_tid_root)) + { + found_noused = 1; + break; + } + } + } + p->avl_key = tid; + lwp_avl_insert(p, &lwp_tid_root); + current_tid = tid; + } + rt_hw_interrupt_enable(level); + return tid; +} + +void lwp_tid_put(int tid) +{ + rt_base_t level; + struct lwp_avl_struct *p; + + level = rt_hw_interrupt_disable(); + p = lwp_avl_find(tid, lwp_tid_root); + if (p) + { + p->data = RT_NULL; + lwp_avl_remove(p, &lwp_tid_root); + p->avl_right = lwp_tid_free_head; + lwp_tid_free_head = p; + } + rt_hw_interrupt_enable(level); +} + +rt_thread_t lwp_tid_get_thread(int tid) +{ + rt_base_t level; + struct lwp_avl_struct *p; + rt_thread_t thread = RT_NULL; + + level = rt_hw_interrupt_disable(); + p = lwp_avl_find(tid, lwp_tid_root); + if (p) + { + thread = (rt_thread_t)p->data; + } + rt_hw_interrupt_enable(level); + return thread; +} + +void lwp_tid_set_thread(int tid, rt_thread_t thread) +{ + rt_base_t level; + struct lwp_avl_struct *p; + + level = rt_hw_interrupt_disable(); + p = lwp_avl_find(tid, lwp_tid_root); + if (p) + { + p->data = thread; + } + rt_hw_interrupt_enable(level); +} diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c new file mode 100644 index 0000000000000000000000000000000000000000..c71f16a9c3958399170734abe6b86a9c462f82c5 --- /dev/null +++ b/components/lwp/lwp_user_mm.c @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-28 Jesven first version + * 2021-02-06 lizhirui fixed fixed vtable size problem + * 2021-02-12 lizhirui add 64-bit support for lwp_brk + * 2021-02-19 lizhirui add riscv64 support for lwp_user_accessable and lwp_get_from_user + * 2021-06-07 lizhirui modify user space bound check + */ + +#include +#include + +#ifdef RT_USING_USERSPACE + +#include +#include +#include +#include +#include + +#ifdef RT_USING_GDBSERVER +#include +#include +#endif + +int lwp_user_space_init(struct rt_lwp *lwp) +{ + return arch_user_space_init(lwp); +} + +void switch_mmu(void *mtable); +void *mmu_table_get(void); +void lwp_mmu_switch(struct rt_thread *thread) +{ + struct rt_lwp *l = RT_NULL; + void *pre_mmu_table = RT_NULL, *new_mmu_table = RT_NULL; + + if (thread->lwp) + { + l = (struct rt_lwp *)thread->lwp; + new_mmu_table = (void *)((char *)l->mmu_info.vtable + l->mmu_info.pv_off); + } + else + { + new_mmu_table = arch_kernel_mmu_table_get(); + } + + pre_mmu_table = mmu_table_get(); + if (pre_mmu_table != new_mmu_table) + { + switch_mmu(new_mmu_table); + } +} + +static void unmap_range(struct rt_lwp *lwp, void *addr, size_t size, int pa_need_free) +{ + void *va = RT_NULL, *pa = RT_NULL; + int i = 0; + + for (va = addr, i = 0; i < size; va = (void *)((char *)va + ARCH_PAGE_SIZE), i += ARCH_PAGE_SIZE) + { + pa = rt_hw_mmu_v2p(&lwp->mmu_info, va); + if (pa) + { + rt_hw_mmu_unmap(&lwp->mmu_info, va, ARCH_PAGE_SIZE); + if (pa_need_free) + { + rt_pages_free((void *)((char *)pa - PV_OFFSET), 0); + } + } + } +} + +void lwp_unmap_user_space(struct rt_lwp *lwp) +{ + struct lwp_avl_struct *node = RT_NULL; + + while ((node = lwp_map_find_first(lwp->map_area)) != 0) + { + struct rt_mm_area_struct *ma = (struct rt_mm_area_struct *)node->data; + int pa_need_free = 0; + + RT_ASSERT(ma->type < MM_AREA_TYPE_UNKNOW); + + switch (ma->type) + { + case MM_AREA_TYPE_DATA: + case MM_AREA_TYPE_TEXT: + pa_need_free = 1; + break; + case MM_AREA_TYPE_SHM: + lwp_shm_ref_dec(lwp, (void *)ma->addr); + break; + } + unmap_range(lwp, (void *)ma->addr, ma->size, pa_need_free); + lwp_map_area_remove(&lwp->map_area, ma->addr); + } + + arch_user_space_vtable_free(lwp); +} + +static void *_lwp_map_user(struct rt_lwp *lwp, void *map_va, size_t map_size, int text) +{ + void *va = RT_NULL; + int ret = 0; + rt_mmu_info *m_info = &lwp->mmu_info; + int area_type; + + va = rt_hw_mmu_map_auto(m_info, map_va, map_size, MMU_MAP_U_RWCB); + if (!va) + { + return 0; + } + + area_type = text ? MM_AREA_TYPE_TEXT : MM_AREA_TYPE_DATA; + ret = lwp_map_area_insert(&lwp->map_area, (size_t)va, map_size, area_type); + if (ret != 0) + { + unmap_range(lwp, va, map_size, 1); + return 0; + } + return va; +} + +int lwp_unmap_user(struct rt_lwp *lwp, void *va) +{ + rt_base_t level = 0; + struct lwp_avl_struct *ma_avl_node = RT_NULL; + struct rt_mm_area_struct *ma = RT_NULL; + int pa_need_free = 0; + + level = rt_hw_interrupt_disable(); + ma_avl_node = lwp_map_find(lwp->map_area, (size_t)va); + if (!ma_avl_node) + { + rt_hw_interrupt_enable(level); + return -1; + } + ma = (struct rt_mm_area_struct *)ma_avl_node->data; + + RT_ASSERT(ma->type < MM_AREA_TYPE_UNKNOW); + if ((ma->type == MM_AREA_TYPE_DATA) || (ma->type == MM_AREA_TYPE_TEXT)) + { + pa_need_free = 1; + } + unmap_range(lwp, (void *)ma->addr, ma->size, pa_need_free); + lwp_map_area_remove(&lwp->map_area, (size_t)va); + rt_hw_interrupt_enable(level); + return 0; +} + +int lwp_dup_user(struct lwp_avl_struct *ptree, void *arg) +{ + struct rt_lwp *self_lwp = lwp_self(); + struct rt_lwp *new_lwp = (struct rt_lwp *)arg; + struct rt_mm_area_struct *ma = (struct rt_mm_area_struct *)ptree->data; + void *pa = RT_NULL; + void *va = RT_NULL; + + switch (ma->type) + { + case MM_AREA_TYPE_PHY: + pa = rt_hw_mmu_v2p(&self_lwp->mmu_info, (void *)ma->addr); + va = lwp_map_user_type(new_lwp, (void *)ma->addr, pa, ma->size, 0, MM_AREA_TYPE_PHY); + break; + case MM_AREA_TYPE_PHY_CACHED: + pa = rt_hw_mmu_v2p(&self_lwp->mmu_info, (void *)ma->addr); + va = lwp_map_user_type(new_lwp, (void *)ma->addr, pa, ma->size, 0, MM_AREA_TYPE_PHY_CACHED); + break; + case MM_AREA_TYPE_SHM: + va = (void *)ma->addr; + if (lwp_shm_ref_inc(self_lwp, va) > 0) + { + pa = rt_hw_mmu_v2p(&self_lwp->mmu_info, va); + va = lwp_map_user_type(new_lwp, va, pa, ma->size, 1, MM_AREA_TYPE_SHM); + } + break; + case MM_AREA_TYPE_DATA: + va = lwp_map_user(new_lwp, (void *)ma->addr, ma->size, 0); + if (va == (void *)ma->addr) + { + lwp_data_put(&new_lwp->mmu_info, va, va, ma->size); + } + break; + case MM_AREA_TYPE_TEXT: + { + char *addr = (char *)ma->addr; + size_t size = ma->size; + + while (size) + { + pa = rt_hw_mmu_v2p(&self_lwp->mmu_info, (void *)addr); + rt_page_ref_inc((char *)pa - self_lwp->mmu_info.pv_off, 0); + va = lwp_map_user_type(new_lwp, addr, pa, ARCH_PAGE_SIZE, 1, MM_AREA_TYPE_TEXT); + if (va != addr) + { + return -1; + } + addr += ARCH_PAGE_SIZE; + size -= ARCH_PAGE_SIZE; + } + va = (void *)ma->addr; + } + break; + default: + RT_ASSERT(0); + break; + } + if (va != (void *)ma->addr) + { + return -1; + } + return 0; +} + +int lwp_unmap_user_phy(struct rt_lwp *lwp, void *va) +{ + return lwp_unmap_user(lwp, va); +} + +int lwp_unmap_user_type(struct rt_lwp *lwp, void *va) +{ + return lwp_unmap_user(lwp, va); +} + +void *lwp_map_user(struct rt_lwp *lwp, void *map_va, size_t map_size, int text) +{ + rt_base_t level = 0; + void *ret = RT_NULL; + size_t offset = 0; + + if (!map_size) + { + return 0; + } + offset = (size_t)map_va & ARCH_PAGE_MASK; + map_size += (offset + ARCH_PAGE_SIZE - 1); + map_size &= ~ARCH_PAGE_MASK; + map_va = (void *)((size_t)map_va & ~ARCH_PAGE_MASK); + + level = rt_hw_interrupt_disable(); + ret = _lwp_map_user(lwp, map_va, map_size, text); + rt_hw_interrupt_enable(level); + if (ret) + { + ret = (void *)((char *)ret + offset); + } + return ret; +} + +static void *_lwp_map_user_type(struct rt_lwp *lwp, void *map_va, void *map_pa, size_t map_size, int cached, int type) +{ + void *va = RT_NULL; + rt_mmu_info *m_info = &lwp->mmu_info; + size_t attr = 0; + int ret = 0; + + if (cached) + { + attr = MMU_MAP_U_RWCB; + if (type == MM_AREA_TYPE_PHY) + { + type = MM_AREA_TYPE_PHY_CACHED; + } + } + else + { + attr = MMU_MAP_U_RW; + } + + va = rt_hw_mmu_map(m_info, map_va, map_pa, map_size, attr); + if (va) + { + ret = lwp_map_area_insert(&lwp->map_area, (size_t)va, map_size, type); + if (ret != 0) + { + unmap_range(lwp, va, map_size, 0); + return 0; + } + } + return va; +} + +void *lwp_map_user_type(struct rt_lwp *lwp, void *map_va, void *map_pa, size_t map_size, int cached, int type) +{ + rt_base_t level = 0; + void *ret = RT_NULL; + size_t offset = 0; + + if (!map_size) + { + return 0; + } + if (map_va) + { + if (((size_t)map_va & ARCH_PAGE_MASK) != ((size_t)map_pa & ARCH_PAGE_MASK)) + { + return 0; + } + } + offset = (size_t)map_pa & ARCH_PAGE_MASK; + map_size += (offset + ARCH_PAGE_SIZE - 1); + map_size &= ~ARCH_PAGE_MASK; + map_pa = (void *)((size_t)map_pa & ~ARCH_PAGE_MASK); + + level = rt_hw_interrupt_disable(); + ret = _lwp_map_user_type(lwp, map_va, map_pa, map_size, cached, type); + rt_hw_interrupt_enable(level); + if (ret) + { + ret = (void *)((char *)ret + offset); + } + return ret; +} + +void *lwp_map_user_phy(struct rt_lwp *lwp, void *map_va, void *map_pa, size_t map_size, int cached) +{ + return lwp_map_user_type(lwp, map_va, map_pa, map_size, cached, MM_AREA_TYPE_PHY); +} + +rt_base_t lwp_brk(void *addr) +{ + rt_base_t level = 0; + rt_base_t ret = -1; + struct rt_lwp *lwp = RT_NULL; + + level = rt_hw_interrupt_disable(); + lwp = rt_thread_self()->lwp; + + if ((size_t)addr <= lwp->end_heap) + { + ret = (rt_base_t)lwp->end_heap; + } + else + { + size_t size = 0; + void *va = RT_NULL; + + if ((size_t)addr <= USER_HEAP_VEND) + { + size = (((size_t)addr - lwp->end_heap) + ARCH_PAGE_SIZE - 1) & ~ARCH_PAGE_MASK; + va = lwp_map_user(lwp, (void *)lwp->end_heap, size, 0); + } + if (va) + { + lwp->end_heap += size; + ret = lwp->end_heap; + } + } + rt_hw_interrupt_enable(level); + return ret; +} + +#define MAP_ANONYMOUS 0x20 + +void* lwp_mmap2(void *addr, size_t length, int prot, + int flags, int fd, off_t pgoffset) +{ + rt_base_t level = 0; + void *ret = (void *)-1; + struct rt_lwp *lwp = RT_NULL; + + if (fd == -1) + { + lwp = rt_thread_self()->lwp; + level = rt_hw_interrupt_disable(); + ret = lwp_map_user(lwp, addr, length, 0); + rt_hw_interrupt_enable(level); + if (ret) + { + if ((flags & MAP_ANONYMOUS) != 0) + { + rt_memset(ret, 0, length); + } + } + else + { + ret = (void *)-1; + } + } + return ret; +} + +int lwp_munmap(void *addr) +{ + rt_base_t level = 0; + int ret = 0; + struct rt_lwp *lwp = RT_NULL; + + level = rt_hw_interrupt_disable(); + lwp = rt_thread_self()->lwp; + ret = lwp_unmap_user(lwp, addr); + rt_hw_interrupt_enable(level); + return ret; +} + +size_t lwp_get_from_user(void *dst, void *src, size_t size) +{ + struct rt_lwp *lwp = RT_NULL; + rt_mmu_info *m_info = RT_NULL; + + /* check src */ + + if (src < (void *)USER_VADDR_START) + { + return 0; + } + if (src >= (void *)USER_VADDR_TOP) + { + return 0; + } + if ((void *)((char *)src + size) > (void *)USER_VADDR_TOP) + { + return 0; + } + + lwp = lwp_self(); + if (!lwp) + { + return 0; + } + m_info = &lwp->mmu_info; + + return lwp_data_get(m_info, dst, src, size); +} + +size_t lwp_put_to_user(void *dst, void *src, size_t size) +{ + struct rt_lwp *lwp = RT_NULL; + rt_mmu_info *m_info = RT_NULL; + + /* check dst */ + if (dst < (void *)USER_VADDR_START) + { + return 0; + } + if (dst >= (void *)USER_VADDR_TOP) + { + return 0; + } + if ((void *)((char *)dst + size) > (void *)USER_VADDR_TOP) + { + return 0; + } + + lwp = lwp_self(); + if (!lwp) + { + return 0; + } + m_info = &lwp->mmu_info; + return lwp_data_put(m_info, dst, src, size); +} + +int lwp_user_accessable(void *addr, size_t size) +{ + void *addr_start = RT_NULL, *addr_end = RT_NULL, *next_page = RT_NULL; + void *tmp_addr = RT_NULL; + struct rt_lwp *lwp = lwp_self(); + rt_mmu_info *mmu_info = RT_NULL; + + if (!lwp) + { + return 0; + } + if (!size || !addr) + { + return 0; + } + addr_start = addr; + addr_end = (void *)((char *)addr + size); + +#ifdef ARCH_RISCV64 + if(addr_start < (void *)USER_VADDR_START) + { + return 0; + } +#else + if (addr_start >= (void *)USER_VADDR_TOP) + { + return 0; + } + if (addr_end > (void *)USER_VADDR_TOP) + { + return 0; + } +#endif + + mmu_info = &lwp->mmu_info; + next_page = (void *)(((size_t)addr_start + ARCH_PAGE_SIZE) & ~(ARCH_PAGE_SIZE - 1)); + do + { + size_t len = (char *)next_page - (char *)addr_start; + + if (size < len) + { + len = size; + } + tmp_addr = rt_hw_mmu_v2p(mmu_info, addr_start); + if (!tmp_addr) + { + return 0; + } + addr_start = (void *)((char *)addr_start + len); + size -= len; + next_page = (void *)((char *)next_page + ARCH_PAGE_SIZE); + } while (addr_start < addr_end); + return 1; +} + +/* src is in mmu_info space, dst is in current thread space */ +size_t lwp_data_get(rt_mmu_info *mmu_info, void *dst, void *src, size_t size) +{ + size_t copy_len = 0; + void *addr_start = RT_NULL, *addr_end = RT_NULL, *next_page = RT_NULL; + void *tmp_dst = RT_NULL, *tmp_src = RT_NULL; + + if (!size || !dst) + { + return 0; + } + tmp_dst = dst; + addr_start = src; + addr_end = (void *)((char *)src + size); + next_page = (void *)(((size_t)addr_start + ARCH_PAGE_SIZE) & ~(ARCH_PAGE_SIZE - 1)); + do + { + size_t len = (char *)next_page - (char *)addr_start; + + if (size < len) + { + len = size; + } + tmp_src = rt_hw_mmu_v2p(mmu_info, addr_start); + if (!tmp_src) + { + break; + } + tmp_src = (void *)((char *)tmp_src - PV_OFFSET); + rt_memcpy(tmp_dst, tmp_src, len); + tmp_dst = (void *)((char *)tmp_dst + len); + addr_start = (void *)((char *)addr_start + len); + size -= len; + next_page = (void *)((char *)next_page + ARCH_PAGE_SIZE); + copy_len += len; + } while (addr_start < addr_end); + return copy_len; +} + +/* dst is in mmu_info space, src is in current thread space */ +size_t lwp_data_put(rt_mmu_info *mmu_info, void *dst, void *src, size_t size) +{ + size_t copy_len = 0; + void *addr_start = RT_NULL, *addr_end = RT_NULL, *next_page = RT_NULL; + void *tmp_dst = RT_NULL, *tmp_src = RT_NULL; + + if (!size || !dst) + { + return 0; + } + tmp_src = src; + addr_start = dst; + addr_end = (void *)((char *)dst + size); + next_page = (void *)(((size_t)addr_start + ARCH_PAGE_SIZE) & ~(ARCH_PAGE_SIZE - 1)); + do + { + size_t len = (char *)next_page - (char *)addr_start; + + if (size < len) + { + len = size; + } + tmp_dst = rt_hw_mmu_v2p(mmu_info, addr_start); + if (!tmp_dst) + { + break; + } + tmp_dst = (void *)((char *)tmp_dst - PV_OFFSET); + rt_memcpy(tmp_dst, tmp_src, len); + tmp_src = (void *)((char *)tmp_src + len); + addr_start = (void *)((char *)addr_start + len); + size -= len; + next_page = (void *)((char *)next_page + ARCH_PAGE_SIZE); + copy_len += len; + } while (addr_start < addr_end); + return copy_len; +} + +void lwp_data_cache_flush(rt_mmu_info *mmu_info, void *vaddr, size_t size) +{ + void *paddr = RT_NULL; + + paddr = rt_hw_mmu_v2p(mmu_info, vaddr); + paddr = (void *)((char *)paddr - PV_OFFSET); + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, paddr, size); +} +#endif diff --git a/components/lwp/lwp_user_mm.h b/components/lwp/lwp_user_mm.h new file mode 100644 index 0000000000000000000000000000000000000000..07cb27e722beb168ceb00239da95035d7556f1bf --- /dev/null +++ b/components/lwp/lwp_user_mm.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-28 Jesven first version + * 2021-02-12 lizhirui add 64-bit support for lwp_brk + */ +#ifndef __LWP_USER_MM_H__ +#define __LWP_USER_MM_H__ + +#include +#include + +#ifdef RT_USING_USERSPACE +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int lwp_user_space_init(struct rt_lwp *lwp); +void lwp_unmap_user_space(struct rt_lwp *lwp); + +int lwp_unmap_user(struct rt_lwp *lwp, void *va); +void *lwp_map_user(struct rt_lwp *lwp, void *map_va, size_t map_size, int text); + +void *lwp_map_user_phy(struct rt_lwp *lwp, void *map_va, void *map_pa, size_t map_size, int cached); +int lwp_unmap_user_phy(struct rt_lwp *lwp, void *va); + +void *lwp_map_user_type(struct rt_lwp *lwp, void *map_va, void *map_pa, size_t map_size, int cached, int type); +int lwp_unmap_user_type(struct rt_lwp *lwp, void *va); + +rt_base_t lwp_brk(void *addr); +void* lwp_mmap2(void *addr, size_t length, int prot, int flags, int fd, off_t pgoffset); +int lwp_munmap(void *addr); + +size_t lwp_get_from_user(void *dst, void *src, size_t size); +size_t lwp_put_to_user(void *dst, void *src, size_t size); +int lwp_user_accessable(void *addr, size_t size); + +size_t lwp_data_get(rt_mmu_info *mmu_info, void *dst, void *src, size_t size); +size_t lwp_data_put(rt_mmu_info *mmu_info, void *dst, void *src, size_t size); +void lwp_data_cache_flush(rt_mmu_info *mmu_info, void *vaddr, size_t size); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /*__LWP_USER_MM_H__*/ diff --git a/components/lwp/page.c b/components/lwp/page.c new file mode 100644 index 0000000000000000000000000000000000000000..091ccee7fa5d717909a3d7fd7a2c84f25f648cb9 --- /dev/null +++ b/components/lwp/page.c @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-01 Jesven The first version + */ +#include + +#include +#include + +#ifdef RT_USING_USERSPACE + +#include +#include + +#define ARCH_PAGE_LIST_SIZE (ARCH_ADDRESS_WIDTH_BITS - ARCH_PAGE_SHIFT) + +#define DBG_TAG "PAGE" +#define DBG_LVL DBG_WARNING +#include + +struct page +{ + struct page *next; /* same level next */ + struct page *pre; /* same level pre */ + uint32_t size_bits; /* if is ARCH_ADDRESS_WIDTH_BITS, means not free */ + int ref_cnt; /* page group ref count */ +}; + +static struct page* page_start; +static void* page_addr; +static size_t page_nr; + +static struct page *page_list[ARCH_PAGE_LIST_SIZE]; + +RT_WEAK int rt_clz(size_t n) +{ + int bits = sizeof(size_t) * 8; + + n |= (n >> 1); + n |= (n >> 2); + n |= (n >> 4); + n |= (n >> 8); + n |= (n >> 16); + +#ifdef ARCH_CPU_64BIT + n |= (n >> 32); + + n = (n & 0x5555555555555555UL) + ((n >> 1) & 0x5555555555555555UL); + n = (n & 0x3333333333333333UL) + ((n >> 2) & 0x3333333333333333UL); + n = (n & 0x0707070707070707UL) + ((n >> 4) & 0x0707070707070707UL); + n = (n & 0x000f000f000f000fUL) + ((n >> 8) & 0x000f000f000f000fUL); + n = (n & 0x0000001f0000001fUL) + ((n >> 16) & 0x0000001f0000001fUL); + n = (n & 0x000000000000003fUL) + ((n >> 32) & 0x000000000000003fUL); +#else + n = (n & 0x55555555UL) + ((n >> 1) & 0x55555555UL); + n = (n & 0x33333333UL) + ((n >> 2) & 0x33333333UL); + n = (n & 0x07070707UL) + ((n >> 4) & 0x07070707UL); + n = (n & 0x000f000fUL) + ((n >> 8) & 0x000f000fUL); + n = (n & 0x0000001fUL) + ((n >> 16) & 0x0000001fUL); +#endif + return bits - n; +} + +RT_WEAK int rt_ctz(size_t n) +{ + int ret = sizeof(size_t) * 8; + + if (n) + { + ret -= (rt_clz(n ^ (n - 1)) + 1); + } + return ret; +} + +size_t rt_page_bits(size_t size) +{ + int bit = sizeof(size_t) * 8 - rt_clz(size) - 1; + + if ((size ^ (1UL << bit)) != 0) + { + bit++; + } + bit -= ARCH_PAGE_SHIFT; + if (bit < 0) + { + bit = 0; + } + return bit; +} + +static struct page * addr_to_page(void *addr) +{ + size_t off; + + if (addr < page_addr) + { + return 0; + } + off = (size_t)((char*)addr - (char*)page_addr); + off >>= ARCH_PAGE_SHIFT; + if (off >= page_nr) + { + return 0; + } + return &page_start[off]; +} + +static void* page_to_addr(struct page* p) +{ + if (!p) + { + return 0; + } + return (void*)((char*)page_addr + ((p - page_start) << ARCH_PAGE_SHIFT)); +} + +static inline struct page *buddy_get(struct page *p, uint32_t size_bits) +{ + size_t addr; + + addr = (size_t)page_to_addr(p); + addr ^= (1UL << (size_bits + ARCH_PAGE_SHIFT)); + return addr_to_page((void*)addr); +} + +static void page_remove(struct page *p, uint32_t size_bits) +{ + if (p->pre) + { + p->pre->next = p->next; + } + else + { + page_list[size_bits] = p->next; + } + + if (p->next) + { + p->next->pre = p->pre; + } + + p->size_bits = ARCH_ADDRESS_WIDTH_BITS; +} + +static void page_insert(struct page *p, uint32_t size_bits) +{ + p->next = page_list[size_bits]; + if (p->next) + { + p->next->pre = p; + } + p->pre = 0; + page_list[size_bits] = p; + p->size_bits = size_bits; +} + +static void _pages_ref_inc(struct page *p, uint32_t size_bits) +{ + struct page *page_head; + int idx; + + /* find page group head */ + idx = p - page_start; + if (idx < 0 || idx >= page_nr) + { + return; + } + idx = idx & ~((1UL << size_bits) - 1); + + page_head = page_start + idx; + page_head->ref_cnt++; +} + +static int _pages_ref_get(struct page *p, uint32_t size_bits) +{ + struct page *page_head; + int idx; + + /* find page group head */ + idx = p - page_start; + if (idx < 0 || idx >= page_nr) + { + return 0; + } + idx = idx & ~((1UL << size_bits) - 1); + + page_head = page_start + idx; + return page_head->ref_cnt; +} + +static int _pages_free(struct page *p, uint32_t size_bits) +{ + uint32_t level = size_bits; + struct page *buddy; + + RT_ASSERT(p->ref_cnt > 0); + RT_ASSERT(p->size_bits == ARCH_ADDRESS_WIDTH_BITS); + + p->ref_cnt--; + if (p->ref_cnt != 0) + { + return 0; + } + + while (level < ARCH_PAGE_LIST_SIZE) + { + buddy = buddy_get(p, level); + if (buddy && buddy->size_bits == level) + { + page_remove(buddy, level); + p = (p < buddy) ? p : buddy; + level++; + } + else + { + break; + } + } + page_insert(p, level); + return 1; +} + +static struct page *_pages_alloc(uint32_t size_bits) +{ + struct page *p; + + if (page_list[size_bits]) + { + p = page_list[size_bits]; + page_remove(p, size_bits); + } + else + { + uint32_t level; + + for (level = size_bits + 1; level < ARCH_PAGE_LIST_SIZE; level++) + { + if (page_list[level]) + { + break; + } + } + if (level == ARCH_PAGE_LIST_SIZE) + { + return 0; + } + + p = page_list[level]; + page_remove(p, level); + while (level > size_bits) + { + page_insert(p, level - 1); + p = buddy_get(p, level - 1); + level--; + } + } + p->size_bits = ARCH_ADDRESS_WIDTH_BITS; + p->ref_cnt = 1; + return p; +} + +int rt_page_ref_get(void *addr, uint32_t size_bits) +{ + struct page *p; + rt_base_t level; + int ref; + + p = addr_to_page(addr); + level = rt_hw_interrupt_disable(); + ref = _pages_ref_get(p, size_bits); + rt_hw_interrupt_enable(level); + return ref; +} + +void rt_page_ref_inc(void *addr, uint32_t size_bits) +{ + struct page *p; + rt_base_t level; + + p = addr_to_page(addr); + level = rt_hw_interrupt_disable(); + _pages_ref_inc(p, size_bits); + rt_hw_interrupt_enable(level); +} + +void *rt_pages_alloc(uint32_t size_bits) +{ + struct page *p; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + p = _pages_alloc(size_bits); + rt_hw_interrupt_enable(level); + return page_to_addr(p); +} + +int rt_pages_free(void *addr, uint32_t size_bits) +{ + struct page *p; + int real_free = 0; + + p = addr_to_page(addr); + if (p) + { + rt_base_t level; + level = rt_hw_interrupt_disable(); + real_free = _pages_free(p, size_bits); + rt_hw_interrupt_enable(level); + } + return real_free; +} + +void list_page(void) +{ + int i; + size_t total = 0; + + rt_base_t level; + level = rt_hw_interrupt_disable(); + + for (i = 0; i < ARCH_PAGE_LIST_SIZE; i++) + { + struct page *p = page_list[i]; + + rt_kprintf("level %d ", i); + + while (p) + { + total += (1UL << i); + rt_kprintf("[0x%08p]", page_to_addr(p)); + p = p->next; + } + rt_kprintf("\n"); + } + rt_hw_interrupt_enable(level); + rt_kprintf("free pages is %08x\n", total); + rt_kprintf("-------------------------------\n"); +} +MSH_CMD_EXPORT(list_page, show page info); + +void rt_page_get_info(size_t *total_nr, size_t *free_nr) +{ + int i; + size_t total_free = 0; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + for (i = 0; i < ARCH_PAGE_LIST_SIZE; i++) + { + struct page *p = page_list[i]; + + while (p) + { + total_free += (1UL << i); + p = p->next; + } + } + rt_hw_interrupt_enable(level); + *total_nr = page_nr; + *free_nr = total_free; +} + +void rt_page_init(rt_region_t reg) +{ + int i; + + LOG_D("split 0x%08x 0x%08x\n", reg.start, reg.end); + + reg.start += ARCH_PAGE_MASK; + reg.start &= ~ARCH_PAGE_MASK; + + reg.end &= ~ARCH_PAGE_MASK; + + { + int nr = ARCH_PAGE_SIZE / sizeof(struct page); + int total = (reg.end - reg.start) >> ARCH_PAGE_SHIFT; + int mnr = (total + nr) / (nr + 1); + + LOG_D("nr = 0x%08x\n", nr); + LOG_D("total = 0x%08x\n", total); + LOG_D("mnr = 0x%08x\n", mnr); + + RT_ASSERT(mnr < total); + + page_start = (struct page*)reg.start; + reg.start += (mnr << ARCH_PAGE_SHIFT); + page_addr = (void*)reg.start; + page_nr = (reg.end - reg.start) >> ARCH_PAGE_SHIFT; + } + + LOG_D("align 0x%08x 0x%08x\n", reg.start, reg.end); + + /* init free list */ + for (i = 0; i < ARCH_PAGE_LIST_SIZE; i++) + { + page_list[i] = 0; + } + + /* add pages to free list */ + while (reg.start != reg.end) + { + struct page *p; + int align_bits; + int size_bits; + + size_bits = ARCH_ADDRESS_WIDTH_BITS - 1 - rt_clz(reg.end - reg.start); + align_bits = rt_ctz(reg.start); + if (align_bits < size_bits) + { + size_bits = align_bits; + } + p = addr_to_page((void*)reg.start); + p->size_bits = ARCH_ADDRESS_WIDTH_BITS; + p->ref_cnt = 1; + _pages_free(p, size_bits - ARCH_PAGE_SHIFT); + reg.start += (1UL << size_bits); + } +} +#endif diff --git a/components/lwp/page.h b/components/lwp/page.h new file mode 100644 index 0000000000000000000000000000000000000000..8b65299d914eb4138a0dec90cb717d80fe494a6d --- /dev/null +++ b/components/lwp/page.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-01 Jesven The first version + */ + +#ifndef __PAGE_H__ +#define __PAGE_H__ + +#ifdef RT_USING_USERSPACE + +typedef struct tag_region +{ + size_t start; + size_t end; +} rt_region_t; + +void rt_page_init(rt_region_t reg); + +void *rt_pages_alloc(uint32_t size_bits); + +void rt_page_ref_inc(void *addr, uint32_t size_bits); + +int rt_page_ref_get(void *addr, uint32_t size_bits); + +int rt_pages_free(void *addr, uint32_t size_bits); + +void rt_pageinfo_dump(void); + +size_t rt_page_bits(size_t size); + +void rt_page_get_info(size_t *total_nr, size_t *free_nr); + +#endif + +#endif /*__PAGE_H__*/ diff --git a/components/net/lwip-2.0.2/src/api/sockets.c b/components/net/lwip-2.0.2/src/api/sockets.c index dc2477b611965522a82224b064149335a2d63648..044d123da396c38177aaad41f7865e42361d9cf1 100644 --- a/components/net/lwip-2.0.2/src/api/sockets.c +++ b/components/net/lwip-2.0.2/src/api/sockets.c @@ -300,7 +300,7 @@ static volatile int select_cb_ctr; #if LWIP_SOCKET_SET_ERRNO #ifndef set_errno -#define set_errno(err) do { if (err) { errno = (err); } } while(0) +#define set_errno(err) do { if (err) { errno = -(err); } } while(0) #endif #else /* LWIP_SOCKET_SET_ERRNO */ #define set_errno(err) @@ -2748,7 +2748,7 @@ lwip_fcntl(int s, int cmd, int val) sock_set_errno(sock, 0); break; case F_SETFL: - if ((val & ~O_NONBLOCK) == 0) { + if ((val & O_NONBLOCK) == O_NONBLOCK) { /* only O_NONBLOCK, all other bits are zero */ netconn_set_nonblocking(sock->conn, val & O_NONBLOCK); ret = 0; diff --git a/components/net/lwip-2.0.2/src/arch/sys_arch.c b/components/net/lwip-2.0.2/src/arch/sys_arch.c index 40c79011ec612e762276212c16ae7aed10fe859d..479fd9608a10292676f8a79775e863db73b87aff 100644 --- a/components/net/lwip-2.0.2/src/arch/sys_arch.c +++ b/components/net/lwip-2.0.2/src/arch/sys_arch.c @@ -321,7 +321,7 @@ u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) */ int sys_sem_valid(sys_sem_t *sem) { - return (int)(*sem); + return (int)(size_t)(*sem); } #endif @@ -397,7 +397,7 @@ void sys_mutex_free(sys_mutex_t *mutex) */ int sys_mutex_valid(sys_mutex_t *mutex) { - return (int)(*mutex); + return (int)(size_t)(*mutex); } #endif @@ -508,7 +508,7 @@ u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) t = timeout / (1000/RT_TICK_PER_SECOND); } - ret = rt_mb_recv(*mbox, (rt_ubase_t *)msg, t); + ret = rt_mb_recv_interruptibale(*mbox, (rt_ubase_t *)msg, t); if(ret != RT_EOK) { return SYS_ARCH_TIMEOUT; @@ -555,7 +555,7 @@ u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) */ int sys_mbox_valid(sys_mbox_t *mbox) { - return (int)(*mbox); + return (int)(size_t)(*mbox); } #endif diff --git a/components/net/lwip-2.1.2/src/api/sockets.c b/components/net/lwip-2.1.2/src/api/sockets.c index 4fea5b3727b13c38aece562877e2aaf634ae98ac..85e5ad1bc93c129cdb467ebd68fbef4b74beb993 100644 --- a/components/net/lwip-2.1.2/src/api/sockets.c +++ b/components/net/lwip-2.1.2/src/api/sockets.c @@ -3905,7 +3905,7 @@ lwip_fcntl(int s, int cmd, int val) case F_SETFL: /* Bits corresponding to the file access mode and the file creation flags [..] that are set in arg shall be ignored */ val &= ~(O_RDONLY | O_WRONLY | O_RDWR); - if ((val & ~O_NONBLOCK) == 0) { + if ((val & O_NONBLOCK) == O_NONBLOCK) { /* only O_NONBLOCK, all other bits are zero */ netconn_set_nonblocking(sock->conn, val & O_NONBLOCK); ret = 0; diff --git a/components/net/lwip-2.1.2/src/arch/include/arch/cc.h b/components/net/lwip-2.1.2/src/arch/include/arch/cc.h index 49c7541ed773e07e9cfb6c19d1290e879772ac00..ea6a5ff75585f9aab3750e4dc0ad53a6a9d9cec0 100644 --- a/components/net/lwip-2.1.2/src/arch/include/arch/cc.h +++ b/components/net/lwip-2.1.2/src/arch/include/arch/cc.h @@ -45,20 +45,6 @@ #define S32_F "ld" #define X32_F "lx" -#ifdef RT_USING_LIBC -#if defined(__CC_ARM) || defined(__CLANG_ARM) || defined(__IAR_SYSTEMS_ICC__) -#include -#else -#include -/* some errno not defined in newlib */ -#define ENSRNOTFOUND 163 /* Domain name not found */ -/* WARNING: ESHUTDOWN also not defined in newlib. We chose - 180 here because the number "108" which is used - in arch.h has been assigned to another error code. */ -#define ESHUTDOWN 180 -#endif /* __CC_ARM/__IAR_SYSTEMS_ICC__ */ -#endif /* RT_USING_LIBC */ - #if defined(RT_USING_LIBC) || defined(RT_USING_MINILIBC) || defined(RT_LIBC_USING_TIME) || (defined( __GNUC__ ) && !defined(__ARMCC_VERSION)) #include #define LWIP_TIMEVAL_PRIVATE 0 diff --git a/components/net/lwip-2.1.2/src/arch/sys_arch.c b/components/net/lwip-2.1.2/src/arch/sys_arch.c index 0633501bb6376e2a42e71f568a5da565cb931fe0..6d353d026fcf473f89484dd209d17cb4dd456b16 100644 --- a/components/net/lwip-2.1.2/src/arch/sys_arch.c +++ b/components/net/lwip-2.1.2/src/arch/sys_arch.c @@ -327,9 +327,9 @@ u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) /** Check if a semaphore is valid/allocated: * return 1 for valid, 0 for invalid */ -int sys_sem_valid(sys_sem_t *sem) +rt_ubase_t sys_sem_valid(sys_sem_t *sem) { - return (int)(*sem); + return (rt_ubase_t)(*sem); } #endif @@ -403,9 +403,9 @@ void sys_mutex_free(sys_mutex_t *mutex) /** Check if a mutex is valid/allocated: * return 1 for valid, 0 for invalid */ -int sys_mutex_valid(sys_mutex_t *mutex) +rt_ubase_t sys_mutex_valid(sys_mutex_t *mutex) { - return (int)(*mutex); + return (rt_ubase_t)(*mutex); } #endif @@ -468,7 +468,7 @@ void sys_mbox_post(sys_mbox_t *mbox, void *msg) { RT_DEBUG_NOT_IN_INTERRUPT; - rt_mb_send_wait(*mbox, (rt_uint32_t)msg, RT_WAITING_FOREVER); + rt_mb_send_wait(*mbox, (rt_ubase_t)msg, RT_WAITING_FOREVER); return; } @@ -480,7 +480,7 @@ void sys_mbox_post(sys_mbox_t *mbox, void *msg) */ err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) { - if (rt_mb_send(*mbox, (rt_uint32_t)msg) == RT_EOK) + if (rt_mb_send(*mbox, (rt_ubase_t)msg) == RT_EOK) return ERR_OK; return ERR_MEM; @@ -567,9 +567,9 @@ u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) /** Check if an mbox is valid/allocated: * return 1 for valid, 0 for invalid */ -int sys_mbox_valid(sys_mbox_t *mbox) +rt_ubase_t sys_mbox_valid(sys_mbox_t *mbox) { - return (int)(*mbox); + return (rt_ubase_t)(*mbox); } #endif diff --git a/components/net/lwip-2.1.2/src/include/lwip/sys.h b/components/net/lwip-2.1.2/src/include/lwip/sys.h index 168e465baa7383f42e47e4ad7c6b0ace6e659020..85f57c06a8ebe44ddad3a8f74d6e2d320461d443 100644 --- a/components/net/lwip-2.1.2/src/include/lwip/sys.h +++ b/components/net/lwip-2.1.2/src/include/lwip/sys.h @@ -161,7 +161,7 @@ void sys_mutex_free(sys_mutex_t *mutex); * When directly using OS structures, implementing this may be more complex. * This may also be a define, in which case the function is not prototyped. */ -int sys_mutex_valid(sys_mutex_t *mutex); +rt_ubase_t sys_mutex_valid(sys_mutex_t *mutex); #endif #ifndef sys_mutex_set_invalid /** @@ -233,7 +233,7 @@ void sys_sem_free(sys_sem_t *sem); * When directly using OS structures, implementing this may be more complex. * This may also be a define, in which case the function is not prototyped. */ -int sys_sem_valid(sys_sem_t *sem); +rt_ubase_t sys_sem_valid(sys_sem_t *sem); #endif #ifndef sys_sem_set_invalid /** @@ -376,7 +376,7 @@ void sys_mbox_free(sys_mbox_t *mbox); * When directly using OS structures, implementing this may be more complex. * This may also be a define, in which case the function is not prototyped. */ -int sys_mbox_valid(sys_mbox_t *mbox); +rt_ubase_t sys_mbox_valid(sys_mbox_t *mbox); #endif #ifndef sys_mbox_set_invalid /** diff --git a/components/net/lwip-2.1.2/src/netif/ethernetif.c b/components/net/lwip-2.1.2/src/netif/ethernetif.c index 10865930c1eae717a8543c32d3d87cd1b774f432..de1d33a7d1488ee350d0530f9d62d397dc519d77 100644 --- a/components/net/lwip-2.1.2/src/netif/ethernetif.c +++ b/components/net/lwip-2.1.2/src/netif/ethernetif.c @@ -84,10 +84,10 @@ struct eth_tx_msg static struct rt_mailbox eth_tx_thread_mb; static struct rt_thread eth_tx_thread; #ifndef RT_LWIP_ETHTHREAD_MBOX_SIZE -static char eth_tx_thread_mb_pool[32 * 4]; +static char eth_tx_thread_mb_pool[32 * sizeof(void *)]; static char eth_tx_thread_stack[512]; #else -static char eth_tx_thread_mb_pool[RT_LWIP_ETHTHREAD_MBOX_SIZE * 4]; +static char eth_tx_thread_mb_pool[RT_LWIP_ETHTHREAD_MBOX_SIZE * sizeof(void *)]; static char eth_tx_thread_stack[RT_LWIP_ETHTHREAD_STACKSIZE]; #endif #endif @@ -96,10 +96,10 @@ static char eth_tx_thread_stack[RT_LWIP_ETHTHREAD_STACKSIZE]; static struct rt_mailbox eth_rx_thread_mb; static struct rt_thread eth_rx_thread; #ifndef RT_LWIP_ETHTHREAD_MBOX_SIZE -static char eth_rx_thread_mb_pool[48 * 4]; +static char eth_rx_thread_mb_pool[48 * sizeof(void *)]; static char eth_rx_thread_stack[1024]; #else -static char eth_rx_thread_mb_pool[RT_LWIP_ETHTHREAD_MBOX_SIZE * 4]; +static char eth_rx_thread_mb_pool[RT_LWIP_ETHTHREAD_MBOX_SIZE * sizeof(void *)]; static char eth_rx_thread_stack[RT_LWIP_ETHTHREAD_STACKSIZE]; #endif #endif @@ -385,7 +385,7 @@ static err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p) /* send a message to eth tx thread */ msg.netif = netif; msg.buf = p; - if (rt_mb_send(ð_tx_thread_mb, (rt_uint32_t) &msg) == RT_EOK) + if (rt_mb_send(ð_tx_thread_mb, (rt_ubase_t) &msg) == RT_EOK) { /* waiting for ack */ rt_sem_take(&(enetif->tx_ack), RT_WAITING_FOREVER); @@ -592,7 +592,7 @@ rt_err_t eth_device_ready(struct eth_device* dev) { if (dev->netif) /* post message to Ethernet thread */ - return rt_mb_send(ð_rx_thread_mb, (rt_uint32_t)dev); + return rt_mb_send(ð_rx_thread_mb, (rt_ubase_t)dev); else return ERR_OK; /* netif is not initialized yet, just return. */ } @@ -612,7 +612,7 @@ rt_err_t eth_device_linkchange(struct eth_device* dev, rt_bool_t up) rt_hw_interrupt_enable(level); /* post message to ethernet thread */ - return rt_mb_send(ð_rx_thread_mb, (rt_uint32_t)dev); + return rt_mb_send(ð_rx_thread_mb, (rt_ubase_t)dev); } #else /* NOTE: please not use it in interrupt when no RxThread exist */ @@ -632,7 +632,6 @@ rt_err_t eth_device_linkchange(struct eth_device* dev, rt_bool_t up) static void eth_tx_thread_entry(void* parameter) { struct eth_tx_msg* msg; - while (1) { if (rt_mb_recv(ð_tx_thread_mb, (rt_ubase_t *)&msg, RT_WAITING_FOREVER) == RT_EOK) @@ -664,7 +663,6 @@ static void eth_tx_thread_entry(void* parameter) static void eth_rx_thread_entry(void* parameter) { struct eth_device* device; - while (1) { if (rt_mb_recv(ð_rx_thread_mb, (rt_ubase_t *)&device, RT_WAITING_FOREVER) == RT_EOK) @@ -723,7 +721,6 @@ int eth_system_device_init(void) { return 0; } - int eth_system_device_init_private(void) { rt_err_t result = RT_EOK; @@ -732,7 +729,7 @@ int eth_system_device_init_private(void) #ifndef LWIP_NO_RX_THREAD /* initialize mailbox and create Ethernet Rx thread */ result = rt_mb_init(ð_rx_thread_mb, "erxmb", - ð_rx_thread_mb_pool[0], sizeof(eth_rx_thread_mb_pool)/4, + ð_rx_thread_mb_pool[0], sizeof(eth_rx_thread_mb_pool)/sizeof(void *), RT_IPC_FLAG_FIFO); RT_ASSERT(result == RT_EOK); @@ -748,7 +745,7 @@ int eth_system_device_init_private(void) #ifndef LWIP_NO_TX_THREAD /* initialize mailbox and create Ethernet Tx thread */ result = rt_mb_init(ð_tx_thread_mb, "etxmb", - ð_tx_thread_mb_pool[0], sizeof(eth_tx_thread_mb_pool)/4, + ð_tx_thread_mb_pool[0], sizeof(eth_tx_thread_mb_pool)/sizeof(void *), RT_IPC_FLAG_FIFO); RT_ASSERT(result == RT_EOK); @@ -758,9 +755,9 @@ int eth_system_device_init_private(void) RT_ASSERT(result == RT_EOK); result = rt_thread_startup(ð_tx_thread); + RT_ASSERT(result == RT_EOK); #endif - return (int)result; } diff --git a/components/net/netdev/src/netdev.c b/components/net/netdev/src/netdev.c index aa43d8d3db6216192540e67299c0ef45e262d8ac..7c4c50671108601255b4144b649bbe41d6cc9714 100644 --- a/components/net/netdev/src/netdev.c +++ b/components/net/netdev/src/netdev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -732,6 +732,14 @@ static void netdev_auto_change_default(struct netdev *netdev) { struct netdev *new_netdev = RT_NULL; + if (netdev->flags & NETDEV_FLAG_LINK_UP) + { + if (!(netdev_default->flags & NETDEV_FLAG_LINK_UP)) + { + netdev_set_default(netdev); + } + return; + } if (rt_memcmp(netdev, netdev_default, sizeof(struct netdev)) == 0) { new_netdev = netdev_get_first_by_flags(NETDEV_FLAG_LINK_UP); @@ -805,12 +813,12 @@ void netdev_low_level_set_link_status(struct netdev *netdev, rt_bool_t is_up) /* set network interface device flags to internet down */ netdev->flags &= ~NETDEV_FLAG_INTERNET_UP; + } #ifdef NETDEV_USING_AUTO_DEFAULT /* change to the first link_up network interface device automatically */ netdev_auto_change_default(netdev); #endif /* NETDEV_USING_AUTO_DEFAULT */ - } /* execute link status change callback function */ if (netdev->status_callback) @@ -988,6 +996,28 @@ int netdev_ifconfig(int argc, char **argv) { netdev_list_if(); } + else if (argc == 3) + { + if (!strcmp(argv[2], "dhcp")) + { + struct netdev *netdev = RT_NULL; + netdev = netdev_get_by_name(argv[1]); + netdev_dhcp_enabled(netdev, 1); + rt_kprintf("config : %s func : %s value : %s\n", argv[1], "dhcp", "1"); + } + else if (!strcmp(argv[2], "-dhcp")) + { + struct netdev *netdev = RT_NULL; + netdev = netdev_get_by_name(argv[1]); + netdev_dhcp_enabled(netdev, 0); + rt_kprintf("config : %s func : %s value : %s\n", argv[1], "dhcp", "0"); + } + else + { + rt_kprintf("bad parameter! e.g: ifconfig e1 dhcp\n"); + rt_kprintf("bad parameter! e.g: ifconfig e1 -dhcp\n"); + } + } else if (argc == 5) { rt_kprintf("config : %s\n", argv[1]); @@ -998,7 +1028,9 @@ int netdev_ifconfig(int argc, char **argv) } else { - rt_kprintf("bad parameter! e.g: ifconfig e0 192.168.1.30 192.168.1.1 255.255.255.0\n"); + rt_kprintf("bad parameter! e.g: ifconfig e1 192.168.1.30 192.168.1.1 255.255.255.0\n"); + rt_kprintf("bad parameter! e.g: ifconfig e1 dhcp\n"); + rt_kprintf("bad parameter! e.g: ifconfig e1 -dhcp\n"); } return 0; diff --git a/components/net/netdev/src/netdev_ipaddr.c b/components/net/netdev/src/netdev_ipaddr.c index a70a90bb75ccb34c6ee19441144b00adb31ea365..a0f4e2f97f2bc55e3ba35bfedbc881f67714da5a 100644 --- a/components/net/netdev/src/netdev_ipaddr.c +++ b/components/net/netdev/src/netdev_ipaddr.c @@ -9,6 +9,7 @@ */ #include +#include #include /* Here for now until needed in other places in lwIP */ diff --git a/components/net/sal_socket/dfs_net/dfs_net.c b/components/net/sal_socket/dfs_net/dfs_net.c index f1a3d777a181a2204a4f7104c81f920f67690bd0..35f03b56f6784ea558fe10bcb60ec247d78e982f 100644 --- a/components/net/sal_socket/dfs_net/dfs_net.c +++ b/components/net/sal_socket/dfs_net/dfs_net.c @@ -21,44 +21,69 @@ int dfs_net_getsocket(int fd) { int socket; - struct dfs_fd *_dfs_fd; + struct dfs_fd *_dfs_fd; _dfs_fd = fd_get(fd); if (_dfs_fd == NULL) return -1; - if (_dfs_fd->type != FT_SOCKET) socket = -1; - else socket = (int)_dfs_fd->data; + if (_dfs_fd->fnode->type != FT_SOCKET) socket = -1; + else socket = (int)(size_t)_dfs_fd->fnode->data; - fd_put(_dfs_fd); /* put this dfs fd */ return socket; } static int dfs_net_ioctl(struct dfs_fd* file, int cmd, void* args) { - int socket = (int) file->data; - - return sal_ioctlsocket(socket, cmd, args); + int ret; + int socket = (int)(size_t)file->fnode->data; + + ret = sal_ioctlsocket(socket, cmd, args); + if (ret < 0) + { + ret = rt_get_errno(); + return (ret > 0) ? (-ret) : ret; + } + return ret; } static int dfs_net_read(struct dfs_fd* file, void *buf, size_t count) { - int socket = (int) file->data; - - return sal_recvfrom(socket, buf, count, 0, NULL, NULL); + int ret; + int socket = (int)(size_t)file->fnode->data; + + ret = sal_recvfrom(socket, buf, count, 0, NULL, NULL); + if (ret < 0) + { + ret = rt_get_errno(); + return (ret > 0) ? (-ret) : ret; + } + return ret; } static int dfs_net_write(struct dfs_fd *file, const void *buf, size_t count) { - int socket = (int) file->data; - - return sal_sendto(socket, buf, count, 0, NULL, 0); + int ret; + int socket = (int)(size_t)file->fnode->data; + + ret = sal_sendto(socket, buf, count, 0, NULL, 0); + if (ret < 0) + { + ret = rt_get_errno(); + return (ret > 0) ? (-ret) : ret; + } + return ret; } - static int dfs_net_close(struct dfs_fd* file) { - int socket = (int) file->data; - - return sal_closesocket(socket); + int socket; + int ret = 0; + + if (file->fnode->ref_count == 1) + { + socket = (int)(size_t)file->fnode->data; + ret = sal_closesocket(socket); + } + return ret; } static int dfs_net_poll(struct dfs_fd *file, struct rt_pollreq *req) @@ -68,7 +93,7 @@ static int dfs_net_poll(struct dfs_fd *file, struct rt_pollreq *req) return sal_poll(file, req); } -const struct dfs_file_ops _net_fops = +const struct dfs_file_ops _net_fops = { NULL, /* open */ dfs_net_close, diff --git a/components/net/sal_socket/impl/af_inet_lwip.c b/components/net/sal_socket/impl/af_inet_lwip.c index 56df735ab99021e36eb18db4406f36d973d7ff02..4dac99c00c2c49fef668d2abc6f3e2efc72cab1c 100644 --- a/components/net/sal_socket/impl/af_inet_lwip.c +++ b/components/net/sal_socket/impl/af_inet_lwip.c @@ -165,7 +165,7 @@ static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len if (event) { - rt_wqueue_wakeup(&sock->wait_head, (void*) event); + rt_wqueue_wakeup(&sock->wait_head, (void*)(size_t)event); } } #endif /* SAL_USING_POSIX */ @@ -229,7 +229,7 @@ int inet_ioctlsocket(int socket, long cmd, void *arg) { case F_GETFL: case F_SETFL: - return lwip_fcntl(socket, cmd, (int) arg); + return lwip_fcntl(socket, cmd, (int)(size_t)arg); default: return lwip_ioctl(socket, cmd, arg); @@ -243,13 +243,13 @@ static int inet_poll(struct dfs_fd *file, struct rt_pollreq *req) struct lwip_sock *sock; struct sal_socket *sal_sock; - sal_sock = sal_get_socket((int) file->data); + sal_sock = sal_get_socket((int)(size_t)file->fnode->data); if(!sal_sock) { return -1; } - sock = lwip_tryget_socket((int)sal_sock->user_data); + sock = lwip_tryget_socket((int)(size_t)sal_sock->user_data); if (sock != NULL) { rt_base_t level; diff --git a/components/net/sal_socket/include/sal_socket.h b/components/net/sal_socket/include/sal_socket.h index b620bbe23cf602a5734cf6815c4b84689d768814..92ba418682ebb175dab65bc5087fadff4ca29812 100644 --- a/components/net/sal_socket/include/sal_socket.h +++ b/components/net/sal_socket/include/sal_socket.h @@ -35,8 +35,12 @@ typedef uint16_t in_port_t; #define SOCK_STREAM 1 #define SOCK_DGRAM 2 #define SOCK_RAW 3 +#define SOCK_PACKET 10 -#define SOCK_MAX (SOCK_RAW + 1) +#define SOCK_NONBLOCK 04000 +#define SOCK_CLOEXEC 02000000 + +#define SOCK_MAX (SOCK_CLOEXEC + 1) /* Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c) */ #define SO_REUSEADDR 0x0004 /* Allow local address reuse */ @@ -193,6 +197,40 @@ struct sockaddr_storage #endif /* NETDEV_IPV6 */ }; +#define IFNAMSIZ 16 +struct sal_ifmap +{ + unsigned long int mem_start; + unsigned long int mem_end; + unsigned short int base_addr; + unsigned char irq; + unsigned char dma; + unsigned char port; +}; + +struct sal_ifreq +{ + union + { + char ifrn_name[IFNAMSIZ]; + } ifr_ifrn; + union + { + struct sockaddr ifru_addr; + struct sockaddr ifru_dstaddr; + struct sockaddr ifru_broadaddr; + struct sockaddr ifru_netmask; + struct sockaddr ifru_hwaddr; + short int ifru_flags; + int ifru_ivalue; + int ifru_mtu; + struct sal_ifmap ifru_map; + char ifru_slave[IFNAMSIZ]; + char ifru_newname[IFNAMSIZ]; + char *ifru_data; + } ifr_ifru; +}; + int sal_accept(int socket, struct sockaddr *addr, socklen_t *addrlen); int sal_bind(int socket, const struct sockaddr *name, socklen_t namelen); int sal_shutdown(int socket, int how); diff --git a/components/net/sal_socket/socket/net_sockets.c b/components/net/sal_socket/socket/net_sockets.c index a53b2f1f9c4fffe4f26a4789fc3a36c42b9560b0..9bc7edf69900c1ce0dc8dec56ba1d753d750a871 100644 --- a/components/net/sal_socket/socket/net_sockets.c +++ b/components/net/sal_socket/socket/net_sockets.c @@ -41,20 +41,28 @@ int accept(int s, struct sockaddr *addr, socklen_t *addrlen) if(d) { /* this is a socket fd */ - d->type = FT_SOCKET; - d->path = NULL; - - d->fops = dfs_net_get_fops(); - + d->fnode = (struct dfs_fnode *)rt_malloc(sizeof(struct dfs_fnode)); + if (!d->fnode) + { + /* release fd */ + fd_release(fd); + rt_set_errno(-ENOMEM); + return -1; + } + rt_memset(d->fnode, 0, sizeof(struct dfs_fnode)); + rt_list_init(&d->fnode->list); + + d->fnode->type = FT_SOCKET; + d->fnode->path = NULL; + d->fnode->fullpath = NULL; + d->fnode->ref_count = 1; + d->fnode->fops = dfs_net_get_fops(); d->flags = O_RDWR; /* set flags as read and write */ - d->size = 0; + d->fnode->size = 0; d->pos = 0; /* set socket to the data of dfs_fd */ - d->data = (void *) new_socket; - - /* release the ref-count of fd */ - fd_put(d); + d->fnode->data = (void *)(size_t)new_socket; return fd; } @@ -95,7 +103,7 @@ int shutdown(int s, int how) rt_set_errno(-EBADF); return -1; } - + if (sal_shutdown(socket, how) == 0) { error = 0; @@ -105,8 +113,6 @@ int shutdown(int s, int how) rt_set_errno(-ENOTSOCK); error = -1; } - - fd_put(d); return error; } @@ -210,38 +216,44 @@ int socket(int domain, int type, int protocol) return -1; } d = fd_get(fd); + d->fnode = (struct dfs_fnode *)rt_malloc(sizeof(struct dfs_fnode)); + if (!d->fnode) + { + /* release fd */ + fd_release(fd); + rt_set_errno(-ENOMEM); + return -1; + } /* create socket and then put it to the dfs_fd */ socket = sal_socket(domain, type, protocol); if (socket >= 0) { + rt_memset(d->fnode, 0, sizeof(struct dfs_fnode)); + rt_list_init(&d->fnode->list); /* this is a socket fd */ - d->type = FT_SOCKET; - d->path = NULL; - - d->fops = dfs_net_get_fops(); + d->fnode->type = FT_SOCKET; + d->fnode->path = NULL; + d->fnode->fullpath = NULL; + d->fnode->ref_count = 1; + d->fnode->fops = dfs_net_get_fops(); d->flags = O_RDWR; /* set flags as read and write */ - d->size = 0; + d->fnode->size = 0; d->pos = 0; /* set socket to the data of dfs_fd */ - d->data = (void *) socket; + d->fnode->data = (void *)(size_t)socket; } else { + rt_free(d->fnode); /* release fd */ - fd_put(d); - fd_put(d); - + fd_release(fd); rt_set_errno(-ENOMEM); - return -1; } - /* release the ref-count of fd */ - fd_put(d); - return fd; } RTM_EXPORT(socket); @@ -266,6 +278,12 @@ int closesocket(int s) return -1; } + if (!d->fnode) + { + rt_set_errno(-EBADF); + return -1; + } + if (sal_closesocket(socket) == 0) { error = 0; @@ -276,9 +294,9 @@ int closesocket(int s) error = -1; } + rt_free(d->fnode); /* socket has been closed, delete it from file system fd */ - fd_put(d); - fd_put(d); + fd_release(s); return error; } diff --git a/components/net/sal_socket/src/sal_socket.c b/components/net/sal_socket/src/sal_socket.c index ec0519df0238829d79255d08c32f1f5ff4213f95..54ed2e5bc73c6c57713a0440f1592400f66d5c18 100644 --- a/components/net/sal_socket/src/sal_socket.c +++ b/components/net/sal_socket/src/sal_socket.c @@ -570,7 +570,7 @@ int sal_accept(int socket, struct sockaddr *addr, socklen_t *addrlen) /* check the network interface socket operations */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, accept); - new_socket = pf->skt_ops->accept((int) sock->user_data, addr, addrlen); + new_socket = pf->skt_ops->accept((int)(size_t)sock->user_data, addr, addrlen); if (new_socket != -1) { int retval; @@ -598,7 +598,7 @@ int sal_accept(int socket, struct sockaddr *addr, socklen_t *addrlen) } /* socket structure user_data used to store the acquired new socket */ - new_sock->user_data = (void *) new_socket; + new_sock->user_data = (void *)(size_t)new_socket; return new_sal_socket; } @@ -664,13 +664,13 @@ int sal_bind(int socket, const struct sockaddr *name, socklen_t namelen) return -1; } sock->netdev = new_netdev; - sock->user_data = (void *) new_socket; + sock->user_data = (void *)(size_t)new_socket; } } /* check and get protocol families by the network interface device */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, bind); - return pf->skt_ops->bind((int) sock->user_data, name, namelen); + return pf->skt_ops->bind((int)(size_t)sock->user_data, name, namelen); } int sal_shutdown(int socket, int how) @@ -686,7 +686,7 @@ int sal_shutdown(int socket, int how) /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, shutdown); - if (pf->skt_ops->shutdown((int) sock->user_data, how) == 0) + if (pf->skt_ops->shutdown((int)(size_t)sock->user_data, how) == 0) { #ifdef SAL_USING_TLS if (SAL_SOCKOPS_PROTO_TLS_VALID(sock, closesocket)) @@ -719,7 +719,7 @@ int sal_getpeername(int socket, struct sockaddr *name, socklen_t *namelen) /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, getpeername); - return pf->skt_ops->getpeername((int) sock->user_data, name, namelen); + return pf->skt_ops->getpeername((int)(size_t)sock->user_data, name, namelen); } int sal_getsockname(int socket, struct sockaddr *name, socklen_t *namelen) @@ -733,7 +733,7 @@ int sal_getsockname(int socket, struct sockaddr *name, socklen_t *namelen) /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, getsockname); - return pf->skt_ops->getsockname((int) sock->user_data, name, namelen); + return pf->skt_ops->getsockname((int)(size_t)sock->user_data, name, namelen); } int sal_getsockopt(int socket, int level, int optname, void *optval, socklen_t *optlen) @@ -747,7 +747,7 @@ int sal_getsockopt(int socket, int level, int optname, void *optval, socklen_t * /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, getsockopt); - return pf->skt_ops->getsockopt((int) sock->user_data, level, optname, optval, optlen); + return pf->skt_ops->getsockopt((int)(size_t)sock->user_data, level, optname, optval, optlen); } int sal_setsockopt(int socket, int level, int optname, const void *optval, socklen_t optlen) @@ -793,7 +793,7 @@ int sal_setsockopt(int socket, int level, int optname, const void *optval, sockl return pf->skt_ops->setsockopt((int) sock->user_data, level, optname, optval, optlen); } #else - return pf->skt_ops->setsockopt((int) sock->user_data, level, optname, optval, optlen); + return pf->skt_ops->setsockopt((int)(size_t)sock->user_data, level, optname, optval, optlen); #endif /* SAL_USING_TLS */ } @@ -811,7 +811,7 @@ int sal_connect(int socket, const struct sockaddr *name, socklen_t namelen) /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, connect); - ret = pf->skt_ops->connect((int) sock->user_data, name, namelen); + ret = pf->skt_ops->connect((int)(size_t)sock->user_data, name, namelen); #ifdef SAL_USING_TLS if (ret >= 0 && SAL_SOCKOPS_PROTO_TLS_VALID(sock, connect)) { @@ -838,7 +838,7 @@ int sal_listen(int socket, int backlog) /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, listen); - return pf->skt_ops->listen((int) sock->user_data, backlog); + return pf->skt_ops->listen((int)(size_t)sock->user_data, backlog); } int sal_recvfrom(int socket, void *mem, size_t len, int flags, @@ -868,10 +868,10 @@ int sal_recvfrom(int socket, void *mem, size_t len, int flags, } else { - return pf->skt_ops->recvfrom((int) sock->user_data, mem, len, flags, from, fromlen); + return pf->skt_ops->recvfrom((int)(size_t)sock->user_data, mem, len, flags, from, fromlen); } #else - return pf->skt_ops->recvfrom((int) sock->user_data, mem, len, flags, from, fromlen); + return pf->skt_ops->recvfrom((int)(size_t)sock->user_data, mem, len, flags, from, fromlen); #endif } @@ -905,7 +905,7 @@ int sal_sendto(int socket, const void *dataptr, size_t size, int flags, return pf->skt_ops->sendto((int) sock->user_data, dataptr, size, flags, to, tolen); } #else - return pf->skt_ops->sendto((int) sock->user_data, dataptr, size, flags, to, tolen); + return pf->skt_ops->sendto((int)(size_t)sock->user_data, dataptr, size, flags, to, tolen); #endif } @@ -957,7 +957,7 @@ int sal_socket(int domain, int type, int protocol) } } #endif - sock->user_data = (void *) proto_socket; + sock->user_data = (void *)(size_t)proto_socket; return sock->socket; } socket_delete(socket); @@ -977,7 +977,7 @@ int sal_closesocket(int socket) /* valid the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, socket); - if (pf->skt_ops->closesocket((int) sock->user_data) == 0) + if (pf->skt_ops->closesocket((int)(size_t)sock->user_data) == 0) { #ifdef SAL_USING_TLS if (SAL_SOCKOPS_PROTO_TLS_VALID(sock, closesocket)) @@ -1005,14 +1005,68 @@ int sal_ioctlsocket(int socket, long cmd, void *arg) { struct sal_socket *sock; struct sal_proto_family *pf; - + struct sockaddr_in *addr_in = RT_NULL; + struct sockaddr *addr = RT_NULL; + ip_addr_t input_ipaddr; /* get the socket object by socket descriptor */ SAL_SOCKET_OBJ_GET(sock, socket); - /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, ioctlsocket); - return pf->skt_ops->ioctlsocket((int) sock->user_data, cmd, arg); + struct sal_ifreq *ifr = (struct sal_ifreq *)arg; + + if((sock->domain == AF_INET)&&(sock->netdev)&&(ifr != RT_NULL)) + { + switch (cmd) + { + case SIOCGIFADDR: + addr_in = (struct sockaddr_in *)&(ifr->ifr_ifru.ifru_addr); +#if NETDEV_IPV4 && NETDEV_IPV6 + addr_in->sin_addr.s_addr = sock->netdev->ip_addr.u_addr.ip4.addr; +#elif NETDEV_IPV4 + addr_in->sin_addr.s_addr = sock->netdev->ip_addr.addr; +#elif NETDEV_IPV6 +#error "not only support IPV6" +#endif /* NETDEV_IPV4 && NETDEV_IPV6*/ + return 0; + + case SIOCSIFADDR: + addr = (struct sockaddr *)&(ifr->ifr_ifru.ifru_addr); + sal_sockaddr_to_ipaddr(addr,&input_ipaddr); + netdev_set_ipaddr(sock->netdev,&input_ipaddr); + return 0; + + case SIOCGIFNETMASK: + addr_in = (struct sockaddr_in *)&(ifr->ifr_ifru.ifru_netmask); +#if NETDEV_IPV4 && NETDEV_IPV6 + addr_in->sin_addr.s_addr = sock->netdev->netmask.u_addr.ip4.addr; +#elif NETDEV_IPV4 + addr_in->sin_addr.s_addr = sock->netdev->netmask.addr; +#elif NETDEV_IPV6 +#error "not only support IPV6" +#endif /* NETDEV_IPV4 && NETDEV_IPV6*/ + return 0; + + case SIOCSIFNETMASK: + addr = (struct sockaddr *)&(ifr->ifr_ifru.ifru_netmask); + sal_sockaddr_to_ipaddr(addr,&input_ipaddr); + netdev_set_netmask(sock->netdev,&input_ipaddr); + return 0; + + case SIOCGIFHWADDR: + addr = (struct sockaddr *)&(ifr->ifr_ifru.ifru_hwaddr); + rt_memcpy(addr->sa_data,sock->netdev->hwaddr,sock->netdev->hwaddr_len); + return 0; + + case SIOCGIFMTU: + ifr->ifr_ifru.ifru_mtu = sock->netdev->mtu; + return 0; + + default: + break; + } + } + return pf->skt_ops->ioctlsocket((int)(size_t)sock->user_data, cmd, arg); } #ifdef SAL_USING_POSIX @@ -1020,7 +1074,7 @@ int sal_poll(struct dfs_fd *file, struct rt_pollreq *req) { struct sal_socket *sock; struct sal_proto_family *pf; - int socket = (int) file->data; + int socket = (int)(size_t)file->fnode->data; /* get the socket object by socket descriptor */ SAL_SOCKET_OBJ_GET(sock, socket); diff --git a/components/utilities/Kconfig b/components/utilities/Kconfig index 8b733ecf5c6e9f9c8097023da66f10cb0284710f..eff7ec304e1df645a09a3ee91f1c57948155dce8 100644 --- a/components/utilities/Kconfig +++ b/components/utilities/Kconfig @@ -205,4 +205,5 @@ config RT_USING_UTEST default 20 endif +source "$RTT_DIR/components/utilities/rt-link/Kconfig" endmenu diff --git a/components/utilities/resource/SConscript b/components/utilities/resource/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..0ab526788f3c97463551e5b1e8fa4a06dad57adc --- /dev/null +++ b/components/utilities/resource/SConscript @@ -0,0 +1,8 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] +group = DefineGroup('resource', src, depend = [], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/utilities/resource/resource_id.c b/components/utilities/resource/resource_id.c new file mode 100644 index 0000000000000000000000000000000000000000..43f64e7b03815f4cc0c2e6ec3ccb9ff82622ff14 --- /dev/null +++ b/components/utilities/resource/resource_id.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-25 RT-Thread First version + */ +#include +#include +#include + +void resource_id_init(resource_id_t *mgr, int size, void **res) +{ + if (mgr) + { + mgr->size = size; + mgr->_res = res; + mgr->noused = 0; + mgr->_free = RT_NULL; + } +} + +int resource_id_get(resource_id_t *mgr) +{ + rt_base_t level; + void **cur; + + level = rt_hw_interrupt_disable(); + if (mgr->_free) + { + cur = mgr->_free; + mgr->_free = (void **)*mgr->_free; + rt_hw_interrupt_enable(level); + return cur - mgr->_res; + } + else if (mgr->noused < mgr->size) + { + cur = &mgr->_res[mgr->noused++]; + rt_hw_interrupt_enable(level); + return cur - mgr->_res; + } + rt_hw_interrupt_enable(level); + return -1; +} + +void resource_id_put(resource_id_t *mgr, int no) +{ + rt_base_t level; + void **cur; + + if (no >= 0 && no < mgr->size) + { + level = rt_hw_interrupt_disable(); + cur = &mgr->_res[no]; + *cur = (void *)mgr->_free; + mgr->_free = cur; + rt_hw_interrupt_enable(level); + } +} + diff --git a/components/utilities/resource/resource_id.h b/components/utilities/resource/resource_id.h new file mode 100644 index 0000000000000000000000000000000000000000..9706a3cbaf98b414bfb3d4a759d65b53337f1d08 --- /dev/null +++ b/components/utilities/resource/resource_id.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-25 RT-Thread First version + */ + +#ifndef RESOURCE_ID_H__ +#define RESOURCE_ID_H__ + +#include +#include + +#define RESOURCE_ID_INIT(size, pool) {size, pool, 0, RT_NULL} + +typedef struct +{ + int size; + void **_res; + int noused; + void **_free; +} resource_id_t; + +void resource_id_init(resource_id_t *mgr, int size, void **res); +int resource_id_get(resource_id_t *mgr); +void resource_id_put(resource_id_t *mgr, int no); + +#endif /*RESOURCE_ID_H__*/ diff --git a/components/utilities/rt-link/Kconfig b/components/utilities/rt-link/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..10ed129e69eb441df97187020ff99c268b31272c --- /dev/null +++ b/components/utilities/rt-link/Kconfig @@ -0,0 +1,40 @@ +# Kconfig file for rt_link +menuconfig RT_USING_RT_LINK + bool "RT-Link" + default n + +if RT_USING_RT_LINK + choice + prompt"use hw crc device or not" + default RT_LINK_USING_SF_CRC + + config RT_LINK_USING_SF_CRC + bool "use software crc table" + config RT_LINK_USING_HW_CRC + bool "use hardware crc device" + endchoice + + menu "rt-link hardware device configuration" + config RT_LINK_HW_DEVICE_NAME + string "the name of base actual device" + default "uart2" + + choice + prompt"hardware device is spi, uart or usb" + default RT_LINK_USING_UART + + config RT_LINK_USING_UART + bool "use UART" + endchoice + + endmenu + + menu "rt link debug option" + config USING_RT_LINK_DEBUG + bool "Enable RT-Link debug" + default n + config USING_RT_LINK_HW_DEBUG + bool "Enable RT-Link hw debug" + default n + endmenu +endif diff --git a/components/utilities/rt-link/SConscript b/components/utilities/rt-link/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..4c815c49b835a3a5ea61f337dc17154dd316d7d1 --- /dev/null +++ b/components/utilities/rt-link/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/components/utilities/rt-link/hw_port/SConscript b/components/utilities/rt-link/hw_port/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e34243ebdaf9515ba586b4c7e997aeffcce4c7a9 --- /dev/null +++ b/components/utilities/rt-link/hw_port/SConscript @@ -0,0 +1,14 @@ +import os +from building import * +import rtconfig + +cwd = GetCurrentDir() +src = [] +CPPPATH = [] + +if GetDepend('RT_LINK_USING_UART'): + src += ['uart/rtlink_port_uart.c'] + +group = DefineGroup('rt-link-port', src, depend = ['RT_USING_RT_LINK'], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/utilities/rt-link/hw_port/uart/rtlink_port_uart.c b/components/utilities/rt-link/hw_port/uart/rtlink_port_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..48fbb91bc3d74047cf398ff672bfca90633aba99 --- /dev/null +++ b/components/utilities/rt-link/hw_port/uart/rtlink_port_uart.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-09 xiangxistu the first version + */ + +#include +#include + +#include + +#ifndef RT_LINK_HW_DEVICE_NAME + #define RT_LINK_HW_DEVICE_NAME "uart2" +#endif + +#define DBG_TAG "rtlink_port" +#define DBG_LVL DBG_INFO +#include + +static struct rt_device *hw_device = RT_NULL; +rt_err_t rt_link_port_rx_ind(rt_device_t device, rt_size_t size) +{ + RT_ASSERT(device != RT_NULL); + + rt_uint8_t buffer[RT_SERIAL_RB_BUFSZ] = {0}; + rt_size_t length = 0; + length = rt_device_read(device, 0, buffer, sizeof(buffer)); + rt_link_hw_write_cb(&buffer, length); + return RT_EOK; +} + +rt_size_t rt_link_port_send(void *data, rt_size_t length) +{ + rt_size_t size = 0; + size = rt_device_write(hw_device, 0, data, length); + return size; +} + +int rt_link_port_init(void) +{ + hw_device = rt_device_find(RT_LINK_HW_DEVICE_NAME); + if (hw_device) + { + rt_device_open(hw_device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_set_rx_indicate(hw_device, rt_link_port_rx_ind); + } + else + { + LOG_E("Not find device %s", RT_LINK_HW_DEVICE_NAME); + return -RT_ERROR; + } + return RT_EOK; +} + +int rt_link_port_deinit(void) +{ + hw_device = rt_device_find(RT_LINK_HW_DEVICE_NAME); + if (hw_device) + { + rt_device_close(hw_device); + rt_device_set_rx_indicate(hw_device, RT_NULL); + } + else + { + LOG_E("Not find device %s", RT_LINK_HW_DEVICE_NAME); + return -RT_ERROR; + } + return RT_EOK; +} diff --git a/components/utilities/rt-link/inc/rtlink.h b/components/utilities/rt-link/inc/rtlink.h new file mode 100644 index 0000000000000000000000000000000000000000..dd98b57c30a07a5e4b864593c0a021b75b13cce5 --- /dev/null +++ b/components/utilities/rt-link/inc/rtlink.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-02 xiangxistu the first version + * 2021-03-19 Sherman Streamline the struct rt_link_session + */ + +#ifndef __RT_LINK_H__ +#define __RT_LINK_H__ + +#include + +#define RT_LINK_AUTO_INIT + +#define RT_LINK_FRAME_HEAD 0x15 +#define RT_LINK_FRAME_HEAD_MASK 0x1F +#define RT_LINK_MAX_DATA_LENGTH 2044 /*can exact divide by 4 bytes*/ +#define RT_LINK_FRAMES_MAX 0x03 /* The maximum number of split frames for a long package*/ + +#define RT_LINK_ACK_MAX 0x07 +#define RT_LINK_CRC_LENGTH 4 +#define RT_LINK_HEAD_LENGTH 4 +#define RT_LINK_MAX_EXTEND_LENGTH 4 +#define RT_LINK_MAX_FRAME_LENGTH (RT_LINK_HEAD_LENGTH + RT_LINK_MAX_EXTEND_LENGTH + RT_LINK_MAX_DATA_LENGTH + RT_LINK_CRC_LENGTH) +#define RT_LINK_RECEIVE_BUFFER_LENGTH (RT_LINK_MAX_FRAME_LENGTH * RT_LINK_FRAMES_MAX + RT_LINK_HEAD_LENGTH + RT_LINK_MAX_EXTEND_LENGTH) + +typedef enum +{ + RT_LINK_SERVICE_RTLINK = 0, + RT_LINK_SERVICE_LINK_SOCKET = 1, + RT_LINK_SERVICE_LINK_WIFI = 2, + RT_LINK_SERVICE_LINK_MNGT = 3, + RT_LINK_SERVICE_LINK_MSHTOOLS = 4, + RT_LINK_SERVICE_MAX +} rt_link_service_t; + +enum +{ + FRAME_EXTEND = 1 << 0, + FRAME_CRC = 1 << 1, + FRAME_ACK = 1 << 2 +}; + +typedef enum +{ + RT_LINK_RESERVE_FRAME = 0, + + RT_LINK_RESEND_FRAME, + RT_LINK_CONFIRM_FRAME, + RT_LINK_SHORT_DATA_FRAME, + RT_LINK_LONG_DATA_FRAME, + RT_LINK_SESSION_END, /* The retring failed to end the session */ + + RT_LINK_HANDSHAKE_FRAME +} rt_link_frame_attribute_t; + +typedef enum +{ + /* receive event */ + RT_LINK_READ_CHECK_EVENT = 1 << 0, + RT_LINK_RECV_TIMEOUT_FRAME_EVENT = 1 << 1, + RT_LINK_RECV_TIMEOUT_LONG_EVENT = 1 << 2, + + /* send event */ + RT_LINK_SEND_READY_EVENT = 1 << 4, + RT_LINK_SEND_OK_EVENT = 1 << 5, + RT_LINK_SEND_FAILED_EVENT = 1 << 6, + RT_LINK_SEND_TIMEOUT_EVENT = 1 << 7 +} rt_link_notice_t; + +typedef enum +{ + RT_LINK_ESTABLISHING = 0, + RT_LINK_NO_RESPONSE, + RT_LINK_CONNECT_DONE, +} rt_link_linkstatus_t; + +typedef enum +{ + RECVTIMER_NONE = 0, + RECVTIMER_FRAME, + RECVTIMER_LONGFRAME +} rt_link_recvtimer_status_t; + +struct rt_link_receive_buffer +{ + rt_uint8_t data[RT_LINK_RECEIVE_BUFFER_LENGTH]; /* rt-link receive data buffer */ + rt_uint8_t *read_point; + rt_uint8_t *write_point; + rt_uint8_t *end_point; +}; + +struct rt_link_frame_head +{ + rt_uint8_t magicid : 5; + rt_uint8_t extend : 1; + rt_uint8_t crc : 1; + rt_uint8_t ack : 1; + rt_uint8_t sequence; + rt_uint16_t channel: 5; + rt_uint16_t length : 11; +}; + +/* record frame information that opposite */ +struct rt_link_record +{ + rt_uint8_t rx_seq; /* record the opposite sequence */ + rt_uint8_t total; /* the number of long frame number */ + rt_uint8_t long_count; /* long packet recv counter */ + rt_uint8_t *dataspace; /* the space of long frame */ +}; + +struct rt_link_extend +{ + rt_uint16_t attribute; /* rt_link_frame_attribute_t */ + rt_uint16_t parameter; +}; + +struct rt_link_frame +{ + struct rt_link_frame_head head; /* frame head */ + struct rt_link_extend extend; /* frame extend data */ + rt_uint8_t *real_data; /* the origin data */ + rt_uint32_t crc; /* CRC result */ + + rt_uint16_t data_len; /* the length of frame length */ + rt_uint16_t attribute; /* this will show frame attribute , rt_link_frame_attribute_t */ + + rt_uint8_t index; /* the index frame for long frame */ + rt_uint8_t total; /* the total frame for long frame */ + + rt_slist_t slist; /* the frame will hang on the send list on session */ +}; + +struct rt_link_service +{ + rt_err_t (*upload_callback)(void *data, rt_size_t size); +}; + +struct rt_link_session +{ + rt_link_linkstatus_t link_status; /* Link connection status*/ + struct rt_event event; /* the event that core logic */ + struct rt_link_service channel[RT_LINK_SERVICE_MAX]; /* thansfer to app layer */ + + rt_slist_t tx_data_slist; + rt_uint8_t tx_seq; /* sequence for frame */ + struct rt_mutex tx_lock; /* protect send data interface, only one thread can hold it */ + struct rt_timer sendtimer; /* send function timer for rt link */ + + struct rt_link_record rx_record; /* the memory of receive status */ + struct rt_timer recvtimer; /* receive a frame timer for rt link */ + struct rt_timer longframetimer; /* receive long frame timer for rt link */ + + struct rt_link_receive_buffer *rx_buffer; /* the buffer will store data */ + rt_uint32_t (*calculate_crc)(rt_uint8_t using_buffer_ring, rt_uint8_t *data, rt_size_t size); /* this function will calculate crc */ +}; + +/* rtlink init and deinit */ +int rt_link_init(void); +rt_err_t rt_link_deinit(void); +/* rtlink send data interface */ +rt_size_t rt_link_send(rt_link_service_t service, void *data, rt_size_t size); +/* rtlink service attach and detach */ +rt_err_t rt_link_service_attach(rt_link_service_t service, rt_err_t (*function)(void *data, rt_size_t size)); +rt_err_t rt_link_service_detach(rt_link_service_t service); + +/* Private operator function */ +struct rt_link_session *rt_link_get_scb(void); + +#endif /* __RT_LINK_H__ */ diff --git a/components/utilities/rt-link/inc/rtlink_hw.h b/components/utilities/rt-link/inc/rtlink_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..c75609a23a62ac5cfaf0ae168b2ba0cf8327b8e0 --- /dev/null +++ b/components/utilities/rt-link/inc/rtlink_hw.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-02 xiangxistu the first version + * + */ +#ifndef __RT_LINK_HW_H__ +#define __RT_LINK_HW_H__ + +#include + +rt_size_t rt_link_hw_recv_len(struct rt_link_receive_buffer *buffer); +void rt_link_hw_copy(rt_uint8_t *dst, rt_uint8_t *src, rt_size_t count); +void rt_link_hw_buffer_point_shift(rt_uint8_t **pointer_address, rt_size_t length); + +rt_err_t rt_link_hw_init(void); +rt_err_t rt_link_hw_deinit(void); +rt_err_t rt_link_hw_send(void *data, rt_size_t length); + +#endif /* _RT_LINK_PORT_INTERNAL_H_ */ diff --git a/components/utilities/rt-link/inc/rtlink_port.h b/components/utilities/rt-link/inc/rtlink_port.h new file mode 100644 index 0000000000000000000000000000000000000000..54a064d117a000cbc8ec025817a0d4ff599a9ace --- /dev/null +++ b/components/utilities/rt-link/inc/rtlink_port.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-02 xiangxistu the first version + * 2021-05-15 Sherman function rename + */ +#ifndef __RT_LINK_PORT_H__ +#define __RT_LINK_PORT_H__ + +#include + +/* Functions that need to be implemented at the hardware */ +int rt_link_port_init(void); +int rt_link_port_deinit(void); +rt_size_t rt_link_port_send(void *data, rt_size_t length); + +#ifdef RT_LINK_USING_HW_CRC + rt_err_t rt_link_hw_crc32_init(void); + rt_err_t rt_link_hw_crc32_deinit(void); + rt_err_t rt_link_hw_crc32_reset(void); + rt_uint32_t rt_link_hw_crc32(rt_uint8_t *data, rt_size_t u32_size) +#endif + +/* Called when the hardware receives data and the data is transferred to RTLink */ +rt_size_t rt_link_hw_write_cb(void *data, rt_size_t length); + +#endif /* __RT_LINK_PORT_H__ */ diff --git a/components/utilities/rt-link/inc/rtlink_utils.h b/components/utilities/rt-link/inc/rtlink_utils.h new file mode 100644 index 0000000000000000000000000000000000000000..564039c39001cce82e0c618a701fee4dd85e0e2c --- /dev/null +++ b/components/utilities/rt-link/inc/rtlink_utils.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-15 Sherman the first version + */ +#ifndef __RT_LINK_UTILITIES_H__ +#define __RT_LINK_UTILITIES_H__ + +#include + +/* Calculate the number of '1' */ +int rt_link_utils_num1(rt_uint32_t n); + +rt_err_t rt_link_sf_crc32_reset(void); +rt_uint32_t rt_link_sf_crc32(rt_uint8_t *data, rt_size_t len); + +#endif /* __RT_LINK_UTILITIES_H__ */ diff --git a/components/utilities/rt-link/src/SConscript b/components/utilities/rt-link/src/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..8bbb969b2a80a8c790664c960f89b53764eb84cb --- /dev/null +++ b/components/utilities/rt-link/src/SConscript @@ -0,0 +1,13 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd + '/../inc'] + +group = DefineGroup('rt-link', src, depend = ['RT_USING_RT_LINK'], CPPPATH = CPPPATH) + +if os.path.isfile(os.path.join(cwd, 'hw', 'SConscript')): + group = group + SConscript(os.path.join('hw', 'SConscript')) + +Return('group') diff --git a/components/utilities/rt-link/src/rtlink.c b/components/utilities/rt-link/src/rtlink.c new file mode 100644 index 0000000000000000000000000000000000000000..37a99538b6654caf399a3826e80eaa1ec070e40d --- /dev/null +++ b/components/utilities/rt-link/src/rtlink.c @@ -0,0 +1,1192 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-02 xiangxistu the first version + * 2021-03-19 Sherman Optimize the transfer process + * 2021-04-20 Sherman Optimize memory footprint + * 2021-05-10 Sherman Add rtlink_status MSH command; Optimize transmission timer Settings; Fix known bugs + */ + +#include +#include +#include +#include + +#include +#include +#include + +#define DBG_ENABLE +#ifdef USING_RT_LINK_DEBUG + #define DBG_LVL DBG_LOG +#else + #define DBG_LVL DBG_INFO +#endif +#define DBG_TAG "rtlink" +#define DBG_COLOR +#include + +#ifdef RT_LINK_USING_SPI + #define RT_LINK_LONG_FRAME_TIMEOUT 50 + #define RT_LINK_SENT_FRAME_TIMEOUT 100 +#else + #define RT_LINK_LONG_FRAME_TIMEOUT 100 + #define RT_LINK_SENT_FRAME_TIMEOUT 200 +#endif /* RT_LINK_USING_SPI */ + +#define RT_LINK_RECV_DATA_SEQUENCE 0 +#define RT_LINK_INIT_FRAME_SEQENCE 129 + +#define RT_LINK_THREAD_NAME "rtlink" +#define RT_LINK_THREAD_TICK 20 +#define RT_LINK_THREAD_PRIORITY 15 +#define RT_LINK_THREAD_STACK_SIZE 832 /* 32 bytes aligned */ + +typedef enum +{ + FIND_FRAME_HEAD = 0, + PARSE_FRAME_HEAD, + PARSE_FRAME_EXTEND, + PARSE_FRAME_SEQ, + CHECK_FRAME_CRC, + HEADLE_FRAME_DATA, +} rt_link_frame_parse_t; + +/* rtlink SCB(Session control block) */ +static struct rt_link_session *rt_link_scb = RT_NULL; +struct rt_link_session *rt_link_get_scb(void) +{ + return rt_link_scb; +} + +static rt_int16_t rt_link_check_seq(rt_uint8_t new, rt_uint8_t used) +{ + rt_int16_t compare_seq = 0; + compare_seq = new - used; + if (compare_seq < 0) + { + compare_seq = compare_seq + 256; + } + return compare_seq; +} + +static int rt_link_frame_init(struct rt_link_frame *frame, rt_uint8_t config) +{ + if (frame == RT_NULL) + { + return -RT_ERROR; + } + + /* set frame control information */ + rt_memset(&frame->head, 0, sizeof(struct rt_link_frame_head)); + if (config & FRAME_CRC) + { + frame->head.crc = 1; + } + if (config & FRAME_ACK) + { + frame->head.ack = 1; + } + + frame->head.magicid = RT_LINK_FRAME_HEAD; + /* frame data information */ + rt_memset(&frame->extend, 0, sizeof(struct rt_link_extend)); + frame->crc = 0; + frame->real_data = RT_NULL; + frame->data_len = 0; + frame->index = 0; + frame->total = 0; + frame->attribute = RT_LINK_RESERVE_FRAME; + + rt_slist_init(&frame->slist); + + return RT_EOK; +} + +static rt_err_t rt_link_frame_free(struct rt_link_frame *frame) +{ + if (frame == RT_NULL) + { + return -RT_ERROR; + } + + if (frame->real_data != RT_NULL) + { + rt_free(frame->real_data); + frame->real_data = RT_NULL; + } + rt_memset(frame, 0, sizeof(struct rt_link_frame)); + rt_free(frame); + return RT_EOK; +} + +/* performs data transmission */ +static rt_err_t rt_link_frame_send(rt_slist_t *slist) +{ + struct rt_link_frame *frame = RT_NULL; + rt_uint8_t *origin_data = RT_NULL; + rt_uint8_t *data = RT_NULL; + rt_size_t length = 0; + rt_uint8_t send_max = RT_LINK_ACK_MAX; /* The number of '1' in the binary number */ + + /* if slist is tx_data_slist, we should send all data on the slist*/ + if (slist == &rt_link_scb->tx_data_slist) + { + slist = rt_slist_next(&rt_link_scb->tx_data_slist); + } + if (slist == RT_NULL) + { + LOG_W("tx_data_slist NULL"); + return -RT_ERROR; + } + data = rt_malloc(RT_LINK_MAX_FRAME_LENGTH); + if (data == RT_NULL) + { + LOG_E("rt link alloc memory(%d B) failed, send frame failed.", RT_LINK_MAX_FRAME_LENGTH); + return -RT_ENOMEM; + } + origin_data = data; + + do + { + /* get frame for send */ + frame = rt_container_of(slist, struct rt_link_frame, slist); + slist = rt_slist_next(slist); + + length = RT_LINK_HEAD_LENGTH; + if (frame->head.crc) + { + length += RT_LINK_CRC_LENGTH; + } + if (frame->head.extend) + { + length += RT_LINK_MAX_EXTEND_LENGTH; + } + + length += frame->data_len; + frame->head.length = frame->data_len; + rt_memcpy(data, &frame->head, RT_LINK_HEAD_LENGTH); + data = data + RT_LINK_HEAD_LENGTH; + if (frame->head.extend) + { + rt_memcpy(data, &frame->extend, RT_LINK_MAX_EXTEND_LENGTH); + data = data + RT_LINK_MAX_EXTEND_LENGTH; + } + if (frame->attribute == RT_LINK_SHORT_DATA_FRAME || frame->attribute == RT_LINK_LONG_DATA_FRAME) + { + rt_memcpy(data, frame->real_data, frame->data_len); + data = data + frame->data_len; + } + if (frame->head.crc) + { + frame->crc = rt_link_scb->calculate_crc(RT_FALSE, origin_data, length - RT_LINK_CRC_LENGTH); + rt_memcpy(data, &frame->crc, RT_LINK_CRC_LENGTH); + } + + LOG_D("frame send(%d) len(%d) attr:(%d), crc:(0x%08x).", frame->head.sequence, length, frame->attribute, frame->crc); + rt_link_hw_send(origin_data, length); + + data = origin_data; + if (slist == RT_NULL) + { + send_max = 0; + } + send_max >>= 1; + }while (send_max); + rt_free(origin_data); + return RT_EOK; +} + +static void _stop_recv_long(void) +{ + rt_timer_stop(&rt_link_scb->longframetimer); + if (rt_link_scb->rx_record.dataspace != RT_NULL) + { + rt_free(rt_link_scb->rx_record.dataspace); + rt_link_scb->rx_record.dataspace = RT_NULL; + } + rt_link_scb->rx_record.long_count = 0; + rt_link_scb->rx_record.total = 0; +} + +static rt_err_t rt_link_frame_stop_receive(struct rt_link_frame *frame) +{ + rt_memset(frame, 0, sizeof(struct rt_link_frame)); + rt_link_hw_buffer_point_shift(&rt_link_scb->rx_buffer->read_point, rt_link_hw_recv_len(rt_link_scb->rx_buffer)); + return RT_EOK; +} + +/* Configure the extended field of the frame */ +static rt_err_t rt_link_frame_extend_config(struct rt_link_frame *frame, rt_link_frame_attribute_t attribute, rt_uint16_t parameter) +{ + frame->head.extend = 1; + frame->extend.attribute = attribute; + frame->extend.parameter = parameter; + return RT_EOK; +} + +static int rt_link_command_frame_send(rt_uint8_t sequence, rt_link_frame_attribute_t attribute, rt_uint16_t parameter) +{ + struct rt_link_frame command_frame = {0}; + rt_uint8_t extend_flag = RT_FALSE; + + /* command frame don't need crc and ack ability */ + rt_link_frame_init(&command_frame, RT_NULL); + command_frame.head.sequence = sequence; + command_frame.head.length = RT_LINK_MAX_EXTEND_LENGTH; + command_frame.attribute = attribute; + switch (attribute) + { + case RT_LINK_RESEND_FRAME: + extend_flag = RT_TRUE; + LOG_D("send RESEND_FRAME(%d).", command_frame.head.sequence); + break; + + case RT_LINK_HANDSHAKE_FRAME: + extend_flag = RT_TRUE; + LOG_D("send HANDSHAKE_FRAME(%d).", command_frame.head.sequence); + break; + + case RT_LINK_CONFIRM_FRAME: + LOG_D("send CONFIRM_FRAME(%d).", command_frame.head.sequence); + break; + + default: + break; + } + + if (extend_flag) + { + rt_link_frame_extend_config(&command_frame, attribute, parameter); + } + rt_link_frame_send(&command_frame.slist); + return RT_EOK; +} + +static rt_err_t rt_link_resend_handle(struct rt_link_frame *receive_frame) +{ + struct rt_link_frame *find_frame = RT_NULL; + rt_slist_t *tem_list = RT_NULL; + + tem_list = rt_slist_first(&rt_link_scb->tx_data_slist); + while (tem_list != RT_NULL) + { + find_frame = rt_container_of(tem_list, struct rt_link_frame, slist); + if (find_frame->head.sequence == receive_frame->head.sequence) + { + LOG_D("resend frame(%d)", find_frame->head.sequence); + rt_link_frame_send(&find_frame->slist); + break; + } + tem_list = tem_list->next; + } + + if (tem_list == RT_NULL) + { + LOG_D("frame resent failed, can't find(%d).", receive_frame->head.sequence); + rt_link_command_frame_send(receive_frame->head.sequence, RT_LINK_SESSION_END, RT_NULL); + } + return RT_EOK; +} + +static rt_err_t rt_link_confirm_handle(struct rt_link_frame *receive_frame) +{ + static struct rt_link_frame *send_frame = RT_NULL; + struct rt_link_frame *find_frame = RT_NULL; + rt_slist_t *tem_list = RT_NULL; + rt_uint16_t seq_offset = 0; + + LOG_D("confirm seq(%d) frame", receive_frame->head.sequence); + if (rt_link_scb->link_status == RT_LINK_NO_RESPONSE) + { + /* The handshake success and resends the data frame */ + LOG_D("link_status RT_LINK_CONNECT_DONE, resend data"); + rt_link_scb->link_status = RT_LINK_CONNECT_DONE; + if (rt_slist_first(&rt_link_scb->tx_data_slist)) + { + rt_event_send(&rt_link_scb->event, RT_LINK_SEND_READY_EVENT); + } + return RT_EOK; + } + + /* Check to see if the frame is send for confirm */ + tem_list = rt_slist_first(&rt_link_scb->tx_data_slist); + if (tem_list == RT_NULL) + { + return -RT_ERROR; + } + + send_frame = rt_container_of(tem_list, struct rt_link_frame, slist); + seq_offset = rt_link_check_seq(receive_frame->head.sequence, + rt_link_scb->tx_seq); + if (seq_offset <= send_frame->total) + { + LOG_D("confirm frame (%d)", receive_frame->head.sequence); + for (int i = 0; i < seq_offset; i++) + { + find_frame = rt_container_of(tem_list, struct rt_link_frame, slist); + LOG_D("confirm(%d), remove(%d)", receive_frame->head.sequence, find_frame->head.sequence); + + rt_enter_critical(); + rt_slist_remove(&rt_link_scb->tx_data_slist, &find_frame->slist); + rt_exit_critical(); + find_frame->real_data = RT_NULL; + rt_link_frame_free(find_frame); + + tem_list = rt_slist_first(&rt_link_scb->tx_data_slist); + if (tem_list == RT_NULL) + { + break; + } + } + rt_link_scb->tx_seq = receive_frame->head.sequence; + rt_link_scb->link_status = RT_LINK_CONNECT_DONE; + if (tem_list == RT_NULL) + { + LOG_D("SEND_OK"); + rt_event_send(&rt_link_scb->event, RT_LINK_SEND_OK_EVENT); + } + else + { + LOG_D("Continue sending"); + rt_event_send(&rt_link_scb->event, RT_LINK_SEND_READY_EVENT); + } + } + return RT_EOK; +} + +static rt_err_t rt_link_short_handle(struct rt_link_frame *receive_frame) +{ + LOG_D("Seq(%d) short data", receive_frame->head.sequence); + rt_link_scb->rx_record.dataspace = rt_malloc(receive_frame->data_len); + if (rt_link_scb->rx_record.dataspace != RT_NULL) + { + rt_link_command_frame_send(receive_frame->head.sequence, RT_LINK_CONFIRM_FRAME, RT_NULL); + rt_link_scb->rx_record.rx_seq = receive_frame->head.sequence; + + if (rt_link_scb->channel[receive_frame->head.channel].upload_callback == RT_NULL) + { + rt_free(rt_link_scb->rx_record.dataspace); + LOG_E("Channel %d has not been registered", receive_frame->head.channel); + } + else + { + rt_enter_critical(); + rt_link_hw_copy(rt_link_scb->rx_record.dataspace, receive_frame->real_data, receive_frame->data_len); + rt_exit_critical(); + rt_link_scb->channel[receive_frame->head.channel].upload_callback(rt_link_scb->rx_record.dataspace, receive_frame->data_len); + } + rt_link_scb->rx_record.dataspace = RT_NULL; + rt_link_frame_stop_receive(receive_frame); + } + else + { + LOG_W("short data %dB alloc failed", receive_frame->data_len); + } + receive_frame->real_data = RT_NULL; + return 0; +} + +static void _long_handle_first(struct rt_link_frame *receive_frame, rt_uint8_t *count_mask) +{ + if (receive_frame->extend.parameter % RT_LINK_MAX_DATA_LENGTH == 0) + { + receive_frame->total = receive_frame->extend.parameter / RT_LINK_MAX_DATA_LENGTH; + } + else + { + receive_frame->total = receive_frame->extend.parameter / RT_LINK_MAX_DATA_LENGTH + 1; + } + + rt_link_scb->rx_record.total = receive_frame->total; + rt_link_scb->rx_record.dataspace = rt_malloc(receive_frame->extend.parameter); + if (rt_link_scb->rx_record.dataspace == RT_NULL) + { + LOG_W("long data %dB alloc failed.", receive_frame->extend.parameter); + } + +} + +static void _long_handle_second(struct rt_link_frame *receive_frame, rt_uint8_t count_mask) +{ + static rt_uint8_t ack_mask = RT_LINK_ACK_MAX; + + void *data = RT_NULL; + rt_size_t size = 0; + rt_uint16_t serve = 0; + rt_size_t offset = 0; /* offset, count from 0 */ + + receive_frame->index = rt_link_check_seq(receive_frame->head.sequence, rt_link_scb->rx_record.rx_seq) - 1; + LOG_D("index= %d, count= 0x%x, seq(%d), rxseq(%d)", receive_frame->index, rt_link_scb->rx_record.long_count, receive_frame->head.sequence, rt_link_scb->rx_record.rx_seq); + + if ((receive_frame->index > RT_LINK_FRAMES_MAX) || (rt_link_scb->rx_record.long_count & (0x01 << receive_frame->index))) + { + LOG_D("ERR:index %d, rx_seq %d", receive_frame->index, rt_link_scb->rx_record.rx_seq); + } + else if (rt_link_scb->rx_record.dataspace != RT_NULL) + { + LOG_D("long_count (0x%02x)index(%d)total(%d) seq(%d)", rt_link_scb->rx_record.long_count, receive_frame->index, receive_frame->total, receive_frame->head.sequence); + rt_link_scb->rx_record.long_count |= (0x01 << receive_frame->index); + offset = RT_LINK_MAX_DATA_LENGTH * receive_frame->index; + + rt_enter_critical(); + rt_link_hw_copy(rt_link_scb->rx_record.dataspace + offset, receive_frame->real_data, receive_frame->data_len); + rt_exit_critical(); + + if (rt_link_utils_num1(rt_link_scb->rx_record.long_count) == rt_link_scb->rx_record.total) + { + rt_link_command_frame_send((rt_link_scb->rx_record.rx_seq + rt_link_scb->rx_record.total), RT_LINK_CONFIRM_FRAME, RT_NULL); + } + else if ((rt_link_scb->rx_record.long_count & ack_mask) == ack_mask) + { + rt_link_command_frame_send((rt_link_scb->rx_record.rx_seq + rt_link_utils_num1(ack_mask)), RT_LINK_CONFIRM_FRAME, RT_NULL); + ack_mask |= ack_mask << rt_link_utils_num1(RT_LINK_ACK_MAX); + } + + /* receive a complete package */ + if (rt_link_utils_num1(rt_link_scb->rx_record.long_count) == rt_link_scb->rx_record.total) + { + rt_timer_stop(&rt_link_scb->longframetimer); + + rt_enter_critical(); + data = rt_link_scb->rx_record.dataspace; + size = receive_frame->extend.parameter; + serve = receive_frame->head.channel; + /* empty rx_record */ + rt_link_scb->rx_record.rx_seq += rt_link_scb->rx_record.total; + rt_link_scb->rx_record.dataspace = RT_NULL; + rt_link_scb->rx_record.long_count = 0; + rt_link_scb->rx_record.total = 0; + ack_mask = RT_LINK_ACK_MAX; + rt_link_frame_stop_receive(receive_frame); + rt_exit_critical(); + + if (rt_link_scb->channel[serve].upload_callback == RT_NULL) + { + rt_free(data); + LOG_E("channel %d haven't been registered.", serve); + } + else + { + rt_link_scb->channel[serve].upload_callback(data, size); + } + } + else if (rt_link_hw_recv_len(rt_link_scb->rx_buffer) < (receive_frame->data_len % RT_LINK_MAX_DATA_LENGTH)) + { + rt_int32_t timeout = RT_LINK_LONG_FRAME_TIMEOUT; + rt_timer_control(&rt_link_scb->longframetimer, RT_TIMER_CTRL_SET_TIME, &timeout); + rt_timer_start(&rt_link_scb->longframetimer); + } + } +} + +static rt_err_t rt_link_long_handle(struct rt_link_frame *receive_frame) +{ + static rt_uint8_t count_mask = 0; + if (rt_link_scb->rx_record.long_count == 0) + { + /* Receive this long package for the first time: + * calculates the total number of frames, + * requests space, and turns on the receive timer */ + _long_handle_first(receive_frame, &count_mask); + } + if (rt_link_scb->rx_record.total > 0) + { + /* Intermediate frame processing: + * serial number repeated check, + * receive completion check, reply to ACK */ + _long_handle_second(receive_frame, count_mask); + } + receive_frame->real_data = RT_NULL; + return RT_EOK; +} + +static rt_err_t rt_link_handshake_handle(struct rt_link_frame *receive_frame) +{ + LOG_D("Sequence(%d) is a connect handshake frame.", receive_frame->head.sequence); + rt_link_scb->link_status = RT_LINK_CONNECT_DONE; + /* sync requester tx seq, responder rx seq = requester tx seq */ + rt_link_scb->rx_record.rx_seq = receive_frame->head.sequence; + /* sync requester rx seq, responder tx seq = requester rx seq */ + rt_link_scb->tx_seq = receive_frame->extend.parameter; + rt_link_command_frame_send(receive_frame->head.sequence, RT_LINK_CONFIRM_FRAME, RT_NULL); + return RT_EOK; +} + +/* Discriminate frame type */ +static rt_err_t rt_link_parse_frame(struct rt_link_frame *receive_frame) +{ + switch (receive_frame->attribute) + { + case RT_LINK_RESEND_FRAME: + rt_link_resend_handle(receive_frame); + break; + case RT_LINK_CONFIRM_FRAME: + rt_link_confirm_handle(receive_frame); + break; + case RT_LINK_SHORT_DATA_FRAME: + rt_link_short_handle(receive_frame); + break; + case RT_LINK_LONG_DATA_FRAME: + rt_link_long_handle(receive_frame); + break; + case RT_LINK_HANDSHAKE_FRAME: + rt_link_handshake_handle(receive_frame); + break; + case RT_LINK_SESSION_END: + rt_link_frame_stop_receive(receive_frame); + break; + default: + break; + } + return RT_EOK; +} + +/* Empty the sending list */ +static void rt_link_datalist_empty(void) +{ + struct rt_link_frame *find_frame = RT_NULL; + rt_slist_t *tem_list = rt_slist_first(&rt_link_scb->tx_data_slist); + while (tem_list != RT_NULL) + { + find_frame = rt_container_of(tem_list, struct rt_link_frame, slist); + tem_list = rt_slist_next(tem_list); + rt_enter_critical(); + rt_slist_remove(&rt_link_scb->tx_data_slist, &find_frame->slist); + rt_exit_critical(); + + find_frame->real_data = RT_NULL; + rt_link_frame_free(find_frame); + } +} + +/* RT_LINK_READ_CHECK_EVENT handle */ +static void rt_link_frame_check(void) +{ + static struct rt_link_frame receive_frame = {0}; + static rt_link_frame_parse_t analysis_status = FIND_FRAME_HEAD; + static rt_uint8_t *data = RT_NULL; + static rt_uint16_t buff_len = RT_LINK_HEAD_LENGTH; + + struct rt_link_frame *send_frame = RT_NULL; + rt_tick_t timeout = 0; + rt_uint8_t *real_data = RT_NULL; + rt_uint32_t temporary_crc = 0; + + rt_uint8_t offset = 0; + rt_size_t recv_len = rt_link_hw_recv_len(rt_link_scb->rx_buffer); + while (recv_len > 0) + { + switch (analysis_status) + { + case FIND_FRAME_HEAD: + { + /* if we can't find frame head, throw that data */ + if ((*rt_link_scb->rx_buffer->read_point & RT_LINK_FRAME_HEAD_MASK) == RT_LINK_FRAME_HEAD) + { + analysis_status = PARSE_FRAME_HEAD; + break; + } + rt_link_hw_buffer_point_shift(&rt_link_scb->rx_buffer->read_point, 1); + break; + } + + case PARSE_FRAME_HEAD: + { + if (recv_len < buff_len) + { + LOG_D("The length is not enough,recv=%d buff=%d", recv_len, buff_len); + return ; + } + /* Data is an offset address */ + data = rt_link_scb->rx_buffer->read_point; + rt_link_frame_init(&receive_frame, RT_NULL); + rt_link_hw_copy((rt_uint8_t *)&receive_frame.head, data, sizeof(struct rt_link_frame_head)); + rt_link_hw_buffer_point_shift(&data, sizeof(struct rt_link_frame_head)); + receive_frame.data_len = receive_frame.head.length; + LOG_D("check seq(%d) data len(%d).", receive_frame.head.sequence, receive_frame.data_len); + + if (receive_frame.head.extend) + { + buff_len += RT_LINK_MAX_EXTEND_LENGTH; + analysis_status = PARSE_FRAME_EXTEND; + } + else + { + analysis_status = PARSE_FRAME_SEQ; + } + } + + case PARSE_FRAME_EXTEND: + { + if (receive_frame.head.extend) + { + if (recv_len < buff_len) + { + LOG_D("PARSE_FRAME_EXTEND: actual: %d, need: %d.", recv_len, buff_len); + + /* should set timer, control receive frame timeout, one shot */ + timeout = 50; + rt_timer_control(&rt_link_scb->recvtimer, RT_TIMER_CTRL_SET_TIME, &timeout); + rt_timer_start(&rt_link_scb->recvtimer); + return; + } + rt_link_hw_copy((rt_uint8_t *)&receive_frame.extend, data, sizeof(struct rt_link_extend)); + rt_link_hw_buffer_point_shift(&data, sizeof(struct rt_link_extend)); + switch (receive_frame.extend.attribute) + { + case RT_LINK_RESEND_FRAME: + case RT_LINK_LONG_DATA_FRAME: + case RT_LINK_HANDSHAKE_FRAME: + receive_frame.attribute = receive_frame.extend.attribute; + break; + default: + receive_frame.attribute = RT_LINK_RESERVE_FRAME; + break; + } + } + else + { + if (receive_frame.head.crc) + { + receive_frame.attribute = RT_LINK_SHORT_DATA_FRAME; + } + else + { + receive_frame.attribute = RT_LINK_CONFIRM_FRAME; + } + } + if (receive_frame.attribute == RT_LINK_RESERVE_FRAME) + { + LOG_D("quick filter error frame."); + rt_link_frame_stop_receive(&receive_frame); + buff_len = RT_LINK_HEAD_LENGTH; + analysis_status = FIND_FRAME_HEAD; + break; + } + analysis_status = PARSE_FRAME_SEQ; + } + + case PARSE_FRAME_SEQ: + { + if ((receive_frame.attribute == RT_LINK_CONFIRM_FRAME) || (receive_frame.attribute == RT_LINK_RESEND_FRAME)) + { + offset = rt_link_check_seq(receive_frame.head.sequence, rt_link_scb->tx_seq); + if (rt_slist_first(&rt_link_scb->tx_data_slist) != RT_NULL) + { + send_frame = rt_container_of(rt_link_scb->tx_data_slist.next, struct rt_link_frame, slist); + if (offset > send_frame->total) + { + /* exceptional frame, ignore it */ + LOG_D("seq (%d) failed, tx_seq (%d).offset=(%d) total= (%d)", receive_frame.head.sequence, rt_link_scb->tx_seq, offset, send_frame->total); + rt_link_frame_stop_receive(&receive_frame); + buff_len = RT_LINK_HEAD_LENGTH; + analysis_status = FIND_FRAME_HEAD; + break; + } + } + } + else + { + offset = rt_link_check_seq(receive_frame.head.sequence, rt_link_scb->rx_record.rx_seq) - 1; + if ((offset > RT_LINK_FRAMES_MAX) && (receive_frame.attribute != RT_LINK_HANDSHAKE_FRAME)) + { + /* exceptional frame, ignore it */ + LOG_D("seq (%d) failed, rx_seq (%d) offset=(%d) attr= (%d) status (%d)", receive_frame.head.sequence, rt_link_scb->rx_record.rx_seq, offset, receive_frame.attribute, rt_link_scb->link_status); + rt_link_frame_stop_receive(&receive_frame); + buff_len = RT_LINK_HEAD_LENGTH; + analysis_status = FIND_FRAME_HEAD; + break; + } + } + + buff_len += receive_frame.data_len; + if (receive_frame.head.crc) + { + buff_len += RT_LINK_CRC_LENGTH; + analysis_status = CHECK_FRAME_CRC; + } + else + { + analysis_status = HEADLE_FRAME_DATA; + } + } + + case CHECK_FRAME_CRC: + { + if (receive_frame.head.crc) + { + if (recv_len < buff_len) + { + /* should set timer, control receive frame timeout, one shot */ + timeout = 50; + rt_timer_control(&rt_link_scb->recvtimer, RT_TIMER_CTRL_SET_TIME, &timeout); + rt_timer_start(&rt_link_scb->recvtimer); + return; + } + + real_data = data; + rt_timer_stop(&rt_link_scb->recvtimer); + rt_link_hw_buffer_point_shift(&data, receive_frame.data_len); + rt_link_hw_copy((rt_uint8_t *)&receive_frame.crc, data, RT_LINK_CRC_LENGTH); + temporary_crc = rt_link_scb->calculate_crc(RT_TRUE, rt_link_scb->rx_buffer->read_point, buff_len - RT_LINK_CRC_LENGTH); + if (receive_frame.crc != temporary_crc) + { + /* check failed. ready resent */ + LOG_D("CRC: calc:(0x%08x) ,recv:(0x%08x).", temporary_crc, receive_frame.crc); + /* quick resent, when sequence is right, we can ask for reset this frame */ + rt_link_command_frame_send(receive_frame.head.sequence, RT_LINK_RESEND_FRAME, RT_NULL); + + /* throw the error frame */ + buff_len = RT_LINK_HEAD_LENGTH; + rt_link_frame_stop_receive(&receive_frame); + + /* clear the frame information */ + analysis_status = FIND_FRAME_HEAD; + break; + } + /* fill real data point */ + receive_frame.real_data = real_data; + } + analysis_status = HEADLE_FRAME_DATA; + } + + case HEADLE_FRAME_DATA: + { + rt_link_hw_buffer_point_shift(&rt_link_scb->rx_buffer->read_point, buff_len); + rt_link_parse_frame(&receive_frame); + data = RT_NULL; + buff_len = RT_LINK_HEAD_LENGTH; + analysis_status = FIND_FRAME_HEAD; + break; + } + + default: + LOG_E("analysis_status is error."); + break; + } + recv_len = rt_link_hw_recv_len(rt_link_scb->rx_buffer); + } +} + +static void rt_link_send_ready(void) +{ + if (rt_link_scb->link_status != RT_LINK_CONNECT_DONE) + { + rt_link_scb->link_status = RT_LINK_NO_RESPONSE; + rt_link_command_frame_send(rt_link_scb->tx_seq, RT_LINK_HANDSHAKE_FRAME, rt_link_scb->rx_record.rx_seq); + } + else + { + if (RT_EOK != rt_link_frame_send(&rt_link_scb->tx_data_slist)) + { + rt_event_send(&rt_link_scb->event, RT_LINK_SEND_FAILED_EVENT); + } + } +} + +static void rt_link_frame_recv_timeout(void) +{ + /* The receiving frame timeout and a new receive begins */ + rt_link_hw_buffer_point_shift(&rt_link_scb->rx_buffer->read_point, rt_link_hw_recv_len(rt_link_scb->rx_buffer)); +} + +static void rt_link_send_timeout(void) +{ + static rt_uint8_t count = 0; + if (count++ > 5) + { + LOG_W("Send timeout, please check the link status!"); + count = 0; + rt_event_send(&rt_link_scb->event, RT_LINK_SEND_FAILED_EVENT); + } + else + { + rt_timer_start(&rt_link_scb->sendtimer); + rt_link_command_frame_send(rt_link_scb->tx_seq, RT_LINK_HANDSHAKE_FRAME, rt_link_scb->rx_record.rx_seq); + } +} + +static int rt_link_long_recv_timeout(void) +{ + static rt_uint8_t count = 0; + if (count++ > 5) + { + LOG_W("long package receive timeout"); + count = 0; + _stop_recv_long(); + } + else + { + for (rt_uint8_t total = rt_link_scb->rx_record.total; total > 0; total--) + { + if (((rt_link_scb->rx_record.long_count >> (total - 1)) & 0x01) == 0x00) + { + /* resend command */ + rt_link_command_frame_send((rt_link_scb->rx_record.rx_seq + total), RT_LINK_RESEND_FRAME, RT_NULL); + } + } + } + return RT_EOK; +} + +void rt_link_thread(void *parameter) +{ + rt_uint32_t recved = 0; + while (1) + { + rt_event_recv(&rt_link_scb->event, RT_LINK_READ_CHECK_EVENT | + RT_LINK_SEND_READY_EVENT | + RT_LINK_SEND_TIMEOUT_EVENT | + RT_LINK_RECV_TIMEOUT_FRAME_EVENT | + RT_LINK_RECV_TIMEOUT_LONG_EVENT, + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_FOREVER, + &recved); + + if (recved & RT_LINK_READ_CHECK_EVENT) + { + rt_link_frame_check(); + } + + if (recved & RT_LINK_SEND_READY_EVENT) + { + rt_link_send_ready(); + } + + if (recved & RT_LINK_SEND_TIMEOUT_EVENT) + { + rt_link_send_timeout(); + } + + if (recved & RT_LINK_RECV_TIMEOUT_FRAME_EVENT) + { + rt_link_frame_recv_timeout(); + } + + if (recved & RT_LINK_RECV_TIMEOUT_LONG_EVENT) + { + rt_link_long_recv_timeout(); + } + } +} + +static void rt_link_sendtimer_callback(void *parameter) +{ + rt_event_send(&rt_link_scb->event, RT_LINK_SEND_TIMEOUT_EVENT); +} + +static void rt_link_recvtimer_callback(void *parameter) +{ + rt_event_send(&rt_link_scb->event, RT_LINK_RECV_TIMEOUT_FRAME_EVENT); +} + +static void rt_link_receive_long_frame_callback(void *parameter) +{ + rt_event_send(&rt_link_scb->event, RT_LINK_RECV_TIMEOUT_LONG_EVENT); +} + +/** + * rtlink send data interface + * @param service Registered service channel, choose enum rt_link_service_t + * @param data send data + * @param size send data size + * @return The actual size of the data sent + * */ +rt_size_t rt_link_send(rt_link_service_t service, void *data, rt_size_t size) +{ + if ((size == 0) || (data == RT_NULL) || (service >= RT_LINK_SERVICE_MAX)) + { + return 0; + } + rt_mutex_take(&rt_link_scb->tx_lock, RT_WAITING_FOREVER); + + rt_uint32_t recved = 0; + rt_err_t result = RT_EOK; + rt_uint32_t timeout = 0; + + rt_uint8_t total = 0; /* The total number of frames to send */ + rt_uint8_t index = 0; /* The index of the split packet */ + rt_size_t offset = 0; /* The offset of the send data */ + + struct rt_link_frame *send_frame = RT_NULL; + rt_link_frame_attribute_t attribute; + if (size % RT_LINK_MAX_DATA_LENGTH == 0) + { + total = size / RT_LINK_MAX_DATA_LENGTH; + } + else + { + total = size / RT_LINK_MAX_DATA_LENGTH + 1; + } + + if (total > RT_LINK_FRAMES_MAX) + { + result = -RT_ENOMEM; + goto __exit; + } + else if (total > 1) + { + attribute = RT_LINK_LONG_DATA_FRAME; + } + else + { + attribute = RT_LINK_SHORT_DATA_FRAME; + } + + do + { + send_frame = rt_malloc(sizeof(struct rt_link_frame)); + rt_link_frame_init(send_frame, FRAME_CRC | FRAME_ACK); + send_frame->head.sequence = rt_link_scb->tx_seq + 1 + index; + send_frame->head.channel = service; + send_frame->real_data = (rt_uint8_t *)data + offset; + send_frame->index = index; + send_frame->total = total; + + if (attribute == RT_LINK_LONG_DATA_FRAME) + { + send_frame->attribute = RT_LINK_LONG_DATA_FRAME; + if (offset + RT_LINK_MAX_DATA_LENGTH > size) + { + send_frame->data_len = size - offset; + } + else + { + send_frame->data_len = RT_LINK_MAX_DATA_LENGTH; + offset += RT_LINK_MAX_DATA_LENGTH; + } + + rt_link_frame_extend_config(send_frame, RT_LINK_LONG_DATA_FRAME, size); + } + else + { + send_frame->attribute = RT_LINK_SHORT_DATA_FRAME; + send_frame->data_len = size; + } + + /* append the frame on the tail of list */ + LOG_D("new data append on the send slist, seq(%d), len(%d).", send_frame->head.sequence, send_frame->data_len); + rt_slist_append(&rt_link_scb->tx_data_slist, &send_frame->slist); + + index++; + }while(total > index); + + timeout = RT_LINK_SENT_FRAME_TIMEOUT * total; + rt_timer_control(&rt_link_scb->sendtimer, RT_TIMER_CTRL_SET_TIME, &timeout); + rt_timer_start(&rt_link_scb->sendtimer); + /* Notify the core thread to send packet */ + rt_event_send(&rt_link_scb->event, RT_LINK_SEND_READY_EVENT); + + /* Wait for the packet to be sent successfully */ + rt_event_recv(&rt_link_scb->event, RT_LINK_SEND_OK_EVENT | RT_LINK_SEND_FAILED_EVENT, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved); + + if (recved & RT_LINK_SEND_OK_EVENT) + { + result = RT_EOK; + } + else if (recved & RT_LINK_SEND_FAILED_EVENT) + { + LOG_E("the data (%dB) send failed", size); + result = -RT_ERROR; + } + else + { + LOG_E("unexpected event."); + result = -RT_ERROR; + } +__exit: + rt_timer_stop(&rt_link_scb->sendtimer); + /* Empty the sending list */ + rt_link_datalist_empty(); + rt_mutex_release(&rt_link_scb->tx_lock); + if (result == RT_EOK) + { + return size; + } + return result; +} + +void rtlink_status(void) +{ + rt_kprintf("rtlink status:\n"); + if (rt_link_scb != RT_NULL) + { + rt_kprintf("\tlink status=%d\n", rt_link_scb->link_status); + + rt_kprintf("\trx seq=%d\n", rt_link_scb->rx_record.rx_seq); + rt_kprintf("\ttx seq=%d\n", rt_link_scb->tx_seq); + rt_kprintf("\trecv len=%d\n", rt_link_hw_recv_len(rt_link_scb->rx_buffer)); + + rt_tick_t state = 0; + rt_timer_control(&rt_link_scb->longframetimer, RT_TIMER_CTRL_GET_STATE, &state); + rt_kprintf("\tlong timer state=%d\n", state); + rt_timer_control(&rt_link_scb->sendtimer, RT_TIMER_CTRL_GET_STATE, &state); + rt_kprintf("\tsend timer state=%d\n", state); + + rt_kprintf("\tevent set=0x%08x\n", rt_link_scb->event.set); + if (rt_link_scb->tx_data_slist.next) + { + rt_slist_t *data = RT_NULL; + rt_slist_for_each(data, &rt_link_scb->tx_data_slist) + { + rt_kprintf("\tsend data list: serv %u\t", ((struct rt_link_frame_head *)data)->channel); + rt_kprintf(" seq %u\t", ((struct rt_link_frame_head *)data)->sequence); + rt_kprintf(" len %u\n", ((struct rt_link_frame_head *)data)->length); + } + } + else + { + rt_kprintf("\tsend data list: NULL\n"); + } + + rt_uint8_t serv = sizeof(rt_link_scb->channel) / sizeof(struct rt_link_service); + while (serv--) + { + rt_kprintf("\tservices [%d](0x%p)\n", serv, rt_link_scb->channel[serv]); + } + } + else + { + rt_kprintf("status NULL, please check the initialization status!\n"); + } +} +MSH_CMD_EXPORT(rtlink_status, Display RTLINK status); + +/** + * rtlink deinit the interface + * */ +rt_err_t rt_link_deinit(void) +{ + rt_enter_critical(); + rt_link_hw_deinit(); + if (rt_link_scb) + { + rt_timer_detach(&rt_link_scb->longframetimer); + rt_timer_detach(&rt_link_scb->sendtimer); + rt_timer_detach(&rt_link_scb->recvtimer); + rt_mutex_detach(&rt_link_scb->tx_lock); + rt_event_detach(&rt_link_scb->event); + rt_free(rt_link_scb); + rt_link_scb = RT_NULL; + } + rt_thread_t thread = rt_thread_find(RT_LINK_THREAD_NAME); + if (thread) + { + rt_thread_delete(thread); + } + rt_exit_critical(); + return RT_EOK; +} +MSH_CMD_EXPORT(rt_link_deinit, rt link deinit); + +/** + * rtlink initializes the interface, usually automatically. + * @return int Function Execution Result + * */ +int rt_link_init(void) +{ + rt_err_t result = RT_EOK; + rt_thread_t thread = RT_NULL; + + if (rt_link_scb != RT_NULL) + { + goto __exit; + } + + rt_link_scb = rt_malloc(sizeof(struct rt_link_session)); + if (rt_link_scb == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + + rt_memset(rt_link_scb, 0, sizeof(struct rt_link_session)); + rt_event_init(&rt_link_scb->event, "lny_event", RT_IPC_FLAG_FIFO); + rt_event_control(&rt_link_scb->event, RT_IPC_CMD_RESET, RT_NULL); + + rt_mutex_init(&rt_link_scb->tx_lock, "tx_lock", RT_IPC_FLAG_FIFO); + rt_timer_init(&rt_link_scb->sendtimer, "tx_time", rt_link_sendtimer_callback, + RT_NULL, 0, RT_TIMER_FLAG_SOFT_TIMER | RT_TIMER_FLAG_PERIODIC); + rt_timer_init(&rt_link_scb->recvtimer, "rx_time", rt_link_recvtimer_callback, + RT_NULL, 0, RT_TIMER_FLAG_SOFT_TIMER | RT_TIMER_FLAG_ONE_SHOT); + rt_timer_init(&rt_link_scb->longframetimer, "rxl_time", rt_link_receive_long_frame_callback, + RT_NULL, 0, RT_TIMER_FLAG_SOFT_TIMER | RT_TIMER_FLAG_PERIODIC); + + rt_link_scb->link_status = RT_LINK_ESTABLISHING; + + rt_link_scb->rx_record.rx_seq = 255; + + rt_slist_init(&rt_link_scb->tx_data_slist); + rt_link_scb->tx_seq = RT_LINK_INIT_FRAME_SEQENCE; + + /* create rtlink core work thread */ + thread = rt_thread_create(RT_LINK_THREAD_NAME, + rt_link_thread, + RT_NULL, + RT_LINK_THREAD_STACK_SIZE, + RT_LINK_THREAD_PRIORITY, + RT_LINK_THREAD_TICK); + if (thread == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + rt_thread_startup(thread); + result = rt_link_hw_init(); + +__exit: + if (result != RT_EOK) + { + LOG_E("rtlink init failed."); + rt_link_deinit(); + } + else + { + LOG_I("rtlink init success."); + } + return result; +} +#ifdef RT_LINK_AUTO_INIT + INIT_ENV_EXPORT(rt_link_init); +#endif +MSH_CMD_EXPORT(rt_link_init, rt link init); + +/** + * rtlink service attach + * @param service Registered service channel, choose enum rt_link_service_t + * @param function receive callback function + * @return Function Execution Result + * */ +rt_err_t rt_link_service_attach(rt_link_service_t service, rt_err_t (*function)(void *data, rt_size_t size)) +{ + if (service >= RT_LINK_SERVICE_MAX) + { + LOG_W("Invalid parameter."); + return -RT_ERROR; + } + rt_link_scb->channel[service].upload_callback = function; + LOG_I("rt link attach service[%02d].", service); + return RT_EOK; +} + +/** + * rtlink service detach + * @param service Registered service channel, choose enum rt_link_service_t + * @return rt_err_t Function Execution Result + * */ +rt_err_t rt_link_service_detach(rt_link_service_t service) +{ + if (service >= RT_LINK_SERVICE_MAX) + { + LOG_W("Invalid parameter."); + return -RT_ERROR; + } + rt_link_scb->channel[service].upload_callback = RT_NULL; + LOG_I("rt link detach service[%02d].", service); + return RT_EOK; +} diff --git a/components/utilities/rt-link/src/rtlink_hw.c b/components/utilities/rt-link/src/rtlink_hw.c new file mode 100644 index 0000000000000000000000000000000000000000..9c4567ab63296f9815e59599ee82f9409d0de56e --- /dev/null +++ b/components/utilities/rt-link/src/rtlink_hw.c @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-02 xiangxistu the first version + * 2021-05-08 Sherman Optimize the operation function on the rt_link_receive_buffer + */ + +#include + +#include +#include +#include +#include + +#define DBG_TAG "rtlink_hw" +#ifdef USING_RT_LINK_HW_DEBUG + #define DBG_LVL DBG_LOG +#else + #define DBG_LVL DBG_INFO +#endif +#define DBG_COLOR +#include + +static struct rt_link_receive_buffer *rx_buffer = RT_NULL; + +struct rt_link_receive_buffer *rt_link_hw_buffer_init(void *parameter) +{ + rx_buffer = rt_malloc(sizeof(struct rt_link_receive_buffer)); + if (rx_buffer != RT_NULL) + { + rt_memset(rx_buffer, 0, sizeof(struct rt_link_receive_buffer)); + rx_buffer->read_point = rx_buffer->data; + rx_buffer->write_point = rx_buffer->data; + rx_buffer->end_point = rx_buffer->data + RT_LINK_RECEIVE_BUFFER_LENGTH; /* Point to memory that has no access rights */ + } + else + { + LOG_E("receive buffer alloc failed, init failed."); + } + + return rx_buffer; +} + +static rt_size_t rt_link_hw_buffer_write(void *data, rt_size_t count) +{ + int surplus = 0; + if (rx_buffer == RT_NULL) + { + return 0; + } + /* (data)----(r)----(w)----(end) */ + if (rx_buffer->write_point >= rx_buffer->read_point) + { + rt_size_t w2end = rx_buffer->end_point - rx_buffer->write_point; + surplus = RT_LINK_RECEIVE_BUFFER_LENGTH - (rx_buffer->write_point - rx_buffer->read_point); + count = count > surplus ? surplus : count; + if (count >= w2end) + { + rt_memcpy(rx_buffer->write_point, data, w2end); + rx_buffer->write_point = rx_buffer->data; + + rt_memcpy(rx_buffer->write_point, (rt_uint8_t *)data + w2end, (count - w2end)); + rx_buffer->write_point += (count - w2end); + } + else + { + rt_memcpy(rx_buffer->write_point, data, count); + rx_buffer->write_point += count; + } + } + else /* (data)----(w)----(r)----(end) */ + { + surplus = rx_buffer->read_point - rx_buffer->write_point; + count = count > surplus ? surplus : count; + rt_memcpy(rx_buffer->write_point, data, count); + rx_buffer->write_point += count; + } + return count; +} + +/* increases buffer pointer by one and circle around if necessary */ +void rt_link_hw_buffer_point_shift(rt_uint8_t **pointer_address, rt_size_t length) +{ + rt_uint8_t *pointer = RT_NULL; + + pointer = *pointer_address + length; + if (pointer >= rx_buffer->end_point) + { + rt_size_t offset = 0; + offset = pointer - rx_buffer->end_point; + *pointer_address = rx_buffer->data + offset; + } + else + { + *pointer_address = *pointer_address + length; + } +} + +/* copy data from receive buffer */ +void rt_link_hw_copy(rt_uint8_t *dst, rt_uint8_t *src, rt_size_t count) +{ + rt_uint8_t *pointer = RT_NULL; + + pointer = src + count; + if (pointer >= rx_buffer->end_point) + { + rt_size_t offset = 0; + offset = rx_buffer->end_point - src; + rt_memcpy(dst, src, offset); + rt_memcpy(dst + offset, rx_buffer->data, pointer - rx_buffer->end_point); + } + else + { + rt_memcpy(dst, src, count); + } +} + +/* Tells, how many chars are saved into the buffer */ +rt_size_t rt_link_hw_recv_len(struct rt_link_receive_buffer *buffer) +{ + if (buffer->write_point >= buffer->read_point) + { + return (buffer->write_point - buffer->read_point); + } + else + { + return (RT_LINK_RECEIVE_BUFFER_LENGTH - (buffer->read_point - buffer->write_point)); + } +} + +rt_err_t rt_link_reset_crc32(void) +{ +#ifdef RT_LINK_USING_HW_CRC + return rt_link_hw_crc32_reset(); +#else + return rt_link_sf_crc32_reset(); +#endif +} + +rt_uint32_t rt_link_crc32(rt_uint8_t *data, rt_size_t u32_size) +{ +#ifdef RT_LINK_USING_HW_CRC + return rt_link_hw_crc32(data, u32_size); +#else + return rt_link_sf_crc32(data, u32_size); +#endif +} + +rt_uint32_t rt_link_get_crc(rt_uint8_t using_buffer_ring, rt_uint8_t *data, rt_size_t size) +{ + rt_uint32_t crc32 = 0x0; + rt_size_t surplus = 0; + + if (data == RT_NULL) + { + LOG_D("warning, the parameter error: %d, data: 0x%08d.", size, data); + return 0; + } + + rt_link_reset_crc32(); + if (using_buffer_ring == 1) + { + /* modify the missing character */ + surplus = rx_buffer->end_point - data; + if (surplus >= size) + { + crc32 = rt_link_crc32(data, size); + } + else + { + rt_link_crc32(data, surplus); + crc32 = rt_link_crc32(rx_buffer->data, size - surplus); + } + } + else + { + crc32 = rt_link_crc32(data, size); + } + return crc32; +} + +rt_err_t rt_link_hw_send(void *data, rt_size_t length) +{ + rt_size_t send_len = 0; + send_len = rt_link_port_send(data, length); + LOG_D("hw_send len= %d", send_len); + return send_len; +} + +/* provide this function to hardware spi/uart/usb to store data */ +rt_size_t rt_link_hw_write_cb(void *data, rt_size_t length) +{ + /* write real data into rtlink receive buffer */ + rt_size_t len = rt_link_hw_buffer_write(data, length); + struct rt_link_session *scb = rt_link_get_scb(); + if (scb) + { + rt_event_send(&scb->event, RT_LINK_READ_CHECK_EVENT); + } + return len; +} + +rt_err_t rt_link_hw_init(void) +{ + struct rt_link_session *scb = rt_link_get_scb(); + if ((rx_buffer != RT_NULL) || (scb == RT_NULL)) + { + return -RT_ERROR; + } + + /* alloc receive buffer to store data */ + if (rt_link_hw_buffer_init(RT_NULL) == RT_NULL) + { + return -RT_ENOMEM; + } + scb->rx_buffer = rx_buffer; + scb->calculate_crc = rt_link_get_crc; + + rt_link_port_init(); + +#ifdef LINK_LAYER_USING_HW_CRC + /* crc hardware device for mcu and node */ + rt_link_hw_crc32_init(); +#endif + + LOG_I("link layer hardware environment init successful."); + return RT_EOK; +} + +rt_err_t rt_link_hw_deinit(void) +{ + if (rx_buffer) + { + rt_free(rx_buffer); + rx_buffer = RT_NULL; + } + struct rt_link_session *scb = rt_link_get_scb(); + if (scb) + { + scb->rx_buffer = rx_buffer; + scb->calculate_crc = RT_NULL; + } + rt_link_port_deinit(); + +#ifdef LINK_LAYER_USING_HW_CRC + /* crc hardware device for mcu and node */ + rt_link_hw_crc32_deinit(); +#endif + + LOG_I("rtlink hardware deinit successful."); + return RT_EOK; +} diff --git a/components/utilities/rt-link/src/rtlink_utils.c b/components/utilities/rt-link/src/rtlink_utils.c new file mode 100644 index 0000000000000000000000000000000000000000..c5cfbb9422bc42cab12bf366c16dfce7a5ddc84c --- /dev/null +++ b/components/utilities/rt-link/src/rtlink_utils.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-15 Sherman the first version + */ + +#include + +/* Calculate the number of '1' */ +int rt_link_utils_num1(rt_uint32_t n) +{ + int ret = 0; + while (n) + { + n &= n - 1; + ret++; + } + return ret; +} + +#ifdef RT_LINK_USING_SF_CRC + +static rt_uint32_t crc = 0xffffffff; +const rt_uint32_t crc_table[256] = +{ + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, + 0x706AF48F, 0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2, 0xF3B97148, + 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, 0x136C9856, 0x646BA8C0, + 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, + 0x4C69105E, 0xD56041E4, 0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, + 0xABD13D59, 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, + 0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, + 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, 0x7807C9A2, 0x0F00F934, 0x9609A88E, + 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, + 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, + 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, + 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, 0x44042D73, 0x33031DE5, + 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525, + 0x206F85B3, 0xB966D409, 0xCE61E49F, 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, + 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84, + 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, 0xF00F9344, + 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, + 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, + 0x3FB506DD, 0x48B2364B, 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, + 0xA867DF55, 0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, + 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, 0x9B64C2B0, 0xEC63F226, + 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, 0x95BF4A82, + 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, + 0x18B74777, 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, + 0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, 0xA7672661, + 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, 0xBDBDF21C, 0xCABAC28A, 0x53B39330, + 0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, + 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D +}; + +rt_err_t rt_link_sf_crc32_reset(void) +{ + crc = 0xffffffff; + return RT_EOK; +} + +rt_uint32_t rt_link_sf_crc32(rt_uint8_t *data, rt_size_t len) +{ + rt_uint32_t x, y; + x = 0; + y = 0; + rt_size_t i; + + for (i = 0; i < len; i++) + { + y = (crc ^ data[i]) & 0xff; + x = crc_table[y]; + crc = (crc >> 8) ^ x; + } + return (crc ^ 0xffffffff); +} +#endif /* RT_LINK_USING_SF_CRC */ diff --git a/components/utilities/ulog/ulog.c b/components/utilities/ulog/ulog.c index 76100892982dde363d1e80b7439dc57a1c06d530..e2685afbbd787156aa1fc817f5701e51de9c0724 100644 --- a/components/utilities/ulog/ulog.c +++ b/components/utilities/ulog/ulog.c @@ -7,7 +7,7 @@ * Date Author Notes * 2018-08-25 armink the first version */ - +#include #include #include "ulog.h" #include "rthw.h" diff --git a/components/utilities/ulog/ulog_def.h b/components/utilities/ulog/ulog_def.h index de5e82fcc55a274dec932c466a95463d631f3cbd..96e2ec36c60c0fe991b54b377c22c61fe280af37 100644 --- a/components/utilities/ulog/ulog_def.h +++ b/components/utilities/ulog/ulog_def.h @@ -135,7 +135,9 @@ extern "C" { #undef ELOG_LVL_INFO #undef ELOG_LVL_DEBUG #undef ELOG_LVL_VERBOSE +#if !defined(RT_USING_MLIB) #define assert ASSERT +#endif #define log_e LOG_E #define log_w LOG_W #define log_i LOG_I diff --git a/components/vbus/prio_queue.c b/components/vbus/prio_queue.c index bca3cdcd9a698095226b0fa8e80326f128c7ecf1..0d15da5ab86d0933873117aa2c2fc2e52d536b9c 100644 --- a/components/vbus/prio_queue.c +++ b/components/vbus/prio_queue.c @@ -205,7 +205,7 @@ rt_err_t rt_prio_queue_pop(struct rt_prio_queue *que, thread = rt_thread_self(); thread->error = RT_EOK; - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); rt_list_insert_before(&(que->suspended_pop_list), &(thread->tlist)); diff --git a/components/vbus/vbus.c b/components/vbus/vbus.c index 8add15d9dbacede318dbbb2374490b6a1c7e23a6..d471a9d21b274cefc66e14228b57332921337551 100644 --- a/components/vbus/vbus.c +++ b/components/vbus/vbus.c @@ -230,7 +230,7 @@ static void _bus_out_entry(void *param) /* kick the guest, hoping this could force it do the work */ rt_vbus_tick(0, RT_VBUS_GUEST_VIRQ); - rt_thread_suspend(rt_thread_self()); + rt_thread_suspend_with_flag(rt_thread_self(), RT_UNINTERRUPTIBLE); rt_schedule(); RT_VBUS_OUT_RING->blocked = 0; @@ -334,7 +334,7 @@ rt_err_t rt_vbus_post(rt_uint8_t id, /* We only touch the _chn_suspended_threads in thread, so lock the * scheduler is enough. */ rt_enter_critical(); - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); rt_list_insert_after(&_chn_suspended_threads[id], &thread->tlist); if (timeout > 0) diff --git a/components/vbus/watermark_queue.h b/components/vbus/watermark_queue.h index 0ecc52d8ff7710650ccef31108b1c6cca79cc914..8828ceb1ac44935d5c90ca3ca91ca93952c9c9b6 100644 --- a/components/vbus/watermark_queue.h +++ b/components/vbus/watermark_queue.h @@ -63,7 +63,7 @@ rt_inline rt_err_t rt_wm_que_inc(struct rt_watermark_queue *wg, thread = rt_thread_self(); thread->error = RT_EOK; - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); rt_list_insert_after(&wg->suspended_threads, &thread->tlist); if (timeout > 0) { diff --git a/examples/kernel/thread_resume.c b/examples/kernel/thread_resume.c index cea814616f92047339f38ddb2631e0fb516df045..26bebe91603f4288ad73872947f9686b83ce6821 100644 --- a/examples/kernel/thread_resume.c +++ b/examples/kernel/thread_resume.c @@ -18,7 +18,7 @@ static void thread1_entry(void* parameter) /* 挂起自身 */ rt_kprintf("suspend thread self\n"); - rt_thread_suspend(tid1); + rt_thread_suspend_witch_flag(tid1, RT_UNINTERRUPTIBLE); /* 主动执行线程调度 */ rt_schedule(); diff --git a/examples/kernel/thread_suspend.c b/examples/kernel/thread_suspend.c index 947cc3cbf61a6f605bc1043f231ccec6efc0910c..a6cf11b08910e9c13eb3505c3bc413dc06675ba5 100644 --- a/examples/kernel/thread_suspend.c +++ b/examples/kernel/thread_suspend.c @@ -28,7 +28,7 @@ static void thread2_entry(void* parameter) rt_thread_delay(10); /* 挂起线程1 */ - rt_thread_suspend(tid1); + rt_thread_suspend_witch_flag(tid1, RT_UNINTERRUPTIBLE); /* 延时10个OS Tick */ rt_thread_delay(10); diff --git a/include/libc/libc_dirent.h b/include/libc/libc_dirent.h index c3a19878ec183d33114d1df43f5e60bd54d18002..4da583fef3669194cf9aa5b60d07b26cbc3a7dd3 100644 --- a/include/libc/libc_dirent.h +++ b/include/libc/libc_dirent.h @@ -8,7 +8,8 @@ #define LIBC_DIRENT_H__ #define DT_UNKNOWN 0x00 -#define DT_REG 0x01 -#define DT_DIR 0x02 +#define DT_FIFO 0x01 +#define DT_DIR 0x04 +#define DT_REG 0x08 #endif diff --git a/include/libc/libc_errno.h b/include/libc/libc_errno.h index 9143c841f24b059d21f1320d1439a4bf2fb6839f..c5471c51b99428173f2db7b8a5d9771532e2c93e 100644 --- a/include/libc/libc_errno.h +++ b/include/libc/libc_errno.h @@ -13,9 +13,10 @@ #include -#if defined(RT_USING_NEWLIB) || defined(_WIN32) || (defined( __GNUC__ ) && !defined(__ARMCC_VERSION)) +#if defined(RT_USING_NEWLIB) || defined(RT_USING_MUSL) || defined(_WIN32) || defined(__ARMCC_GNUC__) /* use errno.h file in toolchains */ #include +#define ENOIOCTLCMD (ERROR_BASE_NO + 515) /* No ioctl command */ #endif #if defined(__CC_ARM) @@ -45,7 +46,7 @@ defined in armcc/errno.h #define ERROR_BASE_NO 0 #endif -#if !defined(RT_USING_NEWLIB) && !defined(_WIN32) && !(defined( __GNUC__ ) && !defined(__ARMCC_VERSION)) +#if !defined(RT_USING_NEWLIB) && !defined(RT_USING_MUSL) && !defined(_WIN32) && !defined(__ARMCC_GNUC__) #define EPERM (ERROR_BASE_NO + 1) #define ENOENT (ERROR_BASE_NO + 2) diff --git a/include/libc/libc_fdset.h b/include/libc/libc_fdset.h index 9700c7e83e6b0f5c36e47fa03c99a4c4360103a0..67014072c58e64b1db05e923ef372a7ac1689c32 100644 --- a/include/libc/libc_fdset.h +++ b/include/libc/libc_fdset.h @@ -15,7 +15,7 @@ #if defined(RT_USING_NEWLIB) || defined(_WIN32) || (defined( __GNUC__ ) && !defined(__ARMCC_VERSION)) #include -#if defined(HAVE_SYS_SELECT_H) +#if defined(HAVE_SYS_SELECT_H) && !defined(RT_USING_MINILIBC) #include #endif diff --git a/include/libc/libc_signal.h b/include/libc/libc_signal.h index 539685de3e32e43e523b03af3df0ba487e3a1095..643efaee9711265db700552ac559a034644ffc8d 100644 --- a/include/libc/libc_signal.h +++ b/include/libc/libc_signal.h @@ -55,16 +55,18 @@ struct siginfo typedef struct siginfo siginfo_t; #endif +#if !defined(RT_USING_MUSL) #define SI_USER 0x01 /* Signal sent by kill(). */ #define SI_QUEUE 0x02 /* Signal sent by sigqueue(). */ -#define SI_TIMER 0x03 /* Signal generated by expiration of a +#define SI_TIMER 0x03 /* Signal generated by expiration of a timer set by timer_settime(). */ -#define SI_ASYNCIO 0x04 /* Signal generated by completion of an +#define SI_ASYNCIO 0x04 /* Signal generated by completion of an asynchronous I/O request. */ -#define SI_MESGQ 0x05 /* Signal generated by arrival of a +#define SI_MESGQ 0x05 /* Signal generated by arrival of a message on an empty message queue. */ +#endif -#if !defined(RT_USING_NEWLIB) +#if !defined(RT_USING_NEWLIB) && !defined(RT_USING_MUSL) typedef void (*_sig_func_ptr)(int); typedef unsigned long sigset_t; #endif diff --git a/include/rtdef.h b/include/rtdef.h index e4ddbd37d394833ce9c6bb7c2e47bd31e9a49f57..39317676503214b92ee5d04280037c2bad61ba21 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -53,9 +53,9 @@ extern "C" { /**@{*/ /* RT-Thread version information */ -#define RT_VERSION 4L /**< major version number */ +#define RT_VERSION 5L /**< major version number */ #define RT_SUBVERSION 0L /**< minor version number */ -#define RT_REVISION 3L /**< revise version number */ +#define RT_REVISION 0L /**< revise version number */ /* RT-Thread version */ #define RTTHREAD_VERSION ((RT_VERSION * 10000) + \ @@ -114,6 +114,10 @@ typedef rt_base_t rt_off_t; /**< Type for offset */ #define __CLANG_ARM #endif +#if defined(__ARMCC_VERSION) && defined(__GNUC__) +#define __ARMCC_GNUC__ +#endif + /* Compiler Related Definitions */ #if defined(__CC_ARM) || defined(__CLANG_ARM) /* ARM Compiler */ #include @@ -143,7 +147,7 @@ typedef rt_base_t rt_off_t; /**< Type for offset */ #define RTT_API #elif defined (__GNUC__) /* GNU GCC Compiler */ - #ifdef RT_USING_NEWLIB + #if defined(RT_USING_NEWLIB) || defined(RT_USING_MUSL) #include #else /* the version of GNU GCC must be greater than 4.x */ @@ -221,11 +225,11 @@ typedef int (*init_fn_t)(void); #define INIT_EXPORT(fn, level) #endif -/* board init routines will be called in board_init() function */ +/* board initial routines will be called in board_init() function */ #define INIT_BOARD_EXPORT(fn) INIT_EXPORT(fn, "1") -/* pre/device/component/env/app init routines will be called in init_thread */ -/* components pre-initialization (pure software initilization) */ +/* pre/device/component/env/app initial routines will be called in init_thread */ +/* components pre-initialization (pure software initialization) */ #define INIT_PREV_EXPORT(fn) INIT_EXPORT(fn, "2") /* device initialization */ #define INIT_DEVICE_EXPORT(fn) INIT_EXPORT(fn, "3") @@ -233,7 +237,7 @@ typedef int (*init_fn_t)(void); #define INIT_COMPONENT_EXPORT(fn) INIT_EXPORT(fn, "4") /* environment initialization (mount disk, ...) */ #define INIT_ENV_EXPORT(fn) INIT_EXPORT(fn, "5") -/* appliation initialization (rtgui application etc ...) */ +/* application initialization (rtgui application etc ...) */ #define INIT_APP_EXPORT(fn) INIT_EXPORT(fn, "6") #if !defined(RT_USING_FINSH) @@ -287,6 +291,7 @@ typedef int (*init_fn_t)(void); #define RT_EIO 8 /**< IO error */ #define RT_EINTR 9 /**< Interrupted system call */ #define RT_EINVAL 10 /**< Invalid argument */ +#define RT_ETRAP 11 /**< trap event */ /**@}*/ @@ -358,6 +363,11 @@ struct rt_object #ifdef RT_USING_MODULE void *module_id; /**< id of application module */ #endif + +#ifdef RT_USING_LWP + int lwp_ref_count; /**< ref count for lwp */ +#endif + rt_list_t list; /**< list node of kernel object */ }; typedef struct rt_object *rt_object_t; /**< Type for kernel objects. */ @@ -393,7 +403,9 @@ enum rt_object_class_type RT_Object_Class_Device = 0x09, /**< The object is a device. */ RT_Object_Class_Timer = 0x0a, /**< The object is a timer. */ RT_Object_Class_Module = 0x0b, /**< The object is a module. */ - RT_Object_Class_Unknown = 0x0c, /**< The object is unknown. */ + RT_Object_Class_Channel = 0x0c, /**< The object is a channel */ + RT_Object_Class_Custom = 0x0d, /**< The object is a custom object */ + RT_Object_Class_Unknown = 0x0e, /**< The object is unknown. */ RT_Object_Class_Static = 0x80 /**< The object is a static object. */ }; @@ -441,6 +453,10 @@ struct rt_object_information #define RT_TIMER_CTRL_SET_ONESHOT 0x2 /**< change timer to one shot */ #define RT_TIMER_CTRL_SET_PERIODIC 0x3 /**< change timer to periodic */ #define RT_TIMER_CTRL_GET_STATE 0x4 /**< get timer run state active or deactive*/ +#define RT_TIMER_CTRL_GET_FUNC 0x5 /**< get timer timeout func */ +#define RT_TIMER_CTRL_SET_FUNC 0x6 /**< set timer timeout func */ +#define RT_TIMER_CTRL_GET_PARM 0x7 /**< get timer parameter */ +#define RT_TIMER_CTRL_SET_PARM 0x8 /**< get timer parameter */ #ifndef RT_TIMER_SKIP_LIST_LEVEL #define RT_TIMER_SKIP_LIST_LEVEL 1 @@ -480,6 +496,13 @@ typedef void (*rt_sighandler_t)(int signo); typedef siginfo_t rt_siginfo_t; #define RT_SIG_MAX 32 + +#else + +#ifdef RT_USING_LWP +#include +#endif + #endif /**@}*/ @@ -496,13 +519,30 @@ typedef siginfo_t rt_siginfo_t; /* * thread state definitions */ -#define RT_THREAD_INIT 0x00 /**< Initialized status */ -#define RT_THREAD_READY 0x01 /**< Ready status */ -#define RT_THREAD_SUSPEND 0x02 /**< Suspend status */ -#define RT_THREAD_RUNNING 0x03 /**< Running status */ -#define RT_THREAD_BLOCK RT_THREAD_SUSPEND /**< Blocked status */ -#define RT_THREAD_CLOSE 0x04 /**< Closed status */ -#define RT_THREAD_STAT_MASK 0x07 +#define RT_THREAD_INIT 0x00 /**< Initialized status */ +#define RT_THREAD_CLOSE 0x01 /**< Closed status */ +#define RT_THREAD_READY 0x02 /**< Ready status */ +#define RT_THREAD_RUNNING 0x03 /**< Running status */ + +/* + * for rt_thread_suspend_with_flag() + */ +enum +{ + RT_INTERRUPTIBLE = 0, + RT_KILLABLE, + RT_UNINTERRUPTIBLE, +}; + +#define RT_THREAD_SUSPEND_MASK 0x04 +#define RT_SIGNAL_COMMON_WAKEUP_MASK 0x02 +#define RT_SIGNAL_KILL_WAKEUP_MASK 0x01 + +#define RT_THREAD_SUSPEND_INTERRUPTIBLE (RT_THREAD_SUSPEND_MASK) /**< Suspend interruptable 0x4 */ +#define RT_THREAD_SUSPEND RT_THREAD_SUSPEND_INTERRUPTIBLE +#define RT_THREAD_SUSPEND_KILLABLE (RT_THREAD_SUSPEND_MASK | RT_SIGNAL_COMMON_WAKEUP_MASK) /**< Suspend with killable 0x6 */ +#define RT_THREAD_SUSPEND_UNINTERRUPTIBLE (RT_THREAD_SUSPEND_MASK | RT_SIGNAL_COMMON_WAKEUP_MASK | RT_SIGNAL_KILL_WAKEUP_MASK) /**< Suspend with uninterruptable 0x7 */ +#define RT_THREAD_STAT_MASK 0x07 #define RT_THREAD_STAT_YIELD 0x08 /**< indicate whether remaining_tick has been reloaded since last schedule */ #define RT_THREAD_STAT_YIELD_MASK RT_THREAD_STAT_YIELD @@ -556,6 +596,51 @@ struct rt_cpu #endif +struct rt_thread; + +#ifdef RT_USING_LWP +typedef rt_err_t (*rt_wakeup_func_t)(void *object, struct rt_thread *thread); + +struct rt_wakeup +{ + rt_wakeup_func_t func; + void *user_data; +}; + +#define _LWP_NSIG 64 + +#ifdef ARCH_CPU_64BIT +#define _LWP_NSIG_BPW 64 +#else +#define _LWP_NSIG_BPW 32 +#endif + +#define _LWP_NSIG_WORDS (_LWP_NSIG / _LWP_NSIG_BPW) + +typedef void (*lwp_sighandler_t)(int); + +typedef struct { + unsigned long sig[_LWP_NSIG_WORDS]; +} lwp_sigset_t; + +struct lwp_sigaction { + union { + void (*_sa_handler)(int); + void (*_sa_sigaction)(int, siginfo_t *, void *); + } __sa_handler; + lwp_sigset_t sa_mask; + int sa_flags; + void (*sa_restorer)(void); +}; + +struct rt_user_context +{ + void *sp; + void *pc; + void *flag; +}; +#endif + /** * Thread structure */ @@ -570,6 +655,10 @@ struct rt_thread void *module_id; /**< id of application module */ #endif +#ifdef RT_USING_LWP + int lwp_ref_count; /**< ref count for lwp */ +#endif + rt_list_t list; /**< the object list */ rt_list_t tlist; /**< the thread list */ @@ -620,9 +709,16 @@ struct rt_thread void *si_list; /**< the signal infor list */ #endif +#if defined(RT_USING_LWP) + void *msg_ret; /**< the return msg */ +#endif + rt_ubase_t init_tick; /**< thread's initialized tick */ rt_ubase_t remaining_tick; /**< remaining tick */ + rt_ubase_t tick_mark; + rt_ubase_t run_tick; + struct rt_timer thread_timer; /**< built-in thread timer */ void (*cleanup)(struct rt_thread *tid); /**< cleanup function when thread exit */ @@ -630,6 +726,36 @@ struct rt_thread /* light weight process if present */ #ifdef RT_USING_LWP void *lwp; + /* for user create */ + void *user_entry; + void *user_stack; + rt_uint32_t user_stack_size; + rt_uint32_t *kernel_sp; /**< kernel stack point */ + rt_list_t sibling; /**< next thread of same process */ + + lwp_sigset_t signal; + lwp_sigset_t signal_mask; + int signal_mask_bak; + rt_uint32_t signal_in_process; +#ifndef ARCH_MM_MMU + lwp_sighandler_t signal_handler[32]; +#endif + struct rt_user_context user_ctx; + + struct rt_wakeup wakeup; /**< wakeup data */ + int exit_request; +#ifdef RT_USING_USERSPACE +#ifdef RT_USING_GDBSERVER + int step_exec; + int debug_attach_req; + int debug_ret_user; + int debug_suspend; + struct rt_hw_exp_stack *regs; +#endif + void * thread_idr; /** lwp thread indicator */ + int *clear_child_tid; +#endif + int tid; #endif rt_ubase_t user_data; /**< private user data beyond this thread */ @@ -652,6 +778,7 @@ typedef struct rt_thread *rt_thread_t; #define RT_IPC_CMD_UNKNOWN 0x00 /**< unknown IPC command */ #define RT_IPC_CMD_RESET 0x01 /**< reset IPC object */ +#define RT_IPC_CMD_GET_STATE 0x02 /**< get the state of IPC object */ #define RT_WAITING_FOREVER -1 /**< Block forever until get resource. */ #define RT_WAITING_NO 0 /**< Non-block. */ @@ -909,6 +1036,8 @@ enum rt_device_class_type #define RT_DEVICE_CTRL_SUSPEND 0x02 /**< suspend device */ #define RT_DEVICE_CTRL_CONFIG 0x03 /**< configure device */ #define RT_DEVICE_CTRL_CLOSE 0x04 /**< close device */ +#define RT_DEVICE_CTRL_NOTIFY_SET 0x05 /**< set notify func */ +#define RT_DEVICE_CTRL_CONSOLE_OFLAG 0x06 /**< get console open flag */ #define RT_DEVICE_CTRL_SET_INT 0x10 /**< set interrupt */ #define RT_DEVICE_CTRL_CLR_INT 0x11 /**< clear interrupt */ @@ -995,6 +1124,29 @@ struct rt_device void *user_data; /**< device private data */ }; +/** + * Notify structure + */ +struct rt_device_notify +{ + void (*notify)(rt_device_t dev); + struct rt_device *dev; +}; + +#ifdef RT_USING_LWP +struct rt_channel +{ + struct rt_ipc_object parent; /**< inherit from object */ + struct rt_thread *reply; /**< the thread will be reply */ + rt_list_t wait_msg; /**< the wait queue of sender msg */ + rt_list_t wait_thread; /**< the wait queue of sender thread */ + rt_wqueue_t reader_queue; /**< channel poll queue */ + rt_uint8_t stat; /**< the status of this channel */ + rt_ubase_t ref; +}; +typedef struct rt_channel *rt_channel_t; +#endif + /** * block device geometry structure */ @@ -1043,11 +1195,10 @@ enum RTGRAPHIC_PIXEL_FORMAT_BGR565 = RTGRAPHIC_PIXEL_FORMAT_RGB565P, RTGRAPHIC_PIXEL_FORMAT_RGB666, RTGRAPHIC_PIXEL_FORMAT_RGB888, + RTGRAPHIC_PIXEL_FORMAT_BGR888, RTGRAPHIC_PIXEL_FORMAT_ARGB888, RTGRAPHIC_PIXEL_FORMAT_ABGR888, - RTGRAPHIC_PIXEL_FORMAT_ARGB565, - RTGRAPHIC_PIXEL_FORMAT_ALPHA, - RTGRAPHIC_PIXEL_FORMAT_COLOR, + RTGRAPHIC_PIXEL_FORMAT_RESERVED, }; /** diff --git a/include/rthw.h b/include/rthw.h index 89877faf9033f0c822063b67ea067df51a9cf72b..6492bec2e90a93abf94af9eb672dac85be603aaf 100644 --- a/include/rthw.h +++ b/include/rthw.h @@ -12,6 +12,7 @@ * 2017-10-17 Hichard add some micros * 2018-11-17 Jesven add rt_hw_spinlock_t * add smp support + * 2019-05-18 Bernard add empty definition for not enable cache case */ #ifndef __RT_HW_H__ @@ -49,6 +50,7 @@ enum RT_HW_CACHE_OPS /* * CPU interfaces */ +#ifdef RT_USING_CACHE void rt_hw_cpu_icache_enable(void); void rt_hw_cpu_icache_disable(void); rt_base_t rt_hw_cpu_icache_status(void); @@ -58,6 +60,20 @@ void rt_hw_cpu_dcache_enable(void); void rt_hw_cpu_dcache_disable(void); rt_base_t rt_hw_cpu_dcache_status(void); void rt_hw_cpu_dcache_ops(int ops, void* addr, int size); +#else + +/* define cache ops as empty */ +#define rt_hw_cpu_icache_enable(...) +#define rt_hw_cpu_icache_disable(...) +#define rt_hw_cpu_icache_ops(...) +#define rt_hw_cpu_dcache_enable(...) +#define rt_hw_cpu_dcache_disable(...) +#define rt_hw_cpu_dcache_ops(...) + +#define rt_hw_cpu_icache_status(...) 0 +#define rt_hw_cpu_dcache_status(...) 0 + +#endif void rt_hw_cpu_reset(void); void rt_hw_cpu_shutdown(void); @@ -116,7 +132,7 @@ void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t t #else void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); void rt_hw_context_switch_to(rt_ubase_t to); -void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread); #endif /*RT_USING_SMP*/ void rt_hw_console_output(const char *str); @@ -135,13 +151,7 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)); void rt_hw_us_delay(rt_uint32_t us); #ifdef RT_USING_SMP -typedef union { - unsigned long slock; - struct __arch_tickets { - unsigned short owner; - unsigned short next; - } tickets; -} rt_hw_spinlock_t; +#include /* for spinlock from arch */ struct rt_spinlock { @@ -181,12 +191,22 @@ void rt_hw_secondary_cpu_up(void); void rt_hw_secondary_cpu_idle_exec(void); #else -#define RT_DEFINE_SPINLOCK(x) +#define RT_DEFINE_SPINLOCK(x) #define RT_DECLARE_SPINLOCK(x) rt_ubase_t x #define rt_hw_spin_lock(lock) *(lock) = rt_hw_interrupt_disable() #define rt_hw_spin_unlock(lock) rt_hw_interrupt_enable(*(lock)) +typedef int rt_spinlock_t; + +#endif + +#ifdef RT_USING_CACHE +#include +#else +#define rt_hw_isb() +#define rt_hw_dmb() +#define rt_hw_dsb() #endif #ifdef __cplusplus diff --git a/include/rtthread.h b/include/rtthread.h index a76601a3bf8a391f6139a4f1e98fc8a2d780fcc5..4581cb1f22f57a026c20c160c70f16c7d0b0b877 100644 --- a/include/rtthread.h +++ b/include/rtthread.h @@ -55,6 +55,12 @@ rt_bool_t rt_object_is_systemobject(rt_object_t object); rt_uint8_t rt_object_get_type(rt_object_t object); rt_object_t rt_object_find(const char *name, rt_uint8_t type); +#ifdef RT_USING_HEAP +/* custom object */ +rt_object_t rt_custom_object_create(const char *name, void *data, rt_err_t (*data_destroy)(void *)); +rt_err_t rt_custom_object_destroy(rt_object_t obj); +#endif + #ifdef RT_USING_HOOK void rt_object_attach_sethook(void (*hook)(struct rt_object *object)); void rt_object_detach_sethook(void (*hook)(struct rt_object *object)); @@ -79,6 +85,9 @@ rt_tick_t rt_tick_get(void); void rt_tick_set(rt_tick_t tick); void rt_tick_increase(void); rt_tick_t rt_tick_from_millisecond(rt_int32_t ms); +#ifdef RT_USING_HOOK +void rt_tick_sethook(void (*hook)(void)); +#endif void rt_system_timer_init(void); void rt_system_timer_thread_init(void); @@ -145,7 +154,12 @@ rt_err_t rt_thread_delay_until(rt_tick_t *tick, rt_tick_t inc_tick); rt_err_t rt_thread_mdelay(rt_int32_t ms); rt_err_t rt_thread_control(rt_thread_t thread, int cmd, void *arg); rt_err_t rt_thread_suspend(rt_thread_t thread); +rt_err_t rt_thread_suspend_with_flag(rt_thread_t thread, int suspend_flag); rt_err_t rt_thread_resume(rt_thread_t thread); +#ifdef RT_USING_LWP +rt_err_t rt_thread_wakeup(rt_thread_t thread); +void rt_thread_wakeup_set(struct rt_thread *thread, rt_wakeup_func_t func, void* user_data); +#endif void rt_thread_timeout(void *parameter); #ifdef RT_USING_SIGNALS @@ -168,7 +182,6 @@ void rt_thread_idle_init(void); rt_err_t rt_thread_idle_sethook(void (*hook)(void)); rt_err_t rt_thread_idle_delhook(void (*hook)(void)); #endif -void rt_thread_idle_excute(void); rt_thread_t rt_thread_idle_gethandler(void); /* @@ -190,6 +203,7 @@ void rt_scheduler_sethook(void (*hook)(rt_thread_t from, rt_thread_t to)); #endif #ifdef RT_USING_SMP +void rt_secondary_cpu_entry(void); void rt_scheduler_ipi_handler(int vector, void *param); #endif @@ -307,6 +321,8 @@ rt_sem_t rt_sem_create(const char *name, rt_uint32_t value, rt_uint8_t flag); rt_err_t rt_sem_delete(rt_sem_t sem); rt_err_t rt_sem_take(rt_sem_t sem, rt_int32_t time); +rt_err_t rt_sem_take_interruptible(rt_sem_t sem, rt_int32_t time); +rt_err_t rt_sem_take_killable(rt_sem_t sem, rt_int32_t time); rt_err_t rt_sem_trytake(rt_sem_t sem); rt_err_t rt_sem_release(rt_sem_t sem); rt_err_t rt_sem_control(rt_sem_t sem, int cmd, void *arg); @@ -322,6 +338,8 @@ rt_mutex_t rt_mutex_create(const char *name, rt_uint8_t flag); rt_err_t rt_mutex_delete(rt_mutex_t mutex); rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t time); +rt_err_t rt_mutex_take_interruptible(rt_mutex_t mutex, rt_int32_t time); +rt_err_t rt_mutex_take_killable(rt_mutex_t mutex, rt_int32_t time); rt_err_t rt_mutex_release(rt_mutex_t mutex); rt_err_t rt_mutex_control(rt_mutex_t mutex, int cmd, void *arg); #endif @@ -341,6 +359,16 @@ rt_err_t rt_event_recv(rt_event_t event, rt_uint8_t opt, rt_int32_t timeout, rt_uint32_t *recved); +rt_err_t rt_event_recv_interruptible(rt_event_t event, + rt_uint32_t set, + rt_uint8_t opt, + rt_int32_t timeout, + rt_uint32_t *recved); +rt_err_t rt_event_recv_killable(rt_event_t event, + rt_uint32_t set, + rt_uint8_t opt, + rt_int32_t timeout, + rt_uint32_t *recved); rt_err_t rt_event_control(rt_event_t event, int cmd, void *arg); #endif @@ -361,7 +389,15 @@ rt_err_t rt_mb_send(rt_mailbox_t mb, rt_ubase_t value); rt_err_t rt_mb_send_wait(rt_mailbox_t mb, rt_ubase_t value, rt_int32_t timeout); +rt_err_t rt_mb_send_wait_interruptible(rt_mailbox_t mb, + rt_ubase_t value, + rt_int32_t timeout); +rt_err_t rt_mb_send_wait_killable(rt_mailbox_t mb, + rt_ubase_t value, + rt_int32_t timeout); rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout); +rt_err_t rt_mb_recv_interruptibale(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout); +rt_err_t rt_mb_recv_killable(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout); rt_err_t rt_mb_control(rt_mailbox_t mb, int cmd, void *arg); #endif @@ -383,18 +419,40 @@ rt_mq_t rt_mq_create(const char *name, rt_err_t rt_mq_delete(rt_mq_t mq); rt_err_t rt_mq_send(rt_mq_t mq, const void *buffer, rt_size_t size); +rt_err_t rt_mq_send_interrupt(rt_mq_t mq, const void *buffer, rt_size_t size); +rt_err_t rt_mq_send_killable(rt_mq_t mq, const void *buffer, rt_size_t size); rt_err_t rt_mq_send_wait(rt_mq_t mq, const void *buffer, rt_size_t size, rt_int32_t timeout); +rt_err_t rt_mq_send_wait_interruptible(rt_mq_t mq, + const void *buffer, + rt_size_t size, + rt_int32_t timeout); +rt_err_t rt_mq_send_wait_killable(rt_mq_t mq, + const void *buffer, + rt_size_t size, + rt_int32_t timeout); rt_err_t rt_mq_urgent(rt_mq_t mq, const void *buffer, rt_size_t size); rt_err_t rt_mq_recv(rt_mq_t mq, void *buffer, rt_size_t size, rt_int32_t timeout); +rt_err_t rt_mq_recv_interruptible(rt_mq_t mq, + void *buffer, + rt_size_t size, + rt_int32_t timeout); +rt_err_t rt_mq_recv_killable(rt_mq_t mq, + void *buffer, + rt_size_t size, + rt_int32_t timeout); rt_err_t rt_mq_control(rt_mq_t mq, int cmd, void *arg); #endif +/* defunct */ +void rt_thread_defunct_enqueue(rt_thread_t thread); +rt_thread_t rt_thread_defunct_dequeue(void); + /* * spinlock */ @@ -493,6 +551,7 @@ struct rt_cpu *rt_cpu_index(int index); rt_uint8_t rt_interrupt_get_nest(void); #ifdef RT_USING_HOOK +void rt_scheduler_switch_sethook(void (*hook)(struct rt_thread *tid)); void rt_interrupt_enter_sethook(void (*hook)(void)); void rt_interrupt_leave_sethook(void (*hook)(void)); #endif @@ -569,7 +628,7 @@ void rt_assert_handler(const char *ex, const char *func, rt_size_t line); #endif /* RT_DEBUG */ #ifdef RT_USING_FINSH -#include +#include #endif /**@}*/ diff --git a/libcpu/Kconfig b/libcpu/Kconfig index ae2767dec9ca53cfe5e53fd4b3a73f8040b7363b..2e6307be97620b932e4b772a936a40afb3722521 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -1,13 +1,27 @@ config ARCH_CPU_64BIT bool -config ARCH_ARM +config RT_USING_CACHE bool + default n config RT_USING_CPU_FFS bool default n +config ARCH_CPU_STACK_GROWS_UPWARD + bool + default n + +config ARCH_MM_MMU + bool + +config ARCH_MM_MPU + bool + +config ARCH_ARM + bool + config ARCH_ARM_CORTEX_M bool select ARCH_ARM @@ -27,6 +41,7 @@ config ARCH_ARM_CORTEX_M3 config ARCH_ARM_MPU bool depends on ARCH_ARM + select ARCH_MM_MPU config ARCH_ARM_CORTEX_M4 bool @@ -44,8 +59,31 @@ config ARCH_ARM_CORTEX_R config ARCH_ARM_MMU bool + select RT_USING_CACHE + select ARCH_MM_MMU depends on ARCH_ARM +config RT_USING_USERSPACE + bool "Isolated user space" + default n + depends on ARCH_MM_MMU + +config KERNEL_VADDR_START + hex "The virtural address of kernel start" + default 0xc0000000 + depends on RT_USING_USERSPACE + +config PV_OFFSET + hex "The offset of kernel physical address and virtural address" + default 0 + depends on RT_USING_USERSPACE + +config RT_IOREMAP_LATE + bool "Support to create IO mapping in the kernel address space after system initlalization." + default n + depends on ARCH_ARM_CORTEX_A + depends on RT_USING_USERSPACE + config ARCH_ARM_ARM9 bool select ARCH_ARM @@ -74,18 +112,26 @@ config ARCH_ARM_CORTEX_A9 bool select ARCH_ARM_CORTEX_A +config ARCH_ARM_SECURE_MODE + bool "Running in secure mode [ARM Cortex-A]" + default n + depends on ARCH_ARM_CORTEX_A + +config RT_BACKTRACE_FUNCTION_NAME + bool "To show function name when backtrace." + default n + depends on ARCH_ARM_CORTEX_A + config ARCH_ARMV8 bool + select ARCH_ARM config ARCH_MIPS bool config ARCH_MIPS64 bool - select ARCH_CPU_64BIT - -config ARCH_CPU_64BIT - bool + select ARCH_CPU_64BIT config ARCH_MIPS_XBURST bool @@ -128,7 +174,3 @@ config ARCH_TIDSP_C28X config ARCH_HOST_SIMULATOR bool - -config ARCH_CPU_STACK_GROWS_UPWARD - bool - default n diff --git a/libcpu/aarch64/common/armv8.h b/libcpu/aarch64/common/armv8.h index 43508905443e73c1c87af39c7e115147559cb505..9527ba5169c073dabbfa2c6d61b5bcd33b3f89d7 100644 --- a/libcpu/aarch64/common/armv8.h +++ b/libcpu/aarch64/common/armv8.h @@ -14,47 +14,51 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long long pc; - unsigned long long spsr; - unsigned long long x30; - unsigned long long xz; - unsigned long long x28; - unsigned long long x29; - unsigned long long x26; - unsigned long long x27; - unsigned long long x24; - unsigned long long x25; - unsigned long long x22; - unsigned long long x23; - unsigned long long x20; - unsigned long long x21; - unsigned long long x18; - unsigned long long x19; - unsigned long long x16; - unsigned long long x17; - unsigned long long x14; - unsigned long long x15; - unsigned long long x12; - unsigned long long x13; - unsigned long long x10; - unsigned long long x11; - unsigned long long x8; - unsigned long long x9; - unsigned long long x6; - unsigned long long x7; - unsigned long long x4; - unsigned long long x5; - unsigned long long x2; - unsigned long long x3; - unsigned long long x0; - unsigned long long x1; + unsigned long pc; + unsigned long cpsr; + unsigned long sp_el0; + unsigned long x30; + unsigned long fpcr; + unsigned long fpsr; + unsigned long x28; + unsigned long x29; + unsigned long x26; + unsigned long x27; + unsigned long x24; + unsigned long x25; + unsigned long x22; + unsigned long x23; + unsigned long x20; + unsigned long x21; + unsigned long x18; + unsigned long x19; + unsigned long x16; + unsigned long x17; + unsigned long x14; + unsigned long x15; + unsigned long x12; + unsigned long x13; + unsigned long x10; + unsigned long x11; + unsigned long x8; + unsigned long x9; + unsigned long x6; + unsigned long x7; + unsigned long x4; + unsigned long x5; + unsigned long x2; + unsigned long x3; + unsigned long x0; + unsigned long x1; + + unsigned long long fpu[16]; }; -#define SP_ELx ( ( unsigned long long ) 0x01 ) -#define SP_EL0 ( ( unsigned long long ) 0x00 ) -#define PSTATE_EL1 ( ( unsigned long long ) 0x04 ) -#define PSTATE_EL2 ( ( unsigned long long ) 0x08 ) -#define PSTATE_EL3 ( ( unsigned long long ) 0x0c ) +#define SP_ELx ( ( unsigned long ) 0x01 ) +#define SP_EL0 ( ( unsigned long ) 0x00 ) +#define PSTATE_EL1 ( ( unsigned long ) 0x04 ) +#define PSTATE_EL2 ( ( unsigned long ) 0x08 ) +#define PSTATE_EL3 ( ( unsigned long ) 0x0c ) rt_ubase_t rt_hw_get_current_el(void); void rt_hw_set_elx_env(void); diff --git a/libcpu/aarch64/common/asm-fpu.h b/libcpu/aarch64/common/asm-fpu.h new file mode 100644 index 0000000000000000000000000000000000000000..8ac4ab9bd88111012a28d1aa3388099060512bf0 --- /dev/null +++ b/libcpu/aarch64/common/asm-fpu.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 Jesven the first version + */ + +.macro SAVE_FPU, reg + STR Q0, [\reg, #-0x10]! + STR Q1, [\reg, #-0x10]! + STR Q2, [\reg, #-0x10]! + STR Q3, [\reg, #-0x10]! + STR Q4, [\reg, #-0x10]! + STR Q5, [\reg, #-0x10]! + STR Q6, [\reg, #-0x10]! + STR Q7, [\reg, #-0x10]! + STR Q8, [\reg, #-0x10]! + STR Q9, [\reg, #-0x10]! + STR Q10, [\reg, #-0x10]! + STR Q11, [\reg, #-0x10]! + STR Q12, [\reg, #-0x10]! + STR Q13, [\reg, #-0x10]! + STR Q14, [\reg, #-0x10]! + STR Q15, [\reg, #-0x10]! +.endm +.macro RESTORE_FPU, reg + LDR Q15, [\reg], #0x10 + LDR Q14, [\reg], #0x10 + LDR Q13, [\reg], #0x10 + LDR Q12, [\reg], #0x10 + LDR Q11, [\reg], #0x10 + LDR Q10, [\reg], #0x10 + LDR Q9, [\reg], #0x10 + LDR Q8, [\reg], #0x10 + LDR Q7, [\reg], #0x10 + LDR Q6, [\reg], #0x10 + LDR Q5, [\reg], #0x10 + LDR Q4, [\reg], #0x10 + LDR Q3, [\reg], #0x10 + LDR Q2, [\reg], #0x10 + LDR Q1, [\reg], #0x10 + LDR Q0, [\reg], #0x10 +.endm diff --git a/libcpu/aarch64/common/cache.S b/libcpu/aarch64/common/cache.S index 7f295a2b02f7758886f81d4cee9e7f70dcf83f66..bd8504e9ff0a002266b28a01d677ffe05406154f 100644 --- a/libcpu/aarch64/common/cache.S +++ b/libcpu/aarch64/common/cache.S @@ -127,7 +127,59 @@ __asm_flush_dcache_range: /* x2 <- minimal cache line size in cache system */ sub x3, x2, #1 bic x0, x0, x3 -1: dc civac, x0 /* clean & invalidate data or unified cache */ + +1: dc civac, x0 /* clean & invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret + +/* void __asm_invalidate_dcache_range(start, end) + * + * invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +.globl __asm_invalidate_dcache_range +__asm_invalidate_dcache_range: + mrs x3, ctr_el0 + lsr x3, x3, #16 + and x3, x3, #0xf + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 + +1: dc ivac, x0 /* invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret + +/* void __asm_invalidate_icache_range(start, end) + * + * invalidate icache in the range + * + * x0: start address + * x1: end address + */ +.globl __asm_invalidate_icache_range +__asm_invalidate_icache_range: + mrs x3, ctr_el0 + and x3, x3, #0xf + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 + +1: ic ivau, x0 /* invalidate instruction or unified cache */ add x0, x0, x2 cmp x0, x1 b.lo 1b @@ -148,4 +200,4 @@ __asm_invalidate_icache_all: .globl __asm_flush_l3_cache __asm_flush_l3_cache: mov x0, #0 /* return status as success */ - ret \ No newline at end of file + ret diff --git a/libcpu/aarch64/common/cache_ops.c b/libcpu/aarch64/common/cache_ops.c new file mode 100644 index 0000000000000000000000000000000000000000..018f0be4a496a102765a6a876e593a40d9ce8cf7 --- /dev/null +++ b/libcpu/aarch64/common/cache_ops.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-29 quanzhao the first version + */ +#include +#include + +void __asm_invalidate_icache_all(void); +void __asm_flush_dcache_all(void); +void __asm_flush_dcache_range(unsigned long start, unsigned long end); +void __asm_invalidate_dcache_range(unsigned long start, unsigned long end); +void __asm_invalidate_icache_range(unsigned long start, unsigned long end); +void __asm_invalidate_dcache_all(void); +void __asm_invalidate_icache_all(void); + +rt_inline rt_uint32_t rt_cpu_icache_line_size(void) +{ + return 0; +} + +rt_inline rt_uint32_t rt_cpu_dcache_line_size(void) +{ + return 0; +} + +void rt_hw_cpu_icache_invalidate(void *addr, int size) +{ + __asm_invalidate_icache_range((unsigned long)addr, (unsigned long)addr + size); +} + +void rt_hw_cpu_dcache_invalidate(void *addr, int size) +{ + __asm_invalidate_dcache_range((unsigned long)addr, (unsigned long)addr + size); +} + +void rt_hw_cpu_dcache_clean(void *addr, int size) +{ + __asm_flush_dcache_range((unsigned long)addr, (unsigned long)addr + size); +} + +void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size) +{ + __asm_flush_dcache_range((unsigned long)addr, (unsigned long)addr + size); +} + +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_INVALIDATE) + { + rt_hw_cpu_icache_invalidate(addr, size); + } +} + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) + { + rt_hw_cpu_dcache_clean(addr, size); + } + else if (ops == RT_HW_CACHE_INVALIDATE) + { + rt_hw_cpu_dcache_invalidate(addr, size); + } +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} + +#ifdef RT_USING_LWP +#define ICACHE (1<<0) +#define DCACHE (1<<1) +#define BCACHE (ICACHE|DCACHE) + +int sys_cacheflush(void *addr, int size, int cache) +{ + if ((size_t)addr < KERNEL_VADDR_START && (size_t)addr + size <= KERNEL_VADDR_START) + { + if ((cache & DCACHE) != 0) + { + rt_hw_cpu_dcache_clean_and_invalidate(addr, size); + } + if ((cache & ICACHE) != 0) + { + rt_hw_cpu_icache_invalidate(addr, size); + } + return 0; + } + return -1; +} +#endif diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S index 934db7ed840707687a41e220234c8b7d6d3f5474..6f6323abe954bc18f07936b9987ad2d6319b0e7f 100644 --- a/libcpu/aarch64/common/context_gcc.S +++ b/libcpu/aarch64/common/context_gcc.S @@ -1,217 +1,279 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-10-06 ZhaoXiaowei the first version + * 2021-05-18 Jesven the first version */ +#include "rtconfig.h" + +#include "asm-fpu.h" + +.text +.weak rt_hw_cpu_id_set +.type rt_hw_cpu_id_set, @function +rt_hw_cpu_id_set: + mrs x0, mpidr_el1 /* MPIDR_EL1: Multi-Processor Affinity Register */ + and x0, x0, #15 + msr tpidr_el1, x0 + ret + +/* +int rt_hw_cpu_id(void) +*/ +.global rt_hw_cpu_id +.type rt_hw_cpu_id, @function +rt_hw_cpu_id: + mrs x0, tpidr_el1 /* MPIDR_EL1: Multi-Processor Affinity Register */ + ret + +/* +void set_process_id(size_t id) +*/ +.global set_process_id +set_process_id: + msr CONTEXTIDR_EL1, x0 + ret + /* *enable gtimer */ .globl rt_hw_gtimer_enable rt_hw_gtimer_enable: - MOV X0,#1 - MSR CNTP_CTL_EL0,X0 - RET + MOV X0,#1 + MSR CNTP_CTL_EL0,X0 + RET /* *set gtimer CNTP_TVAL_EL0 value */ .globl rt_hw_set_gtimer_val rt_hw_set_gtimer_val: - MSR CNTP_TVAL_EL0,X0 - RET + MSR CNTP_TVAL_EL0,X0 + RET /* *get gtimer CNTP_TVAL_EL0 value */ .globl rt_hw_get_gtimer_val rt_hw_get_gtimer_val: - MRS X0,CNTP_TVAL_EL0 - RET + MRS X0,CNTP_TVAL_EL0 + RET .globl rt_hw_get_cntpct_val rt_hw_get_cntpct_val: - MRS X0, CNTPCT_EL0 - RET + MRS X0, CNTPCT_EL0 + RET /* *get gtimer frq value */ .globl rt_hw_get_gtimer_frq rt_hw_get_gtimer_frq: - MRS X0,CNTFRQ_EL0 - RET + MRS X0,CNTFRQ_EL0 + RET .macro SAVE_CONTEXT - - /* Switch to use the EL0 stack pointer. */ - MSR SPSEL, #0 - /* Save the entire context. */ - STP X0, X1, [SP, #-0x10]! - STP X2, X3, [SP, #-0x10]! - STP X4, X5, [SP, #-0x10]! - STP X6, X7, [SP, #-0x10]! - STP X8, X9, [SP, #-0x10]! - STP X10, X11, [SP, #-0x10]! - STP X12, X13, [SP, #-0x10]! - STP X14, X15, [SP, #-0x10]! - STP X16, X17, [SP, #-0x10]! - STP X18, X19, [SP, #-0x10]! - STP X20, X21, [SP, #-0x10]! - STP X22, X23, [SP, #-0x10]! - STP X24, X25, [SP, #-0x10]! - STP X26, X27, [SP, #-0x10]! - STP X28, X29, [SP, #-0x10]! - STP X30, XZR, [SP, #-0x10]! - - MRS X0, CurrentEL - CMP X0, 0xc - B.EQ 3f - CMP X0, 0x8 - B.EQ 2f - CMP X0, 0x4 - B.EQ 1f - B . -3: - MRS X3, SPSR_EL3 - /* Save the ELR. */ - MRS X2, ELR_EL3 - B 0f -2: - MRS X3, SPSR_EL2 - /* Save the ELR. */ - MRS X2, ELR_EL2 - B 0f -1: - MRS X3, SPSR_EL1 - MRS X2, ELR_EL1 - B 0f -0: - - STP X2, X3, [SP, #-0x10]! - - MOV X0, SP /* Move SP into X0 for saving. */ - - /* Switch to use the ELx stack pointer. */ - MSR SPSEL, #1 - - .endm - -.macro SAVE_CONTEXT_T - - /* Switch to use the EL0 stack pointer. */ - MSR SPSEL, #0 - + SAVE_FPU SP + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + MRS X28, FPCR + MRS X29, FPSR + STP X28, X29, [SP, #-0x10]! + MRS X29, SP_EL0 + STP X29, X30, [SP, #-0x10]! + + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 + + STP X2, X3, [SP, #-0x10]! + + MOV X0, SP /* Move SP into X0 for saving. */ +.endm + +.macro SAVE_CONTEXT_FROM_EL1 /* Save the entire context. */ - STP X0, X1, [SP, #-0x10]! - STP X2, X3, [SP, #-0x10]! - STP X4, X5, [SP, #-0x10]! - STP X6, X7, [SP, #-0x10]! - STP X8, X9, [SP, #-0x10]! - STP X10, X11, [SP, #-0x10]! - STP X12, X13, [SP, #-0x10]! - STP X14, X15, [SP, #-0x10]! - STP X16, X17, [SP, #-0x10]! - STP X18, X19, [SP, #-0x10]! - STP X20, X21, [SP, #-0x10]! - STP X22, X23, [SP, #-0x10]! - STP X24, X25, [SP, #-0x10]! - STP X26, X27, [SP, #-0x10]! - STP X28, X29, [SP, #-0x10]! - STP X30, XZR, [SP, #-0x10]! - - MRS X0, CurrentEL - CMP X0, 0xc - B.EQ 3f - CMP X0, 0x8 - B.EQ 2f - CMP X0, 0x4 - B.EQ 1f - B . -3: - MRS X3, SPSR_EL3 - MOV X2, X30 - B 0f -2: - MRS X3, SPSR_EL2 - MOV X2, X30 - B 0f -1: - MRS X3, SPSR_EL1 - MOV X2, X30 - B 0f -0: - - STP X2, X3, [SP, #-0x10]! - - MOV X0, SP /* Move SP into X0 for saving. */ - - /* Switch to use the ELx stack pointer. */ - MSR SPSEL, #1 - - .endm - + SAVE_FPU SP + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + MRS X28, FPCR + MRS X29, FPSR + STP X28, X29, [SP, #-0x10]! + MRS X29, SP_EL0 + STP X29, X30, [SP, #-0x10]! + + MOV X19, #((3 << 6) | 0x4 | 0x1) /* el1h, disable interrupt */ + MOV X18, X30 + + STP X18, X19, [SP, #-0x10]! +.endm + +#ifdef RT_USING_SMP .macro RESTORE_CONTEXT + /* Set the SP to point to the stack of the task being restored. */ + MOV SP, X0 + +#ifdef RT_USING_GDBSERVER + bl lwp_check_debug +#endif + + BL lwp_check_exit + + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + + TST X3, #0x1f + MSR SPSR_EL1, X3 + MSR ELR_EL1, X2 + + LDP X29, X30, [SP], #0x10 + MSR SP_EL0, X29 + LDP X28, X29, [SP], #0x10 + MSR FPCR, X28 + MSR FPSR, X29 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + RESTORE_FPU SP + + BEQ ret_to_user - /* Switch to use the EL0 stack pointer. */ - MSR SPSEL, #0 - + ERET +.endm +#else +.macro RESTORE_CONTEXT /* Set the SP to point to the stack of the task being restored. */ - MOV SP, X0 - - LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ - - MRS X0, CurrentEL - CMP X0, 0xc - B.EQ 3f - CMP X0, 0x8 - B.EQ 2f - CMP X0, 0x4 - B.EQ 1f - B . -3: - MSR SPSR_EL3, X3 - MSR ELR_EL3, X2 - B 0f -2: - MSR SPSR_EL2, X3 - MSR ELR_EL2, X2 - B 0f -1: - MSR SPSR_EL1, X3 - MSR ELR_EL1, X2 - B 0f -0: - - LDP X30, XZR, [SP], #0x10 - LDP X28, X29, [SP], #0x10 - LDP X26, X27, [SP], #0x10 - LDP X24, X25, [SP], #0x10 - LDP X22, X23, [SP], #0x10 - LDP X20, X21, [SP], #0x10 - LDP X18, X19, [SP], #0x10 - LDP X16, X17, [SP], #0x10 - LDP X14, X15, [SP], #0x10 - LDP X12, X13, [SP], #0x10 - LDP X10, X11, [SP], #0x10 - LDP X8, X9, [SP], #0x10 - LDP X6, X7, [SP], #0x10 - LDP X4, X5, [SP], #0x10 - LDP X2, X3, [SP], #0x10 - LDP X0, X1, [SP], #0x10 - - /* Switch to use the ELx stack pointer. _RB_ Might not be required. */ - MSR SPSEL, #1 + MOV SP, X0 + +#ifdef RT_USING_LWP + bl lwp_check_exit +#endif + + BL lwp_check_exit + + BL rt_thread_self + MOV X19, X0 + BL lwp_mmu_switch + MOV X0, X19 + BL lwp_user_setting_restore + + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + + TST X3, #0x1f + MSR SPSR_EL1, X3 + MSR ELR_EL1, X2 + + LDP X29, X30, [SP], #0x10 + MSR SP_EL0, X29 + LDP X28, X29, [SP], #0x10 + MSR FPCR, X28 + MSR FPSR, X29 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + RESTORE_FPU SP + + BEQ ret_to_user ERET +.endm +#endif + +.macro RESTORE_CONTEXT_WITHOUT_MMU_SWITCH + /* the SP is already ok */ + BL lwp_check_exit + + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + + TST X3, #0x1f + MSR SPSR_EL1, X3 + MSR ELR_EL1, X2 + + LDP X29, X30, [SP], #0x10 + MSR SP_EL0, X29 + LDP X28, X29, [SP], #0x10 + MSR FPCR, X28 + MSR FPSR, X29 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + RESTORE_FPU SP + + BEQ ret_to_user - .endm + ERET +.endm + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif .text /* @@ -219,9 +281,9 @@ rt_hw_get_gtimer_frq: */ .globl rt_hw_interrupt_disable rt_hw_interrupt_disable: - MRS X0, DAIF - MSR DAIFSet, #3 - DSB SY + MRS X0, DAIF + MSR DAIFSet, #3 + DSB SY RET /* @@ -230,60 +292,154 @@ rt_hw_interrupt_disable: .globl rt_hw_interrupt_enable rt_hw_interrupt_enable: DSB SY - MOV X1, #0xC0 - ANDS X0, X0, X1 - B.NE rt_hw_interrupt_enable_exit - MSR DAIFClr, #3 -rt_hw_interrupt_enable_exit: + AND X0, X0, #0xc0 + MRS X1, DAIF + BIC X1, X1, #0xc0 + ORR X0, X0, X1 + MSR DAIF, X0 RET +.text + +#ifdef RT_USING_SMP + +/* + * void rt_hw_context_switch_to(rt_uint3 to, struct rt_thread *to_thread); + * X0 --> to (thread stack) + * X1 --> to_thread + */ + +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR X0, [X0] + MOV SP, X0 + MOV X0, X1 + BL rt_cpus_lock_status_restore + BL rt_thread_self + BL lwp_user_setting_restore + B rt_hw_context_switch_exit + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 +to, struct rt_thread *to_thread); + * X0 --> from (from_thread stack) + * X1 --> to (to_thread stack) + * X2 --> to_thread + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + SAVE_CONTEXT_FROM_EL1 + MOV X3, SP + STR X3, [X0] // store sp in preempted tasks TCB + LDR X0, [X1] // get new task stack pointer + MOV SP, X0 + MOV X0, X2 + BL rt_cpus_lock_status_restore + BL rt_thread_self + BL lwp_user_setting_restore + B rt_hw_context_switch_exit + +/* + * void rt_hw_context_switch_interrupt(context, from sp, to sp, tp tcb) + * X0 :interrupt context + * X1 :addr of from_thread's sp + * X2 :addr of to_thread's sp + * X3 :to_thread's tcb + */ +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X29, X30, [SP, #-0x10]! + BL rt_thread_self + BL lwp_user_setting_save + LDP X29, X30, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + STR X0, [X1] + LDR X0, [X2] + MOV SP, X0 + MOV X0, X3 + MOV X19, X0 + BL rt_cpus_lock_status_restore + MOV X0, X19 + BL lwp_user_setting_restore + B rt_hw_context_switch_exit + +.globl vector_fiq +vector_fiq: + B . + +.globl vector_irq +vector_irq: + CLREX + SAVE_CONTEXT + STP X0, X1, [SP, #-0x10]! /* X0 is thread sp */ + + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + LDP X0, X1, [SP], #0x10 + BL rt_scheduler_do_irq_switch + B rt_hw_context_switch_exit + +.global rt_hw_context_switch_exit +rt_hw_context_switch_exit: + MOV X0, SP + RESTORE_CONTEXT + +#else + /* * void rt_hw_context_switch_to(rt_ubase_t to); - * r0 --> to + * X0 --> to sp */ .globl rt_hw_context_switch_to rt_hw_context_switch_to: - LDR X0, [X0] + LDR X0, [X0] RESTORE_CONTEXT -.text /* * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); - * r0 --> from - * r1 --> to + * X0 --> from sp + * X1 --> to sp + * X2 --> to thread */ .globl rt_hw_context_switch rt_hw_context_switch: - MOV X8,X0 - MOV X9,X1 + SAVE_CONTEXT_FROM_EL1 + + MOV X2, SP + STR X2, [X0] // store sp in preempted tasks TCB + LDR X0, [X1] // get new task stack pointer - SAVE_CONTEXT_T - - STR X0, [X8] // store sp in preempted tasks TCB - LDR X0, [X9] // get new task stack pointer - RESTORE_CONTEXT /* - * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread); */ .globl rt_thread_switch_interrupt_flag .globl rt_interrupt_from_thread .globl rt_interrupt_to_thread .globl rt_hw_context_switch_interrupt rt_hw_context_switch_interrupt: - ADR X2, rt_thread_switch_interrupt_flag - LDR X3, [X2] - CMP X3, #1 - B.EQ _reswitch - ADR X4, rt_interrupt_from_thread // set rt_interrupt_from_thread - MOV X3, #1 // set rt_thread_switch_interrupt_flag to 1 - STR X0, [X4] - STR X3, [X2] + ADR X6, rt_thread_switch_interrupt_flag + LDR X7, [X6] + CMP X7, #1 + B.EQ _reswitch + ADR X4, rt_interrupt_from_thread // set rt_interrupt_from_thread + STR X0, [X4] + MOV X7, #1 // set rt_thread_switch_interrupt_flag to 1 + STR X7, [X6] + STP X1, X30, [SP, #-0x10]! + MOV X0, X2 + BL lwp_user_setting_save + LDP X1, X30, [SP], #0x10 _reswitch: - ADR X2, rt_interrupt_to_thread // set rt_interrupt_to_thread - STR X1, [X2] + ADR X6, rt_interrupt_to_thread // set rt_interrupt_to_thread + STR X1, [X6] RET .text @@ -294,9 +450,9 @@ _reswitch: .globl vector_fiq vector_fiq: SAVE_CONTEXT - STP X0, X1, [SP, #-0x10]! + STP X0, X1, [SP, #-0x10]! BL rt_hw_trap_fiq - LDP X0, X1, [SP], #0x10 + LDP X0, X1, [SP], #0x10 RESTORE_CONTEXT .globl rt_interrupt_enter @@ -312,20 +468,20 @@ vector_fiq: .globl vector_irq vector_irq: SAVE_CONTEXT - STP X0, X1, [SP, #-0x10]! + STP X0, X1, [SP, #-0x10]! /* X0 is thread sp */ BL rt_interrupt_enter BL rt_hw_trap_irq BL rt_interrupt_leave - - LDP X0, X1, [SP], #0x10 + + LDP X0, X1, [SP], #0x10 // if rt_thread_switch_interrupt_flag set, jump to // rt_hw_context_switch_interrupt_do and don't return - ADR X1, rt_thread_switch_interrupt_flag + ADR X1, rt_thread_switch_interrupt_flag LDR X2, [X1] CMP X2, #1 - B.NE vector_irq_exit + B.NE vector_irq_exit MOV X2, #0 // clear flag STR X2, [X1] @@ -337,15 +493,53 @@ vector_irq: ADR x3, rt_interrupt_to_thread LDR X4, [X3] LDR x0, [X4] // get new task's stack pointer - -vector_irq_exit: + RESTORE_CONTEXT +vector_irq_exit: + MOV SP, X0 + RESTORE_CONTEXT_WITHOUT_MMU_SWITCH +#endif + // ------------------------------------------------- - .align 8 - .globl vector_error -vector_error: + .globl vector_exception +vector_exception: SAVE_CONTEXT - BL rt_hw_trap_error - B . + STP X0, X1, [SP, #-0x10]! + BL rt_hw_trap_exception + LDP X0, X1, [SP], #0x10 + MOV SP, X0 + RESTORE_CONTEXT_WITHOUT_MMU_SWITCH + + .globl vector_serror +vector_serror: + SAVE_CONTEXT + STP X0, X1, [SP, #-0x10]! + BL rt_hw_trap_serror + b . + +.global switch_mmu +switch_mmu: + MSR TTBR0_EL1, X0 + MRS X1, TCR_EL1 + CMP X0, XZR + ORR X1, X1, #(1 << 7) + BEQ 1f + BIC X1, X1, #(1 << 7) +1: + MSR TCR_EL1, X1 + DSB SY + ISB + TLBI VMALLE1 + DSB SY + ISB + IC IALLUIS + DSB SY + ISB + RET + +.global mmu_table_get +mmu_table_get: + MRS X0, TTBR0_EL1 + RET diff --git a/libcpu/aarch64/common/cp15.h b/libcpu/aarch64/common/cp15.h index f3ffd6f8572814b46f00b8a55a588b071962fe3f..cb1458ceec6e987ba65a92351961df430ec3cf2f 100644 --- a/libcpu/aarch64/common/cp15.h +++ b/libcpu/aarch64/common/cp15.h @@ -47,107 +47,6 @@ __STATIC_FORCEINLINE void __DMB(void) __asm__ volatile ("dmb 0xF":::"memory"); } -#ifdef RT_USING_SMP -static inline void send_ipi_msg(int cpu, int ipi_vector) -{ - IPI_MAILBOX_SET(cpu) = 1 << ipi_vector; -} - -static inline void setup_bootstrap_addr(int cpu, int addr) -{ - CORE_MAILBOX3_SET(cpu) = addr; -} - -static inline void enable_cpu_ipi_intr(int cpu) -{ - COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK; -} - -static inline void enable_cpu_timer_intr(int cpu) -{ - CORETIMER_INTCTL(cpu) = 0x8; -} - -static inline void enable_cntv(void) -{ - rt_uint32_t cntv_ctl; - cntv_ctl = 1; - asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL -} - -static inline void disable_cntv(void) -{ - rt_uint32_t cntv_ctl; - cntv_ctl = 0; - asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL -} - -static inline void mask_cntv(void) -{ - rt_uint32_t cntv_ctl; - cntv_ctl = 2; - asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL -} - -static inline void unmask_cntv(void) -{ - rt_uint32_t cntv_ctl; - cntv_ctl = 1; - asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL -} - -static inline rt_uint64_t read_cntvct(void) -{ - rt_uint32_t val,val1; - asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1)); - return (val); -} - -static inline rt_uint64_t read_cntvoff(void) -{ - - rt_uint64_t val; - asm volatile("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val)); - return (val); -} - -static inline rt_uint32_t read_cntv_tval(void) -{ - rt_uint32_t val; - asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val) ); - return val; -} - - -static inline void write_cntv_tval(rt_uint32_t val) -{ - asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val) ); - return; -} - -static inline rt_uint32_t read_cntfrq(void) -{ - rt_uint32_t val; - asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val) ); - return val; -} - - -static inline rt_uint32_t read_cntctrl(void) -{ - rt_uint32_t val; - asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val) ); - return val; -} - -static inline uint32_t write_cntctrl(uint32_t val) -{ - - asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val) ); - return val; -} -#endif - unsigned long rt_cpu_get_smp_id(void); void rt_cpu_mmu_disable(void); diff --git a/libcpu/aarch64/common/cpu.c b/libcpu/aarch64/common/cpu.c index 962a53a0710765087adee863b094fdefd35e445e..2467c96773a7d87ba5fc1f628e8ca0c2186157fe 100644 --- a/libcpu/aarch64/common/cpu.c +++ b/libcpu/aarch64/common/cpu.c @@ -14,59 +14,53 @@ #include #include "cp15.h" -int rt_hw_cpu_id(void) -{ - int cpu_id; - rt_base_t value; - - __asm__ volatile ( - "mrs %0, mpidr_el1" - :"=r"(value) - ); - cpu_id = value & 0xf; - return cpu_id; -}; - #ifdef RT_USING_SMP void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) { lock->slock = 0; } +#define TICKET_SHIFT 16 void rt_hw_spin_lock(rt_hw_spinlock_t *lock) { - unsigned long tmp; - unsigned long newval; - rt_hw_spinlock_t lockval; - __asm__ __volatile__( - "pld [%0]" - ::"r"(&lock->slock) - ); - - __asm__ __volatile__( - "1: ldrex %0, [%3]\n" - " add %1, %0, %4\n" - " strex %2, %1, [%3]\n" - " teq %2, #0\n" - " bne 1b" - : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) - : "r" (&lock->slock), "I" (1 << 16) - : "cc"); - - while (lockval.tickets.next != lockval.tickets.owner) { - __WFE(); - lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); - } + unsigned int tmp; + struct __arch_tickets lockval, newval; - __DMB(); + asm volatile( + /* Atomically increment the next ticket. */ + " prfm pstl1strm, %3\n" + "1: ldaxr %w0, %3\n" + " add %w1, %w0, %w5\n" + " stxr %w2, %w1, %3\n" + " cbnz %w2, 1b\n" + /* Did we get the lock? */ + " eor %w1, %w0, %w0, ror #16\n" + " cbz %w1, 3f\n" + /* + * No: spin on the owner. Send a local event to avoid missing an + * unlock before the exclusive load. + */ + " sevl\n" + "2: wfe\n" + " ldaxrh %w2, %4\n" + " eor %w1, %w2, %w0, lsr #16\n" + " cbnz %w1, 2b\n" + /* We got the lock. Critical section starts here. */ + "3:" + : "=&r"(lockval), "=&r"(newval), "=&r"(tmp), "+Q"(*lock) + : "Q"(lock->tickets.owner), "I"(1 << TICKET_SHIFT) + : "memory"); + rt_hw_dmb(); } void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) { - __DMB(); - lock->tickets.owner++; - __DSB(); - __SEV(); + rt_hw_dmb(); + asm volatile( + " stlrh %w1, %0\n" + : "=Q"(lock->tickets.owner) + : "r"(lock->tickets.owner + 1) + : "memory"); } #endif /*RT_USING_SMP*/ diff --git a/libcpu/aarch64/common/cpu_gcc.S b/libcpu/aarch64/common/cpu_gcc.S index b8c8b8768c596714c29c7733ef18fc66cf1bb9f0..5e268714921c478303f6879bdab719df66978927 100644 --- a/libcpu/aarch64/common/cpu_gcc.S +++ b/libcpu/aarch64/common/cpu_gcc.S @@ -55,7 +55,6 @@ rt_hw_set_current_vbar: 0: RET - .globl rt_hw_set_elx_env rt_hw_set_elx_env: MRS X1, CurrentEL @@ -80,3 +79,22 @@ rt_hw_set_elx_env: B 0f 0: RET + +.global rt_cpu_vector_set_base +rt_cpu_vector_set_base: + MSR VBAR_EL1,X0 + RET + + +.global ffz +ffz: + mvn x1, x0 + clz x0, x1 + mov x1, #0x3f + sub x0, x1, x0 + ret + +.global rt_clz +rt_clz: + clz x0, x0 + ret diff --git a/libcpu/aarch64/common/cpuport.h b/libcpu/aarch64/common/cpuport.h new file mode 100644 index 0000000000000000000000000000000000000000..9f209069aca34d3ac8745586bdab3d475aff8b7a --- /dev/null +++ b/libcpu/aarch64/common/cpuport.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#include + +#ifdef RT_USING_SMP +typedef union { + unsigned long slock; + struct __arch_tickets { + unsigned short owner; + unsigned short next; + } tickets; +} rt_hw_spinlock_t; +#endif + +rt_inline void rt_hw_isb(void) +{ + asm volatile ("isb":::"memory"); +} + +rt_inline void rt_hw_dmb(void) +{ + asm volatile ("dmb sy":::"memory"); +} + +rt_inline void rt_hw_dsb(void) +{ + asm volatile ("dsb sy":::"memory"); +} + +#endif /*CPUPORT_H__*/ diff --git a/libcpu/aarch64/common/exception.c b/libcpu/aarch64/common/exception.c new file mode 100644 index 0000000000000000000000000000000000000000..c2ad726bdd0991b48fa205a1e96a8555eef75d60 --- /dev/null +++ b/libcpu/aarch64/common/exception.c @@ -0,0 +1,232 @@ +#include "rtthread.h" + +static void data_abort(unsigned long far, unsigned long iss) +{ + rt_kprintf("fault addr = 0x%016lx\n", far); + if (iss & 0x40) + { + rt_kprintf("abort caused by write instruction\n"); + } + else + { + rt_kprintf("abort caused by read instruction\n"); + } + switch (iss & 0x3f) + { + case 0b000000: + rt_kprintf("Address size fault, zeroth level of translation or translation table base register\n"); + break; + + case 0b000001: + rt_kprintf("Address size fault, first level\n"); + break; + + case 0b000010: + rt_kprintf("Address size fault, second level\n"); + break; + + case 0b000011: + rt_kprintf("Address size fault, third level\n"); + break; + + case 0b000100: + rt_kprintf("Translation fault, zeroth level\n"); + break; + + case 0b000101: + rt_kprintf("Translation fault, first level\n"); + break; + + case 0b000110: + rt_kprintf("Translation fault, second level\n"); + break; + + case 0b000111: + rt_kprintf("Translation fault, third level\n"); + break; + + case 0b001001: + rt_kprintf("Access flag fault, first level\n"); + break; + + case 0b001010: + rt_kprintf("Access flag fault, second level\n"); + break; + + case 0b001011: + rt_kprintf("Access flag fault, third level\n"); + break; + + case 0b001101: + rt_kprintf("Permission fault, first level\n"); + break; + + case 0b001110: + rt_kprintf("Permission fault, second level\n"); + break; + + case 0b001111: + rt_kprintf("Permission fault, third level\n"); + break; + + case 0b010000: + rt_kprintf("Synchronous external abort, not on translation table walk\n"); + break; + + case 0b011000: + rt_kprintf("Synchronous parity or ECC error on memory access, not on translation table walk\n"); + break; + + case 0b010100: + rt_kprintf("Synchronous external abort on translation table walk, zeroth level\n"); + break; + + case 0b010101: + rt_kprintf("Synchronous external abort on translation table walk, first level\n"); + break; + + case 0b010110: + rt_kprintf("Synchronous external abort on translation table walk, second level\n"); + break; + + case 0b010111: + rt_kprintf("Synchronous external abort on translation table walk, third level\n"); + break; + + case 0b011100: + rt_kprintf("Synchronous parity or ECC error on memory access on translation table walk, zeroth level\n"); + break; + + case 0b011101: + rt_kprintf("Synchronous parity or ECC error on memory access on translation table walk, first level\n"); + break; + + case 0b011110: + rt_kprintf("Synchronous parity or ECC error on memory access on translation table walk, second level\n"); + break; + + case 0b011111: + rt_kprintf("Synchronous parity or ECC error on memory access on translation table walk, third level\n"); + break; + + case 0b100001: + rt_kprintf("Alignment fault\n"); + break; + + case 0b110000: + rt_kprintf("TLB conflict abort\n"); + break; + + case 0b110100: + rt_kprintf("IMPLEMENTATION DEFINED fault (Lockdown fault)\n"); + break; + + case 0b110101: + rt_kprintf("IMPLEMENTATION DEFINED fault (Unsupported Exclusive access fault)\n"); + break; + + case 0b111101: + rt_kprintf("Section Domain Fault, used only for faults reported in the PAR_EL1\n"); + break; + + case 0b111110: + rt_kprintf("Page Domain Fault, used only for faults reported in the PAR_EL1\n"); + break; + + default: + rt_kprintf("unknow abort\n"); + break; + } +} + +void process_exception(unsigned long esr, unsigned long epc) +{ + rt_uint8_t ec; + rt_uint32_t iss; + unsigned long fault_addr; + rt_kprintf("\nexception info:\n"); + ec = (unsigned char)((esr >> 26) & 0x3fU); + iss = (unsigned int)(esr & 0x00ffffffU); + rt_kprintf("esr.EC :0x%02x\n", ec); + rt_kprintf("esr.IL :0x%02x\n", (unsigned char)((esr >> 25) & 0x01U)); + rt_kprintf("esr.ISS:0x%08x\n", iss); + rt_kprintf("epc :0x%016p\n", (void *)epc); + switch (ec) + { + case 0x00: + rt_kprintf("Exceptions with an unknow reason\n"); + break; + + case 0x01: + rt_kprintf("Exceptions from an WFI or WFE instruction\n"); + break; + + case 0x03: + rt_kprintf("Exceptions from an MCR or MRC access to CP15 from AArch32\n"); + break; + + case 0x04: + rt_kprintf("Exceptions from an MCRR or MRRC access to CP15 from AArch32\n"); + break; + + case 0x05: + rt_kprintf("Exceptions from an MCR or MRC access to CP14 from AArch32\n"); + break; + + case 0x06: + rt_kprintf("Exceptions from an LDC or STC access to CP14 from AArch32\n"); + break; + + case 0x07: + rt_kprintf("Exceptions from Access to Advanced SIMD or floating-point registers\n"); + break; + + case 0x08: + rt_kprintf("Exceptions from an MRC (or VMRS) access to CP10 from AArch32\n"); + break; + + case 0x0c: + rt_kprintf("Exceptions from an MCRR or MRRC access to CP14 from AArch32\n"); + break; + + case 0x0e: + rt_kprintf("Exceptions that occur because ther value of PSTATE.IL is 1\n"); + break; + + case 0x11: + rt_kprintf("SVC call from AArch32 state\n"); + break; + + case 0x15: + rt_kprintf("SVC call from AArch64 state\n"); + break; + + case 0x20: + rt_kprintf("Instruction abort from lower exception level\n"); + break; + + case 0x21: + rt_kprintf("Instruction abort from current exception level\n"); + break; + + case 0x22: + rt_kprintf("PC alignment fault\n"); + break; + + case 0x24: + rt_kprintf("Data abort from a lower Exception level\n"); + __asm__ volatile("mrs %0, far_el1":"=r"(fault_addr)); + data_abort(fault_addr, iss); + break; + + case 0x25: + rt_kprintf("Data abort\n"); + __asm__ volatile("mrs %0, far_el1":"=r"(fault_addr)); + data_abort(fault_addr, iss); + break; + + default: + rt_kprintf("Other error\n"); + break; + } +} diff --git a/libcpu/aarch64/common/gic.c b/libcpu/aarch64/common/gic.c new file mode 100644 index 0000000000000000000000000000000000000000..7c3150635dc54271c880d3550aa50022c3390bde --- /dev/null +++ b/libcpu/aarch64/common/gic.c @@ -0,0 +1,516 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2014-04-03 Grissiom many enhancements + * 2018-11-22 Jesven add rt_hw_ipi_send() + * add rt_hw_ipi_handler_install() + */ + +#include +#include + +#include "gic.h" +#include "cp15.h" + +struct arm_gic +{ + rt_uint64_t offset; /* the first interrupt index in the vector table */ + + rt_uint64_t dist_hw_base; /* the base address of the gic distributor */ + rt_uint64_t cpu_hw_base; /* the base addrees of the gic cpu interface */ +}; + +/* 'ARM_GIC_MAX_NR' is the number of cores */ +static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; + +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) + +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) + +static unsigned int _gic_max_irq; + +int arm_gic_get_active_irq(rt_uint64_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); + irq += _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint64_t index, int irq) +{ + rt_uint64_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; +} + +void arm_gic_mask(rt_uint64_t index, int irq) +{ + rt_uint64_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_umask(rt_uint64_t index, int irq) +{ + rt_uint64_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq) +{ + rt_uint64_t pend; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void arm_gic_set_pending_irq(rt_uint64_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void arm_gic_clear_pending_irq(rt_uint64_t index, int irq) +{ + rt_uint64_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config) +{ + rt_uint64_t icfgr; + rt_uint64_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); +} + +void arm_gic_clear_active(rt_uint64_t index, int irq) +{ + rt_uint64_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask) +{ + rt_uint64_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4U)*8U)); + old_tgt |= cpumask << ((irq % 4U)*8U); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority) +{ + rt_uint64_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; +} + +rt_uint64_t arm_gic_get_priority(rt_uint64_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + /* set priority mask */ + GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base) = priority & 0xFFUL; +} + +rt_uint64_t arm_gic_get_interface_prior_mask(rt_uint64_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point) +{ + GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base) = binary_point & 0x7U; +} + +rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index) +{ + return GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base); +} + +rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq) +{ + rt_uint64_t pending; + rt_uint64_t active; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void arm_gic_send_sgi(rt_uint64_t index, int irq, rt_uint64_t target_list, rt_uint64_t filter_list) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = + ((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL); +} + +rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); +} + +rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group) +{ + uint32_t igroupr; + uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT(group <= 1U); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ((group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +rt_uint64_t arm_gic_get_group(rt_uint64_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; +} + +int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start) +{ + unsigned int gic_type, i; + rt_uint64_t cpumask = 1U << 0U; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020U) + { + _gic_max_irq = 1020U; + } + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + { + _gic_max_irq = ARM_GIC_NR_IRQS; + } + + cpumask |= cpumask << 8U; + cpumask |= cpumask << 16U; + cpumask |= cpumask << 24U; + + GIC_DIST_CTRL(dist_base) = 0x0U; + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32U; i < _gic_max_irq; i += 16U) + { + GIC_DIST_CONFIG(dist_base, i) = 0x0U; + } + + /* Set all global interrupts to this CPU only. */ + for (i = 32U; i < _gic_max_irq; i += 4U) + { + GIC_DIST_TARGET(dist_base, i) = cpumask; + } + + /* Set priority on all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 4U) + { + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; + } + + /* Disable all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; + } + + /* All interrupts defaults to IGROUP1(IRQ). */ + /* + for (i = 0; i < _gic_max_irq; i += 32) + { + GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; + } + */ + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_IGROUP(dist_base, i) = 0U; + } + + /* Enable group0 and group1 interrupt forwarding. */ + GIC_DIST_CTRL(dist_base) = 0x01U; + + return 0; +} + +int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + if (!_gic_table[index].cpu_hw_base) + { + _gic_table[index].cpu_hw_base = cpu_base; + } + cpu_base = _gic_table[index].cpu_hw_base; + + GIC_CPU_PRIMASK(cpu_base) = 0xf0U; + GIC_CPU_BINPOINT(cpu_base) = 0x7U; + /* Enable CPU interrupt */ + GIC_CPU_CTRL(cpu_base) = 0x01U; + + return 0; +} + +void arm_gic_dump_type(rt_uint64_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint64_t index) +{ + unsigned int i, k; + + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n"); +} + +long gic_dump(void) +{ + arm_gic_dump_type(0); + arm_gic_dump(0); + + return 0; +} +MSH_CMD_EXPORT(gic_dump, show gic status); + diff --git a/libcpu/aarch64/common/gic.h b/libcpu/aarch64/common/gic.h new file mode 100644 index 0000000000000000000000000000000000000000..4cdcb4402888cbd6ebcc207c8c36cfea7ee2f33f --- /dev/null +++ b/libcpu/aarch64/common/gic.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#ifndef __GIC_H__ +#define __GIC_H__ + +#include +#include + +int arm_gic_get_active_irq(rt_uint64_t index); +void arm_gic_ack(rt_uint64_t index, int irq); + +void arm_gic_mask(rt_uint64_t index, int irq); +void arm_gic_umask(rt_uint64_t index, int irq); + +rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq); +void arm_gic_set_pending_irq(rt_uint64_t index, int irq); +void arm_gic_clear_pending_irq(rt_uint64_t index, int irq); + +void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config); +rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq); + +void arm_gic_clear_active(rt_uint64_t index, int irq); + +void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask); +rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq); + +void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority); +rt_uint64_t arm_gic_get_priority(rt_uint64_t index, int irq); + +void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority); +rt_uint64_t arm_gic_get_interface_prior_mask(rt_uint64_t index); + +void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point); +rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index); + +rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq); + +void arm_gic_send_sgi(rt_uint64_t index, int irq, rt_uint64_t target_list, rt_uint64_t filter_list); + +rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index); + +rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index); + +void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group); +rt_uint64_t arm_gic_get_group(rt_uint64_t index, int irq); + +int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base); + +void arm_gic_dump_type(rt_uint64_t index); +void arm_gic_dump(rt_uint64_t index); + +#endif + diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c deleted file mode 100644 index 1f4d8686366fbfcc00f9857916b6a622797f3f7e..0000000000000000000000000000000000000000 --- a/libcpu/aarch64/common/gic/gic_pl400.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - * 2014-04-03 Grissiom many enhancements - * 2018-11-22 Jesven add rt_hw_ipi_send() - * add rt_hw_ipi_handler_install() - */ -#include - -#include "gic_pl400.h" -#include "cp15.h" - -#define ARM_GIC_MAX_NR 1 -struct arm_gic -{ - rt_uint32_t offset; /* the first interrupt index in the vector table */ - - rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ - rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */ -}; - -/* 'ARM_GIC_MAX_NR' is the number of cores */ -static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; - -static unsigned int _gic_max_irq; - -int arm_gic_get_active_irq(rt_uint32_t index) -{ - int irq; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); - irq += _gic_table[index].offset; - return irq; -} - -void arm_gic_ack(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_mask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_clear_pending(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_clear_active(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -/* Set up the cpu mask for the specific interrupt */ -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) -{ - rt_uint32_t old_tgt; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); - old_tgt |= cpumask << ((irq % 4)*8); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -void arm_gic_umask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_dump_type(rt_uint32_t index) -{ - unsigned int gic_type; - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1 << 10) ? "has" : "no", - gic_type); -} - -void arm_gic_dump(rt_uint32_t index) -{ - unsigned int i, k; - - k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); - rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); - rt_kprintf("--- hw mask ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw pending ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw active ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n"); -} -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); -#endif - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) -{ - unsigned int gic_type, i; - rt_uint32_t cpumask = 1 << 0; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020) - _gic_max_irq = 1020; - if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ - _gic_max_irq = ARM_GIC_NR_IRQS; - - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - cpumask |= cpumask << 24; - - GIC_DIST_CTRL(dist_base) = 0x0; - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32; i < _gic_max_irq; i += 16) - GIC_DIST_CONFIG(dist_base, i) = 0x0; - - /* Set all global interrupts to this CPU only. */ - for (i = 32; i < _gic_max_irq; i += 4) - GIC_DIST_TARGET(dist_base, i) = cpumask; - - /* Set priority on all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 4) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; - - /* Disable all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; - -#if 0 - /* All interrupts defaults to IGROUP1(IRQ). */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; -#endif - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_IGROUP(dist_base, i) = 0; - - /* Enable group0 and group1 interrupt forwarding. */ - GIC_DIST_CTRL(dist_base) = 0x01; - - return 0; -} - -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].cpu_hw_base = cpu_base; - - GIC_CPU_PRIMASK(cpu_base) = 0xf0; - GIC_CPU_BINPOINT(cpu_base) = 0x7; - /* Enable CPU interrupt */ - GIC_CPU_CTRL(cpu_base) = 0x01; - - return 0; -} - -void arm_gic_set_group(rt_uint32_t index, int vector, int group) -{ - /* As for GICv2, there are only group0 and group1. */ - RT_ASSERT(group <= 1); - RT_ASSERT(vector < _gic_max_irq); - - if (group == 0) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) &= ~(1 << (vector % 32)); - } - else if (group == 1) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) |= (1 << (vector % 32)); - } -} - diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h deleted file mode 100644 index fa20846ea2d212d278f492735c13e60741c6ac57..0000000000000000000000000000000000000000 --- a/libcpu/aarch64/common/gic/gic_pl400.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __GIC_PL400_H__ -#define __GIC_PL400_H__ - -#include -#include - -#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x))) - -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) - -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); - -void arm_gic_mask(rt_uint32_t index, int irq); -void arm_gic_umask(rt_uint32_t index, int irq); -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); -void arm_gic_set_group(rt_uint32_t index, int vector, int group); - -int arm_gic_get_active_irq(rt_uint32_t index); -void arm_gic_ack(rt_uint32_t index, int irq); - -void arm_gic_clear_active(rt_uint32_t index, int irq); -void arm_gic_clear_pending(rt_uint32_t index, int irq); - -void arm_gic_dump_type(rt_uint32_t index); -void arm_gic_dump(rt_uint32_t index); - -#endif - diff --git a/libcpu/aarch64/cortex-a53/interrupt.c b/libcpu/aarch64/common/interrupt.c similarity index 37% rename from libcpu/aarch64/cortex-a53/interrupt.c rename to libcpu/aarch64/common/interrupt.c index a412ca195365a784937633e276eb30787c994103..71f48db366ef867148938a72118e4e33403424dd 100644 --- a/libcpu/aarch64/cortex-a53/interrupt.c +++ b/libcpu/aarch64/common/interrupt.c @@ -1,25 +1,32 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018/5/3 Bernard first version - * 2019-07-28 zdzn add smp support - * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, - * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi + * 2013-07-06 Bernard first version + * 2018-11-22 Jesven add smp support */ #include -#include #include - -#include "cp15.h" -#include "armv8.h" #include "interrupt.h" +#include "gic.h" -#define MAX_HANDLERS 72 +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +#ifndef RT_USING_SMP +/* Those variables will be accessed in ISR, so we need to share them. */ +rt_ubase_t rt_interrupt_from_thread = 0; +rt_ubase_t rt_interrupt_to_thread = 0; +rt_ubase_t rt_thread_switch_interrupt_flag = 0; +#endif + +const unsigned int VECTOR_BASE = 0x00; +extern void rt_cpu_vector_set_base(void *addr); +extern void *system_vectors; #ifdef RT_USING_SMP #define rt_interrupt_nest rt_cpu_self()->irq_nest @@ -27,20 +34,7 @@ extern volatile rt_uint8_t rt_interrupt_nest; #endif -extern int system_vectors; - -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; - -rt_ubase_t rt_interrupt_from_thread; -rt_ubase_t rt_interrupt_to_thread; -rt_ubase_t rt_thread_switch_interrupt_flag; - -void rt_hw_vector_init(void) -{ - rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S -} - +#ifdef SOC_BCM283x static void default_isr_handler(int vector, void *param) { #ifdef RT_USING_SMP @@ -49,13 +43,25 @@ static void default_isr_handler(int vector, void *param) rt_kprintf("unhandled irq: %d\n",vector); #endif } +#endif + +void rt_hw_vector_init(void) +{ + rt_cpu_vector_set_base(&system_vectors); +} /** * This function will initialize hardware interrupt */ void rt_hw_interrupt_init(void) { +#ifdef SOC_BCM283x rt_uint32_t index; + /* initialize vector table */ + rt_hw_vector_init(); + + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); /* mask all of interrupts */ IRQ_DISABLE_BASIC = 0x000000ff; @@ -64,7 +70,7 @@ void rt_hw_interrupt_init(void) for (index = 0; index < MAX_HANDLERS; index ++) { isr_table[index].handler = default_isr_handler; - isr_table[index].param = NULL; + isr_table[index].param = RT_NULL; #ifdef RT_USING_INTERRUPT_INFO rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX); isr_table[index].counter = 0; @@ -76,6 +82,31 @@ void rt_hw_interrupt_init(void) rt_interrupt_from_thread = 0; rt_interrupt_to_thread = 0; rt_thread_switch_interrupt_flag = 0; +#else + rt_uint64_t gic_cpu_base; + rt_uint64_t gic_dist_base; + rt_uint64_t gic_irq_start; + + /* initialize vector table */ + rt_hw_vector_init(); + + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + + /* initialize ARM GIC */ +#ifdef RT_USING_USERSPACE + gic_dist_base = (rt_uint64_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_dist_base(), 0x2000, MMU_MAP_K_DEVICE); + gic_cpu_base = (rt_uint64_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_cpu_base(), 0x1000, MMU_MAP_K_DEVICE); +#else + gic_dist_base = platform_get_gic_dist_base(); + gic_cpu_base = platform_get_gic_cpu_base(); +#endif + + gic_irq_start = GIC_IRQ_START; + + arm_gic_dist_init(0, gic_dist_base, gic_irq_start); + arm_gic_cpu_init(0, gic_cpu_base); +#endif } /** @@ -84,11 +115,12 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { +#ifdef SOC_BCM283x if (vector < 32) { IRQ_DISABLE1 = (1 << vector); } - else if (vector<64) + else if (vector < 64) { vector = vector % 32; IRQ_DISABLE2 = (1 << vector); @@ -98,6 +130,9 @@ void rt_hw_interrupt_mask(int vector) vector = vector - 64; IRQ_DISABLE_BASIC = (1 << vector); } +#else + arm_gic_mask(0, vector); +#endif } /** @@ -106,7 +141,8 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if (vector < 32) +#ifdef SOC_BCM283x +if (vector < 32) { IRQ_ENABLE1 = (1 << vector); } @@ -120,6 +156,176 @@ void rt_hw_interrupt_umask(int vector) vector = vector - 64; IRQ_ENABLE_BASIC = (1 << vector); } +#else + arm_gic_umask(0, vector); +#endif +} + +/** + * This function returns the active interrupt number. + * @param none + */ +int rt_hw_interrupt_get_irq(void) +{ +#ifndef SOC_BCM283x + return arm_gic_get_active_irq(0); +#else + return 0; +#endif +} + +/** + * This function acknowledges the interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_ack(int vector) +{ +#ifndef SOC_BCM283x + arm_gic_ack(0, vector); +#endif +} + +/** + * This function set interrupt CPU targets. + * @param vector: the interrupt number + * cpu_mask: target cpus mask, one bit for one core + */ +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask) +{ + arm_gic_set_cpu(0, vector, cpu_mask); +} + +/** + * This function get interrupt CPU targets. + * @param vector: the interrupt number + * @return target cpus mask, one bit for one core + */ +unsigned int rt_hw_interrupt_get_target_cpus(int vector) +{ + return arm_gic_get_target_cpu(0, vector); +} + +/** + * This function set interrupt triger mode. + * @param vector: the interrupt number + * mode: interrupt triger mode; 0: level triger, 1: edge triger + */ +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode) +{ + arm_gic_set_configuration(0, vector, mode); +} + +/** + * This function get interrupt triger mode. + * @param vector: the interrupt number + * @return interrupt triger mode; 0: level triger, 1: edge triger + */ +unsigned int rt_hw_interrupt_get_triger_mode(int vector) +{ + return arm_gic_get_configuration(0, vector); +} + +/** + * This function set interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_set_pending(int vector) +{ + arm_gic_set_pending_irq(0, vector); +} + +/** + * This function get interrupt pending flag. + * @param vector: the interrupt number + * @return interrupt pending flag, 0: not pending; 1: pending + */ +unsigned int rt_hw_interrupt_get_pending(int vector) +{ + return arm_gic_get_pending_irq(0, vector); +} + +/** + * This function clear interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_clear_pending(int vector) +{ + arm_gic_clear_pending_irq(0, vector); +} + +/** + * This function set interrupt priority value. + * @param vector: the interrupt number + * priority: the priority of interrupt to set + */ +void rt_hw_interrupt_set_priority(int vector, unsigned int priority) +{ + arm_gic_set_priority(0, vector, priority); +} + +/** + * This function get interrupt priority. + * @param vector: the interrupt number + * @return interrupt priority value + */ +unsigned int rt_hw_interrupt_get_priority(int vector) +{ + return arm_gic_get_priority(0, vector); +} + +/** + * This function set priority masking threshold. + * @param priority: priority masking threshold + */ +void rt_hw_interrupt_set_priority_mask(unsigned int priority) +{ + arm_gic_set_interface_prior_mask(0, priority); +} + +/** + * This function get priority masking threshold. + * @param none + * @return priority masking threshold + */ +unsigned int rt_hw_interrupt_get_priority_mask(void) +{ + return arm_gic_get_interface_prior_mask(0); +} + +/** + * This function set priority grouping field split point. + * @param bits: priority grouping field split point + * @return 0: success; -1: failed + */ +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits) +{ + int status; + + if (bits < 8) + { + arm_gic_set_binary_point(0, (7 - bits)); + status = 0; + } + else + { + status = -1; + } + + return (status); +} + +/** + * This function get priority grouping field split point. + * @param none + * @return priority grouping field split point + */ +unsigned int rt_hw_interrupt_get_prior_group_bits(void) +{ + unsigned int bp; + + bp = arm_gic_get_binary_point(0) & 0x07; + + return (7 - bp); } /** @@ -153,31 +359,13 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, #ifdef RT_USING_SMP void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) { - __DSB(); - if(cpu_mask & 0x1) - { - send_ipi_msg(0, ipi_vector); - } - if(cpu_mask & 0x2) - { - send_ipi_msg(1, ipi_vector); - } - if(cpu_mask & 0x4) - { - send_ipi_msg(2, ipi_vector); - } - if(cpu_mask & 0x8) - { - send_ipi_msg(3, ipi_vector); - } - __DSB(); + arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0); } -#endif -#ifdef RT_USING_SMP void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) { /* note: ipi_vector maybe different with irq_vector */ rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); } #endif + diff --git a/libcpu/aarch64/common/interrupt.h b/libcpu/aarch64/common/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..1c4199c61bd197a475cf10c95e27e12a80908d52 --- /dev/null +++ b/libcpu/aarch64/common/interrupt.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ +#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ + +void rt_hw_vector_init(void); + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +int rt_hw_interrupt_get_irq(void); +void rt_hw_interrupt_ack(int vector); + +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask); +unsigned int rt_hw_interrupt_get_target_cpus(int vector); + +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode); +unsigned int rt_hw_interrupt_get_triger_mode(int vector); + +void rt_hw_interrupt_set_pending(int vector); +unsigned int rt_hw_interrupt_get_pending(int vector); +void rt_hw_interrupt_clear_pending(int vector); + +void rt_hw_interrupt_set_priority(int vector, unsigned int priority); +unsigned int rt_hw_interrupt_get_priority(int vector); + +void rt_hw_interrupt_set_priority_mask(unsigned int priority); +unsigned int rt_hw_interrupt_get_priority_mask(void); + +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits); +unsigned int rt_hw_interrupt_get_prior_group_bits(void); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask); +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); +#endif + +#endif + diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c index b799143084ccb58cd66899212ff8a2effb56d225..623bd6a276b0bd1aa59fba922686b8bf746c3706 100644 --- a/libcpu/aarch64/common/mmu.c +++ b/libcpu/aarch64/common/mmu.c @@ -1,47 +1,60 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-02-20 bigmagic first version + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 */ -#include -#include -#include - -#define TTBR_CNP 1 - -typedef unsigned long int uint64_t; -static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096))); - -#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) +#include +#include +#include -#define PMD_TYPE_SECT (1 << 0) +#include "mmu.h" -#define PMD_TYPE_TABLE (3 << 0) +#ifdef RT_USING_USERSPACE +#include +#endif -#define PTE_TYPE_PAGE (3 << 0) +#define MMU_LEVEL_MASK 0x1ffUL +#define MMU_LEVEL_SHIFT 9 +#define MMU_ADDRESS_BITS 39 +#define MMU_ADDRESS_MASK 0x0000fffffffff000UL +#define MMU_ATTRIB_MASK 0xfff0000000000ffcUL -#define BITS_PER_VA 39 +#define MMU_TYPE_MASK 3UL +#define MMU_TYPE_USED 1UL +#define MMU_TYPE_BLOCK 1UL +#define MMU_TYPE_TABLE 3UL +#define MMU_TYPE_PAGE 3UL -/* Granule size of 4KB is being used */ -#define GRANULE_SIZE_SHIFT 12 -#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT) -#define XLAT_ADDR_MASK ((1UL << BITS_PER_VA) - GRANULE_SIZE) +#define MMU_TBL_BLOCK_2M_LEVEL 2 +#define MMU_TBL_PAGE_4k_LEVEL 3 +#define MMU_TBL_LEVEL_NR 4 -#define PMD_TYPE_MASK (3 << 0) +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void *v_addr); -int free_idx = 1; +struct page_table +{ + unsigned long page[512]; +}; -void __asm_invalidate_icache_all(void); -void __asm_flush_dcache_all(void); -int __asm_flush_l3_cache(void); -void __asm_flush_dcache_range(unsigned long long start, unsigned long long end); -void __asm_invalidate_dcache_all(void); -void __asm_invalidate_icache_all(void); +static struct page_table *__init_page_array; +static unsigned long __page_off = 0UL; +unsigned long get_free_page(void) +{ + if (!__init_page_array) + { + unsigned long temp_page_start; + asm volatile("mov %0, sp":"=r"(temp_page_start)); + __init_page_array = (struct page_table *)(temp_page_start & ~(ARCH_SECTION_MASK)); + __page_off = 2; /* 0, 1 for ttbr0, ttrb1 */ + } + __page_off++; + return (unsigned long)(__init_page_array[__page_off - 1].page); +} void mmu_memset(char *dst, char v, size_t len) { @@ -51,148 +64,292 @@ void mmu_memset(char *dst, char v, size_t len) } } -static unsigned long __page_off = 0; -static unsigned long get_free_page(void) +static int _map_single_page_2M(unsigned long *lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) { - __page_off += 512; - return (unsigned long)(main_tbl + __page_off); -} + int level; + unsigned long *cur_lv_tbl = lv0_tbl; + unsigned long page; + unsigned long off; + int level_shift = MMU_ADDRESS_BITS; + if (va & ARCH_SECTION_MASK) + { + return MMU_MAP_ERROR_VANOTALIGN; + } + if (pa & ARCH_SECTION_MASK) + { + return MMU_MAP_ERROR_PANOTALIGN; + } + for (level = 0; level < MMU_TBL_BLOCK_2M_LEVEL; level++) + { + off = (va >> level_shift); + off &= MMU_LEVEL_MASK; + if (!(cur_lv_tbl[off] & MMU_TYPE_USED)) + { + page = get_free_page(); + if (!page) + { + return MMU_MAP_ERROR_NOPAGE; + } + mmu_memset((char *)page, 0, ARCH_PAGE_SIZE); + cur_lv_tbl[off] = page | MMU_TYPE_TABLE; + } + page = cur_lv_tbl[off]; + if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK) + { + /* is block! error! */ + return MMU_MAP_ERROR_CONFLICT; + } + cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK); + level_shift -= MMU_LEVEL_SHIFT; + } + attr &= MMU_ATTRIB_MASK; + pa |= (attr | MMU_TYPE_BLOCK); /* block */ + off = (va >> ARCH_SECTION_SHIFT); + off &= MMU_LEVEL_MASK; + cur_lv_tbl[off] = pa; + return 0; +} -static inline unsigned int get_sctlr(void) +int armv8_init_map_2M(unsigned long *lv0_tbl, unsigned long va, unsigned long pa, unsigned long count, unsigned long attr) { - unsigned int val; - asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); - return val; + unsigned long i; + int ret; + + if (va & ARCH_SECTION_MASK) + { + return -1; + } + if (pa & ARCH_SECTION_MASK) + { + return -1; + } + for (i = 0; i < count; i++) + { + ret = _map_single_page_2M(lv0_tbl, va, pa, attr); + va += ARCH_SECTION_SIZE; + pa += ARCH_SECTION_SIZE; + if (ret != 0) + { + return ret; + } + } + return 0; } -static inline void set_sctlr(unsigned int val) +static int _kenrel_map_2M(unsigned long *lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) { - asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); - asm volatile("isb"); + int level; + unsigned long *cur_lv_tbl = lv0_tbl; + unsigned long page; + unsigned long off; + int level_shift = MMU_ADDRESS_BITS; + + if (va & ARCH_SECTION_MASK) + { + return MMU_MAP_ERROR_VANOTALIGN; + } + if (pa & ARCH_SECTION_MASK) + { + return MMU_MAP_ERROR_PANOTALIGN; + } + for (level = 0; level < MMU_TBL_BLOCK_2M_LEVEL; level++) + { + off = (va >> level_shift); + off &= MMU_LEVEL_MASK; + if (!(cur_lv_tbl[off] & MMU_TYPE_USED)) + { + page = (unsigned long)rt_pages_alloc(0); + if (!page) + { + return MMU_MAP_ERROR_NOPAGE; + } + rt_memset((char *)page, 0, ARCH_PAGE_SIZE); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)page, ARCH_PAGE_SIZE); + cur_lv_tbl[off] = (page + PV_OFFSET) | MMU_TYPE_TABLE; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cur_lv_tbl + off, sizeof(void *)); + } + else + { + page = cur_lv_tbl[off]; + page &= MMU_ADDRESS_MASK; + /* page to va */ + page -= PV_OFFSET; + rt_page_ref_inc((void *)page, 0); + } + page = cur_lv_tbl[off]; + if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK) + { + /* is block! error! */ + return MMU_MAP_ERROR_CONFLICT; + } + cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK); + cur_lv_tbl = (unsigned long *)((unsigned long)cur_lv_tbl - PV_OFFSET); + level_shift -= MMU_LEVEL_SHIFT; + } + attr &= MMU_ATTRIB_MASK; + pa |= (attr | MMU_TYPE_BLOCK); /* block */ + off = (va >> ARCH_SECTION_SHIFT); + off &= MMU_LEVEL_MASK; + cur_lv_tbl[off] = pa; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cur_lv_tbl + off, sizeof(void *)); + + return 0; } -void mmu_init(void) +struct mmu_level_info { - unsigned long val64; - unsigned long val32; + unsigned long *pos; + void *page; +}; - val64 = 0x007f6eUL; - __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64)); - __asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64)); - - //TCR_EL1 - val32 = (16UL << 0)//48bit - | (0x0UL << 6) - | (0x0UL << 7) - | (0x3UL << 8) - | (0x3UL << 10)//Inner Shareable - | (0x2UL << 12) - | (0x0UL << 14)//4K - | (0x0UL << 16) - | (0x0UL << 22) - | (0x1UL << 23) - | (0x2UL << 30) - | (0x1UL << 32) - | (0x0UL << 35) - | (0x0UL << 36) - | (0x0UL << 37) - | (0x0UL << 38); - __asm__ volatile("msr TCR_EL1, %0\n"::"r"(val32)); - __asm__ volatile("mrs %0, TCR_EL1\n":"=r"(val32)); - - __asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl)); - __asm__ volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64)); - - mmu_memset((char *)main_tbl, 0, 4096); -} - -void mmu_enable(void) +static void _kenrel_unmap_4K(unsigned long *lv0_tbl, void *v_addr) { - unsigned long val64; - unsigned long val32; - - __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64)); - val64 &= ~0x1000; //disable I - __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64)); + int level; + unsigned long va = (unsigned long)v_addr; + unsigned long *cur_lv_tbl = lv0_tbl; + unsigned long page; + unsigned long off; + struct mmu_level_info level_info[4]; + int ref; + int level_shift = MMU_ADDRESS_BITS; + unsigned long *pos; - __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n"); - __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n"); + rt_memset(level_info, 0, sizeof level_info); + for (level = 0; level < MMU_TBL_LEVEL_NR; level++) + { + off = (va >> level_shift); + off &= MMU_LEVEL_MASK; + page = cur_lv_tbl[off]; + if (!(page & MMU_TYPE_USED)) + { + break; + } + if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK) + { + break; + } + level_info[level].pos = cur_lv_tbl + off; + cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK); + cur_lv_tbl = (unsigned long *)((unsigned long)cur_lv_tbl - PV_OFFSET); + level_info[level].page = cur_lv_tbl; + level_shift -= MMU_LEVEL_SHIFT; + } - //SCTLR_EL1, turn on mmu - __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32)); - val32 |= 0x1005; //enable mmu, I C M - __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32)); - rt_hw_icache_enable(); - rt_hw_dcache_enable(); + level = MMU_TBL_PAGE_4k_LEVEL; + pos = level_info[level].pos; + if (pos) + { + *pos = (unsigned long)RT_NULL; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, pos, sizeof(void *)); + } + level--; + while (level >= 0) + { + pos = level_info[level].pos; + if (pos) + { + void *cur_page = level_info[level].page; + ref = rt_page_ref_get(cur_page, 0); + if (ref == 1) + { + *pos = (unsigned long)RT_NULL; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, pos, sizeof(void *)); + } + rt_pages_free(cur_page, 0); + } + level--; + } + asm volatile("tlbi vae1, %0\ndsb sy"::"r"(v_addr):"memory"); + return; } -static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) +static int _kenrel_map_4K(unsigned long *lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) { + int ret = 0; int level; - unsigned long* cur_lv_tbl = lv0_tbl; + unsigned long *cur_lv_tbl = lv0_tbl; unsigned long page; unsigned long off; - int level_shift = 39; + int level_shift = MMU_ADDRESS_BITS; - if (va & (0x200000UL - 1)) + if (va & ARCH_PAGE_MASK) { return MMU_MAP_ERROR_VANOTALIGN; } - if (pa & (0x200000UL - 1)) + if (pa & ARCH_PAGE_MASK) { return MMU_MAP_ERROR_PANOTALIGN; } - for (level = 0; level < 2; level++) + for (level = 0; level < MMU_TBL_PAGE_4k_LEVEL; level++) { off = (va >> level_shift); off &= MMU_LEVEL_MASK; - if ((cur_lv_tbl[off] & 1) == 0) + if (!(cur_lv_tbl[off] & MMU_TYPE_USED)) { - page = get_free_page(); - if (!page) + page = (unsigned long)rt_pages_alloc(0); + if (!page) { - return MMU_MAP_ERROR_NOPAGE; + ret = MMU_MAP_ERROR_NOPAGE; + goto err; } - mmu_memset((char *)page, 0, 4096); - cur_lv_tbl[off] = page | 0x3UL; + rt_memset((void *)page, 0, ARCH_PAGE_SIZE); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)page, ARCH_PAGE_SIZE); + cur_lv_tbl[off] = (page + PV_OFFSET) | MMU_TYPE_TABLE; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cur_lv_tbl + off, sizeof(void *)); + } + else + { + page = cur_lv_tbl[off]; + page &= MMU_ADDRESS_MASK; + /* page to va */ + page -= PV_OFFSET; + rt_page_ref_inc((void *)page, 0); } page = cur_lv_tbl[off]; - if (!(page & 0x2)) + if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK) { - //is block! error! - return MMU_MAP_ERROR_CONFLICT; + /* is block! error! */ + ret = MMU_MAP_ERROR_CONFLICT; + goto err; } - cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL); - level_shift -= 9; + cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK); + cur_lv_tbl = (unsigned long *)((unsigned long)cur_lv_tbl - PV_OFFSET); + level_shift -= MMU_LEVEL_SHIFT; } - attr &= 0xfff0000000000ffcUL; - pa |= (attr | 0x1UL); //block - off = (va >> 21); + /* now is level page */ + attr &= MMU_ATTRIB_MASK; + pa |= (attr | MMU_TYPE_PAGE); /* page */ + off = (va >> ARCH_PAGE_SHIFT); off &= MMU_LEVEL_MASK; - cur_lv_tbl[off] = pa; - return 0; + cur_lv_tbl[off] = pa; /* page */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cur_lv_tbl + off, sizeof(void *)); + return ret; +err: + _kenrel_unmap_4K(lv0_tbl, (void *)va); + return ret; } -int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr) +int kernel_map_fixed(unsigned long *lv0_tbl, unsigned long va, unsigned long pa, unsigned long count, unsigned long attr) { - int i; + unsigned long i; int ret; + unsigned long _attr = MMU_MAP_CUSTOM(MMU_AP_KAUN, attr); - if (va & (0x200000 - 1)) + if (va & ARCH_SECTION_MASK) { return -1; } - if (pa & (0x200000 - 1)) + if (pa & ARCH_SECTION_MASK) { return -1; } for (i = 0; i < count; i++) { - ret = map_single_page_2M((unsigned long *)main_tbl, va, pa, attr); - va += 0x200000; - pa += 0x200000; + ret = _kenrel_map_2M(lv0_tbl, va, pa, _attr); + va += ARCH_SECTION_SIZE; + pa += ARCH_SECTION_SIZE; if (ret != 0) { return ret; @@ -201,167 +358,575 @@ int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long at return 0; } -static void set_table(uint64_t *pt, uint64_t *table_addr) +/************ setting el1 mmu register************** + MAIR_EL1 + index 0 : memory outer writeback, write/read alloc + index 1 : memory nocache + index 2 : device nGnRnE + *****************************************************/ +void mmu_tcr_init(void) +{ + unsigned long val64; + + val64 = 0x00447fUL; + __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64)); + + /* TCR_EL1 */ + val64 = (16UL << 0) /* t0sz 48bit */ + | (0x0UL << 6) /* reserved */ + | (0x0UL << 7) /* epd0 */ + | (0x3UL << 8) /* t0 wb cacheable */ + | (0x3UL << 10) /* inner shareable */ + | (0x2UL << 12) /* t0 outer shareable */ + | (0x0UL << 14) /* t0 4K */ + | (16UL << 16) /* t1sz 48bit */ + | (0x0UL << 22) /* define asid use ttbr0.asid */ + | (0x0UL << 23) /* epd1 */ + | (0x3UL << 24) /* t1 inner wb cacheable */ + | (0x3UL << 26) /* t1 outer wb cacheable */ + | (0x2UL << 28) /* t1 outer shareable */ + | (0x2UL << 30) /* t1 4k */ + | (0x1UL << 32) /* 001b 64GB PA */ + | (0x0UL << 35) /* reserved */ + | (0x1UL << 36) /* as: 0:8bit 1:16bit */ + | (0x0UL << 37) /* tbi0 */ + | (0x0UL << 38); /* tbi1 */ + __asm__ volatile("msr TCR_EL1, %0\n"::"r"(val64)); +} + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) { - uint64_t val; - val = (0x3UL | (uint64_t)table_addr); - *pt = val; } -void mmu_memset2(unsigned char *dst, char v, int len) +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) { - while (len--) +} + +volatile unsigned long MMUTable[512] __attribute__((aligned(4 * 1024))); +void rt_hw_mmu_setmtt(unsigned long vaddrStart, + unsigned long vaddrEnd, + unsigned long paddrStart, + unsigned long attr) +{ + unsigned long count; + + if (vaddrStart & ARCH_SECTION_MASK) { - *dst++ = v; + return; + } + if (paddrStart & ARCH_SECTION_MASK) + { + return; + } + if (vaddrStart > vaddrEnd) + { + return; + } + count = vaddrEnd + 1; + if (count & ARCH_SECTION_MASK) + { + return; } + count -= vaddrStart; + if (count == 0) + { + return; + } + count >>= ARCH_SECTION_SHIFT; + kernel_map_fixed((unsigned long *)MMUTable, vaddrStart, paddrStart, count, attr); } -static uint64_t *create_table(void) +void kernel_mmu_switch(unsigned long tbl) { - uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE; - /* Mark all entries as invalid */ - mmu_memset2((unsigned char *)new_table, 0, 4096); - free_idx++; - return new_table; + tbl += PV_OFFSET; + __asm__ volatile("msr TTBR1_EL1, %0\n dsb sy\nisb"::"r"(tbl):"memory"); + __asm__ volatile("tlbi vmalle1\n dsb sy\nisb":::"memory"); + __asm__ volatile("ic ialluis\n dsb sy\nisb":::"memory"); } -static int pte_type(uint64_t *pte) +void rt_hw_mmu_setup(struct mem_desc *mdesc, int desc_nr) { - return *pte & PMD_TYPE_MASK; + /* set page table */ + for (; desc_nr > 0; desc_nr--) + { + rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, + mdesc->paddr_start, mdesc->attr); + mdesc++; + } + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)MMUTable, sizeof MMUTable); + kernel_mmu_switch((unsigned long)MMUTable); } -static int level2shift(int level) +/** + * This function will initialize rt_mmu_info structure. + * + * @param mmu_info rt_mmu_info structure + * @param v_address virtual address + * @param size map size + * @param vtable mmu table + * @param pv_off pv offset in kernel space + * + * @return 0 on successful and -1 for fail + */ +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void *v_address, size_t size, size_t *vtable, size_t pv_off) { - /* Page is 12 bits wide, every level translates 9 bits */ - return (12 + 9 * (3 - level)); + rt_base_t level; + size_t va_s, va_e; + + if (!mmu_info || !vtable) + { + return -1; + } + + va_s = (size_t)v_address; + va_e = (size_t)v_address + size - 1; + + if (va_e < va_s) + { + return -1; + } + + va_s >>= ARCH_SECTION_SHIFT; + va_e >>= ARCH_SECTION_SHIFT; + + if (va_s == 0) + { + return -1; + } + + level = rt_hw_interrupt_disable(); + + mmu_info->vtable = vtable; + mmu_info->vstart = va_s; + mmu_info->vend = va_e; + mmu_info->pv_off = pv_off; + + rt_hw_interrupt_enable(level); + + return 0; } -static uint64_t *get_level_table(uint64_t *pte) +int rt_hw_mmu_ioremap_init(rt_mmu_info *mmu_info, void *v_address, size_t size) { - uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK); - - if (pte_type(pte) != PMD_TYPE_TABLE) + return 0; +} + +static size_t find_vaddr(rt_mmu_info *mmu_info, int pages) +{ + size_t loop_pages; + size_t va; + size_t find_va = 0; + int n = 0; + size_t i; + + if (!pages) + { + return 0; + } + + if (!mmu_info) { - table = create_table(); - set_table(pte, table); + return 0; } - return table; + + loop_pages = mmu_info->vend - mmu_info->vstart + 1; + loop_pages <<= (ARCH_SECTION_SHIFT - ARCH_PAGE_SHIFT); + va = mmu_info->vstart; + va <<= ARCH_SECTION_SHIFT; + for (i = 0; i < loop_pages; i++, va += ARCH_PAGE_SIZE) + { + if (_rt_hw_mmu_v2p(mmu_info, (void *)va)) + { + n = 0; + find_va = 0; + continue; + } + if (!find_va) + { + find_va = va; + } + n++; + if (n >= pages) + { + return find_va; + } + } + return 0; } -static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr) +#ifdef RT_USING_USERSPACE +static int check_vaddr(rt_mmu_info *mmu_info, void *va, int pages) { - uint64_t block_size = 0; - uint64_t block_shift = 0; - uint64_t *pte; - uint64_t idx = 0; - uint64_t addr = 0; - uint64_t *table = 0; - int level = 0; + size_t loop_va; + + if (!pages) + { + return -1; + } + + if (!mmu_info) + { + return -1; + } + + loop_va = ((size_t)va >> ARCH_SECTION_SHIFT); + if (loop_va < mmu_info->vstart || loop_va > mmu_info->vend) + { + return -1; + } + loop_va += ((pages << ARCH_PAGE_SHIFT) >> ARCH_SECTION_SHIFT); + if (loop_va < mmu_info->vstart || loop_va > mmu_info->vend + 1) + { + return -1; + } - addr = virt; - while (size) + loop_va = (size_t)va & ~ARCH_PAGE_MASK; + while (pages--) { - table = &main_tbl[0]; - for (level = 0; level < 4; level++) + if (_rt_hw_mmu_v2p(mmu_info, (void *)loop_va)) { - block_shift = level2shift(level); - idx = addr >> block_shift; - idx = idx%512; - block_size = (uint64_t)(1L << block_shift); - pte = table + idx; + return -1; + } + loop_va += ARCH_PAGE_SIZE; + } + return 0; +} +#endif + +static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void *v_addr, size_t npages) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + + if (!mmu_info || !mmu_info->vtable) + { + return; + } + + while (npages--) + { + _kenrel_unmap_4K(mmu_info->vtable, (void *)loop_va); + loop_va += ARCH_PAGE_SIZE; + } +} + +static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void *p_addr, size_t npages, size_t attr) +{ + int ret = -1; + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa = (size_t)p_addr & ~ARCH_PAGE_MASK; + size_t unmap_va = loop_va; - if (size >= block_size && IS_ALIGNED(addr, block_size)) + if (mmu_info) + { + while (npages--) + { + ret = _kenrel_map_4K(mmu_info->vtable, loop_va, loop_pa, attr); + if (ret != 0) { - attr &= 0xfff0000000000ffcUL; - if(level != 3) + /* error, undo map */ + while (unmap_va != loop_va) { - *pte = phys | (attr | 0x1UL); + _kenrel_unmap_4K(mmu_info->vtable, (void *)unmap_va); + unmap_va += ARCH_PAGE_SIZE; } - else - { - *pte = phys | (attr | 0x3UL); - } - addr += block_size; - phys += block_size; - size -= block_size; break; } - table = get_level_table(pte); + loop_va += ARCH_PAGE_SIZE; + loop_pa += ARCH_PAGE_SIZE; } } + return ret; } -void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr) +static void rt_hw_cpu_tlb_invalidate(void) { - map_region(va, pa, size, attr); + __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n"); } -void rt_hw_dcache_enable(void) +#ifdef RT_USING_USERSPACE +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void *p_addr, size_t size, size_t attr) { - if (!(get_sctlr() & CR_M)) + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + if (!size) { - rt_kprintf("please init mmu!\n"); + return 0; + } + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + if (v_addr) + { + vaddr = (size_t)v_addr; + pa_s = (size_t)p_addr; + if ((vaddr & ARCH_PAGE_MASK) != (pa_s & ARCH_PAGE_MASK)) + { + return 0; + } + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void *)vaddr, pages) != 0) + { + return 0; + } } else { - set_sctlr(get_sctlr() | CR_C); + vaddr = find_vaddr(mmu_info, pages); + } + if (vaddr) + { + ret = __rt_hw_mmu_map(mmu_info, (void *)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void *)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#else +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + vaddr = find_vaddr(mmu_info, pages); + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#endif + +#ifdef RT_USING_USERSPACE +static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t npages, size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa; + + if (!mmu_info) + { + return -1; + } + + while (npages--) + { + loop_pa = (size_t)rt_pages_alloc(0); + if (!loop_pa) + { + goto err; + } + loop_pa += mmu_info->pv_off; + _kenrel_map_4K(mmu_info->vtable, loop_va, loop_pa, attr); + loop_va += ARCH_PAGE_SIZE; + } + return 0; +err: + { + /* error, unmap and quit */ + int i; + void *va, *pa; + + va = (void *)((size_t)v_addr & ~ARCH_PAGE_MASK); + for (i = 0; i < npages; i++) + { + pa = rt_hw_mmu_v2p(mmu_info, va); + pa = (void *)((char *)pa - mmu_info->pv_off); + rt_pages_free(pa, 0); + va = (void *)((char *)va + ARCH_PAGE_SIZE); + } + + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; } } -void rt_hw_dcache_flush_all(void) +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) { + size_t vaddr; + size_t offset; + int pages; int ret; - __asm_flush_dcache_all(); - ret = __asm_flush_l3_cache(); - if (ret) + if (!size) { - rt_kprintf("flushing dcache returns 0x%x\n", ret); + return 0; + } + offset = (size_t)v_addr & ARCH_PAGE_MASK; + size += (offset + ARCH_PAGE_SIZE - 1); + pages = (size >> ARCH_PAGE_SHIFT); + if (v_addr) + { + vaddr = (size_t)v_addr; + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void *)vaddr, pages) != 0) + { + return 0; + } } else { - rt_kprintf("flushing dcache successfully.\n"); + vaddr = find_vaddr(mmu_info, pages); } + if (vaddr) + { + ret = __rt_hw_mmu_map_auto(mmu_info, (void *)vaddr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void *)((char *)vaddr + offset); + } + } + return 0; } +#endif -void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size) +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void *v_addr, size_t size) { - __asm_flush_dcache_range(start_addr, start_addr + size); + size_t va_s, va_e; + int pages; + + va_s = (size_t)v_addr; + va_e = (size_t)v_addr + size - 1; + va_s >>= ARCH_PAGE_SHIFT; + va_e >>= ARCH_PAGE_SHIFT; + pages = va_e - va_s + 1; + __rt_hw_mmu_unmap(mmu_info, v_addr, pages); + rt_hw_cpu_tlb_invalidate(); } -void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size) + +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void *p_addr, size_t size, size_t attr) { - __asm_flush_dcache_range(start_addr, start_addr + size); + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map(mmu_info, v_addr, p_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; } -void rt_hw_dcache_invalidate_all(void) +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) { - __asm_invalidate_dcache_all(); + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map_auto(mmu_info, v_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; } +#endif -void rt_hw_dcache_disable(void) +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void *v_addr, size_t size) { - /* if cache isn't enabled no need to disable */ - if(!(get_sctlr() & CR_C)) - { - rt_kprintf("need enable cache!\n"); - return; - } - set_sctlr(get_sctlr() & ~CR_C); + rt_base_t level; + + level = rt_hw_interrupt_disable(); + _rt_hw_mmu_unmap(mmu_info, v_addr, size); + rt_hw_interrupt_enable(level); } -//icache -void rt_hw_icache_enable(void) +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void *v_addr) { - __asm_invalidate_icache_all(); - set_sctlr(get_sctlr() | CR_I); + int level; + unsigned long va = (unsigned long)v_addr; + unsigned long pa; + unsigned long *cur_lv_tbl; + unsigned long page; + unsigned long off; + unsigned long off_addr; + int level_shift = MMU_ADDRESS_BITS; + + if (!mmu_info) + { + return (void *)0; + } + cur_lv_tbl = mmu_info->vtable; + for (level = 0; level < MMU_TBL_PAGE_4k_LEVEL; level++) + { + off = (va >> level_shift); + off &= MMU_LEVEL_MASK; + if (!(cur_lv_tbl[off] & MMU_TYPE_USED)) + { + return (void *)0; + } + page = cur_lv_tbl[off]; + if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK) + { + off_addr = va & ((1UL << level_shift) - 1); + pa = (page & MMU_ADDRESS_MASK); + pa += off_addr; + return (void *)pa; + } + cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK); + cur_lv_tbl = (unsigned long *)((unsigned long)cur_lv_tbl - PV_OFFSET); + level_shift -= MMU_LEVEL_SHIFT; + } + /* now is level MMU_TBL_PAGE_4k_LEVEL */ + off = (va >> ARCH_PAGE_SHIFT); + off &= MMU_LEVEL_MASK; + page = cur_lv_tbl[off]; + if (!(page & MMU_TYPE_USED)) + { + return (void *)0; + } + pa = (page & MMU_ADDRESS_MASK); + pa += (va & ARCH_PAGE_MASK); + return (void *)pa; } -void rt_hw_icache_invalidate_all(void) +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void *v_addr) { - __asm_invalidate_icache_all(); + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_v2p(mmu_info, v_addr); + rt_hw_interrupt_enable(level); + return ret; } -void rt_hw_icache_disable(void) +#ifdef RT_USING_USERSPACE +void rt_hw_mmu_setup_early(unsigned long *tbl0, unsigned long *tbl1, unsigned long size, unsigned long pv_off) { - set_sctlr(get_sctlr() & ~CR_I); -} \ No newline at end of file + int ret; + unsigned long va = KERNEL_VADDR_START; + unsigned long count = (size + ARCH_SECTION_MASK) >> ARCH_SECTION_SHIFT; + unsigned long normal_attr = MMU_MAP_CUSTOM(MMU_AP_KAUN, NORMAL_MEM); + + /* clean the first two pages */ + mmu_memset((char *)tbl0, 0, ARCH_PAGE_SIZE); + mmu_memset((char *)tbl1, 0, ARCH_PAGE_SIZE); + + ret = armv8_init_map_2M(tbl1, va, va + pv_off, count, normal_attr); + if (ret != 0) + { + while (1); + } + ret = armv8_init_map_2M(tbl0, va + pv_off, va + pv_off, count, normal_attr); + if (ret != 0) + { + while (1); + } +} +#endif diff --git a/libcpu/aarch64/common/mmu.h b/libcpu/aarch64/common/mmu.h index 6a66472c790e0a7505e1d07a49aed8491980a457..abc159e521ca2c31a38ee7fb142504db2d0da2da 100644 --- a/libcpu/aarch64/common/mmu.h +++ b/libcpu/aarch64/common/mmu.h @@ -1,78 +1,136 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-02-20 bigmagic first version + * Date Author Notes + * 2021-05-12 RT-Thread the first version */ +#ifndef __MMU_H_ +#define __MMU_H_ -#ifndef __MMU_H__ -#define __MMU_H__ +#include -/* - * CR1 bits (CP#15 CR1) - */ -#define CR_M (1 << 0) /* MMU enable */ -#define CR_A (1 << 1) /* Alignment abort enable */ -#define CR_C (1 << 2) /* Dcache enable */ -#define CR_W (1 << 3) /* Write buffer enable */ -#define CR_P (1 << 4) /* 32-bit exception handler */ -#define CR_D (1 << 5) /* 32-bit data address range */ -#define CR_L (1 << 6) /* Implementation defined */ -#define CR_B (1 << 7) /* Big endian */ -#define CR_S (1 << 8) /* System MMU protection */ -#define CR_R (1 << 9) /* ROM MMU protection */ -#define CR_F (1 << 10) /* Implementation defined */ -#define CR_Z (1 << 11) /* Implementation defined */ -#define CR_I (1 << 12) /* Icache enable */ -#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ -#define CR_RR (1 << 14) /* Round Robin cache replacement */ -#define CR_L4 (1 << 15) /* LDR pc can set T bit */ -#define CR_DT (1 << 16) -#define CR_IT (1 << 18) -#define CR_ST (1 << 19) -#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ -#define CR_U (1 << 22) /* Unaligned access operation */ -#define CR_XP (1 << 23) /* Extended page tables */ -#define CR_VE (1 << 24) /* Vectored interrupts */ -#define CR_EE (1 << 25) /* Exception (Big) Endian */ -#define CR_TRE (1 << 28) /* TEX remap enable */ -#define CR_AFE (1 << 29) /* Access flag enable */ -#define CR_TE (1 << 30) /* Thumb exception enable */ +/* normal memory wra mapping type */ +#define NORMAL_MEM 0 +/* normal nocache memory mapping type */ +#define NORMAL_NOCACHE_MEM 1 +/* device mapping type */ +#define DEVICE_MEM 2 -#define MMU_LEVEL_MASK 0x1ffUL -#define MMU_MAP_ERROR_VANOTALIGN -1 -#define MMU_MAP_ERROR_PANOTALIGN -2 -#define MMU_MAP_ERROR_NOPAGE -3 -#define MMU_MAP_ERROR_CONFLICT -4 +struct mem_desc +{ + unsigned long vaddr_start; + unsigned long vaddr_end; + unsigned long paddr_start; + unsigned long attr; +}; -#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2)) -#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2)) +#define MMU_AF_SHIFT 10 +#define MMU_SHARED_SHIFT 8 +#define MMU_AP_SHIFT 6 +#define MMU_MA_SHIFT 2 -#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) +#define MMU_AP_KAUN 0UL /* kernel r/w, user none */ +#define MMU_AP_KAUA 1UL /* kernel r/w, user r/w */ +#define MMU_AP_KRUN 2UL /* kernel r, user none */ +#define MMU_AP_KRUR 3UL /* kernel r, user r */ -void mmu_init(void); +#define MMU_MAP_K_RO (\ + (0x1UL << MMU_AF_SHIFT) |\ + (0x2UL << MMU_SHARED_SHIFT) |\ + (MMU_AP_KRUN << MMU_AP_SHIFT) |\ + (NORMAL_MEM << MMU_MA_SHIFT)\ + ) +#define MMU_MAP_K_RWCB (\ + (0x1UL << MMU_AF_SHIFT) |\ + (0x2UL << MMU_SHARED_SHIFT) |\ + (MMU_AP_KAUN << MMU_AP_SHIFT) |\ + (NORMAL_MEM << MMU_MA_SHIFT)\ + ) +#define MMU_MAP_K_RW (\ + (0x1UL << MMU_AF_SHIFT) |\ + (0x2UL << MMU_SHARED_SHIFT) |\ + (MMU_AP_KAUN << MMU_AP_SHIFT) |\ + (NORMAL_NOCACHE_MEM << MMU_MA_SHIFT)\ + ) +#define MMU_MAP_K_DEVICE (\ + (0x1UL << MMU_AF_SHIFT) |\ + (0x2UL << MMU_SHARED_SHIFT) |\ + (MMU_AP_KAUN << MMU_AP_SHIFT) |\ + (DEVICE_MEM << MMU_MA_SHIFT)\ + ) +#define MMU_MAP_U_RO (\ + (0x1UL << MMU_AF_SHIFT) |\ + (0x2UL << MMU_SHARED_SHIFT) |\ + (MMU_AP_KRUR << MMU_AP_SHIFT) |\ + (NORMAL_NOCACHE_MEM << MMU_MA_SHIFT)\ + ) +#define MMU_MAP_U_RWCB (\ + (0x1UL << MMU_AF_SHIFT) |\ + (0x2UL << MMU_SHARED_SHIFT) |\ + (MMU_AP_KAUA << MMU_AP_SHIFT) |\ + (NORMAL_MEM << MMU_MA_SHIFT)\ + ) +#define MMU_MAP_U_RW (\ + (0x1UL << MMU_AF_SHIFT) |\ + (0x2UL << MMU_SHARED_SHIFT) |\ + (MMU_AP_KAUA << MMU_AP_SHIFT) |\ + (NORMAL_NOCACHE_MEM << MMU_MA_SHIFT)\ + ) +#define MMU_MAP_U_DEVICE (\ + (0x1UL << MMU_AF_SHIFT) |\ + (0x2UL << MMU_SHARED_SHIFT) |\ + (MMU_AP_KAUA << MMU_AP_SHIFT) |\ + (DEVICE_MEM << MMU_MA_SHIFT)\ + ) +#define MMU_MAP_CUSTOM(ap, mtype) (\ + (0x1UL << MMU_AF_SHIFT) |\ + (0x2UL << MMU_SHARED_SHIFT) |\ + ((ap) << MMU_AP_SHIFT) |\ + ((mtype) << MMU_MA_SHIFT)\ + ) -void mmu_enable(void); +#define ARCH_SECTION_SHIFT 21 +#define ARCH_SECTION_SIZE (1 << ARCH_SECTION_SHIFT) +#define ARCH_SECTION_MASK (ARCH_SECTION_SIZE - 1) +#define ARCH_PAGE_SHIFT 12 +#define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT) +#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1) +#define ARCH_PAGE_TBL_SHIFT 12 +#define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT) +#define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1) + +#define ARCH_ADDRESS_WIDTH_BITS 64 + +#define MMU_MAP_ERROR_VANOTALIGN -1 +#define MMU_MAP_ERROR_PANOTALIGN -2 +#define MMU_MAP_ERROR_NOPAGE -3 +#define MMU_MAP_ERROR_CONFLICT -4 -int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr); +typedef struct +{ + size_t *vtable; + size_t vstart; + size_t vend; + size_t pv_off; +} rt_mmu_info; -void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr); +void rt_hw_mmu_setup_early(unsigned long *tbl0, unsigned long *tbl1, unsigned long size, unsigned long pv_off); +void rt_hw_mmu_setup(struct mem_desc *mdesc, int desc_nr); -//dcache -void rt_hw_dcache_enable(void); -void rt_hw_dcache_flush_all(void); -void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size); -void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size); -void rt_hw_dcache_invalidate_all(void); -void rt_hw_dcache_disable(void); +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off); +int rt_hw_mmu_ioremap_init(rt_mmu_info *mmu_info, void* v_address, size_t size); -//icache -void rt_hw_icache_enable(void); -void rt_hw_icache_invalidate_all(void); -void rt_hw_icache_disable(void); +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr); +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr); +#else +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr); +#endif +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size); +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr); -#endif /*__MMU_H__*/ +#endif diff --git a/libcpu/aarch64/cortex-a72/stack.c b/libcpu/aarch64/common/stack.c similarity index 43% rename from libcpu/aarch64/cortex-a72/stack.c rename to libcpu/aarch64/common/stack.c index 68222c2c67d440913a54c3e243f4898577f41172..571d39209172e63111eae534a239d5988e46a900 100644 --- a/libcpu/aarch64/cortex-a72/stack.c +++ b/libcpu/aarch64/common/stack.c @@ -1,21 +1,18 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2011-09-23 Bernard the first version - * 2011-10-05 Bernard add thumb mode + * 2021-05-12 RT-Thread init */ #include #include #include -#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0) -#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0) -#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0) +#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_ELx) /** * This function will initialize thread stack @@ -31,20 +28,52 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { rt_ubase_t *stk; - rt_ubase_t current_el; stk = (rt_ubase_t*)stack_addr; - *(--stk) = ( rt_ubase_t ) 11; /* X1 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q0 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q0 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q1 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q1 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q2 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q2 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q3 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q3 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q4 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q4 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q5 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q5 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q6 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q6 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q7 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q7 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q8 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q8 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q9 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q9 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q10 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q10 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q11 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q11 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q12 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q12 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q13 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q13 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q14 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q14 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q15 */ + *(--stk) = ( rt_ubase_t ) 0; /* Q15 */ + + *(--stk) = ( rt_ubase_t ) 1; /* X1 */ *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ - *(--stk) = ( rt_ubase_t ) 33; /* X3 */ - *(--stk) = ( rt_ubase_t ) 22; /* X2 */ - *(--stk) = ( rt_ubase_t ) 55; /* X5 */ - *(--stk) = ( rt_ubase_t ) 44; /* X4 */ - *(--stk) = ( rt_ubase_t ) 77; /* X7 */ - *(--stk) = ( rt_ubase_t ) 66; /* X6 */ - *(--stk) = ( rt_ubase_t ) 99; /* X9 */ - *(--stk) = ( rt_ubase_t ) 88; /* X8 */ + *(--stk) = ( rt_ubase_t ) 3; /* X3 */ + *(--stk) = ( rt_ubase_t ) 2; /* X2 */ + *(--stk) = ( rt_ubase_t ) 5; /* X5 */ + *(--stk) = ( rt_ubase_t ) 4; /* X4 */ + *(--stk) = ( rt_ubase_t ) 7; /* X7 */ + *(--stk) = ( rt_ubase_t ) 6; /* X6 */ + *(--stk) = ( rt_ubase_t ) 9; /* X9 */ + *(--stk) = ( rt_ubase_t ) 8; /* X8 */ *(--stk) = ( rt_ubase_t ) 11; /* X11 */ *(--stk) = ( rt_ubase_t ) 10; /* X10 */ *(--stk) = ( rt_ubase_t ) 13; /* X13 */ @@ -65,23 +94,12 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, *(--stk) = ( rt_ubase_t ) 26; /* X26 */ *(--stk) = ( rt_ubase_t ) 29; /* X29 */ *(--stk) = ( rt_ubase_t ) 28; /* X28 */ - *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = ( rt_ubase_t ) 0; /* FPSR */ + *(--stk) = ( rt_ubase_t ) 0; /* FPCR */ *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ + *(--stk) = ( rt_ubase_t ) 0; /* sp_el0 */ - current_el = rt_hw_get_current_el(); - - if(current_el == 3) - { - *(--stk) = INITIAL_SPSR_EL3; - } - else if(current_el == 2) - { - *(--stk) = INITIAL_SPSR_EL2; - } - else - { - *(--stk) = INITIAL_SPSR_EL1; - } + *(--stk) = INITIAL_SPSR_EL1; *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ diff --git a/libcpu/aarch64/common/startup_gcc.S b/libcpu/aarch64/common/startup_gcc.S index ea4268148c8f50e924cc0ff6bbccecb68bec2ab7..9674b57d5771937d44960285f9308f1b86330897 100644 --- a/libcpu/aarch64/common/startup_gcc.S +++ b/libcpu/aarch64/common/startup_gcc.S @@ -11,3 +11,8 @@ .section ".start", "ax" Reset_Handler: nop + +.text +.weak SVC_Handler +SVC_Handler: + ret diff --git a/libcpu/aarch64/common/trap.c b/libcpu/aarch64/common/trap.c new file mode 100644 index 0000000000000000000000000000000000000000..e8e7323de48083a14514d38a1d81d15bcab4454e --- /dev/null +++ b/libcpu/aarch64/common/trap.c @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#include +#include +#include + +#include +#include "interrupt.h" + +void rt_unwind(struct rt_hw_exp_stack *regs, int pc_adj) +{ +} + +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +#ifdef RT_USING_LWP +#include +#include + +#ifdef LWP_USING_CORE_DUMP +#include +#endif + +#ifdef RT_USING_GDBSERVER +#include +#include + +gdb_thread_info wp_thread_info = { + RT_NULL, + GDB_NOTIFIY_NR, + 0, RT_NULL, 0 +}; + +static int check_debug_event(struct rt_hw_exp_stack *regs, unsigned long esr) +{ + uint32_t elx = regs->cpsr & 0x1fUL; + unsigned char ec; + + ec = (unsigned char)((esr >> 26) & 0x3fU); + if (elx == 0x00) /* is EL0 */ + { + struct rt_channel_msg msg; + gdb_thread_info thread_info; + int ret; + + if (ec == 0x3c || ec == 0x30 /* breakpoint event */ + || ec == 0x32) /* step event */ + { + if (wp_thread_info.notify_type == GDB_NOTIFIY_WATCHPOINT) + { + thread_info.watch_addr = (uint32_t *)regs->pc; + thread_info.rw = wp_thread_info.rw; + thread_info.notify_type = GDB_NOTIFIY_WATCHPOINT; + wp_thread_info.notify_type = GDB_NOTIFIY_NR; + ret = 2; + } + else + { + /* is breakpoint event */ + do { + struct rt_lwp *gdb_lwp = gdb_get_dbg_lwp(); + struct rt_lwp *lwp; + + if (!gdb_lwp) + { + break; + } + lwp = lwp_self(); + if (lwp == gdb_lwp) + { + break; + } + *(uint32_t *)regs->pc = lwp->bak_first_ins; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)regs->pc, 4); + icache_invalid_all(); + lwp->debug = 0; + return 1; + } while (0); + + thread_info.notify_type = GDB_NOTIFIY_BREAKPOINT; + thread_info.abt_ins = *(uint32_t *)regs->pc; + ret = 1; + } + } + else if (ec == 0x35 || ec == 0x34) /* watchpoint event */ + { + /* is watchpoint event */ + arch_deactivate_breakpoints(); + arch_activate_step(); + wp_thread_info.rw = (esr >> 6) & 1UL; + wp_thread_info.notify_type = GDB_NOTIFIY_WATCHPOINT; + return 3; + } + else + { + return 0; /* not support */ + } + thread_info.thread = rt_thread_self(); + thread_info.thread->regs = regs; + msg.u.d = (void *)&thread_info; + rt_hw_dmb(); + thread_info.thread->debug_suspend = 1; + rt_hw_dsb(); + rt_thread_suspend_with_flag(thread_info.thread, RT_UNINTERRUPTIBLE); + rt_raw_channel_send(gdb_get_server_channel(), &msg); + rt_schedule(); + while (thread_info.thread->debug_suspend) + { + rt_thread_suspend_with_flag(thread_info.thread, RT_UNINTERRUPTIBLE); + rt_schedule(); + } + return ret; + } + return 0; +} +#endif +void sys_exit(int value); +void check_user_fault(struct rt_hw_exp_stack *regs, uint32_t pc_adj, char *info) +{ + uint32_t mode = regs->cpsr; + + if ((mode & 0x1f) == 0x00) + { + rt_kprintf("%s! pc = 0x%08x\n", info, regs->pc - pc_adj); +#ifdef LWP_USING_CORE_DUMP + lwp_core_dump(regs, pc_adj); +#endif + sys_exit(-1); + } +} + +int check_user_stack(unsigned long esr, struct rt_hw_exp_stack *regs) +{ + unsigned char ec; + void *dfar; + int ret = 0; + + ec = (unsigned char)((esr >> 26) & 0x3fU); + switch (ec) + { + case 0x20: + case 0x21: + case 0x24: + asm volatile("mrs %0, far_el1":"=r"(dfar)); + if (arch_expand_user_stack(dfar)) + { + ret = 1; + } + break; + default: + break; + } + return ret; +} +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("X00:0x%16.16p X01:0x%16.16p X02:0x%16.16p X03:0x%16.16p\n", (void *)regs->x0, (void *)regs->x1, (void *)regs->x2, (void *)regs->x3); + rt_kprintf("X04:0x%16.16p X05:0x%16.16p X06:0x%16.16p X07:0x%16.16p\n", (void *)regs->x4, (void *)regs->x5, (void *)regs->x6, (void *)regs->x7); + rt_kprintf("X08:0x%16.16p X09:0x%16.16p X10:0x%16.16p X11:0x%16.16p\n", (void *)regs->x8, (void *)regs->x9, (void *)regs->x10, (void *)regs->x11); + rt_kprintf("X12:0x%16.16p X13:0x%16.16p X14:0x%16.16p X15:0x%16.16p\n", (void *)regs->x12, (void *)regs->x13, (void *)regs->x14, (void *)regs->x15); + rt_kprintf("X16:0x%16.16p X17:0x%16.16p X18:0x%16.16p X19:0x%16.16p\n", (void *)regs->x16, (void *)regs->x17, (void *)regs->x18, (void *)regs->x19); + rt_kprintf("X20:0x%16.16p X21:0x%16.16p X22:0x%16.16p X23:0x%16.16p\n", (void *)regs->x20, (void *)regs->x21, (void *)regs->x22, (void *)regs->x23); + rt_kprintf("X24:0x%16.16p X25:0x%16.16p X26:0x%16.16p X27:0x%16.16p\n", (void *)regs->x24, (void *)regs->x25, (void *)regs->x26, (void *)regs->x27); + rt_kprintf("X28:0x%16.16p X29:0x%16.16p X30:0x%16.16p\n", (void *)regs->x28, (void *)regs->x29, (void *)regs->x30); + rt_kprintf("SP_EL0:0x%16.16p\n", (void *)regs->sp_el0); + rt_kprintf("SPSR :0x%16.16p\n", (void *)regs->cpsr); + rt_kprintf("EPC :0x%16.16p\n", (void *)regs->pc); +} + +void rt_hw_trap_irq(void) +{ +#ifdef SOC_BCM283x + extern rt_uint8_t core_timer_flag; + void *param; + uint32_t irq; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + uint32_t value = 0; + value = IRQ_PEND_BASIC & 0x3ff; + + if(core_timer_flag != 0) + { + uint32_t cpu_id = rt_hw_cpu_id(); + uint32_t int_source = CORE_IRQSOURCE(cpu_id); + if (int_source & 0x0f) + { + if (int_source & 0x08) + { + isr_func = isr_table[IRQ_ARM_TIMER].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_TIMER].counter++; +#endif + if (isr_func) + { + param = isr_table[IRQ_ARM_TIMER].param; + isr_func(IRQ_ARM_TIMER, param); + } + } + } + } + + /* local interrupt*/ + if (value) + { + if (value & (1 << 8)) + { + value = IRQ_PEND1; + irq = __rt_ffs(value) - 1; + } + else if (value & (1 << 9)) + { + value = IRQ_PEND2; + irq = __rt_ffs(value) + 31; + } + else + { + value &= 0x0f; + irq = __rt_ffs(value) + 63; + } + + /* get interrupt service routine */ + isr_func = isr_table[irq].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[irq].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[irq].param; + /* turn to interrupt service routine */ + isr_func(irq, param); + } + } +#else + void *param; + int ir, ir_self; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + + if (ir == 1023) + { + /* Spurious interrupt */ + return; + } + + /* bit 10~12 is cpuid, bit 0~9 is interrupt id */ + ir_self = ir & 0x3ffUL; + + /* get interrupt service routine */ + isr_func = isr_table[ir_self].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[ir_self].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir_self].param; + /* turn to interrupt service routine */ + isr_func(ir_self, param); + } + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); +#endif +} + +void rt_hw_trap_fiq(void) +{ + void *param; + int ir, ir_self; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + + /* bit 10~12 is cpuid, bit 0~9 is interrup id */ + ir_self = ir & 0x3ffUL; + + /* get interrupt service routine */ + isr_func = isr_table[ir_self].handler; + param = isr_table[ir_self].param; + + /* turn to interrupt service routine */ + isr_func(ir_self, param); + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); +} + +void process_exception(unsigned long esr, unsigned long epc); +void SVC_Handler(struct rt_hw_exp_stack *regs); +void rt_hw_trap_exception(struct rt_hw_exp_stack *regs) +{ + unsigned long esr; + unsigned char ec; + + asm volatile("mrs %0, esr_el1":"=r"(esr)); + ec = (unsigned char)((esr >> 26) & 0x3fU); + +#ifdef RT_USING_LWP +#ifdef RT_USING_GDBSERVER + if (check_debug_event(regs, esr)) + { + return; + } + else +#endif +#endif + if (ec == 0x15) /* is 64bit syscall ? */ + { + SVC_Handler(regs); + /* never return here */ + } + + if (check_user_stack(esr, regs)) + { + return; + } + + process_exception(esr, regs->pc); + rt_hw_show_register(regs); + rt_kprintf("current: %s\n", rt_thread_self()->name); + check_user_fault(regs, 0, "user fault"); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +void rt_hw_trap_serror(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("SError\n"); + rt_hw_show_register(regs); + rt_kprintf("current: %s\n", rt_thread_self()->name); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} diff --git a/libcpu/aarch64/common/vector_gcc.S b/libcpu/aarch64/common/vector_gcc.S index fc88cce7f864ba7b884eb105abf582fe080ccb5c..d765fdd89ca5081b7be5b1320c4495246700402a 100644 --- a/libcpu/aarch64/common/vector_gcc.S +++ b/libcpu/aarch64/common/vector_gcc.S @@ -10,7 +10,7 @@ .text .globl system_vectors -.globl vector_error +.globl vector_exception .globl vector_irq .globl vector_fiq @@ -18,44 +18,43 @@ system_vectors: .align 11 .set VBAR, system_vectors .org VBAR - // Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1) + + /* Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1) */ .org (VBAR + 0x00 + 0) - B vector_error // Synchronous + B vector_serror /* Synchronous */ .org (VBAR + 0x80 + 0) - B vector_irq // IRQ/vIRQ + B vector_serror /* IRQ/vIRQ */ .org (VBAR + 0x100 + 0) - B vector_fiq // FIQ/vFIQ + B vector_serror /* FIQ/vFIQ */ .org (VBAR + 0x180 + 0) - B vector_error // Error/vError + B vector_serror /* Error/vError */ - // Exception from CurrentEL (EL1) with SP_ELn + /* Exception from CurrentEL (EL1) with SP_ELn */ .org (VBAR + 0x200 + 0) - B vector_error // Synchronous + B vector_exception /* Synchronous */ .org (VBAR + 0x280 + 0) - B vector_irq // IRQ/vIRQ + B vector_irq /* IRQ/vIRQ */ .org (VBAR + 0x300 + 0) - B vector_fiq // FIQ/vFIQ + B vector_fiq /* FIQ/vFIQ */ .org (VBAR + 0x380 + 0) - B vector_error + B vector_serror - // Exception from lower EL, aarch64 + /* Exception from lower EL, aarch64 */ .org (VBAR + 0x400 + 0) - B vector_error + B vector_exception .org (VBAR + 0x480 + 0) - B vector_error + B vector_irq .org (VBAR + 0x500 + 0) - B vector_error + B vector_fiq .org (VBAR + 0x580 + 0) - B vector_error + B vector_serror - // Exception from lower EL, aarch32 + /* Exception from lower EL, aarch32 */ .org (VBAR + 0x600 + 0) - B vector_error + B vector_serror .org (VBAR + 0x680 + 0) - B vector_error + B vector_serror .org (VBAR + 0x700 + 0) - B vector_error + B vector_serror .org (VBAR + 0x780 + 0) - B vector_error - .org (VBAR + 0x800 + 0) - B vector_error + B vector_serror diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a/SConscript similarity index 100% rename from libcpu/aarch64/cortex-a53/SConscript rename to libcpu/aarch64/cortex-a/SConscript diff --git a/libcpu/aarch64/cortex-a/entry_point.S b/libcpu/aarch64/cortex-a/entry_point.S new file mode 100644 index 0000000000000000000000000000000000000000..c02aab89bc65169291c5dc75f4d249b01cc20481 --- /dev/null +++ b/libcpu/aarch64/cortex-a/entry_point.S @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2020-01-15 bigmagic the first version + * 2020-08-10 SummerGift support clang compiler + */ + +#include "rtconfig.h" +.section ".text.entrypoint","ax" +.global __start + +__start: + bl rt_hw_cpu_id_set + /* read cpu id, stop slave cores */ + mrs x0, tpidr_el1 + cbz x0, .L__cpu_0 /* .L prefix is the local label in ELF */ + + /* cpu id > 0, stop */ + /* cpu id == 0 will also goto here after returned from entry() if possible */ +.L__current_cpu_idle: + wfe + b .L__current_cpu_idle + +.L__cpu_0: + /* set stack before our code, Define stack pointer for current exception level */ + adr x1, __start + + /* set up EL1 */ + mrs x0, CurrentEL /* CurrentEL Register. bit 2, 3. Others reserved */ + and x0, x0, #12 /* clear reserved bits */ + + /* running at EL3? */ + cmp x0, #12 /* 1100b. So, EL3 */ + bne .L__not_in_el3 /* 11? !EL3 -> 5: */ + + /* should never be executed, just for completeness. (EL3) */ + mov x2, #0x5b1 + msr scr_el3, x2 /* SCR_ELn Secure Configuration Register */ + mov x2, #0x3c9 + msr spsr_el3, x2 /* SPSR_ELn. Saved Program Status Register. 1111001001 */ + adr x2, .L__not_in_el3 + msr elr_el3, x2 + eret /* Exception Return: from EL3, continue from .L__not_in_el3 */ + +.L__not_in_el3: /* running at EL2 or EL1 */ + cmp x0, #4 /* 0x04 0100 EL1 */ + beq .L__in_el1 /* EL1 -> 5: */ + + mrs x0, hcr_el2 + bic x0, x0, #0xff + msr hcr_el2, x0 + + msr sp_el1, x1 /* in EL2, set sp of EL1 to _start */ + + /* enable CNTP for EL1 */ + mrs x0, cnthctl_el2 /* Counter-timer Hypervisor Control register */ + orr x0, x0, #3 + msr cnthctl_el2, x0 + msr cntvoff_el2, xzr + + /* enable AArch64 in EL1 */ + mov x0, #(1 << 31) /* AArch64 */ + orr x0, x0, #(1 << 1) /* SWIO hardwired on Pi3 */ + msr hcr_el2, x0 + mrs x0, hcr_el2 + + /* change execution level to EL1 */ + mov x2, #0x3c4 + msr spsr_el2, x2 /* 1111000100 */ + adr x2, .L__in_el1 + msr elr_el2, x2 + + eret /* exception return. from EL2. continue from .L__in_el1 */ + +.L__in_el1: + ldr x9, =PV_OFFSET + mov sp, x1 /* in EL1. Set sp to _start */ + + /* Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction */ + mov x1, #0x00300000 /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */ + msr cpacr_el1, x1 + + /* clear bss */ + ldr x1, =__bss_start /* get bss start address */ + ldr x2, =__bss_end + sub x2, x2, x1 /* get bss size */ + add x1, x1, x9 + + and x3, x2, #7 /* x3 is < 7 */ + ldr x4, =~0x7 + and x2, x2, x4 /* mask ~7 */ + +.L__clean_bss_loop: + cbz x2, .L__clean_bss_loop_1 + str xzr, [x1], #8 + sub x2, x2, #8 + b .L__clean_bss_loop + +.L__clean_bss_loop_1: + cbz x3, .L__jump_to_entry + strb wzr, [x1], #1 + sub x3, x3, #1 + b .L__clean_bss_loop_1 + +.L__jump_to_entry: /* jump to C code, should not return */ + bl mmu_tcr_init + + adr x1, __start + ldr x0, =~0x1fffff + and x0, x1, x0 + add x1, x0, #0x1000 + + msr ttbr0_el1, x0 + msr ttbr1_el1, x1 + dsb sy + + ldr x2, =0x40000000 /* map 1G memory for kernel space */ + ldr x3, =PV_OFFSET + bl rt_hw_mmu_setup_early + + ldr x30, =after_mmu_enable /* set LR to after_mmu_enable function, it's a v_addr */ + + mrs x1, sctlr_el1 + bic x1, x1, #(3 << 3) /* dis SA, SA0 */ + bic x1, x1, #(1 << 1) /* dis A */ + orr x1, x1, #(1 << 12) /* I */ + orr x1, x1, #(1 << 2) /* C */ + orr x1, x1, #(1 << 0) /* M */ + msr sctlr_el1, x1 /* enable MMU */ + + dsb sy + isb sy + ic ialluis /* Invalidate all instruction caches in Inner Shareable domain to Point of Unification */ + dsb sy + isb sy + tlbi vmalle1 /* Invalidate all stage 1 translations used at EL1 with the current VMID */ + dsb sy + isb sy + ret + +after_mmu_enable: +#if 0 + mrs x0, tcr_el1 /* disable ttbr0, only using kernel space */ + orr x0, x0, #(1 << 7) + msr tcr_el1, x0 + msr ttbr0_el1, xzr + dsb sy +#endif + + mov x0, #1 + msr spsel, x0 + adr x1, __start + mov sp, x1 /* sp_el1 set to _start */ + + b rtthread_startup + +#ifdef RT_USING_SMP +/** + * secondary cpu + */ + +.globl _secondary_cpu_entry +_secondary_cpu_entry: + bl rt_hw_cpu_id_set + adr x1, __start + + /* set up EL1 */ + mrs x0, CurrentEL /* CurrentEL Register. bit 2, 3. Others reserved */ + and x0, x0, #12 /* clear reserved bits */ + + /* running at EL3? */ + cmp x0, #12 /* 1100b. So, EL3 */ + bne .L__not_in_el3_cpux /* 11? !EL3 -> 5: */ + + /* should never be executed, just for completeness. (EL3) */ + mov x2, #0x5b1 + msr scr_el3, x2 /* SCR_ELn Secure Configuration Register */ + mov x2, #0x3c9 + msr spsr_el3, x2 /* SPSR_ELn. Saved Program Status Register. 1111001001 */ + adr x2, .L__not_in_el3_cpux + msr elr_el3, x2 + eret /* Exception Return: from EL3, continue from .L__not_in_el3 */ + +.L__not_in_el3_cpux: /* running at EL2 or EL1 */ + cmp x0, #4 /* 0x04 0100 EL1 */ + beq .L__in_el1_cpux /* EL1 -> 5: */ + + mrs x0, hcr_el2 + bic x0, x0, #0xff + msr hcr_el2, x0 + + msr sp_el1, x1 /* in EL2, set sp of EL1 to _start */ + + /* enable CNTP for EL1 */ + mrs x0, cnthctl_el2 /* Counter-timer Hypervisor Control register */ + orr x0, x0, #3 + msr cnthctl_el2, x0 + msr cntvoff_el2, xzr + + /* enable AArch64 in EL1 */ + mov x0, #(1 << 31) /* AArch64 */ + orr x0, x0, #(1 << 1) /* SWIO hardwired on Pi3 */ + msr hcr_el2, x0 + mrs x0, hcr_el2 + + /* change execution level to EL1 */ + mov x2, #0x3c4 + msr spsr_el2, x2 /* 1111000100 */ + adr x2, .L__in_el1_cpux + msr elr_el2, x2 + + eret /* exception return. from EL2. continue from .L__in_el1 */ + +.L__in_el1_cpux: + adr x19, .L__in_el1_cpux + ldr x8, =.L__in_el1_cpux + sub x19, x19, x8 /* get PV_OFFSET */ + + mrs x0, tpidr_el1 + /* each cpu init stack is 8k */ + sub x1, x1, x0, lsl #13 + mov sp, x1 /* in EL1. Set sp to _start */ + + /* Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction */ + mov x1, #0x00300000 /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */ + msr cpacr_el1, x1 + +.L__jump_to_entry_cpux: /* jump to C code, should not return */ + + /* init mmu early */ + + bl mmu_tcr_init + + adr x1, __start + ldr x0, =~0x1fffff + and x0, x1, x0 + add x1, x0, #0x1000 + + msr ttbr0_el1, x0 + msr ttbr1_el1, x1 + dsb sy + + ldr x30, =after_mmu_enable_cpux /* set LR to after_mmu_enable function, it's a v_addr */ + + mrs x1, sctlr_el1 + bic x1, x1, #(3 << 3) /* dis SA, SA0 */ + bic x1, x1, #(1 << 1) /* dis A */ + orr x1, x1, #(1 << 12) /* I */ + orr x1, x1, #(1 << 2) /* C */ + orr x1, x1, #(1 << 0) /* M */ + msr sctlr_el1, x1 /* enable MMU */ + + dsb sy + isb sy + ic ialluis /* Invalidate all instruction caches in Inner Shareable domain to Point of Unification */ + dsb sy + isb sy + tlbi vmalle1 /* Invalidate all stage 1 translations used at EL1 with the current VMID */ + dsb sy + isb sy + ret + +after_mmu_enable_cpux: + mrs x0, tcr_el1 /* disable ttbr0, only using kernel space */ + orr x0, x0, #(1 << 7) + msr tcr_el1, x0 + msr ttbr0_el1, xzr + dsb sy + + mov x0, #1 + msr spsel, x0 + mrs x0, tpidr_el1 + /* each cpu init stack is 8k */ + adr x1, __start + sub x1, x1, x0, lsl #13 + mov sp, x1 /* in EL1. Set sp to _start */ + + b rt_hw_secondary_cpu_bsp_start +#endif diff --git a/libcpu/aarch64/cortex-a53/entry_point.S b/libcpu/aarch64/cortex-a53/entry_point.S deleted file mode 100644 index 6d2c69226b64ffc2226308bcd01aee3dbffe176a..0000000000000000000000000000000000000000 --- a/libcpu/aarch64/cortex-a53/entry_point.S +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Date Author Notes - * 2020-01-15 bigmagic the first version - */ - -.section ".text.entrypoint" - -.set EL1_stack, __el1_stack - -.global _start - -// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware -// loads 'kernel8.img' file in. -_start: - // read cpu id, stop slave cores - mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register - and x1, x1, #3 - cbz x1, .L__cpu_0 // .L prefix is the local label in ELF - - // cpu id > 0, stop - // cpu id == 0 will also goto here after returned from entry() if possible -.L__current_cpu_idle: - wfe - b .L__current_cpu_idle - -.L__cpu_0: // cpu id == 0 - - // set stack before our code - - /* Define stack pointer for current exception level */ - // ldr x2, =EL1_stack - // mov sp, x2 - - ldr x1, =_start - - // set up EL1 - mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved - and x0, x0, #12 // clear reserved bits - - // running at EL3? - cmp x0, #12 // 1100b. So, EL3 - bne .L__not_in_el3 // 11? !EL3 -> 5: - - // should never be executed, just for completeness. (EL3) - mov x2, #0x5b1 - msr scr_el3, x2 // SCR_ELn Secure Configuration Register - mov x2, #0x3c9 - msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001 - adr x2, .L__not_in_el3 - msr elr_el3, x2 - eret // Exception Return: from EL3, continue from .L__not_in_el3 - - // running at EL2 or EL1 -.L__not_in_el3: - cmp x0, #4 // 0x04 0100 EL1 - beq .L__in_el1 // EL1 -> 5: - - // in EL2 - msr sp_el1, x1 // Set sp of EL1 to _start - - // enable CNTP for EL1 - mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register - orr x0, x0, #3 - msr cnthctl_el2, x0 - msr cntvoff_el2, xzr - - // enable AArch64 in EL1 - mov x0, #(1 << 31) // AArch64 - orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3 - msr hcr_el2, x0 - mrs x0, hcr_el2 - - // change execution level to EL1 - mov x2, #0x3c4 - msr spsr_el2, x2 // 1111000100 - adr x2, .L__in_el1 - msr elr_el2, x2 - eret // exception return. from EL2. continue from .L__in_el1 - -.L__in_el1: - mov sp, x1 // in EL1. Set sp to _start - - // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction - mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1 - msr cpacr_el1, x1 - - mrs x1, sctlr_el1 - orr x1, x1, #(1 << 12) - bic x1, x1, #(3 << 3) - bic x1, x1, #(1 << 1) - msr sctlr_el1, x1 - - // clear bss - ldr x1, =__bss_start - ldr w2, =__bss_size - -.L__clean_bss_loop: - cbz w2, .L__jump_to_entry - str xzr, [x1], #8 - sub w2, w2, #1 - cbnz w2, .L__clean_bss_loop - - // jump to C code, should not return -.L__jump_to_entry: - bl entry - // for failsafe, halt this core too - b .L__current_cpu_idle diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h deleted file mode 100644 index 8e741ed4e6fc0759cd1bcd423d786494f7004112..0000000000000000000000000000000000000000 --- a/libcpu/aarch64/cortex-a53/interrupt.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-04-16 bigmagic first version - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#include -#include - -#include "raspi.h" - -#define INT_IRQ 0x00 -#define INT_FIQ 0x01 - -void rt_hw_interrupt_init(void); -void rt_hw_interrupt_mask(int vector); -void rt_hw_interrupt_umask(int vector); - -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name); - -#endif diff --git a/libcpu/aarch64/cortex-a53/stack.c b/libcpu/aarch64/cortex-a53/stack.c deleted file mode 100644 index 68222c2c67d440913a54c3e243f4898577f41172..0000000000000000000000000000000000000000 --- a/libcpu/aarch64/cortex-a53/stack.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2006-2019, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-23 Bernard the first version - * 2011-10-05 Bernard add thumb mode - */ -#include -#include - -#include - -#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0) -#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0) -#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0) - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_ubase_t *stk; - rt_ubase_t current_el; - - stk = (rt_ubase_t*)stack_addr; - - *(--stk) = ( rt_ubase_t ) 11; /* X1 */ - *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ - *(--stk) = ( rt_ubase_t ) 33; /* X3 */ - *(--stk) = ( rt_ubase_t ) 22; /* X2 */ - *(--stk) = ( rt_ubase_t ) 55; /* X5 */ - *(--stk) = ( rt_ubase_t ) 44; /* X4 */ - *(--stk) = ( rt_ubase_t ) 77; /* X7 */ - *(--stk) = ( rt_ubase_t ) 66; /* X6 */ - *(--stk) = ( rt_ubase_t ) 99; /* X9 */ - *(--stk) = ( rt_ubase_t ) 88; /* X8 */ - *(--stk) = ( rt_ubase_t ) 11; /* X11 */ - *(--stk) = ( rt_ubase_t ) 10; /* X10 */ - *(--stk) = ( rt_ubase_t ) 13; /* X13 */ - *(--stk) = ( rt_ubase_t ) 12; /* X12 */ - *(--stk) = ( rt_ubase_t ) 15; /* X15 */ - *(--stk) = ( rt_ubase_t ) 14; /* X14 */ - *(--stk) = ( rt_ubase_t ) 17; /* X17 */ - *(--stk) = ( rt_ubase_t ) 16; /* X16 */ - *(--stk) = ( rt_ubase_t ) 19; /* X19 */ - *(--stk) = ( rt_ubase_t ) 18; /* X18 */ - *(--stk) = ( rt_ubase_t ) 21; /* X21 */ - *(--stk) = ( rt_ubase_t ) 20; /* X20 */ - *(--stk) = ( rt_ubase_t ) 23; /* X23 */ - *(--stk) = ( rt_ubase_t ) 22; /* X22 */ - *(--stk) = ( rt_ubase_t ) 25; /* X25 */ - *(--stk) = ( rt_ubase_t ) 24; /* X24 */ - *(--stk) = ( rt_ubase_t ) 27; /* X27 */ - *(--stk) = ( rt_ubase_t ) 26; /* X26 */ - *(--stk) = ( rt_ubase_t ) 29; /* X29 */ - *(--stk) = ( rt_ubase_t ) 28; /* X28 */ - *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ - *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ - - current_el = rt_hw_get_current_el(); - - if(current_el == 3) - { - *(--stk) = INITIAL_SPSR_EL3; - } - else if(current_el == 2) - { - *(--stk) = INITIAL_SPSR_EL2; - } - else - { - *(--stk) = INITIAL_SPSR_EL1; - } - - *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c deleted file mode 100644 index 41d4d620f69170cc5cd1ece6b6bfdb072e2fcea1..0000000000000000000000000000000000000000 --- a/libcpu/aarch64/cortex-a53/trap.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Date Author Notes - * 2018-10-06 ZhaoXiaowei the first version - */ - -#include -#include - -#include "interrupt.h" -#include "armv8.h" - -extern struct rt_thread *rt_current_thread; -#ifdef RT_USING_FINSH -extern long list_thread(void); -#endif - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); - rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); - rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); - rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); - rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); - rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); - rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); - rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); - rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); - rt_kprintf("return pc:0x%16.16lx\n", regs->pc); -} - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_error(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("error exception:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -#define GIC_ACK_INTID_MASK (0x000003ff) -#define CORE0_IRQ_SOURCE (0x40000060) - -void rt_hw_trap_irq(void) -{ - void *param; - uint32_t irq; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - uint32_t value = 0; - value = IRQ_PEND_BASIC & 0x3ff; -#ifdef BSP_USING_CORETIMER - uint32_t int_source = HWREG32(CORE0_IRQ_SOURCE) & 0x3ff; - if (int_source & 0x02) - { - isr_func = isr_table[IRQ_ARM_TIMER].handler; - #ifdef RT_USING_INTERRUPT_INFO - isr_table[IRQ_ARM_TIMER].counter++; - #endif - if (isr_func) - { - param = isr_table[IRQ_ARM_TIMER].param; - isr_func(IRQ_ARM_TIMER, param); - } - } -#endif - /* local interrupt*/ - if (value) - { - if (value & (1 << 8)) - { - value = IRQ_PEND1; - irq = __rt_ffs(value) - 1; - } - else if (value & (1 << 9)) - { - value = IRQ_PEND2; - irq = __rt_ffs(value) + 31; - } - else - { - value &= 0x0f; - irq = __rt_ffs(value) + 63; - } - - /* get interrupt service routine */ - isr_func = isr_table[irq].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; -#endif - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[irq].param; - /* turn to interrupt service routine */ - isr_func(irq, param); - } - } -} - -void rt_hw_trap_fiq(void) -{ - void *param; - uint32_t irq; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - uint32_t value = 0; - value = IRQ_PEND_BASIC & 0x3ff; -#ifdef RT_USING_SMP - uint32_t mailbox_data; - uint32_t cpu_id = rt_hw_cpu_id(); - uint32_t int_source = CORE_IRQSOURCE(cpu_id); - mailbox_data = IPI_MAILBOX_CLEAR(cpu_id); - if (int_source & 0x0f) - { - if (int_source & 0x08) - { - isr_func = isr_table[IRQ_ARM_TIMER].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[IRQ_ARM_TIMER].counter++; -#endif - if (isr_func) - { - param = isr_table[IRQ_ARM_TIMER].param; - isr_func(IRQ_ARM_TIMER, param); - } - } - } - if (int_source & 0xf0) - { - /*it's a ipi interrupt*/ - if (mailbox_data & 0x1) - { - /* clear mailbox */ - IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data; - isr_func = isr_table[IRQ_ARM_MAILBOX].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[IRQ_ARM_MAILBOX].counter++; -#endif - if (isr_func) - { - param = isr_table[IRQ_ARM_MAILBOX].param; - isr_func(IRQ_ARM_MAILBOX, param); - } - } - else - CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data; - } -#endif - /* local interrupt*/ - if (value) - { - if (value & (1 << 8)) - { - value = IRQ_PEND1; - irq = __rt_ffs(value) - 1; - } - else if (value & (1 << 9)) - { - value = IRQ_PEND2; - irq = __rt_ffs(value) + 31; - } - else - { - value &= 0x0f; - irq = __rt_ffs(value) + 63; - } - - /* get interrupt service routine */ - isr_func = isr_table[irq].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; -#endif - if (irq > 1) - rt_kprintf("interrupt fiq %d\n", irq); - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[irq].param; - /* turn to interrupt service routine */ - isr_func(irq, param); - } - } -} diff --git a/libcpu/aarch64/cortex-a72/entry_point.S b/libcpu/aarch64/cortex-a72/entry_point.S deleted file mode 100644 index 6d2c69226b64ffc2226308bcd01aee3dbffe176a..0000000000000000000000000000000000000000 --- a/libcpu/aarch64/cortex-a72/entry_point.S +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Date Author Notes - * 2020-01-15 bigmagic the first version - */ - -.section ".text.entrypoint" - -.set EL1_stack, __el1_stack - -.global _start - -// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware -// loads 'kernel8.img' file in. -_start: - // read cpu id, stop slave cores - mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register - and x1, x1, #3 - cbz x1, .L__cpu_0 // .L prefix is the local label in ELF - - // cpu id > 0, stop - // cpu id == 0 will also goto here after returned from entry() if possible -.L__current_cpu_idle: - wfe - b .L__current_cpu_idle - -.L__cpu_0: // cpu id == 0 - - // set stack before our code - - /* Define stack pointer for current exception level */ - // ldr x2, =EL1_stack - // mov sp, x2 - - ldr x1, =_start - - // set up EL1 - mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved - and x0, x0, #12 // clear reserved bits - - // running at EL3? - cmp x0, #12 // 1100b. So, EL3 - bne .L__not_in_el3 // 11? !EL3 -> 5: - - // should never be executed, just for completeness. (EL3) - mov x2, #0x5b1 - msr scr_el3, x2 // SCR_ELn Secure Configuration Register - mov x2, #0x3c9 - msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001 - adr x2, .L__not_in_el3 - msr elr_el3, x2 - eret // Exception Return: from EL3, continue from .L__not_in_el3 - - // running at EL2 or EL1 -.L__not_in_el3: - cmp x0, #4 // 0x04 0100 EL1 - beq .L__in_el1 // EL1 -> 5: - - // in EL2 - msr sp_el1, x1 // Set sp of EL1 to _start - - // enable CNTP for EL1 - mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register - orr x0, x0, #3 - msr cnthctl_el2, x0 - msr cntvoff_el2, xzr - - // enable AArch64 in EL1 - mov x0, #(1 << 31) // AArch64 - orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3 - msr hcr_el2, x0 - mrs x0, hcr_el2 - - // change execution level to EL1 - mov x2, #0x3c4 - msr spsr_el2, x2 // 1111000100 - adr x2, .L__in_el1 - msr elr_el2, x2 - eret // exception return. from EL2. continue from .L__in_el1 - -.L__in_el1: - mov sp, x1 // in EL1. Set sp to _start - - // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction - mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1 - msr cpacr_el1, x1 - - mrs x1, sctlr_el1 - orr x1, x1, #(1 << 12) - bic x1, x1, #(3 << 3) - bic x1, x1, #(1 << 1) - msr sctlr_el1, x1 - - // clear bss - ldr x1, =__bss_start - ldr w2, =__bss_size - -.L__clean_bss_loop: - cbz w2, .L__jump_to_entry - str xzr, [x1], #8 - sub w2, w2, #1 - cbnz w2, .L__clean_bss_loop - - // jump to C code, should not return -.L__jump_to_entry: - bl entry - // for failsafe, halt this core too - b .L__current_cpu_idle diff --git a/libcpu/aarch64/cortex-a72/interrupt.h b/libcpu/aarch64/cortex-a72/interrupt.h deleted file mode 100644 index 0d2d4867c7d4edd457d25466e31ad83b37815dae..0000000000000000000000000000000000000000 --- a/libcpu/aarch64/cortex-a72/interrupt.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-04-16 bigmagic first version - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#include -#include - -#define INT_IRQ 0x00 -#define INT_FIQ 0x01 - -void rt_hw_interrupt_init(void); -void rt_hw_interrupt_mask(int vector); -void rt_hw_interrupt_umask(int vector); - -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name); - -#endif diff --git a/libcpu/aarch64/cortex-a72/trap.c b/libcpu/aarch64/cortex-a72/trap.c deleted file mode 100644 index d93aa18fd6a9d0adb4123cf46097b1d76a9e6532..0000000000000000000000000000000000000000 --- a/libcpu/aarch64/cortex-a72/trap.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Date Author Notes - * 2018-10-06 ZhaoXiaowei the first version - */ - -#include -#include - -#include "interrupt.h" -#include "armv8.h" - -extern struct rt_thread *rt_current_thread; -#ifdef RT_USING_FINSH -extern long list_thread(void); -#endif - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); - rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); - rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); - rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); - rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); - rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); - rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); - rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); - rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); - rt_kprintf("return pc:0x%16.16lx\n", regs->pc); -} - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_error(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("error exception:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -#define GIC_ACK_INTID_MASK 0x000003ff - -int rt_hw_interrupt_get_irq(void); -void rt_hw_interrupt_ack(int fiq_irq); - -void rt_hw_trap_irq(void) -{ - void *param; - int ir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - ir = rt_hw_interrupt_get_irq(); - if (ir == 1023) - { - /* Spurious interrupt */ - return; - } - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[ir].counter++; -#endif - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[ir].param; - /* turn to interrupt service routine */ - isr_func(ir, param); - } - - /* end of interrupt */ - rt_hw_interrupt_ack(ir); - -} - -void rt_hw_trap_fiq(void) -{ -} diff --git a/libcpu/arm/AT91SAM7X/trap.c b/libcpu/arm/AT91SAM7X/trap.c index 1c1c351ff81b63ac1c80f1586cd2a0d4db0ca9e8..dbbe2a1684a8ea00229ae0cce6c86e995e20f948 100644 --- a/libcpu/arm/AT91SAM7X/trap.c +++ b/libcpu/arm/AT91SAM7X/trap.c @@ -42,7 +42,7 @@ extern struct rt_thread* rt_current_thread; void rt_hw_trap_abort(void) { rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); - rt_thread_suspend(rt_current_thread); + rt_thread_suspend_witch_flag(rt_current_thread, RT_UNINTERRUPTIBLE); rt_schedule(); } diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c deleted file mode 100644 index 4fc87b20d14642c3c64ff6c74f8b381cf6eaa310..0000000000000000000000000000000000000000 --- a/libcpu/arm/common/backtrace.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version from QiuYi implementation - */ - -#include - -#ifdef __GNUC__ -/* --->High Address,Stack Top -PC<------| -LR | -IP | -FP | -...... | -PC <-| | -LR | | -IP | | -FP---|-- | -...... | -PC | -LR | -IP | -FP--- --->Low Address,Stack Bottom -*/ -void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) -{ - rt_uint32_t i, pc, func_entry; - - pc = *fp; - rt_kprintf("[0x%x]\n", pc-0xC); - - for(i=0; i<10; i++) - { - fp = (rt_uint32_t *)*(fp - 3); - pc = *fp ; - - func_entry = pc - 0xC; - - if(func_entry <= 0x30000000) break; - - if(func_entry == thread_entry) - { - rt_kprintf("EntryPoint:0x%x\n", func_entry); - - break; - } - - rt_kprintf("[0x%x]\n", func_entry); - } -} -#else -void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) -{ - /* old compiler implementation */ -} -#endif diff --git a/libcpu/arm/common/showmem.c b/libcpu/arm/common/showmem.c deleted file mode 100644 index b770e4ce173172419e2cf7b24e73953d647cbdf0..0000000000000000000000000000000000000000 --- a/libcpu/arm/common/showmem.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version from QiuYi implementation - */ - -#include - -void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) -{ - int i = 0, j =0; - - RT_ASSERT(addr); - - addr = addr & ~0xF; - size = 4*((size + 3)/4); - - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); - - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - - addr += 4; - i++; - } - - rt_kprintf("\n"); - } - - return; -} diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript index 9ff30a796b5ca7b75c976f1e694598d125655840..42d528ee0da7940f117247caf07f09a52b083dac 100644 --- a/libcpu/arm/cortex-a/SConscript +++ b/libcpu/arm/cortex-a/SConscript @@ -18,6 +18,10 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') +# There is no GIC in Raspi3, so remove it from source files. +if GetDepend('SOC_BCM283x'): + SrcRemove(src, ['gic.c']) + group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-a/backtrace.c b/libcpu/arm/cortex-a/backtrace.c new file mode 100644 index 0000000000000000000000000000000000000000..1d4d444aa96a37dd659d65b94bc3a27c46a10f23 --- /dev/null +++ b/libcpu/arm/cortex-a/backtrace.c @@ -0,0 +1,545 @@ +#ifndef __CHECKER__ +#if !defined (__ARM_EABI__) +#warning Your compiler does not have EABI support. +#warning ARM unwind is known to compile only with EABI compilers. +#warning Change compiler or disable ARM_UNWIND option. +#elif (__GNUC__ == 4 && __GNUC_MINOR__ <= 2) && !defined(__clang__) +#warning Your compiler is too buggy; it is known to not compile ARM unwind support. +#warning Change compiler or disable ARM_UNWIND option. +#endif +#endif /* __CHECKER__ */ + +#include +#include +#include + +#define DBG_TAG "BACKTRACE" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_USERSPACE +#include +#include +#include +#endif + +rt_inline void arm_get_current_stackframe(struct pt_regs *regs, struct stackframe *frame) +{ + frame->fp = frame_pointer(regs); + frame->sp = regs->ARM_sp; + frame->lr = regs->ARM_lr; + frame->pc = regs->ARM_pc; +} + +/* Dummy functions to avoid linker complaints */ +void __aeabi_unwind_cpp_pr0(void) +{ +}; + +void __aeabi_unwind_cpp_pr1(void) +{ +}; + +void __aeabi_unwind_cpp_pr2(void) +{ +}; + +struct unwind_ctrl_block { + unsigned long vrs[16]; /* virtual register set */ + const unsigned long *insn; /* pointer to the current instructions word */ + unsigned long sp_high; /* highest value of sp allowed */ + /* + * 1 : check for stack overflow for each register pop. + * 0 : save overhead if there is plenty of stack remaining. + */ + int check_each_pop; + int entries; /* number of entries left to interpret */ + int byte; /* current byte number in the instructions word */ +}; + +enum regs +{ +#ifdef CONFIG_THUMB2_KERNEL + FP = 7, +#else + FP = 11, +#endif + SP = 13, + LR = 14, + PC = 15 +}; + +static int core_kernel_text(unsigned long addr) +{ + return 1; +} + +/* Convert a prel31 symbol to an absolute address */ +#define prel31_to_addr(ptr) \ + ({ \ + /* sign-extend to 32 bits */ \ + long offset = (((long)*(ptr)) << 1) >> 1; \ + (unsigned long)(ptr) + offset; \ + }) + +/* + * Binary search in the unwind index. The entries are + * guaranteed to be sorted in ascending order by the linker. + * + * start = first entry + * origin = first entry with positive offset (or stop if there is no such entry) + * stop - 1 = last entry + */ +static const struct unwind_idx *search_index(unsigned long addr, + const struct unwind_idx *start, + const struct unwind_idx *origin, + const struct unwind_idx *stop) +{ + unsigned long addr_prel31; + + LOG_D("%s(%08lx, %x, %x, %x)", + __func__, addr, start, origin, stop); + + /* + * only search in the section with the matching sign. This way the + * prel31 numbers can be compared as unsigned longs. + */ + if (addr < (unsigned long)start) + /* negative offsets: [start; origin) */ + stop = origin; + else + /* positive offsets: [origin; stop) */ + start = origin; + + /* prel31 for address relavive to start */ + addr_prel31 = (addr - (unsigned long)start) & 0x7fffffff; + + while (start < stop - 1) + { + const struct unwind_idx *mid = start + ((stop - start) >> 1); + + /* + * As addr_prel31 is relative to start an offset is needed to + * make it relative to mid. + */ + if (addr_prel31 - ((unsigned long)mid - (unsigned long)start) < + mid->addr_offset) + stop = mid; + else + { + /* keep addr_prel31 relative to start */ + addr_prel31 -= ((unsigned long)mid - + (unsigned long)start); + start = mid; + } + } + + if (start->addr_offset <= addr_prel31) + return start; + else + { + LOG_W("unwind: Unknown symbol address %08lx", addr); + return RT_NULL; + } +} + +static const struct unwind_idx *unwind_find_origin( + const struct unwind_idx *start, const struct unwind_idx *stop) +{ + LOG_D("%s(%x, %x)", __func__, start, stop); + while (start < stop) + { + const struct unwind_idx *mid = start + ((stop - start) >> 1); + + if (mid->addr_offset >= 0x40000000) + /* negative offset */ + start = mid + 1; + else + /* positive offset */ + stop = mid; + } + LOG_D("%s -> %x", __func__, stop); + return stop; +} + +static const struct unwind_idx *unwind_find_idx(unsigned long addr, const struct unwind_idx **origin_idx, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]) +{ + const struct unwind_idx *idx = RT_NULL; + + LOG_D("%s(%08lx)", __func__, addr); + + if (core_kernel_text(addr)) + { + if (!*origin_idx) + *origin_idx = + unwind_find_origin(exidx_start, + exidx_end); + + /* main unwind table */ + idx = search_index(addr, exidx_start, + *origin_idx, + exidx_end); + } + + LOG_D("%s: idx = %x", __func__, idx); + return idx; +} + +static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl) +{ + unsigned long ret; + + if (ctrl->entries <= 0) + { + LOG_W("unwind: Corrupt unwind table"); + return 0; + } + + ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff; + + if (ctrl->byte == 0) + { + ctrl->insn++; + ctrl->entries--; + ctrl->byte = 3; + } + else + ctrl->byte--; + + return ret; +} + +/* Before poping a register check whether it is feasible or not */ +static int unwind_pop_register(struct unwind_ctrl_block *ctrl, + unsigned long **vsp, unsigned int reg) +{ + if (ctrl->check_each_pop) + if (*vsp >= (unsigned long *)ctrl->sp_high) + return -URC_FAILURE; + + ctrl->vrs[reg] = *(*vsp)++; + return URC_OK; +} + +/* Helper functions to execute the instructions */ +static int unwind_exec_pop_subset_r4_to_r13(struct unwind_ctrl_block *ctrl, + unsigned long mask) +{ + unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; + int load_sp, reg = 4; + + load_sp = mask & (1 << (13 - 4)); + while (mask) + { + if (mask & 1) + if (unwind_pop_register(ctrl, &vsp, reg)) + return -URC_FAILURE; + mask >>= 1; + reg++; + } + if (!load_sp) + ctrl->vrs[SP] = (unsigned long)vsp; + + return URC_OK; +} + +static int unwind_exec_pop_r4_to_rN(struct unwind_ctrl_block *ctrl, + unsigned long insn) +{ + unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; + int reg; + + /* pop R4-R[4+bbb] */ + for (reg = 4; reg <= 4 + (insn & 7); reg++) + if (unwind_pop_register(ctrl, &vsp, reg)) + return -URC_FAILURE; + + if (insn & 0x8) + if (unwind_pop_register(ctrl, &vsp, 14)) + return -URC_FAILURE; + + ctrl->vrs[SP] = (unsigned long)vsp; + + return URC_OK; +} + +static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl, + unsigned long mask) +{ + unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; + int reg = 0; + + /* pop R0-R3 according to mask */ + while (mask) + { + if (mask & 1) + if (unwind_pop_register(ctrl, &vsp, reg)) + return -URC_FAILURE; + mask >>= 1; + reg++; + } + ctrl->vrs[SP] = (unsigned long)vsp; + + return URC_OK; +} + +/* + * Execute the current unwind instruction. + */ +static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) +{ + unsigned long insn = unwind_get_byte(ctrl); + int ret = URC_OK; + + LOG_D("%s: insn = %08lx", __func__, insn); + + if ((insn & 0xc0) == 0x00) + ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4; + else if ((insn & 0xc0) == 0x40) + ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; + else if ((insn & 0xf0) == 0x80) + { + unsigned long mask; + + insn = (insn << 8) | unwind_get_byte(ctrl); + mask = insn & 0x0fff; + if (mask == 0) + { + LOG_W("unwind: 'Refuse to unwind' instruction %04lx", + insn); + return -URC_FAILURE; + } + + ret = unwind_exec_pop_subset_r4_to_r13(ctrl, mask); + if (ret) + goto error; + } + else if ((insn & 0xf0) == 0x90 && + (insn & 0x0d) != 0x0d) + ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; + else if ((insn & 0xf0) == 0xa0) + { + ret = unwind_exec_pop_r4_to_rN(ctrl, insn); + if (ret) + goto error; + } + else if (insn == 0xb0) + { + if (ctrl->vrs[PC] == 0) + ctrl->vrs[PC] = ctrl->vrs[LR]; + /* no further processing */ + ctrl->entries = 0; + } + else if (insn == 0xb1) + { + unsigned long mask = unwind_get_byte(ctrl); + + if (mask == 0 || mask & 0xf0) + { + LOG_W("unwind: Spare encoding %04lx", + (insn << 8) | mask); + return -URC_FAILURE; + } + + ret = unwind_exec_pop_subset_r0_to_r3(ctrl, mask); + if (ret) + goto error; + } + else if (insn == 0xb2) + { + unsigned long uleb128 = unwind_get_byte(ctrl); + + ctrl->vrs[SP] += 0x204 + (uleb128 << 2); + } + else + { + LOG_W("unwind: Unhandled instruction %02lx", insn); + return -URC_FAILURE; + } + + LOG_D("%s: fp = %08lx sp = %08lx lr = %08lx pc = %08lx", __func__, + ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); + +error: + return ret; +} + +#ifdef RT_BACKTRACE_FUNCTION_NAME +static char *unwind_get_function_name(void *address) +{ + uint32_t flag_word = *(uint32_t *)((char*)address - 4); + + if ((flag_word & 0xff000000) == 0xff000000) + { + return (char *)((char*)address - 4 - (flag_word & 0x00ffffff)); + } + return RT_NULL; +} +#endif +/* + * Unwind a single frame starting with *sp for the symbol at *pc. It + * updates the *pc and *sp with the new values. + */ +int unwind_frame(struct stackframe *frame, const struct unwind_idx **origin_idx, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]) +{ + unsigned long low; + const struct unwind_idx *idx; + struct unwind_ctrl_block ctrl; + struct rt_thread *rt_c_thread; + + /* store the highest address on the stack to avoid crossing it*/ + low = frame->sp; + rt_c_thread = rt_thread_self(); + ctrl.sp_high = (unsigned long)((char*)rt_c_thread->stack_addr + rt_c_thread->stack_size); + + LOG_D("%s(pc = %08lx lr = %08lx sp = %08lx)", __func__, + frame->pc, frame->lr, frame->sp); + + idx = unwind_find_idx(frame->pc, origin_idx, exidx_start, exidx_end); + if (!idx) + { + LOG_W("unwind: Index not found %08lx", frame->pc); + return -URC_FAILURE; + } + +#ifdef RT_BACKTRACE_FUNCTION_NAME + { + char *fun_name; + fun_name = unwind_get_function_name((void *)prel31_to_addr(&idx->addr_offset)); + if (fun_name) + { + rt_kprintf("0x%08x @ %s\n", frame->pc, fun_name); + } + } +#endif + + ctrl.vrs[FP] = frame->fp; + ctrl.vrs[SP] = frame->sp; + ctrl.vrs[LR] = frame->lr; + ctrl.vrs[PC] = 0; + + if (idx->insn == 1) + /* can't unwind */ + return -URC_FAILURE; + else if ((idx->insn & 0x80000000) == 0) + /* prel31 to the unwind table */ + ctrl.insn = (unsigned long *)prel31_to_addr(&idx->insn); + else if ((idx->insn & 0xff000000) == 0x80000000) + /* only personality routine 0 supported in the index */ + ctrl.insn = &idx->insn; + else + { + LOG_W("unwind: Unsupported personality routine %08lx in the index at %x", + idx->insn, idx); + return -URC_FAILURE; + } + + /* check the personality routine */ + if ((*ctrl.insn & 0xff000000) == 0x80000000) + { + ctrl.byte = 2; + ctrl.entries = 1; + } + else if ((*ctrl.insn & 0xff000000) == 0x81000000) + { + ctrl.byte = 1; + ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16); + } + else + { + LOG_W("unwind: Unsupported personality routine %08lx at %x", + *ctrl.insn, ctrl.insn); + return -URC_FAILURE; + } + + ctrl.check_each_pop = 0; + + while (ctrl.entries > 0) + { + int urc; + if ((ctrl.sp_high - ctrl.vrs[SP]) < sizeof(ctrl.vrs)) + ctrl.check_each_pop = 1; + urc = unwind_exec_insn(&ctrl); + if (urc < 0) + return urc; + if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= ctrl.sp_high) + return -URC_FAILURE; + } + + if (ctrl.vrs[PC] == 0) + ctrl.vrs[PC] = ctrl.vrs[LR]; + + /* check for infinite loop */ + if (frame->pc == ctrl.vrs[PC]) + return -URC_FAILURE; + + frame->fp = ctrl.vrs[FP]; + frame->sp = ctrl.vrs[SP]; + frame->lr = ctrl.vrs[LR]; + frame->pc = ctrl.vrs[PC]; + + return URC_OK; +} + +void unwind_backtrace(struct pt_regs *regs, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]) +{ + struct stackframe frame; + const struct unwind_idx *origin_idx = RT_NULL; + + LOG_D("%s(regs = %x)", __func__, regs); + + arm_get_current_stackframe(regs, &frame); + +#ifndef RT_BACKTRACE_FUNCTION_NAME + rt_kprintf("please use: addr2line -e rtthread.elf -a -f %08x", frame.pc); +#endif + LOG_D("pc = %08x, sp = %08x", frame.pc, frame.sp); + + while (1) + { + int urc; + + urc = unwind_frame(&frame, &origin_idx, exidx_start, exidx_end); + if (urc < 0) + break; + //dump_backtrace_entry(where, frame.pc, frame.sp - 4); +#ifndef RT_BACKTRACE_FUNCTION_NAME + rt_kprintf(" %08x", frame.pc); +#endif + LOG_D("from: pc = %08x, frame = %08x", frame.pc, frame.sp - 4); + } + rt_kprintf("\n"); +} + +extern const struct unwind_idx __exidx_start[]; +extern const struct unwind_idx __exidx_end[]; + +void rt_unwind(struct rt_hw_exp_stack *regs, unsigned int pc_adj) +{ + struct pt_regs e_regs; + + e_regs.ARM_fp = regs->fp; + e_regs.ARM_sp = regs->sp; + e_regs.ARM_lr = regs->lr; + e_regs.ARM_pc = regs->pc - pc_adj; +#ifdef RT_USING_USERSPACE + if (!lwp_user_accessable((void *)e_regs.ARM_pc, sizeof (void *))) + { + e_regs.ARM_pc = regs->lr - sizeof(void *); + } +#endif + rt_kprintf("backtrace:\n"); + unwind_backtrace(&e_regs, __exidx_start, __exidx_end); +} + +void rt_backtrace(void) +{ + struct rt_hw_exp_stack regs; + + asm volatile ("mov %0, fp":"=r"(regs.fp)); + asm volatile ("mov %0, sp":"=r"(regs.sp)); + asm volatile ("mov %0, lr":"=r"(regs.lr)); + asm volatile ("mov %0, pc":"=r"(regs.pc)); + rt_unwind(®s, 8); +} + diff --git a/libcpu/arm/cortex-a/backtrace.h b/libcpu/arm/cortex-a/backtrace.h new file mode 100644 index 0000000000000000000000000000000000000000..a6ed226094d434abbc034b7618863a28c3508742 --- /dev/null +++ b/libcpu/arm/cortex-a/backtrace.h @@ -0,0 +1,83 @@ +#ifndef __BACKTRACE_H +#define __BACKTRACE_H + +#ifndef __ASSEMBLY__ +#include + +/* Unwind reason code according the the ARM EABI documents */ +enum unwind_reason_code +{ + URC_OK = 0, /* operation completed successfully */ + URC_CONTINUE_UNWIND = 8, + URC_FAILURE = 9 /* unspecified failure of some kind */ +}; + +struct unwind_idx +{ + unsigned long addr_offset; + unsigned long insn; +}; + +struct unwind_table +{ + const struct unwind_idx *start; + const struct unwind_idx *origin; + const struct unwind_idx *stop; + unsigned long begin_addr; + unsigned long end_addr; +}; + +struct stackframe +{ + /* + * FP member should hold R7 when CONFIG_THUMB2_KERNEL is enabled + * and R11 otherwise. + */ + unsigned long fp; + unsigned long sp; + unsigned long lr; + unsigned long pc; +}; + +struct pt_regs +{ + unsigned long uregs[18]; +}; + +#define ARM_cpsr uregs[16] +#define ARM_pc uregs[15] +#define ARM_lr uregs[14] +#define ARM_sp uregs[13] +#define ARM_ip uregs[12] +#define ARM_fp uregs[11] +#define ARM_r10 uregs[10] +#define ARM_r9 uregs[9] +#define ARM_r8 uregs[8] +#define ARM_r7 uregs[7] +#define ARM_r6 uregs[6] +#define ARM_r5 uregs[5] +#define ARM_r4 uregs[4] +#define ARM_r3 uregs[3] +#define ARM_r2 uregs[2] +#define ARM_r1 uregs[1] +#define ARM_r0 uregs[0] +#define ARM_ORIG_r0 uregs[17] + +#define instruction_pointer(regs) (regs)->ARM_pc + +#ifdef CONFIG_THUMB2_KERNEL +#define frame_pointer(regs) (regs)->ARM_r7 +#else +#define frame_pointer(regs) (regs)->ARM_fp +#endif + +int unwind_frame(struct stackframe *frame, const struct unwind_idx **origin_idx, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]); +void unwind_backtrace(struct pt_regs *regs, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]); + +void rt_unwind(struct rt_hw_exp_stack *regs, unsigned int pc_adj); +void rt_backtrace(void); + +#endif /* !__ASSEMBLY__ */ + +#endif /* __BACKTRACE_H */ + diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c index 30af86baa125b97ae3749b9ae3ed8cc1d66ebe03..411c9838bff03d220347078fcc88e2c2de8e90c3 100644 --- a/libcpu/arm/cortex-a/cache.c +++ b/libcpu/arm/cortex-a/cache.c @@ -31,8 +31,8 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size) rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; asm volatile ("dmb":::"memory"); - start_addr &= ~(line_size-1); - end_addr &= ~(line_size-1); + start_addr &= ~(line_size - 1); + end_addr &= ~(line_size - 1); while (start_addr < end_addr) { asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr)); /* icimvau */ @@ -48,8 +48,8 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size) rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; asm volatile ("dmb":::"memory"); - start_addr &= ~(line_size-1); - end_addr &= ~(line_size-1); + start_addr &= ~(line_size - 1); + end_addr &= ~(line_size - 1); while (start_addr < end_addr) { asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */ @@ -65,8 +65,8 @@ void rt_hw_cpu_dcache_clean(void *addr, int size) rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; asm volatile ("dmb":::"memory"); - start_addr &= ~(line_size-1); - end_addr &= ~(line_size-1); + start_addr &= ~(line_size - 1); + end_addr &= ~(line_size - 1); while (start_addr < end_addr) { asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */ @@ -75,18 +75,42 @@ void rt_hw_cpu_dcache_clean(void *addr, int size) asm volatile ("dsb":::"memory"); } +void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size) +{ + rt_uint32_t line_size = rt_cpu_dcache_line_size(); + rt_uint32_t start_addr = (rt_uint32_t)addr; + rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + + asm volatile ("dmb":::"memory"); + start_addr &= ~(line_size - 1); + end_addr &= ~(line_size - 1); + while (start_addr < end_addr) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */ + asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */ + start_addr += line_size; + } + asm volatile ("dsb":::"memory"); +} + void rt_hw_cpu_icache_ops(int ops, void *addr, int size) { if (ops == RT_HW_CACHE_INVALIDATE) + { rt_hw_cpu_icache_invalidate(addr, size); + } } void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) { if (ops == RT_HW_CACHE_FLUSH) + { rt_hw_cpu_dcache_clean(addr, size); + } else if (ops == RT_HW_CACHE_INVALIDATE) + { rt_hw_cpu_dcache_invalidate(addr, size); + } } rt_base_t rt_hw_cpu_icache_status(void) @@ -98,3 +122,26 @@ rt_base_t rt_hw_cpu_dcache_status(void) { return 0; } + +#ifdef RT_USING_LWP +#define ICACHE (1<<0) +#define DCACHE (1<<1) +#define BCACHE (ICACHE|DCACHE) + +int sys_cacheflush(void *addr, int size, int cache) +{ + if ((size_t)addr < KERNEL_VADDR_START && (size_t)addr + size <= KERNEL_VADDR_START) + { + if ((cache & DCACHE) != 0) + { + rt_hw_cpu_dcache_clean_and_invalidate(addr, size); + } + if ((cache & ICACHE) != 0) + { + rt_hw_cpu_icache_invalidate(addr, size); + } + return 0; + } + return -1; +} +#endif diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S index 768c5138e9c058739a98a98445a6b37550dcd50e..38008facdcaf84adbdb18ab5f2d9eeb6a0dcc3ee 100644 --- a/libcpu/arm/cortex-a/context_gcc.S +++ b/libcpu/arm/cortex-a/context_gcc.S @@ -45,7 +45,20 @@ rt_hw_context_switch_to: #ifdef RT_USING_SMP mov r0, r1 bl rt_cpus_lock_status_restore +#ifdef RT_USING_USERSPACE + bl rt_thread_self + bl lwp_user_setting_restore +#endif +#else +#ifdef RT_USING_USERSPACE + bl rt_thread_self + mov r4, r0 + bl lwp_mmu_switch + mov r0, r4 + bl lwp_user_setting_restore +#endif #endif /*RT_USING_SMP*/ + b rt_hw_context_switch_exit .section .bss.share.isr @@ -95,7 +108,20 @@ rt_hw_context_switch: #ifdef RT_USING_SMP mov r0, r2 bl rt_cpus_lock_status_restore +#ifdef RT_USING_USERSPACE + bl rt_thread_self + bl lwp_user_setting_restore +#endif +#else +#ifdef RT_USING_USERSPACE + bl rt_thread_self + mov r4, r0 + bl lwp_mmu_switch + mov r0, r4 + bl lwp_user_setting_restore +#endif #endif /*RT_USING_SMP*/ + b rt_hw_context_switch_exit /* @@ -123,28 +149,69 @@ rt_hw_context_switch_interrupt: * r2 :addr of to_thread's sp * r3 :to_thread's tcb */ - +#ifdef RT_USING_LWP + push {r0 - r3, lr} +#ifdef RT_USING_USERSPACE + bl rt_thread_self + bl lwp_user_setting_save +#endif + pop {r0 - r3, lr} +#endif str r0, [r1] ldr sp, [r2] mov r0, r3 +#ifdef RT_USING_USERSPACE + mov r4, r0 +#endif bl rt_cpus_lock_status_restore - +#ifdef RT_USING_USERSPACE + mov r0, r4 + bl lwp_user_setting_restore +#endif b rt_hw_context_switch_exit #else /*RT_USING_SMP*/ - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] + /* r0 :addr of from_thread's sp + * r1 :addr of to_thread's sp + * r2 :from_thread's tcb + * r3 :to_thread's tcb + */ +#ifdef RT_USING_LWP + /* now to_thread(r3) not used */ + ldr ip, =rt_thread_switch_interrupt_flag + ldr r3, [ip] + cmp r3, #1 + beq _reswitch + ldr r3, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + str r0, [r3] + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r3, [ip] +#ifdef RT_USING_USERSPACE + push {r1, lr} + mov r0, r2 + bl lwp_user_setting_save + pop {r1, lr} +#endif +_reswitch: + ldr ip, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [ip] + bx lr +#else + /* now from_thread(r2) to_thread(r3) not used */ + ldr ip, =rt_thread_switch_interrupt_flag + ldr r3, [ip] cmp r3, #1 beq _reswitch - ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + ldr r3, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + str r0, [r3] mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r0, [ip] - str r3, [r2] + str r3, [ip] _reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] + ldr ip, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [ip] bx lr +#endif #endif /*RT_USING_SMP*/ .global rt_hw_context_switch_exit @@ -178,5 +245,29 @@ rt_hw_context_switch_exit: #endif ldmfd sp!, {r1} msr spsr_cxsf, r1 /* original mode */ + +#ifdef RT_USING_GDBSERVER + bl lwp_check_debug +#endif + +#ifdef RT_USING_LWP + bl lwp_check_exit +#endif + +#ifdef RT_USING_LWP + and r1, #0x1f + cmp r1, #0x10 + bne 1f + ldmfd sp!, {r0-r12,lr} + ldmfd sp!, {lr} + b ret_to_user +1: +#endif ldmfd sp!, {r0-r12,lr,pc}^ /* irq return */ +#ifdef RT_USING_FPU +.global set_fpexc +set_fpexc: + vmsr fpexc, r0 + bx lr +#endif diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h index 97c5b93ad24a1bf21488f6b9d3fa0664b0ab73d7..dc77ec74c360fa1217022657a520f9f205f8032d 100644 --- a/libcpu/arm/cortex-a/cp15.h +++ b/libcpu/arm/cortex-a/cp15.h @@ -10,6 +10,15 @@ #ifndef __CP15_H__ #define __CP15_H__ +#define __get_cp(cp, op1, Rt, CRn, CRm, op2) \ + __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_cp(cp, op1, Rt, CRn, CRm, op2) \ + __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_cp64(cp, op1, Rt, CRm) \ + __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_cp64(cp, op1, Rt, CRm) \ + __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + unsigned long rt_cpu_get_smp_id(void); void rt_cpu_mmu_disable(void); diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpuport.c similarity index 90% rename from libcpu/arm/cortex-a/cpu.c rename to libcpu/arm/cortex-a/cpuport.c index 7c6bf58a4bea14dbaa6c440b7ba7ae5a099c108d..8087cfff1d12bfe821c57505ec6986ba7db39aba 100644 --- a/libcpu/arm/cortex-a/cpu.c +++ b/libcpu/arm/cortex-a/cpuport.c @@ -13,18 +13,18 @@ #include #include -#ifdef RT_USING_SMP - int rt_hw_cpu_id(void) { int cpu_id; __asm__ volatile ( "mrc p15, 0, %0, c0, c0, 5" :"=r"(cpu_id) - ); + ); cpu_id &= 0xf; return cpu_id; -}; +} + +#ifdef RT_USING_SMP void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) { @@ -40,7 +40,7 @@ void rt_hw_spin_lock(rt_hw_spinlock_t *lock) __asm__ __volatile__( "pld [%0]" ::"r"(&lock->slock) - ); + ); __asm__ __volatile__( "1: ldrex %0, [%3]\n" @@ -52,9 +52,10 @@ void rt_hw_spin_lock(rt_hw_spinlock_t *lock) : "r" (&lock->slock), "I" (1 << 16) : "cc"); - while (lockval.tickets.next != lockval.tickets.owner) { + while (lockval.tickets.next != lockval.tickets.owner) + { __asm__ __volatile__("wfe":::"memory"); - lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); + lockval.tickets.owner = *(volatile unsigned short *) (&lock->tickets.owner); } __asm__ volatile ("dmb":::"memory"); @@ -77,6 +78,7 @@ void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) void rt_hw_cpu_shutdown() { rt_uint32_t level; + rt_kprintf("shutdown...\n"); level = rt_hw_interrupt_disable(); diff --git a/libcpu/arm/cortex-a/armv7.h b/libcpu/arm/cortex-a/cpuport.h similarity index 33% rename from libcpu/arm/cortex-a/armv7.h rename to libcpu/arm/cortex-a/cpuport.h index d22f72fa68c80ffa24aab57197dba327c33b8ffc..a462182390a14eff4587b315c5bb0fed955aafc2 100644 --- a/libcpu/arm/cortex-a/armv7.h +++ b/libcpu/arm/cortex-a/cpuport.h @@ -1,54 +1,55 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -#ifndef __ARMV7_H__ -#define __ARMV7_H__ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; struct rt_hw_stack { - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; }; #define USERMODE 0x10 @@ -69,4 +70,29 @@ struct rt_hw_stack #define E_Bit (1<<9) #define J_Bit (1<<24) +#ifdef RT_USING_SMP +typedef union { + unsigned long slock; + struct __arch_tickets { + unsigned short owner; + unsigned short next; + } tickets; +} rt_hw_spinlock_t; #endif + +rt_inline void rt_hw_isb(void) +{ + asm volatile ("isb":::"memory"); +} + +rt_inline void rt_hw_dmb(void) +{ + asm volatile ("dmb":::"memory"); +} + +rt_inline void rt_hw_dsb(void) +{ + asm volatile ("dsb":::"memory"); +} + +#endif /*CPUPORT_H__*/ diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index 2e94b882770243ee2e1f4c475fba81704aa5865f..00beebb138c3546e6e0f286ef05db7022539fc69 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,29 +28,35 @@ struct arm_gic /* 'ARM_GIC_MAX_NR' is the number of cores */ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) - -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) + +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) static unsigned int _gic_max_irq; @@ -67,12 +73,12 @@ int arm_gic_get_active_irq(rt_uint32_t index) void arm_gic_ack(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; @@ -80,36 +86,136 @@ void arm_gic_ack(rt_uint32_t index, int irq) void arm_gic_mask(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; } -void arm_gic_clear_pending(rt_uint32_t index, int irq) +void arm_gic_umask(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t pend; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void arm_gic_set_pending_irq(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config) +{ + rt_uint32_t icfgr; + rt_uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); } void arm_gic_clear_active(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; } @@ -122,79 +228,150 @@ void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); - old_tgt |= cpumask << ((irq % 4)*8); + old_tgt &= ~(0x0FFUL << ((irq % 4U)*8U)); + old_tgt |= cpumask << ((irq % 4U)*8U); GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; } -void arm_gic_umask(rt_uint32_t index, int irq) +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask; RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; } -void arm_gic_dump_type(rt_uint32_t index) +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) { - unsigned int gic_type; + RT_ASSERT(index < ARM_GIC_MAX_NR); - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1 << 10) ? "has" : "no", - gic_type); + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; } -void arm_gic_dump(rt_uint32_t index) +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) { - unsigned int i, k; + RT_ASSERT(index < ARM_GIC_MAX_NR); - k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); - rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); - rt_kprintf("--- hw mask ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw pending ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw active ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n"); + /* set priority mask */ + GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base) = priority & 0xFFUL; +} + +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) +{ + GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base) = binary_point & 0x7U; +} + +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) +{ + return GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base); +} + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) +{ + rt_uint32_t pending; + rt_uint32_t active; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = + ((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL); +} + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); +} + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) +{ + uint32_t igroupr; + uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT(group <= 1U); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ((group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; } -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); -#endif int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) { unsigned int gic_type, i; - rt_uint32_t cpumask = 1 << 0; + rt_uint32_t cpumask = 1U << 0U; RT_ASSERT(index < ARM_GIC_MAX_NR); @@ -203,50 +380,66 @@ int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) /* Find out how many interrupts are supported. */ gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; /* * The GIC only supports up to 1020 interrupt sources. * Limit this to either the architected maximum, or the * platform maximum. */ - if (_gic_max_irq > 1020) - _gic_max_irq = 1020; + if (_gic_max_irq > 1020U) + { + _gic_max_irq = 1020U; + } if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + { _gic_max_irq = ARM_GIC_NR_IRQS; + } - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - cpumask |= cpumask << 24; + cpumask |= cpumask << 8U; + cpumask |= cpumask << 16U; + cpumask |= cpumask << 24U; - GIC_DIST_CTRL(dist_base) = 0x0; + GIC_DIST_CTRL(dist_base) = 0x0U; /* Set all global interrupts to be level triggered, active low. */ - for (i = 32; i < _gic_max_irq; i += 16) - GIC_DIST_CONFIG(dist_base, i) = 0x0; + for (i = 32U; i < _gic_max_irq; i += 16U) + { + GIC_DIST_CONFIG(dist_base, i) = 0x0U; + } /* Set all global interrupts to this CPU only. */ - for (i = 32; i < _gic_max_irq; i += 4) + for (i = 32U; i < _gic_max_irq; i += 4U) + { GIC_DIST_TARGET(dist_base, i) = cpumask; + } /* Set priority on all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 4) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + for (i = 0U; i < _gic_max_irq; i += 4U) + { + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; + } /* Disable all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; + } -#if 0 /* All interrupts defaults to IGROUP1(IRQ). */ + /* for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; -#endif - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_IGROUP(dist_base, i) = 0; + { + GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; + } + */ + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_IGROUP(dist_base, i) = 0U; + } /* Enable group0 and group1 interrupt forwarding. */ - GIC_DIST_CTRL(dist_base) = 0x01; + GIC_DIST_CTRL(dist_base) = 0x01U; return 0; } @@ -255,46 +448,69 @@ int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) { RT_ASSERT(index < ARM_GIC_MAX_NR); - _gic_table[index].cpu_hw_base = cpu_base; + if (!_gic_table[index].cpu_hw_base) + { + _gic_table[index].cpu_hw_base = cpu_base; + } + cpu_base = _gic_table[index].cpu_hw_base; - GIC_CPU_PRIMASK(cpu_base) = 0xf0; - GIC_CPU_BINPOINT(cpu_base) = 0x7; + GIC_CPU_PRIMASK(cpu_base) = 0xf0U; + GIC_CPU_BINPOINT(cpu_base) = 0x7U; /* Enable CPU interrupt */ - GIC_CPU_CTRL(cpu_base) = 0x01; + GIC_CPU_CTRL(cpu_base) = 0x01U; return 0; } -void arm_gic_set_group(rt_uint32_t index, int vector, int group) +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) { - /* As for GICv2, there are only group0 and group1. */ - RT_ASSERT(group <= 1); - RT_ASSERT(vector < _gic_max_irq); + unsigned int i, k; - if (group == 0) + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) &= ~(1 << (vector % 32)); + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); } - else if (group == 1) + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) |= (1 << (vector % 32)); + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n"); } -#ifdef RT_USING_SMP -void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) - { - /* note: ipi_vector maybe different with irq_vector */ - GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector; -} -#endif - -#ifdef RT_USING_SMP -void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +long gic_dump(void) { - /* note: ipi_vector maybe different with irq_vector */ - rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); + arm_gic_dump_type(0); + arm_gic_dump(0); + + return 0; } -#endif +MSH_CMD_EXPORT(gic_dump, show gic status); + diff --git a/libcpu/arm/cortex-a/gic.h b/libcpu/arm/cortex-a/gic.h index a16d0467fb31d87a6a01baf35478d2acf4990737..e74b760f4521122431ed67ec22981cc303deb298 100644 --- a/libcpu/arm/cortex-a/gic.h +++ b/libcpu/arm/cortex-a/gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,19 +14,46 @@ #include #include -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); void arm_gic_mask(rt_uint32_t index, int irq); void arm_gic_umask(rt_uint32_t index, int irq); -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); -void arm_gic_set_group(rt_uint32_t index, int vector, int group); -int arm_gic_get_active_irq(rt_uint32_t index); -void arm_gic_ack(rt_uint32_t index, int irq); +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq); +void arm_gic_set_pending_irq(rt_uint32_t index, int irq); +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq); + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config); +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq); void arm_gic_clear_active(rt_uint32_t index, int irq); -void arm_gic_clear_pending(rt_uint32_t index, int irq); + +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq); + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority); +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq); + +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority); +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index); + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point); +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index); + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq); + +void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list); + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index); + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index); + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group); +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq); + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); void arm_gic_dump_type(rt_uint32_t index); void arm_gic_dump(rt_uint32_t index); diff --git a/libcpu/arm/cortex-a/gtimer.c b/libcpu/arm/cortex-a/gtimer.c new file mode 100644 index 0000000000000000000000000000000000000000..b193a1593de08df6189ca91554e121ee56d4d2e2 --- /dev/null +++ b/libcpu/arm/cortex-a/gtimer.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#include "cp15.h" +#include + +/** Set CNTFRQ + * This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * @param value: CNTFRQ Register value to set + */ +static inline void __set_cntfrq(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 0, 0); +} + +/** Get CNTFRQ + * This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * return CNTFRQ Register value + */ +static inline rt_uint32_t __get_cntfrq(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 0 , 0); + return result; +} + +/** Set CNTP_TVAL + * This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + * param value: CNTP_TVAL Register value to set + */ +static inline void __set_cntp_tval(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 0); +} + +/** Get CNTP_TVAL + * This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + * return CNTP_TVAL Register value + */ +static inline rt_uint32_t __get_cntp_tval(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 0); + return result; +} + +/** Get CNTPCT + * This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + * return CNTPCT Register value + */ +static inline rt_uint64_t __get_cntpct(void) +{ + rt_uint64_t result; + __get_cp64(15, 0, result, 14); + return result; +} + +/** Set CNTP_CVAL + * This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * param value: CNTP_CVAL Register value to set +*/ +static inline void __set_cntp_cval(rt_uint64_t value) +{ + __set_cp64(15, 2, value, 14); +} + +/** Get CNTP_CVAL + * This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * return CNTP_CVAL Register value + */ +static inline rt_uint64_t __get_cntp_cval(void) +{ + rt_uint64_t result; + __get_cp64(15, 2, result, 14); + return result; +} + +/** Set CNTP_CTL + * This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + * param value: CNTP_CTL Register value to set + */ +static inline void __set_cntp_ctl(uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 1); +} + +/** Get CNTP_CTL register + * return CNTP_CTL Register value + */ +static inline rt_uint32_t __get_cntp_ctl(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 1); + return result; +} + +/** Configures the frequency the timer shall run at. + * param value The timer frequency in Hz. + */ +void gtimer_set_counter_frequency(rt_uint32_t value) +{ + __set_cntfrq(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Sets the reset value of the timer. + * param value: The value the timer is loaded with. + */ +void gtimer_set_load_value(rt_uint32_t value) +{ + __set_cntp_tval(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the current counter value. + * return Current counter value. + */ +rt_uint32_t gtimer_get_current_value(void) +{ + return(__get_cntp_tval()); +} + +/** Get the current physical counter value. + * return Current physical counter value. + */ +rt_uint64_t gtimer_get_current_physical_value(void) +{ + return(__get_cntpct()); +} + +/** Set the physical compare value. + * param value: New physical timer compare value. + */ +void gtimer_set_physical_compare_value(rt_uint64_t value) +{ + __set_cntp_cval(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the physical compare value. + * return Physical compare value. + */ +rt_uint64_t gtimer_get_physical_compare_value(void) +{ + return(__get_cntp_cval()); +} + +/** Configure the timer by setting the control value. + * param value: New timer control value. + */ +void gtimer_set_control(rt_uint32_t value) +{ + __set_cntp_ctl(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the control value. + * return Control value. + */ +rt_uint32_t gtimer_get_control(void) +{ + return(__get_cntp_ctl()); +} + diff --git a/libcpu/arm/cortex-a/gtimer.h b/libcpu/arm/cortex-a/gtimer.h new file mode 100644 index 0000000000000000000000000000000000000000..160d0cefde5a31f0eee2c05520ff93db8b1cbd3d --- /dev/null +++ b/libcpu/arm/cortex-a/gtimer.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#ifndef __GTIMER_H__ +#define __GTIMER_H__ + +#include + +void gtimer_set_counter_frequency(rt_uint32_t value); +void gtimer_set_load_value(rt_uint32_t value); +rt_uint32_t gtimer_get_current_value(void); +rt_uint64_t gtimer_get_current_physical_value(void); +void gtimer_set_physical_compare_value(rt_uint64_t value); +rt_uint64_t gtimer_get_physical_compare_value(void); +void gtimer_set_control(rt_uint32_t value); +rt_uint32_t gtimer_get_control(void); + +#endif + diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index b7a70719a9024741d0d39e10af0f3551780c274f..a93d816d21fceefd8bef056601946805e7523a20 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -14,12 +14,11 @@ #include "interrupt.h" #include "gic.h" - /* exception and interrupt handler table */ struct rt_irq_desc isr_table[MAX_HANDLERS]; #ifndef RT_USING_SMP -/* Those varibles will be accessed in ISR, so we need to share them. */ +/* Those variables will be accessed in ISR, so we need to share them. */ rt_uint32_t rt_interrupt_from_thread = 0; rt_uint32_t rt_interrupt_to_thread = 0; rt_uint32_t rt_thread_switch_interrupt_flag = 0; @@ -29,6 +28,23 @@ const unsigned int VECTOR_BASE = 0x00; extern void rt_cpu_vector_set_base(unsigned int addr); extern int system_vectors; +#ifdef RT_USING_SMP +#define rt_interrupt_nest rt_cpu_self()->irq_nest +#else +extern volatile rt_uint8_t rt_interrupt_nest; +#endif + +#ifdef SOC_BCM283x +static void default_isr_handler(int vector, void *param) +{ +#ifdef RT_USING_SMP + rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector); +#else + rt_kprintf("unhandled irq: %d\n",vector); +#endif +} +#endif + void rt_hw_vector_init(void) { rt_cpu_vector_set_base((unsigned int)&system_vectors); @@ -39,6 +55,34 @@ void rt_hw_vector_init(void) */ void rt_hw_interrupt_init(void) { +#ifdef SOC_BCM283x + rt_uint32_t index; + /* initialize vector table */ + rt_hw_vector_init(); + + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + + /* mask all of interrupts */ + IRQ_DISABLE_BASIC = 0x000000ff; + IRQ_DISABLE1 = 0xffffffff; + IRQ_DISABLE2 = 0xffffffff; + for (index = 0; index < MAX_HANDLERS; index ++) + { + isr_table[index].handler = default_isr_handler; + isr_table[index].param = RT_NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX); + isr_table[index].counter = 0; +#endif + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +#else rt_uint32_t gic_cpu_base; rt_uint32_t gic_dist_base; rt_uint32_t gic_irq_start; @@ -50,13 +94,19 @@ void rt_hw_interrupt_init(void) rt_memset(isr_table, 0x00, sizeof(isr_table)); /* initialize ARM GIC */ +#ifdef RT_USING_USERSPACE + gic_dist_base = (uint32_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_dist_base(), 0x2000, MMU_MAP_K_RW); + gic_cpu_base = (uint32_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_cpu_base(), 0x1000, MMU_MAP_K_RW); +#else gic_dist_base = platform_get_gic_dist_base(); gic_cpu_base = platform_get_gic_cpu_base(); +#endif gic_irq_start = GIC_IRQ_START; arm_gic_dist_init(0, gic_dist_base, gic_irq_start); arm_gic_cpu_init(0, gic_cpu_base); +#endif } /** @@ -65,7 +115,24 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { +#ifdef SOC_BCM283x + if (vector < 32) + { + IRQ_DISABLE1 = (1 << vector); + } + else if (vector < 64) + { + vector = vector % 32; + IRQ_DISABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_DISABLE_BASIC = (1 << vector); + } +#else arm_gic_mask(0, vector); +#endif } /** @@ -74,7 +141,24 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { +#ifdef SOC_BCM283x +if (vector < 32) + { + IRQ_ENABLE1 = (1 << vector); + } + else if (vector < 64) + { + vector = vector % 32; + IRQ_ENABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_ENABLE_BASIC = (1 << vector); + } +#else arm_gic_umask(0, vector); +#endif } /** @@ -83,7 +167,11 @@ void rt_hw_interrupt_umask(int vector) */ int rt_hw_interrupt_get_irq(void) { - return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; +#ifndef SOC_BCM283x + return arm_gic_get_active_irq(0); +#else + return 0; +#endif } /** @@ -92,8 +180,154 @@ int rt_hw_interrupt_get_irq(void) */ void rt_hw_interrupt_ack(int vector) { +#ifndef SOC_BCM283x arm_gic_ack(0, vector); +#endif +} + +/** + * This function set interrupt CPU targets. + * @param vector: the interrupt number + * cpu_mask: target cpus mask, one bit for one core + */ +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask) +{ + arm_gic_set_cpu(0, vector, cpu_mask); +} + +/** + * This function get interrupt CPU targets. + * @param vector: the interrupt number + * @return target cpus mask, one bit for one core + */ +unsigned int rt_hw_interrupt_get_target_cpus(int vector) +{ + return arm_gic_get_target_cpu(0, vector); +} + +/** + * This function set interrupt triger mode. + * @param vector: the interrupt number + * mode: interrupt triger mode; 0: level triger, 1: edge triger + */ +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode) +{ + arm_gic_set_configuration(0, vector, mode); } + +/** + * This function get interrupt triger mode. + * @param vector: the interrupt number + * @return interrupt triger mode; 0: level triger, 1: edge triger + */ +unsigned int rt_hw_interrupt_get_triger_mode(int vector) +{ + return arm_gic_get_configuration(0, vector); +} + +/** + * This function set interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_set_pending(int vector) +{ + arm_gic_set_pending_irq(0, vector); +} + +/** + * This function get interrupt pending flag. + * @param vector: the interrupt number + * @return interrupt pending flag, 0: not pending; 1: pending + */ +unsigned int rt_hw_interrupt_get_pending(int vector) +{ + return arm_gic_get_pending_irq(0, vector); +} + +/** + * This function clear interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_clear_pending(int vector) +{ + arm_gic_clear_pending_irq(0, vector); +} + +/** + * This function set interrupt priority value. + * @param vector: the interrupt number + * priority: the priority of interrupt to set + */ +void rt_hw_interrupt_set_priority(int vector, unsigned int priority) +{ + arm_gic_set_priority(0, vector, priority); +} + +/** + * This function get interrupt priority. + * @param vector: the interrupt number + * @return interrupt priority value + */ +unsigned int rt_hw_interrupt_get_priority(int vector) +{ + return arm_gic_get_priority(0, vector); +} + +/** + * This function set priority masking threshold. + * @param priority: priority masking threshold + */ +void rt_hw_interrupt_set_priority_mask(unsigned int priority) +{ + arm_gic_set_interface_prior_mask(0, priority); +} + +/** + * This function get priority masking threshold. + * @param none + * @return priority masking threshold + */ +unsigned int rt_hw_interrupt_get_priority_mask(void) +{ + return arm_gic_get_interface_prior_mask(0); +} + +/** + * This function set priority grouping field split point. + * @param bits: priority grouping field split point + * @return 0: success; -1: failed + */ +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits) +{ + int status; + + if (bits < 8) + { + arm_gic_set_binary_point(0, (7 - bits)); + status = 0; + } + else + { + status = -1; + } + + return (status); +} + +/** + * This function get priority grouping field split point. + * @param none + * @return priority grouping field split point + */ +unsigned int rt_hw_interrupt_get_prior_group_bits(void) +{ + unsigned int bp; + + bp = arm_gic_get_binary_point(0) & 0x07; + + return (7 - bp); +} + /** * This function will install a interrupt service routine to a interrupt. * @param vector the interrupt number @@ -121,3 +355,17 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, return old_handler; } + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0); +} + +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif + diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h index 442187edee23565f72f5592ea722d034ae22c607..1c4199c61bd197a475cf10c95e27e12a80908d52 100644 --- a/libcpu/arm/cortex-a/interrupt.h +++ b/libcpu/arm/cortex-a/interrupt.h @@ -17,9 +17,10 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -void rt_hw_vector_init(void); +#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ +#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ -void rt_hw_interrupt_control(int vector, int priority, int route); +void rt_hw_vector_init(void); void rt_hw_interrupt_init(void); void rt_hw_interrupt_mask(int vector); @@ -28,7 +29,32 @@ void rt_hw_interrupt_umask(int vector); int rt_hw_interrupt_get_irq(void); void rt_hw_interrupt_ack(int vector); +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask); +unsigned int rt_hw_interrupt_get_target_cpus(int vector); + +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode); +unsigned int rt_hw_interrupt_get_triger_mode(int vector); + +void rt_hw_interrupt_set_pending(int vector); +unsigned int rt_hw_interrupt_get_pending(int vector); +void rt_hw_interrupt_clear_pending(int vector); + +void rt_hw_interrupt_set_priority(int vector, unsigned int priority); +unsigned int rt_hw_interrupt_get_priority(int vector); + +void rt_hw_interrupt_set_priority_mask(unsigned int priority); +unsigned int rt_hw_interrupt_get_priority_mask(void); + +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits); +unsigned int rt_hw_interrupt_get_prior_group_bits(void); + rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask); +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); #endif + +#endif + diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c index 1260f41fe52dbac75f9bb0d2f6ec6e17a8a27305..ea2cadae6f192ecae1e312450b260cc9dc3bc458 100644 --- a/libcpu/arm/cortex-a/mmu.c +++ b/libcpu/arm/cortex-a/mmu.c @@ -15,6 +15,10 @@ #include "cp15.h" #include "mmu.h" +#ifdef RT_USING_USERSPACE +#include "page.h" +#endif + /* dump 2nd level page table */ void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) { @@ -123,7 +127,7 @@ void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) } /* level1 page table, each entry for 1MB memory. */ -volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, @@ -150,6 +154,7 @@ unsigned long rt_hw_set_domain_register(unsigned long domain_val) return old_domain; } +void rt_hw_cpu_dcache_clean(void *addr, int size); void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) { /* set page table */ @@ -159,6 +164,7 @@ void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) mdesc->paddr_start, mdesc->attr); mdesc++; } + rt_hw_cpu_dcache_clean((void*)MMUTable, sizeof MMUTable); } void rt_hw_mmu_init(void) @@ -180,3 +186,683 @@ void rt_hw_mmu_init(void) rt_hw_cpu_dcache_enable(); } +/* + mem map +*/ + +void rt_hw_cpu_dcache_clean(void *addr, int size); + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off) +{ + size_t l1_off, va_s, va_e; + rt_base_t level; + + if (!mmu_info || !vtable) + { + return -1; + } + + va_s = (size_t)v_address; + va_e = (size_t)v_address + size - 1; + + if ( va_e < va_s) + { + return -1; + } + + va_s >>= ARCH_SECTION_SHIFT; + va_e >>= ARCH_SECTION_SHIFT; + + if (va_s == 0) + { + return -1; + } + + level = rt_hw_interrupt_disable(); + + for (l1_off = va_s; l1_off <= va_e; l1_off++) + { + size_t v = vtable[l1_off]; + + if (v & ARCH_MMU_USED_MASK) + { + rt_hw_interrupt_enable(level); + return -1; + } + } + + mmu_info->vtable = vtable; + mmu_info->vstart = va_s; + mmu_info->vend = va_e; + mmu_info->pv_off = pv_off; + + rt_hw_interrupt_enable(level); + + return 0; +} + +int rt_hw_mmu_ioremap_init(rt_mmu_info *mmu_info, void* v_address, size_t size) +{ +#ifdef RT_IOREMAP_LATE + size_t loop_va; + size_t l1_off; + size_t *mmu_l1, *mmu_l2; + size_t sections; +#ifndef RT_USING_USERSPACE + size_t *ref_cnt; +#endif + + /* for kernel ioremap */ + if ((size_t)v_address < KERNEL_VADDR_START) + { + return -1; + } + /* must align to section */ + if ((size_t)v_address & ARCH_SECTION_MASK) + { + return -1; + } + /* must align to section */ + if (size & ARCH_SECTION_MASK) + { + return -1; + } + + loop_va = (size_t)v_address; + sections = (size >> ARCH_SECTION_SHIFT); + while (sections--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + RT_ASSERT((*mmu_l1 & ARCH_MMU_USED_MASK) == 0); +#ifdef RT_USING_USERSPACE + mmu_l2 = (size_t*)rt_pages_alloc(0); +#else + mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); +#endif + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); + + *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + else + { + /* error */ + return -1; + } + +#ifndef RT_USING_USERSPACE + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE / ARCH_PAGE_SIZE); + *ref_cnt = 1; +#endif + + loop_va += ARCH_SECTION_SIZE; + } +#endif + return 0; +} + +static size_t find_vaddr(rt_mmu_info *mmu_info, int pages) +{ + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t find_off = 0; + size_t find_va = 0; + int n = 0; + + if (!pages) + { + return 0; + } + + if (!mmu_info) + { + return 0; + } + + for (l1_off = mmu_info->vstart; l1_off <= mmu_info->vend; l1_off++) + { + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + for (l2_off = 0; l2_off < (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); l2_off++) + { + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + /* in use */ + n = 0; + } + else + { + if (!n) + { + find_va = l1_off; + find_off = l2_off; + } + n++; + if (n >= pages) + { + return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT); + } + } + } + } + else + { + if (!n) + { + find_va = l1_off; + find_off = 0; + } + n += (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + if (n >= pages) + { + return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT); + } + } + } + return 0; +} + +#ifdef RT_USING_USERSPACE +static int check_vaddr(rt_mmu_info *mmu_info, void *va, int pages) +{ + size_t loop_va = (size_t)va & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + + if (!pages) + { + return -1; + } + + if (!mmu_info) + { + return -1; + } + + l1_off = ((size_t)va >> ARCH_SECTION_SHIFT); + if (l1_off < mmu_info->vstart || l1_off > mmu_info->vend) + { + return -1; + } + l1_off += ((pages << ARCH_PAGE_SHIFT) >> ARCH_SECTION_SHIFT); + if (l1_off < mmu_info->vstart || l1_off > mmu_info->vend + 1) + { + return -1; + } + + while (pages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + return -1; + } + } + loop_va += ARCH_PAGE_SIZE; + } + return 0; +} +#endif + +static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; +#ifndef RT_USING_USERSPACE + size_t *ref_cnt; +#endif + + if (!mmu_info) + { + return; + } + + while (npages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + if (l1_off < mmu_info->vstart || l1_off > mmu_info->vend) + { + return; + } + + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { + return; + } + + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + *(mmu_l2 + l2_off) = 0; + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + +#ifdef RT_USING_USERSPACE + if (rt_pages_free(mmu_l2, 0)) + { + *mmu_l1 = 0; + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } +#else + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE / ARCH_PAGE_SIZE); + (*ref_cnt)--; + if (!*ref_cnt) + { + rt_free_align(mmu_l2); + *mmu_l1 = 0; + + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } +#endif + } + loop_va += ARCH_PAGE_SIZE; + } +} + +static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, size_t npages, size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa = (size_t)p_addr & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; +#ifndef RT_USING_USERSPACE + size_t *ref_cnt; +#endif + + if (!mmu_info) + { + return -1; + } + + while (npages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); +#ifdef RT_USING_USERSPACE + rt_page_ref_inc(mmu_l2, 0); +#endif + } + else + { +#ifdef RT_USING_USERSPACE + mmu_l2 = (size_t*)rt_pages_alloc(0); +#else + mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); +#endif + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); + + *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + else + { + /* error, unmap and quit */ + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; + } + } + +#ifndef RT_USING_USERSPACE + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE / ARCH_PAGE_SIZE); + (*ref_cnt)++; +#endif + + *(mmu_l2 + l2_off) = (loop_pa | attr); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + loop_va += ARCH_PAGE_SIZE; + loop_pa += ARCH_PAGE_SIZE; + } + return 0; +} + +static void rt_hw_cpu_tlb_invalidate(void) +{ + asm volatile ("mcr p15, 0, r0, c8, c7, 0\ndsb\nisb" ::: "memory"); +} + +#ifdef RT_USING_USERSPACE +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + if (!size) + { + return 0; + } + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + if (v_addr) + { + vaddr = (size_t)v_addr; + pa_s = (size_t)p_addr; + if ((vaddr & ARCH_PAGE_MASK) != (pa_s & ARCH_PAGE_MASK)) + { + return 0; + } + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info, pages); + } + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#else +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + vaddr = find_vaddr(mmu_info, pages); + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#endif + +#ifdef RT_USING_USERSPACE +static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void* v_addr, size_t npages, size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + + if (!mmu_info) + { + return -1; + } + + while (npages--) + { + loop_pa = (size_t)rt_pages_alloc(0); + if (!loop_pa) + goto err; + + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + rt_page_ref_inc(mmu_l2, 0); + } + else + { + //mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); + mmu_l2 = (size_t*)rt_pages_alloc(0); + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); + + *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + else + goto err; + } + + loop_pa += mmu_info->pv_off; + *(mmu_l2 + l2_off) = (loop_pa | attr); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + loop_va += ARCH_PAGE_SIZE; + } + return 0; +err: + { + /* error, unmap and quit */ + int i; + void *va, *pa; + + va = (void*)((size_t)v_addr & ~ARCH_PAGE_MASK); + for (i = 0; i < npages; i++) + { + pa = rt_hw_mmu_v2p(mmu_info, va); + pa = (void*)((char*)pa - mmu_info->pv_off); + rt_pages_free(pa, 0); + va = (void*)((char*)va + ARCH_PAGE_SIZE); + } + + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; + } +} + +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) +{ + size_t vaddr; + size_t offset; + int pages; + int ret; + + if (!size) + { + return 0; + } + offset = (size_t)v_addr & ARCH_PAGE_MASK; + size += (offset + ARCH_PAGE_SIZE - 1); + pages = (size >> ARCH_PAGE_SHIFT); + if (v_addr) + { + vaddr = (size_t)v_addr; + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info, pages); + } + if (vaddr) { + ret = __rt_hw_mmu_map_auto(mmu_info, (void*)vaddr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)((char*)vaddr + offset); + } + } + return 0; +} +#endif + +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size) +{ + size_t va_s, va_e; + int pages; + + va_s = (size_t)v_addr; + va_e = (size_t)v_addr + size - 1; + va_s >>= ARCH_PAGE_SHIFT; + va_e >>= ARCH_PAGE_SHIFT; + pages = va_e - va_s + 1; + __rt_hw_mmu_unmap(mmu_info, v_addr, pages); + rt_hw_cpu_tlb_invalidate(); +} + +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map(mmu_info, v_addr, p_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; +} + +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map_auto(mmu_info, v_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; +} +#endif + +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + _rt_hw_mmu_unmap(mmu_info, v_addr, size); + rt_hw_interrupt_enable(level); +} + +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr) +{ + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t tmp; + size_t pa; + + l1_off = (size_t)v_addr >> ARCH_SECTION_SHIFT; + + if (!mmu_info) + { + return (void*)0; + } + + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + tmp = *mmu_l1; + + switch (tmp & ARCH_MMU_USED_MASK) + { + case 0: /* not used */ + break; + case 1: /* page table */ + mmu_l2 = (size_t *)((tmp & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + l2_off = (((size_t)v_addr & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + pa = *(mmu_l2 + l2_off); + if (pa & ARCH_MMU_USED_MASK) + { + if ((pa & ARCH_MMU_USED_MASK) == 1) + { + /* large page, not support */ + break; + } + pa &= ~(ARCH_PAGE_MASK); + pa += ((size_t)v_addr & ARCH_PAGE_MASK); + return (void*)pa; + } + break; + case 2: + case 3: + /* section */ + if (tmp & ARCH_TYPE_SUPERSECTION) + { + /* super section, not support */ + break; + } + pa = (tmp & ~ARCH_SECTION_MASK); + pa += ((size_t)v_addr & ARCH_SECTION_MASK); + return (void*)pa; + } + return (void*)0; +} + +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_v2p(mmu_info, v_addr); + rt_hw_interrupt_enable(level); + return ret; +} + +#ifdef RT_USING_USERSPACE +void init_mm_setup(unsigned int *mtbl, unsigned int size, unsigned int pv_off) { + unsigned int va; + + for (va = 0; va < 0x1000; va++) { + unsigned int vaddr = (va << 20); + if (vaddr >= KERNEL_VADDR_START && vaddr - KERNEL_VADDR_START < size) { + mtbl[va] = ((va << 20) + pv_off) | NORMAL_MEM; + } else if (vaddr >= (KERNEL_VADDR_START + pv_off) && vaddr - (KERNEL_VADDR_START + pv_off) < size) { + mtbl[va] = (va << 20) | NORMAL_MEM; + } else { + mtbl[va] = 0; + } + } +} +#endif diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h index fbce6df93514ea612d255977995214c2bda70b40..d5288d8ab1b9d37e00a084a55ab6d05dad65bf05 100644 --- a/libcpu/arm/cortex-a/mmu.h +++ b/libcpu/arm/cortex-a/mmu.h @@ -19,8 +19,14 @@ #define SHAREDEVICE (1<<2) /* shared device */ #define STRONGORDER (0<<2) /* strong ordered */ #define XN (1<<4) /* eXecute Never */ +#ifdef RT_USING_USERSPACE +#define AP_RW (1<<10) /* supervisor=RW, user=No */ +#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ +#else #define AP_RW (3<<10) /* supervisor=RW, user=RW */ -#define AP_RO (2<<10) /* supervisor=RW, user=RO */ +#define AP_RO ((2<<10) /* supervisor=RW, user=RO */ +#endif + #define SHARED (1<<16) /* shareable */ #define DOMAIN_FAULT (0x0) @@ -37,6 +43,8 @@ /* normal memory mapping type */ #define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC) +#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC) + struct mem_desc { rt_uint32_t vaddr_start; @@ -45,5 +53,59 @@ struct mem_desc rt_uint32_t attr; }; +#define MMU_MAP_MTBL_XN (1<<0) +#define MMU_MAP_MTBL_A (1<<1) +#define MMU_MAP_MTBL_B (1<<2) +#define MMU_MAP_MTBL_C (1<<3) +#define MMU_MAP_MTBL_AP01(x) (x<<4) +#define MMU_MAP_MTBL_TEX(x) (x<<6) +#define MMU_MAP_MTBL_AP2(x) (x<<9) +#define MMU_MAP_MTBL_SHARE (1<<10) + +#define MMU_MAP_K_RO (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_RWCB (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_RW (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_DEVICE (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RO (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RWCB (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RW (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_DEVICE (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE) + +#define ARCH_SECTION_SHIFT 20 +#define ARCH_SECTION_SIZE (1 << ARCH_SECTION_SHIFT) +#define ARCH_SECTION_MASK (ARCH_SECTION_SIZE - 1) +#define ARCH_PAGE_SHIFT 12 +#define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT) +#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1) +#define ARCH_PAGE_TBL_SHIFT 10 +#define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT) +#define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1) + +#define ARCH_MMU_USED_MASK 3 + +#define ARCH_TYPE_SUPERSECTION (1 << 18) + +#define ARCH_ADDRESS_WIDTH_BITS 32 + +typedef struct +{ + size_t *vtable; + size_t vstart; + size_t vend; + size_t pv_off; +} rt_mmu_info; + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off); +int rt_hw_mmu_ioremap_init(rt_mmu_info *mmu_info, void* v_address, size_t size); + +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr); +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr); +#else +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr); +#endif + +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size); +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr); #endif diff --git a/libcpu/arm/cortex-a/pmu.c b/libcpu/arm/cortex-a/pmu.c index 8ffc1dede610da978808fa242898e2e2b1b681a2..23bc45156ad0a801b869d77bc1c1497f80a296d3 100644 --- a/libcpu/arm/cortex-a/pmu.c +++ b/libcpu/arm/cortex-a/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,12 +9,16 @@ #include #include "pmu.h" +#define DBG_TAG "PMU" +#define DBG_LVL DBG_WARNING +#include + void rt_hw_pmu_dump_feature(void) { unsigned long reg; reg = rt_hw_pmu_get_control(); - rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n", - reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); + LOG_D("ARM PMU Implementor: %c, ID code: %02x, %d counters\n", + reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); } diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c index 07d795ab5b6fce482bf9211e4fe4b76265ae4c01..8f73d730dd33caa63822afc5dcba0a26a109b63f 100644 --- a/libcpu/arm/cortex-a/stack.c +++ b/libcpu/arm/cortex-a/stack.c @@ -9,11 +9,11 @@ * 2011-10-05 Bernard add thumb mode */ #include +#include #include -#include /** - * @addtogroup AM33xx + * @addtogroup ARM Cortex-A */ /*@{*/ diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 2e99db72189ebb79e766c4633d2b63bbce80edcd..60feb8c3148767a5c75f8d809e686157d02745c1 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -19,16 +19,12 @@ .equ Mode_UND, 0x1B .equ Mode_SYS, 0x1F -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled +.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ +.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ -#ifdef RT_USING_FPU .equ UND_Stack_Size, 0x00000400 -#else -.equ UND_Stack_Size, 0x00000000 -#endif .equ SVC_Stack_Size, 0x00000400 -.equ ABT_Stack_Size, 0x00000000 +.equ ABT_Stack_Size, 0x00000400 .equ RT_FIQ_STACK_PGSZ, 0x00000000 .equ RT_IRQ_STACK_PGSZ, 0x00000800 .equ USR_Stack_Size, 0x00000400 @@ -41,13 +37,19 @@ .globl stack_start .globl stack_top -.align 3 stack_start: .rept ISR_Stack_Size .byte 0 .endr stack_top: +#ifdef RT_USING_USERSPACE +.data +.align 14 +init_mtbl: + .space 16*1024 +#endif + .text /* reset entry */ .globl _reset @@ -65,15 +67,96 @@ overHyped: /* Get out of HYP mode */ adr r1, continue msr ELR_hyp, r1 mrs r1, cpsr_all - and r1, r1, #0x1f ;@ CPSR_MODE_MASK - orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR + and r1, r1, #0x1f /* CPSR_MODE_MASK */ + orr r1, r1, #0x13 /* CPSR_MODE_SUPERVISOR */ + msr SPSR_hyp, r1 + eret + +continue: +#endif + +#ifdef SOC_BCM283x + /* Suspend the other cpu cores */ + mrc p15, 0, r0, c0, c0, 5 + ands r0, #3 + bne _halt + + /* Disable IRQ & FIQ */ + cpsid if + + /* Check for HYP mode */ + mrs r0, cpsr_all + and r0, r0, #0x1F + mov r8, #0x1A + cmp r0, r8 + beq overHyped + b continue + +overHyped: /* Get out of HYP mode */ + adr r1, continue + msr ELR_hyp, r1 + mrs r1, cpsr_all + and r1, r1, #0x1f /* CPSR_MODE_MASK */ + orr r1, r1, #0x13 /* CPSR_MODE_SUPERVISOR */ msr SPSR_hyp, r1 eret continue: + /* set the cpu to SVC32 mode and disable interrupt */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0x13 + msr cpsr_c, r0 +#endif + + /* invalid tlb before enable mmu */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, #1 + mcr p15, 0, r0, c1, c0, 0 + dsb + isb + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c7, c5, 0 /* iciallu */ + mcr p15, 0, r0, c7, c5, 6 /* bpiall */ + dsb + isb + +#ifdef RT_USING_USERSPACE + ldr r5, =PV_OFFSET + + mov r7, #0x100000 + sub r7, #1 + mvn r8, r7 + + + ldr r9, =KERNEL_VADDR_START + + ldr r6, =__bss_end + add r6, r7 + and r6, r8 /* r6 end vaddr align up to 1M */ + sub r6, r9 /* r6 is size */ + + ldr sp, =stack_top + add sp, r5 /* use paddr */ + + ldr r0, =init_mtbl + add r0, r5 + mov r1, r6 + mov r2, r5 + bl init_mm_setup + + ldr lr, =after_enable_mmu + ldr r0, =init_mtbl + add r0, r5 + b enable_mmu + +after_enable_mmu: #endif +#ifndef SOC_BCM283x /* set the cpu to SVC32 mode and disable interrupt */ cps #Mode_SVC +#endif #ifdef RT_USING_FPU mov r4, #0xfffffff @@ -89,20 +172,20 @@ continue: bl stack_setup /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ #ifdef RT_USING_SMP mrc p15, 0, r1, c1, c0, 1 mov r0, #(1<<6) orr r1, r0 - mcr p15, 0, r1, c1, c0, 1 //enable smp + mcr p15, 0, r1, c1, c0, 1 /* enable smp */ #endif /* initialize the mmu table and enable mmu */ @@ -110,9 +193,16 @@ bss_loop: ldr r1, =platform_mem_desc_size ldr r1, [r1] bl rt_hw_init_mmu_table + +#ifdef RT_USING_USERSPACE + ldr r0, =MMUTable /* vaddr */ + add r0, r5 /* to paddr */ + bl switch_mmu +#else bl rt_hw_mmu_init +#endif - /* call C++ constructors of global objects */ + /* call C++ constructors of global objects */ ldr r0, =__ctors_start__ ldr r1, =__ctors_end__ @@ -135,25 +225,25 @@ _rtthread_startup: stack_setup: ldr r0, =stack_top - @ Set the startup stack for svc + /* Set the startup stack for svc */ mov sp, r0 - @ Enter Undefined Instruction Mode and set its Stack Pointer + /* Enter Undefined Instruction Mode and set its Stack Pointer */ msr cpsr_c, #Mode_UND|I_Bit|F_Bit mov sp, r0 sub r0, r0, #UND_Stack_Size - @ Enter Abort Mode and set its Stack Pointer + /* Enter Abort Mode and set its Stack Pointer */ msr cpsr_c, #Mode_ABT|I_Bit|F_Bit mov sp, r0 sub r0, r0, #ABT_Stack_Size - @ Enter FIQ Mode and set its Stack Pointer + /* Enter FIQ Mode and set its Stack Pointer */ msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit mov sp, r0 sub r0, r0, #RT_FIQ_STACK_PGSZ - @ Enter IRQ Mode and set its Stack Pointer + /* Enter IRQ Mode and set its Stack Pointer */ msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit mov sp, r0 sub r0, r0, #RT_IRQ_STACK_PGSZ @@ -162,7 +252,65 @@ stack_setup: msr cpsr_c, #Mode_SVC|I_Bit|F_Bit bx lr -/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ +#ifdef RT_USING_USERSPACE +.align 2 +.global enable_mmu +enable_mmu: + orr r0, #0x18 + mcr p15, 0, r0, c2, c0, 0 /* ttbr0 */ + + mov r0, #(1 << 5) /* PD1=1 */ + mcr p15, 0, r0, c2, c0, 2 /* ttbcr */ + + mov r0, #1 + mcr p15, 0, r0, c3, c0, 0 /* dacr */ + + /* invalid tlb before enable mmu */ + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c7, c5, 0 /* iciallu */ + mcr p15, 0, r0, c7, c5, 6 /* bpiall */ + + mrc p15, 0, r0, c1, c0, 0 + orr r0, #((1 << 12) | (1 << 11)) /* instruction cache, branch prediction */ + orr r0, #((1 << 2) | (1 << 0)) /* data cache, mmu enable */ + mcr p15, 0, r0, c1, c0, 0 + dsb + isb + mov pc, lr + +.global set_process_id +set_process_id: + LSL r0, r0, #8 + MCR p15, 0, r0, c13, c0, 1 + mov pc, lr + +.global switch_mmu +switch_mmu: + orr r0, #0x18 + mcr p15, 0, r0, c2, c0, 0 /* ttbr0 */ + + /* invalid tlb */ + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c7, c5, 0 /* iciallu */ + mcr p15, 0, r0, c7, c5, 6 /* bpiall */ + + dsb + isb + mov pc, lr +.global mmu_table_get +mmu_table_get: + mrc p15, 0, r0, c2, c0, 0 /* ttbr0 */ + bic r0, #0x18 + mov pc, lr +#endif + +_halt: + wfe + b _halt + +/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ .section .text.isr, "ax" .align 5 .globl vector_fiq @@ -195,7 +343,7 @@ vector_irq: cps #Mode_IRQ sub lr, #4 - stmfd r0!, {r1, lr} /* svc_lr, svc_pc */ + stmfd r0!, {r1, lr} /* svc_lr, svc_pc */ stmfd r0!, {r2 - r12} ldmfd sp!, {r1, r2} /* original r0, r1 */ stmfd r0!, {r1 - r2} @@ -203,8 +351,8 @@ vector_irq: stmfd r0!, {r1} #ifdef RT_USING_LWP - stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */ - sub r0, #8 + stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */ + sub r0, #8 #endif #ifdef RT_USING_FPU /* fpu context */ @@ -224,12 +372,13 @@ vector_irq: /* backup r0 -> r8 */ mov r8, r0 + cps #Mode_SVC + mov sp, r8 + bl rt_interrupt_enter bl rt_hw_trap_irq bl rt_interrupt_leave - cps #Mode_SVC - mov sp, r8 mov r0, r8 bl rt_scheduler_do_irq_switch @@ -242,41 +391,70 @@ vector_irq: bl rt_hw_trap_irq bl rt_interrupt_leave - @ if rt_thread_switch_interrupt_flag set, jump to - @ rt_hw_context_switch_interrupt_do and don't return + /* if rt_thread_switch_interrupt_flag set, jump to + * rt_hw_context_switch_interrupt_do and don't return */ ldr r0, =rt_thread_switch_interrupt_flag ldr r1, [r0] cmp r1, #1 beq rt_hw_context_switch_interrupt_do +#ifdef RT_USING_LWP + ldmfd sp!, {r0-r12,lr} + cps #Mode_SVC + push {r0-r12} + mov r7, lr + cps #Mode_IRQ + mrs r4, spsr + sub r5, lr, #4 + cps #Mode_SVC + bl lwp_check_exit + and r6, r4, #0x1f + cmp r6, #0x10 + bne 1f + msr spsr_csxf, r4 + mov lr, r5 + pop {r0-r12} + b ret_to_user +1: + mov lr, r7 + cps #Mode_IRQ + msr spsr_csxf, r4 + mov lr, r5 + cps #Mode_SVC + pop {r0-r12} + cps #Mode_IRQ + movs pc, lr +#else ldmfd sp!, {r0-r12,lr} subs pc, lr, #4 +#endif rt_hw_context_switch_interrupt_do: - mov r1, #0 @ clear flag + mov r1, #0 /* clear flag */ str r1, [r0] - mov r1, sp @ r1 point to {r0-r3} in stack + mov r1, sp /* r1 point to {r0-r3} in stack */ add sp, sp, #4*4 - ldmfd sp!, {r4-r12,lr}@ reload saved registers - mrs r0, spsr @ get cpsr of interrupt thread - sub r2, lr, #4 @ save old task's pc to r2 + ldmfd sp!, {r4-r12,lr} /* reload saved registers */ + mrs r0, spsr /* get cpsr of interrupt thread */ + sub r2, lr, #4 /* save old task's pc to r2 */ - @ Switch to SVC mode with no interrupt. If the usr mode guest is - @ interrupted, this will just switch to the stack of kernel space. - @ save the registers in kernel space won't trigger data abort. + /* Switch to SVC mode with no interrupt. If the usr mode guest is + * interrupted, this will just switch to the stack of kernel space. + * save the registers in kernel space won't trigger data abort. */ msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 - ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread - stmfd sp!, {r1-r4} @ push old task's r0-r3 - stmfd sp!, {r0} @ push old task's cpsr + stmfd sp!, {r2} /* push old task's pc */ + stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */ + ldmfd r1, {r1-r4} /* restore r0-r3 of the interrupt thread */ + stmfd sp!, {r1-r4} /* push old task's r0-r3 */ + stmfd sp!, {r0} /* push old task's cpsr */ #ifdef RT_USING_LWP - stmfd sp, {r13, r14}^ @push usr_sp, usr_lr - sub sp, #8 + stmfd sp, {r13, r14}^ /*push usr_sp, usr_lr */ + sub sp, #8 #endif + #ifdef RT_USING_FPU /* fpu context */ vmrs r6, fpexc @@ -292,14 +470,22 @@ rt_hw_context_switch_interrupt_do: ldr r4, =rt_interrupt_from_thread ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB + str sp, [r5] /* store sp in preempted tasks's TCB */ ldr r6, =rt_interrupt_to_thread ldr r6, [r6] - ldr sp, [r6] @ get new task's stack pointer + ldr sp, [r6] /* get new task's stack pointer */ + + bl rt_thread_self +#ifdef RT_USING_USERSPACE + mov r4, r0 + bl lwp_mmu_switch + mov r0, r4 + bl lwp_user_setting_restore +#endif #ifdef RT_USING_FPU -/* fpu context */ + /* fpu context */ ldmfd sp!, {r6} vmsr fpexc, r6 tst r6, #(1<<30) @@ -312,27 +498,51 @@ rt_hw_context_switch_interrupt_do: #endif #ifdef RT_USING_LWP - ldmfd sp, {r13, r14}^ @pop usr_sp, usr_lr + ldmfd sp, {r13, r14}^ /*pop usr_sp, usr_lr */ add sp, #8 #endif - ldmfd sp!, {r4} @ pop new task's cpsr to spsr + ldmfd sp!, {r4} /* pop new task's cpsr to spsr */ msr spsr_cxsf, r4 - ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr +#ifdef RT_USING_GDBSERVER + bl lwp_check_debug +#endif + +#ifdef RT_USING_LWP + bl lwp_check_exit +#endif + +#ifdef RT_USING_LWP + and r4, #0x1f + cmp r4, #0x10 + bne 1f + ldmfd sp!, {r0-r12,lr} + ldmfd sp!, {lr} + b ret_to_user +1: +#endif + /* pop new task's r0-r12,lr & pc, copy spsr to cpsr */ + ldmfd sp!, {r0-r12,lr,pc}^ #endif .macro push_svc_reg - sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ - stmia sp, {r0 - r12} @/* Calling r0-r12 */ + sub sp, sp, #17 * 4 /* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} /* Calling r0-r12 */ mov r0, sp - mrs r6, spsr @/* Save CPSR */ - str lr, [r0, #15*4] @/* Push PC */ - str r6, [r0, #16*4] @/* Push CPSR */ + add sp, sp, #17 * 4 + mrs r6, spsr /* Save CPSR */ + str lr, [r0, #15*4] /* Push PC */ + str r6, [r0, #16*4] /* Push CPSR */ + and r1, r6, #0x1f + cmp r1, #0x10 + cps #Mode_SYS + streq sp, [r0, #13*4] /* Save calling SP */ + streq lr, [r0, #14*4] /* Save calling PC */ cps #Mode_SVC - str sp, [r0, #13*4] @/* Save calling SP */ - str lr, [r0, #14*4] @/* Save calling PC */ + strne sp, [r0, #13*4] /* Save calling SP */ + strne lr, [r0, #14*4] /* Save calling PC */ .endm .align 5 @@ -346,9 +556,10 @@ vector_swi: .globl vector_undef vector_undef: push_svc_reg - cps #Mode_UND bl rt_hw_trap_undef + cps #Mode_UND #ifdef RT_USING_FPU + sub sp, sp, #17 * 4 ldr lr, [sp, #15*4] ldmia sp, {r0 - r12} add sp, sp, #17 * 4 @@ -360,15 +571,57 @@ vector_undef: .globl vector_pabt vector_pabt: push_svc_reg +#ifdef RT_USING_USERSPACE + /* cp Mode_ABT stack to SVC */ + sub sp, sp, #17 * 4 /* Sizeof(struct rt_hw_exp_stack) */ + mov lr, r0 + ldmia lr, {r0 - r12} + stmia sp, {r0 - r12} + add r1, lr, #13 * 4 + add r2, sp, #13 * 4 + ldmia r1, {r4 - r7} + stmia r2, {r4 - r7} + mov r0, sp + bl rt_hw_trap_pabt + /* return to user */ + ldr lr, [sp, #16*4] /* orign spsr */ + msr spsr_cxsf, lr + ldr lr, [sp, #15*4] /* orign pc */ + ldmia sp, {r0 - r12} + add sp, #17 * 4 + b ret_to_user +#else bl rt_hw_trap_pabt b . +#endif .align 5 .globl vector_dabt vector_dabt: push_svc_reg +#ifdef RT_USING_USERSPACE + /* cp Mode_ABT stack to SVC */ + sub sp, sp, #17 * 4 /* Sizeof(struct rt_hw_exp_stack) */ + mov lr, r0 + ldmia lr, {r0 - r12} + stmia sp, {r0 - r12} + add r1, lr, #13 * 4 + add r2, sp, #13 * 4 + ldmia r1, {r4 - r7} + stmia r2, {r4 - r7} + mov r0, sp + bl rt_hw_trap_dabt + /* return to user */ + ldr lr, [sp, #16*4] /* orign spsr */ + msr spsr_cxsf, lr + ldr lr, [sp, #15*4] /* orign pc */ + ldmia sp, {r0 - r12} + add sp, #17 * 4 + b ret_to_user +#else bl rt_hw_trap_dabt b . +#endif .align 5 .globl vector_resv @@ -378,18 +631,26 @@ vector_resv: b . #ifdef RT_USING_SMP -.global set_secondary_cpu_boot_address -set_secondary_cpu_boot_address: - ldr r0, =secondary_cpu_start - - mvn r1, #0 //0xffffffff - ldr r2, =0x10000034 - str r1, [r2] - str r0, [r2, #-4] - mov pc, lr - -.global secondary_cpu_start -secondary_cpu_start: +.global rt_clz +rt_clz: + clz r0, r0 + bx lr + +.global rt_secondary_cpu_entry +rt_secondary_cpu_entry: +#ifdef RT_USING_USERSPACE + ldr r5, =PV_OFFSET + + ldr lr, =after_enable_mmu2 + ldr r0, =init_mtbl + add r0, r5 + b enable_mmu + +after_enable_mmu2: + ldr r0, =MMUTable + add r0, r5 + bl switch_mmu +#endif #ifdef RT_USING_FPU mov r4, #0xfffffff @@ -399,16 +660,14 @@ secondary_cpu_start: mrc p15, 0, r1, c1, c0, 1 mov r0, #(1<<6) orr r1, r0 - mcr p15, 0, r1, c1, c0, 1 //enable smp + mcr p15, 0, r1, c1, c0, 1 /* enable smp */ mrc p15, 0, r0, c1, c0, 0 bic r0, #(1<<13) mcr p15, 0, r0, c1, c0, 0 -#ifdef RT_USING_FPU cps #Mode_UND ldr sp, =und_stack_2_limit -#endif cps #Mode_IRQ ldr sp, =irq_stack_2_limit @@ -419,14 +678,19 @@ secondary_cpu_start: cps #Mode_SVC ldr sp, =svc_stack_2_limit + cps #Mode_ABT + ldr sp, =abt_stack_2_limit + /* initialize the mmu table and enable mmu */ +#ifndef RT_USING_USERSPACE bl rt_hw_mmu_init +#endif - b secondary_cpu_c_start + b rt_hw_secondary_cpu_bsp_start #endif .bss -.align 2 //align to 2~2=4 +.align 2 /* align to 2~2=4 */ svc_stack_2: .space (1 << 10) svc_stack_2_limit: @@ -435,8 +699,10 @@ irq_stack_2: .space (1 << 10) irq_stack_2_limit: -#ifdef RT_USING_FPU und_stack_2: .space (1 << 10) und_stack_2_limit: -#endif + +abt_stack_2: + .space (1 << 10) +abt_stack_2_limit: diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index dc232a46ee2945ce769c03c97a6b7f213f72f9e9..706f809e5f53d4e3c3f187ea16fce19faafcb8fa 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -11,14 +11,144 @@ #include #include #include +#include -#include "armv7.h" #include "interrupt.h" #ifdef RT_USING_FINSH extern long list_thread(void); #endif +#ifdef RT_USING_LWP +#include +#include + +#ifdef LWP_USING_CORE_DUMP +#include +#endif + +#ifdef RT_USING_GDBSERVER +#include +#include + +static int check_debug_event(struct rt_hw_exp_stack *regs, uint32_t pc_adj) +{ + uint32_t mode = regs->cpsr; + + if ((mode & 0x1f) == 0x10) /* is user mode */ + { + struct rt_channel_msg msg; + gdb_thread_info thread_info; + uint32_t ifsr, dfar, dfsr; + int ret; + + if (pc_adj == 4) /* pabt */ + { + /* check breakpoint event */ + asm volatile ("MRC p15, 0, %0, c5, c0, 1":"=r"(ifsr)); + ifsr &= ((1UL << 12) | 0x3fUL); /* status */ + if (ifsr == 0x2UL) + { + /* is breakpoint event */ + regs->pc -= pc_adj; + do { + struct rt_lwp *gdb_lwp = gdb_get_dbg_lwp(); + struct rt_lwp *lwp; + + if (!gdb_lwp) + { + break; + } + lwp = lwp_self(); + if (lwp == gdb_lwp) + { + break; + } + *(uint32_t *)regs->pc = lwp->bak_first_ins; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)regs->pc, 4); + icache_invalid_all(); + lwp->debug = 0; + return 1; + } while (0); + + thread_info.notify_type = GDB_NOTIFIY_BREAKPOINT; + thread_info.abt_ins = *(uint32_t *)regs->pc; + ret = 1; + } + else + { + return 0; /* not debug pabt */ + } + } + else + { + /* watchpoing event */ + asm volatile ("MRC p15, 0, %0, c5, c0, 0":"=r"(dfsr)); + dfsr = (((dfsr & (1UL << 10)) >> 6) | (dfsr & 0xfUL)); /* status */ + if (dfsr == 0x2UL) + { + /* is watchpoint event */ + regs->pc -= pc_adj; + asm volatile ("MRC p15, 0, %0, c6, c0, 0":"=r"(dfar)); + thread_info.watch_addr = (void *)dfar; + thread_info.rw = (1UL << (((~*(uint32_t *)regs->pc) >> 20) & 1UL)); + thread_info.notify_type = GDB_NOTIFIY_WATCHPOINT; + ret = 2; + } + else + { + return 0; /* not debug dabt */ + } + } + thread_info.thread = rt_thread_self(); + thread_info.thread->regs = regs; + msg.u.d = (void *)&thread_info; + rt_hw_dmb(); + thread_info.thread->debug_suspend = 1; + rt_hw_dsb(); + rt_thread_suspend_with_flag(thread_info.thread, RT_UNINTERRUPTIBLE); + rt_raw_channel_send(gdb_get_server_channel(), &msg); + rt_schedule(); + while (thread_info.thread->debug_suspend) + { + rt_thread_suspend_with_flag(thread_info.thread, RT_UNINTERRUPTIBLE); + rt_schedule(); + } + return ret; + } + return 0; +} +#endif + +void sys_exit(int value); +void check_user_fault(struct rt_hw_exp_stack *regs, uint32_t pc_adj, char *info) +{ + uint32_t mode = regs->cpsr; + + if ((mode & 0x1f) == 0x10) + { + rt_kprintf("%s! pc = 0x%08x\n", info, regs->pc - pc_adj); +#ifdef LWP_USING_CORE_DUMP + lwp_core_dump(regs, pc_adj); +#endif + sys_exit(-1); + } +} + +int check_user_stack(struct rt_hw_exp_stack *regs) +{ + void* dfar = RT_NULL; + + asm volatile ("MRC p15, 0, %0, c6, c0, 0":"=r"(dfar)); + if (arch_expand_user_stack(dfar)) + { + regs->pc -= 8; + return 1; + } + return 0; +} +#endif + /** * this function will show registers of CPU * @@ -33,6 +163,18 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +#ifdef RT_USING_USERSPACE + { + uint32_t v; + asm volatile ("MRC p15, 0, %0, c5, c0, 0":"=r"(v)); + rt_kprintf("dfsr:0x%08x\n", v); + asm volatile ("MRC p15, 0, %0, c2, c0, 0":"=r"(v)); + rt_kprintf("ttbr0:0x%08x\n", v); + asm volatile ("MRC p15, 0, %0, c6, c0, 0":"=r"(v)); + rt_kprintf("dfar:0x%08x\n", v); + rt_kprintf("0x%08x -> 0x%08x\n", v, rt_hw_mmu_v2p(&mmu_info, (void *)v)); + } +#endif } /** @@ -43,6 +185,9 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) * * @note never invoke this function in application */ +#ifdef RT_USING_FPU +void set_fpexc(rt_uint32_t val); +#endif void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) { #ifdef RT_USING_FPU @@ -54,30 +199,32 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) { /* thumb mode */ addr = regs->pc - 2; - ins = (uint32_t)*(uint16_t*)addr; + ins = (uint32_t)*(uint16_t *)addr; if ((ins & (3 << 11)) != 0) { /* 32 bit ins */ ins <<= 16; - ins += *(uint16_t*)(addr + 2); + ins += *(uint16_t *)(addr + 2); } } else { addr = regs->pc - 4; - ins = *(uint32_t*)addr; + ins = *(uint32_t *)addr; } if ((ins & 0xe00) == 0xa00) { /* float ins */ - uint32_t val = (1U << 30); - - asm volatile ("vmsr fpexc, %0"::"r"(val):"memory"); + set_fpexc(1U << 30); regs->pc = addr; return; } } #endif +#ifdef RT_USING_LWP + check_user_fault(regs, 4, "User undefined instruction"); +#endif + rt_unwind(regs, 4); rt_kprintf("undefined instruction:\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH @@ -115,6 +262,16 @@ void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) */ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) { +#ifdef RT_USING_LWP +#ifdef RT_USING_GDBSERVER + if (check_debug_event(regs, 4)) + { + return; + } +#endif + check_user_fault(regs, 4, "User prefetch abort"); +#endif + rt_unwind(regs, 4); rt_kprintf("prefetch abort:\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH @@ -133,6 +290,20 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) */ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) { +#ifdef RT_USING_LWP +#ifdef RT_USING_GDBSERVER + if (check_debug_event(regs, 8)) + { + return; + } +#endif + if (check_user_stack(regs)) + { + return; + } + check_user_fault(regs, 8, "User data abort"); +#endif + rt_unwind(regs, 8); rt_kprintf("data abort:"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH @@ -160,6 +331,69 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) void rt_hw_trap_irq(void) { +#ifdef SOC_BCM283x + extern rt_uint8_t core_timer_flag; + void *param; + uint32_t irq; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + uint32_t value = 0; + value = IRQ_PEND_BASIC & 0x3ff; + + if(core_timer_flag != 0) + { + uint32_t cpu_id = rt_hw_cpu_id(); + uint32_t int_source = CORE_IRQSOURCE(cpu_id); + if (int_source & 0x0f) + { + if (int_source & 0x08) + { + isr_func = isr_table[IRQ_ARM_TIMER].handler; + #ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_TIMER].counter++; + #endif + if (isr_func) + { + param = isr_table[IRQ_ARM_TIMER].param; + isr_func(IRQ_ARM_TIMER, param); + } + } + } + } + + /* local interrupt*/ + if (value) + { + if (value & (1 << 8)) + { + value = IRQ_PEND1; + irq = __rt_ffs(value) - 1; + } + else if (value & (1 << 9)) + { + value = IRQ_PEND2; + irq = __rt_ffs(value) + 31; + } + else + { + value &= 0x0f; + irq = __rt_ffs(value) + 63; + } + + /* get interrupt service routine */ + isr_func = isr_table[irq].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[irq].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[irq].param; + /* turn to interrupt service routine */ + isr_func(irq, param); + } + } +#else void *param; int ir; rt_isr_handler_t isr_func; @@ -188,6 +422,7 @@ void rt_hw_trap_irq(void) /* end of interrupt */ rt_hw_interrupt_ack(ir); +#endif } void rt_hw_trap_fiq(void) diff --git a/libcpu/arm/cortex-a/vector_gcc.S b/libcpu/arm/cortex-a/vector_gcc.S index 60d3c6cf1d9083f312cf47465bd62c96d5fdc9bf..eb872db71f31d9a5caafa13e6a9b6ae16fa55f1a 100644 --- a/libcpu/arm/cortex-a/vector_gcc.S +++ b/libcpu/arm/cortex-a/vector_gcc.S @@ -7,13 +7,19 @@ * Date Author Notes * 2013-07-05 Bernard the first version */ + +#include "rtconfig.h" .section .vectors, "ax" .code 32 .globl system_vectors system_vectors: +#ifdef RT_USING_USERSPACE + b _reset +#else ldr pc, _vector_reset +#endif ldr pc, _vector_undef ldr pc, _vector_swi ldr pc, _vector_pabt diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c index 4d3bf3c1abcc7a5b21a620331ae1c8772e25d636..ccf864a18a158d07ece5895a3436b3dec8dfffee 100644 --- a/libcpu/arm/s3c24x0/cpu.c +++ b/libcpu/arm/s3c24x0/cpu.c @@ -17,77 +17,148 @@ */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define CACHE_LINE_SIZE 32 #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm("mrc p15, 0, %0, c1, c0, 0" + : "=r"(i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( + "mrc p15,0,r0,c1,c0,0\n\t" + "orr r0,r0,%0\n\t" + "mcr p15,0,r0,c1,c0,0" + : + : "r"(bit) + : "memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( + "mrc p15,0,r0,c1,c0,0\n\t" + "bic r0,r0,%0\n\t" + "mcr p15,0,r0,c1,c0,0" + : + : "r"(bit) + : "memory"); +} + +void dcache_clean(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + asm volatile("mcr p15, 0, %0, c7, c10, 1": :"r"(ptr)); + + ptr += CACHE_LINE_SIZE; + } +} + +void dcache_invalidate(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + asm volatile("mcr p15, 0, %0, c7, c6, 1": :"r"(ptr)); + + ptr += CACHE_LINE_SIZE; + } +} + +void icache_invalidate() +{ + asm volatile("mcr p15, 0, %0, c7, c5, 0": :"r"(0)); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } + +void dcache_clean(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + __asm volatile { mcr p15, 0, ptr, c7, c10, 1 } + ptr += CACHE_LINE_SIZE; + } +} + +void dcache_invalidate(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + __asm volatile { mcr p15, 0, ptr, c7, c6, 1 } + ptr += CACHE_LINE_SIZE; + } +} + +void icache_invalidate() +{ + register rt_uint32_t value; + + value = 0; + + __asm volatile { mcr p15, 0, value, c7, c5, 0 } +} + #endif /** @@ -96,7 +167,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -105,7 +176,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -114,7 +185,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -123,7 +194,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -132,7 +203,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -141,7 +212,21 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); +} + +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_INVALIDATE) + icache_invalidate(); /* TODO: only invalidate an addr range */ +} + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) + dcache_clean(addr, size); + else if (ops == RT_HW_CACHE_INVALIDATE) + dcache_invalidate(addr, size); } /** @@ -150,21 +235,22 @@ rt_base_t rt_hw_cpu_dcache_status() */ void rt_hw_cpu_reset() { - /* Disable all interrupt except the WDT */ - INTMSK = (~((rt_uint32_t)1 << INTWDT)); + /* Disable all interrupt except the WDT */ + INTMSK = (~((rt_uint32_t)1 << INTWDT)); - /* Disable watchdog */ - WTCON = 0x0000; + /* Disable watchdog */ + WTCON = 0x0000; - /* Initialize watchdog timer count register */ - WTCNT = 0x0001; + /* Initialize watchdog timer count register */ + WTCNT = 0x0001; - /* Enable watchdog timer; assert reset at timer timeout */ - WTCON = 0x0021; + /* Enable watchdog timer; assert reset at timer timeout */ + WTCON = 0x0021; - while(1); /* loop forever and wait for reset to happen */ + while (1) + ; /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -173,14 +259,14 @@ void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index dece8b042397ff5e2b2b7eb0afc5c317a11346ca..8909c77cdf58bf12f18266f8a9db4fe8872e4e80 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -14,11 +14,15 @@ if rtconfig.CPU == "e906" : group = group elif rtconfig.CPU == "nuclei" : group = group +elif rtconfig.CPU == "virt64" : + group = group +elif rtconfig.CPU == "c906" : + group = group else : group = group + SConscript(os.path.join(cwd, 'common', 'SConscript')) # cpu porting code files -if rtconfig.CPU == "e906" : +if rtconfig.CPU == "e906" or rtconfig.CPU == "c906": group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript')) else : group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript')) diff --git a/libcpu/risc-v/t-head/c906/SConscript b/libcpu/risc-v/t-head/c906/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..2f698f530ad89c0fae239df5757292f849de0b2b --- /dev/null +++ b/libcpu/risc-v/t-head/c906/SConscript @@ -0,0 +1,12 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/t-head/c906/asm/sbiasm.h b/libcpu/risc-v/t-head/c906/asm/sbiasm.h new file mode 100644 index 0000000000000000000000000000000000000000..4639fba68cface55c39c15143440c4312dae8f27 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/asm/sbiasm.h @@ -0,0 +1,10 @@ +#ifndef _SBI_ASM_H +#define _SBI_ASM_H + +.macro SBI_CALL which + li a7, \which + ecall + nop +.endm + +#endif /* _SBI_ASM_H */ diff --git a/libcpu/risc-v/t-head/c906/asm/sbidef.h b/libcpu/risc-v/t-head/c906/asm/sbidef.h new file mode 100644 index 0000000000000000000000000000000000000000..5bcf58ade7c3eeba38e86013137392a91223f63f --- /dev/null +++ b/libcpu/risc-v/t-head/c906/asm/sbidef.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ +#ifndef _ASM_SBI_DEF_H +#define _ASM_SBI_DEF_H + +#define SBI_SET_TIMER 0 +#define SBI_CONSOLE_PUTCHAR 1 +#define SBI_CONSOLE_GETCHAR 2 +#define SBI_CLEAR_IPI 3 +#define SBI_SEND_IPI 4 +#define SBI_REMOTE_FENCE_I 5 +#define SBI_REMOTE_SFENCE_VMA 6 +#define SBI_REMOTE_SFENCE_VMA_ASID 7 +#define SBI_SHUTDOWN 8 + +#define SBI_CONSOLE_PUTSTR 9 + +#define SBI_SD_WRITE 10 +#define SBI_SD_READ 11 +#define SBI_NET_WRITE 12 +#define SBI_NET_READ 13 + +#endif /* _ASM_SBI_DEF_H */ diff --git a/libcpu/risc-v/t-head/c906/cache.c b/libcpu/risc-v/t-head/c906/cache.c new file mode 100644 index 0000000000000000000000000000000000000000..1bb01edec70b347ef5233586d9de854c5e68afa0 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/cache.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-29 lizhirui first version + * 2021-11-05 JasonHu add c906 cache inst + */ + +#include +#include +#include +#include + +#define L1_CACHE_BYTES (64) + +/** + * GCC version not support t-head cache flush, so we use fixed code to achieve. + * The following function cannot be optimized. + */ +static void dcache_wb_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); +static void dcache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); +static void dcache_wbinv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); +static void icache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); + +static void dcache_wb_range(unsigned long start, unsigned long end) +{ + unsigned long i = start & ~(L1_CACHE_BYTES - 1); + + for (; i < end; i += L1_CACHE_BYTES) + { + /* asm volatile("dcache.cva %0\n"::"r"(i):"memory"); */ + /* + * compiler always use a5 = i. + * a6 not used, so we use a6 here. + */ + asm volatile("mv a6, %0\n"::"r"(i):"memory"); /* a6 = a5(i) */ + asm volatile(".long 0x0257800b"); /* dcache.cva a6 */ + } + asm volatile(".long 0x01b0000b"); /* sync.is */ +} + +static void dcache_inv_range(unsigned long start, unsigned long end) +{ + unsigned long i = start & ~(L1_CACHE_BYTES - 1); + + for (; i < end; i += L1_CACHE_BYTES) + { + /* asm volatile("dcache.iva %0\n"::"r"(i):"memory"); */ + asm volatile("mv a6, %0\n"::"r"(i):"memory"); /* a6 = a5(i) */ + asm volatile(".long 0x0268000b"); /* dcache.iva a6 */ + } + asm volatile(".long 0x01b0000b"); +} + +static void dcache_wbinv_range(unsigned long start, unsigned long end) +{ + unsigned long i = start & ~(L1_CACHE_BYTES - 1); + + for (; i < end; i += L1_CACHE_BYTES) + { + /* asm volatile("dcache.civa %0\n"::"r"(i):"memory"); */ + asm volatile("mv a6, %0\n"::"r"(i):"memory"); /* a6 = a5(i) */ + asm volatile(".long 0x0278000b"); /* dcache.civa a6 */ + } + asm volatile(".long 0x01b0000b"); +} + +static void icache_inv_range(unsigned long start, unsigned long end) +{ + unsigned long i = start & ~(L1_CACHE_BYTES - 1); + + for (; i < end; i += L1_CACHE_BYTES) + { + /* asm volatile("icache.iva %0\n"::"r"(i):"memory"); */ + asm volatile("mv a6, %0\n"::"r"(i):"memory"); /* a6 = a5(i) */ + asm volatile(".long 0x0308000b"); /* icache.iva a6 */ + } + asm volatile(".long 0x01b0000b"); +} + +rt_inline rt_uint32_t rt_cpu_icache_line_size(void) +{ + return L1_CACHE_BYTES; +} + +rt_inline rt_uint32_t rt_cpu_dcache_line_size(void) +{ + return L1_CACHE_BYTES; +} + +void rt_hw_cpu_icache_invalidate(void *addr,int size) +{ + icache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); +} + +void rt_hw_cpu_dcache_invalidate(void *addr,int size) +{ + dcache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); +} + +void rt_hw_cpu_dcache_clean(void *addr,int size) +{ + dcache_wb_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); +} + +void rt_hw_cpu_dcache_clean_flush(void *addr,int size) +{ + dcache_wbinv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); +} + +void rt_hw_cpu_icache_ops(int ops,void *addr,int size) +{ + if(ops == RT_HW_CACHE_INVALIDATE) + { + rt_hw_cpu_icache_invalidate(addr, size); + } +} + +void rt_hw_cpu_dcache_ops(int ops,void *addr,int size) +{ + if(ops == RT_HW_CACHE_FLUSH) + { + rt_hw_cpu_dcache_clean(addr, size); + } + else + { + rt_hw_cpu_dcache_invalidate(addr, size); + } +} + +void rt_hw_cpu_dcache_clean_all(void) +{ + /* asm volatile("dcache.call\n":::"memory"); */ + asm volatile(".long 0x0010000b\n":::"memory"); +} + +void rt_hw_cpu_dcache_invalidate_all(void) +{ + /* asm volatile("dcache.ciall\n":::"memory"); */ + asm volatile(".long 0x0030000b\n":::"memory"); +} + +void rt_hw_cpu_icache_invalidate_all(void) +{ + /* asm volatile("icache.iall\n":::"memory"); */ + asm volatile(".long 0x0100000b\n":::"memory"); +} + +int sys_cacheflush(void *addr, int size, int cache) +{ + return 0; +} diff --git a/libcpu/risc-v/t-head/c906/cache.h b/libcpu/risc-v/t-head/c906/cache.h new file mode 100644 index 0000000000000000000000000000000000000000..8e9dffc78dbe3760d3ca571e4f1a1d15da6626ff --- /dev/null +++ b/libcpu/risc-v/t-head/c906/cache.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-11-05 JasonHu The first version + */ + +#ifndef CACHE_H__ +#define CACHE_H__ + +void rt_hw_cpu_dcache_clean(void *addr,int size); +void rt_hw_cpu_icache_invalidate(void *addr,int size); +void rt_hw_cpu_dcache_invalidate(void *addr,int size); + +void rt_hw_cpu_dcache_clean_flush(void *addr,int size); +void rt_hw_cpu_dcache_clean_all(void); +void rt_hw_cpu_dcache_invalidate_all(void); +void rt_hw_cpu_icache_invalidate_all(void); + +#endif /* CACHE_H__ */ diff --git a/libcpu/risc-v/t-head/c906/context_gcc.S b/libcpu/risc-v/t-head/c906/context_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..d121eac67d7d67cd9b8d712bfd9798b16635b4d3 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/context_gcc.S @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting implementation + * 2018/12/27 Jesven Add SMP support + * 2021/02/02 lizhirui Add userspace support + */ + +#define __ASSEMBLY__ +#include "cpuport.h" +#include "stackframe.h" + + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LOAD sp, (a0) + + la s0, rt_current_thread + LOAD s1, (s0) + + #ifdef RT_USING_USERSPACE + mv a0, s1 + jal lwp_mmu_switch + #endif + + RESTORE_ALL + sret + +/* + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mv t2, sp + li t0, 0x120//set SPIE and SPP = 1 + csrs sstatus, t0//if enter here,caller must be in system thread + csrw sepc, ra//return address + //saved from thread context + SAVE_ALL + + STORE t2, 32 * REGBYTES(sp)//save user_sp + + STORE sp, (a0) + + //restore to thread context + LOAD sp, (a1) + + la s0, rt_current_thread + LOAD s1, (s0) + + #ifdef RT_USING_USERSPACE + mv a0, s1 + jal lwp_mmu_switch + #endif + + RESTORE_ALL + sret diff --git a/libcpu/risc-v/t-head/c906/cpuport.c b/libcpu/risc-v/t-head/c906/cpuport.c new file mode 100644 index 0000000000000000000000000000000000000000..8cfe0c44e5ad524ed27b7f088f6092d842116d37 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/cpuport.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + * 2021-02-11 lizhirui add gp support + * 2021-11-19 JasonHu add fpu support + */ + +#include +#include + +#include "cpuport.h" +#include "stack.h" + +#include + + +/** + * @brief from thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_from_thread = 0; +/** + * @brief to thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_to_thread = 0; +/** + * @brief flag to indicate context switch in interrupt or not + * + */ +volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; + + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + extern int __global_pointer$; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; + } + + frame->ra = (rt_ubase_t)texit; + frame->gp = (rt_ubase_t)&__global_pointer$; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + frame->user_sp_exc_stack = (rt_ubase_t)(((rt_ubase_t)stk) + sizeof(struct rt_hw_stack_frame)); + + /* force to supervisor mode(SPP=1) and set SPIE and SUM to 1 */ +#ifdef ENABLE_FPU + frame->sstatus = 0x00046120; /* enable FPU */ +#else + frame->sstatus = 0x00040120; +#endif + + return stk; +} + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + * #endif + */ +#ifndef RT_USING_SMP +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + + return ; +} +#endif /* end of RT_USING_SMP */ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +int rt_hw_cpu_id(void) +{ + return 0; /* d1 has one core */ +} diff --git a/libcpu/risc-v/t-head/c906/cpuport.h b/libcpu/risc-v/t-head/c906/cpuport.h new file mode 100644 index 0000000000000000000000000000000000000000..bb1065a714e7c23faebc791304942452175e120e --- /dev/null +++ b/libcpu/risc-v/t-head/c906/cpuport.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#include + +/* bytes of register width */ +#ifdef ARCH_CPU_64BIT +#define STORE sd +#define LOAD ld +#define REGBYTES 8 +#else +// error here, not portable +#endif + +/* 33 general register */ +#define CTX_GENERAL_REG_NR 33 + +#ifdef ENABLE_FPU +/* 32 fpu register */ +#define CTX_FPU_REG_NR 32 +#else +#define CTX_FPU_REG_NR 0 +#endif + +/* all context registers */ +#define CTX_REG_NR (CTX_GENERAL_REG_NR + CTX_FPU_REG_NR) + +#ifndef __ASSEMBLY__ +rt_inline void rt_hw_dsb() +{ + asm volatile("fence":::"memory"); +} + +rt_inline void rt_hw_dmb() +{ + asm volatile("fence":::"memory"); +} + +rt_inline void rt_hw_isb() +{ + asm volatile("fence.i":::"memory"); +} + +int rt_hw_cpu_id(void); + +#endif + +#endif +#ifdef RISCV_U_MODE +#define RISCV_USER_ENTRY 0xFFFFFFE000000000ULL +#endif diff --git a/libcpu/risc-v/t-head/c906/encoding.h b/libcpu/risc-v/t-head/c906/encoding.h new file mode 100644 index 0000000000000000000000000000000000000000..7197e6b84b30ee9abf075e94c8ae19fd40d5fc99 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/encoding.h @@ -0,0 +1,1331 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 /* Floating-point Status */ +#define SSTATUS_FS_INITIAL 0x00002000 +#define SSTATUS_FS_CLEAN 0x00004000 +#define SSTATUS_FS_DIRTY 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP /* software interrupt */ +#define SIP_STIP MIP_STIP /* timer interrupt */ +#define SIP_SEIP MIP_SEIP /* ext interrupt */ + +#define SIE_SSIE (1 << IRQ_S_SOFT) +#define SIE_STIE (1 << IRQ_S_TIMER) +#define SIE_SEIE (1 << IRQ_S_EXT) + +#define RISCV_XLEN 64 + +#define SCAUSE_INTERRUPT (1UL << (RISCV_XLEN - 1)) + +#define SCAUSE_S_SOFTWARE_INTR 1 +#define SCAUSE_S_TIMER_INTR 5 +#define SCAUSE_S_EXTERNAL_INTR 9 + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif /* end of __riscv64 */ + +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLY__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif /* end of __GNUC__ */ + +#endif /* end of __ASSEMBLY__ */ + +#endif /* end of __riscv */ + +#endif /* end of RISCV_CSR_ENCODING_H */ + +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/risc-v/t-head/c906/interrupt.c similarity index 32% rename from libcpu/aarch64/cortex-a72/interrupt.c rename to libcpu/risc-v/t-head/c906/interrupt.c index 3b689dceb3ab9b845aeac62d88e6967a786b921b..1cabe67587f3848df718fabc1f81a4eea58bfa9f 100644 --- a/libcpu/aarch64/cortex-a72/interrupt.c +++ b/libcpu/risc-v/t-head/c906/interrupt.c @@ -1,40 +1,29 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-04-16 bigmagic first version + * Date Author Notes + * 2021-10-19 JasonHu first version */ #include #include -#include -#include -#include -#define MAX_HANDLERS 256 -#define GIC_ACK_INTID_MASK 0x000003ff +#include "rt_interrupt.h" +#include "riscv.h" +#include "plic.h" -#ifdef RT_USING_SMP -#define rt_interrupt_nest rt_cpu_self()->irq_nest -#else -extern volatile rt_uint8_t rt_interrupt_nest; -#endif +extern rt_uint32_t rt_interrupt_nest; +extern rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +extern rt_uint32_t rt_thread_switch_interrupt_flag; -extern int system_vectors; +struct rt_irq_desc isr_table[INTERRUPTS_MAX]; -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; - -rt_ubase_t rt_interrupt_from_thread; -rt_ubase_t rt_interrupt_to_thread; -rt_ubase_t rt_thread_switch_interrupt_flag; - -void rt_hw_vector_init(void) +static void rt_hw_interrupt_handler(int vector, void *param) { - rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -42,43 +31,22 @@ void rt_hw_vector_init(void) */ void rt_hw_interrupt_init(void) { + /* init interrupt controller */ + plic_init(); - rt_uint32_t gic_cpu_base = 0; - rt_uint32_t gic_dist_base = 0; - - /* initialize ARM GIC */ - gic_dist_base = GIC_PL400_DISTRIBUTOR_PPTR; - gic_cpu_base = GIC_PL400_CONTROLLER_PPTR; - arm_gic_dist_init(0, gic_dist_base, 0); - arm_gic_cpu_init(0, gic_cpu_base); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; + rt_int32_t idx; - if (vector < MAX_HANDLERS) + rt_memset(isr_table, 0x00, sizeof(isr_table)); + for (idx = 0; idx < INTERRUPTS_MAX; idx++) { - old_handler = isr_table[vector].handler; - - if (handler != RT_NULL) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } + isr_table[idx].handler = rt_hw_interrupt_handler; } - return old_handler; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -87,32 +55,51 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, */ void rt_hw_interrupt_mask(int vector) { - arm_gic_mask(0, vector); + if ((vector < 0) || (vector > IRQ_MAX_NR)) + { + return; + } + plic_disable_irq(vector); } /** + * This function will un-mask a interrupt. * @param vector the interrupt number */ void rt_hw_interrupt_umask(int vector) { - arm_gic_umask(0, vector); -} - -/** - * This function returns the active interrupt number. - * @param none - */ -int rt_hw_interrupt_get_irq(void) -{ - return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; + if ((vector < 0) || (vector > IRQ_MAX_NR)) + { + return; + } + plic_enable_irq(vector); } /** - * This function acknowledges the interrupt. + * This function will install a interrupt service routine to a interrupt. * @param vector the interrupt number + * @param handler the interrupt service routine to be installed + * @param param the interrupt service function parameter + * @param name the interrupt name + * @return old handler */ -void rt_hw_interrupt_ack(int vector) +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) { - arm_gic_ack(0, vector); + rt_isr_handler_t old_handler = RT_NULL; + if ((vector < 0) || (vector > IRQ_MAX_NR)) + { + return old_handler; + } + + old_handler = isr_table[IRQ_OFFSET + vector].handler; + +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[IRQ_OFFSET + vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[IRQ_OFFSET + vector].handler = handler; + isr_table[IRQ_OFFSET + vector].param = param; + + return old_handler; } diff --git a/libcpu/risc-v/t-head/c906/interrupt_gcc.S b/libcpu/risc-v/t-head/c906/interrupt_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..d3cc9bae7af254a311ce5975e4652dfd31069894 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/interrupt_gcc.S @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/02 Bernard The first version + * 2018/12/27 Jesven Add SMP schedule + * 2021/02/02 lizhirui Add userspace support + * 2021/12/24 JasonHu Add user setting save/restore + */ + +#define __ASSEMBLY__ +#include "cpuport.h" +#include "encoding.h" +#include "stackframe.h" + + .section .text.entry + .align 2 + .global trap_entry + .extern __stack_cpu0 + .extern get_current_thread_kernel_stack_top +trap_entry: + //backup sp + csrrw sp, sscratch, sp + //load interrupt stack + la sp, __stack_cpu0 + //backup context + SAVE_ALL + + RESTORE_SYS_GP + + //check syscall + csrr t0, scause + li t1, 8//environment call from u-mode + beq t0, t1, syscall_entry + + csrr a0, scause + csrrc a1, stval, zero + csrr a2, sepc + mv a3, sp + + /* scause, stval, sepc, sp */ + call handle_trap + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + lw s2, 0(s0) + beqz s2, spurious_interrupt + sw zero, 0(s0) + +.global rt_hw_context_switch_interrupt_do +rt_hw_context_switch_interrupt_do: + +//swap to thread kernel stack + csrr t0, sstatus + andi t0, t0, 0x100 + beqz t0, __restore_sp_from_tcb_interrupt + +__restore_sp_from_sscratch_interrupt: + csrr t0, sscratch + j __move_stack_context_interrupt + +__restore_sp_from_tcb_interrupt: + la s0, rt_interrupt_from_thread + LOAD a0, 0(s0) + jal rt_thread_sp_to_thread + jal get_thread_kernel_stack_top + mv t0, a0 + +__move_stack_context_interrupt: + mv t1, sp//src + mv sp, t0//switch stack + addi sp, sp, -CTX_REG_NR * REGBYTES + //copy context + li s0, CTX_REG_NR//cnt + mv t2, sp//dst + +copy_context_loop_interrupt: + LOAD t0, 0(t1) + STORE t0, 0(t2) + addi s0, s0, -1 + addi t1, t1, 8 + addi t2, t2, 8 + bnez s0, copy_context_loop_interrupt + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + + #ifdef RT_USING_USERSPACE + mv a0, s1 + jal rt_thread_sp_to_thread + jal lwp_mmu_switch + #endif + +spurious_interrupt: + RESTORE_ALL + sret + +syscall_entry: + //swap to thread kernel stack + csrr t0, sstatus + andi t0, t0, 0x100 + beqz t0, __restore_sp_from_tcb + +__restore_sp_from_sscratch: + csrr t0, sscratch + j __move_stack_context + +__restore_sp_from_tcb: + la a0, rt_current_thread + LOAD a0, 0(a0) + jal get_thread_kernel_stack_top + mv t0, a0 + +__move_stack_context: + mv t1, sp//src + mv sp, t0//switch stack + addi sp, sp, -CTX_REG_NR * REGBYTES + //copy context + li s0, CTX_REG_NR//cnt + mv t2, sp//dst + +copy_context_loop: + LOAD t0, 0(t1) + STORE t0, 0(t2) + addi s0, s0, -1 + addi t1, t1, 8 + addi t2, t2, 8 + bnez s0, copy_context_loop + + LOAD s0, 7 * REGBYTES(sp) + addi s0, s0, -0xfe + beqz s0, lwp_signal_quit + +#ifdef RT_USING_USERSPACE + /* save setting when syscall enter */ + call rt_thread_self + call lwp_user_setting_save +#endif + + mv a0, sp + OPEN_INTERRUPT + call syscall_handler + CLOSE_INTERRUPT + +.global syscall_exit +syscall_exit: + + #if defined(RT_USING_USERSPACE) && defined(RT_USING_SIGNALS) + LOAD s0, 2 * REGBYTES(sp) + andi s0, s0, 0x100 + bnez s0, dont_ret_to_user + li s0, 0 + j ret_to_user + dont_ret_to_user: + #endif + +#ifdef RT_USING_USERSPACE + /* restore setting when syscall exit */ + call rt_thread_self + call lwp_user_setting_restore + + /* after restore the reg `tp`, need modify context */ + STORE tp, 4 * REGBYTES(sp) +#endif + + //restore context + RESTORE_ALL + sret + +.global rt_hw_interrupt_enable +rt_hw_interrupt_enable: + csrs sstatus, a0 /* restore to old csr */ + jr ra + +.global rt_hw_interrupt_disable +rt_hw_interrupt_disable: + csrrci a0, sstatus, 2 /* clear SIE */ + jr ra diff --git a/libcpu/risc-v/t-head/c906/io.h b/libcpu/risc-v/t-head/c906/io.h new file mode 100644 index 0000000000000000000000000000000000000000..1285d5955bfd26a3e214f4f7806f96f7c31beaca --- /dev/null +++ b/libcpu/risc-v/t-head/c906/io.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ +#ifndef ARCH_IO_H +#define ARCH_IO_H +#include +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") + +/* These barriers need to enforce ordering on both devices or memory. */ +#define mb() RISCV_FENCE(iorw,iorw) +#define rmb() RISCV_FENCE(ir,ir) +#define wmb() RISCV_FENCE(ow,ow) + +#define __arch_getl(a) (*(unsigned int *)(a)) +#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) + +#define dmb() mb() +#define __iormb() rmb() +#define __iowmb() wmb() + +static inline void writel(uint32_t val, volatile void *addr) +{ + __iowmb(); + __arch_putl(val, addr); +} + +static inline uint32_t readl(const volatile void *addr) +{ + uint32_t val; + + val = __arch_getl(addr); + __iormb(); + return val; +} + +static inline void write_reg( + uint32_t val, volatile void *addr, unsigned offset) +{ + writel(val, addr + offset); +} + +static inline uint32_t read_reg( + const volatile void *addr, unsigned offset) +{ + return readl(addr + offset); +} + +#endif // ARCH_IO_H diff --git a/libcpu/risc-v/t-head/c906/mmu.c b/libcpu/risc-v/t-head/c906/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..9bcaade31cb513db5dffcd4a3c2ab7fd5a2777c7 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/mmu.c @@ -0,0 +1,635 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#include +#include +#include +#include "page.h" +#include +#include +#include + +#include "riscv.h" +#include "riscv_mmu.h" +#include "mmu.h" + +void *current_mmu_table = RT_NULL; + +static void rt_hw_cpu_tlb_invalidate() +{ + rt_size_t satpv = read_csr(satp); + write_csr(satp,satpv); + mmu_flush_tlb(); +} + +void *mmu_table_get() +{ + return current_mmu_table; +} + +void switch_mmu(void *mmu_table) +{ + current_mmu_table = mmu_table; + RT_ASSERT(__CHECKALIGN(mmu_table,PAGE_OFFSET_BIT)); + mmu_set_pagetable((rt_ubase_t)mmu_table); + rt_hw_cpu_dcache_clean_all(); + rt_hw_cpu_icache_invalidate_all(); +} + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info,void *v_address,rt_size_t size,rt_size_t *vtable,rt_size_t pv_off) +{ + size_t l1_off,va_s,va_e; + rt_base_t level; + + if((!mmu_info) || (!vtable)) + { + return -1; + } + + va_s = (rt_size_t)v_address; + va_e = ((rt_size_t)v_address) + size - 1; + + if(va_e < va_s) + { + return -1; + } + + //convert address to level 1 page frame id + va_s = GET_L1(va_s); + va_e = GET_L1(va_e); + + if(va_s == 0) + { + return -1; + } + + level = rt_hw_interrupt_disable(); + + //vtable initialization check + for(l1_off = va_s;l1_off <= va_e;l1_off++) + { + size_t v = vtable[l1_off]; + + if(v) + { + rt_hw_interrupt_enable(level); + return 0; + } + } + + mmu_info -> vtable = vtable; + mmu_info -> vstart = va_s; + mmu_info -> vend = va_e; + mmu_info -> pv_off = pv_off; + + rt_hw_interrupt_enable(level); + return 0; +} + +void rt_hw_mmu_kernel_map_init(rt_mmu_info *mmu_info,rt_size_t vaddr_start,rt_size_t size) +{ + rt_size_t paddr_start = __UMASKVALUE(VPN_TO_PPN(vaddr_start,mmu_info -> pv_off),PAGE_OFFSET_MASK); + rt_size_t va_s = GET_L1(vaddr_start); + rt_size_t va_e = GET_L1(vaddr_start + size - 1); + rt_size_t i; + + for(i = va_s;i <= va_e;i++) + { + mmu_info -> vtable[i] = COMBINEPTE(paddr_start,PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE | PTE_SHARE | PTE_BUF | PTE_A | PTE_D); + paddr_start += L1_PAGE_SIZE; + } + + rt_hw_cpu_tlb_invalidate(); +} + +//find a range of free virtual address specified by pages +static rt_size_t find_vaddr(rt_mmu_info *mmu_info,rt_size_t pages) +{ + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t find_l1 = 0,find_l2 = 0,find_l3 = 0; + rt_size_t n = 0; + + if(!pages) + { + return 0; + } + + if(!mmu_info) + { + return 0; + } + + for(l1_off = mmu_info -> vstart;l1_off <= mmu_info -> vend;l1_off++) + { + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + + if(PTE_USED(*mmu_l1)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off); + + for(l2_off = 0;l2_off < __SIZE(VPN1_BIT);l2_off++) + { + if(PTE_USED(*(mmu_l2 + l2_off))) + { + RT_ASSERT(!PAGE_IS_LEAF(*(mmu_l2 + l2_off))); + mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)),mmu_info -> pv_off); + + for(l3_off = 0;l3_off < __SIZE(VPN0_BIT);l3_off++) + { + if(PTE_USED(*(mmu_l3 + l3_off))) + { + RT_ASSERT(PAGE_IS_LEAF(*(mmu_l3 + l3_off))); + n = 0;//in use + } + else + { + if(!n) + { + find_l1 = l1_off; + find_l2 = l2_off; + find_l3 = l3_off; + } + + n++; + + if(n >= pages) + { + return COMBINEVADDR(find_l1,find_l2,find_l3); + } + } + } + } + else + { + if(!n) + { + find_l1 = l1_off; + find_l2 = l2_off; + find_l3 = 0; + } + + n += __SIZE(VPN0_BIT); + + if(n >= pages) + { + return COMBINEVADDR(find_l1,find_l2,find_l3); + } + } + } + } + else + { + if(!n) + { + find_l1 = l1_off; + find_l2 = 0; + find_l3 = 0; + } + + n += __SIZE(VPN1_BIT); + + if(n >= pages) + { + return COMBINEVADDR(find_l1,find_l2,find_l3); + } + } + } + + return 0; +} + +//check whether the range of virtual address are free +static int check_vaddr(rt_mmu_info *mmu_info,void *va,rt_size_t pages) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)va,PAGE_OFFSET_MASK); + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + + if(!pages) + { + return -1; + } + + if(!mmu_info) + { + return -1; + } + + while(pages--) + { + l1_off = GET_L1(loop_va); + l2_off = GET_L2(loop_va); + l3_off = GET_L3(loop_va); + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + + if(PTE_USED(*mmu_l1)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off) + l2_off; + + if(PTE_USED(*mmu_l2)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l2)); + mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l2),mmu_info -> pv_off) + l3_off; + + if(PTE_USED(*mmu_l3)) + { + RT_ASSERT(PAGE_IS_LEAF(*mmu_l3)); + return -1; + } + } + } + + loop_va += PAGE_SIZE; + } + + return 0; +} + +static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t npages) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t *ref_cnt; + + RT_ASSERT(mmu_info); + + while(npages--) + { + l1_off = (rt_size_t)GET_L1(loop_va); + RT_ASSERT((l1_off >= mmu_info -> vstart) && (l1_off <= mmu_info -> vend)); + l2_off = (rt_size_t)GET_L2(loop_va); + l3_off = (rt_size_t)GET_L3(loop_va); + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + RT_ASSERT(PTE_USED(*mmu_l1)) + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = ((rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off)) + l2_off; + RT_ASSERT(PTE_USED(*mmu_l2)); + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l2)); + mmu_l3 = ((rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l2),mmu_info -> pv_off)) + l3_off; + RT_ASSERT(PTE_USED(*mmu_l3)); + RT_ASSERT(PAGE_IS_LEAF(*(mmu_l3))); + *mmu_l3 = 0; + rt_hw_cpu_dcache_clean(mmu_l3,sizeof(*mmu_l3)); + mmu_l3 -= l3_off; + ref_cnt = mmu_l3 + __SIZE(VPN0_BIT); + (*ref_cnt)--; + + if(!*ref_cnt) + { + //release level 3 page + rt_pages_free(mmu_l3,1);//entry page and ref_cnt page + *mmu_l2 = 0; + rt_hw_cpu_dcache_clean(mmu_l2,sizeof(*mmu_l2)); + mmu_l2 -= l2_off; + + ref_cnt = mmu_l2 + __SIZE(VPN1_BIT); + (*ref_cnt)--; + + if(!*ref_cnt) + { + //release level 2 page + rt_pages_free(mmu_l2,1);//entry page and ref_cnt page + *mmu_l1 = 0; + rt_hw_cpu_dcache_clean(mmu_l1,sizeof(*mmu_l1)); + } + } + + loop_va += PAGE_SIZE; + } +} + +static int __rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t npages,rt_size_t attr) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + rt_size_t loop_pa = __UMASKVALUE((rt_size_t)p_addr,PAGE_OFFSET_MASK); + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t *ref_cnt; + //rt_kprintf("v_addr = 0x%p,p_addr = 0x%p,npages = %lu\n",v_addr,p_addr,npages); + + if(!mmu_info) + { + return -1; + } + + while(npages--) + { + l1_off = GET_L1(loop_va); + l2_off = GET_L2(loop_va); + l3_off = GET_L3(loop_va); + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + + if(PTE_USED(*mmu_l1)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off); + } + else + { + mmu_l2 = (rt_size_t *)rt_pages_alloc(1); + + if(mmu_l2) + { + rt_memset(mmu_l2,0,PAGE_SIZE * 2); + rt_hw_cpu_dcache_clean(mmu_l2,PAGE_SIZE * 2); + *mmu_l1 = COMBINEPTE((rt_size_t)VPN_TO_PPN(mmu_l2,mmu_info -> pv_off),PAGE_DEFAULT_ATTR_NEXT); + rt_hw_cpu_dcache_clean(mmu_l1,sizeof(*mmu_l1)); + } + else + { + __rt_hw_mmu_unmap(mmu_info,v_addr,npages); + return -1; + } + } + + if(PTE_USED(*(mmu_l2 + l2_off))) + { + RT_ASSERT(!PAGE_IS_LEAF(*(mmu_l2 + l2_off))); + mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)),mmu_info -> pv_off); + } + else + { + mmu_l3 = (rt_size_t *)rt_pages_alloc(1); + + if(mmu_l3) + { + rt_memset(mmu_l3,0,PAGE_SIZE * 2); + rt_hw_cpu_dcache_clean(mmu_l3,PAGE_SIZE * 2); + *(mmu_l2 + l2_off) = COMBINEPTE((rt_size_t)VPN_TO_PPN(mmu_l3,mmu_info -> pv_off),PAGE_DEFAULT_ATTR_NEXT); + rt_hw_cpu_dcache_clean(mmu_l2,sizeof(*mmu_l2)); + ref_cnt = mmu_l2 + __SIZE(VPN1_BIT); + (*ref_cnt)++; + } + else + { + __rt_hw_mmu_unmap(mmu_info,v_addr,npages); + return -1; + } + } + + RT_ASSERT(!PTE_USED(*(mmu_l3 + l3_off))); + ref_cnt = mmu_l3 + __SIZE(VPN0_BIT); + (*ref_cnt)++; + *(mmu_l3 + l3_off) = COMBINEPTE((rt_size_t)loop_pa,PAGE_DEFAULT_ATTR_LEAF); + rt_hw_cpu_dcache_clean(mmu_l3 + l3_off,sizeof(*(mmu_l3 + l3_off))); + + loop_va += PAGE_SIZE; + loop_pa += PAGE_SIZE; + } + + return 0; +} + +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr) +{ + rt_size_t pa_s,pa_e; + rt_size_t vaddr; + rt_size_t pages; + int ret; + + if(!size) + { + return 0; + } + + pa_s = (rt_size_t)p_addr; + pa_e = ((rt_size_t)p_addr) + size - 1; + pa_s = GET_PF_ID(pa_s); + pa_e = GET_PF_ID(pa_e); + pages = pa_e - pa_s + 1; + + if(v_addr) + { + vaddr = (rt_size_t)v_addr; + pa_s = (rt_size_t)p_addr; + + if(GET_PF_OFFSET(vaddr) != GET_PF_OFFSET(pa_s)) + { + return 0; + } + + vaddr = __UMASKVALUE(vaddr,PAGE_OFFSET_MASK); + + if(check_vaddr(mmu_info,(void *)vaddr,pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info,pages); + } + + if(vaddr) + { + ret = __rt_hw_mmu_map(mmu_info,(void *)vaddr,p_addr,pages,attr); + + if(ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void *)(vaddr | GET_PF_OFFSET((rt_size_t)p_addr)); + } + } + + return 0; +} + +static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t npages,rt_size_t attr) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + rt_size_t loop_pa; + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t *ref_cnt; + rt_size_t i; + void *va,*pa; + + if(!mmu_info) + { + return -1; + } + + while(npages--) + { + loop_pa = (rt_size_t)rt_pages_alloc(0); + + if(!loop_pa) + { + goto err; + } + + if(__rt_hw_mmu_map(mmu_info,(void *)loop_va,(void *)loop_pa,1,attr) < 0) + { + goto err; + } + + loop_va += PAGE_SIZE; + } + + return 0; + + err: + va = (void *)__UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + + for(i = 0;i < npages;i++) + { + pa = rt_hw_mmu_v2p(mmu_info,va); + + if(pa) + { + rt_pages_free((void *)PPN_TO_VPN(pa,mmu_info -> pv_off),0); + } + + va = (void *)((rt_uint8_t *)va + PAGE_SIZE); + } + + __rt_hw_mmu_unmap(mmu_info,v_addr,npages); + return -1; +} + +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr) +{ + rt_size_t vaddr; + rt_size_t offset; + rt_size_t pages; + int ret; + + if(!size) + { + return 0; + } + + offset = GET_PF_OFFSET((rt_size_t)v_addr); + size += (offset + PAGE_SIZE - 1); + pages = size >> PAGE_OFFSET_BIT; + + if(v_addr) + { + vaddr = __UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + + if(check_vaddr(mmu_info,(void *)vaddr,pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info,pages); + } + + if(vaddr) + { + ret = __rt_hw_mmu_map_auto(mmu_info,(void *)vaddr,pages,attr); + + if(ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void *)(vaddr | offset); + } + } + + return 0; +} + +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size) +{ + rt_size_t va_s,va_e; + rt_size_t pages; + + va_s = ((rt_size_t)v_addr) >> PAGE_OFFSET_BIT; + va_e = (((rt_size_t)v_addr) + size - 1) >> PAGE_OFFSET_BIT; + pages = va_e - va_s + 1; + __rt_hw_mmu_unmap(mmu_info,v_addr,pages); + rt_hw_cpu_tlb_invalidate(); +} + +void *rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map(mmu_info,v_addr,p_addr,size,attr); + rt_hw_interrupt_enable(level); + return ret; +} + +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map_auto(mmu_info,v_addr,size,attr); + rt_hw_interrupt_enable(level); + return ret; +} + +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + _rt_hw_mmu_unmap(mmu_info,v_addr,size); + rt_hw_interrupt_enable(level); +} + +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr) +{ + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t pa; + + l1_off = GET_L1((rt_size_t)v_addr); + l2_off = GET_L2((rt_size_t)v_addr); + l3_off = GET_L3((rt_size_t)v_addr); + + if(!mmu_info) + { + return RT_NULL; + } + + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + + if(PTE_USED(*mmu_l1)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off); + + if(PTE_USED(*(mmu_l2 + l2_off))) + { + RT_ASSERT(!PAGE_IS_LEAF(*(mmu_l2 + l2_off))); + mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)),mmu_info -> pv_off); + + if(PTE_USED(*(mmu_l3 + l3_off))) + { + RT_ASSERT(PAGE_IS_LEAF(*(mmu_l3 + l3_off))); + return (void *)(GET_PADDR(*(mmu_l3 + l3_off)) | GET_PF_OFFSET((rt_size_t)v_addr)); + } + } + } + + return RT_NULL; +} + +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_v2p(mmu_info,v_addr); + rt_hw_interrupt_enable(level); + return ret; +} diff --git a/libcpu/risc-v/t-head/c906/mmu.h b/libcpu/risc-v/t-head/c906/mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..8ad4c1c32a591ea171a9ea94dfd8d20844c3858f --- /dev/null +++ b/libcpu/risc-v/t-head/c906/mmu.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#ifndef __MMU_H__ +#define __MMU_H__ + +#include "riscv.h" +#include "riscv_mmu.h" +struct mem_desc +{ + rt_size_t vaddr_start; + rt_size_t vaddr_end; + rt_size_t paddr_start; + rt_size_t attr; +}; + +#define GET_PF_ID(addr) ((addr) >> PAGE_OFFSET_BIT) +#define GET_PF_OFFSET(addr) __MASKVALUE(addr,PAGE_OFFSET_MASK) +#define GET_L1(addr) __PARTBIT(addr,VPN2_SHIFT,VPN2_BIT) +#define GET_L2(addr) __PARTBIT(addr,VPN1_SHIFT,VPN1_BIT) +#define GET_L3(addr) __PARTBIT(addr,VPN0_SHIFT,VPN0_BIT) +#define GET_PPN(pte) (__PARTBIT(pte,PTE_PPN_SHIFT,PHYSICAL_ADDRESS_WIDTH_BITS - PTE_PPN_SHIFT)) +#define GET_PADDR(pte) (GET_PPN(pte) << PAGE_OFFSET_BIT) +#define VPN_TO_PPN(vaddr,pv_off) (((rt_size_t)(vaddr)) + (pv_off)) +#define PPN_TO_VPN(paddr,pv_off) (((rt_size_t)(paddr)) - (pv_off)) +#define COMBINEVADDR(l1_off,l2_off,l3_off) (((l1_off) << VPN2_SHIFT) | ((l2_off) << VPN1_SHIFT) | ((l3_off) << VPN0_SHIFT)) +#define COMBINEPTE(paddr,attr) ((((paddr) >> PAGE_OFFSET_BIT) << PTE_PPN_SHIFT) | (attr)) + +typedef struct +{ + size_t *vtable; + size_t vstart; + size_t vend; + size_t pv_off; +}rt_mmu_info; + +void *mmu_table_get(); +void switch_mmu(void *mmu_table); +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info,void *v_address,rt_size_t size,rt_size_t *vtable,rt_size_t pv_off); +void rt_hw_mmu_kernel_map_init(rt_mmu_info *mmu_info,rt_size_t vaddr_start,rt_size_t size); +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr); +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr); +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size); +void *rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr); +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr); +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size); +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr); +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr); + +#endif diff --git a/libcpu/risc-v/t-head/c906/plic.c b/libcpu/risc-v/t-head/c906/plic.c new file mode 100644 index 0000000000000000000000000000000000000000..796bdfc967f6878ceaa01900b927bba857363c03 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/plic.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-19 JasonHu first version + * 2021-11-12 JasonHu fix bug that not intr on f133 + */ + +#include + +#include + +#include "plic.h" +#include "rt_interrupt.h" +#include "io.h" +#include "encoding.h" + +static void *c906_plic_regs = RT_NULL; + +struct plic_handler +{ + rt_bool_t present; + void *hart_base; + void *enable_base; +}; + +rt_inline void plic_toggle(struct plic_handler *handler, int hwirq, int enable); +struct plic_handler c906_plic_handlers[C906_NR_CPUS]; + +rt_inline void plic_irq_toggle(int hwirq, int enable) +{ + int cpu = 0; + + /* set priority of interrupt, interrupt 0 is zero. */ + writel(enable, c906_plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); + struct plic_handler *handler = &c906_plic_handlers[cpu]; + + if (handler->present) + { + plic_toggle(handler, hwirq, enable); + } +} + +void plic_complete(int irqno) +{ + int cpu = 0; + struct plic_handler *handler = &c906_plic_handlers[cpu]; + + writel(irqno, handler->hart_base + CONTEXT_CLAIM); +} + +void plic_disable_irq(int irqno) +{ + plic_irq_toggle(irqno, 0); +} + +void plic_enable_irq(int irqno) +{ + plic_irq_toggle(irqno, 1); +} + +/* + * Handling an interrupt is a two-step process: first you claim the interrupt + * by reading the claim register, then you complete the interrupt by writing + * that source ID back to the same claim register. This automatically enables + * and disables the interrupt, so there's nothing else to do. + */ +void plic_handle_irq(void) +{ + int cpu = 0; + unsigned int irq; + + struct plic_handler *handler = &c906_plic_handlers[cpu]; + void *claim = handler->hart_base + CONTEXT_CLAIM; + + if (c906_plic_regs == RT_NULL || !handler->present) + { + LOG_E("plic state not initialized."); + return; + } + + clear_csr(sie, SIE_SEIE); + + while ((irq = readl(claim))) + { + /* ID0 is diabled permantually from spec. */ + if (irq == 0) + { + LOG_E("irq no is zero."); + } + else + { + generic_handle_irq(irq); + } + } + set_csr(sie, SIE_SEIE); +} + +rt_inline void plic_toggle(struct plic_handler *handler, int hwirq, int enable) +{ + uint32_t *reg = handler->enable_base + (hwirq / 32) * sizeof(uint32_t); + uint32_t hwirq_mask = 1 << (hwirq % 32); + + if (enable) + { + writel(readl(reg) | hwirq_mask, reg); + } + else + { + writel(readl(reg) & ~hwirq_mask, reg); + } +} + +void plic_init(void) +{ + int nr_irqs; + int nr_context; + int i; + unsigned long hwirq; + int cpu = 0; + + if (c906_plic_regs) + { + LOG_E("plic already initialized!"); + return; + } + + nr_context = C906_NR_CONTEXT; + + c906_plic_regs = (void *)C906_PLIC_PHY_ADDR; + if (!c906_plic_regs) + { + LOG_E("fatal error, plic is reg space is null."); + return; + } + + nr_irqs = C906_PLIC_NR_EXT_IRQS; + + for (i = 0; i < nr_context; i ++) + { + struct plic_handler *handler; + uint32_t threshold = 0; + + cpu = 0; + + /* skip contexts other than supervisor external interrupt */ + if (i == 0) + { + continue; + } + + // we always use CPU0 M-mode target register. + handler = &c906_plic_handlers[cpu]; + if (handler->present) + { + threshold = 0xffffffff; + goto done; + } + + handler->present = RT_TRUE; + handler->hart_base = c906_plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART; + handler->enable_base = c906_plic_regs + ENABLE_BASE + i * ENABLE_PER_HART; +done: + /* priority must be > threshold to trigger an interrupt */ + writel(threshold, handler->hart_base + CONTEXT_THRESHOLD); + for (hwirq = 1; hwirq <= nr_irqs; hwirq++) + { + plic_toggle(handler, hwirq, 0); + } + } + + /* Enable supervisor external interrupts. */ + set_csr(sie, SIE_SEIE); +} diff --git a/libcpu/risc-v/t-head/c906/plic.h b/libcpu/risc-v/t-head/c906/plic.h new file mode 100644 index 0000000000000000000000000000000000000000..727782c11dfe475b1515f200bc0846be0dc56e1a --- /dev/null +++ b/libcpu/risc-v/t-head/c906/plic.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-19 JasonHu first version + */ + +#ifndef __RISCV64_PLIC_H__ +#define __RISCV64_PLIC_H__ + +#include + +#define C906_PLIC_PHY_ADDR (0x10000000) +#define C906_PLIC_NR_EXT_IRQS (IRQ_MAX_NR) +#define C906_NR_CPUS (NR_CPUS) + +/* M and S mode context. */ +#define C906_NR_CONTEXT (2) + +#define MAX_DEVICES 1024 +#define MAX_CONTEXTS 15872 + +/* + * Each interrupt source has a priority register associated with it. + * We always hardwire it to one in Linux. + */ +#define PRIORITY_BASE 0 +#define PRIORITY_PER_ID 4 + +/* + * Each hart context has a vector of interrupt enable bits associated with it. + * There's one bit for each interrupt source. + */ +#define ENABLE_BASE 0x2000 +#define ENABLE_PER_HART 0x80 + +/* + * Each hart context has a set of control registers associated with it. Right + * now there's only two: a source priority threshold over which the hart will + * take an interrupt, and a register to claim interrupts. + */ +#define CONTEXT_BASE 0x200000 +#define CONTEXT_PER_HART 0x1000 +#define CONTEXT_THRESHOLD 0x00 +#define CONTEXT_CLAIM 0x04 + +void plic_init(void); +void plic_enable_irq(int irqno); +void plic_disable_irq(int irqno); +// tell PLIC that we've served this IRQ +void plic_complete(int irq); +void plic_handle_irq(void); + +#endif diff --git a/libcpu/risc-v/t-head/c906/riscv.h b/libcpu/risc-v/t-head/c906/riscv.h new file mode 100644 index 0000000000000000000000000000000000000000..d0c0cc4b38ae4c0c60dc35a8015798732d571262 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/riscv.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#ifndef __RISCV_H__ +#define __RISCV_H__ + +#include + +#define __SIZE(bit) (1UL << (bit)) +#define __MASK(bit) (__SIZE(bit) - 1UL) +#define __UMASK(bit) (~(__MASK(bit))) +#define __MASKVALUE(value,maskvalue) ((value) & (maskvalue)) +#define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue))) +#define __CHECKUPBOUND(value,bit_count) (!(((rt_size_t)value) & (~__MASK(bit_count)))) +#define __CHECKALIGN(value,start_bit) (!(((rt_size_t)value) & (__MASK(start_bit)))) + +#define __PARTBIT(value,start_bit,length) (((value) >> (start_bit)) & __MASK(length)) + +#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit)) +#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit)) + +#endif diff --git a/libcpu/risc-v/t-head/c906/riscv_io.h b/libcpu/risc-v/t-head/c906/riscv_io.h new file mode 100644 index 0000000000000000000000000000000000000000..cde0495b293692c024c5254d26c39f5b12ae3ec0 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/riscv_io.h @@ -0,0 +1,109 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_IO_H__ +#define __RISCV_IO_H__ + + static inline void __raw_writeb(rt_uint8_t val, volatile void *addr) + { + asm volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr)); + } + + static inline void __raw_writew(rt_uint16_t val, volatile void *addr) + { + asm volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr)); + } + + static inline void __raw_writel(rt_uint32_t val, volatile void *addr) + { + asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr)); + } + + #if __riscv_xlen != 32 + static inline void __raw_writeq(rt_uint64_t val, volatile void *addr) + { + asm volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr)); + } + #endif + + static inline rt_uint8_t __raw_readb(const volatile void *addr) + { + rt_uint8_t val; + + asm volatile("lb %0, 0(%1)" : "=r"(val) : "r"(addr)); + return val; + } + + static inline rt_uint16_t __raw_readw(const volatile void *addr) + { + rt_uint16_t val; + + asm volatile("lh %0, 0(%1)" : "=r"(val) : "r"(addr)); + return val; + } + + static inline rt_uint32_t __raw_readl(const volatile void *addr) + { + rt_uint32_t val; + + asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr)); + return val; + } + + #if __riscv_xlen != 32 + static inline rt_uint64_t __raw_readq(const volatile void *addr) + { + rt_uint64_t val; + + asm volatile("ld %0, 0(%1)" : "=r"(val) : "r"(addr)); + return val; + } + #endif + + /* FIXME: These are now the same as asm-generic */ + + /* clang-format off */ + + #define __io_rbr() do {} while (0) + #define __io_rar() do {} while (0) + #define __io_rbw() do {} while (0) + #define __io_raw() do {} while (0) + + #define readb_relaxed(c) ({ rt_uint8_t __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; }) + #define readw_relaxed(c) ({ rt_uint16_t __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; }) + #define readl_relaxed(c) ({ rt_uint32_t __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; }) + + #define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); }) + #define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); }) + #define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); }) + + #if __riscv_xlen != 32 + #define readq_relaxed(c) ({ rt_uint64_t __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; }) + #define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); }) + #endif + + #define __io_br() do {} while (0) + #define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory"); + #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory"); + #define __io_aw() do {} while (0) + + #define readb(c) ({ rt_uint8_t __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; }) + #define readw(c) ({ rt_uint16_t __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; }) + #define readl(c) ({ rt_uint32_t __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; }) + + #define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); }) + #define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); }) + #define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); }) + + #if __riscv_xlen != 32 + #define readq(c) ({ rt_uint64_t __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; }) + #define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); }) + #endif + +#endif diff --git a/libcpu/risc-v/t-head/c906/riscv_mmu.c b/libcpu/risc-v/t-head/c906/riscv_mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..9ba48e34c42c0067212743fbc76ee069bb6a8aa3 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/riscv_mmu.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#include +#include + +#include +#include +#include +#include + +#include "riscv_mmu.h" + +void mmu_set_pagetable(rt_ubase_t addr) +{ + RT_ASSERT(__CHECKALIGN(addr,PAGE_OFFSET_BIT)); + RT_ASSERT(__CHECKUPBOUND(addr,PHYSICAL_ADDRESS_WIDTH_BITS)); + write_csr(satp,(((size_t)8) << 60) | (addr >> PAGE_OFFSET_BIT)); + mmu_flush_tlb(); +} + +void mmu_enable_user_page_access() +{ + set_csr(sstatus,SSTATUS_PUM); +} + +void mmu_disable_user_page_access() +{ + clear_csr(sstatus,SSTATUS_PUM); +} diff --git a/libcpu/risc-v/t-head/c906/riscv_mmu.h b/libcpu/risc-v/t-head/c906/riscv_mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..138bd596e9aaa68c33fc2648c45ecf3231655a13 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/riscv_mmu.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + * 2021-05-03 lizhirui porting to c906 + */ + +#ifndef __RISCV_MMU_H__ +#define __RISCV_MMU_H__ + +#include +#include +#include "riscv.h" + +#undef PAGE_SIZE + +/* C-SKY extend */ +#define PTE_SEC (1UL << 59) /* Security */ +#define PTE_SHARE (1UL << 60) /* Shareable */ +#define PTE_BUF (1UL << 61) /* Bufferable */ +#define PTE_CACHE (1UL << 62) /* Cacheable */ +#define PTE_SO (1UL << 63) /* Strong Order */ + +#define PAGE_OFFSET_SHIFT 0 +#define PAGE_OFFSET_BIT 12 +#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT) +#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT) +#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT) +#define VPN0_BIT 9 +#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT) +#define VPN1_BIT 9 +#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT) +#define VPN2_BIT 9 + +#define PPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT) +#define PPN0_BIT 9 +#define PPN1_SHIFT (PPN0_SHIFT + PPN0_BIT) +#define PPN1_BIT 9 +#define PPN2_SHIFT (PPN1_SHIFT + PPN1_BIT) +#define PPN2_BIT 26 + +#define L1_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT + VPN1_BIT) +#define L2_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT) +#define L3_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT) + +#define ARCH_ADDRESS_WIDTH_BITS 64 + +#define PHYSICAL_ADDRESS_WIDTH_BITS 56 + +#define PAGE_ATTR_NEXT_LEVEL (0) +#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R) +#define PAGE_ATTR_READONLY (PTE_R) +#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R) + +#define PAGE_ATTR_USER (PTE_U) +#define PAGE_ATTR_SYSTEM (0) + +#define PAGE_DEFAULT_ATTR_LEAF (PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D) +#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D) + +#define PAGE_IS_LEAF(pte) __MASKVALUE(pte,PAGE_ATTR_RWX) + +#define PTE_USED(pte) __MASKVALUE(pte,PTE_V) + +#define mmu_flush_tlb() do{asm volatile("sfence.vma x0,x0");}while(0) + +//compatible to rt-smart new version +#define MMU_MAP_K_DEVICE (PAGE_ATTR_RWX | PTE_V | PTE_G | PTE_SO | PTE_BUF | PTE_A | PTE_D) +#define MMU_MAP_K_RWCB (PAGE_ATTR_RWX | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D) +#define ARCH_PAGE_SIZE PAGE_SIZE +#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1) +#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT + +void mmu_set_pagetable(rt_ubase_t addr); +void mmu_enable_user_page_access(); +void mmu_disable_user_page_access(); + +#endif diff --git a/libcpu/risc-v/t-head/c906/rt_interrupt.h b/libcpu/risc-v/t-head/c906/rt_interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..c55a7fc0bddf137576772d9ceb526940d2e3b047 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/rt_interrupt.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-19 JasonHu first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include + +#define NR_CPUS 1 + +#define IRQ_OFFSET 16 +#define IRQ_MAX_NR 207 +#define INTERRUPTS_MAX (IRQ_OFFSET + IRQ_MAX_NR) + +enum { + EP_INSTRUCTION_ADDRESS_MISALIGNED = 0, + EP_INSTRUCTION_ACCESS_FAULT, + EP_ILLEGAL_INSTRUCTION, + EP_BREAKPOINT, + EP_LOAD_ADDRESS_MISALIGNED, + EP_LOAD_ACCESS_FAULT, + EP_STORE_ADDRESS_MISALIGNED, + EP_STORE_ACCESS_FAULT, + EP_ENVIRONMENT_CALL_U_MODE, + EP_ENVIRONMENT_CALL_S_MODE, + EP_RESERVED10, + EP_ENVIRONMENT_CALL_M_MODE, + EP_INSTRUCTION_PAGE_FAULT, /* page attr */ + EP_LOAD_PAGE_FAULT, /* read data */ + EP_RESERVED14, + EP_STORE_PAGE_FAULT, /* write data */ +}; + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); + +void generic_handle_irq(int irq); + +#endif diff --git a/libcpu/risc-v/t-head/c906/sbi.c b/libcpu/risc-v/t-head/c906/sbi.c new file mode 100644 index 0000000000000000000000000000000000000000..f848ec781032a5d71031c0bd8e10da6be6fa46a6 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/sbi.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 Bernard port from FreeBSD + */ + +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2019 Mitchell Horne + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "sbi.h" +#include +#include + +/* SBI Implementation-Specific Definitions */ +#define OPENSBI_VERSION_MAJOR_OFFSET 16 +#define OPENSBI_VERSION_MINOR_MASK 0xFFFF + +unsigned long sbi_spec_version; +unsigned long sbi_impl_id; +unsigned long sbi_impl_version; + +static bool has_time_extension = false; +static bool has_ipi_extension = false; +static bool has_rfnc_extension = false; + +static struct sbi_ret +sbi_get_spec_version(void) +{ + return (SBI_CALL0(SBI_EXT_ID_BASE, SBI_BASE_GET_SPEC_VERSION)); +} + +static struct sbi_ret +sbi_get_impl_id(void) +{ + return (SBI_CALL0(SBI_EXT_ID_BASE, SBI_BASE_GET_IMPL_ID)); +} + +static struct sbi_ret +sbi_get_impl_version(void) +{ + return (SBI_CALL0(SBI_EXT_ID_BASE, SBI_BASE_GET_IMPL_VERSION)); +} + +void +sbi_print_version(void) +{ + u_int major; + u_int minor; + + /* For legacy SBI implementations. */ + if (sbi_spec_version == 0) + { + rt_kprintf("SBI: Unknown (Legacy) Implementation\n"); + rt_kprintf("SBI Specification Version: 0.1\n"); + return; + } + + switch (sbi_impl_id) + { + case (SBI_IMPL_ID_BBL): + rt_kprintf("SBI: Berkely Boot Loader %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_XVISOR): + rt_kprintf("SBI: eXtensible Versatile hypervISOR %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_KVM): + rt_kprintf("SBI: Kernel-based Virtual Machine %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_RUSTSBI): + rt_kprintf("SBI: RustSBI %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_DIOSIX): + rt_kprintf("SBI: Diosix %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_OPENSBI): + major = sbi_impl_version >> OPENSBI_VERSION_MAJOR_OFFSET; + minor = sbi_impl_version & OPENSBI_VERSION_MINOR_MASK; + rt_kprintf("SBI: OpenSBI v%u.%u\n", major, minor); + break; + default: + rt_kprintf("SBI: Unrecognized Implementation: %lu\n", sbi_impl_id); + break; + } + + major = (sbi_spec_version & SBI_SPEC_VERS_MAJOR_MASK) >> + SBI_SPEC_VERS_MAJOR_OFFSET; + minor = (sbi_spec_version & SBI_SPEC_VERS_MINOR_MASK); + rt_kprintf("SBI Specification Version: %u.%u\n", major, minor); +} + +void +sbi_set_timer(uint64_t val) +{ + struct sbi_ret ret; + + /* Use the TIME legacy replacement extension, if available. */ + if (has_time_extension) + { + ret = SBI_CALL1(SBI_EXT_ID_TIME, SBI_TIME_SET_TIMER, val); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL1(SBI_SET_TIMER, 0, val); + } +} + +void +sbi_send_ipi(const unsigned long *hart_mask) +{ + struct sbi_ret ret; + + /* Use the IPI legacy replacement extension, if available. */ + if (has_ipi_extension) + { + ret = SBI_CALL2(SBI_EXT_ID_IPI, SBI_IPI_SEND_IPI, + *hart_mask, 0); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL1(SBI_SEND_IPI, 0, (uint64_t)hart_mask); + } +} + +void +sbi_remote_fence_i(const unsigned long *hart_mask) +{ + struct sbi_ret ret; + + /* Use the RFENCE legacy replacement extension, if available. */ + if (has_rfnc_extension) + { + ret = SBI_CALL2(SBI_EXT_ID_RFNC, SBI_RFNC_REMOTE_FENCE_I, + *hart_mask, 0); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL1(SBI_REMOTE_FENCE_I, 0, (uint64_t)hart_mask); + } +} + +void +sbi_remote_sfence_vma(const unsigned long *hart_mask, unsigned long start, unsigned long size) +{ + struct sbi_ret ret; + + /* Use the RFENCE legacy replacement extension, if available. */ + if (has_rfnc_extension) + { + ret = SBI_CALL4(SBI_EXT_ID_RFNC, SBI_RFNC_REMOTE_SFENCE_VMA, + *hart_mask, 0, start, size); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL3(SBI_REMOTE_SFENCE_VMA, 0, (uint64_t)hart_mask, + start, size); + } +} + +void +sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long start, unsigned long size, + unsigned long asid) +{ + struct sbi_ret ret; + + /* Use the RFENCE legacy replacement extension, if available. */ + if (has_rfnc_extension) + { + ret = SBI_CALL5(SBI_EXT_ID_RFNC, SBI_RFNC_REMOTE_SFENCE_VMA_ASID, + *hart_mask, 0, start, size, asid); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL4(SBI_REMOTE_SFENCE_VMA_ASID, 0, + (uint64_t)hart_mask, start, size, asid); + } +} + +int +sbi_hsm_hart_start(unsigned long hart, unsigned long start_addr, unsigned long priv) +{ + struct sbi_ret ret; + + ret = SBI_CALL3(SBI_EXT_ID_HSM, SBI_HSM_HART_START, hart, start_addr, priv); + return (ret.error != 0 ? (int)ret.error : 0); +} + +void +sbi_hsm_hart_stop(void) +{ + (void)SBI_CALL0(SBI_EXT_ID_HSM, SBI_HSM_HART_STOP); +} + +int +sbi_hsm_hart_status(unsigned long hart) +{ + struct sbi_ret ret; + + ret = SBI_CALL1(SBI_EXT_ID_HSM, SBI_HSM_HART_STATUS, hart); + + return (ret.error != 0 ? (int)ret.error : (int)ret.value); +} + +void +sbi_init(void) +{ + struct sbi_ret sret; + + /* + * Get the spec version. For legacy SBI implementations this will + * return an error, otherwise it is guaranteed to succeed. + */ + sret = sbi_get_spec_version(); + if (sret.error != 0) + { + /* We are running a legacy SBI implementation. */ + sbi_spec_version = 0; + return; + } + + /* Set the SBI implementation info. */ + sbi_spec_version = sret.value; + sbi_impl_id = sbi_get_impl_id().value; + sbi_impl_version = sbi_get_impl_version().value; + + /* Probe for legacy replacement extensions. */ + if (sbi_probe_extension(SBI_EXT_ID_TIME) != 0) + has_time_extension = true; + if (sbi_probe_extension(SBI_EXT_ID_IPI) != 0) + has_ipi_extension = true; + if (sbi_probe_extension(SBI_EXT_ID_RFNC) != 0) + has_rfnc_extension = true; +} diff --git a/libcpu/risc-v/t-head/c906/sbi.h b/libcpu/risc-v/t-head/c906/sbi.h new file mode 100644 index 0000000000000000000000000000000000000000..0e95ede3343eec9aa9ba7ed0b92797b0978631c2 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/sbi.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 Bernard port from FreeBSD + */ + +/*- + * Copyright (c) 2016-2017 Ruslan Bukin + * All rights reserved. + * Copyright (c) 2019 Mitchell Horne + * + * Portions of this software were developed by SRI International and the + * University of Cambridge Computer Laboratory under DARPA/AFRL contract + * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Portions of this software were developed by the University of Cambridge + * Computer Laboratory as part of the CTSRD Project, with support from the + * UK Higher Education Innovation Fund (HEIF). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_SBI_H_ +#define _MACHINE_SBI_H_ + +#include + +/* SBI Specification Version */ +#define SBI_SPEC_VERS_MAJOR_OFFSET 24 +#define SBI_SPEC_VERS_MAJOR_MASK (0x7F << SBI_SPEC_VERS_MAJOR_OFFSET) +#define SBI_SPEC_VERS_MINOR_OFFSET 0 +#define SBI_SPEC_VERS_MINOR_MASK (0xFFFFFF << SBI_SPEC_VERS_MINOR_OFFSET) + +/* SBI Implementation IDs */ +#define SBI_IMPL_ID_BBL 0 +#define SBI_IMPL_ID_OPENSBI 1 +#define SBI_IMPL_ID_XVISOR 2 +#define SBI_IMPL_ID_KVM 3 +#define SBI_IMPL_ID_RUSTSBI 4 +#define SBI_IMPL_ID_DIOSIX 5 + +/* SBI Error Codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILURE -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 + +/* SBI Base Extension */ +#define SBI_EXT_ID_BASE 0x10 +#define SBI_BASE_GET_SPEC_VERSION 0 +#define SBI_BASE_GET_IMPL_ID 1 +#define SBI_BASE_GET_IMPL_VERSION 2 +#define SBI_BASE_PROBE_EXTENSION 3 +#define SBI_BASE_GET_MVENDORID 4 +#define SBI_BASE_GET_MARCHID 5 +#define SBI_BASE_GET_MIMPID 6 + +/* Timer (TIME) Extension */ +#define SBI_EXT_ID_TIME 0x54494D45 +#define SBI_TIME_SET_TIMER 0 + +/* IPI (IPI) Extension */ +#define SBI_EXT_ID_IPI 0x735049 +#define SBI_IPI_SEND_IPI 0 + +/* RFENCE (RFNC) Extension */ +#define SBI_EXT_ID_RFNC 0x52464E43 +#define SBI_RFNC_REMOTE_FENCE_I 0 +#define SBI_RFNC_REMOTE_SFENCE_VMA 1 +#define SBI_RFNC_REMOTE_SFENCE_VMA_ASID 2 +#define SBI_RFNC_REMOTE_HFENCE_GVMA_VMID 3 +#define SBI_RFNC_REMOTE_HFENCE_GVMA 4 +#define SBI_RFNC_REMOTE_HFENCE_VVMA_ASID 5 +#define SBI_RFNC_REMOTE_HFENCE_VVMA 6 + +/* Hart State Management (HSM) Extension */ +#define SBI_EXT_ID_HSM 0x48534D +#define SBI_HSM_HART_START 0 +#define SBI_HSM_HART_STOP 1 +#define SBI_HSM_HART_STATUS 2 +#define SBI_HSM_STATUS_STARTED 0 +#define SBI_HSM_STATUS_STOPPED 1 +#define SBI_HSM_STATUS_START_PENDING 2 +#define SBI_HSM_STATUS_STOP_PENDING 3 + +/* Legacy Extensions */ +#define SBI_SET_TIMER 0 +#define SBI_CONSOLE_PUTCHAR 1 +#define SBI_CONSOLE_GETCHAR 2 +#define SBI_CLEAR_IPI 3 +#define SBI_SEND_IPI 4 +#define SBI_REMOTE_FENCE_I 5 +#define SBI_REMOTE_SFENCE_VMA 6 +#define SBI_REMOTE_SFENCE_VMA_ASID 7 +#define SBI_SHUTDOWN 8 + +#define SBI_CALL0(e, f) SBI_CALL5(e, f, 0, 0, 0, 0, 0) +#define SBI_CALL1(e, f, p1) SBI_CALL5(e, f, p1, 0, 0, 0, 0) +#define SBI_CALL2(e, f, p1, p2) SBI_CALL5(e, f, p1, p2, 0, 0, 0) +#define SBI_CALL3(e, f, p1, p2, p3) SBI_CALL5(e, f, p1, p2, p3, 0, 0) +#define SBI_CALL4(e, f, p1, p2, p3, p4) SBI_CALL5(e, f, p1, p2, p3, p4, 0) +#define SBI_CALL5(e, f, p1, p2, p3, p4, p5) sbi_call(e, f, p1, p2, p3, p4, p5) + +/* + * Documentation available at + * https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc + */ + +struct sbi_ret +{ + long error; + long value; +}; + +static __inline struct sbi_ret +sbi_call(uint64_t arg7, uint64_t arg6, uint64_t arg0, uint64_t arg1, + uint64_t arg2, uint64_t arg3, uint64_t arg4) +{ + struct sbi_ret ret; + + register uintptr_t a0 __asm("a0") = (uintptr_t)(arg0); + register uintptr_t a1 __asm("a1") = (uintptr_t)(arg1); + register uintptr_t a2 __asm("a2") = (uintptr_t)(arg2); + register uintptr_t a3 __asm("a3") = (uintptr_t)(arg3); + register uintptr_t a4 __asm("a4") = (uintptr_t)(arg4); + register uintptr_t a6 __asm("a6") = (uintptr_t)(arg6); + register uintptr_t a7 __asm("a7") = (uintptr_t)(arg7); + + __asm __volatile(\ + "ecall" \ + : "+r"(a0), "+r"(a1) \ + : "r"(a2), "r"(a3), "r"(a4), "r"(a6), "r"(a7) \ + : "memory"); + + ret.error = a0; + ret.value = a1; + return (ret); +} + +/* Base extension functions and variables. */ +extern unsigned long sbi_spec_version; +extern unsigned long sbi_impl_id; +extern unsigned long sbi_impl_version; + +static __inline long +sbi_probe_extension(long id) +{ + return (SBI_CALL1(SBI_EXT_ID_BASE, SBI_BASE_PROBE_EXTENSION, id).value); +} + +/* TIME extension functions. */ +void sbi_set_timer(uint64_t val); + +/* IPI extension functions. */ +void sbi_send_ipi(const unsigned long *hart_mask); + +/* RFENCE extension functions. */ +void sbi_remote_fence_i(const unsigned long *hart_mask); +void sbi_remote_sfence_vma(const unsigned long *hart_mask, unsigned long start, unsigned long size); +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long start, + unsigned long size, unsigned long asid); + +/* Hart State Management extension functions. */ + +/* + * Start execution on the specified hart at physical address start_addr. The + * register a0 will contain the hart's ID, and a1 will contain the value of + * priv. + */ +int sbi_hsm_hart_start(unsigned long hart, unsigned long start_addr, unsigned long priv); + +/* + * Stop execution on the current hart. Interrupts should be disabled, or this + * function may return. + */ +void sbi_hsm_hart_stop(void); + +/* + * Get the execution status of the specified hart. The status will be one of: + * - SBI_HSM_STATUS_STARTED + * - SBI_HSM_STATUS_STOPPED + * - SBI_HSM_STATUS_START_PENDING + * - SBI_HSM_STATUS_STOP_PENDING + */ +int sbi_hsm_hart_status(unsigned long hart); + +/* Legacy extension functions. */ +static __inline void +sbi_console_putchar(int ch) +{ + (void)SBI_CALL1(SBI_CONSOLE_PUTCHAR, 0, ch); +} + +static __inline int +sbi_console_getchar(void) +{ + /* + * XXX: The "error" is returned here because legacy SBI functions + * continue to return their value in a0. + */ + return (SBI_CALL0(SBI_CONSOLE_GETCHAR, 0).error); +} + +static __inline void +sbi_shutdown(void) +{ + (void)SBI_CALL0(SBI_SHUTDOWN, 0); +} + +void sbi_print_version(void); +void sbi_init(void); + +#endif /* !_MACHINE_SBI_H_ */ diff --git a/libcpu/risc-v/t-head/c906/stack.h b/libcpu/risc-v/t-head/c906/stack.h new file mode 100644 index 0000000000000000000000000000000000000000..1ac507efbaea764ae3ff5613ea10587e48acd838 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/stack.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + * 2021-11-18 JasonHu add fpu member + */ + +#ifndef __STACK_H__ +#define __STACK_H__ + +#include +struct rt_hw_stack_frame +{ + rt_ubase_t epc; /* epc - epc - program counter */ + rt_ubase_t ra; /* x1 - ra - return address for jumps */ + rt_ubase_t sstatus; /* - supervisor status register */ + rt_ubase_t gp; /* x3 - gp - global pointer */ + rt_ubase_t tp; /* x4 - tp - thread pointer */ + rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /* x9 - s1 - saved register 1 */ + rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /* x12 - a2 - function argument 2 */ + rt_ubase_t a3; /* x13 - a3 - function argument 3 */ + rt_ubase_t a4; /* x14 - a4 - function argument 4 */ + rt_ubase_t a5; /* x15 - a5 - function argument 5 */ + rt_ubase_t a6; /* x16 - a6 - function argument 6 */ + rt_ubase_t a7; /* x17 - s7 - function argument 7 */ + rt_ubase_t s2; /* x18 - s2 - saved register 2 */ + rt_ubase_t s3; /* x19 - s3 - saved register 3 */ + rt_ubase_t s4; /* x20 - s4 - saved register 4 */ + rt_ubase_t s5; /* x21 - s5 - saved register 5 */ + rt_ubase_t s6; /* x22 - s6 - saved register 6 */ + rt_ubase_t s7; /* x23 - s7 - saved register 7 */ + rt_ubase_t s8; /* x24 - s8 - saved register 8 */ + rt_ubase_t s9; /* x25 - s9 - saved register 9 */ + rt_ubase_t s10; /* x26 - s10 - saved register 10 */ + rt_ubase_t s11; /* x27 - s11 - saved register 11 */ + rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ + rt_ubase_t user_sp_exc_stack; /* sscratch - user mode sp/exception stack */ +#ifdef ENABLE_FPU + rt_ubase_t f[CTX_FPU_REG_NR]; /* f0~f31 */ +#endif +}; + +#endif diff --git a/libcpu/risc-v/t-head/c906/stackframe.h b/libcpu/risc-v/t-head/c906/stackframe.h new file mode 100644 index 0000000000000000000000000000000000000000..1e191900b4a262e7aefb08611fd7e5ed832fb310 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/stackframe.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-02 lizhirui first version + * 2021-02-11 lizhirui fixed gp save/store bug + * 2021-11-18 JasonHu add fpu registers save/restore + */ + +#ifndef __STACKFRAME_H__ +#define __STACKFRAME_H__ + +#include "cpuport.h" +#include "encoding.h" + +#ifdef ENABLE_FPU +#define FPU_CTX_F0_OFF 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F1_OFF 8 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F2_OFF 16 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F3_OFF 24 /* offsetof(fpu_context_t, fpustatus.f[3]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F4_OFF 32 /* offsetof(fpu_context_t, fpustatus.f[4]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F5_OFF 40 /* offsetof(fpu_context_t, fpustatus.f[5]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F6_OFF 48 /* offsetof(fpu_context_t, fpustatus.f[6]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F7_OFF 56 /* offsetof(fpu_context_t, fpustatus.f[7]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F8_OFF 64 /* offsetof(fpu_context_t, fpustatus.f[8]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F9_OFF 72 /* offsetof(fpu_context_t, fpustatus.f[9]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F10_OFF 80 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F11_OFF 88 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F12_OFF 96 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F13_OFF 104 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F14_OFF 112 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F15_OFF 120 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F16_OFF 128 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F17_OFF 136 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F18_OFF 144 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F19_OFF 152 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F20_OFF 160 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F21_OFF 168 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F22_OFF 176 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F23_OFF 184 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F24_OFF 192 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F25_OFF 200 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F26_OFF 208 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F27_OFF 216 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F28_OFF 224 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F29_OFF 232 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F30_OFF 240 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F31_OFF 248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#endif /* ENABLE_FPU */ + +/** + * The register `tp` always save/restore when context switch, + * we call `lwp_user_setting_save` when syscall enter, + * call `lwp_user_setting_restore` when syscall exit + * and modify context stack after `lwp_user_setting_restore` called + * so that the `tp` can be the correct thread area value. + */ + +.macro SAVE_ALL + +#ifdef ENABLE_FPU + /* reserve float registers */ + addi sp, sp, -CTX_FPU_REG_NR * REGBYTES +#endif /* ENABLE_FPU */ + + /* save general registers */ + addi sp, sp, -CTX_GENERAL_REG_NR * REGBYTES + STORE x1, 1 * REGBYTES(sp) + + csrr x1, sstatus + STORE x1, 2 * REGBYTES(sp) + + csrr x1, sepc + STORE x1, 0 * REGBYTES(sp) + + STORE x3, 3 * REGBYTES(sp) + STORE x4, 4 * REGBYTES(sp) /* save tp */ + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + csrr t0, sscratch + STORE t0, 32 * REGBYTES(sp) + +#ifdef ENABLE_FPU + /* backup sp and adjust sp to save float registers */ + mv t1, sp + addi t1, t1, CTX_GENERAL_REG_NR * REGBYTES + + li t0, SSTATUS_FS + csrs sstatus, t0 + fsd f0, FPU_CTX_F0_OFF(t1) + fsd f1, FPU_CTX_F1_OFF(t1) + fsd f2, FPU_CTX_F2_OFF(t1) + fsd f3, FPU_CTX_F3_OFF(t1) + fsd f4, FPU_CTX_F4_OFF(t1) + fsd f5, FPU_CTX_F5_OFF(t1) + fsd f6, FPU_CTX_F6_OFF(t1) + fsd f7, FPU_CTX_F7_OFF(t1) + fsd f8, FPU_CTX_F8_OFF(t1) + fsd f9, FPU_CTX_F9_OFF(t1) + fsd f10, FPU_CTX_F10_OFF(t1) + fsd f11, FPU_CTX_F11_OFF(t1) + fsd f12, FPU_CTX_F12_OFF(t1) + fsd f13, FPU_CTX_F13_OFF(t1) + fsd f14, FPU_CTX_F14_OFF(t1) + fsd f15, FPU_CTX_F15_OFF(t1) + fsd f16, FPU_CTX_F16_OFF(t1) + fsd f17, FPU_CTX_F17_OFF(t1) + fsd f18, FPU_CTX_F18_OFF(t1) + fsd f19, FPU_CTX_F19_OFF(t1) + fsd f20, FPU_CTX_F20_OFF(t1) + fsd f21, FPU_CTX_F21_OFF(t1) + fsd f22, FPU_CTX_F22_OFF(t1) + fsd f23, FPU_CTX_F23_OFF(t1) + fsd f24, FPU_CTX_F24_OFF(t1) + fsd f25, FPU_CTX_F25_OFF(t1) + fsd f26, FPU_CTX_F26_OFF(t1) + fsd f27, FPU_CTX_F27_OFF(t1) + fsd f28, FPU_CTX_F28_OFF(t1) + fsd f29, FPU_CTX_F29_OFF(t1) + fsd f30, FPU_CTX_F30_OFF(t1) + fsd f31, FPU_CTX_F31_OFF(t1) + + /* clr FS domain */ + csrc sstatus, t0 + + /* clean status would clr sr_sd; */ + li t0, SSTATUS_FS_CLEAN + csrs sstatus, t0 + +#endif /* ENABLE_FPU */ + +.endm + +.macro RESTORE_ALL + +#ifdef ENABLE_FPU + /* restore float register */ + mv t2, sp + addi t2, t2, CTX_GENERAL_REG_NR * REGBYTES /* skip all normal reg */ + + li t0, SSTATUS_FS + csrs sstatus, t0 + fld f0, FPU_CTX_F0_OFF(t2) + fld f1, FPU_CTX_F1_OFF(t2) + fld f2, FPU_CTX_F2_OFF(t2) + fld f3, FPU_CTX_F3_OFF(t2) + fld f4, FPU_CTX_F4_OFF(t2) + fld f5, FPU_CTX_F5_OFF(t2) + fld f6, FPU_CTX_F6_OFF(t2) + fld f7, FPU_CTX_F7_OFF(t2) + fld f8, FPU_CTX_F8_OFF(t2) + fld f9, FPU_CTX_F9_OFF(t2) + fld f10, FPU_CTX_F10_OFF(t2) + fld f11, FPU_CTX_F11_OFF(t2) + fld f12, FPU_CTX_F12_OFF(t2) + fld f13, FPU_CTX_F13_OFF(t2) + fld f14, FPU_CTX_F14_OFF(t2) + fld f15, FPU_CTX_F15_OFF(t2) + fld f16, FPU_CTX_F16_OFF(t2) + fld f17, FPU_CTX_F17_OFF(t2) + fld f18, FPU_CTX_F18_OFF(t2) + fld f19, FPU_CTX_F19_OFF(t2) + fld f20, FPU_CTX_F20_OFF(t2) + fld f21, FPU_CTX_F21_OFF(t2) + fld f22, FPU_CTX_F22_OFF(t2) + fld f23, FPU_CTX_F23_OFF(t2) + fld f24, FPU_CTX_F24_OFF(t2) + fld f25, FPU_CTX_F25_OFF(t2) + fld f26, FPU_CTX_F26_OFF(t2) + fld f27, FPU_CTX_F27_OFF(t2) + fld f28, FPU_CTX_F28_OFF(t2) + fld f29, FPU_CTX_F29_OFF(t2) + fld f30, FPU_CTX_F30_OFF(t2) + fld f31, FPU_CTX_F31_OFF(t2) + + /* clr FS domain */ + csrc sstatus, t0 + + /* clean status would clr sr_sd; */ + li t0, SSTATUS_FS_CLEAN + csrs sstatus, t0 + +#endif /* ENABLE_FPU */ + + /* restore general register */ + + /* resw ra to sepc */ + LOAD x1, 0 * REGBYTES(sp) + csrw sepc, x1 + + LOAD x1, 2 * REGBYTES(sp) + csrw sstatus, x1 + + LOAD x1, 1 * REGBYTES(sp) + + LOAD x3, 3 * REGBYTES(sp) + LOAD x4, 4 * REGBYTES(sp) /* restore tp */ + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + /* restore user sp */ + LOAD sp, 32 * REGBYTES(sp) +.endm + +.macro RESTORE_SYS_GP + .option push + .option norelax + la gp, __global_pointer$ + .option pop +.endm + +.macro OPEN_INTERRUPT + csrsi sstatus, 2 +.endm + +.macro CLOSE_INTERRUPT + csrci sstatus, 2 +.endm + +#endif diff --git a/libcpu/risc-v/t-head/c906/startup_gcc.S b/libcpu/risc-v/t-head/c906/startup_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..3760b857b3da3af6c5849f0549133528f2bcb15d --- /dev/null +++ b/libcpu/risc-v/t-head/c906/startup_gcc.S @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/01 Bernard The first version + * 2018/12/27 Jesven Add SMP support + * 2020/6/12 Xim Port to QEMU and remove SMP support + */ + +#define __ASSEMBLY__ +#define SSTATUS_FS 0x00006000U /* initial state of FPU, clear to disable */ +#include + + .global _start + .section ".start", "ax" +_start: + j 1f + .word 0xdeadbeef + .align 3 + .global g_wake_up + g_wake_up: + .dword 1 + .dword 0 +1: + csrw sie, 0 + csrw sip, 0 + la t0, trap_entry + csrw stvec, t0 + + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10,0 + li x11,0 + li x12,0 + li x13,0 + li x14,0 + li x15,0 + li x16,0 + li x17,0 + li x18,0 + li x19,0 + li x20,0 + li x21,0 + li x22,0 + li x23,0 + li x24,0 + li x25,0 + li x26,0 + li x27,0 + li x28,0 + li x29,0 + li x30,0 + li x31,0 + + /* set to disable FPU */ + li t0, SSTATUS_FS + csrc sstatus, t0 + li t0, 0x40000 // SUM in sstatus + csrs sstatus, t0 + +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + // removed SMP support here + la sp, __stack_start__ + li t0, __STACKSIZE__ + add sp, sp, t0 + csrw sscratch, sp + j primary_cpu_entry diff --git a/libcpu/risc-v/t-head/c906/symbol_analysis.c b/libcpu/risc-v/t-head/c906/symbol_analysis.c new file mode 100644 index 0000000000000000000000000000000000000000..83edacb1c43f773197f11e78317140890fae4d7f --- /dev/null +++ b/libcpu/risc-v/t-head/c906/symbol_analysis.c @@ -0,0 +1,298 @@ +/* + * Copyright lizhirui + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 lizhirui the first version + * 2021-05-20 lizhirui add os debug support + */ + +#include +#include "symbol_analysis.h" + +#define MEMORY_BASE 0x40000000 +#define MEMORY_SIZE (128 * 0x100000) + +extern rt_size_t _osdebug_start; + +static os_symtab_header *symtab_header = (os_symtab_header *)&_osdebug_start; + +//该函数用于在指定的表中查找某个地址对应的符号的描述结构体指针，返回值的符号遵循规则详见文档 +os_symtab_item *find_symbol_table(rt_size_t symbol_table_addr,rt_size_t symbol_num,rt_size_t address) +{ + rt_size_t left = 0; + rt_size_t right = symbol_num; + os_symtab_item *sym_table = (os_symtab_item *)((rt_size_t)&_osdebug_start + symbol_table_addr); + + while(left < right) + { + rt_size_t mid = (left + right) >> 1; + //rt_kprintf("left = %d,right = %d,mid = %d\n",left,right,mid); + + if(address < sym_table[mid].address) + { + right = mid; + + while((right < symbol_num) && ((right - 1) >= 0) && (sym_table[right].address == sym_table[right - 1].address)) + { + right--; + } + } + else if(address == sym_table[mid].address) + { + left = mid + 1; + break; + } + else + { + left = mid; + + while((left >= 0) && ((left + 1) < symbol_num) && (sym_table[left].address == sym_table[left + 1].address)) + { + left++; + } + + left++; + } + } + + left--; + + if(left == ((rt_size_t)-1)) + { + return RT_NULL; + } + + while((left < symbol_num) && ((left - 1) >= 0) && (sym_table[left].address == sym_table[left - 1].address)) + { + left--; + } + + return &sym_table[left]; +} + +//该函数用于根据给定的符号指针从字符串表中找到对应的符号名指针并返回 +const char *get_symbol_name(os_symtab_item *symbol) +{ + return (const char *)((rt_size_t)&_osdebug_start + symtab_header -> string_table_offset + symbol -> name_offset); +} + +//该函数可以根据给定的符号和地址向中断打印出标准格式的符号信息 +void print_symbol(os_symtab_item *symbol,rt_size_t address) +{ + rt_kprintf("<%s(0x%p)",get_symbol_name(symbol),symbol -> address); + + if(symbol -> size) + { + rt_kprintf(" : 0x%x>",symbol -> size); + } + else + { + rt_kprintf(">"); + } + + if(address > symbol -> address) + { + rt_kprintf(" + 0x%x",address - symbol -> address); + } +} + +//该函数用于打印出一个地址关联的全部符号信息 +void print_symbol_info(rt_size_t address,rt_bool_t function) +{ + os_symtab_item *function_symbol = find_symbol_table(symtab_header -> function_table_offset,symtab_header -> function_table_num,address); + os_symtab_item *object_symbol = find_symbol_table(symtab_header -> object_table_offset,symtab_header -> object_table_num,address); + os_symtab_item *general_symbol = find_symbol_table(symtab_header -> general_symbol_table_offset,symtab_header -> general_symbol_table_num,address); + const char *dot = ""; + rt_bool_t valid = RT_FALSE; + + if(function) + { + while(function_symbol != RT_NULL) + { + if((function_symbol -> address + function_symbol -> size) > address) + { + rt_kprintf(dot); + print_symbol(function_symbol,address); + dot = ","; + valid = RT_TRUE; + } + + if(((rt_size_t)(function_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> function_table_offset + symtab_header -> function_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(function_symbol[0].address == function_symbol[1].address) + { + function_symbol++; + } + + break; + } + + if(!valid) + { + while(general_symbol != RT_NULL) + { + rt_kprintf(dot); + print_symbol(general_symbol,address); + dot = ","; + valid = RT_TRUE; + + if(((rt_size_t)(general_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> general_symbol_table_offset + symtab_header -> general_symbol_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(general_symbol[0].address == general_symbol[1].address) + { + general_symbol++; + } + + break; + } + + while(object_symbol != RT_NULL) + { + if((object_symbol -> address + object_symbol -> size) > address) + { + rt_kprintf(dot); + print_symbol(object_symbol,address); + dot = ","; + valid = RT_TRUE; + } + + if(((rt_size_t)(object_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> object_table_offset + symtab_header -> object_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(object_symbol[0].address == object_symbol[1].address) + { + object_symbol++; + } + + break; + } + } + } + else + { + while(object_symbol != RT_NULL) + { + if((object_symbol -> address + object_symbol -> size) > address) + { + rt_kprintf(dot); + print_symbol(object_symbol,address); + dot = ","; + valid = RT_TRUE; + } + + if(((rt_size_t)(object_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> object_table_offset + symtab_header -> object_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(object_symbol[0].address == object_symbol[1].address) + { + object_symbol++; + } + + break; + } + + if(!valid) + { + while(general_symbol != RT_NULL) + { + rt_kprintf(dot); + print_symbol(general_symbol,address); + dot = ","; + valid = RT_TRUE; + + if(((rt_size_t)(general_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> general_symbol_table_offset + symtab_header -> general_symbol_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(general_symbol[0].address == general_symbol[1].address) + { + general_symbol++; + } + + break; + } + + while(function_symbol != RT_NULL) + { + if((function_symbol -> address + function_symbol -> size) > address) + { + rt_kprintf(dot); + print_symbol(function_symbol,address); + dot = ","; + valid = RT_TRUE; + } + + if(((rt_size_t)(function_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> function_table_offset + symtab_header -> function_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(function_symbol[0].address == function_symbol[1].address) + { + function_symbol++; + } + + break; + } + } + } + + if(dot == "") + { + rt_kprintf(""); + } +} + +//该函数用于在出错时打印出栈跟踪信息 +void print_stacktrace(rt_size_t epc,rt_size_t fp) +{ + rt_kprintf("-----------------------------Dump Stacktrace----------------------------\n\n"); + rt_size_t sp = fp; + rt_size_t i = 0; + + rt_kprintf("address 0x%p(",epc); + print_symbol_info(epc,RT_TRUE); + rt_kprintf(")\n\n"); + + while(1) + { + if((sp >= MEMORY_BASE) && (sp < (MEMORY_BASE + MEMORY_SIZE))) + { + //rt_kprintf("%d: 0x%p\n",i,sp); + rt_size_t *stack = (rt_size_t *)(sp - sizeof(rt_size_t) * 2); + rt_size_t ra = stack[1]; + + if(!ra) + { + break; + } + + rt_kprintf("return to 0x%p(",ra); + print_symbol_info(ra,RT_TRUE); + rt_kprintf(")\n\n"); + //rt_kprintf("ra = 0x%p,fp = 0x%p\n",stack[1],stack[0]); + sp = stack[0]; + i++; + } + else + { + break; + } + } + + rt_kprintf("---------------------------------Dump OK--------------------------------\n"); +} diff --git a/libcpu/risc-v/t-head/c906/symbol_analysis.h b/libcpu/risc-v/t-head/c906/symbol_analysis.h new file mode 100644 index 0000000000000000000000000000000000000000..a9db46ffd39db4435c1e451353ede2ac56586e40 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/symbol_analysis.h @@ -0,0 +1,44 @@ +/* + * Copyright lizhirui + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 lizhirui the first version + * 2021-05-20 lizhirui add os debug support + */ + +#ifndef __SYMBOL_ANALYSIS_H__ +#define __SYMBOL_ANALYSIS_H__ + + #include + + //osdebug节区头描述结构体 + typedef struct os_symtab_header + { + rt_size_t function_table_offset;//函数表的偏移地址（相对于节区起始地址，下同） + rt_size_t function_table_num;//函数表中的符号数量 + rt_size_t object_table_offset;//对象表的偏移地址 + rt_size_t object_table_num;//对象表中的符号数量 + rt_size_t general_symbol_table_offset;//一般符号（指代类型虽为NONE但带有GLOBAL的符号）表的偏移地址 + rt_size_t general_symbol_table_num;//一般符号表中的符号数量 + rt_size_t string_table_offset;//字符串表的偏移地址 + rt_size_t string_table_size;//字符串表的大小（字节为单位） + }os_symtab_header; + + //符号描述结构体 + typedef struct os_symtab_item + { + rt_size_t name_offset;//符号名称在字符串表中的偏移地址 + rt_size_t address;//该符号所代表的地址 + rt_size_t size;//该符号所代表的大小 + }os_symtab_item; + + os_symtab_item *find_symbol_table(rt_size_t symbol_table_addr,rt_size_t symbol_num,rt_size_t address); + const char *get_symbol_name(os_symtab_item *symbol); + void print_symbol(os_symtab_item *symbol,rt_size_t address); + void print_symbol_info(rt_size_t address,rt_bool_t function); + void print_stacktrace(rt_size_t epc,rt_size_t fp); + +#endif diff --git a/libcpu/risc-v/t-head/c906/syscall_c.c b/libcpu/risc-v/t-head/c906/syscall_c.c new file mode 100644 index 0000000000000000000000000000000000000000..16c8369db1b6e8d6f4e533e2d67f75a0b9abdc98 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/syscall_c.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-03 lizhirui first version + */ + +#include +#include + +#define DBG_LEVEL DBG_WARNING +//#define DBG_LEVEL DBG_INFO +#include + +#include +#include +#include +#include +#include + +#include + +#include "riscv_mmu.h" +#include "stack.h" + +typedef rt_size_t (*syscallfunc_t)(rt_size_t,rt_size_t,rt_size_t,rt_size_t,rt_size_t,rt_size_t,rt_size_t); +syscallfunc_t lwp_get_sys_api(uint32_t); + +void syscall_handler(struct rt_hw_stack_frame *regs) +{ + if(regs -> a7 == 0) + { + rt_kprintf("syscall id = 0!\n"); + while(1); + } + + if(regs -> a7 == 0xdeadbeef) + { + rt_kprintf("syscall id = 0xdeadbeef\n"); + while(1); + } + + syscallfunc_t syscallfunc = (syscallfunc_t)lwp_get_sys_api(regs -> a7); + + if(syscallfunc == RT_NULL) + { + rt_kprintf("unsupported syscall!\n"); + while(1); + } + + LOG_I("\033[36msyscall id = %d,arg0 = 0x%p,arg1 = 0x%p,arg2 = 0x%p,arg3 = 0x%p,arg4 = 0x%p,arg5 = 0x%p,arg6 = 0x%p\n\033[37m",regs -> a7,regs -> a0,regs -> a1,regs -> a2,regs -> a3,regs -> a4,regs -> a5,regs -> a6); + regs -> a0 = syscallfunc(regs -> a0,regs -> a1,regs -> a2,regs -> a3,regs -> a4,regs -> a5,regs -> a6); + regs -> a7 = 0; + regs -> epc += 4;//skip ecall instruction + LOG_I("\033[36msyscall deal ok,ret = 0x%p\n\033[37m",regs -> a0); +} diff --git a/libcpu/risc-v/t-head/c906/tick.c b/libcpu/risc-v/t-head/c906/tick.c new file mode 100644 index 0000000000000000000000000000000000000000..0cb3c79be3a92c3dc4a868cecd858c7f4c055154 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/tick.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + */ + +#include +#include + +#include +#include "sbi.h" +#include "tick.h" + +static volatile uint64_t time_elapsed = 0; +static volatile unsigned long tick_cycles = 0; + +static unsigned long tick_delta = TIMER_CLK_FREQ / RT_TICK_PER_SECOND; + +static uint64_t get_ticks() +{ + __asm__ __volatile__( + "rdtime %0" + : "=r"(time_elapsed)); + return time_elapsed; +} + +int tick_isr(void) +{ + rt_tick_increase(); + sbi_set_timer(get_ticks() + tick_delta); + return 0; +} + +/* Sets and enable the timer interrupt */ +int rt_hw_tick_init(void) +{ + /* Clear the Supervisor-Timer bit in SIE */ + clear_csr(sie, SIP_STIP); + + /* Set timer */ + sbi_set_timer(get_ticks() + tick_delta); + + /* Enable the Supervisor-Timer bit in SIE */ + set_csr(sie, SIP_STIP); + + return 0; +} diff --git a/libcpu/risc-v/t-head/c906/tick.h b/libcpu/risc-v/t-head/c906/tick.h new file mode 100644 index 0000000000000000000000000000000000000000..18333ef6677776c35ca716395a952ca24adcedd1 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/tick.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + */ + +#ifndef TICK_H__ +#define TICK_H__ + +/* timer clock is 24 MHZ */ +#define TIMER_CLK_FREQ (24000000) + +int tick_isr(void); +int rt_hw_tick_init(void); + +#endif diff --git a/libcpu/risc-v/t-head/c906/trap.c b/libcpu/risc-v/t-head/c906/trap.c new file mode 100644 index 0000000000000000000000000000000000000000..831ea3b0a20059346130bfd4d1dbc9fc7210cb29 --- /dev/null +++ b/libcpu/risc-v/t-head/c906/trap.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021/1/30 lizirui first version + * 2021/10/20 JasonHu move to trap.c + */ + +#include +#include +#define DBG_LVL DBG_LOG +#include + +#include "board.h" +#include "tick.h" + +#include "drv_uart.h" +#include "encoding.h" +#include "stack.h" +#include "sbi.h" +#include "riscv.h" + +#include "rt_interrupt.h" +#include "plic.h" + +#ifdef RT_USING_USERSPACE + #include "riscv_mmu.h" + #include "mmu.h" + #include "page.h" + #include "lwp_arch.h" +#endif + +void dump_regs(struct rt_hw_stack_frame *regs) +{ + rt_kprintf("--------------Dump Registers-----------------\n"); + + rt_kprintf("Function Registers:\n"); + rt_kprintf("\tra(x1) = 0x%p(",regs->ra); + rt_kprintf(")\n"); + rt_kprintf("\tuser_sp(x2) = 0x%p(",regs->user_sp_exc_stack); + rt_kprintf(")\n"); + rt_kprintf("\tgp(x3) = 0x%p(",regs->gp); + rt_kprintf(")\n"); + rt_kprintf("\ttp(x4) = 0x%p(",regs->tp); + rt_kprintf(")\n"); + rt_kprintf("Temporary Registers:\n"); + rt_kprintf("\tt0(x5) = 0x%p(",regs->t0); + rt_kprintf(")\n"); + rt_kprintf("\tt1(x6) = 0x%p(",regs->t1); + rt_kprintf(")\n"); + rt_kprintf("\tt2(x7) = 0x%p(",regs->t2); + rt_kprintf(")\n"); + rt_kprintf("\tt3(x28) = 0x%p(",regs->t3); + rt_kprintf(")\n"); + rt_kprintf("\tt4(x29) = 0x%p(",regs->t4); + rt_kprintf(")\n"); + rt_kprintf("\tt5(x30) = 0x%p(",regs->t5); + rt_kprintf(")\n"); + rt_kprintf("\tt6(x31) = 0x%p(",regs->t6); + rt_kprintf(")\n"); + rt_kprintf("Saved Registers:\n"); + rt_kprintf("\ts0/fp(x8) = 0x%p(",regs->s0_fp); + rt_kprintf(")\n"); + rt_kprintf("\ts1(x9) = 0x%p(",regs->s1); + rt_kprintf(")\n"); + rt_kprintf("\ts2(x18) = 0x%p(",regs->s2); + rt_kprintf(")\n"); + rt_kprintf("\ts3(x19) = 0x%p(",regs->s3); + rt_kprintf(")\n"); + rt_kprintf("\ts4(x20) = 0x%p(",regs->s4); + rt_kprintf(")\n"); + rt_kprintf("\ts5(x21) = 0x%p(",regs->s5); + rt_kprintf(")\n"); + rt_kprintf("\ts6(x22) = 0x%p(",regs->s6); + rt_kprintf(")\n"); + rt_kprintf("\ts7(x23) = 0x%p(",regs->s7); + rt_kprintf(")\n"); + rt_kprintf("\ts8(x24) = 0x%p(",regs->s8); + rt_kprintf(")\n"); + rt_kprintf("\ts9(x25) = 0x%p(",regs->s9); + rt_kprintf(")\n"); + rt_kprintf("\ts10(x26) = 0x%p(",regs->s10); + rt_kprintf(")\n"); + rt_kprintf("\ts11(x27) = 0x%p(",regs->s11); + rt_kprintf(")\n"); + rt_kprintf("Function Arguments Registers:\n"); + rt_kprintf("\ta0(x10) = 0x%p(",regs->a0); + rt_kprintf(")\n"); + rt_kprintf("\ta1(x11) = 0x%p(",regs->a1); + rt_kprintf(")\n"); + rt_kprintf("\ta2(x12) = 0x%p(",regs->a2); + rt_kprintf(")\n"); + rt_kprintf("\ta3(x13) = 0x%p(",regs->a3); + rt_kprintf(")\n"); + rt_kprintf("\ta4(x14) = 0x%p(",regs->a4); + rt_kprintf(")\n"); + rt_kprintf("\ta5(x15) = 0x%p(",regs->a5); + rt_kprintf(")\n"); + rt_kprintf("\ta6(x16) = 0x%p(",regs->a6); + rt_kprintf(")\n"); + rt_kprintf("\ta7(x17) = 0x%p(",regs->a7); + rt_kprintf(")\n"); + rt_kprintf("sstatus = 0x%p\n",regs->sstatus); + rt_kprintf("\t%s\n",(regs->sstatus & SSTATUS_SIE) ? "Supervisor Interrupt Enabled" : "Supervisor Interrupt Disabled"); + rt_kprintf("\t%s\n",(regs->sstatus & SSTATUS_SPIE) ? "Last Time Supervisor Interrupt Enabled" : "Last Time Supervisor Interrupt Disabled"); + rt_kprintf("\t%s\n",(regs->sstatus & SSTATUS_SPP) ? "Last Privilege is Supervisor Mode" : "Last Privilege is User Mode"); + rt_kprintf("\t%s\n",(regs->sstatus & SSTATUS_PUM) ? "Permit to Access User Page" : "Not Permit to Access User Page"); + rt_kprintf("\t%s\n",(regs->sstatus & (1 << 19)) ? "Permit to Read Executable-only Page" : "Not Permit to Read Executable-only Page"); + rt_size_t satp_v = read_csr(satp); + rt_kprintf("satp = 0x%p\n",satp_v); + +#ifdef RT_USING_USERSPACE + rt_kprintf("\tCurrent Page Table(Physical) = 0x%p\n",__MASKVALUE(satp_v,__MASK(44)) << PAGE_OFFSET_BIT); + rt_kprintf("\tCurrent ASID = 0x%p\n",__MASKVALUE(satp_v >> 44,__MASK(16)) << PAGE_OFFSET_BIT); +#endif + + const char *mode_str = "Unknown Address Translation/Protection Mode"; + + switch(__MASKVALUE(satp_v >> 60,__MASK(4))) + { + case 0: + mode_str = "No Address Translation/Protection Mode"; + break; + + case 8: + mode_str = "Page-based 39-bit Virtual Addressing Mode"; + break; + + case 9: + mode_str = "Page-based 48-bit Virtual Addressing Mode"; + break; + } + + rt_kprintf("\tMode = %s\n",mode_str); + rt_kprintf("-----------------Dump OK---------------------\n"); +} + +static const char *Exception_Name[] = + { + "Instruction Address Misaligned", + "Instruction Access Fault", + "Illegal Instruction", + "Breakpoint", + "Load Address Misaligned", + "Load Access Fault", + "Store/AMO Address Misaligned", + "Store/AMO Access Fault", + "Environment call from U-mode", + "Environment call from S-mode", + "Reserved-10", + "Reserved-11", + "Instruction Page Fault", + "Load Page Fault", + "Reserved-14", + "Store/AMO Page Fault" + }; + +static const char *Interrupt_Name[] = + { + "User Software Interrupt", + "Supervisor Software Interrupt", + "Reversed-2", + "Reversed-3", + "User Timer Interrupt", + "Supervisor Timer Interrupt", + "Reversed-6", + "Reversed-7", + "User External Interrupt", + "Supervisor External Interrupt", + "Reserved-10", + "Reserved-11", + }; + +extern struct rt_irq_desc isr_table[]; + +void generic_handle_irq(int irq) +{ + rt_isr_handler_t isr; + void *param; + + if (irq < 0 || irq >= IRQ_MAX_NR) + { + LOG_E("bad irq number %d!\n", irq); + return; + } + + if (!irq) // irq = 0 => no irq + { + LOG_W("no irq!\n"); + return; + } + isr = isr_table[IRQ_OFFSET + irq].handler; + param = isr_table[IRQ_OFFSET + irq].param; + if (isr != RT_NULL) + { + isr(irq, param); + } + /* complete irq. */ + plic_complete(irq); +} + +/* Trap entry */ +void handle_trap(rt_size_t scause,rt_size_t stval,rt_size_t sepc,struct rt_hw_stack_frame *sp) +{ + rt_size_t id = __MASKVALUE(scause,__MASK(63UL)); + const char *msg; + + /* supervisor external interrupt */ + if ((SCAUSE_INTERRUPT & scause) && SCAUSE_S_EXTERNAL_INTR == (scause & 0xff)) + { + rt_interrupt_enter(); + plic_handle_irq(); + rt_interrupt_leave(); + return; + } + else if ((SCAUSE_INTERRUPT | SCAUSE_S_TIMER_INTR) == scause) + { + /* supervisor timer */ + rt_interrupt_enter(); + tick_isr(); + rt_interrupt_leave(); + return; + } + else if (SCAUSE_INTERRUPT & scause) + { + if(id < sizeof(Interrupt_Name) / sizeof(const char *)) + { + msg = Interrupt_Name[id]; + } + else + { + msg = "Unknown Interrupt"; + } + LOG_E("Unhandled Interrupt %ld:%s\n",id,msg); + } + else + { +#ifdef RT_USING_USERSPACE + /* page fault */ + if (id == EP_LOAD_PAGE_FAULT || + id == EP_STORE_PAGE_FAULT) + { + arch_expand_user_stack((void *)stval); + return; + } +#endif + if(id < sizeof(Exception_Name) / sizeof(const char *)) + { + msg = Exception_Name[id]; + } + else + { + msg = "Unknown Exception"; + } + + rt_kprintf("Unhandled Exception %ld:%s\n",id,msg); + } + + rt_kprintf("scause:0x%p,stval:0x%p,sepc:0x%p\n",scause,stval,sepc); + dump_regs(sp); + while(1); +} diff --git a/libcpu/aarch64/cortex-a72/SConscript b/libcpu/risc-v/virt64/SConscript similarity index 48% rename from libcpu/aarch64/cortex-a72/SConscript rename to libcpu/risc-v/virt64/SConscript index c6a4817802203c83f205c56082846214b801df82..b0ae20ba0298e00e05eba2ddc73df9424d22ec79 100644 --- a/libcpu/aarch64/cortex-a72/SConscript +++ b/libcpu/risc-v/virt64/SConscript @@ -5,9 +5,10 @@ from building import * Import('rtconfig') cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] +ASFLAGS = '' -group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/virt64/cache.c b/libcpu/risc-v/virt64/cache.c new file mode 100644 index 0000000000000000000000000000000000000000..280674090989d948610a5e44c13ce0f71c6de834 --- /dev/null +++ b/libcpu/risc-v/virt64/cache.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-29 lizhirui first version + */ + +#include +#include +#include +#include + +rt_inline rt_uint32_t rt_cpu_icache_line_size() +{ + return 0; +} + +rt_inline rt_uint32_t rt_cpu_dcache_line_size() +{ + return 0; +} + +void rt_hw_cpu_icache_invalidate(void *addr,int size) +{ + +} + +void rt_hw_cpu_dcache_invalidate(void *addr,int size) +{ + +} + +void rt_hw_cpu_dcache_clean(void *addr,int size) +{ + +} + +void rt_hw_cpu_icache_ops(int ops,void *addr,int size) +{ + if(ops == RT_HW_CACHE_INVALIDATE) + { + rt_hw_cpu_icache_invalidate(addr,size); + } +} + +void rt_hw_cpu_dcache_ops(int ops,void *addr,int size) +{ + if(ops == RT_HW_CACHE_FLUSH) + { + rt_hw_cpu_dcache_clean(addr,size); + } + else + { + rt_hw_cpu_dcache_invalidate(addr,size); + } +} + +void rt_hw_cpu_dcache_flush_all() +{ + +} + +void rt_hw_cpu_icache_invalidate_all() +{ + +} + +rt_base_t rt_hw_cpu_icache_status() +{ + return 0; +} + +rt_base_t rt_hw_cpu_dcache_status() +{ + return 0; +} + +int sys_cacheflush(void *addr, int size, int cache) +{ + return 0; +} diff --git a/libcpu/risc-v/virt64/context_gcc.S b/libcpu/risc-v/virt64/context_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..d121eac67d7d67cd9b8d712bfd9798b16635b4d3 --- /dev/null +++ b/libcpu/risc-v/virt64/context_gcc.S @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting implementation + * 2018/12/27 Jesven Add SMP support + * 2021/02/02 lizhirui Add userspace support + */ + +#define __ASSEMBLY__ +#include "cpuport.h" +#include "stackframe.h" + + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LOAD sp, (a0) + + la s0, rt_current_thread + LOAD s1, (s0) + + #ifdef RT_USING_USERSPACE + mv a0, s1 + jal lwp_mmu_switch + #endif + + RESTORE_ALL + sret + +/* + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mv t2, sp + li t0, 0x120//set SPIE and SPP = 1 + csrs sstatus, t0//if enter here,caller must be in system thread + csrw sepc, ra//return address + //saved from thread context + SAVE_ALL + + STORE t2, 32 * REGBYTES(sp)//save user_sp + + STORE sp, (a0) + + //restore to thread context + LOAD sp, (a1) + + la s0, rt_current_thread + LOAD s1, (s0) + + #ifdef RT_USING_USERSPACE + mv a0, s1 + jal lwp_mmu_switch + #endif + + RESTORE_ALL + sret diff --git a/libcpu/risc-v/virt64/cpuport.c b/libcpu/risc-v/virt64/cpuport.c new file mode 100644 index 0000000000000000000000000000000000000000..4d6fef1b30c426023f462a771dbe9d7f8075832f --- /dev/null +++ b/libcpu/risc-v/virt64/cpuport.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + * 2021-02-11 lizhirui add gp support + */ + +#include +#include + +#include "cpuport.h" +#include "stack.h" + +#include + + +/** + * @brief from thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_from_thread = 0; +/** + * @brief to thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_to_thread = 0; +/** + * @brief flag to indicate context switch in interrupt or not + * + */ +volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; + + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + extern int __global_pointer$; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; + } + + frame->ra = (rt_ubase_t)texit; + frame->gp = (rt_ubase_t)&__global_pointer$; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + frame->user_sp_exc_stack = (rt_ubase_t)(((rt_ubase_t)stk) + sizeof(struct rt_hw_stack_frame)); + + /* force to supervisor mode(SPP=1) and set SPIE and SUM to 1 */ +#ifdef ENABLE_FPU + frame->sstatus = 0x00046120; /* enable FPU */ +#else + frame->sstatus = 0x00040120; +#endif + + return stk; +} + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + * #endif + */ +#ifndef RT_USING_SMP +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + + return ; +} +#endif /* end of RT_USING_SMP */ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} diff --git a/libcpu/risc-v/virt64/cpuport.h b/libcpu/risc-v/virt64/cpuport.h new file mode 100644 index 0000000000000000000000000000000000000000..9895f9a199851a917464a8ffcc880fdb1984dbc7 --- /dev/null +++ b/libcpu/risc-v/virt64/cpuport.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#include + +/* bytes of register width */ +#ifdef ARCH_CPU_64BIT +#define STORE sd +#define LOAD ld +#define REGBYTES 8 +#else +// error here, not portable +#endif + +/* 33 general register */ +#define CTX_GENERAL_REG_NR 33 + +#ifdef ENABLE_FPU +/* 32 fpu register */ +#define CTX_FPU_REG_NR 32 +#else +#define CTX_FPU_REG_NR 0 +#endif + +/* all context registers */ +#define CTX_REG_NR (CTX_GENERAL_REG_NR + CTX_FPU_REG_NR) + +#ifndef __ASSEMBLY__ +rt_inline void rt_hw_dsb() +{ + asm volatile("fence":::"memory"); +} + +rt_inline void rt_hw_dmb() +{ + asm volatile("fence":::"memory"); +} + +rt_inline void rt_hw_isb() +{ + asm volatile("fence.i":::"memory"); +} + +#endif + +#endif +#ifdef RISCV_U_MODE +#define RISCV_USER_ENTRY 0xFFFFFFE000000000ULL +#endif diff --git a/libcpu/risc-v/virt64/encoding.h b/libcpu/risc-v/virt64/encoding.h new file mode 100644 index 0000000000000000000000000000000000000000..88c3bde9fe43edfe7ba4dff038a4b94c5dff507f --- /dev/null +++ b/libcpu/risc-v/virt64/encoding.h @@ -0,0 +1,1319 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 /* Floating-point Status */ +#define SSTATUS_FS_INITIAL 0x00002000 +#define SSTATUS_FS_CLEAN 0x00004000 +#define SSTATUS_FS_DIRTY 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP /* software interrupt */ +#define SIP_STIP MIP_STIP /* timer interrupt */ +#define SIP_SEIP MIP_SEIP /* ext interrupt */ + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif /* end of __riscv64 */ + +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif /* end of __GNUC__ */ + +#endif /* end of __ASSEMBLER__ */ + +#endif /* end of __riscv */ + +#endif /* end of RISCV_CSR_ENCODING_H */ + +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/libcpu/risc-v/virt64/interrupt_gcc.S b/libcpu/risc-v/virt64/interrupt_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..d3cc9bae7af254a311ce5975e4652dfd31069894 --- /dev/null +++ b/libcpu/risc-v/virt64/interrupt_gcc.S @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/02 Bernard The first version + * 2018/12/27 Jesven Add SMP schedule + * 2021/02/02 lizhirui Add userspace support + * 2021/12/24 JasonHu Add user setting save/restore + */ + +#define __ASSEMBLY__ +#include "cpuport.h" +#include "encoding.h" +#include "stackframe.h" + + .section .text.entry + .align 2 + .global trap_entry + .extern __stack_cpu0 + .extern get_current_thread_kernel_stack_top +trap_entry: + //backup sp + csrrw sp, sscratch, sp + //load interrupt stack + la sp, __stack_cpu0 + //backup context + SAVE_ALL + + RESTORE_SYS_GP + + //check syscall + csrr t0, scause + li t1, 8//environment call from u-mode + beq t0, t1, syscall_entry + + csrr a0, scause + csrrc a1, stval, zero + csrr a2, sepc + mv a3, sp + + /* scause, stval, sepc, sp */ + call handle_trap + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + lw s2, 0(s0) + beqz s2, spurious_interrupt + sw zero, 0(s0) + +.global rt_hw_context_switch_interrupt_do +rt_hw_context_switch_interrupt_do: + +//swap to thread kernel stack + csrr t0, sstatus + andi t0, t0, 0x100 + beqz t0, __restore_sp_from_tcb_interrupt + +__restore_sp_from_sscratch_interrupt: + csrr t0, sscratch + j __move_stack_context_interrupt + +__restore_sp_from_tcb_interrupt: + la s0, rt_interrupt_from_thread + LOAD a0, 0(s0) + jal rt_thread_sp_to_thread + jal get_thread_kernel_stack_top + mv t0, a0 + +__move_stack_context_interrupt: + mv t1, sp//src + mv sp, t0//switch stack + addi sp, sp, -CTX_REG_NR * REGBYTES + //copy context + li s0, CTX_REG_NR//cnt + mv t2, sp//dst + +copy_context_loop_interrupt: + LOAD t0, 0(t1) + STORE t0, 0(t2) + addi s0, s0, -1 + addi t1, t1, 8 + addi t2, t2, 8 + bnez s0, copy_context_loop_interrupt + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + + #ifdef RT_USING_USERSPACE + mv a0, s1 + jal rt_thread_sp_to_thread + jal lwp_mmu_switch + #endif + +spurious_interrupt: + RESTORE_ALL + sret + +syscall_entry: + //swap to thread kernel stack + csrr t0, sstatus + andi t0, t0, 0x100 + beqz t0, __restore_sp_from_tcb + +__restore_sp_from_sscratch: + csrr t0, sscratch + j __move_stack_context + +__restore_sp_from_tcb: + la a0, rt_current_thread + LOAD a0, 0(a0) + jal get_thread_kernel_stack_top + mv t0, a0 + +__move_stack_context: + mv t1, sp//src + mv sp, t0//switch stack + addi sp, sp, -CTX_REG_NR * REGBYTES + //copy context + li s0, CTX_REG_NR//cnt + mv t2, sp//dst + +copy_context_loop: + LOAD t0, 0(t1) + STORE t0, 0(t2) + addi s0, s0, -1 + addi t1, t1, 8 + addi t2, t2, 8 + bnez s0, copy_context_loop + + LOAD s0, 7 * REGBYTES(sp) + addi s0, s0, -0xfe + beqz s0, lwp_signal_quit + +#ifdef RT_USING_USERSPACE + /* save setting when syscall enter */ + call rt_thread_self + call lwp_user_setting_save +#endif + + mv a0, sp + OPEN_INTERRUPT + call syscall_handler + CLOSE_INTERRUPT + +.global syscall_exit +syscall_exit: + + #if defined(RT_USING_USERSPACE) && defined(RT_USING_SIGNALS) + LOAD s0, 2 * REGBYTES(sp) + andi s0, s0, 0x100 + bnez s0, dont_ret_to_user + li s0, 0 + j ret_to_user + dont_ret_to_user: + #endif + +#ifdef RT_USING_USERSPACE + /* restore setting when syscall exit */ + call rt_thread_self + call lwp_user_setting_restore + + /* after restore the reg `tp`, need modify context */ + STORE tp, 4 * REGBYTES(sp) +#endif + + //restore context + RESTORE_ALL + sret + +.global rt_hw_interrupt_enable +rt_hw_interrupt_enable: + csrs sstatus, a0 /* restore to old csr */ + jr ra + +.global rt_hw_interrupt_disable +rt_hw_interrupt_disable: + csrrci a0, sstatus, 2 /* clear SIE */ + jr ra diff --git a/libcpu/risc-v/virt64/io.h b/libcpu/risc-v/virt64/io.h new file mode 100644 index 0000000000000000000000000000000000000000..1285d5955bfd26a3e214f4f7806f96f7c31beaca --- /dev/null +++ b/libcpu/risc-v/virt64/io.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ +#ifndef ARCH_IO_H +#define ARCH_IO_H +#include +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") + +/* These barriers need to enforce ordering on both devices or memory. */ +#define mb() RISCV_FENCE(iorw,iorw) +#define rmb() RISCV_FENCE(ir,ir) +#define wmb() RISCV_FENCE(ow,ow) + +#define __arch_getl(a) (*(unsigned int *)(a)) +#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) + +#define dmb() mb() +#define __iormb() rmb() +#define __iowmb() wmb() + +static inline void writel(uint32_t val, volatile void *addr) +{ + __iowmb(); + __arch_putl(val, addr); +} + +static inline uint32_t readl(const volatile void *addr) +{ + uint32_t val; + + val = __arch_getl(addr); + __iormb(); + return val; +} + +static inline void write_reg( + uint32_t val, volatile void *addr, unsigned offset) +{ + writel(val, addr + offset); +} + +static inline uint32_t read_reg( + const volatile void *addr, unsigned offset) +{ + return readl(addr + offset); +} + +#endif // ARCH_IO_H diff --git a/libcpu/risc-v/virt64/mmu.c b/libcpu/risc-v/virt64/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..6ed53f312005279de7f776de8366931b2a9c1390 --- /dev/null +++ b/libcpu/risc-v/virt64/mmu.c @@ -0,0 +1,637 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#include +#include +#include +#include "page.h" +#include +#include + +#include "riscv.h" +#include "riscv_mmu.h" +#include "mmu.h" + +void *current_mmu_table = RT_NULL; +void rt_hw_cpu_icache_invalidate_all(); +void rt_hw_cpu_dcache_flush_all(); +void rt_hw_cpu_dcache_clean(void *addr,rt_size_t size); + +static void rt_hw_cpu_tlb_invalidate() +{ + rt_size_t satpv = read_csr(satp); + write_csr(satp,satpv); + mmu_flush_tlb(); +} + +void *mmu_table_get() +{ + return current_mmu_table; +} + +void switch_mmu(void *mmu_table) +{ + current_mmu_table = mmu_table; + RT_ASSERT(__CHECKALIGN(mmu_table,PAGE_OFFSET_BIT)); + mmu_set_pagetable((rt_ubase_t)mmu_table); + rt_hw_cpu_dcache_flush_all(); + rt_hw_cpu_icache_invalidate_all(); +} + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info,void *v_address,rt_size_t size,rt_size_t *vtable,rt_size_t pv_off) +{ + size_t l1_off,va_s,va_e; + rt_base_t level; + + if((!mmu_info) || (!vtable)) + { + return -1; + } + + va_s = (rt_size_t)v_address; + va_e = ((rt_size_t)v_address) + size - 1; + + if(va_e < va_s) + { + return -1; + } + + //convert address to level 1 page frame id + va_s = GET_L1(va_s); + va_e = GET_L1(va_e); + + if(va_s == 0) + { + return -1; + } + + level = rt_hw_interrupt_disable(); + + //vtable initialization check + for(l1_off = va_s;l1_off <= va_e;l1_off++) + { + size_t v = vtable[l1_off]; + + if(v) + { + rt_hw_interrupt_enable(level); + return 0; + } + } + + mmu_info -> vtable = vtable; + mmu_info -> vstart = va_s; + mmu_info -> vend = va_e; + mmu_info -> pv_off = pv_off; + + rt_hw_interrupt_enable(level); + return 0; +} + +void rt_hw_mmu_kernel_map_init(rt_mmu_info *mmu_info,rt_size_t vaddr_start,rt_size_t size) +{ + rt_size_t paddr_start = __UMASKVALUE(VPN_TO_PPN(vaddr_start,mmu_info -> pv_off),PAGE_OFFSET_MASK); + rt_size_t va_s = GET_L1(vaddr_start); + rt_size_t va_e = GET_L1(vaddr_start + size - 1); + rt_size_t i; + + for(i = va_s;i <= va_e;i++) + { + mmu_info -> vtable[i] = COMBINEPTE(paddr_start,PAGE_ATTR_RWX | PTE_G | PTE_V); + paddr_start += L1_PAGE_SIZE; + } + + rt_hw_cpu_tlb_invalidate(); +} + +//find a range of free virtual address specified by pages +static rt_size_t find_vaddr(rt_mmu_info *mmu_info,rt_size_t pages) +{ + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t find_l1 = 0,find_l2 = 0,find_l3 = 0; + rt_size_t n = 0; + + if(!pages) + { + return 0; + } + + if(!mmu_info) + { + return 0; + } + + for(l1_off = mmu_info -> vstart;l1_off <= mmu_info -> vend;l1_off++) + { + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + + if(PTE_USED(*mmu_l1)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off); + + for(l2_off = 0;l2_off < __SIZE(VPN1_BIT);l2_off++) + { + if(PTE_USED(*(mmu_l2 + l2_off))) + { + RT_ASSERT(!PAGE_IS_LEAF(*(mmu_l2 + l2_off))); + mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)),mmu_info -> pv_off); + + for(l3_off = 0;l3_off < __SIZE(VPN0_BIT);l3_off++) + { + if(PTE_USED(*(mmu_l3 + l3_off))) + { + RT_ASSERT(PAGE_IS_LEAF(*(mmu_l3 + l3_off))); + n = 0;//in use + } + else + { + if(!n) + { + find_l1 = l1_off; + find_l2 = l2_off; + find_l3 = l3_off; + } + + n++; + + if(n >= pages) + { + return COMBINEVADDR(find_l1,find_l2,find_l3); + } + } + } + } + else + { + if(!n) + { + find_l1 = l1_off; + find_l2 = l2_off; + find_l3 = 0; + } + + n += __SIZE(VPN0_BIT); + + if(n >= pages) + { + return COMBINEVADDR(find_l1,find_l2,find_l3); + } + } + } + } + else + { + if(!n) + { + find_l1 = l1_off; + find_l2 = 0; + find_l3 = 0; + } + + n += __SIZE(VPN1_BIT); + + if(n >= pages) + { + return COMBINEVADDR(find_l1,find_l2,find_l3); + } + } + } + + return 0; +} + +//check whether the range of virtual address are free +static int check_vaddr(rt_mmu_info *mmu_info,void *va,rt_size_t pages) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)va,PAGE_OFFSET_MASK); + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + + if(!pages) + { + return -1; + } + + if(!mmu_info) + { + return -1; + } + + while(pages--) + { + l1_off = GET_L1(loop_va); + l2_off = GET_L2(loop_va); + l3_off = GET_L3(loop_va); + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + + if(PTE_USED(*mmu_l1)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off) + l2_off; + + if(PTE_USED(*mmu_l2)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l2)); + mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l2),mmu_info -> pv_off) + l3_off; + + if(PTE_USED(*mmu_l3)) + { + RT_ASSERT(PAGE_IS_LEAF(*mmu_l3)); + return -1; + } + } + } + + loop_va += PAGE_SIZE; + } + + return 0; +} + +static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t npages) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t *ref_cnt; + + RT_ASSERT(mmu_info); + + while(npages--) + { + l1_off = (rt_size_t)GET_L1(loop_va); + RT_ASSERT((l1_off >= mmu_info -> vstart) && (l1_off <= mmu_info -> vend)); + l2_off = (rt_size_t)GET_L2(loop_va); + l3_off = (rt_size_t)GET_L3(loop_va); + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + RT_ASSERT(PTE_USED(*mmu_l1)) + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = ((rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off)) + l2_off; + RT_ASSERT(PTE_USED(*mmu_l2)); + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l2)); + mmu_l3 = ((rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l2),mmu_info -> pv_off)) + l3_off; + RT_ASSERT(PTE_USED(*mmu_l3)); + RT_ASSERT(PAGE_IS_LEAF(*(mmu_l3))); + *mmu_l3 = 0; + rt_hw_cpu_dcache_clean(mmu_l3,sizeof(*mmu_l3)); + mmu_l3 -= l3_off; + ref_cnt = mmu_l3 + __SIZE(VPN0_BIT); + (*ref_cnt)--; + + if(!*ref_cnt) + { + //release level 3 page + rt_pages_free(mmu_l3,1);//entry page and ref_cnt page + *mmu_l2 = 0; + rt_hw_cpu_dcache_clean(mmu_l2,sizeof(*mmu_l2)); + mmu_l2 -= l2_off; + + ref_cnt = mmu_l2 + __SIZE(VPN1_BIT); + (*ref_cnt)--; + + if(!*ref_cnt) + { + //release level 2 page + rt_pages_free(mmu_l2,1);//entry page and ref_cnt page + *mmu_l1 = 0; + rt_hw_cpu_dcache_clean(mmu_l1,sizeof(*mmu_l1)); + } + } + + loop_va += PAGE_SIZE; + } +} + +static int __rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t npages,rt_size_t attr) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + rt_size_t loop_pa = __UMASKVALUE((rt_size_t)p_addr,PAGE_OFFSET_MASK); + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t *ref_cnt; + //rt_kprintf("v_addr = 0x%p,p_addr = 0x%p,npages = %lu\n",v_addr,p_addr,npages); + + if(!mmu_info) + { + return -1; + } + + while(npages--) + { + l1_off = GET_L1(loop_va); + l2_off = GET_L2(loop_va); + l3_off = GET_L3(loop_va); + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + + if(PTE_USED(*mmu_l1)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off); + } + else + { + mmu_l2 = (rt_size_t *)rt_pages_alloc(1); + + if(mmu_l2) + { + rt_memset(mmu_l2,0,PAGE_SIZE * 2); + rt_hw_cpu_dcache_clean(mmu_l2,PAGE_SIZE * 2); + *mmu_l1 = COMBINEPTE((rt_size_t)VPN_TO_PPN(mmu_l2,mmu_info -> pv_off),PAGE_DEFAULT_ATTR_NEXT); + rt_hw_cpu_dcache_clean(mmu_l1,sizeof(*mmu_l1)); + } + else + { + __rt_hw_mmu_unmap(mmu_info,v_addr,npages); + return -1; + } + } + + if(PTE_USED(*(mmu_l2 + l2_off))) + { + RT_ASSERT(!PAGE_IS_LEAF(*(mmu_l2 + l2_off))); + mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)),mmu_info -> pv_off); + } + else + { + mmu_l3 = (rt_size_t *)rt_pages_alloc(1); + + if(mmu_l3) + { + rt_memset(mmu_l3,0,PAGE_SIZE * 2); + rt_hw_cpu_dcache_clean(mmu_l3,PAGE_SIZE * 2); + *(mmu_l2 + l2_off) = COMBINEPTE((rt_size_t)VPN_TO_PPN(mmu_l3,mmu_info -> pv_off),PAGE_DEFAULT_ATTR_NEXT); + rt_hw_cpu_dcache_clean(mmu_l2,sizeof(*mmu_l2)); + ref_cnt = mmu_l2 + __SIZE(VPN1_BIT); + (*ref_cnt)++; + } + else + { + __rt_hw_mmu_unmap(mmu_info,v_addr,npages); + return -1; + } + } + + RT_ASSERT(!PTE_USED(*(mmu_l3 + l3_off))); + ref_cnt = mmu_l3 + __SIZE(VPN0_BIT); + (*ref_cnt)++; + *(mmu_l3 + l3_off) = COMBINEPTE((rt_size_t)loop_pa,PAGE_DEFAULT_ATTR_LEAF); + rt_hw_cpu_dcache_clean(mmu_l3 + l3_off,sizeof(*(mmu_l3 + l3_off))); + + loop_va += PAGE_SIZE; + loop_pa += PAGE_SIZE; + } + + return 0; +} + +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr) +{ + rt_size_t pa_s,pa_e; + rt_size_t vaddr; + rt_size_t pages; + int ret; + + if(!size) + { + return 0; + } + + pa_s = (rt_size_t)p_addr; + pa_e = ((rt_size_t)p_addr) + size - 1; + pa_s = GET_PF_ID(pa_s); + pa_e = GET_PF_ID(pa_e); + pages = pa_e - pa_s + 1; + + if(v_addr) + { + vaddr = (rt_size_t)v_addr; + pa_s = (rt_size_t)p_addr; + + if(GET_PF_OFFSET(vaddr) != GET_PF_OFFSET(pa_s)) + { + return 0; + } + + vaddr = __UMASKVALUE(vaddr,PAGE_OFFSET_MASK); + + if(check_vaddr(mmu_info,(void *)vaddr,pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info,pages); + } + + if(vaddr) + { + ret = __rt_hw_mmu_map(mmu_info,(void *)vaddr,p_addr,pages,attr); + + if(ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void *)(vaddr | GET_PF_OFFSET((rt_size_t)p_addr)); + } + } + + return 0; +} + +static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t npages,rt_size_t attr) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + rt_size_t loop_pa; + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t *ref_cnt; + rt_size_t i; + void *va,*pa; + + if(!mmu_info) + { + return -1; + } + + while(npages--) + { + loop_pa = (rt_size_t)rt_pages_alloc(0); + + if(!loop_pa) + { + goto err; + } + + if(__rt_hw_mmu_map(mmu_info,(void *)loop_va,(void *)loop_pa,1,attr) < 0) + { + goto err; + } + + loop_va += PAGE_SIZE; + } + + return 0; + + err: + va = (void *)__UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + + for(i = 0;i < npages;i++) + { + pa = rt_hw_mmu_v2p(mmu_info,va); + + if(pa) + { + rt_pages_free((void *)PPN_TO_VPN(pa,mmu_info -> pv_off),0); + } + + va = (void *)((rt_uint8_t *)va + PAGE_SIZE); + } + + __rt_hw_mmu_unmap(mmu_info,v_addr,npages); + return -1; +} + +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr) +{ + rt_size_t vaddr; + rt_size_t offset; + rt_size_t pages; + int ret; + + if(!size) + { + return 0; + } + + offset = GET_PF_OFFSET((rt_size_t)v_addr); + size += (offset + PAGE_SIZE - 1); + pages = size >> PAGE_OFFSET_BIT; + + if(v_addr) + { + vaddr = __UMASKVALUE((rt_size_t)v_addr,PAGE_OFFSET_MASK); + + if(check_vaddr(mmu_info,(void *)vaddr,pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info,pages); + } + + if(vaddr) + { + ret = __rt_hw_mmu_map_auto(mmu_info,(void *)vaddr,pages,attr); + + if(ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void *)(vaddr | offset); + } + } + + return 0; +} + +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size) +{ + rt_size_t va_s,va_e; + rt_size_t pages; + + va_s = ((rt_size_t)v_addr) >> PAGE_OFFSET_BIT; + va_e = (((rt_size_t)v_addr) + size - 1) >> PAGE_OFFSET_BIT; + pages = va_e - va_s + 1; + __rt_hw_mmu_unmap(mmu_info,v_addr,pages); + rt_hw_cpu_tlb_invalidate(); +} + +void *rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map(mmu_info,v_addr,p_addr,size,attr); + rt_hw_interrupt_enable(level); + return ret; +} + +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map_auto(mmu_info,v_addr,size,attr); + rt_hw_interrupt_enable(level); + return ret; +} + +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + _rt_hw_mmu_unmap(mmu_info,v_addr,size); + rt_hw_interrupt_enable(level); +} + +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr) +{ + rt_size_t l1_off,l2_off,l3_off; + rt_size_t *mmu_l1,*mmu_l2,*mmu_l3; + rt_size_t pa; + + l1_off = GET_L1((rt_size_t)v_addr); + l2_off = GET_L2((rt_size_t)v_addr); + l3_off = GET_L3((rt_size_t)v_addr); + + if(!mmu_info) + { + return RT_NULL; + } + + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + + if(PTE_USED(*mmu_l1)) + { + RT_ASSERT(!PAGE_IS_LEAF(*mmu_l1)); + mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1),mmu_info -> pv_off); + + if(PTE_USED(*(mmu_l2 + l2_off))) + { + RT_ASSERT(!PAGE_IS_LEAF(*(mmu_l2 + l2_off))); + mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)),mmu_info -> pv_off); + + if(PTE_USED(*(mmu_l3 + l3_off))) + { + RT_ASSERT(PAGE_IS_LEAF(*(mmu_l3 + l3_off))); + return (void *)(GET_PADDR(*(mmu_l3 + l3_off)) | GET_PF_OFFSET((rt_size_t)v_addr)); + } + } + } + + return RT_NULL; +} + +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_v2p(mmu_info,v_addr); + rt_hw_interrupt_enable(level); + return ret; +} diff --git a/libcpu/risc-v/virt64/mmu.h b/libcpu/risc-v/virt64/mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..8ad4c1c32a591ea171a9ea94dfd8d20844c3858f --- /dev/null +++ b/libcpu/risc-v/virt64/mmu.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#ifndef __MMU_H__ +#define __MMU_H__ + +#include "riscv.h" +#include "riscv_mmu.h" +struct mem_desc +{ + rt_size_t vaddr_start; + rt_size_t vaddr_end; + rt_size_t paddr_start; + rt_size_t attr; +}; + +#define GET_PF_ID(addr) ((addr) >> PAGE_OFFSET_BIT) +#define GET_PF_OFFSET(addr) __MASKVALUE(addr,PAGE_OFFSET_MASK) +#define GET_L1(addr) __PARTBIT(addr,VPN2_SHIFT,VPN2_BIT) +#define GET_L2(addr) __PARTBIT(addr,VPN1_SHIFT,VPN1_BIT) +#define GET_L3(addr) __PARTBIT(addr,VPN0_SHIFT,VPN0_BIT) +#define GET_PPN(pte) (__PARTBIT(pte,PTE_PPN_SHIFT,PHYSICAL_ADDRESS_WIDTH_BITS - PTE_PPN_SHIFT)) +#define GET_PADDR(pte) (GET_PPN(pte) << PAGE_OFFSET_BIT) +#define VPN_TO_PPN(vaddr,pv_off) (((rt_size_t)(vaddr)) + (pv_off)) +#define PPN_TO_VPN(paddr,pv_off) (((rt_size_t)(paddr)) - (pv_off)) +#define COMBINEVADDR(l1_off,l2_off,l3_off) (((l1_off) << VPN2_SHIFT) | ((l2_off) << VPN1_SHIFT) | ((l3_off) << VPN0_SHIFT)) +#define COMBINEPTE(paddr,attr) ((((paddr) >> PAGE_OFFSET_BIT) << PTE_PPN_SHIFT) | (attr)) + +typedef struct +{ + size_t *vtable; + size_t vstart; + size_t vend; + size_t pv_off; +}rt_mmu_info; + +void *mmu_table_get(); +void switch_mmu(void *mmu_table); +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info,void *v_address,rt_size_t size,rt_size_t *vtable,rt_size_t pv_off); +void rt_hw_mmu_kernel_map_init(rt_mmu_info *mmu_info,rt_size_t vaddr_start,rt_size_t size); +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr); +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr); +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size); +void *rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr); +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr); +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size); +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr); +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr); + +#endif diff --git a/libcpu/risc-v/virt64/plic.c b/libcpu/risc-v/virt64/plic.c new file mode 100644 index 0000000000000000000000000000000000000000..d538083660bb1563674ae7e7c77439068b1c779a --- /dev/null +++ b/libcpu/risc-v/virt64/plic.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-31 lizhirui first version + */ + + +#include +#include + +#include +#include +#include +#include +#include + +#include "plic.h" + +void plic_set_priority(rt_uint32_t source,rt_uint32_t val) +{ + volatile void *plic_priority = (void *)(rt_size_t)(PLIC_BASE_ADDR + PLIC_PRIORITY_BASE + 4 * source); + writel(val,plic_priority); +} + +void plic_set_thresh(rt_uint32_t val) +{ + volatile void *plic_thresh = (void *)(rt_size_t)(PLIC_BASE_ADDR + PLIC_CONTEXT_BASE); + writel(val,plic_thresh); +} + +void plic_set_ie(rt_uint32_t word_index,rt_uint32_t val) +{ + volatile void *plic_ie = (void *)(rt_size_t)(PLIC_BASE_ADDR + PLIC_ENABLE_BASE + word_index * 4); + writel(val,plic_ie); +} + +void plic_init() +{ + int i; + + plic_set_thresh(0); + + for(i = 0;i < 128;i++) + { + plic_set_priority(i,7); + } + + plic_set_ie(0,0xffffffff); + plic_set_ie(1,0xffffffff); + plic_set_ie(2,0xffffffff); + plic_set_ie(3,0xffffffff); + + rt_uint64_t addr; + + for(addr = 0xC001000;addr <= 0xC1F1F80;addr += 4) + { + *((rt_uint32_t *)addr) = 0xffffffff; + } +} diff --git a/libcpu/risc-v/virt64/plic.h b/libcpu/risc-v/virt64/plic.h new file mode 100644 index 0000000000000000000000000000000000000000..ca126736f3e7cf2d152e197e3c57239d4fa5a528 --- /dev/null +++ b/libcpu/risc-v/virt64/plic.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-31 lizhirui first version + */ + +#ifndef __PLIC_H__ +#define __PLIC_H__ + +#define PLIC_PRIORITY_BASE 0x0 +#define PLIC_PENDING_BASE 0x1000 +#define PLIC_ENABLE_BASE 0x2000 +#define PLIC_ENABLE_STRIDE 0x80 +#define PLIC_CONTEXT_BASE 0x200000 +#define PLIC_CONTEXT_STRIDE 0x1000 + +#define PLIC_BASE_ADDR 0xC000000 + +void plic_set_priority(rt_uint32_t source,rt_uint32_t val); +void plic_set_thresh(rt_uint32_t val); +void plic_set_ie(rt_uint32_t word_index,rt_uint32_t val); +void plic_init(); + +#endif diff --git a/libcpu/risc-v/virt64/riscv.h b/libcpu/risc-v/virt64/riscv.h new file mode 100644 index 0000000000000000000000000000000000000000..d0c0cc4b38ae4c0c60dc35a8015798732d571262 --- /dev/null +++ b/libcpu/risc-v/virt64/riscv.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#ifndef __RISCV_H__ +#define __RISCV_H__ + +#include + +#define __SIZE(bit) (1UL << (bit)) +#define __MASK(bit) (__SIZE(bit) - 1UL) +#define __UMASK(bit) (~(__MASK(bit))) +#define __MASKVALUE(value,maskvalue) ((value) & (maskvalue)) +#define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue))) +#define __CHECKUPBOUND(value,bit_count) (!(((rt_size_t)value) & (~__MASK(bit_count)))) +#define __CHECKALIGN(value,start_bit) (!(((rt_size_t)value) & (__MASK(start_bit)))) + +#define __PARTBIT(value,start_bit,length) (((value) >> (start_bit)) & __MASK(length)) + +#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit)) +#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit)) + +#endif diff --git a/libcpu/risc-v/virt64/riscv_io.h b/libcpu/risc-v/virt64/riscv_io.h new file mode 100644 index 0000000000000000000000000000000000000000..cde0495b293692c024c5254d26c39f5b12ae3ec0 --- /dev/null +++ b/libcpu/risc-v/virt64/riscv_io.h @@ -0,0 +1,109 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_IO_H__ +#define __RISCV_IO_H__ + + static inline void __raw_writeb(rt_uint8_t val, volatile void *addr) + { + asm volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr)); + } + + static inline void __raw_writew(rt_uint16_t val, volatile void *addr) + { + asm volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr)); + } + + static inline void __raw_writel(rt_uint32_t val, volatile void *addr) + { + asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr)); + } + + #if __riscv_xlen != 32 + static inline void __raw_writeq(rt_uint64_t val, volatile void *addr) + { + asm volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr)); + } + #endif + + static inline rt_uint8_t __raw_readb(const volatile void *addr) + { + rt_uint8_t val; + + asm volatile("lb %0, 0(%1)" : "=r"(val) : "r"(addr)); + return val; + } + + static inline rt_uint16_t __raw_readw(const volatile void *addr) + { + rt_uint16_t val; + + asm volatile("lh %0, 0(%1)" : "=r"(val) : "r"(addr)); + return val; + } + + static inline rt_uint32_t __raw_readl(const volatile void *addr) + { + rt_uint32_t val; + + asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr)); + return val; + } + + #if __riscv_xlen != 32 + static inline rt_uint64_t __raw_readq(const volatile void *addr) + { + rt_uint64_t val; + + asm volatile("ld %0, 0(%1)" : "=r"(val) : "r"(addr)); + return val; + } + #endif + + /* FIXME: These are now the same as asm-generic */ + + /* clang-format off */ + + #define __io_rbr() do {} while (0) + #define __io_rar() do {} while (0) + #define __io_rbw() do {} while (0) + #define __io_raw() do {} while (0) + + #define readb_relaxed(c) ({ rt_uint8_t __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; }) + #define readw_relaxed(c) ({ rt_uint16_t __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; }) + #define readl_relaxed(c) ({ rt_uint32_t __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; }) + + #define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); }) + #define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); }) + #define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); }) + + #if __riscv_xlen != 32 + #define readq_relaxed(c) ({ rt_uint64_t __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; }) + #define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); }) + #endif + + #define __io_br() do {} while (0) + #define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory"); + #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory"); + #define __io_aw() do {} while (0) + + #define readb(c) ({ rt_uint8_t __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; }) + #define readw(c) ({ rt_uint16_t __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; }) + #define readl(c) ({ rt_uint32_t __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; }) + + #define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); }) + #define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); }) + #define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); }) + + #if __riscv_xlen != 32 + #define readq(c) ({ rt_uint64_t __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; }) + #define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); }) + #endif + +#endif diff --git a/libcpu/risc-v/virt64/riscv_mmu.c b/libcpu/risc-v/virt64/riscv_mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..9ba48e34c42c0067212743fbc76ee069bb6a8aa3 --- /dev/null +++ b/libcpu/risc-v/virt64/riscv_mmu.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#include +#include + +#include +#include +#include +#include + +#include "riscv_mmu.h" + +void mmu_set_pagetable(rt_ubase_t addr) +{ + RT_ASSERT(__CHECKALIGN(addr,PAGE_OFFSET_BIT)); + RT_ASSERT(__CHECKUPBOUND(addr,PHYSICAL_ADDRESS_WIDTH_BITS)); + write_csr(satp,(((size_t)8) << 60) | (addr >> PAGE_OFFSET_BIT)); + mmu_flush_tlb(); +} + +void mmu_enable_user_page_access() +{ + set_csr(sstatus,SSTATUS_PUM); +} + +void mmu_disable_user_page_access() +{ + clear_csr(sstatus,SSTATUS_PUM); +} diff --git a/libcpu/risc-v/virt64/riscv_mmu.h b/libcpu/risc-v/virt64/riscv_mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..89ef712a5be7e8b77c8c687256a78fe3e797fd52 --- /dev/null +++ b/libcpu/risc-v/virt64/riscv_mmu.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#ifndef __RISCV_MMU_H__ +#define __RISCV_MMU_H__ + +#include "riscv.h" + +#undef PAGE_SIZE + +#define PAGE_OFFSET_SHIFT 0 +#define PAGE_OFFSET_BIT 12 +#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT) +#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT) +#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT) +#define VPN0_BIT 9 +#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT) +#define VPN1_BIT 9 +#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT) +#define VPN2_BIT 9 + +#define PPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT) +#define PPN0_BIT 9 +#define PPN1_SHIFT (PPN0_SHIFT + PPN0_BIT) +#define PPN1_BIT 9 +#define PPN2_SHIFT (PPN1_SHIFT + PPN1_BIT) +#define PPN2_BIT 26 + +#define L1_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT + VPN1_BIT) +#define L2_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT) +#define L3_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT) + +#define ARCH_ADDRESS_WIDTH_BITS 64 + +#define PHYSICAL_ADDRESS_WIDTH_BITS 56 + +#define PAGE_ATTR_NEXT_LEVEL (0) +#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R) +#define PAGE_ATTR_READONLY (PTE_R) +#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R) + +#define PAGE_ATTR_USER (PTE_U) +#define PAGE_ATTR_SYSTEM (0) + +#define PAGE_DEFAULT_ATTR_LEAF (PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G) +#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G) + +#define PAGE_IS_LEAF(pte) __MASKVALUE(pte,PAGE_ATTR_RWX) + +#define PTE_USED(pte) __MASKVALUE(pte,PTE_V) + +#define mmu_flush_tlb() do{asm volatile("sfence.vma x0,x0");}while(0) + +//compatible to rt-smart new version +#define MMU_MAP_K_DEVICE (PAGE_ATTR_RWX | PTE_V | PTE_G) +#define MMU_MAP_K_RWCB (PAGE_ATTR_RWX | PTE_V | PTE_G) +#define ARCH_PAGE_SIZE PAGE_SIZE +#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1) +#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT + +void mmu_set_pagetable(rt_ubase_t addr); +void mmu_enable_user_page_access(); +void mmu_disable_user_page_access(); + +#endif diff --git a/libcpu/risc-v/virt64/sbi.c b/libcpu/risc-v/virt64/sbi.c new file mode 100644 index 0000000000000000000000000000000000000000..f848ec781032a5d71031c0bd8e10da6be6fa46a6 --- /dev/null +++ b/libcpu/risc-v/virt64/sbi.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 Bernard port from FreeBSD + */ + +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2019 Mitchell Horne + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "sbi.h" +#include +#include + +/* SBI Implementation-Specific Definitions */ +#define OPENSBI_VERSION_MAJOR_OFFSET 16 +#define OPENSBI_VERSION_MINOR_MASK 0xFFFF + +unsigned long sbi_spec_version; +unsigned long sbi_impl_id; +unsigned long sbi_impl_version; + +static bool has_time_extension = false; +static bool has_ipi_extension = false; +static bool has_rfnc_extension = false; + +static struct sbi_ret +sbi_get_spec_version(void) +{ + return (SBI_CALL0(SBI_EXT_ID_BASE, SBI_BASE_GET_SPEC_VERSION)); +} + +static struct sbi_ret +sbi_get_impl_id(void) +{ + return (SBI_CALL0(SBI_EXT_ID_BASE, SBI_BASE_GET_IMPL_ID)); +} + +static struct sbi_ret +sbi_get_impl_version(void) +{ + return (SBI_CALL0(SBI_EXT_ID_BASE, SBI_BASE_GET_IMPL_VERSION)); +} + +void +sbi_print_version(void) +{ + u_int major; + u_int minor; + + /* For legacy SBI implementations. */ + if (sbi_spec_version == 0) + { + rt_kprintf("SBI: Unknown (Legacy) Implementation\n"); + rt_kprintf("SBI Specification Version: 0.1\n"); + return; + } + + switch (sbi_impl_id) + { + case (SBI_IMPL_ID_BBL): + rt_kprintf("SBI: Berkely Boot Loader %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_XVISOR): + rt_kprintf("SBI: eXtensible Versatile hypervISOR %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_KVM): + rt_kprintf("SBI: Kernel-based Virtual Machine %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_RUSTSBI): + rt_kprintf("SBI: RustSBI %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_DIOSIX): + rt_kprintf("SBI: Diosix %lu\n", sbi_impl_version); + break; + case (SBI_IMPL_ID_OPENSBI): + major = sbi_impl_version >> OPENSBI_VERSION_MAJOR_OFFSET; + minor = sbi_impl_version & OPENSBI_VERSION_MINOR_MASK; + rt_kprintf("SBI: OpenSBI v%u.%u\n", major, minor); + break; + default: + rt_kprintf("SBI: Unrecognized Implementation: %lu\n", sbi_impl_id); + break; + } + + major = (sbi_spec_version & SBI_SPEC_VERS_MAJOR_MASK) >> + SBI_SPEC_VERS_MAJOR_OFFSET; + minor = (sbi_spec_version & SBI_SPEC_VERS_MINOR_MASK); + rt_kprintf("SBI Specification Version: %u.%u\n", major, minor); +} + +void +sbi_set_timer(uint64_t val) +{ + struct sbi_ret ret; + + /* Use the TIME legacy replacement extension, if available. */ + if (has_time_extension) + { + ret = SBI_CALL1(SBI_EXT_ID_TIME, SBI_TIME_SET_TIMER, val); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL1(SBI_SET_TIMER, 0, val); + } +} + +void +sbi_send_ipi(const unsigned long *hart_mask) +{ + struct sbi_ret ret; + + /* Use the IPI legacy replacement extension, if available. */ + if (has_ipi_extension) + { + ret = SBI_CALL2(SBI_EXT_ID_IPI, SBI_IPI_SEND_IPI, + *hart_mask, 0); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL1(SBI_SEND_IPI, 0, (uint64_t)hart_mask); + } +} + +void +sbi_remote_fence_i(const unsigned long *hart_mask) +{ + struct sbi_ret ret; + + /* Use the RFENCE legacy replacement extension, if available. */ + if (has_rfnc_extension) + { + ret = SBI_CALL2(SBI_EXT_ID_RFNC, SBI_RFNC_REMOTE_FENCE_I, + *hart_mask, 0); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL1(SBI_REMOTE_FENCE_I, 0, (uint64_t)hart_mask); + } +} + +void +sbi_remote_sfence_vma(const unsigned long *hart_mask, unsigned long start, unsigned long size) +{ + struct sbi_ret ret; + + /* Use the RFENCE legacy replacement extension, if available. */ + if (has_rfnc_extension) + { + ret = SBI_CALL4(SBI_EXT_ID_RFNC, SBI_RFNC_REMOTE_SFENCE_VMA, + *hart_mask, 0, start, size); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL3(SBI_REMOTE_SFENCE_VMA, 0, (uint64_t)hart_mask, + start, size); + } +} + +void +sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long start, unsigned long size, + unsigned long asid) +{ + struct sbi_ret ret; + + /* Use the RFENCE legacy replacement extension, if available. */ + if (has_rfnc_extension) + { + ret = SBI_CALL5(SBI_EXT_ID_RFNC, SBI_RFNC_REMOTE_SFENCE_VMA_ASID, + *hart_mask, 0, start, size, asid); + RT_ASSERT(ret.error == SBI_SUCCESS); + } + else + { + (void)SBI_CALL4(SBI_REMOTE_SFENCE_VMA_ASID, 0, + (uint64_t)hart_mask, start, size, asid); + } +} + +int +sbi_hsm_hart_start(unsigned long hart, unsigned long start_addr, unsigned long priv) +{ + struct sbi_ret ret; + + ret = SBI_CALL3(SBI_EXT_ID_HSM, SBI_HSM_HART_START, hart, start_addr, priv); + return (ret.error != 0 ? (int)ret.error : 0); +} + +void +sbi_hsm_hart_stop(void) +{ + (void)SBI_CALL0(SBI_EXT_ID_HSM, SBI_HSM_HART_STOP); +} + +int +sbi_hsm_hart_status(unsigned long hart) +{ + struct sbi_ret ret; + + ret = SBI_CALL1(SBI_EXT_ID_HSM, SBI_HSM_HART_STATUS, hart); + + return (ret.error != 0 ? (int)ret.error : (int)ret.value); +} + +void +sbi_init(void) +{ + struct sbi_ret sret; + + /* + * Get the spec version. For legacy SBI implementations this will + * return an error, otherwise it is guaranteed to succeed. + */ + sret = sbi_get_spec_version(); + if (sret.error != 0) + { + /* We are running a legacy SBI implementation. */ + sbi_spec_version = 0; + return; + } + + /* Set the SBI implementation info. */ + sbi_spec_version = sret.value; + sbi_impl_id = sbi_get_impl_id().value; + sbi_impl_version = sbi_get_impl_version().value; + + /* Probe for legacy replacement extensions. */ + if (sbi_probe_extension(SBI_EXT_ID_TIME) != 0) + has_time_extension = true; + if (sbi_probe_extension(SBI_EXT_ID_IPI) != 0) + has_ipi_extension = true; + if (sbi_probe_extension(SBI_EXT_ID_RFNC) != 0) + has_rfnc_extension = true; +} diff --git a/libcpu/risc-v/virt64/sbi.h b/libcpu/risc-v/virt64/sbi.h new file mode 100644 index 0000000000000000000000000000000000000000..0e95ede3343eec9aa9ba7ed0b92797b0978631c2 --- /dev/null +++ b/libcpu/risc-v/virt64/sbi.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 Bernard port from FreeBSD + */ + +/*- + * Copyright (c) 2016-2017 Ruslan Bukin + * All rights reserved. + * Copyright (c) 2019 Mitchell Horne + * + * Portions of this software were developed by SRI International and the + * University of Cambridge Computer Laboratory under DARPA/AFRL contract + * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Portions of this software were developed by the University of Cambridge + * Computer Laboratory as part of the CTSRD Project, with support from the + * UK Higher Education Innovation Fund (HEIF). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_SBI_H_ +#define _MACHINE_SBI_H_ + +#include + +/* SBI Specification Version */ +#define SBI_SPEC_VERS_MAJOR_OFFSET 24 +#define SBI_SPEC_VERS_MAJOR_MASK (0x7F << SBI_SPEC_VERS_MAJOR_OFFSET) +#define SBI_SPEC_VERS_MINOR_OFFSET 0 +#define SBI_SPEC_VERS_MINOR_MASK (0xFFFFFF << SBI_SPEC_VERS_MINOR_OFFSET) + +/* SBI Implementation IDs */ +#define SBI_IMPL_ID_BBL 0 +#define SBI_IMPL_ID_OPENSBI 1 +#define SBI_IMPL_ID_XVISOR 2 +#define SBI_IMPL_ID_KVM 3 +#define SBI_IMPL_ID_RUSTSBI 4 +#define SBI_IMPL_ID_DIOSIX 5 + +/* SBI Error Codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILURE -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 + +/* SBI Base Extension */ +#define SBI_EXT_ID_BASE 0x10 +#define SBI_BASE_GET_SPEC_VERSION 0 +#define SBI_BASE_GET_IMPL_ID 1 +#define SBI_BASE_GET_IMPL_VERSION 2 +#define SBI_BASE_PROBE_EXTENSION 3 +#define SBI_BASE_GET_MVENDORID 4 +#define SBI_BASE_GET_MARCHID 5 +#define SBI_BASE_GET_MIMPID 6 + +/* Timer (TIME) Extension */ +#define SBI_EXT_ID_TIME 0x54494D45 +#define SBI_TIME_SET_TIMER 0 + +/* IPI (IPI) Extension */ +#define SBI_EXT_ID_IPI 0x735049 +#define SBI_IPI_SEND_IPI 0 + +/* RFENCE (RFNC) Extension */ +#define SBI_EXT_ID_RFNC 0x52464E43 +#define SBI_RFNC_REMOTE_FENCE_I 0 +#define SBI_RFNC_REMOTE_SFENCE_VMA 1 +#define SBI_RFNC_REMOTE_SFENCE_VMA_ASID 2 +#define SBI_RFNC_REMOTE_HFENCE_GVMA_VMID 3 +#define SBI_RFNC_REMOTE_HFENCE_GVMA 4 +#define SBI_RFNC_REMOTE_HFENCE_VVMA_ASID 5 +#define SBI_RFNC_REMOTE_HFENCE_VVMA 6 + +/* Hart State Management (HSM) Extension */ +#define SBI_EXT_ID_HSM 0x48534D +#define SBI_HSM_HART_START 0 +#define SBI_HSM_HART_STOP 1 +#define SBI_HSM_HART_STATUS 2 +#define SBI_HSM_STATUS_STARTED 0 +#define SBI_HSM_STATUS_STOPPED 1 +#define SBI_HSM_STATUS_START_PENDING 2 +#define SBI_HSM_STATUS_STOP_PENDING 3 + +/* Legacy Extensions */ +#define SBI_SET_TIMER 0 +#define SBI_CONSOLE_PUTCHAR 1 +#define SBI_CONSOLE_GETCHAR 2 +#define SBI_CLEAR_IPI 3 +#define SBI_SEND_IPI 4 +#define SBI_REMOTE_FENCE_I 5 +#define SBI_REMOTE_SFENCE_VMA 6 +#define SBI_REMOTE_SFENCE_VMA_ASID 7 +#define SBI_SHUTDOWN 8 + +#define SBI_CALL0(e, f) SBI_CALL5(e, f, 0, 0, 0, 0, 0) +#define SBI_CALL1(e, f, p1) SBI_CALL5(e, f, p1, 0, 0, 0, 0) +#define SBI_CALL2(e, f, p1, p2) SBI_CALL5(e, f, p1, p2, 0, 0, 0) +#define SBI_CALL3(e, f, p1, p2, p3) SBI_CALL5(e, f, p1, p2, p3, 0, 0) +#define SBI_CALL4(e, f, p1, p2, p3, p4) SBI_CALL5(e, f, p1, p2, p3, p4, 0) +#define SBI_CALL5(e, f, p1, p2, p3, p4, p5) sbi_call(e, f, p1, p2, p3, p4, p5) + +/* + * Documentation available at + * https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc + */ + +struct sbi_ret +{ + long error; + long value; +}; + +static __inline struct sbi_ret +sbi_call(uint64_t arg7, uint64_t arg6, uint64_t arg0, uint64_t arg1, + uint64_t arg2, uint64_t arg3, uint64_t arg4) +{ + struct sbi_ret ret; + + register uintptr_t a0 __asm("a0") = (uintptr_t)(arg0); + register uintptr_t a1 __asm("a1") = (uintptr_t)(arg1); + register uintptr_t a2 __asm("a2") = (uintptr_t)(arg2); + register uintptr_t a3 __asm("a3") = (uintptr_t)(arg3); + register uintptr_t a4 __asm("a4") = (uintptr_t)(arg4); + register uintptr_t a6 __asm("a6") = (uintptr_t)(arg6); + register uintptr_t a7 __asm("a7") = (uintptr_t)(arg7); + + __asm __volatile(\ + "ecall" \ + : "+r"(a0), "+r"(a1) \ + : "r"(a2), "r"(a3), "r"(a4), "r"(a6), "r"(a7) \ + : "memory"); + + ret.error = a0; + ret.value = a1; + return (ret); +} + +/* Base extension functions and variables. */ +extern unsigned long sbi_spec_version; +extern unsigned long sbi_impl_id; +extern unsigned long sbi_impl_version; + +static __inline long +sbi_probe_extension(long id) +{ + return (SBI_CALL1(SBI_EXT_ID_BASE, SBI_BASE_PROBE_EXTENSION, id).value); +} + +/* TIME extension functions. */ +void sbi_set_timer(uint64_t val); + +/* IPI extension functions. */ +void sbi_send_ipi(const unsigned long *hart_mask); + +/* RFENCE extension functions. */ +void sbi_remote_fence_i(const unsigned long *hart_mask); +void sbi_remote_sfence_vma(const unsigned long *hart_mask, unsigned long start, unsigned long size); +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long start, + unsigned long size, unsigned long asid); + +/* Hart State Management extension functions. */ + +/* + * Start execution on the specified hart at physical address start_addr. The + * register a0 will contain the hart's ID, and a1 will contain the value of + * priv. + */ +int sbi_hsm_hart_start(unsigned long hart, unsigned long start_addr, unsigned long priv); + +/* + * Stop execution on the current hart. Interrupts should be disabled, or this + * function may return. + */ +void sbi_hsm_hart_stop(void); + +/* + * Get the execution status of the specified hart. The status will be one of: + * - SBI_HSM_STATUS_STARTED + * - SBI_HSM_STATUS_STOPPED + * - SBI_HSM_STATUS_START_PENDING + * - SBI_HSM_STATUS_STOP_PENDING + */ +int sbi_hsm_hart_status(unsigned long hart); + +/* Legacy extension functions. */ +static __inline void +sbi_console_putchar(int ch) +{ + (void)SBI_CALL1(SBI_CONSOLE_PUTCHAR, 0, ch); +} + +static __inline int +sbi_console_getchar(void) +{ + /* + * XXX: The "error" is returned here because legacy SBI functions + * continue to return their value in a0. + */ + return (SBI_CALL0(SBI_CONSOLE_GETCHAR, 0).error); +} + +static __inline void +sbi_shutdown(void) +{ + (void)SBI_CALL0(SBI_SHUTDOWN, 0); +} + +void sbi_print_version(void); +void sbi_init(void); + +#endif /* !_MACHINE_SBI_H_ */ diff --git a/libcpu/risc-v/virt64/stack.h b/libcpu/risc-v/virt64/stack.h new file mode 100644 index 0000000000000000000000000000000000000000..bd47570d9871f1eb372b15d39c0f94e67d4084b8 --- /dev/null +++ b/libcpu/risc-v/virt64/stack.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#ifndef __STACK_H__ +#define __STACK_H__ + +#include +struct rt_hw_stack_frame +{ + rt_ubase_t epc; /* epc - epc - program counter */ + rt_ubase_t ra; /* x1 - ra - return address for jumps */ + rt_ubase_t sstatus; /* - supervisor status register */ + rt_ubase_t gp; /* x3 - gp - global pointer */ + rt_ubase_t tp; /* x4 - tp - thread pointer */ + rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /* x9 - s1 - saved register 1 */ + rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /* x12 - a2 - function argument 2 */ + rt_ubase_t a3; /* x13 - a3 - function argument 3 */ + rt_ubase_t a4; /* x14 - a4 - function argument 4 */ + rt_ubase_t a5; /* x15 - a5 - function argument 5 */ + rt_ubase_t a6; /* x16 - a6 - function argument 6 */ + rt_ubase_t a7; /* x17 - s7 - function argument 7 */ + rt_ubase_t s2; /* x18 - s2 - saved register 2 */ + rt_ubase_t s3; /* x19 - s3 - saved register 3 */ + rt_ubase_t s4; /* x20 - s4 - saved register 4 */ + rt_ubase_t s5; /* x21 - s5 - saved register 5 */ + rt_ubase_t s6; /* x22 - s6 - saved register 6 */ + rt_ubase_t s7; /* x23 - s7 - saved register 7 */ + rt_ubase_t s8; /* x24 - s8 - saved register 8 */ + rt_ubase_t s9; /* x25 - s9 - saved register 9 */ + rt_ubase_t s10; /* x26 - s10 - saved register 10 */ + rt_ubase_t s11; /* x27 - s11 - saved register 11 */ + rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ + rt_ubase_t user_sp_exc_stack; /* sscratch - user mode sp/exception stack */ +#ifdef ENABLE_FPU + rt_ubase_t f[CTX_FPU_REG_NR]; /* f0~f31 */ +#endif +}; + +#endif diff --git a/libcpu/risc-v/virt64/stackframe.h b/libcpu/risc-v/virt64/stackframe.h new file mode 100644 index 0000000000000000000000000000000000000000..1e191900b4a262e7aefb08611fd7e5ed832fb310 --- /dev/null +++ b/libcpu/risc-v/virt64/stackframe.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-02 lizhirui first version + * 2021-02-11 lizhirui fixed gp save/store bug + * 2021-11-18 JasonHu add fpu registers save/restore + */ + +#ifndef __STACKFRAME_H__ +#define __STACKFRAME_H__ + +#include "cpuport.h" +#include "encoding.h" + +#ifdef ENABLE_FPU +#define FPU_CTX_F0_OFF 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F1_OFF 8 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F2_OFF 16 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F3_OFF 24 /* offsetof(fpu_context_t, fpustatus.f[3]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F4_OFF 32 /* offsetof(fpu_context_t, fpustatus.f[4]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F5_OFF 40 /* offsetof(fpu_context_t, fpustatus.f[5]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F6_OFF 48 /* offsetof(fpu_context_t, fpustatus.f[6]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F7_OFF 56 /* offsetof(fpu_context_t, fpustatus.f[7]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F8_OFF 64 /* offsetof(fpu_context_t, fpustatus.f[8]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F9_OFF 72 /* offsetof(fpu_context_t, fpustatus.f[9]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F10_OFF 80 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F11_OFF 88 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F12_OFF 96 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F13_OFF 104 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F14_OFF 112 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F15_OFF 120 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F16_OFF 128 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F17_OFF 136 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F18_OFF 144 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F19_OFF 152 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F20_OFF 160 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F21_OFF 168 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F22_OFF 176 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F23_OFF 184 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F24_OFF 192 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F25_OFF 200 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F26_OFF 208 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F27_OFF 216 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F28_OFF 224 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F29_OFF 232 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F30_OFF 240 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F31_OFF 248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#endif /* ENABLE_FPU */ + +/** + * The register `tp` always save/restore when context switch, + * we call `lwp_user_setting_save` when syscall enter, + * call `lwp_user_setting_restore` when syscall exit + * and modify context stack after `lwp_user_setting_restore` called + * so that the `tp` can be the correct thread area value. + */ + +.macro SAVE_ALL + +#ifdef ENABLE_FPU + /* reserve float registers */ + addi sp, sp, -CTX_FPU_REG_NR * REGBYTES +#endif /* ENABLE_FPU */ + + /* save general registers */ + addi sp, sp, -CTX_GENERAL_REG_NR * REGBYTES + STORE x1, 1 * REGBYTES(sp) + + csrr x1, sstatus + STORE x1, 2 * REGBYTES(sp) + + csrr x1, sepc + STORE x1, 0 * REGBYTES(sp) + + STORE x3, 3 * REGBYTES(sp) + STORE x4, 4 * REGBYTES(sp) /* save tp */ + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + csrr t0, sscratch + STORE t0, 32 * REGBYTES(sp) + +#ifdef ENABLE_FPU + /* backup sp and adjust sp to save float registers */ + mv t1, sp + addi t1, t1, CTX_GENERAL_REG_NR * REGBYTES + + li t0, SSTATUS_FS + csrs sstatus, t0 + fsd f0, FPU_CTX_F0_OFF(t1) + fsd f1, FPU_CTX_F1_OFF(t1) + fsd f2, FPU_CTX_F2_OFF(t1) + fsd f3, FPU_CTX_F3_OFF(t1) + fsd f4, FPU_CTX_F4_OFF(t1) + fsd f5, FPU_CTX_F5_OFF(t1) + fsd f6, FPU_CTX_F6_OFF(t1) + fsd f7, FPU_CTX_F7_OFF(t1) + fsd f8, FPU_CTX_F8_OFF(t1) + fsd f9, FPU_CTX_F9_OFF(t1) + fsd f10, FPU_CTX_F10_OFF(t1) + fsd f11, FPU_CTX_F11_OFF(t1) + fsd f12, FPU_CTX_F12_OFF(t1) + fsd f13, FPU_CTX_F13_OFF(t1) + fsd f14, FPU_CTX_F14_OFF(t1) + fsd f15, FPU_CTX_F15_OFF(t1) + fsd f16, FPU_CTX_F16_OFF(t1) + fsd f17, FPU_CTX_F17_OFF(t1) + fsd f18, FPU_CTX_F18_OFF(t1) + fsd f19, FPU_CTX_F19_OFF(t1) + fsd f20, FPU_CTX_F20_OFF(t1) + fsd f21, FPU_CTX_F21_OFF(t1) + fsd f22, FPU_CTX_F22_OFF(t1) + fsd f23, FPU_CTX_F23_OFF(t1) + fsd f24, FPU_CTX_F24_OFF(t1) + fsd f25, FPU_CTX_F25_OFF(t1) + fsd f26, FPU_CTX_F26_OFF(t1) + fsd f27, FPU_CTX_F27_OFF(t1) + fsd f28, FPU_CTX_F28_OFF(t1) + fsd f29, FPU_CTX_F29_OFF(t1) + fsd f30, FPU_CTX_F30_OFF(t1) + fsd f31, FPU_CTX_F31_OFF(t1) + + /* clr FS domain */ + csrc sstatus, t0 + + /* clean status would clr sr_sd; */ + li t0, SSTATUS_FS_CLEAN + csrs sstatus, t0 + +#endif /* ENABLE_FPU */ + +.endm + +.macro RESTORE_ALL + +#ifdef ENABLE_FPU + /* restore float register */ + mv t2, sp + addi t2, t2, CTX_GENERAL_REG_NR * REGBYTES /* skip all normal reg */ + + li t0, SSTATUS_FS + csrs sstatus, t0 + fld f0, FPU_CTX_F0_OFF(t2) + fld f1, FPU_CTX_F1_OFF(t2) + fld f2, FPU_CTX_F2_OFF(t2) + fld f3, FPU_CTX_F3_OFF(t2) + fld f4, FPU_CTX_F4_OFF(t2) + fld f5, FPU_CTX_F5_OFF(t2) + fld f6, FPU_CTX_F6_OFF(t2) + fld f7, FPU_CTX_F7_OFF(t2) + fld f8, FPU_CTX_F8_OFF(t2) + fld f9, FPU_CTX_F9_OFF(t2) + fld f10, FPU_CTX_F10_OFF(t2) + fld f11, FPU_CTX_F11_OFF(t2) + fld f12, FPU_CTX_F12_OFF(t2) + fld f13, FPU_CTX_F13_OFF(t2) + fld f14, FPU_CTX_F14_OFF(t2) + fld f15, FPU_CTX_F15_OFF(t2) + fld f16, FPU_CTX_F16_OFF(t2) + fld f17, FPU_CTX_F17_OFF(t2) + fld f18, FPU_CTX_F18_OFF(t2) + fld f19, FPU_CTX_F19_OFF(t2) + fld f20, FPU_CTX_F20_OFF(t2) + fld f21, FPU_CTX_F21_OFF(t2) + fld f22, FPU_CTX_F22_OFF(t2) + fld f23, FPU_CTX_F23_OFF(t2) + fld f24, FPU_CTX_F24_OFF(t2) + fld f25, FPU_CTX_F25_OFF(t2) + fld f26, FPU_CTX_F26_OFF(t2) + fld f27, FPU_CTX_F27_OFF(t2) + fld f28, FPU_CTX_F28_OFF(t2) + fld f29, FPU_CTX_F29_OFF(t2) + fld f30, FPU_CTX_F30_OFF(t2) + fld f31, FPU_CTX_F31_OFF(t2) + + /* clr FS domain */ + csrc sstatus, t0 + + /* clean status would clr sr_sd; */ + li t0, SSTATUS_FS_CLEAN + csrs sstatus, t0 + +#endif /* ENABLE_FPU */ + + /* restore general register */ + + /* resw ra to sepc */ + LOAD x1, 0 * REGBYTES(sp) + csrw sepc, x1 + + LOAD x1, 2 * REGBYTES(sp) + csrw sstatus, x1 + + LOAD x1, 1 * REGBYTES(sp) + + LOAD x3, 3 * REGBYTES(sp) + LOAD x4, 4 * REGBYTES(sp) /* restore tp */ + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + /* restore user sp */ + LOAD sp, 32 * REGBYTES(sp) +.endm + +.macro RESTORE_SYS_GP + .option push + .option norelax + la gp, __global_pointer$ + .option pop +.endm + +.macro OPEN_INTERRUPT + csrsi sstatus, 2 +.endm + +.macro CLOSE_INTERRUPT + csrci sstatus, 2 +.endm + +#endif diff --git a/libcpu/risc-v/virt64/startup_gcc.S b/libcpu/risc-v/virt64/startup_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..6ed73d86fe0f608991a105b03282652846b682c1 --- /dev/null +++ b/libcpu/risc-v/virt64/startup_gcc.S @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/01 Bernard The first version + * 2018/12/27 Jesven Add SMP support + * 2020/6/12 Xim Port to QEMU and remove SMP support + */ + +#define SSTATUS_FS 0x00006000U /* initial state of FPU, clear to disable */ +#define __ASSEMBLY__ +#include + + .global _start + .section ".start", "ax" +_start: + j 1f + .word 0xdeadbeef + .align 3 + .global g_wake_up + g_wake_up: + .dword 1 + .dword 0 +1: + csrw sie, 0 + csrw sip, 0 + la t0, trap_entry + csrw stvec, t0 + + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10,0 + li x11,0 + li x12,0 + li x13,0 + li x14,0 + li x15,0 + li x16,0 + li x17,0 + li x18,0 + li x19,0 + li x20,0 + li x21,0 + li x22,0 + li x23,0 + li x24,0 + li x25,0 + li x26,0 + li x27,0 + li x28,0 + li x29,0 + li x30,0 + li x31,0 + + /* set to disable FPU */ + li t0, SSTATUS_FS + csrc sstatus, t0 + li t0, 0x40000 // SUM in sstatus + csrs sstatus, t0 + +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + // removed SMP support here + la sp, __stack_start__ + li t0, __STACKSIZE__ + add sp, sp, t0 + csrw sscratch, sp + j primary_cpu_entry diff --git a/libcpu/risc-v/virt64/syscall_c.c b/libcpu/risc-v/virt64/syscall_c.c new file mode 100644 index 0000000000000000000000000000000000000000..16c8369db1b6e8d6f4e533e2d67f75a0b9abdc98 --- /dev/null +++ b/libcpu/risc-v/virt64/syscall_c.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-03 lizhirui first version + */ + +#include +#include + +#define DBG_LEVEL DBG_WARNING +//#define DBG_LEVEL DBG_INFO +#include + +#include +#include +#include +#include +#include + +#include + +#include "riscv_mmu.h" +#include "stack.h" + +typedef rt_size_t (*syscallfunc_t)(rt_size_t,rt_size_t,rt_size_t,rt_size_t,rt_size_t,rt_size_t,rt_size_t); +syscallfunc_t lwp_get_sys_api(uint32_t); + +void syscall_handler(struct rt_hw_stack_frame *regs) +{ + if(regs -> a7 == 0) + { + rt_kprintf("syscall id = 0!\n"); + while(1); + } + + if(regs -> a7 == 0xdeadbeef) + { + rt_kprintf("syscall id = 0xdeadbeef\n"); + while(1); + } + + syscallfunc_t syscallfunc = (syscallfunc_t)lwp_get_sys_api(regs -> a7); + + if(syscallfunc == RT_NULL) + { + rt_kprintf("unsupported syscall!\n"); + while(1); + } + + LOG_I("\033[36msyscall id = %d,arg0 = 0x%p,arg1 = 0x%p,arg2 = 0x%p,arg3 = 0x%p,arg4 = 0x%p,arg5 = 0x%p,arg6 = 0x%p\n\033[37m",regs -> a7,regs -> a0,regs -> a1,regs -> a2,regs -> a3,regs -> a4,regs -> a5,regs -> a6); + regs -> a0 = syscallfunc(regs -> a0,regs -> a1,regs -> a2,regs -> a3,regs -> a4,regs -> a5,regs -> a6); + regs -> a7 = 0; + regs -> epc += 4;//skip ecall instruction + LOG_I("\033[36msyscall deal ok,ret = 0x%p\n\033[37m",regs -> a0); +} diff --git a/libcpu/risc-v/virt64/tick.c b/libcpu/risc-v/virt64/tick.c new file mode 100644 index 0000000000000000000000000000000000000000..8fdbe0809f465bf3ac0a2573b09ff959ee513c10 --- /dev/null +++ b/libcpu/risc-v/virt64/tick.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + */ + +#include +#include + +#include +#include "sbi.h" + +static volatile uint64_t time_elapsed = 0; +static volatile unsigned long tick_cycles = 0; + +static uint64_t get_ticks() +{ + __asm__ __volatile__( + "rdtime %0" + : "=r"(time_elapsed)); + return time_elapsed; +} + +int tick_isr(void) +{ + // uint64_t core_id = current_coreid(); + int tick_cycles = 40000; + // clint->mtimecmp[core_id] += tick_cycles; + rt_tick_increase(); + sbi_set_timer(get_ticks() + tick_cycles); + + return 0; +} + +/* Sets and enable the timer interrupt */ +int rt_hw_tick_init(void) +{ + /* Read core id */ + // unsigned long core_id = current_coreid(); + unsigned long interval = 1000/RT_TICK_PER_SECOND; + + /* Clear the Supervisor-Timer bit in SIE */ + clear_csr(sie, SIP_STIP); + + /* calculate the tick cycles */ + // tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1; + tick_cycles = 40000; + /* Set timer */ + sbi_set_timer(get_ticks() + tick_cycles); + + /* Enable the Supervisor-Timer bit in SIE */ + set_csr(sie, SIP_STIP); + + return 0; +} diff --git a/libcpu/risc-v/virt64/tick.h b/libcpu/risc-v/virt64/tick.h new file mode 100644 index 0000000000000000000000000000000000000000..0bfd6f62e885acec99f3f95d55754d7824fb3e8c --- /dev/null +++ b/libcpu/risc-v/virt64/tick.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + */ + +#ifndef TICK_H__ +#define TICK_H__ + +int tick_isr(void); +int rt_hw_tick_init(void); + +#endif diff --git a/libcpu/x86/SConscript b/libcpu/x86/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..01afd9a24eef4c92c317509029391d59602a2033 --- /dev/null +++ b/libcpu/x86/SConscript @@ -0,0 +1,20 @@ +# RT-Thread building script for bridge +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# add common code files +if rtconfig.CPU == "i386" : + group = group +else : + group = group + SConscript(os.path.join(cwd, 'common', 'SConscript')) + +# cpu porting code files +group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript')) + +Return('group') \ No newline at end of file diff --git a/libcpu/x86/i386/SConscript b/libcpu/x86/i386/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..b0ae20ba0298e00e05eba2ddc73df9424d22ec79 --- /dev/null +++ b/libcpu/x86/i386/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/x86/i386/backtrace.c b/libcpu/x86/i386/backtrace.c new file mode 100644 index 0000000000000000000000000000000000000000..f93a08e9dcffffd74560eda0f38f8dcbf35b4434 --- /dev/null +++ b/libcpu/x86/i386/backtrace.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-28 JasonHu first version + */ + +#include +#include + +static int rt_hw_backtrace(void **buffer, int size) +{ + int i = 0; + int n = 0; + unsigned int _ebp = 0; + unsigned int _eip = 0; + __asm__ __volatile__(" movl %%ebp, %0" :"=g" (_ebp)::"memory"); + for(i = 0; i < size && _ebp != 0 && *(unsigned int*)_ebp != 0 && + *(unsigned int *)_ebp != _ebp; i++) { + _eip = (unsigned int)((unsigned int*)_ebp + 1); + _eip = *(unsigned int*)_eip; + _ebp = *(unsigned int*)_ebp; + buffer[i] = (void*)_eip; + n++; + } + return n; +} + +void rt_hw_print_backtrace(void) +{ + void *buf[BACKTRACE_CNT] = {RT_NULL}; + int cnt = rt_hw_backtrace(buf, BACKTRACE_CNT); + rt_kprintf("[!] Call backtrace:\n"); + int i; + for (i = 0; i < cnt; i++) + { + rt_kprintf("%d: call %p\n", i, buf[i]); + } + rt_kprintf("[!] Call backtrace done.\n"); +} diff --git a/libcpu/x86/i386/backtrace.h b/libcpu/x86/i386/backtrace.h new file mode 100644 index 0000000000000000000000000000000000000000..bc4d686bf9bac1a933359a9db6d4092963b2d3e8 --- /dev/null +++ b/libcpu/x86/i386/backtrace.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-28 JasonHu first version + */ + +#ifndef __HW_BACKTRACE_H__ +#define __HW_BACKTRACE_H__ + +#define BACKTRACE_CNT 10 +void rt_hw_print_backtrace(void); + +#endif /* __HW_BACKTRACE_H__ */ diff --git a/libcpu/x86/i386/bitmap.c b/libcpu/x86/i386/bitmap.c new file mode 100644 index 0000000000000000000000000000000000000000..f0399dd4c00266cceda8f907bde4bb2a5b22ab7e --- /dev/null +++ b/libcpu/x86/i386/bitmap.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 JasonHu First Version + */ + +#include +#include +#include + +void rt_bitmap_init(rt_bitmap_t *bitmap, uint8_t *bits, rt_size_t byte_len) +{ + bitmap->bits = bits; + bitmap->byte_length = byte_len; + memset(bitmap->bits, 0, bitmap->byte_length); +} + +static rt_bool_t rt_bitmap_test(rt_bitmap_t *bitmap, rt_ubase_t index) +{ + rt_ubase_t byte_idx = index / 8; + rt_ubase_t bit_odd = index % 8; + return (bitmap->bits[byte_idx] & (RT_BITMAP_MASK << bit_odd)); +} + +rt_base_t rt_bitmap_scan(rt_bitmap_t *bitmap, rt_size_t count) +{ + if (!bitmap || !count) + { + return -1; + } + + rt_ubase_t idx_byte = 0; + + while ((0xff == bitmap->bits[idx_byte]) && (idx_byte < bitmap->byte_length)) + { + idx_byte++; + } + + if (idx_byte == bitmap->byte_length) /* out of array range */ + { + return -1; + } + + rt_base_t idx_bit = 0; + + while ((rt_uint8_t)(RT_BITMAP_MASK << idx_bit) & bitmap->bits[idx_byte]) + { + idx_bit++; + } + + rt_base_t idx_start = idx_byte * 8 + idx_bit; + if (count == 1) + { + return idx_start; + } + + rt_ubase_t bit_left = (bitmap->byte_length * 8 - idx_start); + rt_ubase_t next_bit = idx_start + 1; + rt_ubase_t ret_count = 1; + + idx_start = -1; + while (bit_left-- > 0) + { + if (!(rt_bitmap_test(bitmap, next_bit))) + { + ret_count++; + } + else + { + ret_count = 0; /* no consecutive bits, reset count */ + } + + if (ret_count == count) + { + idx_start = next_bit - ret_count + 1; + break; + } + next_bit++; + } + return idx_start; +} + +void rt_bitmap_set(rt_bitmap_t *bitmap, rt_ubase_t index, rt_bool_t value) +{ + rt_ubase_t byte_idx = index / 8; + rt_ubase_t bit_odd = index % 8; + + if (value) { + bitmap->bits[byte_idx] |= (RT_BITMAP_MASK << bit_odd); + } else { + bitmap->bits[byte_idx] &= ~(RT_BITMAP_MASK << bit_odd); + } +} + +rt_bool_t rt_bitmap_change(rt_bitmap_t *bitmap, rt_ubase_t index) +{ + rt_ubase_t byte_idx = index / 8; + rt_ubase_t bit_odd = index % 8; + + bitmap->bits[byte_idx] ^= (RT_BITMAP_MASK << bit_odd); /* xor */ + return (bitmap->bits[byte_idx] & (RT_BITMAP_MASK << bit_odd)); +} + +rt_bool_t rt_bitmap_test_and_change(rt_bitmap_t *bitmap, rt_ubase_t index) +{ + rt_ubase_t byte_idx = index / 8; + rt_ubase_t bit_odd = index % 8; + + rt_bool_t ret = (rt_bool_t) bitmap->bits[byte_idx] & (RT_BITMAP_MASK << bit_odd); + + bitmap->bits[byte_idx] ^= (RT_BITMAP_MASK << bit_odd); /* xor */ + return ret; +} diff --git a/libcpu/x86/i386/bitmap.h b/libcpu/x86/i386/bitmap.h new file mode 100644 index 0000000000000000000000000000000000000000..7c480d7dc89e4f106458f05a14ba0fc940af9f65 --- /dev/null +++ b/libcpu/x86/i386/bitmap.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 JasonHu first version + */ + +#ifndef __RT_BITMAP_H__ +#define __RT_BITMAP_H__ + +#include + +#define RT_BITMAP_MASK 1UL + +/** + * rt_bitmap structure + */ +struct rt_bitmap +{ + rt_size_t byte_length; /**< rt_bitmap size in byte. */ + rt_uint8_t *bits; /**< rt_bitmap bits base addr. */ +}; +typedef struct rt_bitmap rt_bitmap_t; + +void rt_bitmap_init(rt_bitmap_t *bitmap, uint8_t *bits, rt_size_t byte_len); +rt_base_t rt_bitmap_scan(rt_bitmap_t *bitmap, rt_size_t count); +void rt_bitmap_set(rt_bitmap_t *bitmap, rt_ubase_t index, rt_bool_t value); +rt_bool_t rt_bitmap_change(rt_bitmap_t *bitmap, rt_ubase_t index); +rt_bool_t rt_bitmap_test_and_change(rt_bitmap_t *bitmap, rt_ubase_t index); + +#endif /* __RT_BITMAP_H__ */ diff --git a/libcpu/x86/i386/boot_module.c b/libcpu/x86/i386/boot_module.c new file mode 100644 index 0000000000000000000000000000000000000000..f637a83a5df11bdfbec0c5cf4704b329b00efcd2 --- /dev/null +++ b/libcpu/x86/i386/boot_module.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-15 JasonHu,GUI first version + */ + +#include "boot_module.h" +#include "multiboot2.h" +#include + +static void boot_module_init(struct multiboot_tag *tag) +{ + struct boot_modules_info_block *modules_info = (struct boot_modules_info_block *)BOOT_MODULE_INFO_ADDR; + int index = modules_info->modules_num; + + if (index >= MAX_BOOT_MODULES_NUM + || modules_info->modules_size + ((struct multiboot_tag_module *)tag)->size > MAX_BOOT_MODULES_SIZE) + { + return; + } + + modules_info->modules[index].size = ((struct multiboot_tag_module *)tag)->size; + modules_info->modules[index].start = ((struct multiboot_tag_module *)tag)->mod_start; + modules_info->modules[index].end = ((struct multiboot_tag_module *)tag)->mod_end; + modules_info->modules[index].type = BOOT_MODULE_UNKNOWN; + + modules_info->modules_size += modules_info->modules[index].size; + ++modules_info->modules_num; +} + +static void boot_memory_init(struct multiboot_tag *tag) +{ + unsigned long mem_upper = ((struct multiboot_tag_basic_meminfo *)tag)->mem_upper; + unsigned long mem_lower = ((struct multiboot_tag_basic_meminfo *)tag)->mem_lower; + // memory size store in 0x000001000 + *((unsigned int *)0x000001000) = ((mem_upper - mem_lower) << 10) + 0x100000; +} + +int rt_boot_setup_entry(unsigned long magic, unsigned long addr) +{ + // whether a multiboot + if (magic != MULTIBOOT2_BOOTLOADER_MAGIC || addr & 7) + return -1; + struct multiboot_tag *tag; + + boot_module_info_init(); + + for (tag = (struct multiboot_tag*)(addr + 8); tag->type != MULTIBOOT_TAG_TYPE_END; \ + tag = (struct multiboot_tag*)((rt_uint8_t *)tag + ((tag->size + 7) & ~7))) + { + switch (tag->type) + { + case MULTIBOOT_TAG_TYPE_MODULE: + boot_module_init(tag); + break; + case MULTIBOOT_TAG_TYPE_BASIC_MEMINFO: + boot_memory_init(tag); + break; + default: // other type, do nothing + break; + } + } + return 0; +} diff --git a/libcpu/x86/i386/boot_module.h b/libcpu/x86/i386/boot_module.h new file mode 100644 index 0000000000000000000000000000000000000000..8bc880ab491f6d0d63cae58041fa68b03c5f7d4c --- /dev/null +++ b/libcpu/x86/i386/boot_module.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-15 JasonHu,GuEe-GUI first version + */ + +#ifndef __BOOT_MODULE_H__ +#define __BOOT_MODULE_H__ + +#include + +#define BOOT_MODULE_INFO_ADDR 0x3F1000 + +#define SIZE_MB (1024*1024) +#define MAX_BOOT_MODULES_NUM 1 +#define MAX_BOOT_MODULES_SIZE (1 * SIZE_MB) + +enum boot_module_type +{ + // Unknown type + BOOT_MODULE_UNKNOWN = 0, +}; + +struct boot_modules_info_block +{ + rt_uint32_t modules_num; + rt_uint32_t modules_size; + struct { + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t start; + rt_uint32_t end; + } modules[MAX_BOOT_MODULES_NUM]; +} __attribute__((packed)); + +rt_inline void boot_module_info_init() +{ + struct boot_modules_info_block *modules_info = (struct boot_modules_info_block *)BOOT_MODULE_INFO_ADDR; + modules_info->modules_num = 0; + modules_info->modules_size = 0; +} + +rt_inline void *boot_module_info_find(unsigned long base_addr, enum boot_module_type type) +{ + int i; + struct boot_modules_info_block *modules_info; + modules_info = (struct boot_modules_info_block *)(base_addr + BOOT_MODULE_INFO_ADDR); + + for (i = 0; i < modules_info->modules_num; ++i) + { + if (modules_info->modules[i].type == type) + { + return (void*)(base_addr + modules_info->modules[i].start); + } + } + return (void*)0; +} + +#endif /* __BOOT_MODULE_H__ */ diff --git a/libcpu/x86/i386/cache.c b/libcpu/x86/i386/cache.c new file mode 100644 index 0000000000000000000000000000000000000000..cb36fdd4d135fb18618689e16f8f12a1244dc566 --- /dev/null +++ b/libcpu/x86/i386/cache.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-14 JasonHu first version + */ + +#include +#include + +#include "cache.h" + +void rt_hw_cpu_icache_invalidate(void *addr,int size) +{ + +} + +void rt_hw_cpu_dcache_invalidate(void *addr,int size) +{ + +} + +void rt_hw_cpu_dcache_clean(void *addr,int size) +{ + +} + +void rt_hw_cpu_icache_ops(int ops,void *addr,int size) +{ + +} + +void rt_hw_cpu_dcache_ops(int ops,void *addr,int size) +{ + +} + +void rt_hw_cpu_dcache_flush_all() +{ + +} + +void rt_hw_cpu_icache_invalidate_all() +{ + +} + +rt_base_t rt_hw_cpu_icache_status() +{ + return 0; +} + +rt_base_t rt_hw_cpu_dcache_status() +{ + return 0; +} + +int sys_cacheflush(void *addr, int size, int cache) +{ + return 0; +} diff --git a/libcpu/x86/i386/cache.h b/libcpu/x86/i386/cache.h new file mode 100644 index 0000000000000000000000000000000000000000..273adea2842a311024c5d045f8ef584c4499486a --- /dev/null +++ b/libcpu/x86/i386/cache.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-7-19 JasonHu The first version + */ + +#ifndef __CACHE_H__ +#define __CACHE_H__ + +#include + +rt_inline rt_uint32_t rt_cpu_icache_line_size() +{ + return 0; +} + +rt_inline rt_uint32_t rt_cpu_dcache_line_size() +{ + return 0; +} + +void rt_hw_cpu_icache_invalidate(void *addr,int size); +void rt_hw_cpu_dcache_invalidate(void *addr,int size); +void rt_hw_cpu_dcache_clean(void *addr,int size); +void rt_hw_cpu_icache_ops(int ops,void *addr,int size); +void rt_hw_cpu_dcache_ops(int ops,void *addr,int size); +void rt_hw_cpu_dcache_flush_all(); +void rt_hw_cpu_icache_invalidate_all(); +rt_base_t rt_hw_cpu_icache_status(); +rt_base_t rt_hw_cpu_dcache_status(); + +#endif /* __CACHE_H__ */ diff --git a/libcpu/x86/i386/context_gcc.S b/libcpu/x86/i386/context_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..bf49dc1adcea9cb3192377713950666f40e68188 --- /dev/null +++ b/libcpu/x86/i386/context_gcc.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021/07/14 JasonHu First version + */ + +#define __ASSEMBLY__ +#include + +.code32 +.text + +/* + * void rt_hw_context_switch_to_real(rt_ubase_t to); + */ +.globl rt_hw_context_switch_to_real +rt_hw_context_switch_to_real: + movl 0x4(%esp), %eax // get thread "to" + movl (%eax), %esp // restore sp + + popl %ebp + popl %ebx + popl %edi + popl %esi + ret + +/* + * void rt_hw_context_switch_real(rt_ubase_t from, rt_ubase_t to); + */ +.globl rt_hw_context_switch_real +rt_hw_context_switch_real: + pushl %esi + pushl %edi + pushl %ebx + pushl %ebp + + movl 0x14(%esp), %eax // get "from" + movl %esp, (%eax) // save sp + + movl 0x18(%esp), %eax // get "to" + movl (%eax), %esp // restore sp + + popl %ebp + popl %ebx + popl %edi + popl %esi + ret diff --git a/libcpu/x86/i386/cpuport.c b/libcpu/x86/i386/cpuport.c new file mode 100644 index 0000000000000000000000000000000000000000..98e55fa6f394ee86e215520264f245a47d6c8dd1 --- /dev/null +++ b/libcpu/x86/i386/cpuport.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-14 JasonHu First Version + */ + +#include +#include +#include +#include + +#include "cpuport.h" +#include "tss.h" +#include "segment.h" +#include "gate.h" +#include "stackframe.h" +#include "page.h" +#include "mmu.h" +#include +#include +#include + +/** + * @brief from thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_from_thread = 0; +/** + * @brief to thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_to_thread = 0; +/** + * @brief flag to indicate context switch in interrupt or not + * + */ +volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; + +extern void rt_hw_context_switch_to_real(rt_ubase_t to); +extern void rt_hw_context_switch_real(rt_ubase_t from, rt_ubase_t to); + +/** + * any thread will come here when first start + */ +static void rt_hw_thread_entry(hw_thread_func_t function, void *arg, void (*texit)()) +{ + rt_hw_interrupt_enable(EFLAGS_IF); /* enable interrupt, avoid not sched */ + function(arg); + if (texit) + texit(); + dbg_log(DBG_ERROR, "rt thread execute done, should never be here!"); + for (;;) + { + } +} + +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + rt_uint8_t *stk; + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, sizeof(rt_ubase_t)); + stk -= sizeof(struct rt_hw_stack_frame); + stk -= sizeof(rt_hw_context_t); + + rt_hw_context_t *context = (rt_hw_context_t *)stk; + context->eip = rt_hw_thread_entry; + context->function = tentry; + context->arg = parameter; + context->texit = texit; + context->ebp = context->ebx = context->esi = context->edi = 0; + return stk; +} + +void rt_hw_context_switch_to(rt_ubase_t to) +{ + rt_thread_t to_thread = rt_thread_sp_to_thread((void *)to); + +#ifdef RT_USING_USERSPACE + /** + * update kernel esp0 as to thread's kernel stack, to make sure process can't + * get the correct kernel stack from tss esp0 when interrupt occur in user mode. + */ + rt_ubase_t stacktop = (rt_ubase_t)(to_thread->stack_addr + to_thread->stack_size); + rt_hw_tss_set_kstacktop(stacktop); + lwp_mmu_switch(to_thread); /* switch mmu before switch context */ +#endif /* RT_USING_USERSPACE */ + rt_hw_context_switch_to_real(to); +} + +void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) +{ + rt_thread_t from_thread = rt_thread_sp_to_thread((void *)from); + rt_thread_t to_thread = rt_thread_sp_to_thread((void *)to); + +#ifdef RT_USING_LWP + lwp_user_setting_save(from_thread); +#endif /* RT_USING_LWP */ + +#ifdef RT_USING_USERSPACE + /** + * update kernel esp0 as to thread's kernel stack, to make sure process can't + * get the correct kernel stack from tss esp0 when interrupt occur in user mode. + */ + rt_ubase_t stacktop = (rt_ubase_t)(to_thread->stack_addr + to_thread->stack_size); + rt_hw_tss_set_kstacktop(stacktop); + lwp_mmu_switch(to_thread); /* switch mmu before switch context */ +#endif /* RT_USING_USERSPACE */ + + rt_hw_context_switch_real(from, to); + +#ifdef RT_USING_LWP + lwp_user_setting_restore(to_thread); +#endif /* RT_USING_LWP */ +} + +/** + * when called rt_hw_context_switch_interrupt, just set from and to thread stack. + * when interrupt leave, we check rt_thread_switch_interrupt_flag. if it's 1, we + * will set rt_thread_switch_interrupt_flag as 0 then do context switch. + * see interrupt_gcc.S on lable rt_hw_intr_thread_switch. + */ +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + return; +} + +void rt_hw_cpu_shutdown() +{ +} + +void rt_hw_cpu_init() +{ + rt_hw_segment_init(); + rt_hw_gate_init(); + rt_hw_tss_init(); +} diff --git a/libcpu/x86/i386/cpuport.h b/libcpu/x86/i386/cpuport.h new file mode 100644 index 0000000000000000000000000000000000000000..a718da3d28ca03ebdeab30988739696c0934b9f1 --- /dev/null +++ b/libcpu/x86/i386/cpuport.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-7-14 JasonHu The first version + */ + +#ifndef __CPUPORT_H__ +#define __CPUPORT_H__ + +#include +#include + +#ifndef __ASSEMBLY__ + +/* write memory */ +rt_inline void rt_hw_dsb(void) +{ + asm volatile ("sfence": : :"memory"); +} + +/* read memory */ +rt_inline void rt_hw_dmb(void) +{ + asm volatile ("lfence": : :"memory"); +} + +/* instruction */ +rt_inline void rt_hw_isb(void) +{ + asm volatile ("": : :"memory"); +} + +#endif /* __ASSEMBLY__ */ + +void rt_hw_cpu_init(); + +#endif /* __CPUPORT_H__ */ diff --git a/libcpu/x86/i386/dma.c b/libcpu/x86/i386/dma.c new file mode 100644 index 0000000000000000000000000000000000000000..e8f4bb2a2514687495f3b932ae8853c5a20373de --- /dev/null +++ b/libcpu/x86/i386/dma.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 JasonHu First Version + */ + +#include +#include +#include +#include +#include +#include + +/** + * dma is physical addr + */ +struct rt_hw_dma_manager +{ + rt_ubase_t start; + rt_ubase_t end; + rt_bitmap_t bitmap; +}; +typedef struct rt_hw_dma_manager rt_hw_dma_manager_t; + +static rt_hw_dma_manager_t g_dma_manager; + +rt_err_t rt_hw_dma_init(rt_ubase_t start, rt_ubase_t end) +{ + g_dma_manager.start = start; + g_dma_manager.end = end; + rt_size_t pages = (end - start) / ARCH_PAGE_SIZE; + RT_ASSERT(pages > 0); + rt_size_t byte_len = pages / 8; + rt_uint8_t *bits = rt_malloc(byte_len); + if (!bits) + { + return RT_ENOMEM; + } + rt_kprintf("dma: range:%x~%x, pages:%d, bitmap bits:%x, byte_len:0x%x\n", + start, end, pages, bits, byte_len); + rt_bitmap_init(&g_dma_manager.bitmap, bits, byte_len); + + return RT_EOK; +} + +static rt_ubase_t dma_alloc_pages(rt_size_t npages) +{ + rt_base_t off = rt_bitmap_scan(&g_dma_manager.bitmap, npages); + if (off < 0) + { + return 0; + } + int i; + for (i = 0; i < npages; i++) + { + rt_bitmap_set(&g_dma_manager.bitmap, off + i, 1); + } + return (rt_ubase_t) (g_dma_manager.start + off * ARCH_PAGE_SIZE); +} + +static void dma_free_pages(rt_ubase_t addr, rt_size_t npages) +{ + rt_ubase_t start_idx = (addr - g_dma_manager.start) / ARCH_PAGE_SIZE; + int i; + for (i = 0; i < npages; i++) + { + rt_bitmap_set(&g_dma_manager.bitmap, start_idx + i, 0); + } +} + +rt_err_t rt_hw_dma_alloc(rt_hw_dma_t *dma) +{ + if (!dma->size) + { + return RT_EINVAL; + } + int npages = (dma->size + (ARCH_PAGE_SIZE - 1)) / ARCH_PAGE_SIZE; + dma->paddr = dma_alloc_pages(npages); + if(dma->paddr == 0) + { + return RT_ENOMEM; + } + + dma->vaddr = rt_hw_phy2vir(dma->paddr); + rt_memset((void *)dma->vaddr, 0, npages * ARCH_PAGE_SIZE); + return RT_EOK; +} + +rt_err_t rt_hw_dma_free(rt_hw_dma_t *dma) +{ + if (!dma->size || !dma->paddr || !dma->vaddr) + return RT_EINVAL; + + dma_free_pages(dma->paddr, (dma->size + (ARCH_PAGE_SIZE - 1)) / ARCH_PAGE_SIZE); + dma->paddr = dma->vaddr = 0; + return RT_EOK; +} diff --git a/libcpu/x86/i386/dma.h b/libcpu/x86/i386/dma.h new file mode 100644 index 0000000000000000000000000000000000000000..e6b47b0936430eeb418e09ceee90db9948cca719 --- /dev/null +++ b/libcpu/x86/i386/dma.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 JasonHu First Version + */ + +#ifndef __HW_DMA_H__ +#define __HW_DMA_H__ + +#include + +struct rt_hw_dma +{ + rt_ubase_t paddr; + rt_ubase_t vaddr; + rt_size_t size; + rt_ubase_t alignment; /* addr align */ +}; +typedef struct rt_hw_dma rt_hw_dma_t; + +rt_err_t rt_hw_dma_alloc(rt_hw_dma_t *dma); +rt_err_t rt_hw_dma_free(rt_hw_dma_t *dma); +rt_err_t rt_hw_dma_init(rt_ubase_t start, rt_ubase_t end); + +#endif /* __HW_DMA_H__ */ diff --git a/libcpu/x86/i386/gate.c b/libcpu/x86/i386/gate.c new file mode 100644 index 0000000000000000000000000000000000000000..59536ddfe91d80e32dfa3f13d97f0314b096e267 --- /dev/null +++ b/libcpu/x86/i386/gate.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 JasonHu first version + */ + +#include "gate.h" +#include "segment.h" +#include "interrupt.h" +#include + +struct rt_hw_gate +{ + rt_uint16_t offset_low, selector; + rt_uint8_t datacount; + rt_uint8_t attributes; /* P(1) DPL(2) DT(1) TYPE(4) */ + rt_uint16_t offset_high; +}; +typedef struct rt_hw_gate rt_hw_gate_t; + +typedef void (*rt_hw_intr_entry_t)(void); + +extern void rt_hw_intr_entry0x00(void); +extern void rt_hw_intr_entry0x01(void); +extern void rt_hw_intr_entry0x02(void); +extern void rt_hw_intr_entry0x03(void); +extern void rt_hw_intr_entry0x04(void); +extern void rt_hw_intr_entry0x05(void); +extern void rt_hw_intr_entry0x06(void); +extern void rt_hw_intr_entry0x07(void); +extern void rt_hw_intr_entry0x08(void); +extern void rt_hw_intr_entry0x09(void); +extern void rt_hw_intr_entry0x0a(void); +extern void rt_hw_intr_entry0x0b(void); +extern void rt_hw_intr_entry0x0c(void); +extern void rt_hw_intr_entry0x0d(void); +extern void rt_hw_intr_entry0x0e(void); +extern void rt_hw_intr_entry0x0f(void); +extern void rt_hw_intr_entry0x10(void); +extern void rt_hw_intr_entry0x11(void); +extern void rt_hw_intr_entry0x12(void); +extern void rt_hw_intr_entry0x13(void); +extern void rt_hw_intr_entry0x14(void); +extern void rt_hw_intr_entry0x15(void); +extern void rt_hw_intr_entry0x16(void); +extern void rt_hw_intr_entry0x17(void); +extern void rt_hw_intr_entry0x18(void); +extern void rt_hw_intr_entry0x19(void); +extern void rt_hw_intr_entry0x1a(void); +extern void rt_hw_intr_entry0x1b(void); +extern void rt_hw_intr_entry0x1c(void); +extern void rt_hw_intr_entry0x1d(void); +extern void rt_hw_intr_entry0x1e(void); +extern void rt_hw_intr_entry0x1f(void); + +extern void rt_hw_intr_entry0x20(void); +extern void rt_hw_intr_entry0x21(void); +extern void rt_hw_intr_entry0x22(void); +extern void rt_hw_intr_entry0x23(void); +extern void rt_hw_intr_entry0x24(void); +extern void rt_hw_intr_entry0x25(void); +extern void rt_hw_intr_entry0x26(void); +extern void rt_hw_intr_entry0x27(void); +extern void rt_hw_intr_entry0x28(void); +extern void rt_hw_intr_entry0x29(void); +extern void rt_hw_intr_entry0x2a(void); +extern void rt_hw_intr_entry0x2b(void); +extern void rt_hw_intr_entry0x2c(void); +extern void rt_hw_intr_entry0x2d(void); +extern void rt_hw_intr_entry0x2e(void); +extern void rt_hw_intr_entry0x2f(void); + +static void gate_set(rt_hw_gate_t *gate, rt_hw_intr_entry_t handler, + rt_uint32_t selector, rt_uint32_t attributes, rt_uint8_t privilege) +{ + rt_ubase_t offset = (rt_ubase_t) handler; + gate->offset_low = offset & 0xffff; + gate->selector = selector; + gate->attributes = attributes | (privilege << 5); + gate->datacount = 0; + gate->offset_high = (offset >> 16) & 0xffff; +} + +void rt_hw_gate_init(void) +{ + rt_hw_gate_t *idt = (rt_hw_gate_t *) (IDT_VADDR); + /* + 将中断描述符表的内容设置成内核下的中断门 + 并把汇编部分的中断处理函数传入进去 + */ + int i; + for (i = 0; i < MAX_IDT_NR; i++) { + gate_set(IDT_OFF2PTR(idt, i), 0, 0, 0, 0); + } + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE), rt_hw_intr_entry0x00, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+1), rt_hw_intr_entry0x01, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+2), rt_hw_intr_entry0x02, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+3), rt_hw_intr_entry0x03, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+4), rt_hw_intr_entry0x04, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+5), rt_hw_intr_entry0x05, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+6), rt_hw_intr_entry0x06, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+7), rt_hw_intr_entry0x07, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+8), rt_hw_intr_entry0x08, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+9), rt_hw_intr_entry0x09, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+10), rt_hw_intr_entry0x0a, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+11), rt_hw_intr_entry0x0b, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+12), rt_hw_intr_entry0x0c, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+13), rt_hw_intr_entry0x0d, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+14), rt_hw_intr_entry0x0e, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+15), rt_hw_intr_entry0x0f, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+16), rt_hw_intr_entry0x10, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+17), rt_hw_intr_entry0x11, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+18), rt_hw_intr_entry0x12, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+19), rt_hw_intr_entry0x13, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+20), rt_hw_intr_entry0x14, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+21), rt_hw_intr_entry0x15, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+22), rt_hw_intr_entry0x16, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+23), rt_hw_intr_entry0x17, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+24), rt_hw_intr_entry0x18, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+25), rt_hw_intr_entry0x19, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+26), rt_hw_intr_entry0x1a, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+27), rt_hw_intr_entry0x1b, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+28), rt_hw_intr_entry0x1c, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+29), rt_hw_intr_entry0x1d, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+30), rt_hw_intr_entry0x1e, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, EXCEPTION_INTR_BASE+31), rt_hw_intr_entry0x1f, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE), rt_hw_intr_entry0x20, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+1), rt_hw_intr_entry0x21, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+2), rt_hw_intr_entry0x22, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+3), rt_hw_intr_entry0x23, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+4), rt_hw_intr_entry0x24, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+5), rt_hw_intr_entry0x25, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+6), rt_hw_intr_entry0x26, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+7), rt_hw_intr_entry0x27, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+8), rt_hw_intr_entry0x28, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+9), rt_hw_intr_entry0x29, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+10), rt_hw_intr_entry0x2a, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+11), rt_hw_intr_entry0x2b, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+12), rt_hw_intr_entry0x2c, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+13), rt_hw_intr_entry0x2d, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+14), rt_hw_intr_entry0x2e, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + gate_set(IDT_OFF2PTR(idt, IRQ_INTR_BASE+15), rt_hw_intr_entry0x2f, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL0); + /* 系统调用处理中断 */ +#ifdef RT_USING_USERSPACE + extern void hw_syscall_entry(void); + gate_set(IDT_OFF2PTR(idt, SYSCALL_INTR_BASE), hw_syscall_entry, KERNEL_CODE_SEL, DA_386_INTR_GATE, DA_GATE_DPL3); +#endif /* RT_USING_USERSPACE */ + + extern void load_new_idt(rt_ubase_t size, rt_ubase_t idtr); + load_new_idt(IDT_LIMIT, IDT_VADDR); +} diff --git a/libcpu/x86/i386/gate.h b/libcpu/x86/i386/gate.h new file mode 100644 index 0000000000000000000000000000000000000000..b3fd706a1b72ab7bc81962ecd667cc7b98e91cab --- /dev/null +++ b/libcpu/x86/i386/gate.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 JasonHu first version + */ + +#ifndef __X86_GATE_H__ +#define __X86_GATE_H__ + +#include + +#define IDT_LIMIT 0x000007ff +#define IDT_PADDR 0x003F0800 + +#define IDT_VADDR (KERNEL_VADDR_START + IDT_PADDR) + +#define MAX_IDT_NR (IDT_LIMIT/8) + +#define IDT_OFF2PTR(idt, off) (idt + off) + +/* DA: Descriptor Attribute */ +#define DA_TASK_GATE 0x85 +#define DA_386_CALL_GATE 0x8C +#define DA_386_INTR_GATE 0x8E +#define DA_386_TRAP_GATE 0x8F + +#define DA_GATE_DPL0 0 +#define DA_GATE_DPL1 1 +#define DA_GATE_DPL2 2 +#define DA_GATE_DPL3 3 + +#ifndef __ASSEMBLY__ +void rt_hw_gate_init(void); +#endif + +#endif /* __X86_GATE_H__ */ diff --git a/libcpu/x86/i386/i386.h b/libcpu/x86/i386/i386.h new file mode 100644 index 0000000000000000000000000000000000000000..7a0a07f1b6037461285ddc60a281fed6d36f756c --- /dev/null +++ b/libcpu/x86/i386/i386.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-14 JasonHu first version + */ + +#ifndef __I386_H__ +#define __I386_H__ + +#include + +#define EFLAGS_MBS (1 << 1) +#define EFLAGS_IF_1 (1 << 9) +#define EFLAGS_IF_0 0 +#define EFLAGS_IOPL_3 (3 << 12) +#define EFLAGS_IOPL_1 (1 << 12) +#define EFLAGS_IOPL_0 (0 << 12) + +#define EFLAGS_IF (EFLAGS_IF_1) + +/* cr0 bit 31 is page enable bit, 1: enable MMU, 0: disable MMU */ +#define CR0_PG (1 << 31) + +rt_inline rt_uint8_t inb(int port) +{ + rt_uint8_t data; + __asm__ __volatile__("inb %w1,%0" : "=a" (data) : "d" (port)); + return data; +} + +rt_inline rt_uint16_t inw(int port) +{ + rt_uint16_t data; + __asm__ __volatile__("inw %w1,%0" : "=a" (data) : "d" (port)); + return data; +} + +rt_inline rt_uint32_t inl(int port) +{ + rt_uint32_t data; + __asm__ __volatile__("inl %w1,%0" : "=a" (data) : "d" (port)); + return data; +} + +rt_inline void outb(int port, rt_uint8_t data) +{ + __asm__ __volatile__("outb %0,%w1" : : "a" (data), "d" (port)); +} + +rt_inline void outw(int port, rt_uint16_t data) +{ + __asm__ __volatile__("outw %0,%w1" : : "a" (data), "d" (port)); +} + +rt_inline void outl(int port, rt_uint32_t data) +{ + __asm__ __volatile__("outl %0,%w1" : : "a" (data), "d" (port)); +} + +rt_inline rt_uint8_t read_cmos(int reg) +{ + outb(0x70, reg); + return (rt_uint8_t) inb(0x71); +} + +#define io_delay() \ + __asm__ __volatile__ ("pushal \n\t"\ + "mov $0x3F6, %dx \n\t" \ + "inb %dx, %al \n\t" \ + "inb %dx, %al \n\t" \ + "inb %dx, %al \n\t" \ + "inb %dx, %al \n\t" \ + "popal") + +rt_inline void ltr(rt_uint32_t selector) +{ + __asm__ __volatile__("ltr %w0" : : "q" (selector)); +} + +rt_uint32_t read_cr0(void); +rt_uint32_t read_cr2(void); +void write_cr0(rt_uint32_t value); +void write_cr3(rt_uint32_t pgdir); + +rt_inline void rt_hw_cpu_pause(void) +{ + __asm__ __volatile__ ("pause"); +} + +#endif /* __I386_H__ */ diff --git a/libcpu/x86/i386/interrupt.c b/libcpu/x86/i386/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..6f66c0daee0bc8fc81832a99c24eca649e71218f --- /dev/null +++ b/libcpu/x86/i386/interrupt.c @@ -0,0 +1,358 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-14 JasonHu first version + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef RT_USING_SIGNALS +#include +#endif /* RT_USING_SIGNALS */ + +enum HW_EXCEPTION_TYPE +{ + HW_EXCEPT_DIVIDE = 0, /* Division error: DIV and IDIV instructions */ + HW_EXCEPT_DEBUG, /* Debugging exceptions: access to any code and data */ + HW_EXCEPT_INTERRUPT, /* Unshielded interrupt: Unshielded external interrupt */ + HW_EXCEPT_BREAKPOINT, /* Debug breakpoint: instruction INT3 */ + HW_EXCEPT_OVERFLOW, /* Overflow: instruction INTO */ + HW_EXCEPT_BOUND_RANGE, /* Out of bounds: command BOUND */ + HW_EXCEPT_INVALID_OPCODE, /* Invalid (undefined) opcode: + instruction UD2 or invalid instruction */ + HW_EXCEPT_DEVICE_NOT_AVAILABLE, /* Device unavailable (no math processor): + floating point or WAIT/FWAIT instructions */ + HW_EXCEPT_DOUBLE_FAULT, /* Double error: all instructions that can generate an exception + or NMI or INTR */ + HW_EXCEPT_COPROCESSOR_SEGMENT_OVERRUN, /* Assist the processor segment to cross the boundary: + floating-point instructions (IA32 processors after 386 + no longer generate such exceptions) */ + HW_EXCEPT_INVALID_TSS, /* Invalid TSS: When switching tasks or accessing TSS */ + HW_EXCEPT_SEGMENT_NOT_PRESENT, /* Segment does not exist: when loading segment registers + or accessing system segments */ + HW_EXCEPT_STACK_FAULT, /* Stack segmentation error: stack operation or loading SS */ + HW_EXCEPT_GENERAL_PROTECTION, /* General protection error: memory or other protection check */ + HW_EXCEPT_PAGE_FAULT, /* Page fault: memory access */ + HW_EXCEPT_RESERVED, /* INTEL reserved, not used */ + HW_EXCEPT_X87_FLOAT_POINT, /* X87FPU floating point error (math error): + X87FPU floating point instruction or WAIT/FWAIIT instruction */ + HW_EXCEPT_ALIGNMENT_CHECK, /* Alignment check: data access in memory (supported from 486) */ + HW_EXCEPT_MACHINE_CHECK, /* Machine Check: The error code (if any) and source + depend on the specific mode (Pentium CPU starts to support) */ + HW_EXCEPT_SIMD_FLOAT_POINT, /* SIMD floating-point exceptions: SSE and SSE2 floating-point + instructions (supported by Pentium III) */ +}; + +typedef void (*rt_hw_intr_handler_t)(rt_hw_stack_frame_t *); + +static rt_hw_intr_handler_t interrupt_handlers[MAX_INTR_NR] = {0}; +static struct rt_irq_desc irq_desc[MAX_IRQ_NR] = {0}; + +static char *hw_exception_names[] = { + "#DE Divide Error", + "#DB Debug Exception", + "NMI Interrupt", + "#BP Breakpoint Exception", + "#OF Overflow Exception", + "#BR BOUND Range Exceeded Exception", + "#UD Invalid Opcode Exception", + "#NM Device Not Available Exception", + "#DF Double Fault Exception", + "Coprocessor Segment Overrun", + "#TS Invalid TSS Exception", + "#NP Segment Not Present", + "#SS Stack Fault Exception", + "#GP General Protection Exception", + "#PF Page-Fault Exception", + "Reserved", + "#MF x87 FPU Floating-Point Error", + "#AC Alignment Check Exception", + "#MC Machine-Check Exception", + "#XF SIMD Floating-Point Exception", + "Unknown Exception" +}; + +static void exception_frame_dump(rt_hw_stack_frame_t *frame); + +static void rt_hw_interrupt_handle(int vector, void *param) +{ + rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector); +} + +static void hw_general_handler(rt_hw_stack_frame_t *frame) +{ + rt_kprintf("general intr %d handled\n", frame->vec_no); +} + +static void hw_external_handler(rt_hw_stack_frame_t *frame) +{ + int irqno = frame->vec_no - IRQ_INTR_BASE; + if (irqno < 0 || irqno >= MAX_IRQ_NR) + { + dbg_log(DBG_ERROR, "unknown IRQ %d occurred!!\n", irqno); + return; + } + irq_desc[irqno].handler(irqno, irq_desc[irqno].param); + rt_hw_pic_ack(irqno); +} + +#ifdef RT_USING_LWP +static int check_user_stack(rt_hw_stack_frame_t *frame) +{ + if (frame->vec_no == EXCEPTION_PAGE_FAULT) + { + void *fault_addr = (void *)read_cr2(); // get page fault addr + rt_interrupt_leave(); + if (arch_expand_user_stack(fault_addr)) + { + rt_interrupt_enter(); + return 1; + } + rt_interrupt_enter(); + } + return 0; +} +#endif /* RT_USING_LWP */ + +static void hw_exception_handler(rt_hw_stack_frame_t *frame) +{ +#ifdef RT_USING_LWP + if (check_user_stack(frame)) + return; +#endif /* RT_USING_LWP */ + rt_thread_t cur = rt_thread_self(); + rt_kprintf("thread name: %s\n", cur->name); + +#ifdef RT_USING_LWP + if (cur->lwp) + { + struct rt_lwp *lwp = cur->lwp; + rt_kprintf("thread id:%d\n", lwp->pid); + } +#endif /* RT_USING_LWP */ + + exception_frame_dump(frame); + rt_hw_print_backtrace(); + +#ifdef RT_USING_SIGNALS + dbg_log(DBG_ERROR, "[exception] send signal to thread %s\n", rt_thread_self()->name); + /* send signal to thread */ + switch (frame->vec_no) + { + case HW_EXCEPT_DIVIDE: + case HW_EXCEPT_INVALID_OPCODE: + lwp_thread_kill(rt_thread_self(), SIGILL); + return; + case HW_EXCEPT_DEVICE_NOT_AVAILABLE: + lwp_thread_kill(rt_thread_self(), SIGIO); + return; + case HW_EXCEPT_COPROCESSOR_SEGMENT_OVERRUN: + case HW_EXCEPT_X87_FLOAT_POINT: + case HW_EXCEPT_SIMD_FLOAT_POINT: + lwp_thread_kill(rt_thread_self(), SIGFPE); + return; + case HW_EXCEPT_OVERFLOW: + case HW_EXCEPT_BOUND_RANGE: + case HW_EXCEPT_INVALID_TSS: + case HW_EXCEPT_ALIGNMENT_CHECK: + lwp_thread_kill(rt_thread_self(), SIGBUS); + return; + case HW_EXCEPT_SEGMENT_NOT_PRESENT: + case HW_EXCEPT_GENERAL_PROTECTION: + lwp_thread_kill(rt_thread_self(), SIGSEGV); + return; + case HW_EXCEPT_STACK_FAULT: + lwp_thread_kill(rt_thread_self(), SIGSTKFLT); + return; + case HW_EXCEPT_MACHINE_CHECK: + case HW_EXCEPT_INTERRUPT: + lwp_thread_kill(rt_thread_self(), SIGINT); + return; + case HW_EXCEPT_DOUBLE_FAULT: + lwp_thread_kill(rt_thread_self(), SIGKILL); + return; + case HW_EXCEPT_DEBUG: + case HW_EXCEPT_BREAKPOINT: + lwp_thread_kill(rt_thread_self(), SIGTRAP); + return; + default: + break; + } +#endif + + /* unhandled exception */ + rt_hw_interrupt_disable(); + for (;;) + { + } +} + +rt_base_t rt_hw_interrupt_disable(void) +{ + rt_base_t level; + __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); + return level; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); +} + +void rt_hw_interrupt_dispatch(rt_hw_stack_frame_t *frame) +{ + rt_ubase_t vec_no = frame->vec_no; + if (vec_no < 0 || vec_no >= MAX_INTR_NR) + { + dbg_log(DBG_ERROR, "unknown intr vector %x!\n", frame->vec_no); + return; + } + interrupt_handlers[vec_no](frame); +} + +void rt_hw_stack_frame_dump(rt_hw_stack_frame_t *frame) +{ + rt_kprintf("edi:%x\nesi:%x\nebp:%x\nesp dummy:%x\nebx:%x\nedx:%x\necx:%x\neax:%x\n", + frame->edi, frame->esi, frame->ebp, frame->esp_dummy, + frame->ebx, frame->edx, frame->ecx, frame->eax); + rt_kprintf("gs:%x\nfs:%x\nes:%x\nds:%x\nerror code:%x\neip:%x\ncs:%x\neflags:%x\nesp:%x\nss:%x\n", + frame->gs, frame->fs, frame->es, frame->ds, frame->error_code, + frame->eip, frame->cs, frame->eflags, frame->esp, frame->ss); +} + +static void exception_frame_dump(rt_hw_stack_frame_t *frame) +{ + rt_kprintf("\n!!! Stack frame: exception name %s\n", hw_exception_names[frame->vec_no]); + if (frame->vec_no == 14) + { + rt_kprintf("page fault addr: %p\n", read_cr2()); + } + rt_hw_stack_frame_dump(frame); + if (frame->error_code != 0xFFFFFFFF) + { + if (frame->error_code & 1) + { + rt_kprintf(" External Event: NMI,hard interruption,ect.\n"); + } + else + { + rt_kprintf(" Not External Event: inside.\n"); + } + if (frame->error_code & (1 << 1)) + { + rt_kprintf(" IDT: selector in idt.\n"); + } + else + { + rt_kprintf(" IDT: selector in gdt or ldt.\n"); + } + if(frame->error_code & (1 <<2 )) + { + rt_kprintf(" TI: selector in ldt.\n"); + } + else + { + rt_kprintf(" TI: selector in gdt.\n"); + } + rt_kprintf(" Selector: idx %d\n", (frame->error_code&0xfff8)>>3); + } +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + rt_hw_pic_disable(vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + rt_hw_pic_enable(vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if(vector < MAX_IRQ_NR) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); + irq_desc[vector].counter = 0; +#endif + } + } + + return old_handler; +} + +extern volatile rt_ubase_t rt_interrupt_from_thread; +extern volatile rt_ubase_t rt_interrupt_to_thread; +extern volatile rt_ubase_t rt_thread_switch_interrupt_flag; +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; + int i; + for (i = 0; i < MAX_INTR_NR; i++) + { + if (i < IRQ_INTR_BASE) + { + interrupt_handlers[i] = hw_exception_handler; + } + else if (i >= IRQ_INTR_BASE && i < IRQ_INTR_BASE + MAX_IRQ_NR) + { + interrupt_handlers[i] = hw_external_handler; + } + else + { + interrupt_handlers[i] = hw_general_handler; + } + } + for (i = 0; i < MAX_IRQ_NR; i++) + { + irq_desc[i].handler = rt_hw_interrupt_handle; + irq_desc[i].param = RT_NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[i].name, RT_NAME_MAX - 1, "default"); + irq_desc[i].counter = 0; +#endif + } + /* init intr controller */ + rt_hw_pic_init(); +} diff --git a/libcpu/x86/i386/interrupt.h b/libcpu/x86/i386/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..b7207d309d83f944ab4c71ea3e623d5e35b7758c --- /dev/null +++ b/libcpu/x86/i386/interrupt.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 JasonHu first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#define MAX_INTR_NR 0x81 +#define EXCEPTION_INTR_BASE 0x00 +#define IRQ_INTR_BASE 0x20 +#define SYSCALL_INTR_BASE 0x80 + +#define MAX_IRQ_NR 16 + +#define EXCEPTION_PAGE_FAULT 14 + +#define IRQ0_CLOCK 0 +#define IRQ1_KEYBOARD 1 +#define IRQ2_CONNECT 2 /* connect to slave */ +#define IRQ3_SERIAL2 3 +#define IRQ4_SERIAL1 4 +#define IRQ5_PARALLEL2 5 +#define IRQ6_FLOPPY 6 +#define IRQ7_PARALLEL1 7 + +#define IRQ8_RTCLOCK 8 /* real-time clock */ +#define IRQ9_REDIRECT 9 /* redirect to IRQ2 */ +#define IRQ10_RESERVED 10 +#define IRQ11_RESERVED 11 +#define IRQ12_MOUSE 12 +#define IRQ13_FPU 13 +#define IRQ14_HARDDISK 14 +#define IRQ15_RESERVE 15 + +#include "i386.h" + +#endif /* __INTERRUPT_H__ */ diff --git a/libcpu/x86/i386/interrupt_gcc.S b/libcpu/x86/i386/interrupt_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..ddc70ccf9cbc860a841358e0c4e5b7c342a4940a --- /dev/null +++ b/libcpu/x86/i386/interrupt_gcc.S @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021/07/15 JasonHu The first version + */ +#define __ASSEMBLY__ +#include + +.code32 +.text + +.extern rt_interrupt_enter +.extern rt_interrupt_leave +.extern rt_thread_switch_interrupt_flag +.extern rt_interrupt_from_thread +.extern rt_interrupt_to_thread +.extern rt_hw_interrupt_dispatch +.extern rt_hw_context_switch + +// cpu no error code, need push by us +.macro rt_hw_intr_entry_push_errcode p1 +.global rt_hw_intr_entry\p1 +rt_hw_intr_entry\p1: + pushl $0x00 + + pushl %ds + pushl %es + pushl %fs + pushl %gs + + pushal + + movl %ss, %edx + movl %edx, %ds + movl %edx, %es + + pushl $\p1 + + call rt_interrupt_enter + pushl %esp + call rt_hw_interrupt_dispatch + addl $4, %esp + call rt_interrupt_leave + +#ifdef RT_USING_SIGNALS + // check signal and do signal + pushl %esp + call lwp_try_do_signal + addl $4, %esp +#endif /* RT_USING_SIGNALS */ + + /** + * if rt_thread_switch_interrupt_flag == 1 then + * jmp rt_hw_intr_thread_switch + * end + */ + movl $rt_thread_switch_interrupt_flag, %eax + movl (%eax), %ebx + cmp $0x1, %ebx + jz rt_hw_intr_thread_switch + + // jmp to exit + movl $rt_hw_intr_exit, %eax + jmp *%eax +.endm + +// cpu with error code +.macro rt_hw_intr_entry p1 +.global rt_hw_intr_entry\p1 +rt_hw_intr_entry\p1: + nop; + pushl %ds + pushl %es + pushl %fs + pushl %gs + + pushal + + movl %ss, %edx + movl %edx, %ds + movl %edx, %es + + pushl $\p1 + + call rt_interrupt_enter + pushl %esp; + call rt_hw_interrupt_dispatch + addl $4, %esp; + call rt_interrupt_leave + +#ifdef RT_USING_SIGNALS + // check signal and do signal + pushl %esp + call lwp_try_do_signal + addl $4, %esp +#endif /* RT_USING_SIGNALS */ + + /** + * if rt_thread_switch_interrupt_flag == 1 then + * jmp rt_hw_intr_thread_switch + * end + */ + movl $rt_thread_switch_interrupt_flag, %eax + movl (%eax), %ebx + cmp $0x1, %ebx + jz rt_hw_intr_thread_switch + + // jmp to exit + movl $rt_hw_intr_exit, %eax + jmp *%eax +.endm + +rt_hw_intr_entry_push_errcode 0x00 +rt_hw_intr_entry_push_errcode 0x01 +rt_hw_intr_entry_push_errcode 0x02 +rt_hw_intr_entry_push_errcode 0x03 +rt_hw_intr_entry_push_errcode 0x04 +rt_hw_intr_entry_push_errcode 0x05 +rt_hw_intr_entry_push_errcode 0x06 +rt_hw_intr_entry_push_errcode 0x07 +rt_hw_intr_entry 0x08 +rt_hw_intr_entry_push_errcode 0x09 +rt_hw_intr_entry 0x0a +rt_hw_intr_entry 0x0b +rt_hw_intr_entry_push_errcode 0x0c +rt_hw_intr_entry 0x0d +rt_hw_intr_entry 0x0e +rt_hw_intr_entry_push_errcode 0x0f +rt_hw_intr_entry_push_errcode 0x10 +rt_hw_intr_entry 0x11 +rt_hw_intr_entry_push_errcode 0x12 +rt_hw_intr_entry_push_errcode 0x13 +rt_hw_intr_entry_push_errcode 0x14 +rt_hw_intr_entry_push_errcode 0x15 +rt_hw_intr_entry_push_errcode 0x16 +rt_hw_intr_entry_push_errcode 0x17 +rt_hw_intr_entry 0x18 +rt_hw_intr_entry_push_errcode 0x19 +rt_hw_intr_entry 0x1a +rt_hw_intr_entry 0x1b +rt_hw_intr_entry_push_errcode 0x1c +rt_hw_intr_entry 0x1d +rt_hw_intr_entry 0x1e +rt_hw_intr_entry_push_errcode 0x1f +rt_hw_intr_entry_push_errcode 0x20 +rt_hw_intr_entry_push_errcode 0x21 +rt_hw_intr_entry_push_errcode 0x22 +rt_hw_intr_entry_push_errcode 0x23 +rt_hw_intr_entry_push_errcode 0x24 +rt_hw_intr_entry_push_errcode 0x25 +rt_hw_intr_entry_push_errcode 0x26 +rt_hw_intr_entry_push_errcode 0x27 +rt_hw_intr_entry_push_errcode 0x28 +rt_hw_intr_entry_push_errcode 0x29 +rt_hw_intr_entry_push_errcode 0x2a +rt_hw_intr_entry_push_errcode 0x2b +rt_hw_intr_entry_push_errcode 0x2c +rt_hw_intr_entry_push_errcode 0x2d +rt_hw_intr_entry_push_errcode 0x2e +rt_hw_intr_entry_push_errcode 0x2f +rt_hw_intr_entry_push_errcode 0x80 // syscall + +rt_hw_intr_thread_switch: + // set rt_thread_switch_interrupt_flag as 0 + movl $0x0, %ebx + movl %ebx, (%eax) + + // push to into stack + movl $rt_interrupt_to_thread, %eax // get "to" + movl (%eax), %ebx + + // push from into stack + movl $rt_interrupt_from_thread, %ecx // get "from" + movl (%ecx), %edx + + pushl %ebx + pushl %edx + call rt_hw_context_switch + addl $8, %esp // restore stack + + // jmp to exit + movl $rt_hw_intr_exit, %eax + jmp *%eax + +#ifdef RT_USING_USERSPACE + +.extern rt_hw_syscall_dispath + +#ifdef RT_USING_SIGNALS +.extern lwp_try_do_signal +#endif /* RT_USING_SIGNALS */ + +.global hw_syscall_entry +hw_syscall_entry: + pushl $0x00 + + pushl %ds + pushl %es + pushl %fs + pushl %gs + + pushal + + movl %ss, %edx + movl %edx, %ds + movl %edx, %es + + pushl $0x80 + + sti // enable interrupt + + pushl %esp + call rt_hw_syscall_dispath + addl $4, %esp + +#ifdef RT_USING_SIGNALS + // check signal and do signal + pushl %esp + call lwp_try_do_signal + addl $4, %esp +#endif /* RT_USING_SIGNALS */ + + cli // disable interrupt + + // jmp to exit + movl $rt_hw_intr_exit, %eax + jmp *%eax + +.global syscall_exit +syscall_exit: +#endif /* RT_USING_USERSPACE */ +.global rt_hw_intr_exit +rt_hw_intr_exit: + addl $4, %esp // skip intr no + + popal + + popl %gs + popl %fs + popl %es + popl %ds + + addl $4, %esp // skip error_code + + iret \ No newline at end of file diff --git a/libcpu/x86/i386/mmu.c b/libcpu/x86/i386/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..79a2b058d1761adfcfa4a4d409dc013c72270744 --- /dev/null +++ b/libcpu/x86/i386/mmu.c @@ -0,0 +1,681 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-14 JasonHu first version + */ + +#include +#include +#include +#include +#include + +#include "mmu.h" +#include "cache.h" +#include "i386.h" + +#ifdef RT_USING_USERSPACE +#include "page.h" +#endif /* RT_USING_USERSPACE */ + +// #define RT_DEBUG_MMU_X86 + +static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t npages); + +#ifdef RT_USING_USERSPACE +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr); +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr); +#else +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr); +#endif + +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size); +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr); + +void *current_mmu_table = RT_NULL; + +static void rt_hw_cpu_tlb_invalidate() +{ + mmu_flush_tlb(); +} + +void *mmu_table_get() +{ + return current_mmu_table; +} + +void switch_mmu(void *mmu_table) +{ + current_mmu_table = mmu_table; + if (mmu_table == RT_NULL) + { + dbg_log(DBG_ERROR, "switch_mmu: NULL mmu table!\n"); + } + else + { + RT_ASSERT(__CHECKALIGN(mmu_table,PAGE_OFFSET_BIT)); + mmu_set_pagetable((rt_ubase_t)mmu_table); + } +} + +/** + * init page table, check vaddr whether used. + */ +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info,void *v_address,rt_size_t size,rt_size_t *vtable,rt_size_t pv_off) +{ + size_t l1_off,va_s,va_e; + rt_base_t level; + + if((!mmu_info) || (!vtable)) + { + return -1; + } + + va_s = (rt_size_t)v_address; + va_e = ((rt_size_t)v_address) + size - 1; + + if(va_e < va_s) + { + dbg_log(DBG_ERROR, "end=%p lower than start=%p\n", va_e, va_s); + return -1; + } + + //convert address to level 1 page frame id + va_s = GET_L1(va_s); + va_e = GET_L1(va_e); + + if(va_s == 0) + { + return -1; + } + + level = rt_hw_interrupt_disable(); + + //vtable initialization check + for(l1_off = va_s;l1_off <= va_e;l1_off++) + { + size_t v = vtable[l1_off]; + + if(PTE_USED(v)) + { + rt_hw_interrupt_enable(level); + return -1; + } + } + + va_s = (rt_size_t)v_address; + va_e = ((rt_size_t)v_address) + size; + + mmu_info -> vtable = vtable; + mmu_info -> vstart = va_s; + mmu_info -> vend = va_e; + mmu_info -> pv_off = pv_off; + + rt_hw_interrupt_enable(level); + return 0; +} + +void rt_hw_mmu_kernel_map_init(rt_mmu_info *mmu_info,rt_size_t vaddr_start,rt_size_t size) +{ + vaddr_start = vaddr_start & PAGE_ADDR_MASK; + rt_size_t paddr_start = vaddr_start; + rt_size_t vaddr_end = vaddr_start + __ALIGNUP(size, PAGE_OFFSET_BIT); + + rt_kprintf("kernel: map on [%p~%p]\n", vaddr_start, vaddr_end); + pde_t *pdt = (pde_t *)mmu_info->vtable; + + rt_size_t pde_nr = (vaddr_end - vaddr_start) / (PTE_PER_PAGE * PAGE_SIZE); + rt_size_t pte_nr = ((vaddr_end - vaddr_start) / PAGE_SIZE) % PTE_PER_PAGE; + rt_size_t *pte_addr = (rt_size_t *) PAGE_TABLE_VADDR; + rt_size_t pde_off = GET_L1(vaddr_start); + int i, j; + for (i = 0; i < pde_nr; i++) + { + pdt[pde_off + i] = MAKE_PTE(pte_addr, KERNEL_PAGE_ATTR); + for (j = 0; j < PTE_PER_PAGE; j++) + { + pte_addr[j] = MAKE_PTE(paddr_start, KERNEL_PAGE_ATTR); + paddr_start += PAGE_SIZE; + } + pte_addr += PAGE_SIZE; + } + if (pte_nr > 0) + { + pdt[pde_off + i] = MAKE_PTE(pte_addr, KERNEL_PAGE_ATTR); + for (j = 0; j < pte_nr; j++) + { + pte_addr[j] = MAKE_PTE(paddr_start, KERNEL_PAGE_ATTR); + paddr_start += PAGE_SIZE; + } + } +} + +static int __rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t npages,rt_size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa = (size_t)p_addr & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + + if (!mmu_info) + { + return -1; + } + while (npages--) + { + l1_off = GET_L1(loop_va); + l2_off = GET_L2(loop_va); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + if(PTE_USED(*mmu_l1)) + { + mmu_l2 = ((size_t *)GET_PADDR(*mmu_l1)); + rt_page_ref_inc(mmu_l2, 0); /* mmu l2 ref inc when map */ + mmu_l2 += l2_off; + } + else + { + mmu_l2 = (size_t*)rt_pages_alloc(0); + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_SIZE); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_SIZE); + + *mmu_l1 = MAKE_PTE((size_t)mmu_l2, attr | PTE_P); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, sizeof(*mmu_l1)); + + mmu_l2 += l2_off; + } + else + { + /* error, unmap and quit */ + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; + } + } + *mmu_l2 = MAKE_PTE(loop_pa, attr | PTE_P); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, sizeof(*mmu_l2)); + + loop_va += ARCH_PAGE_SIZE; + loop_pa += ARCH_PAGE_SIZE; + } + return 0; +} + +#ifdef RT_USING_USERSPACE +//check whether the range of virtual address are free +static int check_vaddr(rt_mmu_info *mmu_info,void *va,rt_size_t pages) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)va,PAGE_OFFSET_MASK); + rt_size_t l1_off, l2_off; + rt_size_t *mmu_l1,*mmu_l2; + + if(!pages) + { + dbg_log(DBG_ERROR, "%s: check vaddr=%p pages=zero!\n", __func__, va); + return -1; + } + + if(!mmu_info) + { + dbg_log(DBG_ERROR, "%s: check vaddr=%p pages=%d mmu NULL!\n", __func__, va, pages); + return -1; + } + + while(pages--) + { + l1_off = GET_L1(loop_va); + l2_off = GET_L2(loop_va); + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + + if(PTE_USED(*mmu_l1)) + { + mmu_l2 = ((rt_size_t *)GET_PADDR(*mmu_l1)) + l2_off; + + if(PTE_USED(*mmu_l2)) + { + dbg_log(DBG_ERROR, "%s: check vaddr=%p pages=%d mmu l2 used %p->%x!\n", __func__, va, pages, mmu_l2, *mmu_l2); + return -1; + } + } + + loop_va += PAGE_SIZE; + } + + return 0; +} +#endif /* RT_USING_USERSPACE */ + +//find a range of free virtual address specified by pages +static size_t find_vaddr(rt_mmu_info *mmu_info, int pages) +{ + size_t va; + size_t find_va = 0; + int n = 0; + size_t start, end; + + if (!pages) + { + return 0; + } + + if (!mmu_info) + { + return 0; + } + + start = mmu_info->vstart; + end = mmu_info->vend; + va = mmu_info->vstart; + for (; start < end; start += ARCH_PAGE_SIZE, va += ARCH_PAGE_SIZE) + { + if (_rt_hw_mmu_v2p(mmu_info, (void *)va)) + { + n = 0; + find_va = 0; + continue; + } + if (!find_va) + { + find_va = va; + } + n++; + if (n >= pages) + { + return find_va; + } + } + return 0; +} + +#ifdef RT_USING_USERSPACE +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr) +{ + rt_size_t pa_s,pa_e; + rt_size_t vaddr; + rt_size_t pages; + int ret; + + if(!size) + { + return 0; + } + + pa_s = (rt_size_t)p_addr; + pa_e = ((rt_size_t)p_addr) + size - 1; + pa_s = GET_PF_ID(pa_s); + pa_e = GET_PF_ID(pa_e); + pages = pa_e - pa_s + 1; + if(v_addr) + { + vaddr = (rt_size_t)v_addr; + pa_s = (rt_size_t)p_addr; + if(GET_PF_OFFSET(vaddr) != GET_PF_OFFSET(pa_s)) + { + return 0; + } + + vaddr = __UMASKVALUE(vaddr,PAGE_OFFSET_MASK); + + if(check_vaddr(mmu_info,(void *)vaddr,pages) != 0) + { + dbg_log(DBG_ERROR, "%s: check vaddr=%p pages=%d failed!\n", __func__, vaddr, pages); + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info,pages); + } + + if(vaddr) + { + ret = __rt_hw_mmu_map(mmu_info,(void *)vaddr,p_addr,pages,attr); + + if(ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void *)(vaddr | GET_PF_OFFSET((rt_size_t)p_addr)); + } + } + + return 0; +} + +#else +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + vaddr = find_vaddr(mmu_info, pages); + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#endif /* RT_USING_USERSPACE */ + +#ifdef RT_USING_USERSPACE +static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t npages,rt_size_t attr) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr, PAGE_OFFSET_MASK); + rt_size_t loop_pa; + rt_size_t i; + rt_size_t left_npages = npages; + rt_size_t used_npages; + void *va,*pa; + + if (!mmu_info) + { + return -1; + } + + while (left_npages) + { + loop_pa = (rt_size_t)rt_pages_alloc(0); + if (!loop_pa) + { + goto err; + } + rt_memset((void *)loop_pa, 0, ARCH_PAGE_SIZE); + if (__rt_hw_mmu_map(mmu_info, (void *)loop_va, (void *)loop_pa, 1, attr) < 0) + { + rt_pages_free((void *)loop_pa, 0); /* free unmaped phy page first */ + goto err; + } + --left_npages; + loop_va += PAGE_SIZE; + } + return 0; +err: + va = (void *)__UMASKVALUE((rt_size_t)v_addr, PAGE_OFFSET_MASK); + used_npages = npages - left_npages; + + for (i = 0; i < used_npages; i++) + { + pa = rt_hw_mmu_v2p(mmu_info, va); + if (pa) + { + rt_pages_free(pa, 0); + } + va = (void *)((rt_uint8_t *)va + PAGE_SIZE); + } + __rt_hw_mmu_unmap(mmu_info,v_addr, used_npages); + return -1; +} + +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr) +{ + rt_size_t vaddr; + rt_size_t offset; + rt_size_t pages; + int ret; + + if(!size) + { + return 0; + } + + offset = GET_PF_OFFSET((rt_size_t)v_addr); + size += (offset + ARCH_PAGE_SIZE - 1); + pages = size >> PAGE_OFFSET_BIT; + + if(v_addr) + { + vaddr = __UMASKVALUE((rt_size_t)v_addr, PAGE_OFFSET_MASK); + + if(check_vaddr(mmu_info,(void *)vaddr, pages) != 0) + { + dbg_log(DBG_ERROR, "_rt_hw_mmu_map_auto: check vaddr %p on pages %d failed!\n", vaddr, pages); + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info,pages); + } + + if(vaddr) + { + ret = __rt_hw_mmu_map_auto(mmu_info, (void *)vaddr, pages, attr); + + if(ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void *)(vaddr | offset); + } + dbg_log(DBG_ERROR, "_rt_hw_mmu_map_auto: do __rt_hw_mmu_map_auto failed!\n"); + } + else + { + dbg_log(DBG_ERROR, "_rt_hw_mmu_map_auto: get vaddr failed!\n"); + } + return 0; +} +#endif /* RT_USING_USERSPACE */ + +/** + * unmap page on v_addr, free page if unmapped, further more, if page table empty, need free it. + */ +static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t npages) +{ + rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr, PAGE_OFFSET_MASK); + rt_size_t l1_off, l2_off; + rt_size_t *mmu_l1, *mmu_l2; + + RT_ASSERT(mmu_info); + + if ((rt_size_t)v_addr < mmu_info->vstart || (rt_size_t)v_addr >= mmu_info -> vend) + { + dbg_log(DBG_ERROR, "unmap vaddr %p out of range [%p~%p)\n", v_addr, mmu_info->vstart, mmu_info->vend); + return; + } + + while(npages--) + { + l1_off = (rt_size_t)GET_L1(loop_va); + l2_off = (rt_size_t)GET_L2(loop_va); + mmu_l1 = ((rt_size_t *)mmu_info -> vtable) + l1_off; + if (!PTE_USED(*mmu_l1)) + { + dbg_log(DBG_ERROR, "unmap vaddr %p mmu l1 unused %p->%x\n", v_addr, mmu_l1, *mmu_l1); + } + RT_ASSERT(PTE_USED(*mmu_l1)) + mmu_l2 = (rt_size_t *)(GET_PADDR(*mmu_l1)) + l2_off; + if (!PTE_USED(*mmu_l2)) + { + dbg_log(DBG_ERROR, "unmap vaddr %p mmu l2 unused %p->%x\n", v_addr, mmu_l2, *mmu_l2); + } + RT_ASSERT(PTE_USED(*mmu_l2)); + *mmu_l2 = 0; /* clear page table entry */ + rt_hw_cpu_dcache_clean(mmu_l2, sizeof(*mmu_l2)); + mmu_l2 -= l2_off; /* get base addr on page aligned */ + + if(rt_pages_free(mmu_l2, 0)) /* page table no phy page, empty */ + { + *mmu_l1 = 0; /* clear page dir table entry */ + rt_hw_cpu_dcache_clean(mmu_l1, sizeof(*mmu_l1)); + } + + loop_va += PAGE_SIZE; + } +} + +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size) +{ + rt_size_t va_s,va_e; + rt_size_t pages; + + va_s = ((rt_size_t)v_addr) >> PAGE_OFFSET_BIT; + va_e = (((rt_size_t)v_addr) + size - 1) >> PAGE_OFFSET_BIT; + pages = va_e - va_s + 1; + __rt_hw_mmu_unmap(mmu_info,v_addr,pages); + rt_hw_cpu_tlb_invalidate(); +} + +#ifdef RT_USING_USERSPACE +/** + * map vaddr in vtable with size and attr, this need a phy addr + * + * if v_addr == RT_NULL, get a valid vaddr to map. + * + * success return start vaddr, failed return RT_NULL + */ +void *rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map(mmu_info,v_addr,p_addr,size,attr); + rt_hw_interrupt_enable(level); + return ret; +} + +/** + * map vaddr in vtable with size and attr, this will auto alloc phy addr + * + * if v_addr == RT_NULL, get a valid vaddr to map. + * + * success return start vaddr, failed return RT_NULL + */ +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map_auto(mmu_info,v_addr,size,attr); + rt_hw_interrupt_enable(level); + return ret; +} +#else +/** + * map vaddr in vtable with size and attr, this need a phy addr + * + * success return start vaddr, failed return RT_NULL + */ +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map(mmu_info, p_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; +} +#endif + +/** + * unmap vaddr in vtable, free phyaddr and page table + */ +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + _rt_hw_mmu_unmap(mmu_info,v_addr,size); + rt_hw_interrupt_enable(level); +} + +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void *v_addr) +{ + size_t l1 = GET_L1((size_t)v_addr); + pde_t *pde = &mmu_info->vtable[l1]; + if (*pde & PTE_P) + { + size_t *pte_addr = (size_t *)GET_PADDR(*pde); + size_t l2 = GET_L2((size_t)v_addr); + pte_t *pte = (pte_t *)&pte_addr[l2]; + if (*pte & PTE_P) + { + return (void *)(GET_PADDR(*pte) | GET_PF_OFFSET((rt_size_t)v_addr)); + } + } + return RT_NULL; +} + +#ifdef RT_DEBUG_MMU_X86 +void *_rt_hw_mmu_v2p_with_dbg(rt_mmu_info *mmu_info, void *v_addr) +{ + rt_kprintf("v2p: mmu vtable=%p, vaddr=%p\n", mmu_info->vtable, v_addr); + size_t l1 = GET_L1((size_t)v_addr); + rt_kprintf("=>L1=%d ", l1); + pde_t *pde = &mmu_info->vtable[l1]; + rt_kprintf("pde=>%p:%x (%x|%x)\n", pde, *pde, GET_PADDR(*pde), GET_PATTR(*pde)); + if (*pde & PTE_P) + { + size_t *pte_addr = (size_t *)GET_PADDR(*pde); + size_t l2 = GET_L2((size_t)v_addr); + rt_kprintf(" =>L2=%d ", l2); + pte_t *pte = (pte_t *)&pte_addr[l2]; + rt_kprintf("pte=>%p:%x (%x|%x)\n", pte, *pte, GET_PADDR(*pte), GET_PATTR(*pte)); + if (*pte & PTE_P) + { + rt_kprintf(" =>paddr:%p\n", GET_PADDR(*pte)); + return (void *)GET_PADDR(*pte); + } + } + rt_kprintf("v2p: mmu v2p %p failed!\n", v_addr); + return RT_NULL; +} +#endif + +/** + * virtual addr to physical addr + * + * success return phyaddr, failed return RT_NULL + */ +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); +#ifdef RT_DEBUG_MMU_X86 + ret = _rt_hw_mmu_v2p_with_dbg(mmu_info,v_addr); +#else + ret = _rt_hw_mmu_v2p(mmu_info,v_addr); +#endif + rt_hw_interrupt_enable(level); + return ret; +} + +void mmu_set_pagetable(rt_ubase_t addr) +{ + /* set new pgdir will flush tlb */ + write_cr3(addr); +} + +void mmu_enable_user_page_access() +{ +} + +void mmu_disable_user_page_access() +{ +} + +void mmu_enable() +{ + write_cr0(read_cr0() | CR0_PG); +} diff --git a/libcpu/x86/i386/mmu.h b/libcpu/x86/i386/mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..2f704e4c431fe8f40ae3ab42545210545a20a89c --- /dev/null +++ b/libcpu/x86/i386/mmu.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-14 JasonHu first version + */ + +#ifndef __MMU_H__ +#define __MMU_H__ + +#include +#include +#include + +#undef PAGE_SIZE + +#define ADDRESS_WIDTH_BITS 32 +#define PHYSICAL_ADDRESS_WIDTH_BITS ADDRESS_WIDTH_BITS +#define ARCH_ADDRESS_WIDTH_BITS ADDRESS_WIDTH_BITS + +#define __SIZE(bit) (1U << (bit)) +#define __MASK(bit) (__SIZE(bit) - 1UL) +#define __UMASK(bit) (~(__MASK(bit))) +#define __MASKVALUE(value,maskvalue) ((value) & (maskvalue)) +#define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue))) +#define __CHECKUPBOUND(value,bit_count) (!(((rt_size_t)(value)) & (~__MASK(bit_count)))) +#define __CHECKALIGN(value,start_bit) (!(((rt_size_t)(value)) & (__MASK(start_bit)))) + +#define __PARTBIT(value,start_bit,length) (((value) >> (start_bit)) & __MASK(length)) + +#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit)) +#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit)) + +#define PAGE_OFFSET_SHIFT 0 +#define PAGE_OFFSET_BIT 12 +#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT) +#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT) +#define PAGE_ADDR_MASK __UMASK(PAGE_OFFSET_BIT) + +#define PTE_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT) +#define PTE_BIT 10 +#define PDE_SHIFT (PTE_SHIFT + PTE_BIT) +#define PDE_BIT 10 + +#define mmu_flush_tlb() \ + do \ + { \ + unsigned long tmpreg; \ + __asm__ __volatile__ ( \ + "movl %%cr3, %0 \n\t" \ + "movl %0, %%cr3 \n\t" \ + :"=r"(tmpreg) \ + : \ + :"memory" \ + ); \ + } \ + while(0) + +#define ARCH_PAGE_SIZE PAGE_SIZE +#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1) +#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT + +typedef struct +{ + rt_size_t *vtable; + rt_size_t vstart; + rt_size_t vend; + rt_size_t pv_off; +}rt_mmu_info; + +typedef rt_size_t pde_t; /* page dir entry */ +typedef rt_size_t pte_t; /* page table entry */ + +/* page offset */ +#define GET_PF_ID(addr) ((addr) >> PAGE_OFFSET_BIT) +#define GET_PF_OFFSET(addr) __MASKVALUE(addr,PAGE_OFFSET_MASK) +#define GET_L1(addr) __PARTBIT(addr,PDE_SHIFT,PDE_BIT) +#define GET_L2(addr) __PARTBIT(addr,PTE_SHIFT,PTE_BIT) +#define GET_PADDR(pte) ((pte) & PAGE_ADDR_MASK) +#define GET_PATTR(pte) ((pte) & PAGE_OFFSET_MASK) + +#define PTE_PER_PAGE 1024 + +#define PAGE_TABLE_PADDR 0X3F3000 +#define PAGE_TABLE_VADDR (KERNEL_VADDR_START + PAGE_TABLE_PADDR) + +#define MAKE_PTE(paddr, attr) (rt_size_t) (((rt_size_t)(paddr) & PAGE_ADDR_MASK) | ((attr) & PAGE_OFFSET_MASK)) + +// page table entry (PTE) fields +#define PTE_P 0x001 // Present +#define PTE_R 0x000 // Read +#define PTE_W 0x002 // Write +#define PTE_X 0x000 // Execute +#define PTE_U 0x004 // User +#define PTE_PWT 0x008 // Write-through +#define PTE_S 0x000 // System +#define PTE_A 0x020 // Accessed +#define PTE_D 0x040 // Dirty + +#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R) +#define PAGE_ATTR_READONLY (PTE_R) +#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R) + +#define PAGE_ATTR_USER (PTE_U) +#define PAGE_ATTR_SYSTEM (PTE_S) + +#define KERNEL_PAGE_ATTR (PTE_P | PAGE_ATTR_RWX | PAGE_ATTR_SYSTEM) + +#define PTE_USED(pte) __MASKVALUE(pte,PTE_P) + +#define MMU_MAP_K_RO (PTE_S | PTE_R) +#define MMU_MAP_K_RWCB (PTE_S | PTE_R | PTE_W) +#define MMU_MAP_K_RW (PTE_S | PTE_R | PTE_W) +#define MMU_MAP_K_DEVICE (PTE_S | PTE_R | PTE_W) +#define MMU_MAP_U_RO (PTE_U | PTE_R) +#define MMU_MAP_U_RWCB (PTE_U | PTE_R | PTE_W) +#define MMU_MAP_U_RW (PTE_U | PTE_R | PTE_W) +#define MMU_MAP_U_DEVICE (PTE_U | PTE_R | PTE_W) + +#define PAGE_ATTR_MASK PAGE_OFFSET_MASK + +void mmu_set_pagetable(rt_ubase_t addr); +void mmu_enable_user_page_access(); +void mmu_disable_user_page_access(); +void mmu_enable(); + +void *mmu_table_get(); +void switch_mmu(void *mmu_table); +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info,void *v_address,rt_size_t size,rt_size_t *vtable,rt_size_t pv_off); +void rt_hw_mmu_kernel_map_init(rt_mmu_info *mmu_info,rt_size_t vaddr_start,rt_size_t size); + +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info,void *v_addr,void *p_addr,rt_size_t size,rt_size_t attr); +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size,rt_size_t attr); +#else +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr); +#endif /* RT_USING_USERSPACE */ + +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info,void *v_addr,rt_size_t size); +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr); + +/* used in kernel mmaped area */ +#define rt_hw_phy2vir(p) ((rt_ubase_t)(p) + KERNEL_VADDR_START) +#define rt_hw_vir2phy(v) ((rt_ubase_t)(v) - KERNEL_VADDR_START) + +#endif diff --git a/libcpu/x86/i386/multiboot2.h b/libcpu/x86/i386/multiboot2.h new file mode 100644 index 0000000000000000000000000000000000000000..9534b81b262cb396fa3c09fc8c3649f028e2346b --- /dev/null +++ b/libcpu/x86/i386/multiboot2.h @@ -0,0 +1,401 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-17 JasonHu,GuEe-GUI used in i386 + */ + +#ifndef __MULTIBOOT_H__ +#define __MULTIBOOT_H__ + +/* How many bytes from the start of the file we search for the header. */ +#define MULTIBOOT_SEARCH 32768 +#define MULTIBOOT_HEADER_ALIGN 8 + +/* The magic field should contain this. */ +#define MULTIBOOT2_HEADER_MAGIC 0xe85250d6 + +/* This should be in %eax. */ +#define MULTIBOOT2_BOOTLOADER_MAGIC 0x36d76289 + +/* Alignment of multiboot modules. */ +#define MULTIBOOT_MOD_ALIGN 0x00001000 + +/* Alignment of the multiboot info structure. */ +#define MULTIBOOT_INFO_ALIGN 0x00000008 + +/* Flags set in the ’flags’ member of the multiboot header. */ + +#define MULTIBOOT_TAG_ALIGN 8 +#define MULTIBOOT_TAG_TYPE_END 0 +#define MULTIBOOT_TAG_TYPE_CMDLINE 1 +#define MULTIBOOT_TAG_TYPE_BOOT_LOADER_NAME 2 +#define MULTIBOOT_TAG_TYPE_MODULE 3 +#define MULTIBOOT_TAG_TYPE_BASIC_MEMINFO 4 +#define MULTIBOOT_TAG_TYPE_BOOTDEV 5 +#define MULTIBOOT_TAG_TYPE_MMAP 6 +#define MULTIBOOT_TAG_TYPE_VBE 7 +#define MULTIBOOT_TAG_TYPE_FRAMEBUFFER 8 +#define MULTIBOOT_TAG_TYPE_ELF_SECTIONS 9 +#define MULTIBOOT_TAG_TYPE_APM 10 +#define MULTIBOOT_TAG_TYPE_EFI32 11 +#define MULTIBOOT_TAG_TYPE_EFI64 12 +#define MULTIBOOT_TAG_TYPE_SMBIOS 13 +#define MULTIBOOT_TAG_TYPE_ACPI_OLD 14 +#define MULTIBOOT_TAG_TYPE_ACPI_NEW 15 +#define MULTIBOOT_TAG_TYPE_NETWORK 16 +#define MULTIBOOT_TAG_TYPE_EFI_MMAP 17 +#define MULTIBOOT_TAG_TYPE_EFI_BS 18 +#define MULTIBOOT_TAG_TYPE_EFI32_IH 19 +#define MULTIBOOT_TAG_TYPE_EFI64_IH 20 +#define MULTIBOOT_TAG_TYPE_LOAD_BASE_ADDR 21 + +#define MULTIBOOT_HEADER_TAG_END 0 +#define MULTIBOOT_HEADER_TAG_INFORMATION_REQUEST 1 +#define MULTIBOOT_HEADER_TAG_ADDRESS 2 +#define MULTIBOOT_HEADER_TAG_ENTRY_ADDRESS 3 +#define MULTIBOOT_HEADER_TAG_CONSOLE_FLAGS 4 +#define MULTIBOOT_HEADER_TAG_FRAMEBUFFER 5 +#define MULTIBOOT_HEADER_TAG_MODULE_ALIGN 6 +#define MULTIBOOT_HEADER_TAG_EFI_BS 7 +#define MULTIBOOT_HEADER_TAG_ENTRY_ADDRESS_EFI32 8 +#define MULTIBOOT_HEADER_TAG_ENTRY_ADDRESS_EFI64 9 +#define MULTIBOOT_HEADER_TAG_RELOCATABLE 10 + +#define MULTIBOOT_ARCHITECTURE_I386 0 +#define MULTIBOOT_ARCHITECTURE_MIPS32 4 +#define MULTIBOOT_HEADER_TAG_OPTIONAL 1 + +#define MULTIBOOT_LOAD_PREFERENCE_NONE 0 +#define MULTIBOOT_LOAD_PREFERENCE_LOW 1 +#define MULTIBOOT_LOAD_PREFERENCE_HIGH 2 + +#define MULTIBOOT_CONSOLE_FLAGS_CONSOLE_REQUIRED 1 +#define MULTIBOOT_CONSOLE_FLAGS_EGA_TEXT_SUPPORTED 2 + +#ifndef __ASSEMBLY__ + +struct multiboot_header +{ + /* Must be MULTIBOOT_MAGIC - see above. */ + rt_uint32_t magic; + + /* ISA */ + rt_uint32_t architecture; + + /* Total header length. */ + rt_uint32_t header_length; + + /* The above fields plus this one must equal 0 mod 2^32. */ + rt_uint32_t checksum; +}; + +struct multiboot_header_tag +{ + rt_uint16_t type; + rt_uint16_t flags; + rt_uint32_t size; +}; + +struct multiboot_header_tag_information_request +{ + rt_uint16_t type; + rt_uint16_t flags; + rt_uint32_t size; + rt_uint32_t requests[0]; +}; + +struct multiboot_header_tag_address +{ + rt_uint16_t type; + rt_uint16_t flags; + rt_uint32_t size; + rt_uint32_t header_addr; + rt_uint32_t load_addr; + rt_uint32_t load_end_addr; + rt_uint32_t bss_end_addr; +}; + +struct multiboot_header_tag_entry_address +{ + rt_uint16_t type; + rt_uint16_t flags; + rt_uint32_t size; + rt_uint32_t entry_addr; +}; + +struct multiboot_header_tag_console_flags +{ + rt_uint16_t type; + rt_uint16_t flags; + rt_uint32_t size; + rt_uint32_t console_flags; +}; + +struct multiboot_header_tag_framebuffer +{ + rt_uint16_t type; + rt_uint16_t flags; + rt_uint32_t size; + rt_uint32_t width; + rt_uint32_t height; + rt_uint32_t depth; +}; + +struct multiboot_header_tag_module_align +{ + rt_uint16_t type; + rt_uint16_t flags; + rt_uint32_t size; +}; + +struct multiboot_header_tag_relocatable +{ + rt_uint16_t type; + rt_uint16_t flags; + rt_uint32_t size; + rt_uint32_t min_addr; + rt_uint32_t max_addr; + rt_uint32_t align; + rt_uint32_t preference; +}; + +struct multiboot_color +{ + rt_uint8_t red; + rt_uint8_t green; + rt_uint8_t blue; +}; + +struct multiboot_mmap_entry +{ + rt_uint64_t addr; + rt_uint64_t len; +#define MULTIBOOT_MEMORY_AVAILABLE 1 +#define MULTIBOOT_MEMORY_RESERVED 2 +#define MULTIBOOT_MEMORY_ACPI_RECLAIMABLE 3 +#define MULTIBOOT_MEMORY_NVS 4 +#define MULTIBOOT_MEMORY_BADRAM 5 + rt_uint32_t type; + rt_uint32_t zero; +}; +typedef struct multiboot_mmap_entry multiboot_memory_map_t; + +struct multiboot_tag +{ + rt_uint32_t type; + rt_uint32_t size; +}; + +struct multiboot_tag_string +{ + rt_uint32_t type; + rt_uint32_t size; + char string[0]; +}; + +struct multiboot_tag_module +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t mod_start; + rt_uint32_t mod_end; + char cmdline[0]; +}; + +struct multiboot_tag_basic_meminfo +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t mem_lower; + rt_uint32_t mem_upper; +}; + +struct multiboot_tag_bootdev +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t biosdev; + rt_uint32_t slice; + rt_uint32_t part; +}; + +struct multiboot_tag_mmap +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t entry_size; + rt_uint32_t entry_version; + struct multiboot_mmap_entry entries[0]; +}; + +struct multiboot_vbe_info_block +{ + rt_uint8_t external_specification[512]; +}; + +struct multiboot_vbe_mode_info_block +{ + rt_uint8_t external_specification[256]; +}; + +struct multiboot_tag_vbe +{ + rt_uint32_t type; + rt_uint32_t size; + + rt_uint16_t vbe_mode; + rt_uint16_t vbe_interface_seg; + rt_uint16_t vbe_interface_off; + rt_uint16_t vbe_interface_len; + + struct multiboot_vbe_info_block vbe_control_info; + struct multiboot_vbe_mode_info_block vbe_mode_info; +}; + +struct multiboot_tag_framebuffer_common +{ + rt_uint32_t type; + rt_uint32_t size; + + rt_uint64_t framebuffer_addr; + rt_uint32_t framebuffer_pitch; + rt_uint32_t framebuffer_width; + rt_uint32_t framebuffer_height; + rt_uint8_t framebuffer_bpp; +#define MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED 0 +#define MULTIBOOT_FRAMEBUFFER_TYPE_RGB 1 +#define MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT 2 + rt_uint8_t framebuffer_type; + rt_uint16_t reserved; +}; + +struct multiboot_tag_framebuffer +{ + struct multiboot_tag_framebuffer_common common; + + union + { + struct + { + rt_uint16_t framebuffer_palette_num_colors; + struct multiboot_color framebuffer_palette[0]; + }; + struct + { + rt_uint8_t framebuffer_red_field_position; + rt_uint8_t framebuffer_red_mask_size; + rt_uint8_t framebuffer_green_field_position; + rt_uint8_t framebuffer_green_mask_size; + rt_uint8_t framebuffer_blue_field_position; + rt_uint8_t framebuffer_blue_mask_size; + }; + }; +}; + +struct multiboot_tag_elf_sections +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t num; + rt_uint32_t entsize; + rt_uint32_t shndx; + char sections[0]; +}; + +struct multiboot_tag_apm +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint16_t version; + rt_uint16_t cseg; + rt_uint32_t offset; + rt_uint16_t cseg_16; + rt_uint16_t dseg; + rt_uint16_t flags; + rt_uint16_t cseg_len; + rt_uint16_t cseg_16_len; + rt_uint16_t dseg_len; +}; + +struct multiboot_tag_efi32 +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t pointer; +}; + +struct multiboot_tag_efi64 +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint64_t pointer; +}; + +struct multiboot_tag_smbios +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint8_t major; + rt_uint8_t minor; + rt_uint8_t reserved[6]; + rt_uint8_t tables[0]; +}; + +struct multiboot_tag_old_acpi +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint8_t rsdp[0]; +}; + +struct multiboot_tag_new_acpi +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint8_t rsdp[0]; +}; + +struct multiboot_tag_network +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint8_t dhcpack[0]; +}; + +struct multiboot_tag_efi_mmap +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t descr_size; + rt_uint32_t descr_vers; + rt_uint8_t efi_mmap[0]; +}; + +struct multiboot_tag_efi32_ih +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t pointer; +}; + +struct multiboot_tag_efi64_ih +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint64_t pointer; +}; + +struct multiboot_tag_load_base_addr +{ + rt_uint32_t type; + rt_uint32_t size; + rt_uint32_t load_base_addr; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* __MULTIBOOT_H__ */ diff --git a/libcpu/x86/i386/pic.c b/libcpu/x86/i386/pic.c new file mode 100644 index 0000000000000000000000000000000000000000..4be3a81b8f89f582a1685a6c04bffcd0d02082fb --- /dev/null +++ b/libcpu/x86/i386/pic.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 JasonHu first version + */ + +#include "pic.h" +#include + +void rt_hw_pic_init(void) +{ + /* mask all interrupts */ + outb(PIC_MASTER_CTLMASK, 0xff); + outb(PIC_SLAVE_CTLMASK, 0xff); + + outb(PIC_MASTER_CTL, 0x11); + outb(PIC_MASTER_CTLMASK, 0x20); + outb(PIC_MASTER_CTLMASK, 1 << 2); + outb(PIC_MASTER_CTLMASK, 0x01); + + outb(PIC_SLAVE_CTL, 0x11); + outb(PIC_SLAVE_CTLMASK, 0x28); + outb(PIC_SLAVE_CTLMASK, 2); + outb(PIC_SLAVE_CTLMASK, 0x01); + + /* mask all interrupts */ + outb(PIC_MASTER_CTLMASK, 0xff); + outb(PIC_SLAVE_CTLMASK, 0xff); +} + +void rt_hw_pic_enable(int irq) +{ + if (irq < 8) /* clear master */ + { + outb(PIC_MASTER_CTLMASK, inb(PIC_MASTER_CTLMASK) & ~(1 << irq)); + } + else /* clear irq 2 first, then clear slave */ + { + outb(PIC_MASTER_CTLMASK, inb(PIC_MASTER_CTLMASK) & ~(1 << PIC_SLAVE_CONNECT_IRQ)); + outb(PIC_SLAVE_CTLMASK, inb(PIC_SLAVE_CTLMASK) & ~ (1 << (irq - 8))); + } +} + +void rt_hw_pic_disable(int irq) +{ + if(irq < 8) /* set master */ + { + outb(PIC_MASTER_CTLMASK, inb(PIC_MASTER_CTLMASK) | (1 << irq)); + } + else /* set slave */ + { + outb(PIC_SLAVE_CTLMASK, inb(PIC_SLAVE_CTLMASK) | (1 << (irq - 8))); + } +} + +void rt_hw_pic_ack(int irq) +{ + if (irq >= 8) /* slaver */ + { + outb(PIC_SLAVE_CTL, PIC_EIO); + } + outb(PIC_MASTER_CTL, PIC_EIO); +} diff --git a/libcpu/x86/i386/pic.h b/libcpu/x86/i386/pic.h new file mode 100644 index 0000000000000000000000000000000000000000..5de220dd47af89b8d2dfb95ae37a2a2b91451c7f --- /dev/null +++ b/libcpu/x86/i386/pic.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 JasonHu first version + */ + +#ifndef __PIC_H__ +#define __PIC_H__ + +#define PIC_MASTER_CTL 0x20 /* I/O port for interrupt controller */ +#define PIC_MASTER_CTLMASK 0x21 /* setting bits in this port disables ints */ +#define PIC_SLAVE_CTL 0xa0 /* I/O port for second interrupt controller */ +#define PIC_SLAVE_CTLMASK 0xa1 /* setting bits in this port disables ints */ + +#define PIC_EIO 0x20 /* end of IO port */ + +#define PIC_SLAVE_CONNECT_IRQ 2 /* irq2 connected to slaver pic */ + +void rt_hw_pic_init(); +void rt_hw_pic_enable(int irq); +void rt_hw_pic_disable(int irq); +void rt_hw_pic_ack(int irq); + +#endif /* __PIC_H__ */ diff --git a/libcpu/x86/i386/segment.c b/libcpu/x86/i386/segment.c new file mode 100644 index 0000000000000000000000000000000000000000..54c82caee5efe4a71dce773c809cecb520c3efc3 --- /dev/null +++ b/libcpu/x86/i386/segment.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-06 JasonHu first version + */ + +#include "segment.h" +#include "tss.h" +#include "cpuport.h" + +#include +#include + +struct rt_hw_segment +{ + rt_uint16_t limit_low, base_low; + rt_uint8_t base_mid, access_right; + rt_uint8_t limit_high, base_high; +}; +typedef struct rt_hw_segment rt_hw_segment_t; + +static void segment_set(rt_hw_segment_t *seg, rt_ubase_t limit, + rt_ubase_t base, rt_ubase_t attributes) +{ + seg->limit_low = limit & 0xffff; + seg->base_low = base & 0xffff; + seg->base_mid = (base >> 16) & 0xff; + seg->access_right = attributes & 0xff; + seg->limit_high = ((limit >> 16) & 0x0f) | ((attributes >> 8) & 0xf0); + seg->base_high = (base >> 24) & 0xff; +} + +/** + * in x86, we can use fs/gs segment to save thread info, + * set thread info base addr, os can use gs:0 to get the first + * data on [base] + */ +void rt_hw_seg_tls_set(rt_ubase_t base) +{ + rt_hw_segment_t *seg = GDT_OFF2PTR(((rt_hw_segment_t *) GDT_VADDR), INDEX_USER_TLS); + seg->base_low = base & 0xffff; + seg->base_mid = (base >> 16) & 0xff; + seg->base_high = (base >> 24) & 0xff; +} + +rt_ubase_t rt_hw_seg_tls_get() +{ + rt_hw_segment_t *seg = GDT_OFF2PTR(((rt_hw_segment_t *) GDT_VADDR), INDEX_USER_TLS); + return (seg->base_low & 0xffff) | ((seg->base_mid & 0xff) << 16) | ((seg->base_high & 0xff) << 24); +} + +void rt_hw_segment_init(void) +{ + /* Global segment table */ + rt_hw_segment_t *gdt = (rt_hw_segment_t *) GDT_VADDR; + + int i; + for (i = 0; i <= GDT_LIMIT/8; i++) + { + segment_set(GDT_OFF2PTR(gdt, i), 0, 0, 0); + } + + segment_set(GDT_OFF2PTR(gdt, INDEX_KERNEL_CODE), GDT_BOUND_TOP, GDT_BOUND_BOTTOM, GDT_KERNEL_CODE_ATTR); + segment_set(GDT_OFF2PTR(gdt, INDEX_KERNEL_DATA), GDT_BOUND_TOP, GDT_BOUND_BOTTOM, GDT_KERNEL_DATA_ATTR); + + rt_hw_tss_t *tss = rt_hw_tss_get(); + segment_set(GDT_OFF2PTR(gdt, INDEX_TSS), sizeof(rt_hw_tss_t) - 1, (rt_ubase_t )tss, GDT_TSS_ATTR); + + segment_set(GDT_OFF2PTR(gdt, INDEX_USER_CODE), GDT_BOUND_TOP, GDT_BOUND_BOTTOM, GDT_USER_CODE_ATTR); + segment_set(GDT_OFF2PTR(gdt, INDEX_USER_DATA), GDT_BOUND_TOP, GDT_BOUND_BOTTOM, GDT_USER_DATA_ATTR); + + segment_set(GDT_OFF2PTR(gdt, INDEX_USER_TLS), GDT_BOUND_TOP, GDT_BOUND_BOTTOM, GDT_USER_TLS_ATTR); + + extern void load_new_gdt(rt_ubase_t size, rt_ubase_t gdtr); + load_new_gdt(GDT_LIMIT, GDT_VADDR); +} diff --git a/libcpu/x86/i386/segment.h b/libcpu/x86/i386/segment.h new file mode 100644 index 0000000000000000000000000000000000000000..57997dfb275d40a8bfc4e43d4a4e2664065e9200 --- /dev/null +++ b/libcpu/x86/i386/segment.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-06 JasonHu first version + */ + +#ifndef __X86_SEGMENT_H__ +#define __X86_SEGMENT_H__ + +#include + +/* DA: Descriptor Attribute */ +#define DA_32 0x4000 /* 32 bits segment */ +#define DA_G 0x8000 /* segment limit is 4KB */ +#define DA_DPL0 0x00 /* DPL = 0 */ +#define DA_DPL1 0x20 /* DPL = 1 */ +#define DA_DPL2 0x40 /* DPL = 2 */ +#define DA_DPL3 0x60 /* DPL = 3 */ +#define DA_DR 0x90 /* readonly data */ +#define DA_DRW 0x92 /* read/write data */ +#define DA_DRWA 0x93 /* accessed read/write data */ +#define DA_C 0x98 /* code */ +#define DA_CR 0x9A /* readable code */ +#define DA_CCO 0x9C /* only execute consistent code segment */ +#define DA_CCOR 0x9E /* executable readable and consistent code segment */ +#define DA_LDT 0x82 /* local descriptor table */ +#define DA_386TSS 0x89 /* 386 TSS */ + +/* SA : Selector Attribute */ +#define SA_RPL0 0 +#define SA_RPL1 1 +#define SA_RPL2 2 +#define SA_RPL3 3 + +#define SA_TIG 0 /* selector in GDT */ +#define SA_TIL 1 /* selector in IDT */ + +/* index of descriptor */ +#define INDEX_DUMMY 0 +#define INDEX_KERNEL_CODE 1 +#define INDEX_KERNEL_DATA 2 +#define INDEX_TSS 3 +#define INDEX_USER_CODE 4 +#define INDEX_USER_DATA 5 +#define INDEX_USER_TLS 6 + +#define KERNEL_CODE_SEL ((INDEX_KERNEL_CODE << 3) + (SA_TIG << 2) + SA_RPL0) +#define KERNEL_DATA_SEL ((INDEX_KERNEL_DATA << 3) + (SA_TIG << 2) + SA_RPL0) +#define KERNEL_STACK_SEL KERNEL_DATA_SEL + +#define KERNEL_TSS_SEL ((INDEX_TSS << 3) + (SA_TIG << 2) + SA_RPL0) + +#define USER_CODE_SEL ((INDEX_USER_CODE << 3) + (SA_TIG << 2) + SA_RPL3) +#define USER_DATA_SEL ((INDEX_USER_DATA << 3) + (SA_TIG << 2) + SA_RPL3) +#define USER_STACK_SEL USER_DATA_SEL + +#define USER_TLS_SEL ((INDEX_USER_TLS << 3) + (SA_TIG << 2) + SA_RPL3) + +#define GDT_LIMIT 0x000007ff +#define GDT_PADDR 0x003F0000 + +#define GDT_VADDR (KERNEL_VADDR_START + GDT_PADDR) + +#define GDT_OFF2PTR(gdt, off) (gdt + off) + +#define GDT_BOUND_BOTTOM 0 +#define GDT_BOUND_TOP 0xffffffff + +#define GDT_KERNEL_CODE_ATTR (DA_CR | DA_DPL0 | DA_32 | DA_G) +#define GDT_KERNEL_DATA_ATTR (DA_DRW | DA_DPL0 | DA_32 | DA_G) +#define GDT_USER_CODE_ATTR (DA_CR | DA_DPL3 | DA_32 | DA_G) +#define GDT_USER_DATA_ATTR (DA_DRW | DA_DPL3 | DA_32 | DA_G) +#define GDT_TSS_ATTR (DA_386TSS) +#define GDT_USER_TLS_ATTR (DA_DR | DA_DPL3 | DA_32 | DA_G) /* read only data seg */ + +#ifndef __ASSEMBLY__ + +#include + +void rt_hw_segment_init(void); + +void rt_hw_seg_tls_set(rt_ubase_t base); +rt_ubase_t rt_hw_seg_tls_get(); + +#endif + +#endif /*__X86_SEGMENT_H__*/ diff --git a/libcpu/x86/i386/stackframe.h b/libcpu/x86/i386/stackframe.h new file mode 100644 index 0000000000000000000000000000000000000000..37e2d3e4221b083c1d2b6b0427ed941458e43496 --- /dev/null +++ b/libcpu/x86/i386/stackframe.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 JasonHu first version + */ + +#ifndef __STACK_FRAME_H__ +#define __STACK_FRAME_H__ + +#include + +struct rt_hw_stack_frame +{ + rt_uint32_t vec_no; + + rt_uint32_t edi; + rt_uint32_t esi; + rt_uint32_t ebp; + rt_uint32_t esp_dummy; /* esp_dummy not used, only use a position */ + rt_uint32_t ebx; + rt_uint32_t edx; + rt_uint32_t ecx; + rt_uint32_t eax; + + rt_uint32_t gs; + rt_uint32_t fs; + rt_uint32_t es; + rt_uint32_t ds; + rt_uint32_t error_code; /* error code will push into stack if exception has it, or not push 0 by ourself */ + rt_uint32_t eip; + rt_uint32_t cs; + rt_uint32_t eflags; + /* + * below will push into stack when from user privilege level enter + * kernel privilege level (syscall/excption/interrupt) + */ + rt_uint32_t esp; + rt_uint32_t ss; +} __attribute__((packed)); + +typedef struct rt_hw_stack_frame rt_hw_stack_frame_t; + +typedef void (*hw_thread_func_t)(void *); + +/* we use ebp, ebx, edi, esi, eip as context for fork/clone */ +#define HW_CONTEXT_MEMBER_NR 5 + +struct rt_hw_context +{ + rt_uint32_t ebp; + rt_uint32_t ebx; + rt_uint32_t edi; + rt_uint32_t esi; + + /* first run point to func, other time point to the ret addr of switch_to */ + void (*eip) (hw_thread_func_t func, void *arg, void (*texit)()); + + rt_uint32_t unused; + hw_thread_func_t function; + void *arg; + void *texit; /* thread exit call */ +}; +typedef struct rt_hw_context rt_hw_context_t; + +void rt_hw_stack_frame_dump(rt_hw_stack_frame_t *frame); + +#endif /* __STACK_FRAME_H__ */ diff --git a/libcpu/x86/i386/start_gcc.S b/libcpu/x86/i386/start_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..73cb76514a3492d656ea0551884481e758d4413d --- /dev/null +++ b/libcpu/x86/i386/start_gcc.S @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 JasonHu,GuEe-GUI first version + */ + +#define __ASSEMBLY__ +#include "multiboot2.h" + +# the size of stack is 16KB +#define STACK_SIZE 0x4000 + +#define KSTACK_TOP_PHY 0x9f000 + +.code32 + +.extern rt_boot_setup_entry, primary_cpu_entry + +.section .init +.globl start, _start + +start: +_start: + jmp multiboot_entry + +.align 8 +multiboot_header: + .long MULTIBOOT2_HEADER_MAGIC # magic number (multiboot 2) + .long MULTIBOOT_ARCHITECTURE_I386 # architecture 0 (protected mode i386) + .long multiboot_header_end - multiboot_header # header length + # checksum + .long -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT_ARCHITECTURE_I386 + (multiboot_header_end - multiboot_header)) + # insert optional multiboot tags here + + # required end tag + .align 8 + .short MULTIBOOT_HEADER_TAG_END # type + .short 0 # flags + .long 8 # size +multiboot_header_end: +multiboot_entry: + # initialize the stack pointer + movl $(stack + STACK_SIZE), %esp + + # reset EFLAGS + pushl $0 + popf + + # push the pointer to the Multiboot information structure + pushl %ebx + # push the magic value + pushl %eax + + # jump to rt_boot_setup_entry + call rt_boot_setup_entry + + # jump to setup_fail if rt_boot_setup_entry return -1 + popl %eax + cmpl $-1, %eax + je setup_fail + + # set kernel stack top + movl $KSTACK_TOP_PHY, %esp + + # jump to kernel_start + movl $primary_cpu_entry, %eax + jmp *%eax + +setup_fail: + # print "Error!" in protected mode + movl $0xcf72cf45, 0xb8000 + movl $0xcf6fcf72, 0xb8004 + movl $0xcf21cf72, 0xb8008 + +multiboot_hlt: + hlt + jmp multiboot_hlt + + .comm stack, STACK_SIZE \ No newline at end of file diff --git a/libcpu/x86/i386/syscall_c.c b/libcpu/x86/i386/syscall_c.c new file mode 100644 index 0000000000000000000000000000000000000000..332fb6fa967a64843c18cb5ef917dc79af7fbde3 --- /dev/null +++ b/libcpu/x86/i386/syscall_c.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-03 lizhirui first version + * 2021-07-27 JasonHu port to i386 + */ + +#include +#include +#include + +//#define DBG_LEVEL DBG_WARNING +//#define DBG_LEVEL DBG_INFO +#include + +#ifdef RT_USING_USERSPACE + +#include +#include +#include +#include +#include +#include + +#include "stackframe.h" + +#ifdef RT_USING_SIGNALS +#include +#endif /* RT_USING_SIGNALS */ + +typedef rt_size_t (*syscallfunc_t)(rt_size_t,rt_size_t,rt_size_t,rt_size_t,rt_size_t,rt_size_t,rt_size_t); +syscallfunc_t lwp_get_sys_api(uint32_t); + +void rt_hw_syscall_dispath(struct rt_hw_stack_frame *frame) +{ + if(frame->eax == 0) + { + dbg_log(DBG_ERROR, "[syscall] thread %s called syscall id = 0!\n", rt_thread_self()->name); +#ifdef RT_USING_SIGNALS + lwp_thread_kill(rt_thread_self(), SIGSYS); +#else + for(;;) + { + } +#endif + } + + if(frame->eax == 0xdeadbeef) + { + dbg_log(DBG_ERROR, "[syscall] thread %s called syscall id = 0xdeadbeef!\n", rt_thread_self()->name); +#ifdef RT_USING_SIGNALS + lwp_thread_kill(rt_thread_self(), SIGSYS); +#else + for(;;) + { + } +#endif + } + +#ifdef RT_USING_SIGNALS + if(frame->eax == SIGNAL_RETURN_SYSCAL_ID) /* signal return */ + { + lwp_signal_do_return(frame); + return; + } +#endif /* RT_USING_SIGNALS */ + + syscallfunc_t syscallfunc = (syscallfunc_t)lwp_get_sys_api(frame->eax); + + if(syscallfunc == RT_NULL) + { + dbg_log(DBG_ERROR, "[syscall] thread %s called unsupported syscall %d!\n", + rt_thread_self()->name, frame->eax); +#ifdef RT_USING_SIGNALS + lwp_thread_kill(rt_thread_self(), SIGSYS); +#else + for(;;) + { + } +#endif + } + /* TODO: support arg6 */ + LOG_I("\033[36msyscall id = %d,arg0 = 0x%p,arg1 = 0x%p,arg2 = 0x%p,arg3 = 0x%p,arg4 = 0x%p," + "arg5 = 0x%p,arg6 = 0x%p(unsupport)\n\033[37m", + frame->eax, frame->ebx, frame->ecx, frame->edx, frame->esi, frame->edi, frame->ebp, 0); + frame->eax = syscallfunc(frame->ebx, frame->ecx, frame->edx, frame->esi, frame->edi, frame->ebp, 0); + LOG_I("\033[36msyscall deal ok,ret = 0x%p\n\033[37m",frame->eax); +} + +#endif /* RT_USING_USERSPACE */ diff --git a/libcpu/x86/i386/tss.c b/libcpu/x86/i386/tss.c new file mode 100644 index 0000000000000000000000000000000000000000..ffe3c5c9f2a07e456ba5a08d0aed208077243dc2 --- /dev/null +++ b/libcpu/x86/i386/tss.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-06 JasonHu first version + */ + +#include "tss.h" +#include "cpuport.h" +#include "segment.h" +#include +#include +#include + +static rt_hw_tss_t tss; + +rt_hw_tss_t *rt_hw_tss_get() +{ + return &tss; +} + +/** + * @brief : set current process kernel stack top + * + * @param top : stack top + */ +void rt_hw_tss_set_kstacktop(rt_ubase_t top) +{ + // tss.esp0 is kernel statck + tss.esp0 = top; +} + +void rt_hw_tss_init() +{ + memset(&tss, 0, sizeof(rt_hw_tss_t)); + tss.esp0 = KERNEL_STACK_TOP; + tss.ss0 = KERNEL_DATA_SEL; + tss.iobase = sizeof(rt_hw_tss_t); + /* load tr */ + ltr(KERNEL_TSS_SEL); +} diff --git a/libcpu/x86/i386/tss.h b/libcpu/x86/i386/tss.h new file mode 100644 index 0000000000000000000000000000000000000000..fb1022e73b5ed5b1f019a602f2d1541436b4bf8c --- /dev/null +++ b/libcpu/x86/i386/tss.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-06 JasonHu first version + */ + +#ifndef __X86_TSS_H__ +#define __X86_TSS_H__ + +#include +#include + +#define KERNEL_STACK_TOP_PHY 0x9f000 +#define KERNEL_STACK_TOP (KERNEL_VADDR_START + KERNEL_STACK_TOP_PHY) + +struct rt_hw_tss +{ + rt_uint32_t backlink; + rt_uint32_t esp0; + rt_uint32_t ss0; + rt_uint32_t esp1; + rt_uint32_t ss1; + rt_uint32_t esp2; + rt_uint32_t ss2; + rt_uint32_t cr3; + rt_uint32_t eip; + rt_uint32_t eflags; + rt_uint32_t eax; + rt_uint32_t ecx; + rt_uint32_t edx; + rt_uint32_t ebx; + rt_uint32_t esp; + rt_uint32_t ebp; + rt_uint32_t esi; + rt_uint32_t edi; + rt_uint32_t es; + rt_uint32_t cs; + rt_uint32_t ss; + rt_uint32_t ds; + rt_uint32_t fs; + rt_uint32_t gs; + rt_uint32_t ldtr; + rt_uint32_t trap; + rt_uint32_t iobase; +}; +typedef struct rt_hw_tss rt_hw_tss_t; + +void rt_hw_tss_init(); +rt_hw_tss_t *rt_hw_tss_get(); +void rt_hw_tss_set_kstacktop(rt_ubase_t top); + +#endif /* __X86_TSS_H__ */ diff --git a/libcpu/x86/i386/x86_gcc.S b/libcpu/x86/i386/x86_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..2baeabd0424f37349012d7bd98f790446b390bdd --- /dev/null +++ b/libcpu/x86/i386/x86_gcc.S @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-13 JasonHu first version + */ + +#define __ASSEMBLY__ +#include "segment.h" + +.global load_new_gdt +load_new_gdt: + movl 4(%esp), %eax + movw %ax, 6(%esp) + lgdt 6(%esp) + + # flush segment registers + movw $KERNEL_DATA_SEL, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + xor %eax, %eax + movw %ax, %fs + movw %ax, %gs + ljmp $KERNEL_CODE_SEL, $.newpc +.newpc: + ret + +.global load_new_idt +load_new_idt: + movl 4(%esp), %eax + movw %ax, 6(%esp) + lidt 6(%esp) + ret + +.global write_cr3 +write_cr3: + movl 4(%esp), %eax + movl %eax, %cr3 + ret + +.global read_cr0 +read_cr0: + movl %cr0, %eax + ret + +.global read_cr2 +read_cr2: + movl %cr2, %eax + ret + +.global write_cr0 +write_cr0: + movl 4(%esp), %eax + movl %eax, %cr0 + ret \ No newline at end of file diff --git a/src/Kconfig b/src/Kconfig index 63a7a67887285ff1b45b584c505cd45faf655476..fd59cdd34d0d948afd136a2d859fceef85d44f59 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -17,6 +17,13 @@ config RT_USING_ARCH_DATA_TYPE Please re-define these data types in rtconfig_project.h file. +config RT_USING_SMART + bool "Enable RT-Thread Smart (microkernel on kernel/userland)" + default n + select RT_USING_LWP + help + RT-Thread Smart is a microkernel based operating system on RT-Thread. + config RT_USING_SMP bool "Enable SMP(Symmetric multiprocessing)" default n @@ -98,6 +105,11 @@ config IDLE_THREAD_STACK_SIZE int "The stack size of idle thread" default 256 +config SYSTEM_THREAD_STACK_SIZE + int "The stack size of system thread (for defunct etc.)" + depends on RT_USING_SMP + default IDLE_THREAD_STACK_SIZE + config RT_USING_TIMER_SOFT bool "Enable software timer with a timer thread" default y @@ -331,7 +343,7 @@ endmenu config RT_VER_NUM hex - default 0x40003 + default 0x50000 help RT-Thread version number diff --git a/src/clock.c b/src/clock.c index a91cd829b65fad7f9044e886213b42afe5a27b35..7ac68c469b7a58b2a93b29f8b3b8a61e2d2426ca 100644 --- a/src/clock.c +++ b/src/clock.c @@ -65,6 +65,15 @@ void rt_tick_set(rt_tick_t tick) rt_hw_interrupt_enable(level); } +#ifdef RT_USING_HOOK +static void (*rt_tick_hook)(void); + +void rt_tick_sethook(void (*hook)(void)) +{ + rt_tick_hook = hook; +} +#endif + /** * This function will notify kernel there is one tick passed. Normally, * this function is invoked by clock ISR. @@ -80,6 +89,13 @@ void rt_tick_increase(void) ++ rt_tick; #endif +#ifdef RT_USING_HOOK + if (rt_tick_hook) + { + rt_tick_hook(); + } +#endif + /* check time slice */ thread = rt_thread_self(); diff --git a/src/cpu.c b/src/cpu.c index 96e585713ba39adc1266e74b00f15b7f72942f9f..d253275c331c2013f56921ba066a5e6db3c1ce29 100644 --- a/src/cpu.c +++ b/src/cpu.c @@ -10,6 +10,10 @@ #include #include +#ifdef RT_USING_USERSPACE +#include +#endif + #ifdef RT_USING_SMP static struct rt_cpu rt_cpus[RT_CPUS_NR]; rt_hw_spinlock_t _cpus_lock; @@ -64,29 +68,41 @@ static void rt_preempt_enable(void) /* enable interrupt */ rt_hw_local_irq_enable(level); } +#endif /* end of RT_USING_SMP */ void rt_spin_lock_init(struct rt_spinlock *lock) { +#ifdef RT_USING_SMP rt_hw_spin_lock_init(&lock->lock); +#endif } RTM_EXPORT(rt_spin_lock_init) void rt_spin_lock(struct rt_spinlock *lock) { +#ifdef RT_USING_SMP rt_preempt_disable(); rt_hw_spin_lock(&lock->lock); +#else + rt_enter_critical(); +#endif } RTM_EXPORT(rt_spin_lock) void rt_spin_unlock(struct rt_spinlock *lock) { +#ifdef RT_USING_SMP rt_hw_spin_unlock(&lock->lock); rt_preempt_enable(); +#else + rt_exit_critical(); +#endif } RTM_EXPORT(rt_spin_unlock) rt_base_t rt_spin_lock_irqsave(struct rt_spinlock *lock) { +#ifdef RT_USING_SMP unsigned long level; rt_preempt_disable(); @@ -95,20 +111,27 @@ rt_base_t rt_spin_lock_irqsave(struct rt_spinlock *lock) rt_hw_spin_lock(&lock->lock); return level; +#else + return rt_hw_interrupt_disable(); +#endif } RTM_EXPORT(rt_spin_lock_irqsave) void rt_spin_unlock_irqrestore(struct rt_spinlock *lock, rt_base_t level) { +#ifdef RT_USING_SMP rt_hw_spin_unlock(&lock->lock); rt_hw_local_irq_enable(level); rt_preempt_enable(); +#else + rt_hw_interrupt_enable(level); +#endif } RTM_EXPORT(rt_spin_unlock_irqrestore) /** - * This fucntion will return current cpu. + * This function will return current cpu. */ struct rt_cpu *rt_cpu_self(void) { @@ -177,6 +200,9 @@ void rt_cpus_lock_status_restore(struct rt_thread *thread) { struct rt_cpu* pcpu = rt_cpu_self(); +#ifdef RT_USING_USERSPACE + lwp_mmu_switch(thread); +#endif pcpu->current_thread = thread; if (!thread->cpus_lock_nest) { @@ -184,5 +210,3 @@ void rt_cpus_lock_status_restore(struct rt_thread *thread) } } RTM_EXPORT(rt_cpus_lock_status_restore); - -#endif diff --git a/src/idle.c b/src/idle.c index 99db64f571c0523b67c0d9b31409a66d346a3a29..b5bfcbe0de4a43824d45e9753411c124abf1f318 100644 --- a/src/idle.c +++ b/src/idle.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -44,12 +44,22 @@ #define _CPUS_NR 1 #endif -extern rt_list_t rt_thread_defunct; +static rt_list_t _rt_thread_defunct = RT_LIST_OBJECT_INIT(_rt_thread_defunct);; static struct rt_thread idle[_CPUS_NR]; ALIGN(RT_ALIGN_SIZE) static rt_uint8_t rt_thread_stack[_CPUS_NR][IDLE_THREAD_STACK_SIZE]; +#ifdef RT_USING_SMP +#ifndef SYSTEM_THREAD_STACK_SIZE +#define SYSTEM_THREAD_STACK_SIZE IDLE_THREAD_STACK_SIZE +#endif +static struct rt_thread rt_system_thread; +ALIGN(RT_ALIGN_SIZE) +static rt_uint8_t rt_system_stack[SYSTEM_THREAD_STACK_SIZE]; +static struct rt_semaphore system_sem; +#endif + #ifdef RT_USING_IDLE_HOOK #ifndef RT_IDLE_HOOK_LIST_SIZE #define RT_IDLE_HOOK_LIST_SIZE 4 @@ -127,33 +137,66 @@ rt_err_t rt_thread_idle_delhook(void (*hook)(void)) #endif +#ifdef RT_USING_MODULE /* Return whether there is defunctional thread to be deleted. */ rt_inline int _has_defunct_thread(void) { /* The rt_list_isempty has prototype of "int rt_list_isempty(const rt_list_t *l)". - * So the compiler has a good reason that the rt_thread_defunct list does - * not change within rt_thread_idle_excute thus optimize the "while" loop + * So the compiler has a good reason that the _rt_thread_defunct list does + * not change within rt_thread_defunct_exceute thus optimize the "while" loop * into a "if". * * So add the volatile qualifier here. */ - const volatile rt_list_t *l = (const volatile rt_list_t *)&rt_thread_defunct; + const volatile rt_list_t *l = (const volatile rt_list_t *)&_rt_thread_defunct; return l->next != l; } +#endif + +/* enqueue a thread to defunct queue + * it must be called between rt_hw_interrupt_disable and rt_hw_interrupt_enable + */ +void rt_thread_defunct_enqueue(rt_thread_t thread) +{ + rt_list_insert_after(&_rt_thread_defunct, &thread->tlist); +#ifdef RT_USING_SMP + rt_sem_release(&system_sem); +#endif +} + +/* dequeue a thread from defunct queue + * it must be called between rt_hw_interrupt_disable and rt_hw_interrupt_enable + */ +rt_thread_t rt_thread_defunct_dequeue(void) +{ + rt_thread_t thread = RT_NULL; + rt_list_t *l = &_rt_thread_defunct; + + if (l->next != l) + { + thread = rt_list_entry(l->next, + struct rt_thread, + tlist); + rt_list_remove(&(thread->tlist)); + } + return thread; +} /** * @ingroup Thread * * This function will perform system background job when system idle. */ -void rt_thread_idle_excute(void) +static void rt_defunct_execute(void) { - /* Loop until there is no dead thread. So one call to rt_thread_idle_excute + /* Loop until there is no dead thread. So one call to rt_defunct_execute * will do all the cleanups. */ - while (_has_defunct_thread()) + while (1) { rt_base_t lock; rt_thread_t thread; + void (*cleanup)(struct rt_thread *tid); + #ifdef RT_USING_MODULE struct rt_dlmodule *module = RT_NULL; #endif @@ -162,69 +205,63 @@ void rt_thread_idle_excute(void) /* disable interrupt */ lock = rt_hw_interrupt_disable(); - /* re-check whether list is empty */ - if (_has_defunct_thread()) - { - /* get defunct thread */ - thread = rt_list_entry(rt_thread_defunct.next, - struct rt_thread, - tlist); #ifdef RT_USING_MODULE - module = (struct rt_dlmodule*)thread->module_id; - if (module) - { - dlmodule_destroy(module); - } + /* check whether list is empty */ + if (!_has_defunct_thread()) + { + rt_hw_interrupt_enable(lock); + break; + } + /* get defunct thread */ + thread = rt_list_entry(_rt_thread_defunct.next, + struct rt_thread, + tlist); + module = (struct rt_dlmodule*)thread->module_id; + if (module) + { + dlmodule_destroy(module); + } + /* remove defunct thread */ + rt_list_remove(&(thread->tlist)); +#else + thread = rt_thread_defunct_dequeue(); + if (!thread) + { + rt_hw_interrupt_enable(lock); + break; + } #endif - /* remove defunct thread */ - rt_list_remove(&(thread->tlist)); - - /* lock scheduler to prevent scheduling in cleanup function. */ - rt_enter_critical(); - - /* invoke thread cleanup */ - if (thread->cleanup != RT_NULL) - thread->cleanup(thread); + /* invoke thread cleanup */ + cleanup = thread->cleanup; + if (cleanup != RT_NULL) + { + rt_hw_interrupt_enable(lock); + cleanup(thread); + lock = rt_hw_interrupt_disable(); + } #ifdef RT_USING_SIGNALS - rt_thread_free_sig(thread); + rt_thread_free_sig(thread); #endif - /* if it's a system object, not delete it */ - if (rt_object_is_systemobject((rt_object_t)thread) == RT_TRUE) - { - /* detach this object */ - rt_object_detach((rt_object_t)thread); - /* unlock scheduler */ - rt_exit_critical(); - - /* enable interrupt */ - rt_hw_interrupt_enable(lock); - - return; - } - - /* unlock scheduler */ - rt_exit_critical(); - } - else + /* if it's a system object, not delete it */ + if (rt_object_is_systemobject((rt_object_t)thread) == RT_TRUE) { + /* detach this object */ + rt_object_detach((rt_object_t)thread); /* enable interrupt */ rt_hw_interrupt_enable(lock); - - /* may the defunct thread list is removed by others, just return */ - return; } - - /* enable interrupt */ - rt_hw_interrupt_enable(lock); - + else + { + rt_hw_interrupt_enable(lock); #ifdef RT_USING_HEAP - /* release thread's stack */ - RT_KERNEL_FREE(thread->stack_addr); - /* delete thread object */ - rt_object_delete((rt_object_t)thread); + /* release thread's stack */ + RT_KERNEL_FREE(thread->stack_addr); + /* delete thread object */ + rt_object_delete((rt_object_t)thread); #endif + } } } @@ -255,13 +292,27 @@ static void rt_thread_idle_entry(void *parameter) } #endif - rt_thread_idle_excute(); -#ifdef RT_USING_PM +#ifndef RT_USING_SMP + rt_defunct_execute(); +#endif + +#ifdef RT_USING_PM rt_system_power_manager(); #endif } } +#ifdef RT_USING_SMP +static void rt_thread_system_entry(void *parameter) +{ + while (1) + { + rt_sem_take(&system_sem, RT_WAITING_FOREVER); + rt_defunct_execute(); + } +} +#endif + /** * @ingroup SystemInit * @@ -291,6 +342,24 @@ void rt_thread_idle_init(void) /* startup */ rt_thread_startup(&idle[i]); } + +#ifdef RT_USING_SMP + RT_ASSERT(RT_THREAD_PRIORITY_MAX > 2); + + rt_sem_init(&system_sem, "defunct", 1, RT_IPC_FLAG_FIFO); + + /* create defunct thread */ + rt_thread_init(&rt_system_thread, + "tsystem", + rt_thread_system_entry, + RT_NULL, + rt_system_stack, + sizeof(rt_system_stack), + RT_THREAD_PRIORITY_MAX - 2, + 32); + /* startup */ + rt_thread_startup(&rt_system_thread); +#endif } /** diff --git a/src/ipc.c b/src/ipc.c index 454fcb5439bd26ae3534d4e6c7c66b22e31b1f89..e78c88854955d80a8442d9e0bf0d85809c300a04 100644 --- a/src/ipc.c +++ b/src/ipc.c @@ -82,10 +82,16 @@ rt_inline rt_err_t rt_ipc_object_init(struct rt_ipc_object *ipc) */ rt_inline rt_err_t rt_ipc_list_suspend(rt_list_t *list, struct rt_thread *thread, - rt_uint8_t flag) + rt_uint8_t flag, + int suspend_flag) { + rt_err_t ret = rt_thread_suspend_with_flag(thread, suspend_flag); + /* suspend thread */ - rt_thread_suspend(thread); + if (ret != RT_EOK) + { + return ret; + } switch (flag) { @@ -144,6 +150,8 @@ rt_inline rt_err_t rt_ipc_list_resume(rt_list_t *list) /* get thread entry */ thread = rt_list_entry(list->next, struct rt_thread, tlist); + thread->error = RT_EOK; + RT_DEBUG_LOG(RT_DEBUG_IPC, ("resume thread:%s\n", thread->name)); /* resume it */ @@ -327,10 +335,11 @@ RTM_EXPORT(rt_sem_delete); * * @return the error code */ -rt_err_t rt_sem_take(rt_sem_t sem, rt_int32_t time) +static rt_err_t _rt_sem_take(rt_sem_t sem, rt_int32_t time, int suspend_flag) { register rt_base_t temp; struct rt_thread *thread; + rt_err_t ret; /* parameter check */ RT_ASSERT(sem != RT_NULL); @@ -373,15 +382,21 @@ rt_err_t rt_sem_take(rt_sem_t sem, rt_int32_t time) thread = rt_thread_self(); /* reset thread error number */ - thread->error = RT_EOK; + thread->error = -RT_EINTR; RT_DEBUG_LOG(RT_DEBUG_IPC, ("sem take: suspend thread - %s\n", thread->name)); /* suspend thread */ - rt_ipc_list_suspend(&(sem->parent.suspend_thread), + ret = rt_ipc_list_suspend(&(sem->parent.suspend_thread), thread, - sem->parent.parent.flag); + sem->parent.parent.flag, + suspend_flag); + if (ret != RT_EOK) + { + rt_hw_interrupt_enable(temp); + return ret; + } /* has waiting time, start thread timer */ if (time > 0) @@ -413,8 +428,25 @@ rt_err_t rt_sem_take(rt_sem_t sem, rt_int32_t time) return RT_EOK; } + +rt_err_t rt_sem_take(rt_sem_t sem, rt_int32_t time) +{ + return _rt_sem_take(sem, time, RT_UNINTERRUPTIBLE); +} RTM_EXPORT(rt_sem_take); +rt_err_t rt_sem_take_interruptible(rt_sem_t sem, rt_int32_t time) +{ + return _rt_sem_take(sem, time, RT_INTERRUPTIBLE); +} +RTM_EXPORT(rt_sem_take_interruptible); + +rt_err_t rt_sem_take_killable(rt_sem_t sem, rt_int32_t time) +{ + return _rt_sem_take(sem, time, RT_KILLABLE); +} +RTM_EXPORT(rt_sem_take_killable); + /** * This function will try to take a semaphore and immediately return * @@ -667,10 +699,11 @@ RTM_EXPORT(rt_mutex_delete); * * @return the error code */ -rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t time) +static rt_err_t _rt_mutex_take(rt_mutex_t mutex, rt_int32_t time, int suspend_flag) { register rt_base_t temp; struct rt_thread *thread; + rt_err_t ret; /* this function must not be used in interrupt even if time = 0 */ RT_DEBUG_IN_THREAD_CONTEXT; @@ -692,7 +725,7 @@ rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t time) thread->name, mutex->value, mutex->hold)); /* reset thread error */ - thread->error = RT_EOK; + thread->error = -RT_EINTR; if (mutex->owner == thread) { @@ -709,9 +742,6 @@ rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t time) } else { -#ifdef RT_USING_SIGNALS -__again: -#endif /* end of RT_USING_SIGNALS */ /* The value of mutex is 1 in initial status. Therefore, if the * value is great than 0, it indicates the mutex is avaible. */ @@ -762,9 +792,15 @@ __again: } /* suspend current thread */ - rt_ipc_list_suspend(&(mutex->parent.suspend_thread), + ret = rt_ipc_list_suspend(&(mutex->parent.suspend_thread), thread, - mutex->parent.parent.flag); + mutex->parent.parent.flag, + suspend_flag); + if (ret != RT_EOK) + { + rt_hw_interrupt_enable(temp); + return ret; + } /* has waiting time, start thread timer */ if (time > 0) @@ -788,11 +824,6 @@ __again: if (thread->error != RT_EOK) { -#ifdef RT_USING_SIGNALS - /* interrupt by signal, try it again */ - if (thread->error == -RT_EINTR) goto __again; -#endif /* end of RT_USING_SIGNALS */ - /* return error */ return thread->error; } @@ -813,8 +844,25 @@ __again: return RT_EOK; } + +rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t time) +{ + return _rt_mutex_take(mutex, time, RT_UNINTERRUPTIBLE); +} RTM_EXPORT(rt_mutex_take); +rt_err_t rt_mutex_take_interruptible(rt_mutex_t mutex, rt_int32_t time) +{ + return _rt_mutex_take(mutex, time, RT_INTERRUPTIBLE); +} +RTM_EXPORT(rt_mutex_take_interruptible); + +rt_err_t rt_mutex_take_killable(rt_mutex_t mutex, rt_int32_t time) +{ + return _rt_mutex_take(mutex, time, RT_KILLABLE); +} +RTM_EXPORT(rt_mutex_take_killable); + /** * This function will release a mutex, if there are threads suspended on mutex, * it will be waked up. @@ -915,7 +963,7 @@ rt_err_t rt_mutex_release(rt_mutex_t mutex) rt_hw_interrupt_enable(temp); /* enable interrupt */ return -RT_EFULL; /* value overflowed */ } - + /* clear owner */ mutex->owner = RT_NULL; mutex->original_priority = 0xff; @@ -1152,6 +1200,7 @@ rt_err_t rt_event_send(rt_event_t event, rt_uint32_t set) /* resume thread, and thread list breaks out */ rt_thread_resume(thread); + thread->error = RT_EOK; /* need do a scheduling */ need_schedule = RT_TRUE; @@ -1183,15 +1232,17 @@ RTM_EXPORT(rt_event_send); * * @return the error code */ -rt_err_t rt_event_recv(rt_event_t event, +static rt_err_t _rt_event_recv(rt_event_t event, rt_uint32_t set, rt_uint8_t option, rt_int32_t timeout, - rt_uint32_t *recved) + rt_uint32_t *recved, + int suspend_flag) { struct rt_thread *thread; register rt_ubase_t level; register rt_base_t status; + rt_err_t ret; RT_DEBUG_IN_THREAD_CONTEXT; @@ -1207,7 +1258,7 @@ rt_err_t rt_event_recv(rt_event_t event, /* get current thread */ thread = rt_thread_self(); /* reset thread error */ - thread->error = RT_EOK; + thread->error = -RT_EINTR; RT_OBJECT_HOOK_CALL(rt_object_trytake_hook, (&(event->parent.parent))); @@ -1233,14 +1284,16 @@ rt_err_t rt_event_recv(rt_event_t event, if (status == RT_EOK) { + thread->error = RT_EOK; + /* set received event */ if (recved) *recved = (event->set & set); - - /* fill thread event info */ + + /* fill thread event info */ thread->event_set = (event->set & set); thread->event_info = option; - + /* received event */ if (option & RT_EVENT_FLAG_CLEAR) event->set &= ~set; @@ -1262,9 +1315,15 @@ rt_err_t rt_event_recv(rt_event_t event, thread->event_info = option; /* put thread to suspended thread list */ - rt_ipc_list_suspend(&(event->parent.suspend_thread), + ret = rt_ipc_list_suspend(&(event->parent.suspend_thread), thread, - event->parent.parent.flag); + event->parent.parent.flag, + suspend_flag); + if (ret != RT_EOK) + { + rt_hw_interrupt_enable(level); + return ret; + } /* if there is a waiting timeout, active thread timer */ if (timeout > 0) @@ -1303,8 +1362,36 @@ rt_err_t rt_event_recv(rt_event_t event, return thread->error; } + +rt_err_t rt_event_recv(rt_event_t event, + rt_uint32_t set, + rt_uint8_t option, + rt_int32_t timeout, + rt_uint32_t *recved) +{ + return _rt_event_recv(event, set, option, timeout, recved, RT_UNINTERRUPTIBLE); +} RTM_EXPORT(rt_event_recv); +rt_err_t rt_event_recv_interruptible(rt_event_t event, + rt_uint32_t set, + rt_uint8_t option, + rt_int32_t timeout, + rt_uint32_t *recved) +{ + return _rt_event_recv(event, set, option, timeout, recved, RT_INTERRUPTIBLE); +} +RTM_EXPORT(rt_event_recv_interruptible); + +rt_err_t rt_event_recv_killable(rt_event_t event, + rt_uint32_t set, + rt_uint8_t option, + rt_int32_t timeout, + rt_uint32_t *recved) +{ + return _rt_event_recv(event, set, option, timeout, recved, RT_KILLABLE); +} +RTM_EXPORT(rt_event_recv_killable); /** * This function can get or set some extra attributions of an event object. * @@ -1507,13 +1594,15 @@ RTM_EXPORT(rt_mb_delete); * * @return the error code */ -rt_err_t rt_mb_send_wait(rt_mailbox_t mb, +static rt_err_t _rt_mb_send_wait(rt_mailbox_t mb, rt_ubase_t value, - rt_int32_t timeout) + rt_int32_t timeout, + int suspend_flag) { struct rt_thread *thread; register rt_ubase_t temp; rt_uint32_t tick_delta; + rt_err_t ret; /* parameter check */ RT_ASSERT(mb != RT_NULL); @@ -1541,7 +1630,7 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb, while (mb->entry == mb->size) { /* reset error number in thread */ - thread->error = RT_EOK; + thread->error = -RT_EINTR; /* no waiting, return timeout */ if (timeout == 0) @@ -1554,9 +1643,16 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb, RT_DEBUG_IN_THREAD_CONTEXT; /* suspend current thread */ - rt_ipc_list_suspend(&(mb->suspend_sender_thread), + ret = rt_ipc_list_suspend(&(mb->suspend_sender_thread), thread, - mb->parent.parent.flag); + mb->parent.parent.flag, + suspend_flag); + + if (ret != RT_EOK) + { + rt_hw_interrupt_enable(temp); + return ret; + } /* has waiting time, start thread timer */ if (timeout > 0) @@ -1606,7 +1702,7 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb, ++ mb->in_offset; if (mb->in_offset >= mb->size) mb->in_offset = 0; - + if(mb->entry < RT_MB_ENTRY_MAX) { /* increase message entry */ @@ -1617,7 +1713,7 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb, rt_hw_interrupt_enable(temp); /* enable interrupt */ return -RT_EFULL; /* value overflowed */ } - + /* resume suspended thread */ if (!rt_list_isempty(&mb->parent.suspend_thread)) { @@ -1636,8 +1732,30 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb, return RT_EOK; } + +rt_err_t rt_mb_send_wait(rt_mailbox_t mb, + rt_ubase_t value, + rt_int32_t timeout) +{ + return _rt_mb_send_wait(mb, value, timeout, RT_UNINTERRUPTIBLE); +} RTM_EXPORT(rt_mb_send_wait); +rt_err_t rt_mb_send_wait_interruptible(rt_mailbox_t mb, + rt_ubase_t value, + rt_int32_t timeout) +{ + return _rt_mb_send_wait(mb, value, timeout, RT_INTERRUPTIBLE); +} +RTM_EXPORT(rt_mb_send_wait_interruptible); + +rt_err_t rt_mb_send_wait_killable(rt_mailbox_t mb, + rt_ubase_t value, + rt_int32_t timeout) +{ + return _rt_mb_send_wait(mb, value, timeout, RT_KILLABLE); +} +RTM_EXPORT(rt_mb_send_wait_killable); /** * This function will send a mail to mailbox object, if there are threads * suspended on mailbox object, it will be waked up. This function will return @@ -1654,6 +1772,18 @@ rt_err_t rt_mb_send(rt_mailbox_t mb, rt_ubase_t value) } RTM_EXPORT(rt_mb_send); +rt_err_t rt_mb_send_interruptible(rt_mailbox_t mb, rt_ubase_t value) +{ + return rt_mb_send_wait_interruptible(mb, value, 0); +} +RTM_EXPORT(rt_mb_send_interruptible); + +rt_err_t rt_mb_send_killable(rt_mailbox_t mb, rt_ubase_t value) +{ + return rt_mb_send_wait_killable(mb, value, 0); +} +RTM_EXPORT(rt_mb_send_killable); + /** * This function will receive a mail from mailbox object, if there is no mail * in mailbox object, the thread shall wait for a specified time. @@ -1664,11 +1794,12 @@ RTM_EXPORT(rt_mb_send); * * @return the error code */ -rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout) +static rt_err_t _rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout, int suspend_flag) { struct rt_thread *thread; register rt_ubase_t temp; rt_uint32_t tick_delta; + rt_err_t ret; /* parameter check */ RT_ASSERT(mb != RT_NULL); @@ -1696,7 +1827,7 @@ rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout) while (mb->entry == 0) { /* reset error number in thread */ - thread->error = RT_EOK; + thread->error = -RT_EINTR; /* no waiting, return timeout */ if (timeout == 0) @@ -1711,9 +1842,15 @@ rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout) RT_DEBUG_IN_THREAD_CONTEXT; /* suspend current thread */ - rt_ipc_list_suspend(&(mb->parent.suspend_thread), + ret = rt_ipc_list_suspend(&(mb->parent.suspend_thread), thread, - mb->parent.parent.flag); + mb->parent.parent.flag, + suspend_flag); + if (ret != RT_EOK) + { + rt_hw_interrupt_enable(temp); + return ret; + } /* has waiting time, start thread timer */ if (timeout > 0) @@ -1789,8 +1926,25 @@ rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout) return RT_EOK; } + +rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout) +{ + return _rt_mb_recv(mb, value, timeout, RT_UNINTERRUPTIBLE); +} RTM_EXPORT(rt_mb_recv); +rt_err_t rt_mb_recv_interruptibale(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout) +{ + return _rt_mb_recv(mb, value, timeout, RT_INTERRUPTIBLE); +} +RTM_EXPORT(rt_mb_recv_interruptibale); + +rt_err_t rt_mb_recv_killable(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout) +{ + return _rt_mb_recv(mb, value, timeout, RT_KILLABLE); +} +RTM_EXPORT(rt_mb_recv_killable); + /** * This function can get or set some extra attributions of a mailbox object. * @@ -2049,15 +2203,17 @@ RTM_EXPORT(rt_mq_delete); * * @return the error code */ -rt_err_t rt_mq_send_wait(rt_mq_t mq, +static rt_err_t _rt_mq_send_wait(rt_mq_t mq, const void *buffer, rt_size_t size, - rt_int32_t timeout) + rt_int32_t timeout, + int suspend_flag) { register rt_ubase_t temp; struct rt_mq_message *msg; rt_uint32_t tick_delta; struct rt_thread *thread; + rt_err_t ret; /* parameter check */ RT_ASSERT(mq != RT_NULL); @@ -2094,7 +2250,7 @@ rt_err_t rt_mq_send_wait(rt_mq_t mq, while ((msg = mq->msg_queue_free) == RT_NULL) { /* reset error number in thread */ - thread->error = RT_EOK; + thread->error = -RT_EINTR; /* no waiting, return timeout */ if (timeout == 0) @@ -2107,9 +2263,15 @@ rt_err_t rt_mq_send_wait(rt_mq_t mq, RT_DEBUG_IN_THREAD_CONTEXT; /* suspend current thread */ - rt_ipc_list_suspend(&(mq->suspend_sender_thread), + ret = rt_ipc_list_suspend(&(mq->suspend_sender_thread), thread, - mq->parent.parent.flag); + mq->parent.parent.flag, + suspend_flag); + if (ret != RT_EOK) + { + rt_hw_interrupt_enable(temp); + return ret; + } /* has waiting time, start thread timer */ if (timeout > 0) @@ -2208,8 +2370,33 @@ rt_err_t rt_mq_send_wait(rt_mq_t mq, return RT_EOK; } + +rt_err_t rt_mq_send_wait(rt_mq_t mq, + const void *buffer, + rt_size_t size, + rt_int32_t timeout) +{ + return _rt_mq_send_wait(mq, buffer, size, timeout, RT_UNINTERRUPTIBLE); +} RTM_EXPORT(rt_mq_send_wait) +rt_err_t rt_mq_send_wait_interruptible(rt_mq_t mq, + const void *buffer, + rt_size_t size, + rt_int32_t timeout) +{ + return _rt_mq_send_wait(mq, buffer, size, timeout, RT_INTERRUPTIBLE); +} +RTM_EXPORT(rt_mq_send_wait_interruptible) + +rt_err_t rt_mq_send_wait_killable(rt_mq_t mq, + const void *buffer, + rt_size_t size, + rt_int32_t timeout) +{ + return _rt_mq_send_wait(mq, buffer, size, timeout, RT_KILLABLE); +} +RTM_EXPORT(rt_mq_send_wait_killable) /** * This function will send a message to message queue object, if there are * threads suspended on message queue object, it will be waked up. @@ -2226,6 +2413,17 @@ rt_err_t rt_mq_send(rt_mq_t mq, const void *buffer, rt_size_t size) } RTM_EXPORT(rt_mq_send); +rt_err_t rt_mq_send_interrupt(rt_mq_t mq, const void *buffer, rt_size_t size) +{ + return rt_mq_send_wait_interruptible(mq, buffer, size, 0); +} +RTM_EXPORT(rt_mq_send_interrupt); + +rt_err_t rt_mq_send_killable(rt_mq_t mq, const void *buffer, rt_size_t size) +{ + return rt_mq_send_wait_killable(mq, buffer, size, 0); +} +RTM_EXPORT(rt_mq_send_killable); /** * This function will send an urgent message to message queue object, which * means the message will be inserted to the head of message queue. If there @@ -2297,7 +2495,7 @@ rt_err_t rt_mq_urgent(rt_mq_t mq, const void *buffer, rt_size_t size) rt_hw_interrupt_enable(temp); /* enable interrupt */ return -RT_EFULL; /* value overflowed */ } - + /* resume suspended thread */ if (!rt_list_isempty(&mq->parent.suspend_thread)) { @@ -2330,15 +2528,17 @@ RTM_EXPORT(rt_mq_urgent); * * @return the error code */ -rt_err_t rt_mq_recv(rt_mq_t mq, +static rt_err_t _rt_mq_recv(rt_mq_t mq, void *buffer, rt_size_t size, - rt_int32_t timeout) + rt_int32_t timeout, + int suspend_flag) { struct rt_thread *thread; register rt_ubase_t temp; struct rt_mq_message *msg; rt_uint32_t tick_delta; + rt_err_t ret; /* parameter check */ RT_ASSERT(mq != RT_NULL); @@ -2369,7 +2569,7 @@ rt_err_t rt_mq_recv(rt_mq_t mq, RT_DEBUG_IN_THREAD_CONTEXT; /* reset error number in thread */ - thread->error = RT_EOK; + thread->error = -RT_EINTR; /* no waiting, return timeout */ if (timeout == 0) @@ -2383,9 +2583,15 @@ rt_err_t rt_mq_recv(rt_mq_t mq, } /* suspend current thread */ - rt_ipc_list_suspend(&(mq->parent.suspend_thread), + ret = rt_ipc_list_suspend(&(mq->parent.suspend_thread), thread, - mq->parent.parent.flag); + mq->parent.parent.flag, + suspend_flag); + if (ret != RT_EOK) + { + rt_hw_interrupt_enable(temp); + return ret; + } /* has waiting time, start thread timer */ if (timeout > 0) @@ -2475,8 +2681,33 @@ rt_err_t rt_mq_recv(rt_mq_t mq, return RT_EOK; } + +rt_err_t rt_mq_recv(rt_mq_t mq, + void *buffer, + rt_size_t size, + rt_int32_t timeout) +{ + return _rt_mq_recv(mq, buffer, size, timeout, RT_UNINTERRUPTIBLE); +} RTM_EXPORT(rt_mq_recv); +rt_err_t rt_mq_recv_interruptible(rt_mq_t mq, + void *buffer, + rt_size_t size, + rt_int32_t timeout) +{ + return _rt_mq_recv(mq, buffer, size, timeout, RT_INTERRUPTIBLE); +} +RTM_EXPORT(rt_mq_recv_interruptible); + +rt_err_t rt_mq_recv_killable(rt_mq_t mq, + void *buffer, + rt_size_t size, + rt_int32_t timeout) +{ + return _rt_mq_recv(mq, buffer, size, timeout, RT_KILLABLE); +} +RTM_EXPORT(rt_mq_recv_killable); /** * This function can get or set some extra attributions of a message queue * object. diff --git a/src/kservice.c b/src/kservice.c index 0a74f052689a797f6ca6fcd3e0327eea82941a14..a33774b698fc9e51239bb7f8b6c6567f634dde3b 100644 --- a/src/kservice.c +++ b/src/kservice.c @@ -26,6 +26,12 @@ #include #endif +#ifdef RT_USING_LWP +#include +#include +#include +#endif + /* use precision */ #define RT_PRINTF_PRECISION @@ -49,7 +55,7 @@ static rt_device_t _console_device = RT_NULL; */ rt_err_t rt_get_errno(void) { - rt_thread_t tid; + rt_thread_t tid = RT_NULL; if (rt_interrupt_get_nest() != 0) { @@ -59,7 +65,9 @@ rt_err_t rt_get_errno(void) tid = rt_thread_self(); if (tid == RT_NULL) - return __rt_errno; + { + return __rt_errno; + } return tid->error; } @@ -72,7 +80,7 @@ RTM_EXPORT(rt_get_errno); */ void rt_set_errno(rt_err_t error) { - rt_thread_t tid; + rt_thread_t tid = RT_NULL; if (rt_interrupt_get_nest() != 0) { @@ -101,14 +109,18 @@ RTM_EXPORT(rt_set_errno); */ int *_rt_errno(void) { - rt_thread_t tid; + rt_thread_t tid = RT_NULL; if (rt_interrupt_get_nest() != 0) - return (int *)&__rt_errno; + { + return (int *)&__rt_errno; + } tid = rt_thread_self(); if (tid != RT_NULL) - return (int *) & (tid->error); + { + return (int *) & (tid->error); + } return (int *)&__rt_errno; } @@ -137,10 +149,10 @@ void *rt_memset(void *s, int c, rt_ubase_t count) #define UNALIGNED(X) ((long)X & (LBLOCKSIZE - 1)) #define TOO_SMALL(LEN) ((LEN) < LBLOCKSIZE) - unsigned int i; + unsigned int i = 0; char *m = (char *)s; - unsigned long buffer; - unsigned long *aligned_addr; + unsigned long buffer = 0; + unsigned long *aligned_addr = RT_NULL; unsigned int d = c & 0xff; /* To avoid sign extension, copy C to an unsigned variable. */ @@ -161,7 +173,9 @@ void *rt_memset(void *s, int c, rt_ubase_t count) { buffer = 0; for (i = 0; i < LBLOCKSIZE; i ++) - buffer = (buffer << 8) | d; + { + buffer = (buffer << 8) | d; + } } while (count >= LBLOCKSIZE * 4) @@ -211,17 +225,21 @@ void *rt_memcpy(void *dst, const void *src, rt_ubase_t count) { #ifdef RT_USING_TINY_SIZE char *tmp = (char *)dst, *s = (char *)src; - rt_ubase_t len; + rt_ubase_t len = 0; if (tmp <= s || tmp > (s + count)) { while (count--) - *tmp ++ = *s ++; + { + *tmp ++ = *s ++; + } } else { for (len = count; len > 0; len --) - tmp[len - 1] = s[len - 1]; + { + tmp[len - 1] = s[len - 1]; + } } return dst; @@ -235,8 +253,8 @@ void *rt_memcpy(void *dst, const void *src, rt_ubase_t count) char *dst_ptr = (char *)dst; char *src_ptr = (char *)src; - long *aligned_dst; - long *aligned_src; + long *aligned_dst = RT_NULL; + long *aligned_src = RT_NULL; int len = count; /* If the size is small, or either SRC or DST is unaligned, @@ -269,7 +287,9 @@ void *rt_memcpy(void *dst, const void *src, rt_ubase_t count) } while (len--) - *dst_ptr++ = *src_ptr++; + { + *dst_ptr++ = *src_ptr++; + } return dst; #undef UNALIGNED @@ -300,12 +320,16 @@ void *rt_memmove(void *dest, const void *src, rt_ubase_t n) s += n; while (n--) - *(--tmp) = *(--s); + { + *(--tmp) = *(--s); + } } else { while (n--) - *tmp++ = *s++; + { + *tmp++ = *s++; + } } return dest; @@ -323,12 +347,16 @@ RTM_EXPORT(rt_memmove); */ rt_int32_t rt_memcmp(const void *cs, const void *ct, rt_ubase_t count) { - const unsigned char *su1, *su2; + const unsigned char *su1 = RT_NULL, *su2 = RT_NULL; int res = 0; for (su1 = (const unsigned char *)cs, su2 = (const unsigned char *)ct; 0 < count; ++su1, ++su2, count--) + { if ((res = *su1 - *su2) != 0) - break; + { + break; + } + } return res; } @@ -344,17 +372,23 @@ RTM_EXPORT(rt_memcmp); */ char *rt_strstr(const char *s1, const char *s2) { - int l1, l2; + int l1 = 0, l2 = 0; l2 = rt_strlen(s2); if (!l2) - return (char *)s1; + { + return (char *)s1; + } + l1 = rt_strlen(s1); while (l1 >= l2) { l1 --; if (!rt_memcmp(s1, s2, l2)) - return (char *)s1; + { + return (char *)s1; + } + s1 ++; } @@ -372,7 +406,7 @@ RTM_EXPORT(rt_strstr); */ rt_int32_t rt_strcasecmp(const char *a, const char *b) { - int ca, cb; + int ca = 0, cb = 0; do { @@ -411,7 +445,10 @@ char *rt_strncpy(char *dst, const char *src, rt_ubase_t n) { /* NUL pad the remaining n-1 bytes */ while (--n != 0) - *d++ = 0; + { + *d++ = 0; + } + break; } } while (--n != 0); @@ -437,7 +474,10 @@ rt_int32_t rt_strncmp(const char *cs, const char *ct, rt_ubase_t count) while (count) { if ((__res = *cs - *ct++) != 0 || !*cs++) - break; + { + break; + } + count --; } @@ -456,7 +496,7 @@ RTM_EXPORT(rt_strncmp); rt_int32_t rt_strcmp(const char *cs, const char *ct) { while (*cs && *cs == *ct) - { + { cs++; ct++; } @@ -478,7 +518,7 @@ RTM_EXPORT(rt_strcmp); */ rt_size_t rt_strnlen(const char *s, rt_ubase_t maxlen) { - const char *sc; + const char *sc = RT_NULL; for (sc = s; *sc != '\0' && (rt_ubase_t)(sc - s) < maxlen; ++sc) /* nothing */ ; @@ -497,7 +537,7 @@ RTM_EXPORT(rt_strnlen); */ rt_size_t rt_strlen(const char *s) { - const char *sc; + const char *sc = RT_NULL; for (sc = s; *sc != '\0'; ++sc) /* nothing */ ; @@ -520,7 +560,9 @@ char *rt_strdup(const char *s) char *tmp = (char *)rt_malloc(len); if (!tmp) - return RT_NULL; + { + return RT_NULL; + } rt_memcpy(tmp, s, len); @@ -538,7 +580,11 @@ char *strdup(const char *s) __attribute__((alias("rt_strdup"))); void rt_show_version(void) { rt_kprintf("\n \\ | /\n"); +#ifdef RT_USING_SMART + rt_kprintf("- RT - Thread Smart Operating System\n"); +#else rt_kprintf("- RT - Thread Operating System\n"); +#endif rt_kprintf(" / | \\ %d.%d.%d build %s\n", RT_VERSION, RT_SUBVERSION, RT_REVISION, __DATE__); rt_kprintf(" 2006 - 2020 Copyright by rt-thread team\n"); @@ -551,7 +597,7 @@ RTM_EXPORT(rt_show_version); #ifdef RT_PRINTF_LONGLONG rt_inline int divide(long long *n, int base) { - int res; + int res = 0; /* optimized for processor which does not support divide instructions. */ if (base == 10) @@ -570,7 +616,7 @@ rt_inline int divide(long long *n, int base) #else rt_inline int divide(long *n, int base) { - int res; + int res = 0; /* optimized for processor which does not support divide instructions. */ if (base == 10) @@ -592,7 +638,9 @@ rt_inline int skip_atoi(const char **s) { register int i = 0; while (_ISDIGIT(**s)) - i = i * 10 + *((*s)++) - '0'; + { + i = i * 10 + *((*s)++) - '0'; + } return i; } @@ -630,24 +678,26 @@ static char *print_number(char *buf, int type) #endif { - char c, sign; + char c = 0, sign = 0; #ifdef RT_PRINTF_LONGLONG - char tmp[32]; + char tmp[32] = {0}; #else - char tmp[16]; + char tmp[16] = {0}; #endif int precision_bak = precision; - const char *digits; + const char *digits = RT_NULL; static const char small_digits[] = "0123456789abcdef"; static const char large_digits[] = "0123456789ABCDEF"; - register int i; - register int size; + register int i = 0; + register int size = 0; size = s; digits = (type & LARGE) ? large_digits : small_digits; if (type & LEFT) - type &= ~ZEROPAD; + { + type &= ~ZEROPAD; + } c = (type & ZEROPAD) ? '0' : ' '; @@ -661,33 +711,47 @@ static char *print_number(char *buf, num = -num; } else if (type & PLUS) - sign = '+'; + { + sign = '+'; + } else if (type & SPACE) - sign = ' '; + { + sign = ' '; + } } #ifdef RT_PRINTF_SPECIAL if (type & SPECIAL) { if (base == 16) - size -= 2; + { + size -= 2; + } else if (base == 8) - size--; + { + size--; + } } #endif i = 0; if (num == 0) - tmp[i++] = '0'; + { + tmp[i++] = '0'; + } else { while (num != 0) - tmp[i++] = digits[divide(&num, base)]; + { + tmp[i++] = digits[divide(&num, base)]; + } } #ifdef RT_PRINTF_PRECISION if (i > precision) - precision = i; + { + precision = i; + } size -= precision; #else size -= i; @@ -696,12 +760,17 @@ static char *print_number(char *buf, if (!(type & (ZEROPAD | LEFT))) { if ((sign) && (size > 0)) - size--; + { + size--; + } while (size-- > 0) { if (buf < end) - *buf = ' '; + { + *buf = ' '; + } + ++ buf; } } @@ -722,13 +791,19 @@ static char *print_number(char *buf, if (base == 8) { if (buf < end) - *buf = '0'; + { + *buf = '0'; + } + ++ buf; } else if (base == 16) { if (buf < end) - *buf = '0'; + { + *buf = '0'; + } + ++ buf; if (buf < end) { @@ -745,7 +820,10 @@ static char *print_number(char *buf, while (size-- > 0) { if (buf < end) - *buf = c; + { + *buf = c; + } + ++ buf; } } @@ -754,7 +832,10 @@ static char *print_number(char *buf, while (i < precision--) { if (buf < end) - *buf = '0'; + { + *buf = '0'; + } + ++ buf; } #endif @@ -763,14 +844,20 @@ static char *print_number(char *buf, while (i-- > 0 && (precision_bak != 0)) { if (buf < end) - *buf = tmp[i]; + { + *buf = tmp[i]; + } + ++ buf; } while (size-- > 0) { if (buf < end) - *buf = ' '; + { + *buf = ' '; + } + ++ buf; } @@ -783,21 +870,21 @@ rt_int32_t rt_vsnprintf(char *buf, va_list args) { #ifdef RT_PRINTF_LONGLONG - unsigned long long num; + unsigned long long num = 0; #else - rt_uint32_t num; + long num = 0; #endif - int i, len; - char *str, *end, c; - const char *s; + int i = 0, len = 0; + char *str = RT_NULL, *end = RT_NULL, c = 0; + const char *s = RT_NULL; - rt_uint8_t base; /* the base of number */ - rt_uint8_t flags; /* flags to print number */ - rt_uint8_t qualifier; /* 'h', 'l', or 'L' for integer fields */ - rt_int32_t field_width; /* width of output field */ + rt_uint8_t base = 0; /* the base of number */ + rt_uint8_t flags = 0; /* flags to print number */ + rt_uint8_t qualifier = 0; /* 'h', 'l', or 'L' for integer fields */ + rt_int32_t field_width = 0; /* width of output field */ #ifdef RT_PRINTF_PRECISION - int precision; /* min. # of digits for integers and max for a string */ + int precision = 0; /* min. # of digits for integers and max for a string */ #endif str = buf; @@ -815,7 +902,10 @@ rt_int32_t rt_vsnprintf(char *buf, if (*fmt != '%') { if (str < end) - *str = *fmt; + { + *str = *fmt; + } + ++ str; continue; } @@ -837,7 +927,10 @@ rt_int32_t rt_vsnprintf(char *buf, /* get field width */ field_width = -1; - if (_ISDIGIT(*fmt)) field_width = skip_atoi(&fmt); + if (_ISDIGIT(*fmt)) + { + field_width = skip_atoi(&fmt); + } else if (*fmt == '*') { ++ fmt; @@ -856,14 +949,20 @@ rt_int32_t rt_vsnprintf(char *buf, if (*fmt == '.') { ++ fmt; - if (_ISDIGIT(*fmt)) precision = skip_atoi(&fmt); + if (_ISDIGIT(*fmt)) + { + precision = skip_atoi(&fmt); + } else if (*fmt == '*') { ++ fmt; /* it's the next argument */ precision = va_arg(args, int); } - if (precision < 0) precision = 0; + if (precision < 0) + { + precision = 0; + } } #endif /* get the conversion qualifier */ @@ -902,7 +1001,10 @@ rt_int32_t rt_vsnprintf(char *buf, /* get character */ c = (rt_uint8_t)va_arg(args, int); - if (str < end) *str = c; + if (str < end) + { + *str = c; + } ++ str; /* put width */ @@ -915,11 +1017,17 @@ rt_int32_t rt_vsnprintf(char *buf, case 's': s = va_arg(args, char *); - if (!s) s = "(NULL)"; + if (!s) + { + s = "(NULL)"; + } len = rt_strlen(s); #ifdef RT_PRINTF_PRECISION - if (precision > 0 && len > precision) len = precision; + if (precision > 0 && len > precision) + { + len = precision; + } #endif if (!(flags & LEFT)) @@ -963,7 +1071,10 @@ rt_int32_t rt_vsnprintf(char *buf, continue; case '%': - if (str < end) *str = '%'; + if (str < end) + { + *str = '%'; + } ++ str; continue; @@ -985,12 +1096,18 @@ rt_int32_t rt_vsnprintf(char *buf, break; default: - if (str < end) *str = '%'; + if (str < end) + { + *str = '%'; + } ++ str; if (*fmt) { - if (str < end) *str = *fmt; + if (str < end) + { + *str = *fmt; + } ++ str; } else @@ -1001,24 +1118,36 @@ rt_int32_t rt_vsnprintf(char *buf, } #ifdef RT_PRINTF_LONGLONG - if (qualifier == 'L') num = va_arg(args, long long); + if (qualifier == 'L') + { + num = va_arg(args, long long); + } else if (qualifier == 'l') #else if (qualifier == 'l') #endif { - num = va_arg(args, rt_uint32_t); - if (flags & SIGN) num = (rt_int32_t)num; + num = va_arg(args, long); + if (flags & SIGN) + { + num = (rt_int32_t)num; + } } else if (qualifier == 'h') { num = (rt_uint16_t)va_arg(args, rt_int32_t); - if (flags & SIGN) num = (rt_int16_t)num; + if (flags & SIGN) + { + num = (rt_int16_t)num; + } } else { - num = va_arg(args, rt_uint32_t); - if (flags & SIGN) num = (rt_int32_t)num; + num = va_arg(args, long); + if (flags & SIGN) + { + num = (rt_int32_t)num; + } } #ifdef RT_PRINTF_PRECISION str = print_number(str, end, num, base, field_width, precision, flags); @@ -1029,7 +1158,10 @@ rt_int32_t rt_vsnprintf(char *buf, if (size > 0) { - if (str < end) *str = '\0'; + if (str < end) + { + *str = '\0'; + } else { end[-1] = '\0'; @@ -1052,7 +1184,7 @@ RTM_EXPORT(rt_vsnprintf); */ rt_int32_t rt_snprintf(char *buf, rt_size_t size, const char *fmt, ...) { - rt_int32_t n; + rt_int32_t n = 0; va_list args; va_start(args, fmt); @@ -1084,7 +1216,7 @@ RTM_EXPORT(rt_vsprintf); */ rt_int32_t rt_sprintf(char *buf, const char *format, ...) { - rt_int32_t n; + rt_int32_t n = 0; va_list arg_ptr; va_start(arg_ptr, format); @@ -1120,6 +1252,28 @@ RTM_EXPORT(rt_console_get_device); */ rt_device_t rt_console_set_device(const char *name) { +#ifdef RT_USING_LWP + rt_device_t new_iodev = RT_NULL, old_iodev = RT_NULL; +extern void console_init(); + console_init(); /*add line discipline*/ + /* find new console device */ + new_iodev = rt_device_find(name); + if (new_iodev != RT_NULL) + { + if (_console_device != RT_NULL) + { + old_iodev = console_set_iodev(new_iodev); + } + else + { + console_register("console", new_iodev); + _console_device = rt_device_find("console"); + rt_device_open(_console_device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_STREAM); + } + } + + return old_iodev; +#else rt_device_t new_device, old_device; /* save old device */ @@ -1145,6 +1299,7 @@ rt_device_t rt_console_set_device(const char *name) } return old_device; +#endif } RTM_EXPORT(rt_console_set_device); #endif @@ -1162,7 +1317,10 @@ RTM_EXPORT(rt_hw_console_output); */ void rt_kputs(const char *str) { - if (!str) return; + if (!str) + { + return; + } #ifdef RT_USING_DEVICE if (_console_device == RT_NULL) @@ -1190,7 +1348,7 @@ void rt_kputs(const char *str) void rt_kprintf(const char *fmt, ...) { va_list args; - rt_size_t length; + rt_size_t length = 0; static char rt_log_buf[RT_CONSOLEBUF_SIZE]; va_start(args, fmt); @@ -1201,7 +1359,10 @@ void rt_kprintf(const char *fmt, ...) * length. */ length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args); if (length > RT_CONSOLEBUF_SIZE - 1) - length = RT_CONSOLEBUF_SIZE - 1; + { + length = RT_CONSOLEBUF_SIZE - 1; + } + #ifdef RT_USING_DEVICE if (_console_device == RT_NULL) { @@ -1235,10 +1396,10 @@ RTM_EXPORT(rt_kprintf); */ void *rt_malloc_align(rt_size_t size, rt_size_t align) { - void *ptr; - void *align_ptr; - int uintptr_size; - rt_size_t align_size; + void *ptr = RT_NULL; + void *align_ptr = RT_NULL; + int uintptr_size = 0; + rt_size_t align_size = 0; /* sizeof pointer */ uintptr_size = sizeof(void*); @@ -1281,7 +1442,7 @@ RTM_EXPORT(rt_malloc_align); */ void rt_free_align(void *ptr) { - void *real_ptr; + void *real_ptr = RT_NULL; real_ptr = (void *) * (rt_ubase_t *)((rt_ubase_t)ptr - sizeof(void *)); rt_free(real_ptr); @@ -1322,16 +1483,25 @@ const rt_uint8_t __lowest_bit_bitmap[] = */ int __rt_ffs(int value) { - if (value == 0) return 0; + if (value == 0) + { + return 0; + } if (value & 0xff) - return __lowest_bit_bitmap[value & 0xff] + 1; + { + return __lowest_bit_bitmap[value & 0xff] + 1; + } if (value & 0xff00) - return __lowest_bit_bitmap[(value & 0xff00) >> 8] + 9; + { + return __lowest_bit_bitmap[(value & 0xff00) >> 8] + 9; + } if (value & 0xff0000) - return __lowest_bit_bitmap[(value & 0xff0000) >> 16] + 17; + { + return __lowest_bit_bitmap[(value & 0xff0000) >> 16] + 17; + } return __lowest_bit_bitmap[(value & 0xff000000) >> 24] + 25; } diff --git a/src/mem.c b/src/mem.c index c03c8b3452854b6c82ca2e94cc3b2e4e292377ef..d531508ae698b508745fa93f6bf092a6d0ad44f7 100644 --- a/src/mem.c +++ b/src/mem.c @@ -629,12 +629,24 @@ void rt_memory_info(rt_uint32_t *total, } #ifdef RT_USING_FINSH -#include + +#ifdef RT_USING_LWP +#include +#endif +#ifndef ARCH_PAGE_SIZE +#define ARCH_PAGE_SIZE 0 + +#endif void list_mem(void) { - rt_kprintf("total memory: %d\n", mem_size_aligned); - rt_kprintf("used memory : %d\n", used_mem); + size_t total_pages = 0, free_pages = 0; +#ifdef RT_USING_USERSPACE + rt_page_get_info(&total_pages, &free_pages); +#endif + + rt_kprintf("total memory: %d\n", mem_size_aligned + total_pages * ARCH_PAGE_SIZE); + rt_kprintf("used memory : %d\n", used_mem + (total_pages - free_pages) * ARCH_PAGE_SIZE); rt_kprintf("maximum allocated memory: %d\n", max_mem); } FINSH_FUNCTION_EXPORT(list_mem, list memory usage information) diff --git a/src/mempool.c b/src/mempool.c index db614032aa67ac7d357408b9521192c39555adbe..5be9520c94454d2f0c4dbb208c522d303f316d2c 100644 --- a/src/mempool.c +++ b/src/mempool.c @@ -334,7 +334,7 @@ void *rt_mp_alloc(rt_mp_t mp, rt_int32_t time) thread->error = RT_EOK; /* need suspend thread */ - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); rt_list_insert_after(&(mp->suspend_thread), &(thread->tlist)); if (time > 0) diff --git a/src/object.c b/src/object.c index 6866d805ca3064991086741644a1f128b110303a..05dc0c0ef91987a4b0565fd623f32f3b90a53c6f 100644 --- a/src/object.c +++ b/src/object.c @@ -22,6 +22,17 @@ #include #endif +#ifdef RT_USING_LWP +#include +#endif + +struct rt_custom_object +{ + struct rt_object parent; + rt_err_t (*destroy)(void *); + void *data; +}; + /* * define object_info for the number of rt_object_container items. */ @@ -55,6 +66,12 @@ enum rt_object_info_type RT_Object_Info_Timer, /**< The object is a timer. */ #ifdef RT_USING_MODULE RT_Object_Info_Module, /**< The object is a module. */ +#endif +#ifdef RT_USING_LWP + RT_Object_Info_Channel, /**< The object is a IPC channel */ +#endif +#ifdef RT_USING_HEAP + RT_Object_Info_Custom, /**< The object is a custom object */ #endif RT_Object_Info_Unknown, /**< The object is unknown. */ }; @@ -103,6 +120,11 @@ static struct rt_object_information rt_object_container[RT_Object_Info_Unknown] /* initialize object container - module */ {RT_Object_Class_Module, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Module), sizeof(struct rt_dlmodule)}, #endif +#ifdef RT_USING_LWP + /* initialize object container - module */ + {RT_Object_Class_Channel, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Channel), sizeof(struct rt_channel)}, + {RT_Object_Class_Custom, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Custom), sizeof(struct rt_custom_object)}, +#endif }; #ifdef RT_USING_HOOK @@ -212,7 +234,7 @@ void rt_system_object_init(void) /** * This function will return the specified type of object information. * - * @param type the type of object, which can be + * @param type the type of object, which can be * RT_Object_Class_Thread/Semaphore/Mutex... etc * * @return the object type information or RT_NULL @@ -232,7 +254,7 @@ RTM_EXPORT(rt_object_get_information); /** * This function will return the length of object list in object container. * - * @param type the type of object, which can be + * @param type the type of object, which can be * RT_Object_Class_Thread/Semaphore/Mutex... etc * @return the length of object list */ @@ -259,10 +281,10 @@ int rt_object_get_length(enum rt_object_class_type type) RTM_EXPORT(rt_object_get_length); /** - * This function will copy the object pointer of the specified type, + * This function will copy the object pointer of the specified type, * with the maximum size specified by maxlen. * - * @param type the type of object, which can be + * @param type the type of object, which can be * RT_Object_Class_Thread/Semaphore/Mutex... etc * @param pointers the pointers will be saved to * @param maxlen the maximum number of pointers can be saved @@ -585,4 +607,60 @@ rt_object_t rt_object_find(const char *name, rt_uint8_t type) return RT_NULL; } +#ifdef RT_USING_HEAP +/** + * This function will create a custom object + * container. + * + * @param name the specified name of object. + * @param type the type of object + * @param data the custom data + * @param data_destroy the custom object destroy callback + * + * @return the found object or RT_NULL if there is no this object + * in object container. + * + * @note this function shall not be invoked in interrupt status. + */ + +rt_object_t rt_custom_object_create(const char *name, void *data, rt_err_t (*data_destroy)(void *)) +{ + struct rt_custom_object *cobj = RT_NULL; + + cobj = (struct rt_custom_object *)rt_object_allocate(RT_Object_Class_Custom, name); + if (!cobj) + { + return RT_NULL; + } + cobj->destroy = data_destroy; + cobj->data = data; + return (struct rt_object *)cobj; +} + +/** + * This function will destroy a custom object + * container. + * + * @param obj the specified name of object. + * + * @note this function shall not be invoked in interrupt status. + */ +rt_err_t rt_custom_object_destroy(rt_object_t obj) +{ + rt_err_t ret = -1; + + struct rt_custom_object *cobj = (struct rt_custom_object *)obj; + + if (obj && obj->type == RT_Object_Class_Custom) + { + if (cobj->destroy) + { + ret = cobj->destroy(cobj->data); + } + rt_object_delete(obj); + } + return ret; +} +#endif + /**@}*/ diff --git a/src/scheduler.c b/src/scheduler.c index 2250c4a00696152091093e67765332491f7bcddc..faa67ca0049cf921e36d1129f484ec1ee0b4ff59 100644 --- a/src/scheduler.c +++ b/src/scheduler.c @@ -33,6 +33,10 @@ #include #include +#ifdef RT_USING_LWP +#include +#endif /* RT_USING_LWP */ + rt_list_t rt_thread_priority_table[RT_THREAD_PRIORITY_MAX]; rt_uint32_t rt_thread_ready_priority_group; #if RT_THREAD_PRIORITY_MAX > 32 @@ -47,10 +51,9 @@ struct rt_thread *rt_current_thread; rt_uint8_t rt_current_priority; #endif /*RT_USING_SMP*/ -rt_list_t rt_thread_defunct; - #ifdef RT_USING_HOOK static void (*rt_scheduler_hook)(struct rt_thread *from, struct rt_thread *to); +static void (*rt_scheduler_switch_hook)(struct rt_thread *tid); /** * @addtogroup Hook @@ -70,6 +73,11 @@ rt_scheduler_sethook(void (*hook)(struct rt_thread *from, struct rt_thread *to)) rt_scheduler_hook = hook; } +void +rt_scheduler_switch_sethook(void (*hook)(struct rt_thread *tid)) +{ + rt_scheduler_switch_hook = hook; +} /**@}*/ #endif @@ -78,6 +86,19 @@ static void _rt_scheduler_stack_check(struct rt_thread *thread) { RT_ASSERT(thread != RT_NULL); +#ifdef RT_USING_LWP +#ifndef ARCH_MM_MMU + struct rt_lwp *lwp = thread ? (struct rt_lwp *)thread->lwp : 0; + + /* if stack pointer locate in user data section skip stack check. */ + if (lwp && ((rt_uint32_t)thread->sp > (rt_uint32_t)lwp->data_entry && + (rt_uint32_t)thread->sp <= (rt_uint32_t)lwp->data_entry + (rt_uint32_t)lwp->data_size)) + { + return; + } +#endif /* not defined ARCH_MM_MMU */ +#endif /* RT_USING_LWP */ + #if defined(ARCH_CPU_STACK_GROWS_UPWARD) if (*((rt_uint8_t *)((rt_ubase_t)thread->stack_addr + thread->stack_size - 1)) != '#' || #else @@ -229,9 +250,6 @@ void rt_system_scheduler_init(void) /* initialize ready table */ rt_memset(rt_thread_ready_table, 0, sizeof(rt_thread_ready_table)); #endif - - /* initialize thread defunct */ - rt_list_init(&rt_thread_defunct); } /** @@ -275,10 +293,10 @@ void rt_system_scheduler_start(void) #ifdef RT_USING_SMP /** * This function will handle IPI interrupt and do a scheduling in system; - * + * * @param vector, the number of IPI interrupt for system scheduling * @param param, use RT_NULL - * + * * NOTE: this function should be invoke or register as ISR in BSP. */ void rt_scheduler_ipi_handler(int vector, void *param) @@ -288,7 +306,7 @@ void rt_scheduler_ipi_handler(int vector, void *param) /** * This function will perform one scheduling. It will select one thread - * with the highest priority level in global ready queue or local ready queue, + * with the highest priority level in global ready queue or local ready queue, * then switch to it. */ void rt_schedule(void) @@ -315,13 +333,17 @@ void rt_schedule(void) } #ifdef RT_USING_SIGNALS - if ((current_thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND) + if ((current_thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) { /* if current_thread signal is in pending */ if ((current_thread->stat & RT_THREAD_STAT_SIGNAL_MASK) & RT_THREAD_STAT_SIGNAL_PENDING) { +#ifdef RT_USING_LWP + rt_thread_wakeup(current_thread); +#else rt_thread_resume(current_thread); +#endif } } #endif @@ -373,7 +395,7 @@ void rt_schedule(void) #ifdef RT_USING_OVERFLOW_CHECK _rt_scheduler_stack_check(to_thread); #endif - + RT_OBJECT_HOOK_CALL(rt_scheduler_switch_hook, (current_thread)); rt_hw_context_switch((rt_ubase_t)¤t_thread->sp, (rt_ubase_t)&to_thread->sp, to_thread); } @@ -479,6 +501,7 @@ void rt_schedule(void) _rt_scheduler_stack_check(to_thread); #endif + RT_OBJECT_HOOK_CALL(rt_scheduler_switch_hook, (from_thread)); if (rt_interrupt_nest == 0) { extern void rt_thread_handle_sig(rt_bool_t clean_state); @@ -515,7 +538,7 @@ void rt_schedule(void) RT_DEBUG_LOG(RT_DEBUG_SCHEDULER, ("switch in interrupt\n")); rt_hw_context_switch_interrupt((rt_ubase_t)&from_thread->sp, - (rt_ubase_t)&to_thread->sp); + (rt_ubase_t)&to_thread->sp, from_thread, to_thread); } } else @@ -555,13 +578,17 @@ void rt_scheduler_do_irq_switch(void *context) current_thread = pcpu->current_thread; #ifdef RT_USING_SIGNALS - if ((current_thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND) + if ((current_thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) { /* if current_thread signal is in pending */ if ((current_thread->stat & RT_THREAD_STAT_SIGNAL_MASK) & RT_THREAD_STAT_SIGNAL_PENDING) { +#ifdef RT_USING_LWP + rt_thread_wakeup(current_thread); +#else rt_thread_resume(current_thread); +#endif } } #endif @@ -854,7 +881,6 @@ void rt_enter_critical(void) * the maximal number of nest is RT_UINT16_MAX, which is big * enough and does not check here */ - { register rt_uint16_t lock_nest = current_thread->cpus_lock_nest; current_thread->cpus_lock_nest++; diff --git a/src/signal.c b/src/signal.c index bb9339ab6c3f216cdaa5ab3569aa70543d415232..cef7e853352f0062929f8688f59233b792af582b 100644 --- a/src/signal.c +++ b/src/signal.c @@ -102,10 +102,14 @@ static void _signal_deliver(rt_thread_t tid) return; } - if ((tid->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND) + if ((tid->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) { /* resume thread to handle signal */ +#ifdef RT_USING_LWP + rt_thread_wakeup(tid); +#else rt_thread_resume(tid); +#endif /* add signal state */ tid->stat |= (RT_THREAD_STAT_SIGNAL | RT_THREAD_STAT_SIGNAL_PENDING); @@ -197,7 +201,7 @@ void *rt_signal_check(void* context) rt_hw_interrupt_enable(level); sig_context = rt_hw_stack_init((void *)_signal_entry, context, - (void *)(context - 32), RT_NULL); + (void*)((char*)context - 32), RT_NULL); return sig_context; } } @@ -298,7 +302,7 @@ int rt_signal_wait(const rt_sigset_t *set, rt_siginfo_t *si, rt_int32_t timeout) } /* suspend self thread */ - rt_thread_suspend(tid); + rt_thread_suspend_with_flag(tid, RT_UNINTERRUPTIBLE); /* set thread stat as waiting for signal */ tid->stat |= RT_THREAD_STAT_SIGNAL_WAIT; diff --git a/src/thread.c b/src/thread.c index 49e2022bf7a275a302ff0b0efd5e5894e4ece15a..2027852e45e584f032cf4219dd2f6f8141e9054d 100644 --- a/src/thread.c +++ b/src/thread.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,8 +31,6 @@ #include #include -extern rt_list_t rt_thread_defunct; - #ifdef RT_USING_HOOK static void (*rt_thread_suspend_hook)(rt_thread_t thread); static void (*rt_thread_resume_hook) (rt_thread_t thread); @@ -104,7 +102,7 @@ void rt_thread_exit(void) else { /* insert to defunct thread list */ - rt_list_insert_after(&rt_thread_defunct, &(thread->tlist)); + rt_thread_defunct_enqueue(thread); } /* switch to next task */ @@ -126,6 +124,10 @@ static rt_err_t _rt_thread_init(struct rt_thread *thread, /* init thread list */ rt_list_init(&(thread->tlist)); +#ifdef RT_USING_LWP + thread->wakeup.func = RT_NULL; +#endif + thread->entry = (void *)entry; thread->parameter = parameter; @@ -201,6 +203,12 @@ static rt_err_t _rt_thread_init(struct rt_thread *thread, #ifdef RT_USING_LWP thread->lwp = RT_NULL; + rt_list_init(&(thread->sibling)); + rt_memset(&thread->signal, 0, sizeof(lwp_sigset_t)); + rt_memset(&thread->signal_mask, 0, sizeof(lwp_sigset_t)); + thread->signal_mask_bak = 0; + thread->signal_in_process = 0; + rt_memset(&thread->user_ctx, 0, sizeof thread->user_ctx); #endif RT_OBJECT_HOOK_CALL(rt_thread_inited_hook, (thread)); @@ -363,7 +371,7 @@ rt_err_t rt_thread_detach(rt_thread_t thread) /* disable interrupt */ lock = rt_hw_interrupt_disable(); /* insert to defunct thread list */ - rt_list_insert_after(&rt_thread_defunct, &(thread->tlist)); + rt_thread_defunct_enqueue(thread); /* enable interrupt */ rt_hw_interrupt_enable(lock); } @@ -459,7 +467,7 @@ rt_err_t rt_thread_delete(rt_thread_t thread) thread->stat = RT_THREAD_CLOSE; /* insert to defunct thread list */ - rt_list_insert_after(&rt_thread_defunct, &(thread->tlist)); + rt_thread_defunct_enqueue(thread); /* enable interrupt */ rt_hw_interrupt_enable(lock); @@ -478,15 +486,18 @@ RTM_EXPORT(rt_thread_delete); */ rt_err_t rt_thread_yield(void) { + rt_base_t level; struct rt_thread *thread; - rt_base_t lock; thread = rt_thread_self(); - lock = rt_hw_interrupt_disable(); + + level = rt_hw_interrupt_disable(); + thread->remaining_tick = thread->init_tick; thread->stat |= RT_THREAD_STAT_YIELD; + rt_schedule(); - rt_hw_interrupt_enable(lock); + rt_hw_interrupt_enable(level); return RT_EOK; } @@ -513,7 +524,7 @@ rt_err_t rt_thread_sleep(rt_tick_t tick) temp = rt_hw_interrupt_disable(); /* suspend thread */ - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_INTERRUPTIBLE); /* reset the timeout of thread timer and start it */ rt_timer_control(&(thread->thread_timer), RT_TIMER_CTRL_SET_TIME, &tick); @@ -572,7 +583,7 @@ rt_err_t rt_thread_delay_until(rt_tick_t *tick, rt_tick_t inc_tick) *tick = *tick + inc_tick - rt_tick_get(); /* suspend thread */ - rt_thread_suspend(thread); + rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); /* reset the timeout of thread timer and start it */ rt_timer_control(&(thread->thread_timer), RT_TIMER_CTRL_SET_TIME, tick); @@ -724,17 +735,45 @@ rt_err_t rt_thread_control(rt_thread_t thread, int cmd, void *arg) } RTM_EXPORT(rt_thread_control); +#ifdef RT_USING_LWP +int lwp_suspend_sigcheck(rt_thread_t thread, int suspend_flag); +#endif + +static void rt_thread_set_suspend_state(struct rt_thread *thread, int suspend_flag) +{ + rt_uint8_t stat = RT_THREAD_SUSPEND_UNINTERRUPTIBLE; + + RT_ASSERT(thread != RT_NULL); + switch (suspend_flag) + { + case RT_INTERRUPTIBLE: + stat = RT_THREAD_SUSPEND_INTERRUPTIBLE; + break; + case RT_KILLABLE: + stat = RT_THREAD_SUSPEND_KILLABLE; + break; + case RT_UNINTERRUPTIBLE: + stat = RT_THREAD_SUSPEND_UNINTERRUPTIBLE; + break; + default: + RT_ASSERT(0); + break; + } + thread->stat = stat | (thread->stat & ~RT_THREAD_STAT_MASK); +} + /** * This function will suspend the specified thread. * * @param thread the thread to be suspended + * @param suspend_flag status flag of the thread to be suspended * * @return the operation status, RT_EOK on OK, -RT_ERROR on error * * @note if suspend self thread, after this function call, the * rt_schedule() must be invoked. */ -rt_err_t rt_thread_suspend(rt_thread_t thread) +rt_err_t rt_thread_suspend_with_flag(rt_thread_t thread, int suspend_flag) { register rt_base_t stat; register rt_base_t temp; @@ -760,10 +799,18 @@ rt_err_t rt_thread_suspend(rt_thread_t thread) /* not suspend running status thread on other core */ RT_ASSERT(thread == rt_thread_self()); } +#ifdef RT_USING_LWP + if (lwp_suspend_sigcheck(thread, suspend_flag) == 0) + { + /* not to suspend */ + rt_hw_interrupt_enable(temp); + return -RT_EINTR; + } +#endif /* change thread stat */ rt_schedule_remove_thread(thread); - thread->stat = RT_THREAD_SUSPEND | (thread->stat & ~RT_THREAD_STAT_MASK); + rt_thread_set_suspend_state(thread, suspend_flag); /* stop thread timer anyway */ rt_timer_stop(&(thread->thread_timer)); @@ -774,8 +821,15 @@ rt_err_t rt_thread_suspend(rt_thread_t thread) RT_OBJECT_HOOK_CALL(rt_thread_suspend_hook, (thread)); return RT_EOK; } +RTM_EXPORT(rt_thread_suspend_with_flag); + +rt_err_t rt_thread_suspend(rt_thread_t thread) +{ + return rt_thread_suspend_with_flag(thread, RT_UNINTERRUPTIBLE); +} RTM_EXPORT(rt_thread_suspend); + /** * This function will resume a thread and put it to system ready queue. * @@ -793,7 +847,7 @@ rt_err_t rt_thread_resume(rt_thread_t thread) RT_DEBUG_LOG(RT_DEBUG_THREAD, ("thread resume: %s\n", thread->name)); - if ((thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_SUSPEND) + if ((thread->stat & RT_THREAD_SUSPEND_MASK) != RT_THREAD_SUSPEND_MASK) { RT_DEBUG_LOG(RT_DEBUG_THREAD, ("thread resume: thread disorder, %d\n", thread->stat)); @@ -809,6 +863,10 @@ rt_err_t rt_thread_resume(rt_thread_t thread) rt_timer_stop(&thread->thread_timer); +#ifdef RT_USING_LWP + thread->wakeup.func = RT_NULL; +#endif + /* enable interrupt */ rt_hw_interrupt_enable(temp); @@ -820,6 +878,53 @@ rt_err_t rt_thread_resume(rt_thread_t thread) } RTM_EXPORT(rt_thread_resume); +#ifdef RT_USING_LWP +/** + * This function will wakeup a thread with customized operation. + * + * @param thread the thread to be resumed + * + * @return the operation status, RT_EOK on OK, -RT_ERROR on error + */ +rt_err_t rt_thread_wakeup(rt_thread_t thread) +{ + register rt_base_t temp; + rt_err_t ret; + + RT_ASSERT(thread != RT_NULL); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + if (thread->wakeup.func) + { + ret = thread->wakeup.func(thread->wakeup.user_data, thread); + thread->wakeup.func = RT_NULL; + } + else + { + ret = rt_thread_resume(thread); + } + + rt_hw_interrupt_enable(temp); + return ret; +} +RTM_EXPORT(rt_thread_wakeup); + +void rt_thread_wakeup_set(struct rt_thread *thread, rt_wakeup_func_t func, void* user_data) +{ + register rt_base_t temp; + + RT_ASSERT(thread != RT_NULL); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + + temp = rt_hw_interrupt_disable(); + thread->wakeup.func = func; + thread->wakeup.user_data = user_data; + rt_hw_interrupt_enable(temp); +} +RTM_EXPORT(rt_thread_wakeup_set); +#endif + /** * This function is the timeout function for thread, normally which is invoked * when thread is timeout to wait some resource. @@ -834,7 +939,7 @@ void rt_thread_timeout(void *parameter) /* thread check */ RT_ASSERT(thread != RT_NULL); - RT_ASSERT((thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND); + RT_ASSERT((thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK); RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); /* set error number */ diff --git a/src/timer.c b/src/timer.c index 4b9003794c0fc2c5aa928150081cafdc51cab965..838d1c2d1fbd2e1b7cbc5d3115cd2c108801c654 100644 --- a/src/timer.c +++ b/src/timer.c @@ -331,7 +331,6 @@ rt_err_t rt_timer_start(rt_timer_t timer) _rt_timer_remove(timer); /* change status of timer */ timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; - rt_hw_interrupt_enable(level); RT_OBJECT_HOOK_CALL(rt_object_take_hook, (&(timer->parent))); @@ -342,9 +341,6 @@ rt_err_t rt_timer_start(rt_timer_t timer) RT_ASSERT(timer->init_tick < RT_TICK_MAX / 2); timer->timeout_tick = rt_tick_get() + timer->init_tick; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - #ifdef RT_USING_TIMER_SOFT if (timer->parent.flag & RT_TIMER_FLAG_SOFT_TIMER) { @@ -419,7 +415,7 @@ rt_err_t rt_timer_start(rt_timer_t timer) { /* check whether timer thread is ready */ if ((soft_timer_status == RT_SOFT_TIMER_IDLE) && - ((timer_thread.stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND)) + ((timer_thread.stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK)) { /* resume timer thread to check soft timer */ rt_thread_resume(&timer_thread); @@ -443,18 +439,21 @@ rt_err_t rt_timer_stop(rt_timer_t timer) { register rt_base_t level; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + /* timer check */ RT_ASSERT(timer != RT_NULL); RT_ASSERT(rt_object_get_type(&timer->parent) == RT_Object_Class_Timer); if (!(timer->parent.flag & RT_TIMER_FLAG_ACTIVATED)) + { + rt_hw_interrupt_enable(level); return -RT_ERROR; + } RT_OBJECT_HOOK_CALL(rt_object_put_hook, (&(timer->parent))); - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - _rt_timer_remove(timer); /* change status */ timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; @@ -514,6 +513,21 @@ rt_err_t rt_timer_control(rt_timer_t timer, int cmd, void *arg) *(rt_tick_t *)arg = RT_TIMER_FLAG_DEACTIVATED; } break; + case RT_TIMER_CTRL_GET_FUNC: + *(void **)arg = timer->timeout_func; + break; + + case RT_TIMER_CTRL_SET_FUNC: + timer->timeout_func = (void (*)(void*))arg; + break; + + case RT_TIMER_CTRL_GET_PARM: + *(void **)arg = timer->parameter; + break; + + case RT_TIMER_CTRL_SET_PARM: + timer->parameter = arg; + break; default: break; @@ -580,6 +594,7 @@ void rt_timer_check(void) continue; } + rt_list_remove(&(t->row[RT_TIMER_SKIP_LIST_LEVEL - 1])); if ((t->parent.flag & RT_TIMER_FLAG_PERIODIC) && (t->parent.flag & RT_TIMER_FLAG_ACTIVATED)) { @@ -668,6 +683,7 @@ void rt_soft_timer_check(void) continue; } + rt_list_remove(&(t->row[RT_TIMER_SKIP_LIST_LEVEL - 1])); if ((t->parent.flag & RT_TIMER_FLAG_PERIODIC) && (t->parent.flag & RT_TIMER_FLAG_ACTIVATED)) { @@ -696,7 +712,7 @@ static void rt_thread_timer_entry(void *parameter) if (next_timeout == RT_TICK_MAX) { /* no software timer exist, suspend self. */ - rt_thread_suspend(rt_thread_self()); + rt_thread_suspend_with_flag(rt_thread_self(), RT_UNINTERRUPTIBLE); rt_schedule(); } else diff --git a/tools/building.py b/tools/building.py index 1de54e236b685ac546de5e304fb5f84c8e8b2b9f..026dd10d0cfa3f2d799ce616544f7e31b0957d39 100644 --- a/tools/building.py +++ b/tools/building.py @@ -1,7 +1,7 @@ # # File : building.py # This file is part of RT-Thread RTOS -# COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team +# COPYRIGHT (C) 2006 - 2021, RT-Thread Development Team # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -22,6 +22,7 @@ # 2015-01-20 Bernard Add copyright information # 2015-07-25 Bernard Add LOCAL_CCFLAGS/LOCAL_CPPPATH/LOCAL_CPPDEFINES for # group definition. +# 2021-02-06 lizhirui Add dump support # import os @@ -229,6 +230,12 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [ default = False, help = 'print verbose information during build') + AddOption('--dump', + dest = 'dump', + action = 'store_true', + default = False, + help = 'dump assembler file') + Env = env Rtt_Root = os.path.abspath(root_directory) @@ -275,9 +282,6 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [ except KeyError: print ('Unknow target: '+ tgt_name+'. Avaible targets: ' +', '.join(tgt_dict.keys())) sys.exit(1) - elif (GetDepend('RT_USING_NEWLIB') == False and GetDepend('RT_USING_NOLIBC') == False) \ - and rtconfig.PLATFORM == 'gcc': - AddDepend('RT_USING_MINILIBC') # auto change the 'RTT_EXEC_PATH' when 'rtconfig.EXEC_PATH' get failed if not os.path.exists(rtconfig.EXEC_PATH): @@ -331,11 +335,17 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [ # parse rtconfig.h to get used component PreProcessor = PatchedPreProcessor() - f = open('rtconfig.h', 'r') - contents = f.read() - f.close() - PreProcessor.process_contents(contents) - BuildOptions = PreProcessor.cpp_namespace + try: + f = open('rtconfig.h', 'r') + contents = f.read() + f.close() + PreProcessor.process_contents(contents) + BuildOptions = PreProcessor.cpp_namespace + except: + pass + + if rtconfig.PLATFORM == 'gcc' and not GetDepend('RT_USING_LIBC'): + AddDepend('RT_USING_MINILIBC') # use minilibc if GetOption('clang-analyzer'): # perform what scan-build does @@ -889,6 +899,10 @@ def EndBuilding(target, program = None): Env['dist_handle'] = rtconfig.dist_handle Env.AddPostAction(target, rtconfig.POST_ACTION) + + if hasattr(rtconfig, 'DUMP_ACTION') and GetOption('dump'): + Env.AddPostAction(target, rtconfig.DUMP_ACTION) + # Add addition clean files Clean(target, 'cconfig.h') Clean(target, 'rtua.py') diff --git a/tools/gcc.py b/tools/gcc.py index 8c9685d52b9a9811c367ca26e95331a012f0deca..6c31a279f71ee09876b150c43ea924ecd14e0f53 100644 --- a/tools/gcc.py +++ b/tools/gcc.py @@ -86,10 +86,29 @@ def GetNewLibVersion(rtconfig): f.close() return version +def CheckMUSLLibc(): + try: + f = open(".config") + if f: + for line in f: + if line.find('CONFIG_RT_USING_MUSL=y') != -1: + return True + + f.close() + else: + print("open .config failed") + + return False + except Exception as e: + pass + + return False + def GCCResult(rtconfig, str): import subprocess result = '' + use_musl = CheckMUSLLibc() def checkAndGetResult(pattern, string): if re.search(pattern, string): @@ -149,16 +168,19 @@ def GCCResult(rtconfig, str): if re.findall('pthread_create', line): posix_thread = 1 + if use_musl: + result += '#define HAVE_SYS_SELECT_H 1\n\n' + if have_fdset: result += '#define HAVE_FDSET 1\n' - if have_sigaction: + if have_sigaction or use_musl: result += '#define HAVE_SIGACTION 1\n' - if have_sigevent: + if have_sigevent or use_musl: result += '#define HAVE_SIGEVENT 1\n' - if have_siginfo: + if have_siginfo or use_musl: result += '#define HAVE_SIGINFO 1\n' - if have_sigval: + if have_sigval or use_musl: result += '#define HAVE_SIGVAL 1\n' if version: