From d5414a50b9a691641937d7d856690e7fc47c18e5 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Thu, 26 Nov 2020 09:08:23 +0800 Subject: [PATCH 1/3] fixed tick inaccuracy --- bsp/raspberry-pi/raspi4-32/driver/board.c | 15 ++++++++++----- bsp/raspberry-pi/raspi4-32/driver/mbox.h | 11 +++++++++++ 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.c b/bsp/raspberry-pi/raspi4-32/driver/board.c index 3afaba5e3b..a06cddb215 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/board.c +++ b/bsp/raspberry-pi/raspi4-32/driver/board.c @@ -73,21 +73,26 @@ void rt_hw_timer_isr(int vector, void *parameter) void rt_hw_timer_init(void) { - rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_umask(ARM_TIMER_IRQ); + rt_uint32_t apb_clock = 0; + rt_uint32_t timer_clock = 1000000; /* timer_clock = apb_clock/(pre_divider + 1) */ - ARM_TIMER_PREDIV = (250 - 1); + apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID); + ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1); ARM_TIMER_RELOAD = 0; ARM_TIMER_LOAD = 0; ARM_TIMER_IRQCLR = 0; ARM_TIMER_CTRL = 0; - ARM_TIMER_RELOAD = 10000; - ARM_TIMER_LOAD = 10000; + ARM_TIMER_RELOAD = 1000000/RT_TICK_PER_SECOND; + ARM_TIMER_LOAD = 1000000/RT_TICK_PER_SECOND; /* 23-bit counter, enable interrupt, enable timer */ ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7); + + rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(ARM_TIMER_IRQ); + } void idle_wfi(void) diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.h b/bsp/raspberry-pi/raspi4-32/driver/mbox.h index 75993eccbc..eae6572503 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/mbox.h +++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.h @@ -136,6 +136,17 @@ enum { #define MBOX_ADDR 0x08000000 extern uint32_t mbox_addr; +#define RES_CLK_ID (0x000000000) +#define EMMC_CLK_ID (0x000000001) +#define UART_CLK_ID (0x000000002) +#define ARM_CLK_ID (0x000000003) +#define CORE_CLK_ID (0x000000004) +#define V3D_CLK_ID (0x000000005) +#define H264_CLK_ID (0x000000006) +#define ISP_CLK_ID (0x000000007) +#define SDRAM_CLK_ID (0x000000008) +#define PIXEL_CLK_ID (0x000000009) +#define PWM_CLK_ID (0x00000000a) int mbox_call(unsigned char ch, int mmu_enable); int bcm271x_notify_reboot(void); -- Gitee From 644005c58a57c4eb4a320b313d3e2e13fc5949de Mon Sep 17 00:00:00 2001 From: bigmagic Date: Thu, 26 Nov 2020 09:10:52 +0800 Subject: [PATCH 2/3] add tick pre --- bsp/raspberry-pi/raspi4-32/.config | 24 ++++++++++++++++++------ bsp/raspberry-pi/raspi4-32/rtconfig.h | 7 +++++-- 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/bsp/raspberry-pi/raspi4-32/.config b/bsp/raspberry-pi/raspi4-32/.config index 364c5fd8ca..c7fa97fc47 100644 --- a/bsp/raspberry-pi/raspi4-32/.config +++ b/bsp/raspberry-pi/raspi4-32/.config @@ -15,7 +15,7 @@ CONFIG_RT_ALIGN_SIZE=4 CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y @@ -69,8 +69,10 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=512 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_VER_NUM=0x40003 -CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CACHE=y # CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_MMU=y CONFIG_RT_USING_USERSPACE=y CONFIG_KERNEL_VADDR_START=0xc0000000 @@ -79,8 +81,6 @@ CONFIG_RT_IOREMAP_LATE=y CONFIG_ARCH_ARM_CORTEX_A=y # CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set CONFIG_ARCH_ARMV8=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -CONFIG_RT_USING_CACHE=y # # RT-Thread Components @@ -166,6 +166,7 @@ CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -210,7 +211,6 @@ CONFIG_RT_USING_WDT=y CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_NEWLIB is not set CONFIG_RT_USING_MUSL=y -# CONFIG_RT_USING_MUSL_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set CONFIG_RT_USING_POSIX=y CONFIG_RT_USING_POSIX_MMAP=y @@ -328,7 +328,6 @@ CONFIG_RT_LWP_MAX_NR=30 CONFIG_RT_CH_MSG_MAX_NR=1024 CONFIG_RT_LWP_SHM_MAX_NR=64 CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 -# CONFIG_LWP_USING_CORE_DUMP is not set # # RT-Thread online packages @@ -438,6 +437,7 @@ CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set # CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set # # tools packages @@ -486,7 +486,15 @@ CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 # CONFIG_PKG_USING_RAMDISK is not set # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set # @@ -542,6 +550,7 @@ CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set # # miscellaneous packages @@ -571,6 +580,7 @@ CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_NNOM is not set # CONFIG_PKG_USING_LIBANN is not set # CONFIG_PKG_USING_ELAPACK is not set @@ -622,6 +632,8 @@ CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 # CONFIG_PKG_USING_DCM is not set # CONFIG_PKG_USING_EMQ is not set # CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_VIRTUAL_DEVICE is not set CONFIG_BCM2711_SOC=y # CONFIG_BSP_SUPPORT_FPU is not set diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.h b/bsp/raspberry-pi/raspi4-32/rtconfig.h index 4f5065c629..f91646ec51 100644 --- a/bsp/raspberry-pi/raspi4-32/rtconfig.h +++ b/bsp/raspberry-pi/raspi4-32/rtconfig.h @@ -11,7 +11,7 @@ #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK @@ -46,6 +46,7 @@ #define RT_CONSOLEBUF_SIZE 512 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_VER_NUM 0x40003 +#define RT_USING_CACHE #define ARCH_ARM #define ARCH_ARM_MMU #define RT_USING_USERSPACE @@ -54,7 +55,6 @@ #define RT_IOREMAP_LATE #define ARCH_ARM_CORTEX_A #define ARCH_ARMV8 -#define RT_USING_CACHE /* RT-Thread Components */ @@ -251,6 +251,9 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ -- Gitee From 8ac1e0446f7d0384d7a8b8c98cc4dcfdcc4ed256 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Thu, 26 Nov 2020 09:13:38 +0800 Subject: [PATCH 3/3] fixed eth driver rx count overflow --- bsp/raspberry-pi/raspi4-32/driver/drv_eth.c | 149 ++++++++++++------- bsp/raspberry-pi/raspi4-32/driver/drv_eth.h | 11 ++ bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c | 4 +- bsp/raspberry-pi/raspi4-32/driver/raspi4.h | 2 + 4 files changed, 114 insertions(+), 52 deletions(-) diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c index ae41f01620..20ae855b6c 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c @@ -19,6 +19,8 @@ #include "raspi4.h" #include "drv_eth.h" +//#define ETH_RX_POLL + #define DBG_LEVEL DBG_LOG #include #define LOG_TAG "drv.eth" @@ -76,19 +78,36 @@ static inline void write32(void *addr, rt_uint32_t value) (*((volatile unsigned int*)(addr))) = value; } -void eth_rx_irq(void *param) +static void eth_rx_irq(int irq, void *param) { +#ifndef ETH_RX_POLL + rt_uint32_t val = 0; + val = read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT); + val &= ~read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT_MASK); + write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR, val); + if (val & GENET_IRQ_RXDMA_DONE) + { + eth_device_ready(ð_dev.parent); + } + + if (val & GENET_IRQ_TXDMA_DONE) + { + //todo + } +#else eth_device_ready(ð_dev.parent); +#endif } /* We only support RGMII (as used on the RPi4). */ static int bcmgenet_interface_set(void) { int phy_mode = PHY_INTERFACE_MODE_RGMII; - switch (phy_mode) { + switch (phy_mode) + { case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_RXID: - write32(mac_reg_base_addr + SYS_PORT_CTRL,PORT_MODE_EXT_GPHY); + write32(mac_reg_base_addr + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY); break; default: rt_kprintf("unknown phy mode: %d\n", mac_reg_base_addr); @@ -105,10 +124,10 @@ static void bcmgenet_umac_reset(void) write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); reg &= ~BIT(1); - write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL),reg); + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg); DELAY_MICROS(10); - write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL),0); + write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), 0); DELAY_MICROS(10); write32(mac_reg_base_addr + UMAC_CMD, 0); write32(mac_reg_base_addr + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN)); @@ -156,7 +175,7 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va { int count = 10000; rt_uint32_t val; - val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |(reg << MDIO_REG_SHIFT) | (0xffff & value); + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT) | (0xffff & value); write32(mac_reg_base_addr + MDIO_CMD, val); rt_uint32_t reg_val = read32(mac_reg_base_addr + MDIO_CMD); @@ -169,7 +188,6 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va reg_val = read32(mac_reg_base_addr + MDIO_CMD); return reg_val & 0xffff; - } static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg) @@ -190,7 +208,7 @@ static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg) reg_val = read32(mac_reg_base_addr + MDIO_CMD); - return reg_val & 0xffff; + return reg_val & 0xffff; } static int bcmgenet_gmac_write_hwaddr(void) @@ -218,7 +236,7 @@ static int get_ethernet_uid(void) uid_low = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_LOW); uid = (uid_high << 16 | uid_low); - if(BCM54213PE_VERSION_B1 == uid) + if (BCM54213PE_VERSION_B1 == uid) { LOG_I("version is B1\n"); } @@ -230,7 +248,7 @@ static void bcmgenet_mdio_init(void) rt_uint32_t ret = 0; /*get ethernet uid*/ ret = get_ethernet_uid(); - if(ret == 0) + if (ret == 0) { return; } @@ -255,13 +273,13 @@ static void bcmgenet_mdio_init(void) bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL); /* set mii control */ - bcmgenet_mdio_write(1,BCM54213PE_MII_CONTROL,(MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART| MII_CONTROL_PHY_FULL_DUPLEX| MII_CONTROL_SPEED_SELECTION)); + bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, (MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART | MII_CONTROL_PHY_FULL_DUPLEX | MII_CONTROL_SPEED_SELECTION)); } static void rx_ring_init(void) { write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); - write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_START_ADDR,0x0 ); + write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); write32(mac_reg_base_addr + RDMA_READ_PTR, 0x0); write32(mac_reg_base_addr + RDMA_WRITE_PTR, 0x0); write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1); @@ -270,7 +288,7 @@ static void rx_ring_init(void) write32(mac_reg_base_addr + RDMA_CONS_INDEX, 0x0); write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); write32(mac_reg_base_addr + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE); - write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q); + write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); } static void tx_ring_init(void) @@ -281,13 +299,13 @@ static void tx_ring_init(void) write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0); write32(mac_reg_base_addr + TDMA_WRITE_PTR, 0x0); - write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_END_ADDR,TX_DESCS * DMA_DESC_SIZE / 4 - 1); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1); write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0x0); write32(mac_reg_base_addr + TDMA_CONS_INDEX, 0x0); - write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH,0x1); - write32(mac_reg_base_addr + TDMA_FLOW_PERIOD,0x0); + write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1); + write32(mac_reg_base_addr + TDMA_FLOW_PERIOD, 0x0); write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); - write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q); + write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q); } static void rx_descs_init(void) @@ -297,10 +315,11 @@ static void rx_descs_init(void) void *desc_base = (void *)RX_DESC_BASE; len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; - for (i = 0; i < RX_DESCS; i++) { + for (i = 0; i < RX_DESCS; i++) + { write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO), lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); - write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI),upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); - write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS),len_stat); + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI), upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS), len_stat); } } @@ -308,8 +327,9 @@ static int bcmgenet_adjust_link(void) { rt_uint32_t speed; rt_uint32_t phy_dev_speed = link_speed; - - switch (phy_dev_speed) { + + switch (phy_dev_speed) + { case SPEED_1000: speed = UMAC_SPEED_1000; break; @@ -337,7 +357,7 @@ static int bcmgenet_adjust_link(void) void link_irq(void *param) { - if((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) != 0) + if ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) != 0) { rt_sem_release(&link_ack); } @@ -362,14 +382,15 @@ static int bcmgenet_gmac_eth_start(void) /* Update MAC registers based on PHY property */ ret = bcmgenet_adjust_link(); - if (ret) { + if(ret) + { rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret); return ret; } /* wait tx index clear */ while ((read32(mac_reg_base_addr + TDMA_CONS_INDEX) != 0) && (--count)) - DELAY_MICROS(1); + DELAY_MICROS(1); tx_index = read32(mac_reg_base_addr + TDMA_CONS_INDEX); write32(mac_reg_base_addr + TDMA_PROD_INDEX, tx_index); @@ -388,6 +409,8 @@ static int bcmgenet_gmac_eth_start(void) rx_tx_en |= (CMD_TX_EN | CMD_RX_EN); write32(mac_reg_base_addr + UMAC_CMD, rx_tx_en); + //IRQ + write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE); return 0; } @@ -402,6 +425,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) if(prod_index == index_flag) { cur_recv_cnt = index_flag; + index_flag = 0x7fffffff; //no buff return 0; } @@ -411,7 +435,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) { return 0; } - + desc_base = RX_DESC_BASE + rx_index * DMA_DESC_SIZE; length = read32(desc_base + DMA_DESC_LENGTH_STATUS); length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; @@ -430,6 +454,11 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) write32(mac_reg_base_addr + RDMA_CONS_INDEX, cur_recv_cnt); cur_recv_cnt = cur_recv_cnt + 1; + + if(cur_recv_cnt > 0xffff) + { + cur_recv_cnt = 0; + } prev_recv_cnt = cur_recv_cnt; return length; @@ -438,41 +467,53 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) static int bcmgenet_gmac_eth_send(void *packet, int length) { - void* desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE); + void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE); rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT; rt_uint32_t prod_index, cons; rt_uint32_t tries = 100; - + prod_index = read32(mac_reg_base_addr + TDMA_PROD_INDEX); len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; - write32((desc_base + DMA_DESC_ADDRESS_LO),SEND_DATA_NO_CACHE); - write32((desc_base + DMA_DESC_ADDRESS_HI),0); - write32((desc_base + DMA_DESC_LENGTH_STATUS),len_stat); + write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE); + write32((desc_base + DMA_DESC_ADDRESS_HI), 0); + write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat); + + tx_index = tx_index + 1; + prod_index = prod_index + 1; - if(++tx_index>= TX_DESCS) + if (prod_index == 0xe000) + { + write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0); + prod_index = 0; + } + + if (tx_index == 256) { tx_index = 0; } - prod_index++; + /* Start Transmisson */ - write32(mac_reg_base_addr + TDMA_PROD_INDEX,prod_index); + write32(mac_reg_base_addr + TDMA_PROD_INDEX, prod_index); - do { + do + { cons = read32(mac_reg_base_addr + TDMA_CONS_INDEX); } while ((cons & 0xffff) < prod_index && --tries); + if (!tries) { + rt_kprintf("send err! tries is %d\n", tries); return -1; } return 0; } static void link_task_entry(void *param) -{ +{ struct eth_device *eth_device = (struct eth_device *)param; RT_ASSERT(eth_device != RT_NULL); struct rt_eth_dev *dev = ð_dev; @@ -488,7 +529,7 @@ static void link_task_entry(void *param) //link wait forever rt_sem_take(&link_ack, RT_WAITING_FOREVER); - eth_device_linkchange(ð_dev.parent, RT_TRUE);//link up + eth_device_linkchange(ð_dev.parent, RT_TRUE); //link up rt_timer_stop(&dev->link_timer); //set mac @@ -496,12 +537,12 @@ static void link_task_entry(void *param) bcmgenet_gmac_write_hwaddr(); //check link speed - if((bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 10)) || (bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 11))) + if ((bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 10)) || (bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 11))) { link_speed = 1000; rt_kprintf("Support link mode Speed 1000M\n"); } - else if((bcmgenet_mdio_read(1, 0x05) & (1 << 7)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 8)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 9))) + else if ((bcmgenet_mdio_read(1, 0x05) & (1 << 7)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 8)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 9))) { link_speed = 100; rt_kprintf("Support link mode Speed 100M\n"); @@ -514,6 +555,7 @@ static void link_task_entry(void *param) bcmgenet_gmac_eth_start(); //irq or poll +#ifdef ETH_RX_POLL rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer", eth_rx_irq, NULL, @@ -521,6 +563,10 @@ static void link_task_entry(void *param) RT_TIMER_FLAG_PERIODIC); rt_timer_start(&dev->rx_poll_timer); +#else + rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq"); + rt_hw_interrupt_umask(ETH_IRQ); +#endif link_flag = 1; } @@ -533,7 +579,8 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device) rt_uint8_t major = 0; hw_reg = read32(mac_reg_base_addr + SYS_REV_CTRL); major = (hw_reg >> 24) & 0x0f; - if (major != 6) { + if (major != 6) + { if (major == 5) major = 4; else if (major == 0) @@ -547,7 +594,7 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device) if (ret) { return ret; - } + } /* rbuf clear */ write32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL, 0); @@ -557,9 +604,9 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device) /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ write32(mac_reg_base_addr + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN); - link_thread_tid = rt_thread_create("link",link_task_entry, (void *)device, - LINK_THREAD_STACK_SIZE, - LINK_THREAD_PRIORITY, LINK_THREAD_TIMESLICE); + link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device, + LINK_THREAD_STACK_SIZE, + LINK_THREAD_PRIORITY, LINK_THREAD_TIMESLICE); if (link_thread_tid != RT_NULL) rt_thread_startup(link_thread_tid); @@ -571,10 +618,12 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args) switch (cmd) { case NIOCTL_GADDR: - if (args) rt_memcpy(args, eth_dev.dev_addr, 6); - else return -RT_ERROR; + if (args) + rt_memcpy(args, eth_dev.dev_addr, 6); + else + return -RT_ERROR; break; - default : + default: break; } return RT_EOK; @@ -584,7 +633,7 @@ rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) { rt_uint32_t sendbuf = (rt_uint32_t)eth_send_no_cache; /* lock eth device */ - if(link_flag == 1) + if (link_flag == 1) { rt_sem_take(&sem_lock, RT_WAITING_FOREVER); pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0); @@ -602,11 +651,11 @@ struct pbuf *rt_eth_rx(rt_device_t device) int recv_len = 0; rt_uint32_t addr_point[8]; struct pbuf *pbuf = RT_NULL; - if(link_flag == 1) + if (link_flag == 1) { rt_sem_take(&sem_lock, RT_WAITING_FOREVER); recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]); - if(recv_len > 0) + if (recv_len > 0) { pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); //calc offset diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h index c631be53ba..860674847a 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h @@ -52,6 +52,17 @@ #define MDIO_REG_SHIFT (16) #define MDIO_REG_MASK (0x1f) +#define GENET_INTRL2_OFF (0x0200) +#define GENET_INTRL2_CPU_STAT (GENET_INTRL2_OFF + 0x00) +#define GENET_INTRL2_CPU_CLEAR (GENET_INTRL2_OFF + 0x08) +#define GENET_INTRL2_CPU_STAT_MASK (GENET_INTRL2_OFF + 0x0c) +#define GENET_INTRL2_CPU_SET_MASK (GENET_INTRL2_OFF + 0x10) +#define GENET_INTRL2_CPU_CLEAR_MASK (GENET_INTRL2_OFF + 0x14) +#define GENET_IRQ_MDIO_ERROR BIT(24) +#define GENET_IRQ_MDIO_DONE BIT(23) +#define GENET_IRQ_TXDMA_DONE BIT(16) +#define GENET_IRQ_RXDMA_DONE BIT(13) + #define CMD_TX_EN BIT(0) #define CMD_RX_EN BIT(1) #define UMAC_SPEED_10 (0) diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c index 9d87838ea0..9d4824e310 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c @@ -552,8 +552,8 @@ static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat) // Clear control2 write32(pdat->virt + EMMC_CONTROL2, 0); - // Get the base clock rate - mmc_base_clock = bcm271x_mbox_clock_get_rate(12); + // Get the base clock rate //12 + mmc_base_clock = bcm271x_mbox_clock_get_rate(EMMC_CLK_ID); if(mmc_base_clock == 0) { rt_kprintf("EMMC: assuming clock rate to be 100MHz\n"); diff --git a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h index cae2c74acc..db431bf4d4 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h +++ b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h @@ -165,6 +165,8 @@ extern uint32_t mmc2_base_addr; #define MAC_REG (void *)(0xfd580000) extern void * mac_reg_base_addr; +#define ETH_IRQ (160+29) + #define SEND_DATA_NO_CACHE (0x08200000) extern void * eth_send_no_cache; -- Gitee