A minimal GPU design in Verilog to learn how GPUs work from the ground up

Merg-path based Parallel Sparse Matrix-Matrix Algorithm for Irregular Sparse Matrices

A completely configurable RISC-V Out of Order Core with a base model geared towards maximizing performance

The code for Leveled Packed Memory Array for GPU

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

GL0AM GPU Accelerated Gate Level Logic Simulator