# lowRISC SystemVerilog Programming Style Guides

**Repository Path**: shi-feng-logic/low-risc-style-guides

## Basic Information

- **Project Name**: lowRISC SystemVerilog Programming Style Guides
- **Description**: lowRISC Style Guides
- **Primary Language**: Verilog
- **License**: CC-BY-4.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-06-21
- **Last Updated**: 2025-06-21

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# lowRISC Style Guides

This repository contains style guides curated by lowRISC for use in our
code and documentation.

- [SystemVerilog style guide](VerilogCodingStyle.md)
- [Coding Style Guide for Design Verification](DVCodingStyle.md)

We invite issues and pull requests to add clarity to these guides.

All documents in this repository are licensed under Creative Commons
Attribution 4.0 International
([CC-BY 4.0](https://creativecommons.org/licenses/by/4.0/deed)).