SSRV (Super-scalar RISC-V) - Super-scalar Out-of-Order (OoO) RV32IMC CPU core, 6.4 CoreMark/MHz.
Work Stealing Queue, Job System, Thread Pool, Programming Parallel / Concurrent Applications
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
RIDECORE (RISC-V Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
Tiny, header-only C++20 implementation of the dominator tree algorithm by Lengauer and Tarjan
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A delightful community-driven framework for managing your bash configuration, and an auto-update tool so that makes it easy to keep up with the latest updates from the community.
