# mriscv_vivado

**Repository Path**: simonxing/mriscv_vivado

## Basic Information

- **Project Name**: mriscv_vivado
- **Description**: A 32-bit Microcontroller for NEXYS4-DDR fpga based on mriscv.
- **Primary Language**: Unknown
- **License**: MIT
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2020-01-06
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# mriscv_vivado
The micro controller also was tested under a NEXYS4 FPGA platform. The whole system is composed by two masters (SPI and mriscv core) and 8 slaves. All the peripherals are communicated with the masters through a AXI4-lite bus. The slaves are a block that emulates the processor RAM, a DDR2 driver, a ROM with a built-in SPI protocol, a GPIO with RS232 support, a SPI, a DAC, a 7-segment display and xADC. xADC is an interface to the ADCs available in the FPGA. The file "diagram.pdf" shows the block diagram of the implemented micro controller.