From 04870825b4138d6eb54f077aeac59757d3eedf85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=BA=B7=E5=90=8E=E9=93=B6?= <@kanghou-silver> Date: Thu, 18 Apr 2024 20:21:15 +0800 Subject: [PATCH] add sw8a --- boost.spec | 35 +- ...oost-add-sw.patch => boost_1_66_0-sw.patch | 970 ++++++++++-------- boost_1_66_0-sw8a.patch | 785 ++++++++++++++ 3 files changed, 1321 insertions(+), 469 deletions(-) rename 1010-boost-add-sw.patch => boost_1_66_0-sw.patch (62%) create mode 100644 boost_1_66_0-sw8a.patch diff --git a/boost.spec b/boost.spec index 85830c2..a377cf4 100644 --- a/boost.spec +++ b/boost.spec @@ -1,4 +1,4 @@ -%define anolis_release .0.2 +%define anolis_release .0.3 # Support for documentation installation As the %%doc macro erases the # target directory ($RPM_BUILD_ROOT%%{_docdir}/%%{name}), manually # installed documentation must be saved into a temporary dedicated @@ -8,16 +8,9 @@ %global boost_docdir __tmp_docdir %global boost_examplesdir __tmp_examplesdir -%if 0%{?flatpak} -# For bundling in Flatpak, currently build without mpich and openmpi, -# which aren't needed and cause prefix=/app errors. -%bcond_with mpich -%bcond_with openmpi -%else # All arches have openmpi and mpich %bcond_without mpich %bcond_without openmpi -%endif %ifnarch %{ix86} x86_64 ppc64le aarch64 %bcond_with context @@ -35,7 +28,7 @@ Name: boost Summary: The free peer-reviewed portable C++ source libraries Version: 1.66.0 %global version_enc 1_66_0 -Release: 13%{anolis_release}%{?dist} +Release: 10%{anolis_release}%{?dist} License: Boost and MIT and Python %global toplev_dirname %{name}_%{version_enc} @@ -89,7 +82,6 @@ BuildRequires: m4 BuildRequires: libstdc++-devel BuildRequires: bzip2-devel BuildRequires: zlib-devel -BuildRequires: xz-devel BuildRequires: python3-devel BuildRequires: python3-numpy BuildRequires: libicu-devel @@ -165,8 +157,9 @@ Patch1006: 1006-Name-the-empty_value-template-parameters.patch Patch1007: 1007-Improve-C++11-allocator-support.patch Patch1008: 1008-Use-boost::allocator_rebind-instead-of-A::template-rebind.patch Patch1009: 1009-Implement-allocator-access-utilities.patch +Patch1010: boost_1_66_0-sw.patch +Patch1011: boost_1_66_0-sw8a.patch # End Anolis customized patches -Patch1010: 1010-boost-add-sw.patch %bcond_with tests %bcond_with docs_generated @@ -685,6 +678,7 @@ find ./boost -name '*.hpp' -perm /111 | xargs chmod a-x %patch1008 -p2 %patch1009 -p2 %patch1010 -p1 +%patch1011 -p1 %build PYTHON3_ABIFLAGS=$(/usr/bin/python3-config --abiflags) @@ -1344,10 +1338,13 @@ fi %{_mandir}/man1/bjam.1* %changelog -* Tue Mar 19 2024 wxiat - 1.66.0-13.0.2 -- cherry-pick `add sw patch #ca22c7e4c2f3f6e491647752c2ddda1be280209a`. +* Thu Apr 18 2024 wxiat - 1.66.0-10.0.3 +- add sw8a + +* Thu Apr 18 2024 wxiat - 1.66.0-10.0.2 +- add sw patch -* Wed Jul 05 2023 Liwei Ge - 1.66.0-13.0.1 +* Fri Jan 1 2021 Liwei Ge - 1.66.0-10.0.1 - backport patches to fit with C++20 until upstream chase up: * Replace-std::allocate-with-std::allocator_traits.patch * Replace-std::allocate-deprecated-in-C++17.patch @@ -1359,16 +1356,6 @@ fi * Use-boost::allocator_rebind-instead-of-A::template-rebind.patch * Implement-allocator-access-utilities.patch -* Wed Jun 22 2022 Jonathan Wakely - 1.66.0-13 -- Remove unused libzstd-devel dependency (#2069831) -- Preserve hardening flags when building bjam - -* Tue Jun 21 2022 Jonathan Wakely - 1.66.0-12 -- Build with lzma and zstd support (#2069831) - -* Wed Jan 20 2021 Stephan Bergmann - 1.66.0-11 -- Disable openmpi and mpich for Flatpak-bundled builds (#1895928) - * Tue Aug 04 2020 Jonathan Wakely - 1.66.0-10 - Revert changes for s390x support in Boost.Context diff --git a/1010-boost-add-sw.patch b/boost_1_66_0-sw.patch similarity index 62% rename from 1010-boost-add-sw.patch rename to boost_1_66_0-sw.patch index 4164f55..9e1a4d5 100644 --- a/1010-boost-add-sw.patch +++ b/boost_1_66_0-sw.patch @@ -1,52 +1,6 @@ -From 2784d4c78d5a96edffdc1a5c74bf8d3a45293ce0 Mon Sep 17 00:00:00 2001 -From: wxiat -Date: Fri, 28 Jul 2023 16:47:53 +0800 -Subject: [PATCH] add sw - -Signed-off-by: wxiat ---- - boost/atomic/detail/caps_gcc_sw_64.hpp | 34 + - boost/atomic/detail/ops_gcc_sw_64.hpp | 876 ++++++++++++++++++ - boost/atomic/detail/platform.hpp | 4 + - .../detail/sw_64_rounding_control.hpp | 113 +++ - boost/numeric/interval/hw_rounding.hpp | 2 + - boost/predef/architecture.h | 1 + - boost/predef/architecture/sw_64.h | 51 + - .../systems/si/codata/sw_64_constants.hpp | 66 ++ - boost/wave/wave_config.hpp | 2 +- - boostcpp.jam | 6 +- - libs/atomic/test/lockfree.cpp | 2 +- - libs/config/checks/architecture/Jamroot.jam | 1 + - libs/config/checks/architecture/sw_64.cpp | 15 + - libs/config/test/config_info.cpp | 1 + - libs/context/build/Jamfile.v2 | 24 + - libs/context/build/architecture.jam | 4 + - libs/context/doc/architectures.qbk | 1 + - .../src/asm/jump_sw_64_aapcs_elf_gas.S | 86 ++ - .../src/asm/make_sw_64_aapcs_elf_gas.S | 37 + - .../src/asm/ontop_sw_64_aapcs_elf_gas.S | 86 ++ - libs/log/build/log-architecture.jam | 4 + - tools/build/doc/src/reference.xml | 1 + - tools/build/src/engine/jam.h | 5 + - tools/build/src/tools/builtin.py | 3 + - .../tools/features/architecture-feature.jam | 3 + - tools/build/tutorial.html | 2 +- - 26 files changed, 1426 insertions(+), 4 deletions(-) - create mode 100644 boost/atomic/detail/caps_gcc_sw_64.hpp - create mode 100644 boost/atomic/detail/ops_gcc_sw_64.hpp - create mode 100644 boost/numeric/interval/detail/sw_64_rounding_control.hpp - create mode 100644 boost/predef/architecture/sw_64.h - create mode 100644 boost/units/systems/si/codata/sw_64_constants.hpp - create mode 100644 libs/config/checks/architecture/sw_64.cpp - create mode 100644 libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S - create mode 100644 libs/context/src/asm/make_sw_64_aapcs_elf_gas.S - create mode 100644 libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S - -diff --git a/boost/atomic/detail/caps_gcc_sw_64.hpp b/boost/atomic/detail/caps_gcc_sw_64.hpp -new file mode 100644 -index 00000000..8cb7b949 ---- /dev/null -+++ b/boost/atomic/detail/caps_gcc_sw_64.hpp +diff -uNar boost_1_66_0.org/boost/atomic/detail/caps_gcc_sw_64.hpp boost_1_66_0.new/boost/atomic/detail/caps_gcc_sw_64.hpp +--- boost_1_66_0.org/boost/atomic/detail/caps_gcc_sw_64.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ boost_1_66_0.new/boost/atomic/detail/caps_gcc_sw_64.hpp 2024-04-18 13:53:40.552733880 +0800 @@ -0,0 +1,34 @@ +/* + * Distributed under the Boost Software License, Version 1.0. @@ -82,12 +36,10 @@ index 00000000..8cb7b949 +#define BOOST_ATOMIC_SIGNAL_FENCE 2 + +#endif // BOOST_ATOMIC_DETAIL_CAPS_GCC_SW_64_HPP_INCLUDED_ -diff --git a/boost/atomic/detail/ops_gcc_sw_64.hpp b/boost/atomic/detail/ops_gcc_sw_64.hpp -new file mode 100644 -index 00000000..5f8c5681 ---- /dev/null -+++ b/boost/atomic/detail/ops_gcc_sw_64.hpp -@@ -0,0 +1,876 @@ +diff -uNar boost_1_66_0.org/boost/atomic/detail/ops_gcc_sw_64.hpp boost_1_66_0.new/boost/atomic/detail/ops_gcc_sw_64.hpp +--- boost_1_66_0.org/boost/atomic/detail/ops_gcc_sw_64.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ boost_1_66_0.new/boost/atomic/detail/ops_gcc_sw_64.hpp 2024-04-18 15:10:32.172733880 +0800 +@@ -0,0 +1,1038 @@ +/* + * Distributed under the Boost Software License, Version 1.0. + * (See accompanying file LICENSE_1_0.txt or copy at @@ -204,23 +156,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; ++ storage_type tmp1, tmp2; + fence_before(order); + __asm__ __volatile__ + ( -+ "1:\n" -+ "mov %3, %1\n" -+ "ldl_l %0, %2\n" -+ "stl_c %1, %2\n" -+ "beq %1, 2f\n" -+ -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ "1:\n\t" ++ "ldi %2,%4\n\t" ++ "ldi %3,1\n\t" ++ "mov %5, %1\n\t" ++ "lldw %0, 0(%2)\n\t" ++ "wr_f %3\n\t" ++ "lstw %1, 0(%2)\n\t" ++ "rd_f %1\n\t" ++ "beq %1, 2f\n\t" ++ ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (tmp) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (tmp), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -233,21 +192,27 @@ index 00000000..5f8c5681 + fence_before(success_order); + int success; + storage_type current; ++ storage_type tmp1,tmp2; + __asm__ __volatile__ + ( -+ "1:\n" -+ "ldl_l %2, %4\n" // current = *(&storage) -+ "cmpeq %2, %0, %3\n" // success = current == expected -+ "mov %2, %0\n" // expected = current -+ "beq %3, 2f\n" // if (success == 0) goto end -+ "stl_c %1, %4\n" // storage = desired; desired = store succeeded -+ "mov %1, %3\n" // success = desired -+ "2:\n" -+ : "+&r" (expected), // %0 -+ "+&r" (desired), // %1 ++ "1:\n\t" ++ "ldi %4,%6\n\t" ++ "lldw %2, 0(%4)\n\t" // current = *(&storage) ++ "cmpeq %2, %0, %5\n\t" // success = current == expected ++ "wr_f %5\n\t" // success = current == expected ++ "mov %2, %0\n\t" // expected = current ++ "lstw %1, 0(%4)\n\t" // storage = desired; desired = store succeeded ++ "rd_f %1\n\t" // storage = desired; desired = store succeeded ++ "beq %5, 2f\n\t" // if (success == 0) goto end ++ "mov %1, %3\n\t" // success = desired ++ "2:\n\t" ++ : "+r" (expected), // %0 ++ "+r" (desired), // %1 + "=&r" (current), // %2 -+ "=&r" (success) // %3 -+ : "m" (storage) // %4 ++ "=&r" (success), // %3 ++ "=&r" (tmp1), // %4 ++ "=&r" (tmp2) // %5 ++ : "m" (storage) // %6 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + if (success) @@ -262,30 +227,36 @@ index 00000000..5f8c5681 + { + int success; + storage_type current, tmp; ++ storage_type tmp1,tmp2; + fence_before(success_order); + __asm__ __volatile__ + ( -+ "1:\n" -+ "mov %5, %1\n" // tmp = desired -+ "ldl_l %2, %4\n" // current = *(&storage) -+ "cmpeq %2, %0, %3\n" // success = current == expected -+ "mov %2, %0\n" // expected = current -+ "beq %3, 2f\n" // if (success == 0) goto end -+ "stl_c %1, %4\n" // storage = tmp; tmp = store succeeded -+ "beq %1, 3f\n" // if (tmp == 0) goto retry -+ "mov %1, %3\n" // success = tmp -+ "2:\n" -+ -+ ".subsection 2\n" -+ "3: br 1b\n" -+ ".previous\n" -+ -+ : "+&r" (expected), // %0 ++ "1:\n\t" ++ "ldi %4,%6\n\t" ++ "mov %7, %1\n\t" // tmp = desired ++ "lldw %2, 0(%4)\n\t" // current = *(&storage) ++ "cmpeq %2, %0, %5\n\t" // success = current == expected ++ "wr_f %5\n\t" // success = current == expected ++ "mov %2, %0\n\t" // expected = current ++ "lstw %1, 0(%4)\n\t" // storage = tmp; tmp = store succeeded ++ "rd_f %1\n\t" // storage = tmp; tmp = store succeeded ++ "beq %5, 2f\n\t" // if (success == 0) goto end ++ "beq %1, 3f\n\t" // if (tmp == 0) goto retry ++ "mov %1, %3\n\t" // success = tmp ++ "2:\n\t" ++ ++ ".subsection 2\n\t" ++ "3: br 1b\n\t" ++ ".previous\n\t" ++ ++ : "+r" (expected), // %0 + "=&r" (tmp), // %1 + "=&r" (current), // %2 -+ "=&r" (success) // %3 -+ : "m" (storage), // %4 -+ "r" (desired) // %5 ++ "=&r" (success), // %3 ++ "=&r" (tmp1), // %4 ++ "=&r" (tmp2) // %5 ++ : "m" (storage), // %6 ++ "r" (desired) // %7 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + if (success) @@ -298,23 +269,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1, tmp2; + fence_before(order); + __asm__ __volatile__ + ( -+ "1:\n" -+ "ldl_l %0, %2\n" -+ "addl %0, %3, %1\n" -+ "stl_c %1, %2\n" -+ "beq %1, 2f\n" -+ -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ "1:\n\t" ++ "ldi %2,%4\n\t" ++ "ldi %3,1\n\t" ++ "lldw %0, 0(%2)\n\t" ++ "wr_f %3\n\t" ++ "addw %0, %5, %1\n\t" ++ "lstw %1, 0(%2)\n\t" ++ "rd_f %1\n\t" ++ "beq %1, 2f\n\t" ++ ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -324,23 +302,29 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1, tmp2; + fence_before(order); + __asm__ __volatile__ + ( -+ "1:\n" -+ "ldl_l %0, %2\n" -+ "subl %0, %3, %1\n" -+ "stl_c %1, %2\n" -+ "beq %1, 2f\n" -+ -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ "1:\n\t" ++ "ldi %2,%4\n\t" ++ "ldi %3,1\n\t" ++ "lldw %0, 0(%2)\n\t" ++ "wr_f %3\n\t" ++ "subw %0, %5, %1\n\t" ++ "lstw %1, 0(%2)\n\t" ++ "rd_f %1\n\t" ++ "beq %1, 2f\n\t" ++ ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -350,23 +334,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( -+ "1:\n" -+ "ldl_l %0, %2\n" -+ "and %0, %3, %1\n" -+ "stl_c %1, %2\n" -+ "beq %1, 2f\n" -+ -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ "1:\n\t" ++ "ldi %2,%4\n\t" ++ "ldi %3,1\n\t" ++ "lldw %0, 0(%2)\n\t" ++ "wr_f %3\n\t" ++ "and %0, %5, %1\n\t" ++ "lstw %1, 0(%2)\n\t" ++ "rd_f %1\n\t" ++ "beq %1, 2f\n\t" ++ ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -376,23 +367,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldl_l %0, %2\n" -+ "bis %0, %3, %1\n" -+ "stl_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "bis %0, %5, %1\n" ++ "lstw %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + -+ : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ : "=&r" (original), // %0 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -402,23 +400,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1, tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldl_l %0, %2\n" -+ "xor %0, %3, %1\n" -+ "stl_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "xor %0, %5, %1\n" ++ "lstw %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -447,24 +452,31 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1, tmp2; + fence_before(order); + __asm__ __volatile__ -+ ( ++ ( + "1:\n" -+ "ldl_l %0, %2\n" -+ "addl %0, %3, %1\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "addw %0, %5, %1\n" + "zapnot %1, #1, %1\n" -+ "stl_c %1, %2\n" ++ "lstw %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + -+ : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ : "=&r" (original), // %0 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -474,24 +486,31 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1, tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldl_l %0, %2\n" -+ "subl %0, %3, %1\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "subw %0, %5, %1\n" + "zapnot %1, #1, %1\n" -+ "stl_c %1, %2\n" ++ "lstw %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + -+ : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ : "=&r" (original), // %0 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -509,24 +528,31 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldl_l %0, %2\n" -+ "addl %0, %3, %1\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "addw %0, %5, %1\n" + "sextb %1, %1\n" -+ "stl_c %1, %2\n" ++ "lstw %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -536,24 +562,31 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldl_l %0, %2\n" -+ "subl %0, %3, %1\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "subw %0, %5, %1\n" + "sextb %1, %1\n" -+ "stl_c %1, %2\n" ++ "lstw %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + -+ : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ : "=&r" (original), // %0 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -572,24 +605,31 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldl_l %0, %2\n" -+ "addl %0, %3, %1\n" ++ "ldi %2,%4\n" ++ "ldi %3\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "addw %0, %5, %1\n" + "zapnot %1, #3, %1\n" -+ "stl_c %1, %2\n" ++ "lstw %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -599,24 +639,31 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldl_l %0, %2\n" -+ "subl %0, %3, %1\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "subw %0, %5, %1\n" + "zapnot %1, #3, %1\n" -+ "stl_c %1, %2\n" ++ "lstw %1, %2\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -634,24 +681,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( -+ "1:\n" -+ "ldl_l %0, %2\n" -+ "addl %0, %3, %1\n" -+ "sextw %1, %1\n" -+ "stl_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "addw %0, %5, %1\n" ++ "sexth %1, %1\n" ++ "lstw %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -661,24 +714,31 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldl_l %0, %2\n" -+ "subl %0, %3, %1\n" -+ "sextw %1, %1\n" -+ "stl_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldw %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "subw %0, %5, %1\n" ++ "sexth %1, %1\n" ++ "lstw %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -714,23 +774,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "mov %3, %1\n" -+ "ldq_l %0, %2\n" -+ "stq_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "mov %5, %1\n" ++ "lldl %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "lstl %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (tmp) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (tmp), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -743,21 +810,27 @@ index 00000000..5f8c5681 + fence_before(success_order); + int success; + storage_type current; ++ storage_type tmp1,tmp2; + __asm__ __volatile__ + ( + "1:\n" -+ "ldq_l %2, %4\n" // current = *(&storage) -+ "cmpeq %2, %0, %3\n" // success = current == expected ++ "ldi %4,%6\n" ++ "lldl %2, 0(%4)\n" // current = *(&storage) ++ "cmpeq %2, %0, %5\n" // success = current == expected ++ "wr_f %5 \n" + "mov %2, %0\n" // expected = current -+ "beq %3, 2f\n" // if (success == 0) goto end -+ "stq_c %1, %4\n" // storage = desired; desired = store succeeded ++ "lstl %1, 0(%4)\n" // storage = desired; desired = store succeeded ++ "rd_f %1 \n" ++ "beq %5, 2f\n" // if (success == 0) goto end + "mov %1, %3\n" // success = desired -+ "2:\n" -+ : "+&r" (expected), // %0 -+ "+&r" (desired), // %1 ++ "2:\n\t" ++ : "+r" (expected), // %0 ++ "+r" (desired), // %1 + "=&r" (current), // %2 -+ "=&r" (success) // %3 -+ : "m" (storage) // %4 ++ "=&r" (success), // %3 ++ "=&r" (tmp1), // %4 ++ "=&r" (tmp2) // %5 ++ : "m" (storage) // %6 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + if (success) @@ -772,30 +845,36 @@ index 00000000..5f8c5681 + { + int success; + storage_type current, tmp; ++ storage_type tmp1,tmp2; + fence_before(success_order); + __asm__ __volatile__ + ( + "1:\n" -+ "mov %5, %1\n" // tmp = desired -+ "ldq_l %2, %4\n" // current = *(&storage) -+ "cmpeq %2, %0, %3\n" // success = current == expected ++ "ldi %4,%6\n" ++ "mov %7, %1\n" // tmp = desired ++ "lldl %2, 0(%4)\n" // current = *(&storage) ++ "cmpeq %2, %0, %5\n" // success = current == expected ++ "wr_f %5 \n" + "mov %2, %0\n" // expected = current -+ "beq %3, 2f\n" // if (success == 0) goto end -+ "stq_c %1, %4\n" // storage = tmp; tmp = store succeeded ++ "lstl %1, 0(%4)\n" // storage = tmp; tmp = store succeeded ++ "rd_f %1 \n" ++ "beq %5, 2f\n" // if (success == 0) goto end + "beq %1, 3f\n" // if (tmp == 0) goto retry + "mov %1, %3\n" // success = tmp -+ "2:\n" ++ "2:\n\t" + -+ ".subsection 2\n" -+ "3: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "3: br 1b\n\t" ++ ".previous\n\t" + -+ : "+&r" (expected), // %0 ++ : "+r" (expected), // %0 + "=&r" (tmp), // %1 + "=&r" (current), // %2 -+ "=&r" (success) // %3 -+ : "m" (storage), // %4 -+ "r" (desired) // %5 ++ "=&r" (success), // %3 ++ "=&r" (tmp1), // %4 ++ "=&r" (tmp2) // %5 ++ : "m" (storage), // %6 ++ "r" (desired) // %7 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + if (success) @@ -808,23 +887,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1, tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldq_l %0, %2\n" -+ "addq %0, %3, %1\n" -+ "stq_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldl %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "addl %0, %5, %1\n" ++ "lstl %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -834,23 +920,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldq_l %0, %2\n" -+ "subq %0, %3, %1\n" -+ "stq_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldl %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "subl %0, %5, %1\n" ++ "lstl %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -860,23 +953,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldq_l %0, %2\n" -+ "and %0, %3, %1\n" -+ "stq_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldl %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "and %0, %5, %1\n" ++ "lstl %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -886,23 +986,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldq_l %0, %2\n" -+ "bis %0, %3, %1\n" -+ "stq_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldl %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "bis %0, %5, %1\n" ++ "lstl %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -912,23 +1019,30 @@ index 00000000..5f8c5681 + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; ++ storage_type tmp1,tmp2; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" -+ "ldq_l %0, %2\n" -+ "xor %0, %3, %1\n" -+ "stq_c %1, %2\n" ++ "ldi %2,%4\n" ++ "ldi %3,1\n" ++ "lldl %0, 0(%2)\n" ++ "wr_f %3 \n" ++ "xor %0, %5, %1\n" ++ "lstl %1, 0(%2)\n" ++ "rd_f %1 \n" + "beq %1, 2f\n" + -+ ".subsection 2\n" -+ "2: br 1b\n" -+ ".previous\n" ++ ".subsection 2\n\t" ++ "2: br 1b\n\t" ++ ".previous\n\t" + + : "=&r" (original), // %0 -+ "=&r" (modified) // %1 -+ : "m" (storage), // %2 -+ "r" (v) // %3 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1), // %2 ++ "=&r" (tmp2) // %3 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); @@ -964,10 +1078,9 @@ index 00000000..5f8c5681 +} // namespace boost + +#endif // BOOST_ATOMIC_DETAIL_OPS_GCC_SW_64_HPP_INCLUDED_ -diff --git a/boost/atomic/detail/platform.hpp b/boost/atomic/detail/platform.hpp -index 117dff27..501b8143 100644 ---- a/boost/atomic/detail/platform.hpp -+++ b/boost/atomic/detail/platform.hpp +diff -uNar boost_1_66_0.org/boost/atomic/detail/platform.hpp boost_1_66_0.new/boost/atomic/detail/platform.hpp +--- boost_1_66_0.org/boost/atomic/detail/platform.hpp 2017-12-14 07:56:41.000000000 +0800 ++++ boost_1_66_0.new/boost/atomic/detail/platform.hpp 2024-04-18 13:53:40.562733880 +0800 @@ -68,6 +68,10 @@ #define BOOST_ATOMIC_DETAIL_PLATFORM gcc_sparc @@ -979,11 +1092,9 @@ index 117dff27..501b8143 100644 #elif defined(__GNUC__) && defined(__alpha__) #define BOOST_ATOMIC_DETAIL_PLATFORM gcc_alpha -diff --git a/boost/numeric/interval/detail/sw_64_rounding_control.hpp b/boost/numeric/interval/detail/sw_64_rounding_control.hpp -new file mode 100644 -index 00000000..01b41024 ---- /dev/null -+++ b/boost/numeric/interval/detail/sw_64_rounding_control.hpp +diff -uNar boost_1_66_0.org/boost/numeric/interval/detail/sw_64_rounding_control.hpp boost_1_66_0.new/boost/numeric/interval/detail/sw_64_rounding_control.hpp +--- boost_1_66_0.org/boost/numeric/interval/detail/sw_64_rounding_control.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ boost_1_66_0.new/boost/numeric/interval/detail/sw_64_rounding_control.hpp 2024-04-18 13:53:40.562733880 +0800 @@ -0,0 +1,113 @@ +/* Boost interval/detail/sw_64_rounding_control.hpp file + * @@ -1098,10 +1209,9 @@ index 00000000..01b41024 +#endif + +#endif /* BOOST_NUMERIC_INTERVAL_DETAIL_SW_64_ROUNDING_CONTROL_HPP */ -diff --git a/boost/numeric/interval/hw_rounding.hpp b/boost/numeric/interval/hw_rounding.hpp -index 574b2433..addf0253 100644 ---- a/boost/numeric/interval/hw_rounding.hpp -+++ b/boost/numeric/interval/hw_rounding.hpp +diff -uNar boost_1_66_0.org/boost/numeric/interval/hw_rounding.hpp boost_1_66_0.new/boost/numeric/interval/hw_rounding.hpp +--- boost_1_66_0.org/boost/numeric/interval/hw_rounding.hpp 2017-12-14 07:56:46.000000000 +0800 ++++ boost_1_66_0.new/boost/numeric/interval/hw_rounding.hpp 2024-04-18 13:53:40.562733880 +0800 @@ -27,6 +27,8 @@ # include #elif defined(sparc) || defined(__sparc__) @@ -1111,23 +1221,9 @@ index 574b2433..addf0253 100644 #elif defined(alpha) || defined(__alpha__) # include #elif defined(ia64) || defined(__ia64) || defined(__ia64__) -diff --git a/boost/predef/architecture.h b/boost/predef/architecture.h -index c433d437..16ec8527 100644 ---- a/boost/predef/architecture.h -+++ b/boost/predef/architecture.h -@@ -11,6 +11,7 @@ http://www.boost.org/LICENSE_1_0.txt) - #endif - - #include -+#include - #include - #include - #include -diff --git a/boost/predef/architecture/sw_64.h b/boost/predef/architecture/sw_64.h -new file mode 100644 -index 00000000..9ae5e7b3 ---- /dev/null -+++ b/boost/predef/architecture/sw_64.h +diff -uNar boost_1_66_0.org/boost/predef/architecture/sw_64.h boost_1_66_0.new/boost/predef/architecture/sw_64.h +--- boost_1_66_0.org/boost/predef/architecture/sw_64.h 1970-01-01 08:00:00.000000000 +0800 ++++ boost_1_66_0.new/boost/predef/architecture/sw_64.h 2024-04-18 13:53:40.562733880 +0800 @@ -0,0 +1,51 @@ +/* +Copyright Rene Rivera 2008-2015 @@ -1180,11 +1276,20 @@ index 00000000..9ae5e7b3 + +#include +BOOST_PREDEF_DECLARE_TEST(BOOST_ARCH_SW_64,BOOST_ARCH_SW_64_NAME) -diff --git a/boost/units/systems/si/codata/sw_64_constants.hpp b/boost/units/systems/si/codata/sw_64_constants.hpp -new file mode 100644 -index 00000000..98112313 ---- /dev/null -+++ b/boost/units/systems/si/codata/sw_64_constants.hpp +diff -uNar boost_1_66_0.org/boost/predef/architecture.h boost_1_66_0.new/boost/predef/architecture.h +--- boost_1_66_0.org/boost/predef/architecture.h 2017-12-14 07:56:47.000000000 +0800 ++++ boost_1_66_0.new/boost/predef/architecture.h 2024-04-18 13:53:40.562733880 +0800 +@@ -11,6 +11,7 @@ + #endif + + #include ++#include + #include + #include + #include +diff -uNar boost_1_66_0.org/boost/units/systems/si/codata/sw_64_constants.hpp boost_1_66_0.new/boost/units/systems/si/codata/sw_64_constants.hpp +--- boost_1_66_0.org/boost/units/systems/si/codata/sw_64_constants.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ boost_1_66_0.new/boost/units/systems/si/codata/sw_64_constants.hpp 2024-04-18 13:53:40.562733880 +0800 @@ -0,0 +1,66 @@ +// Boost.Units - A C++ library for zero-overhead dimensional analysis and +// unit/quantity manipulation and conversion @@ -1252,10 +1357,9 @@ index 00000000..98112313 +} // namespace boost + +#endif // BOOST_UNITS_CODATA_SW_64_CONSTANTS_HPP -diff --git a/boost/wave/wave_config.hpp b/boost/wave/wave_config.hpp -index 6e4b15d1..28ce2fff 100644 ---- a/boost/wave/wave_config.hpp -+++ b/boost/wave/wave_config.hpp +diff -uNar boost_1_66_0.org/boost/wave/wave_config.hpp boost_1_66_0.new/boost/wave/wave_config.hpp +--- boost_1_66_0.org/boost/wave/wave_config.hpp 2017-12-14 07:56:49.000000000 +0800 ++++ boost_1_66_0.new/boost/wave/wave_config.hpp 2024-04-18 13:53:40.562733880 +0800 @@ -205,7 +205,7 @@ // CW up to 8.3 chokes as well *sigh* // Tru64/CXX has linker problems when using flex_string @@ -1265,11 +1369,10 @@ index 6e4b15d1..28ce2fff 100644 defined(BOOST_WAVE_STRINGTYPE_USE_STDSTRING) #define BOOST_WAVE_STRINGTYPE std::string -diff --git a/boostcpp.jam b/boostcpp.jam -index 85a4cb32..d4fc832f 100644 ---- a/boostcpp.jam -+++ b/boostcpp.jam -@@ -678,7 +678,7 @@ rule address-model ( ) +diff -uNar boost_1_66_0.org/boostcpp.jam boost_1_66_0.new/boostcpp.jam +--- boost_1_66_0.org/boostcpp.jam 2017-12-14 07:56:35.000000000 +0800 ++++ boost_1_66_0.new/boostcpp.jam 2024-04-18 13:53:40.562733880 +0800 +@@ -678,7 +678,7 @@ return @boostcpp.deduce-address-model ; } @@ -1278,7 +1381,7 @@ index 85a4cb32..d4fc832f 100644 feature.feature deduced-architecture : $(deducable-architectures) : propagated optional composite hidden ; for a in $(deducable-architectures) { -@@ -705,6 +705,10 @@ rule deduce-architecture ( properties * ) +@@ -705,6 +705,10 @@ { result = sparc ; } @@ -1289,11 +1392,10 @@ index 85a4cb32..d4fc832f 100644 else if [ configure.builds /boost/architecture//x86 : $(filtered) : x86 ] { result = x86 ; -diff --git a/libs/atomic/test/lockfree.cpp b/libs/atomic/test/lockfree.cpp -index 33c62e2a..a022def6 100644 ---- a/libs/atomic/test/lockfree.cpp -+++ b/libs/atomic/test/lockfree.cpp -@@ -88,7 +88,7 @@ verify_lock_free(const char * type_name, int lock_free_macro_val, int lock_free_ +diff -uNar boost_1_66_0.org/libs/atomic/test/lockfree.cpp boost_1_66_0.new/libs/atomic/test/lockfree.cpp +--- boost_1_66_0.org/libs/atomic/test/lockfree.cpp 2017-12-14 07:56:41.000000000 +0800 ++++ boost_1_66_0.new/libs/atomic/test/lockfree.cpp 2024-04-18 13:53:40.562733880 +0800 +@@ -88,7 +88,7 @@ #define EXPECT_POINTER_LOCK_FREE 2 #define EXPECT_BOOL_LOCK_FREE 2 @@ -1302,11 +1404,10 @@ index 33c62e2a..a022def6 100644 #define EXPECT_CHAR_LOCK_FREE 2 #define EXPECT_CHAR16_T_LOCK_FREE 2 -diff --git a/libs/config/checks/architecture/Jamroot.jam b/libs/config/checks/architecture/Jamroot.jam -index ca653b75..0e1df50d 100644 ---- a/libs/config/checks/architecture/Jamroot.jam -+++ b/libs/config/checks/architecture/Jamroot.jam -@@ -16,6 +16,7 @@ obj 32 : 32.cpp ; +diff -uNar boost_1_66_0.org/libs/config/checks/architecture/Jamroot.jam boost_1_66_0.new/libs/config/checks/architecture/Jamroot.jam +--- boost_1_66_0.org/libs/config/checks/architecture/Jamroot.jam 2017-12-14 07:56:42.000000000 +0800 ++++ boost_1_66_0.new/libs/config/checks/architecture/Jamroot.jam 2024-04-18 13:53:40.562733880 +0800 +@@ -16,6 +16,7 @@ obj 64 : 64.cpp ; obj arm : arm.cpp ; @@ -1314,11 +1415,9 @@ index ca653b75..0e1df50d 100644 obj combined : combined.cpp ; obj mips1 : mips1.cpp ; obj power : power.cpp ; -diff --git a/libs/config/checks/architecture/sw_64.cpp b/libs/config/checks/architecture/sw_64.cpp -new file mode 100644 -index 00000000..8200abde ---- /dev/null -+++ b/libs/config/checks/architecture/sw_64.cpp +diff -uNar boost_1_66_0.org/libs/config/checks/architecture/sw_64.cpp boost_1_66_0.new/libs/config/checks/architecture/sw_64.cpp +--- boost_1_66_0.org/libs/config/checks/architecture/sw_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ boost_1_66_0.new/libs/config/checks/architecture/sw_64.cpp 2024-04-18 13:53:40.562733880 +0800 @@ -0,0 +1,15 @@ +// sw_64.cpp +// @@ -1335,11 +1434,10 @@ index 00000000..8200abde +#error "Not SW_64" +#endif + -diff --git a/libs/config/test/config_info.cpp b/libs/config/test/config_info.cpp -index 89f6b07b..32a19e03 100644 ---- a/libs/config/test/config_info.cpp -+++ b/libs/config/test/config_info.cpp -@@ -146,6 +146,7 @@ void print_compiler_macros() +diff -uNar boost_1_66_0.org/libs/config/test/config_info.cpp boost_1_66_0.new/libs/config/test/config_info.cpp +--- boost_1_66_0.org/libs/config/test/config_info.cpp 2017-12-14 07:56:42.000000000 +0800 ++++ boost_1_66_0.new/libs/config/test/config_info.cpp 2024-04-18 13:53:40.562733880 +0800 +@@ -146,6 +146,7 @@ PRINT_MACRO(_CPPRTTI); PRINT_MACRO(_DLL); PRINT_MACRO(_M_ALPHA); @@ -1347,11 +1445,24 @@ index 89f6b07b..32a19e03 100644 PRINT_MACRO(_M_MPPC); PRINT_MACRO(_M_MRX000); PRINT_MACRO(_M_PPC); -diff --git a/libs/context/build/Jamfile.v2 b/libs/context/build/Jamfile.v2 -index 719ca91e..abca0193 100644 ---- a/libs/context/build/Jamfile.v2 -+++ b/libs/context/build/Jamfile.v2 -@@ -234,6 +234,30 @@ alias asm_sources +diff -uNar boost_1_66_0.org/libs/context/build/architecture.jam boost_1_66_0.new/libs/context/build/architecture.jam +--- boost_1_66_0.org/libs/context/build/architecture.jam 2017-12-14 07:56:42.000000000 +0800 ++++ boost_1_66_0.new/libs/context/build/architecture.jam 2024-04-18 13:53:40.562733880 +0800 +@@ -59,6 +59,10 @@ + { + return mips1 ; + } ++ else if [ configure.builds /boost/architecture//sw_64 : $(properties) : sw_64 ] ++ { ++ return sw_64 ; ++ } + else if [ configure.builds /boost/architecture//power : $(properties) : power ] + { + return power ; +diff -uNar boost_1_66_0.org/libs/context/build/Jamfile.v2 boost_1_66_0.new/libs/context/build/Jamfile.v2 +--- boost_1_66_0.org/libs/context/build/Jamfile.v2 2017-12-14 07:56:42.000000000 +0800 ++++ boost_1_66_0.new/libs/context/build/Jamfile.v2 2024-04-18 13:53:40.562733880 +0800 +@@ -234,6 +234,30 @@ msvc ; @@ -1382,26 +1493,10 @@ index 719ca91e..abca0193 100644 # ARM64 # ARM64/AAPCS/ELF alias asm_sources -diff --git a/libs/context/build/architecture.jam b/libs/context/build/architecture.jam -index 81dcb497..b80a7eab 100644 ---- a/libs/context/build/architecture.jam -+++ b/libs/context/build/architecture.jam -@@ -59,6 +59,10 @@ rule deduce-architecture ( properties * ) - { - return mips1 ; - } -+ else if [ configure.builds /boost/architecture//sw_64 : $(properties) : sw_64 ] -+ { -+ return sw_64 ; -+ } - else if [ configure.builds /boost/architecture//power : $(properties) : power ] - { - return power ; -diff --git a/libs/context/doc/architectures.qbk b/libs/context/doc/architectures.qbk -index 893c5b39..1e9555a1 100644 ---- a/libs/context/doc/architectures.qbk -+++ b/libs/context/doc/architectures.qbk -@@ -20,6 +20,7 @@ architectures: +diff -uNar boost_1_66_0.org/libs/context/doc/architectures.qbk boost_1_66_0.new/libs/context/doc/architectures.qbk +--- boost_1_66_0.org/libs/context/doc/architectures.qbk 2017-12-14 07:56:42.000000000 +0800 ++++ boost_1_66_0.new/libs/context/doc/architectures.qbk 2024-04-18 13:53:40.562733880 +0800 +@@ -20,6 +20,7 @@ [[ppc64] [SYSV|ELF,XCOFF] [-] [SYSV|MACH-O] [-]] [[sparc] [-] [-] [-] [-]] [[x86_64] [SYSV,X32|ELF] [MS|PE] [SYSV|MACH-O] [-]] @@ -1409,11 +1504,9 @@ index 893c5b39..1e9555a1 100644 ] [note If the architecture is not supported but the platform provides -diff --git a/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S b/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S -new file mode 100644 -index 00000000..913b4d8d ---- /dev/null -+++ b/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S +diff -uNar boost_1_66_0.org/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S boost_1_66_0.new/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S +--- boost_1_66_0.org/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S 1970-01-01 08:00:00.000000000 +0800 ++++ boost_1_66_0.new/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S 2024-04-18 13:53:40.562733880 +0800 @@ -0,0 +1,86 @@ +.text +.align 2 @@ -1501,11 +1594,9 @@ index 00000000..913b4d8d +.size jump_fcontext,.-jump_fcontext +# Mark that we don't need executable stack. +.section .note.GNU-stack,"",%progbits -diff --git a/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S b/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S -new file mode 100644 -index 00000000..7f7d6917 ---- /dev/null -+++ b/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S +diff -uNar boost_1_66_0.org/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S boost_1_66_0.new/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S +--- boost_1_66_0.org/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S 1970-01-01 08:00:00.000000000 +0800 ++++ boost_1_66_0.new/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S 2024-04-18 13:53:40.562733880 +0800 @@ -0,0 +1,37 @@ +.text +.align 2 @@ -1544,11 +1635,9 @@ index 00000000..7f7d6917 +.size make_fcontext,.-make_fcontext +# Mark that we don't need executable stack. +.section .note.GNU-stack,"",%progbits -diff --git a/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S b/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S -new file mode 100644 -index 00000000..1e647646 ---- /dev/null -+++ b/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S +diff -uNar boost_1_66_0.org/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S boost_1_66_0.new/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S +--- boost_1_66_0.org/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S 1970-01-01 08:00:00.000000000 +0800 ++++ boost_1_66_0.new/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S 2024-04-18 13:53:40.562733880 +0800 @@ -0,0 +1,86 @@ +.text +.align 2 @@ -1636,11 +1725,10 @@ index 00000000..1e647646 +.size ontop_fcontext,.-ontop_fcontext +# Mark that we don't need executable stack. +.section .note.GNU-stack,"",%progbits -diff --git a/libs/log/build/log-architecture.jam b/libs/log/build/log-architecture.jam -index 785dda0f..a63b4816 100644 ---- a/libs/log/build/log-architecture.jam -+++ b/libs/log/build/log-architecture.jam -@@ -69,6 +69,10 @@ rule deduce-architecture ( properties * ) +diff -uNar boost_1_66_0.org/libs/log/build/log-architecture.jam boost_1_66_0.new/libs/log/build/log-architecture.jam +--- boost_1_66_0.org/libs/log/build/log-architecture.jam 2017-12-14 07:56:44.000000000 +0800 ++++ boost_1_66_0.new/libs/log/build/log-architecture.jam 2024-04-18 13:53:40.562733880 +0800 +@@ -69,6 +69,10 @@ { return mips1 ; } @@ -1651,11 +1739,10 @@ index 785dda0f..a63b4816 100644 else if [ configure.builds /boost/architecture//power : $(properties) : power ] { return power ; -diff --git a/tools/build/doc/src/reference.xml b/tools/build/doc/src/reference.xml -index 24652f15..74d6eba0 100644 ---- a/tools/build/doc/src/reference.xml -+++ b/tools/build/doc/src/reference.xml -@@ -728,6 +728,7 @@ path-constant DATA : data/a.txt ; +diff -uNar boost_1_66_0.org/tools/build/doc/src/reference.xml boost_1_66_0.new/tools/build/doc/src/reference.xml +--- boost_1_66_0.org/tools/build/doc/src/reference.xml 2017-12-14 07:56:49.000000000 +0800 ++++ boost_1_66_0.new/tools/build/doc/src/reference.xml 2024-04-18 13:53:40.572733880 +0800 +@@ -728,6 +728,7 @@ Allowed values: x86, @@ -1663,10 +1750,9 @@ index 24652f15..74d6eba0 100644 ia64, sparc, power, -diff --git a/tools/build/src/engine/jam.h b/tools/build/src/engine/jam.h -index a6abf410..5703a6b7 100644 ---- a/tools/build/src/engine/jam.h -+++ b/tools/build/src/engine/jam.h +diff -uNar boost_1_66_0.org/tools/build/src/engine/jam.h boost_1_66_0.new/tools/build/src/engine/jam.h +--- boost_1_66_0.org/tools/build/src/engine/jam.h 2017-12-14 07:56:50.000000000 +0800 ++++ boost_1_66_0.new/tools/build/src/engine/jam.h 2024-04-18 13:53:40.572733880 +0800 @@ -379,6 +379,11 @@ #define OSPLAT "OSPLAT=PPC" #endif @@ -1679,11 +1765,10 @@ index a6abf410..5703a6b7 100644 #if defined( _ALPHA_ ) || \ defined( __alpha__ ) #define OSPLAT "OSPLAT=AXP" -diff --git a/tools/build/src/tools/builtin.py b/tools/build/src/tools/builtin.py -index ee6474b7..dd5c797b 100644 ---- a/tools/build/src/tools/builtin.py -+++ b/tools/build/src/tools/builtin.py -@@ -247,6 +247,9 @@ def register_globals (): +diff -uNar boost_1_66_0.org/tools/build/src/tools/builtin.py boost_1_66_0.new/tools/build/src/tools/builtin.py +--- boost_1_66_0.org/tools/build/src/tools/builtin.py 2017-12-14 07:56:50.000000000 +0800 ++++ boost_1_66_0.new/tools/build/src/tools/builtin.py 2024-04-18 13:53:40.572733880 +0800 +@@ -247,6 +247,9 @@ # x86 and x86-64 'x86', @@ -1693,11 +1778,10 @@ index ee6474b7..dd5c797b 100644 # ia64 'ia64', -diff --git a/tools/build/src/tools/features/architecture-feature.jam b/tools/build/src/tools/features/architecture-feature.jam -index b8f7fbcb..20532181 100644 ---- a/tools/build/src/tools/features/architecture-feature.jam -+++ b/tools/build/src/tools/features/architecture-feature.jam -@@ -12,6 +12,9 @@ feature.feature architecture +diff -uNar boost_1_66_0.org/tools/build/src/tools/features/architecture-feature.jam boost_1_66_0.new/tools/build/src/tools/features/architecture-feature.jam +--- boost_1_66_0.org/tools/build/src/tools/features/architecture-feature.jam 2017-12-14 07:56:50.000000000 +0800 ++++ boost_1_66_0.new/tools/build/src/tools/features/architecture-feature.jam 2024-04-18 13:53:40.572733880 +0800 +@@ -12,6 +12,9 @@ # x86 and x86-64 x86 @@ -1707,11 +1791,10 @@ index b8f7fbcb..20532181 100644 # ia64 ia64 -diff --git a/tools/build/tutorial.html b/tools/build/tutorial.html -index f50586e4..84e76f46 100644 ---- a/tools/build/tutorial.html -+++ b/tools/build/tutorial.html -@@ -1254,7 +1254,7 @@ exe hello : hello.cpp : <library>/boost//thread ; +diff -uNar boost_1_66_0.org/tools/build/tutorial.html boost_1_66_0.new/tools/build/tutorial.html +--- boost_1_66_0.org/tools/build/tutorial.html 2017-12-14 07:56:50.000000000 +0800 ++++ boost_1_66_0.new/tools/build/tutorial.html 2024-04-18 13:53:40.572733880 +0800 +@@ -1254,7 +1254,7 @@ <architecture> @@ -1720,6 +1803,3 @@ index f50586e4..84e76f46 100644 mips32r2, mips64, parisc, arm, combined, combined-x86-power Set processor family to generate code for. --- -2.31.1 - diff --git a/boost_1_66_0-sw8a.patch b/boost_1_66_0-sw8a.patch new file mode 100644 index 0000000..303e878 --- /dev/null +++ b/boost_1_66_0-sw8a.patch @@ -0,0 +1,785 @@ +diff -uNar boost_1_66_0.org/boost/atomic/detail/ops_gcc_sw_64.hpp boost_1_66_0.new/boost/atomic/detail/ops_gcc_sw_64.hpp +--- boost_1_66_0.org/boost/atomic/detail/ops_gcc_sw_64.hpp 2024-04-18 20:04:06.118977106 +0800 ++++ boost_1_66_0.new/boost/atomic/detail/ops_gcc_sw_64.hpp 2024-04-18 20:11:07.335077135 +0800 +@@ -114,18 +114,15 @@ + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" +- "mov %5, %1\n\t" ++ "ldi %2,%3\n\t" ++ "mov %4, %1\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -133,11 +130,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (tmp), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -156,13 +152,11 @@ + "1:\n\t" + "ldi %4,%6\n\t" + "lldw %2, 0(%4)\n\t" // current = *(&storage) +- "cmpeq %2, %0, %5\n\t" // success = current == expected +- "wr_f %5\n\t" // success = current == expected +- "mov %2, %0\n\t" // expected = current ++ "cmpeq %2, %0, %5\n\t" // success = current == expected ++ "mov %2, %0\n\t" // expected = current + "lstw %1, 0(%4)\n\t" // storage = desired; desired = store succeeded +- "rd_f %1\n\t" // storage = desired; desired = store succeeded +- "beq %5, 2f\n\t" // if (success == 0) goto end +- "mov %1, %3\n\t" // success = desired ++ "beq %5, 2f\n\t" // if (success == 0) goto end ++ "mov %1, %3\n\t" // success = desired + "2:\n\t" + : "+r" (expected), // %0 + "+r" (desired), // %1 +@@ -194,10 +188,8 @@ + "mov %7, %1\n\t" // tmp = desired + "lldw %2, 0(%4)\n\t" // current = *(&storage) + "cmpeq %2, %0, %5\n\t" // success = current == expected +- "wr_f %5\n\t" // success = current == expected + "mov %2, %0\n\t" // expected = current + "lstw %1, 0(%4)\n\t" // storage = tmp; tmp = store succeeded +- "rd_f %1\n\t" // storage = tmp; tmp = store succeeded + "beq %5, 2f\n\t" // if (success == 0) goto end + "beq %1, 3f\n\t" // if (tmp == 0) goto retry + "mov %1, %3\n\t" // success = tmp +@@ -227,30 +219,26 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "addw %0, %5, %1\n\t" ++ "addw %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" + "2: br 1b\n\t" + ".previous\n\t" + +- : "=&r" (original), // %0 ++ : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -260,18 +248,15 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "subw %0, %5, %1\n\t" ++ "subw %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -279,10 +264,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -292,18 +277,15 @@ + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "and %0, %5, %1\n\t" ++ "and %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -311,11 +293,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -325,18 +306,15 @@ + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "bis %0, %5, %1\n" ++ "bis %0, %4, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -345,10 +323,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -358,18 +335,15 @@ + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "xor %0, %5, %1\n" ++ "xor %0, %4, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -378,10 +352,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -410,19 +383,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ +- ( ++ ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "zapnot %1, #1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -431,10 +401,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -444,19 +413,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "zapnot %1, #1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -465,10 +431,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -486,19 +451,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "sextb %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -507,10 +469,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -520,19 +481,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "sextb %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -541,10 +499,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -563,19 +520,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "zapnot %1, #3, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -584,8 +538,7 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 ++ "=&r" (tmp1) // %2 + : "m" (storage), // %4 + "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC +@@ -597,19 +550,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "zapnot %1, #3, %1\n" + "lstw %1, %2\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -618,10 +568,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -639,18 +588,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "sexth %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -659,10 +605,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -672,19 +617,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %3, %1\n" + "sexth %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -693,10 +635,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -732,18 +673,15 @@ + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" +- "mov %5, %1\n" ++ "ldi %2,%3\n" ++ "mov %4, %1\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -751,11 +689,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (tmp), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -775,10 +712,8 @@ + "ldi %4,%6\n" + "lldl %2, 0(%4)\n" // current = *(&storage) + "cmpeq %2, %0, %5\n" // success = current == expected +- "wr_f %5 \n" + "mov %2, %0\n" // expected = current + "lstl %1, 0(%4)\n" // storage = desired; desired = store succeeded +- "rd_f %1 \n" + "beq %5, 2f\n" // if (success == 0) goto end + "mov %1, %3\n" // success = desired + "2:\n\t" +@@ -812,10 +747,8 @@ + "mov %7, %1\n" // tmp = desired + "lldl %2, 0(%4)\n" // current = *(&storage) + "cmpeq %2, %0, %5\n" // success = current == expected +- "wr_f %5 \n" + "mov %2, %0\n" // expected = current + "lstl %1, 0(%4)\n" // storage = tmp; tmp = store succeeded +- "rd_f %1 \n" + "beq %5, 2f\n" // if (success == 0) goto end + "beq %1, 3f\n" // if (tmp == 0) goto retry + "mov %1, %3\n" // success = tmp +@@ -845,18 +778,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "addl %0, %5, %1\n" ++ "addl %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -865,10 +795,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -878,18 +807,15 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "subl %0, %5, %1\n" ++ "subl %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -898,10 +824,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -911,18 +836,15 @@ + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "and %0, %5, %1\n" ++ "and %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -931,10 +853,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -944,18 +865,15 @@ + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "bis %0, %5, %1\n" ++ "bis %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -964,10 +882,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -977,18 +894,15 @@ + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" + "ldi %2,%4\n" +- "ldi %3,1\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" + "xor %0, %5, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -997,10 +911,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); -- Gitee