diff --git a/boost.spec b/boost.spec index 9846098dbb0adf15716d9f32a7ebea572668df96..8838b8796b4134e4f139c431050899c9e9413b06 100644 --- a/boost.spec +++ b/boost.spec @@ -1,4 +1,4 @@ -%define anolis_release .0.2 +%define anolis_release .0.3 # Support for documentation installation As the %%doc macro erases the # target directory ($RPM_BUILD_ROOT%%{_docdir}/%%{name}), manually # installed documentation must be saved into a temporary dedicated @@ -166,6 +166,7 @@ Patch1007: 1007-Improve-C++11-allocator-support.patch Patch1008: 1008-Use-boost::allocator_rebind-instead-of-A::template-rebind.patch Patch1009: 1009-Implement-allocator-access-utilities.patch Patch1010: boost_1_66_0-sw.patch +Patch1011: boost_1_66_0-sw8a.patch # End Anolis customized patches %bcond_with tests @@ -685,6 +686,7 @@ find ./boost -name '*.hpp' -perm /111 | xargs chmod a-x %patch1008 -p2 %patch1009 -p2 %patch1010 -p1 +%patch1011 -p1 %build PYTHON3_ABIFLAGS=$(/usr/bin/python3-config --abiflags) @@ -1344,6 +1346,9 @@ fi %{_mandir}/man1/bjam.1* %changelog +* Thu Apr 22 2024 wxiat - 1.66.0-13.0.3 +- add sw8a patch + * Thu Apr 18 2024 wxiat - 1.66.0-13.0.2 - add sw patch diff --git a/boost_1_66_0-sw8a.patch b/boost_1_66_0-sw8a.patch new file mode 100644 index 0000000000000000000000000000000000000000..303e8784bc8d823378ce963c0202174f2a66b0f6 --- /dev/null +++ b/boost_1_66_0-sw8a.patch @@ -0,0 +1,785 @@ +diff -uNar boost_1_66_0.org/boost/atomic/detail/ops_gcc_sw_64.hpp boost_1_66_0.new/boost/atomic/detail/ops_gcc_sw_64.hpp +--- boost_1_66_0.org/boost/atomic/detail/ops_gcc_sw_64.hpp 2024-04-18 20:04:06.118977106 +0800 ++++ boost_1_66_0.new/boost/atomic/detail/ops_gcc_sw_64.hpp 2024-04-18 20:11:07.335077135 +0800 +@@ -114,18 +114,15 @@ + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" +- "mov %5, %1\n\t" ++ "ldi %2,%3\n\t" ++ "mov %4, %1\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -133,11 +130,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (tmp), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -156,13 +152,11 @@ + "1:\n\t" + "ldi %4,%6\n\t" + "lldw %2, 0(%4)\n\t" // current = *(&storage) +- "cmpeq %2, %0, %5\n\t" // success = current == expected +- "wr_f %5\n\t" // success = current == expected +- "mov %2, %0\n\t" // expected = current ++ "cmpeq %2, %0, %5\n\t" // success = current == expected ++ "mov %2, %0\n\t" // expected = current + "lstw %1, 0(%4)\n\t" // storage = desired; desired = store succeeded +- "rd_f %1\n\t" // storage = desired; desired = store succeeded +- "beq %5, 2f\n\t" // if (success == 0) goto end +- "mov %1, %3\n\t" // success = desired ++ "beq %5, 2f\n\t" // if (success == 0) goto end ++ "mov %1, %3\n\t" // success = desired + "2:\n\t" + : "+r" (expected), // %0 + "+r" (desired), // %1 +@@ -194,10 +188,8 @@ + "mov %7, %1\n\t" // tmp = desired + "lldw %2, 0(%4)\n\t" // current = *(&storage) + "cmpeq %2, %0, %5\n\t" // success = current == expected +- "wr_f %5\n\t" // success = current == expected + "mov %2, %0\n\t" // expected = current + "lstw %1, 0(%4)\n\t" // storage = tmp; tmp = store succeeded +- "rd_f %1\n\t" // storage = tmp; tmp = store succeeded + "beq %5, 2f\n\t" // if (success == 0) goto end + "beq %1, 3f\n\t" // if (tmp == 0) goto retry + "mov %1, %3\n\t" // success = tmp +@@ -227,30 +219,26 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "addw %0, %5, %1\n\t" ++ "addw %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" + "2: br 1b\n\t" + ".previous\n\t" + +- : "=&r" (original), // %0 ++ : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %4 ++ "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -260,18 +248,15 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "subw %0, %5, %1\n\t" ++ "subw %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -279,10 +264,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -292,18 +277,15 @@ + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "and %0, %5, %1\n\t" ++ "and %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -311,11 +293,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -325,18 +306,15 @@ + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "bis %0, %5, %1\n" ++ "bis %0, %4, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -345,10 +323,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -358,18 +335,15 @@ + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "xor %0, %5, %1\n" ++ "xor %0, %4, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -378,10 +352,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -410,19 +383,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ +- ( ++ ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "zapnot %1, #1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -431,10 +401,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -444,19 +413,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "zapnot %1, #1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -465,10 +431,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -486,19 +451,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "sextb %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -507,10 +469,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -520,19 +481,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "sextb %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -541,10 +499,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -563,19 +520,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "zapnot %1, #3, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -584,8 +538,7 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 ++ "=&r" (tmp1) // %2 + : "m" (storage), // %4 + "r" (v) // %5 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC +@@ -597,19 +550,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "zapnot %1, #3, %1\n" + "lstw %1, %2\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -618,10 +568,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -639,18 +588,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "sexth %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -659,10 +605,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -672,19 +617,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %3, %1\n" + "sexth %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -693,10 +635,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -732,18 +673,15 @@ + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" +- "mov %5, %1\n" ++ "ldi %2,%3\n" ++ "mov %4, %1\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -751,11 +689,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (tmp), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -775,10 +712,8 @@ + "ldi %4,%6\n" + "lldl %2, 0(%4)\n" // current = *(&storage) + "cmpeq %2, %0, %5\n" // success = current == expected +- "wr_f %5 \n" + "mov %2, %0\n" // expected = current + "lstl %1, 0(%4)\n" // storage = desired; desired = store succeeded +- "rd_f %1 \n" + "beq %5, 2f\n" // if (success == 0) goto end + "mov %1, %3\n" // success = desired + "2:\n\t" +@@ -812,10 +747,8 @@ + "mov %7, %1\n" // tmp = desired + "lldl %2, 0(%4)\n" // current = *(&storage) + "cmpeq %2, %0, %5\n" // success = current == expected +- "wr_f %5 \n" + "mov %2, %0\n" // expected = current + "lstl %1, 0(%4)\n" // storage = tmp; tmp = store succeeded +- "rd_f %1 \n" + "beq %5, 2f\n" // if (success == 0) goto end + "beq %1, 3f\n" // if (tmp == 0) goto retry + "mov %1, %3\n" // success = tmp +@@ -845,18 +778,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "addl %0, %5, %1\n" ++ "addl %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -865,10 +795,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -878,18 +807,15 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "subl %0, %5, %1\n" ++ "subl %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -898,10 +824,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -911,18 +836,15 @@ + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "and %0, %5, %1\n" ++ "and %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -931,10 +853,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -944,18 +865,15 @@ + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "bis %0, %5, %1\n" ++ "bis %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -964,10 +882,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -977,18 +894,15 @@ + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" + "ldi %2,%4\n" +- "ldi %3,1\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" + "xor %0, %5, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -997,10 +911,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order);